| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the RISCV target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | const unsigned MAX_SUBTARGET_PREDICATES = 91; |
| 11 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 12 | #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 | |
| 14 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 | mutable MatcherState State; |
| 16 | typedef ComplexRendererFns(RISCVInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 | typedef void(RISCVInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 19 | static RISCVInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 | static RISCVInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 | const uint8_t *getMatchTable() const override; |
| 25 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 26 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 27 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 28 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 29 | |
| 30 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 31 | , State(1), |
| 32 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 33 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_IMPL |
| 36 | // LLT Objects. |
| 37 | enum { |
| 38 | GILLT_p0s32, |
| 39 | GILLT_p0s64, |
| 40 | GILLT_s16, |
| 41 | GILLT_s32, |
| 42 | GILLT_s64, |
| 43 | GILLT_nxv1s1, |
| 44 | GILLT_nxv1s8, |
| 45 | GILLT_nxv1s16, |
| 46 | GILLT_nxv1s32, |
| 47 | GILLT_nxv1s64, |
| 48 | GILLT_nxv2s1, |
| 49 | GILLT_nxv2s8, |
| 50 | GILLT_nxv2s16, |
| 51 | GILLT_nxv2s32, |
| 52 | GILLT_nxv2s64, |
| 53 | GILLT_nxv4s1, |
| 54 | GILLT_nxv4s8, |
| 55 | GILLT_nxv4s16, |
| 56 | GILLT_nxv4s32, |
| 57 | GILLT_nxv4s64, |
| 58 | GILLT_nxv8s1, |
| 59 | GILLT_nxv8s8, |
| 60 | GILLT_nxv8s16, |
| 61 | GILLT_nxv8s32, |
| 62 | GILLT_nxv8s64, |
| 63 | GILLT_nxv16s1, |
| 64 | GILLT_nxv16s8, |
| 65 | GILLT_nxv16s16, |
| 66 | GILLT_nxv16s32, |
| 67 | GILLT_nxv32s1, |
| 68 | GILLT_nxv32s8, |
| 69 | GILLT_nxv32s16, |
| 70 | GILLT_nxv64s1, |
| 71 | GILLT_nxv64s8, |
| 72 | }; |
| 73 | const static size_t NumTypeObjects = 34; |
| 74 | const static LLT TypeObjects[] = { |
| 75 | LLT::pointer(0, 32), |
| 76 | LLT::pointer(0, 64), |
| 77 | LLT::scalar(16), |
| 78 | LLT::scalar(32), |
| 79 | LLT::scalar(64), |
| 80 | LLT::vector(ElementCount::getScalable(1), 1), |
| 81 | LLT::vector(ElementCount::getScalable(1), 8), |
| 82 | LLT::vector(ElementCount::getScalable(1), 16), |
| 83 | LLT::vector(ElementCount::getScalable(1), 32), |
| 84 | LLT::vector(ElementCount::getScalable(1), 64), |
| 85 | LLT::vector(ElementCount::getScalable(2), 1), |
| 86 | LLT::vector(ElementCount::getScalable(2), 8), |
| 87 | LLT::vector(ElementCount::getScalable(2), 16), |
| 88 | LLT::vector(ElementCount::getScalable(2), 32), |
| 89 | LLT::vector(ElementCount::getScalable(2), 64), |
| 90 | LLT::vector(ElementCount::getScalable(4), 1), |
| 91 | LLT::vector(ElementCount::getScalable(4), 8), |
| 92 | LLT::vector(ElementCount::getScalable(4), 16), |
| 93 | LLT::vector(ElementCount::getScalable(4), 32), |
| 94 | LLT::vector(ElementCount::getScalable(4), 64), |
| 95 | LLT::vector(ElementCount::getScalable(8), 1), |
| 96 | LLT::vector(ElementCount::getScalable(8), 8), |
| 97 | LLT::vector(ElementCount::getScalable(8), 16), |
| 98 | LLT::vector(ElementCount::getScalable(8), 32), |
| 99 | LLT::vector(ElementCount::getScalable(8), 64), |
| 100 | LLT::vector(ElementCount::getScalable(16), 1), |
| 101 | LLT::vector(ElementCount::getScalable(16), 8), |
| 102 | LLT::vector(ElementCount::getScalable(16), 16), |
| 103 | LLT::vector(ElementCount::getScalable(16), 32), |
| 104 | LLT::vector(ElementCount::getScalable(32), 1), |
| 105 | LLT::vector(ElementCount::getScalable(32), 8), |
| 106 | LLT::vector(ElementCount::getScalable(32), 16), |
| 107 | LLT::vector(ElementCount::getScalable(64), 1), |
| 108 | LLT::vector(ElementCount::getScalable(64), 8), |
| 109 | }; |
| 110 | |
| 111 | // Bits for subtarget features that participate in instruction matching. |
| 112 | enum SubtargetFeatureBits : uint8_t { |
| 113 | Feature_HasStdExtZicbopBit = 67, |
| 114 | Feature_HasStdExtZicondBit = 68, |
| 115 | Feature_HasStdExtZimopBit = 66, |
| 116 | Feature_HasStdExtZicfilpBit = 2, |
| 117 | Feature_NoStdExtZicfilpBit = 1, |
| 118 | Feature_HasStdExtZmmulBit = 19, |
| 119 | Feature_HasStdExtMBit = 20, |
| 120 | Feature_HasStdExtABit = 22, |
| 121 | Feature_HasStdExtZtsoBit = 24, |
| 122 | Feature_NotHasStdExtZtsoBit = 23, |
| 123 | Feature_HasStdExtZabhaBit = 27, |
| 124 | Feature_HasStdExtZacasBit = 26, |
| 125 | Feature_NoStdExtZacasBit = 25, |
| 126 | Feature_HasStdExtFBit = 5, |
| 127 | Feature_HasStdExtDBit = 7, |
| 128 | Feature_HasStdExtZfhminBit = 28, |
| 129 | Feature_HasStdExtZfhBit = 9, |
| 130 | Feature_NoStdExtZfhBit = 30, |
| 131 | Feature_HasStdExtZfbfminBit = 32, |
| 132 | Feature_HasStdExtZfaBit = 33, |
| 133 | Feature_HasStdExtZfinxBit = 6, |
| 134 | Feature_HasStdExtZdinxBit = 8, |
| 135 | Feature_HasStdExtZhinxminBit = 29, |
| 136 | Feature_HasStdExtZhinxBit = 10, |
| 137 | Feature_NoStdExtZhinxBit = 31, |
| 138 | Feature_HasStdExtCBit = 15, |
| 139 | Feature_HasStdExtCOrZcaBit = 17, |
| 140 | Feature_HasStdExtZbaBit = 39, |
| 141 | Feature_NotHasStdExtZbaBit = 18, |
| 142 | Feature_HasStdExtZbbBit = 36, |
| 143 | Feature_NoStdExtZbbBit = 38, |
| 144 | Feature_HasStdExtZbcBit = 41, |
| 145 | Feature_HasStdExtZbsBit = 35, |
| 146 | Feature_HasStdExtZbkbBit = 37, |
| 147 | Feature_HasStdExtZbkxBit = 42, |
| 148 | Feature_HasStdExtZbbOrZbkbBit = 34, |
| 149 | Feature_HasStdExtZbcOrZbkcBit = 40, |
| 150 | Feature_HasStdExtZkndBit = 43, |
| 151 | Feature_HasStdExtZkneBit = 45, |
| 152 | Feature_HasStdExtZkndOrZkneBit = 44, |
| 153 | Feature_HasStdExtZknhBit = 46, |
| 154 | Feature_HasStdExtZksedBit = 47, |
| 155 | Feature_HasStdExtZkshBit = 48, |
| 156 | Feature_HasStdExtZvfbfwmaBit = 55, |
| 157 | Feature_HasStdExtZvkbBit = 58, |
| 158 | Feature_HasStdExtZvbbBit = 57, |
| 159 | Feature_HasStdExtZvbcBit = 62, |
| 160 | Feature_HasStdExtZvkgBit = 59, |
| 161 | Feature_HasStdExtZvknedBit = 60, |
| 162 | Feature_HasStdExtZvknhaBit = 63, |
| 163 | Feature_HasStdExtZvknhbBit = 64, |
| 164 | Feature_HasStdExtZvksedBit = 65, |
| 165 | Feature_HasStdExtZvkshBit = 61, |
| 166 | Feature_HasVInstructionsBit = 11, |
| 167 | Feature_HasVInstructionsI64Bit = 51, |
| 168 | Feature_HasVInstructionsAnyFBit = 50, |
| 169 | Feature_HasVInstructionsF16MinimalBit = 56, |
| 170 | Feature_HasVInstructionsBF16Bit = 54, |
| 171 | Feature_HasVInstructionsF16Bit = 49, |
| 172 | Feature_HasVInstructionsF64Bit = 53, |
| 173 | Feature_HasVInstructionsFullMultiplyBit = 52, |
| 174 | Feature_HasVendorXVentanaCondOpsBit = 69, |
| 175 | Feature_HasVendorXTHeadBaBit = 70, |
| 176 | Feature_HasVendorXTHeadBbBit = 71, |
| 177 | Feature_HasVendorXTHeadBsBit = 72, |
| 178 | Feature_HasVendorXTHeadCondMovBit = 73, |
| 179 | Feature_HasVendorXTHeadFMemIdxBit = 78, |
| 180 | Feature_HasVendorXTHeadMacBit = 74, |
| 181 | Feature_HasVendorXTHeadMemIdxBit = 77, |
| 182 | Feature_HasVendorXTHeadMemPairBit = 76, |
| 183 | Feature_HasVendorXTHeadVdotBit = 75, |
| 184 | Feature_HasVendorXSfvcpBit = 79, |
| 185 | Feature_HasVendorXSfvqmaccdodBit = 80, |
| 186 | Feature_HasVendorXSfvqmaccqoqBit = 81, |
| 187 | Feature_HasVendorXSfvfwmaccqqqBit = 82, |
| 188 | Feature_HasVendorXSfvfnrclipxfqfBit = 83, |
| 189 | Feature_HasVendorXCVbitmanipBit = 85, |
| 190 | Feature_HasVendorXCVmacBit = 88, |
| 191 | Feature_HasVendorXCVmemBit = 84, |
| 192 | Feature_HasVendorXCValuBit = 86, |
| 193 | Feature_HasVendorXCVbiBit = 87, |
| 194 | Feature_IsRV64Bit = 4, |
| 195 | Feature_IsRV32Bit = 3, |
| 196 | Feature_HasShortForwardBranchOptBit = 12, |
| 197 | Feature_NoShortForwardBranchOptBit = 14, |
| 198 | Feature_HasConditionalMoveFusionBit = 13, |
| 199 | Feature_NoConditionalMoveFusionBit = 0, |
| 200 | Feature_HasAtomicLdStBit = 21, |
| 201 | Feature_OptForMinSizeBit = 16, |
| 202 | Feature_HwMode1Bit = 90, |
| 203 | Feature_HwMode0Bit = 89, |
| 204 | }; |
| 205 | |
| 206 | PredicateBitset RISCVInstructionSelector:: |
| 207 | computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const { |
| 208 | PredicateBitset Features{}; |
| 209 | if (Subtarget->hasStdExtZicbop()) |
| 210 | Features.set(Feature_HasStdExtZicbopBit); |
| 211 | if (Subtarget->hasStdExtZicond()) |
| 212 | Features.set(Feature_HasStdExtZicondBit); |
| 213 | if (Subtarget->hasStdExtZimop()) |
| 214 | Features.set(Feature_HasStdExtZimopBit); |
| 215 | if (Subtarget->hasStdExtZicfilp()) |
| 216 | Features.set(Feature_HasStdExtZicfilpBit); |
| 217 | if (!Subtarget->hasStdExtZicfilp()) |
| 218 | Features.set(Feature_NoStdExtZicfilpBit); |
| 219 | if (Subtarget->hasStdExtZmmul()) |
| 220 | Features.set(Feature_HasStdExtZmmulBit); |
| 221 | if (Subtarget->hasStdExtM()) |
| 222 | Features.set(Feature_HasStdExtMBit); |
| 223 | if (Subtarget->hasStdExtA()) |
| 224 | Features.set(Feature_HasStdExtABit); |
| 225 | if (Subtarget->hasStdExtZtso()) |
| 226 | Features.set(Feature_HasStdExtZtsoBit); |
| 227 | if (!Subtarget->hasStdExtZtso()) |
| 228 | Features.set(Feature_NotHasStdExtZtsoBit); |
| 229 | if (Subtarget->hasStdExtZabha()) |
| 230 | Features.set(Feature_HasStdExtZabhaBit); |
| 231 | if (Subtarget->hasStdExtZacas()) |
| 232 | Features.set(Feature_HasStdExtZacasBit); |
| 233 | if (!Subtarget->hasStdExtZacas()) |
| 234 | Features.set(Feature_NoStdExtZacasBit); |
| 235 | if (Subtarget->hasStdExtF()) |
| 236 | Features.set(Feature_HasStdExtFBit); |
| 237 | if (Subtarget->hasStdExtD()) |
| 238 | Features.set(Feature_HasStdExtDBit); |
| 239 | if (Subtarget->hasStdExtZfhmin()) |
| 240 | Features.set(Feature_HasStdExtZfhminBit); |
| 241 | if (Subtarget->hasStdExtZfh()) |
| 242 | Features.set(Feature_HasStdExtZfhBit); |
| 243 | if (!Subtarget->hasStdExtZfh()) |
| 244 | Features.set(Feature_NoStdExtZfhBit); |
| 245 | if (Subtarget->hasStdExtZfbfmin()) |
| 246 | Features.set(Feature_HasStdExtZfbfminBit); |
| 247 | if (Subtarget->hasStdExtZfa()) |
| 248 | Features.set(Feature_HasStdExtZfaBit); |
| 249 | if (Subtarget->hasStdExtZfinx()) |
| 250 | Features.set(Feature_HasStdExtZfinxBit); |
| 251 | if (Subtarget->hasStdExtZdinx()) |
| 252 | Features.set(Feature_HasStdExtZdinxBit); |
| 253 | if (Subtarget->hasStdExtZhinxmin()) |
| 254 | Features.set(Feature_HasStdExtZhinxminBit); |
| 255 | if (Subtarget->hasStdExtZhinx()) |
| 256 | Features.set(Feature_HasStdExtZhinxBit); |
| 257 | if (!Subtarget->hasStdExtZhinx()) |
| 258 | Features.set(Feature_NoStdExtZhinxBit); |
| 259 | if (Subtarget->hasStdExtC()) |
| 260 | Features.set(Feature_HasStdExtCBit); |
| 261 | if (Subtarget->hasStdExtCOrZca()) |
| 262 | Features.set(Feature_HasStdExtCOrZcaBit); |
| 263 | if (Subtarget->hasStdExtZba()) |
| 264 | Features.set(Feature_HasStdExtZbaBit); |
| 265 | if (!Subtarget->hasStdExtZba()) |
| 266 | Features.set(Feature_NotHasStdExtZbaBit); |
| 267 | if (Subtarget->hasStdExtZbb()) |
| 268 | Features.set(Feature_HasStdExtZbbBit); |
| 269 | if (!Subtarget->hasStdExtZbb()) |
| 270 | Features.set(Feature_NoStdExtZbbBit); |
| 271 | if (Subtarget->hasStdExtZbc()) |
| 272 | Features.set(Feature_HasStdExtZbcBit); |
| 273 | if (Subtarget->hasStdExtZbs()) |
| 274 | Features.set(Feature_HasStdExtZbsBit); |
| 275 | if (Subtarget->hasStdExtZbkb()) |
| 276 | Features.set(Feature_HasStdExtZbkbBit); |
| 277 | if (Subtarget->hasStdExtZbkx()) |
| 278 | Features.set(Feature_HasStdExtZbkxBit); |
| 279 | if (Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()) |
| 280 | Features.set(Feature_HasStdExtZbbOrZbkbBit); |
| 281 | if (Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()) |
| 282 | Features.set(Feature_HasStdExtZbcOrZbkcBit); |
| 283 | if (Subtarget->hasStdExtZknd()) |
| 284 | Features.set(Feature_HasStdExtZkndBit); |
| 285 | if (Subtarget->hasStdExtZkne()) |
| 286 | Features.set(Feature_HasStdExtZkneBit); |
| 287 | if (Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()) |
| 288 | Features.set(Feature_HasStdExtZkndOrZkneBit); |
| 289 | if (Subtarget->hasStdExtZknh()) |
| 290 | Features.set(Feature_HasStdExtZknhBit); |
| 291 | if (Subtarget->hasStdExtZksed()) |
| 292 | Features.set(Feature_HasStdExtZksedBit); |
| 293 | if (Subtarget->hasStdExtZksh()) |
| 294 | Features.set(Feature_HasStdExtZkshBit); |
| 295 | if (Subtarget->hasStdExtZvfbfwma()) |
| 296 | Features.set(Feature_HasStdExtZvfbfwmaBit); |
| 297 | if (Subtarget->hasStdExtZvkb()) |
| 298 | Features.set(Feature_HasStdExtZvkbBit); |
| 299 | if (Subtarget->hasStdExtZvbb()) |
| 300 | Features.set(Feature_HasStdExtZvbbBit); |
| 301 | if (Subtarget->hasStdExtZvbc()) |
| 302 | Features.set(Feature_HasStdExtZvbcBit); |
| 303 | if (Subtarget->hasStdExtZvkg()) |
| 304 | Features.set(Feature_HasStdExtZvkgBit); |
| 305 | if (Subtarget->hasStdExtZvkned()) |
| 306 | Features.set(Feature_HasStdExtZvknedBit); |
| 307 | if (Subtarget->hasStdExtZvknha()) |
| 308 | Features.set(Feature_HasStdExtZvknhaBit); |
| 309 | if (Subtarget->hasStdExtZvknhb()) |
| 310 | Features.set(Feature_HasStdExtZvknhbBit); |
| 311 | if (Subtarget->hasStdExtZvksed()) |
| 312 | Features.set(Feature_HasStdExtZvksedBit); |
| 313 | if (Subtarget->hasStdExtZvksh()) |
| 314 | Features.set(Feature_HasStdExtZvkshBit); |
| 315 | if (Subtarget->hasVInstructions()) |
| 316 | Features.set(Feature_HasVInstructionsBit); |
| 317 | if (Subtarget->hasVInstructionsI64()) |
| 318 | Features.set(Feature_HasVInstructionsI64Bit); |
| 319 | if (Subtarget->hasVInstructionsAnyF()) |
| 320 | Features.set(Feature_HasVInstructionsAnyFBit); |
| 321 | if (Subtarget->hasVInstructionsF16Minimal()) |
| 322 | Features.set(Feature_HasVInstructionsF16MinimalBit); |
| 323 | if (Subtarget->hasVInstructionsBF16()) |
| 324 | Features.set(Feature_HasVInstructionsBF16Bit); |
| 325 | if (Subtarget->hasVInstructionsF16()) |
| 326 | Features.set(Feature_HasVInstructionsF16Bit); |
| 327 | if (Subtarget->hasVInstructionsF64()) |
| 328 | Features.set(Feature_HasVInstructionsF64Bit); |
| 329 | if (Subtarget->hasVInstructionsFullMultiply()) |
| 330 | Features.set(Feature_HasVInstructionsFullMultiplyBit); |
| 331 | if (Subtarget->hasVendorXVentanaCondOps()) |
| 332 | Features.set(Feature_HasVendorXVentanaCondOpsBit); |
| 333 | if (Subtarget->hasVendorXTHeadBa()) |
| 334 | Features.set(Feature_HasVendorXTHeadBaBit); |
| 335 | if (Subtarget->hasVendorXTHeadBb()) |
| 336 | Features.set(Feature_HasVendorXTHeadBbBit); |
| 337 | if (Subtarget->hasVendorXTHeadBs()) |
| 338 | Features.set(Feature_HasVendorXTHeadBsBit); |
| 339 | if (Subtarget->hasVendorXTHeadCondMov()) |
| 340 | Features.set(Feature_HasVendorXTHeadCondMovBit); |
| 341 | if (Subtarget->hasVendorXTHeadFMemIdx()) |
| 342 | Features.set(Feature_HasVendorXTHeadFMemIdxBit); |
| 343 | if (Subtarget->hasVendorXTHeadMac()) |
| 344 | Features.set(Feature_HasVendorXTHeadMacBit); |
| 345 | if (Subtarget->hasVendorXTHeadMemIdx()) |
| 346 | Features.set(Feature_HasVendorXTHeadMemIdxBit); |
| 347 | if (Subtarget->hasVendorXTHeadMemPair()) |
| 348 | Features.set(Feature_HasVendorXTHeadMemPairBit); |
| 349 | if (Subtarget->hasVendorXTHeadVdot()) |
| 350 | Features.set(Feature_HasVendorXTHeadVdotBit); |
| 351 | if (Subtarget->hasVendorXSfvcp()) |
| 352 | Features.set(Feature_HasVendorXSfvcpBit); |
| 353 | if (Subtarget->hasVendorXSfvqmaccdod()) |
| 354 | Features.set(Feature_HasVendorXSfvqmaccdodBit); |
| 355 | if (Subtarget->hasVendorXSfvqmaccqoq()) |
| 356 | Features.set(Feature_HasVendorXSfvqmaccqoqBit); |
| 357 | if (Subtarget->hasVendorXSfvfwmaccqqq()) |
| 358 | Features.set(Feature_HasVendorXSfvfwmaccqqqBit); |
| 359 | if (Subtarget->hasVendorXSfvfnrclipxfqf()) |
| 360 | Features.set(Feature_HasVendorXSfvfnrclipxfqfBit); |
| 361 | if (Subtarget->hasVendorXCVbitmanip()) |
| 362 | Features.set(Feature_HasVendorXCVbitmanipBit); |
| 363 | if (Subtarget->hasVendorXCVmac()) |
| 364 | Features.set(Feature_HasVendorXCVmacBit); |
| 365 | if (Subtarget->hasVendorXCVmem()) |
| 366 | Features.set(Feature_HasVendorXCVmemBit); |
| 367 | if (Subtarget->hasVendorXCValu()) |
| 368 | Features.set(Feature_HasVendorXCValuBit); |
| 369 | if (Subtarget->hasVendorXCVbi()) |
| 370 | Features.set(Feature_HasVendorXCVbiBit); |
| 371 | if (Subtarget->is64Bit()) |
| 372 | Features.set(Feature_IsRV64Bit); |
| 373 | if (!Subtarget->is64Bit()) |
| 374 | Features.set(Feature_IsRV32Bit); |
| 375 | if (Subtarget->hasShortForwardBranchOpt()) |
| 376 | Features.set(Feature_HasShortForwardBranchOptBit); |
| 377 | if (!Subtarget->hasShortForwardBranchOpt()) |
| 378 | Features.set(Feature_NoShortForwardBranchOptBit); |
| 379 | if (Subtarget->hasConditionalMoveFusion()) |
| 380 | Features.set(Feature_HasConditionalMoveFusionBit); |
| 381 | if (!Subtarget->hasConditionalMoveFusion()) |
| 382 | Features.set(Feature_NoConditionalMoveFusionBit); |
| 383 | if (Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()) |
| 384 | Features.set(Feature_HasAtomicLdStBit); |
| 385 | if (MF ? MF->getFunction().hasMinSize() : false) |
| 386 | Features.set(Feature_OptForMinSizeBit); |
| 387 | if (!((Subtarget->is64Bit()))) |
| 388 | Features.set(Feature_HwMode1Bit); |
| 389 | if ((Subtarget->is64Bit())) |
| 390 | Features.set(Feature_HwMode0Bit); |
| 391 | return Features; |
| 392 | } |
| 393 | |
| 394 | void RISCVInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 395 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const RISCVSubtarget *)&MF.getSubtarget(), &MF); |
| 396 | } |
| 397 | PredicateBitset RISCVInstructionSelector:: |
| 398 | computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, const MachineFunction *MF) const { |
| 399 | PredicateBitset Features{}; |
| 400 | return Features; |
| 401 | } |
| 402 | |
| 403 | // Feature bitsets. |
| 404 | enum { |
| 405 | GIFBS_Invalid, |
| 406 | GIFBS_HwMode0, |
| 407 | GIFBS_HwMode1, |
| 408 | GIFBS_HasAtomicLdSt_HwMode0, |
| 409 | GIFBS_HasAtomicLdSt_HwMode1, |
| 410 | GIFBS_HasShortForwardBranchOpt_HwMode0, |
| 411 | GIFBS_HasShortForwardBranchOpt_HwMode1, |
| 412 | GIFBS_HasStdExtA_HwMode1, |
| 413 | GIFBS_HasStdExtD, |
| 414 | GIFBS_HasStdExtD_HwMode0, |
| 415 | GIFBS_HasStdExtD_HwMode1, |
| 416 | GIFBS_HasStdExtF, |
| 417 | GIFBS_HasStdExtF_HwMode0, |
| 418 | GIFBS_HasStdExtF_HwMode1, |
| 419 | GIFBS_HasStdExtM_HwMode0, |
| 420 | GIFBS_HasStdExtM_HwMode1, |
| 421 | GIFBS_HasStdExtZba_HwMode0, |
| 422 | GIFBS_HasStdExtZba_HwMode1, |
| 423 | GIFBS_HasStdExtZbb_HwMode0, |
| 424 | GIFBS_HasStdExtZbb_HwMode1, |
| 425 | GIFBS_HasStdExtZbbOrZbkb_HwMode0, |
| 426 | GIFBS_HasStdExtZbbOrZbkb_HwMode1, |
| 427 | GIFBS_HasStdExtZbkx_HwMode0, |
| 428 | GIFBS_HasStdExtZbkx_HwMode1, |
| 429 | GIFBS_HasStdExtZbs_HwMode0, |
| 430 | GIFBS_HasStdExtZbs_HwMode1, |
| 431 | GIFBS_HasStdExtZfa, |
| 432 | GIFBS_HasStdExtZfa_HwMode0, |
| 433 | GIFBS_HasStdExtZfa_HwMode1, |
| 434 | GIFBS_HasStdExtZfbfmin_HwMode0, |
| 435 | GIFBS_HasStdExtZfbfmin_HwMode1, |
| 436 | GIFBS_HasStdExtZfh, |
| 437 | GIFBS_HasStdExtZfh_HwMode0, |
| 438 | GIFBS_HasStdExtZfh_HwMode1, |
| 439 | GIFBS_HasStdExtZfhmin_HwMode0, |
| 440 | GIFBS_HasStdExtZfhmin_HwMode1, |
| 441 | GIFBS_HasStdExtZfinx, |
| 442 | GIFBS_HasStdExtZfinx_HwMode0, |
| 443 | GIFBS_HasStdExtZfinx_HwMode1, |
| 444 | GIFBS_HasStdExtZhinx, |
| 445 | GIFBS_HasStdExtZhinx_HwMode0, |
| 446 | GIFBS_HasStdExtZhinx_HwMode1, |
| 447 | GIFBS_HasStdExtZhinxmin_HwMode0, |
| 448 | GIFBS_HasStdExtZhinxmin_HwMode1, |
| 449 | GIFBS_HasStdExtZmmul_HwMode0, |
| 450 | GIFBS_HasStdExtZmmul_HwMode1, |
| 451 | GIFBS_HasVInstructions_HwMode0, |
| 452 | GIFBS_HasVInstructions_HwMode1, |
| 453 | GIFBS_HasVInstructionsAnyF_HwMode0, |
| 454 | GIFBS_HasVInstructionsAnyF_HwMode1, |
| 455 | GIFBS_HasVInstructionsBF16_HwMode0, |
| 456 | GIFBS_HasVInstructionsBF16_HwMode1, |
| 457 | GIFBS_HasVInstructionsF16_HwMode0, |
| 458 | GIFBS_HasVInstructionsF16_HwMode1, |
| 459 | GIFBS_HasVInstructionsF16Minimal_HwMode0, |
| 460 | GIFBS_HasVInstructionsF16Minimal_HwMode1, |
| 461 | GIFBS_HasVInstructionsF64_HwMode0, |
| 462 | GIFBS_HasVInstructionsF64_HwMode1, |
| 463 | GIFBS_HasVInstructionsFullMultiply_HwMode0, |
| 464 | GIFBS_HasVInstructionsFullMultiply_HwMode1, |
| 465 | GIFBS_HasVInstructionsI64_HwMode0, |
| 466 | GIFBS_HasVInstructionsI64_HwMode1, |
| 467 | GIFBS_HasVendorXCVmac_HwMode0, |
| 468 | GIFBS_HasVendorXCVmac_HwMode1, |
| 469 | GIFBS_HasVendorXTHeadBa_HwMode0, |
| 470 | GIFBS_HasVendorXTHeadBa_HwMode1, |
| 471 | GIFBS_HasVendorXTHeadBb_HwMode0, |
| 472 | GIFBS_HasVendorXTHeadBb_HwMode1, |
| 473 | GIFBS_HasVendorXTHeadBs_HwMode0, |
| 474 | GIFBS_HasVendorXTHeadBs_HwMode1, |
| 475 | GIFBS_HasVendorXTHeadCondMov_HwMode0, |
| 476 | GIFBS_HasVendorXTHeadCondMov_HwMode1, |
| 477 | GIFBS_HasVendorXTHeadMac_HwMode0, |
| 478 | GIFBS_HasVendorXTHeadMac_HwMode1, |
| 479 | GIFBS_IsRV32_HwMode0, |
| 480 | GIFBS_IsRV32_HwMode1, |
| 481 | GIFBS_IsRV64_HwMode0, |
| 482 | GIFBS_IsRV64_HwMode1, |
| 483 | GIFBS_HasAtomicLdSt_IsRV64_HwMode0, |
| 484 | GIFBS_HasStdExtA_HasStdExtZtso_HwMode0, |
| 485 | GIFBS_HasStdExtA_HasStdExtZtso_HwMode1, |
| 486 | GIFBS_HasStdExtA_IsRV64_HwMode1, |
| 487 | GIFBS_HasStdExtA_NoStdExtZacas_HwMode1, |
| 488 | GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0, |
| 489 | GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1, |
| 490 | GIFBS_HasStdExtD_HasStdExtZfa, |
| 491 | GIFBS_HasStdExtD_HasStdExtZfa_HwMode0, |
| 492 | GIFBS_HasStdExtD_HasStdExtZfa_HwMode1, |
| 493 | GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode0, |
| 494 | GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode1, |
| 495 | GIFBS_HasStdExtD_IsRV64_HwMode0, |
| 496 | GIFBS_HasStdExtF_IsRV64_HwMode0, |
| 497 | GIFBS_HasStdExtM_IsRV64_HwMode0, |
| 498 | GIFBS_HasStdExtM_IsRV64_HwMode1, |
| 499 | GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0, |
| 500 | GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1, |
| 501 | GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0, |
| 502 | GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1, |
| 503 | GIFBS_HasStdExtZba_IsRV64_HwMode0, |
| 504 | GIFBS_HasStdExtZba_IsRV64_HwMode1, |
| 505 | GIFBS_HasStdExtZbb_IsRV32_HwMode0, |
| 506 | GIFBS_HasStdExtZbb_IsRV32_HwMode1, |
| 507 | GIFBS_HasStdExtZbb_IsRV64_HwMode0, |
| 508 | GIFBS_HasStdExtZbb_IsRV64_HwMode1, |
| 509 | GIFBS_HasStdExtZbbOrZbkb_IsRV32_HwMode0, |
| 510 | GIFBS_HasStdExtZbbOrZbkb_IsRV32_HwMode1, |
| 511 | GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0, |
| 512 | GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1, |
| 513 | GIFBS_HasStdExtZbs_IsRV64_HwMode0, |
| 514 | GIFBS_HasStdExtZbs_IsRV64_HwMode1, |
| 515 | GIFBS_HasStdExtZdinx_IsRV32, |
| 516 | GIFBS_HasStdExtZdinx_IsRV32_HwMode0, |
| 517 | GIFBS_HasStdExtZdinx_IsRV32_HwMode1, |
| 518 | GIFBS_HasStdExtZdinx_IsRV64_HwMode0, |
| 519 | GIFBS_HasStdExtZfa_HasStdExtZfh, |
| 520 | GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0, |
| 521 | GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1, |
| 522 | GIFBS_HasStdExtZfbfmin_IsRV64_HwMode0, |
| 523 | GIFBS_HasStdExtZfh_IsRV64_HwMode0, |
| 524 | GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0, |
| 525 | GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1, |
| 526 | GIFBS_HasStdExtZfinx_IsRV64_HwMode0, |
| 527 | GIFBS_HasStdExtZhinx_IsRV64_HwMode0, |
| 528 | GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0, |
| 529 | GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1, |
| 530 | GIFBS_HasStdExtZknd_IsRV32_HwMode1, |
| 531 | GIFBS_HasStdExtZknd_IsRV64_HwMode0, |
| 532 | GIFBS_HasStdExtZkndOrZkne_IsRV64_HwMode0, |
| 533 | GIFBS_HasStdExtZkne_IsRV32_HwMode1, |
| 534 | GIFBS_HasStdExtZkne_IsRV64_HwMode0, |
| 535 | GIFBS_HasStdExtZknh_IsRV32_HwMode1, |
| 536 | GIFBS_HasStdExtZknh_IsRV64_HwMode0, |
| 537 | GIFBS_HasStdExtZmmul_IsRV64_HwMode0, |
| 538 | GIFBS_HasStdExtZmmul_IsRV64_HwMode1, |
| 539 | GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0, |
| 540 | GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1, |
| 541 | GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0, |
| 542 | GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1, |
| 543 | GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0, |
| 544 | GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1, |
| 545 | GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode0, |
| 546 | GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode1, |
| 547 | GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0, |
| 548 | GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1, |
| 549 | GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0, |
| 550 | GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1, |
| 551 | GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0, |
| 552 | GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1, |
| 553 | GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0, |
| 554 | GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1, |
| 555 | GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode0, |
| 556 | GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode1, |
| 557 | GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0, |
| 558 | GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1, |
| 559 | GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0, |
| 560 | GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1, |
| 561 | GIFBS_HasVendorXCValu_IsRV32_HwMode0, |
| 562 | GIFBS_HasVendorXCValu_IsRV32_HwMode1, |
| 563 | GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0, |
| 564 | GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1, |
| 565 | GIFBS_HasVendorXTHeadBb_IsRV64_HwMode0, |
| 566 | GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode0, |
| 567 | GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode1, |
| 568 | GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0, |
| 569 | GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1, |
| 570 | GIFBS_IsRV64_NotHasStdExtZba_HwMode0, |
| 571 | GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0, |
| 572 | GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1, |
| 573 | GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0, |
| 574 | GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1, |
| 575 | GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0, |
| 576 | GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0, |
| 577 | GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0, |
| 578 | GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1, |
| 579 | GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0, |
| 580 | GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1, |
| 581 | GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0, |
| 582 | GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0, |
| 583 | GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode0, |
| 584 | GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode1, |
| 585 | GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode0, |
| 586 | GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode1, |
| 587 | GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode0, |
| 588 | GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode1, |
| 589 | GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV64_HwMode0, |
| 590 | GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0, |
| 591 | GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0, |
| 592 | GIFBS_HasStdExtZmmul_IsRV64_NotHasStdExtZba_HwMode0, |
| 593 | }; |
| 594 | constexpr static PredicateBitset FeatureBitsets[] { |
| 595 | {}, // GIFBS_Invalid |
| 596 | {Feature_HwMode0Bit, }, |
| 597 | {Feature_HwMode1Bit, }, |
| 598 | {Feature_HasAtomicLdStBit, Feature_HwMode0Bit, }, |
| 599 | {Feature_HasAtomicLdStBit, Feature_HwMode1Bit, }, |
| 600 | {Feature_HasShortForwardBranchOptBit, Feature_HwMode0Bit, }, |
| 601 | {Feature_HasShortForwardBranchOptBit, Feature_HwMode1Bit, }, |
| 602 | {Feature_HasStdExtABit, Feature_HwMode1Bit, }, |
| 603 | {Feature_HasStdExtDBit, }, |
| 604 | {Feature_HasStdExtDBit, Feature_HwMode0Bit, }, |
| 605 | {Feature_HasStdExtDBit, Feature_HwMode1Bit, }, |
| 606 | {Feature_HasStdExtFBit, }, |
| 607 | {Feature_HasStdExtFBit, Feature_HwMode0Bit, }, |
| 608 | {Feature_HasStdExtFBit, Feature_HwMode1Bit, }, |
| 609 | {Feature_HasStdExtMBit, Feature_HwMode0Bit, }, |
| 610 | {Feature_HasStdExtMBit, Feature_HwMode1Bit, }, |
| 611 | {Feature_HasStdExtZbaBit, Feature_HwMode0Bit, }, |
| 612 | {Feature_HasStdExtZbaBit, Feature_HwMode1Bit, }, |
| 613 | {Feature_HasStdExtZbbBit, Feature_HwMode0Bit, }, |
| 614 | {Feature_HasStdExtZbbBit, Feature_HwMode1Bit, }, |
| 615 | {Feature_HasStdExtZbbOrZbkbBit, Feature_HwMode0Bit, }, |
| 616 | {Feature_HasStdExtZbbOrZbkbBit, Feature_HwMode1Bit, }, |
| 617 | {Feature_HasStdExtZbkxBit, Feature_HwMode0Bit, }, |
| 618 | {Feature_HasStdExtZbkxBit, Feature_HwMode1Bit, }, |
| 619 | {Feature_HasStdExtZbsBit, Feature_HwMode0Bit, }, |
| 620 | {Feature_HasStdExtZbsBit, Feature_HwMode1Bit, }, |
| 621 | {Feature_HasStdExtZfaBit, }, |
| 622 | {Feature_HasStdExtZfaBit, Feature_HwMode0Bit, }, |
| 623 | {Feature_HasStdExtZfaBit, Feature_HwMode1Bit, }, |
| 624 | {Feature_HasStdExtZfbfminBit, Feature_HwMode0Bit, }, |
| 625 | {Feature_HasStdExtZfbfminBit, Feature_HwMode1Bit, }, |
| 626 | {Feature_HasStdExtZfhBit, }, |
| 627 | {Feature_HasStdExtZfhBit, Feature_HwMode0Bit, }, |
| 628 | {Feature_HasStdExtZfhBit, Feature_HwMode1Bit, }, |
| 629 | {Feature_HasStdExtZfhminBit, Feature_HwMode0Bit, }, |
| 630 | {Feature_HasStdExtZfhminBit, Feature_HwMode1Bit, }, |
| 631 | {Feature_HasStdExtZfinxBit, }, |
| 632 | {Feature_HasStdExtZfinxBit, Feature_HwMode0Bit, }, |
| 633 | {Feature_HasStdExtZfinxBit, Feature_HwMode1Bit, }, |
| 634 | {Feature_HasStdExtZhinxBit, }, |
| 635 | {Feature_HasStdExtZhinxBit, Feature_HwMode0Bit, }, |
| 636 | {Feature_HasStdExtZhinxBit, Feature_HwMode1Bit, }, |
| 637 | {Feature_HasStdExtZhinxminBit, Feature_HwMode0Bit, }, |
| 638 | {Feature_HasStdExtZhinxminBit, Feature_HwMode1Bit, }, |
| 639 | {Feature_HasStdExtZmmulBit, Feature_HwMode0Bit, }, |
| 640 | {Feature_HasStdExtZmmulBit, Feature_HwMode1Bit, }, |
| 641 | {Feature_HasVInstructionsBit, Feature_HwMode0Bit, }, |
| 642 | {Feature_HasVInstructionsBit, Feature_HwMode1Bit, }, |
| 643 | {Feature_HasVInstructionsAnyFBit, Feature_HwMode0Bit, }, |
| 644 | {Feature_HasVInstructionsAnyFBit, Feature_HwMode1Bit, }, |
| 645 | {Feature_HasVInstructionsBF16Bit, Feature_HwMode0Bit, }, |
| 646 | {Feature_HasVInstructionsBF16Bit, Feature_HwMode1Bit, }, |
| 647 | {Feature_HasVInstructionsF16Bit, Feature_HwMode0Bit, }, |
| 648 | {Feature_HasVInstructionsF16Bit, Feature_HwMode1Bit, }, |
| 649 | {Feature_HasVInstructionsF16MinimalBit, Feature_HwMode0Bit, }, |
| 650 | {Feature_HasVInstructionsF16MinimalBit, Feature_HwMode1Bit, }, |
| 651 | {Feature_HasVInstructionsF64Bit, Feature_HwMode0Bit, }, |
| 652 | {Feature_HasVInstructionsF64Bit, Feature_HwMode1Bit, }, |
| 653 | {Feature_HasVInstructionsFullMultiplyBit, Feature_HwMode0Bit, }, |
| 654 | {Feature_HasVInstructionsFullMultiplyBit, Feature_HwMode1Bit, }, |
| 655 | {Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, |
| 656 | {Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, |
| 657 | {Feature_HasVendorXCVmacBit, Feature_HwMode0Bit, }, |
| 658 | {Feature_HasVendorXCVmacBit, Feature_HwMode1Bit, }, |
| 659 | {Feature_HasVendorXTHeadBaBit, Feature_HwMode0Bit, }, |
| 660 | {Feature_HasVendorXTHeadBaBit, Feature_HwMode1Bit, }, |
| 661 | {Feature_HasVendorXTHeadBbBit, Feature_HwMode0Bit, }, |
| 662 | {Feature_HasVendorXTHeadBbBit, Feature_HwMode1Bit, }, |
| 663 | {Feature_HasVendorXTHeadBsBit, Feature_HwMode0Bit, }, |
| 664 | {Feature_HasVendorXTHeadBsBit, Feature_HwMode1Bit, }, |
| 665 | {Feature_HasVendorXTHeadCondMovBit, Feature_HwMode0Bit, }, |
| 666 | {Feature_HasVendorXTHeadCondMovBit, Feature_HwMode1Bit, }, |
| 667 | {Feature_HasVendorXTHeadMacBit, Feature_HwMode0Bit, }, |
| 668 | {Feature_HasVendorXTHeadMacBit, Feature_HwMode1Bit, }, |
| 669 | {Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 670 | {Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 671 | {Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 672 | {Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 673 | {Feature_HasAtomicLdStBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 674 | {Feature_HasStdExtABit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 675 | {Feature_HasStdExtABit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 676 | {Feature_HasStdExtABit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 677 | {Feature_HasStdExtABit, Feature_NoStdExtZacasBit, Feature_HwMode1Bit, }, |
| 678 | {Feature_HasStdExtABit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 679 | {Feature_HasStdExtABit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 680 | {Feature_HasStdExtDBit, Feature_HasStdExtZfaBit, }, |
| 681 | {Feature_HasStdExtDBit, Feature_HasStdExtZfaBit, Feature_HwMode0Bit, }, |
| 682 | {Feature_HasStdExtDBit, Feature_HasStdExtZfaBit, Feature_HwMode1Bit, }, |
| 683 | {Feature_HasStdExtDBit, Feature_HasStdExtZfhminBit, Feature_HwMode0Bit, }, |
| 684 | {Feature_HasStdExtDBit, Feature_HasStdExtZfhminBit, Feature_HwMode1Bit, }, |
| 685 | {Feature_HasStdExtDBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 686 | {Feature_HasStdExtFBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 687 | {Feature_HasStdExtMBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 688 | {Feature_HasStdExtMBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 689 | {Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 690 | {Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 691 | {Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 692 | {Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 693 | {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 694 | {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 695 | {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 696 | {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 697 | {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 698 | {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 699 | {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 700 | {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 701 | {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 702 | {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 703 | {Feature_HasStdExtZbsBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 704 | {Feature_HasStdExtZbsBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 705 | {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, |
| 706 | {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 707 | {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 708 | {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 709 | {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, }, |
| 710 | {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, Feature_HwMode0Bit, }, |
| 711 | {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, Feature_HwMode1Bit, }, |
| 712 | {Feature_HasStdExtZfbfminBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 713 | {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 714 | {Feature_HasStdExtZfhminBit, Feature_NoStdExtZfhBit, Feature_HwMode0Bit, }, |
| 715 | {Feature_HasStdExtZfhminBit, Feature_NoStdExtZfhBit, Feature_HwMode1Bit, }, |
| 716 | {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 717 | {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 718 | {Feature_HasStdExtZhinxminBit, Feature_NoStdExtZhinxBit, Feature_HwMode0Bit, }, |
| 719 | {Feature_HasStdExtZhinxminBit, Feature_NoStdExtZhinxBit, Feature_HwMode1Bit, }, |
| 720 | {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 721 | {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 722 | {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 723 | {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 724 | {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 725 | {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 726 | {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 727 | {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 728 | {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 729 | {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsBit, Feature_HwMode0Bit, }, |
| 730 | {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsBit, Feature_HwMode1Bit, }, |
| 731 | {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, |
| 732 | {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, |
| 733 | {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsBit, Feature_HwMode0Bit, }, |
| 734 | {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsBit, Feature_HwMode1Bit, }, |
| 735 | {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, |
| 736 | {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, |
| 737 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsAnyFBit, Feature_HwMode0Bit, }, |
| 738 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsAnyFBit, Feature_HwMode1Bit, }, |
| 739 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsF16Bit, Feature_HwMode0Bit, }, |
| 740 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsF16Bit, Feature_HwMode1Bit, }, |
| 741 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsF64Bit, Feature_HwMode0Bit, }, |
| 742 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsF64Bit, Feature_HwMode1Bit, }, |
| 743 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, |
| 744 | {Feature_HasVInstructionsBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, |
| 745 | {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsF64Bit, Feature_HwMode0Bit, }, |
| 746 | {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsF64Bit, Feature_HwMode1Bit, }, |
| 747 | {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, |
| 748 | {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, |
| 749 | {Feature_HasVInstructionsF64Bit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, |
| 750 | {Feature_HasVInstructionsF64Bit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, |
| 751 | {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 752 | {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 753 | {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 754 | {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 755 | {Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 756 | {Feature_HasVendorXTHeadCondMovBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 757 | {Feature_HasVendorXTHeadCondMovBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 758 | {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 759 | {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, |
| 760 | {Feature_IsRV64Bit, Feature_NotHasStdExtZbaBit, Feature_HwMode0Bit, }, |
| 761 | {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 762 | {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 763 | {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 764 | {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 765 | {Feature_HasStdExtABit, Feature_HasStdExtZtsoBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 766 | {Feature_HasStdExtABit, Feature_IsRV64Bit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 767 | {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 768 | {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 769 | {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 770 | {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, |
| 771 | {Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 772 | {Feature_HasStdExtZacasBit, Feature_IsRV64Bit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, |
| 773 | {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, Feature_NoStdExtZbbBit, Feature_HwMode0Bit, }, |
| 774 | {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, Feature_NoStdExtZbbBit, Feature_HwMode1Bit, }, |
| 775 | {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, Feature_NoStdExtZbbBit, Feature_HwMode0Bit, }, |
| 776 | {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, Feature_NoStdExtZbbBit, Feature_HwMode1Bit, }, |
| 777 | {Feature_HasStdExtZdinxBit, Feature_HasStdExtZhinxminBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, |
| 778 | {Feature_HasStdExtZdinxBit, Feature_HasStdExtZhinxminBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, |
| 779 | {Feature_HasStdExtZdinxBit, Feature_HasStdExtZhinxminBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, |
| 780 | {Feature_HasStdExtZfhminBit, Feature_IsRV64Bit, Feature_NoStdExtZfhBit, Feature_HwMode0Bit, }, |
| 781 | {Feature_HasStdExtZhinxminBit, Feature_IsRV64Bit, Feature_NoStdExtZhinxBit, Feature_HwMode0Bit, }, |
| 782 | {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, Feature_NotHasStdExtZbaBit, Feature_HwMode0Bit, }, |
| 783 | }; |
| 784 | |
| 785 | // ComplexPattern predicates. |
| 786 | enum { |
| 787 | GICP_Invalid, |
| 788 | GICP_GIAddrRegImm, |
| 789 | GICP_GIShiftMask32, |
| 790 | GICP_GIShiftMaskXLen, |
| 791 | GICP_gi_sh1add_op, |
| 792 | GICP_gi_sh1add_uw_op, |
| 793 | GICP_gi_sh2add_op, |
| 794 | GICP_gi_sh2add_uw_op, |
| 795 | GICP_gi_sh3add_op, |
| 796 | GICP_gi_sh3add_uw_op, |
| 797 | }; |
| 798 | // See constructor for table contents |
| 799 | |
| 800 | RISCVInstructionSelector::ComplexMatcherMemFn |
| 801 | RISCVInstructionSelector::ComplexPredicateFns[] = { |
| 802 | nullptr, // GICP_Invalid |
| 803 | &RISCVInstructionSelector::selectAddrRegImm, // GIAddrRegImm |
| 804 | &RISCVInstructionSelector::selectShiftMask, // GIShiftMask32 |
| 805 | &RISCVInstructionSelector::selectShiftMask, // GIShiftMaskXLen |
| 806 | &RISCVInstructionSelector::selectSHXADDOp<1>, // gi_sh1add_op |
| 807 | &RISCVInstructionSelector::selectSHXADD_UWOp<1>, // gi_sh1add_uw_op |
| 808 | &RISCVInstructionSelector::selectSHXADDOp<2>, // gi_sh2add_op |
| 809 | &RISCVInstructionSelector::selectSHXADD_UWOp<2>, // gi_sh2add_uw_op |
| 810 | &RISCVInstructionSelector::selectSHXADDOp<3>, // gi_sh3add_op |
| 811 | &RISCVInstructionSelector::selectSHXADD_UWOp<3>, // gi_sh3add_uw_op |
| 812 | }; |
| 813 | |
| 814 | // PatFrag predicates. |
| 815 | enum { |
| 816 | GICXXPred_MI_Predicate_add_like_non_imm12 = GICXXPred_Invalid + 1, |
| 817 | GICXXPred_MI_Predicate_add_non_imm12, |
| 818 | }; |
| 819 | bool RISCVInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 820 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 821 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 822 | const auto &Operands = State.RecordedOperands; |
| 823 | (void)Operands; |
| 824 | (void)MRI; |
| 825 | switch (PredicateID) { |
| 826 | case GICXXPred_MI_Predicate_add_like_non_imm12: { |
| 827 | |
| 828 | const MachineOperand &ImmOp = *Operands[1]; |
| 829 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 830 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 831 | |
| 832 | if (ImmOp.isReg() && ImmOp.getReg()) |
| 833 | if (auto Val = getIConstantVRegValWithLookThrough(ImmOp.getReg(), MRI)) { |
| 834 | // We do NOT want immediates that fit in 12 bits. |
| 835 | return !isInt<12>(Val->Value.getSExtValue()); |
| 836 | } |
| 837 | |
| 838 | return true; |
| 839 | |
| 840 | llvm_unreachable("add_like_non_imm12 should have returned"); |
| 841 | } |
| 842 | case GICXXPred_MI_Predicate_add_non_imm12: { |
| 843 | |
| 844 | const MachineOperand &ImmOp = *Operands[1]; |
| 845 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 846 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 847 | |
| 848 | if (ImmOp.isReg() && ImmOp.getReg()) |
| 849 | if (auto Val = getIConstantVRegValWithLookThrough(ImmOp.getReg(), MRI)) { |
| 850 | // We do NOT want immediates that fit in 12 bits. |
| 851 | return !isInt<12>(Val->Value.getSExtValue()); |
| 852 | } |
| 853 | |
| 854 | return true; |
| 855 | |
| 856 | llvm_unreachable("add_non_imm12 should have returned"); |
| 857 | } |
| 858 | } |
| 859 | llvm_unreachable("Unknown predicate"); |
| 860 | return false; |
| 861 | } |
| 862 | // PatFrag predicates. |
| 863 | enum { |
| 864 | GICXXPred_I64_Predicate_BCLRMask = GICXXPred_Invalid + 1, |
| 865 | GICXXPred_I64_Predicate_BCLRMaski32, |
| 866 | GICXXPred_I64_Predicate_SingleBitSetMask, |
| 867 | GICXXPred_I64_Predicate_SingleBitSetMaski32, |
| 868 | GICXXPred_I64_Predicate_byteselect, |
| 869 | GICXXPred_I64_Predicate_c_lui_imm, |
| 870 | GICXXPred_I64_Predicate_csr_sysreg, |
| 871 | GICXXPred_I64_Predicate_cv_tuimm2, |
| 872 | GICXXPred_I64_Predicate_cv_tuimm5, |
| 873 | GICXXPred_I64_Predicate_cv_uimm10, |
| 874 | GICXXPred_I64_Predicate_immzero, |
| 875 | GICXXPred_I64_Predicate_payload1, |
| 876 | GICXXPred_I64_Predicate_payload2, |
| 877 | GICXXPred_I64_Predicate_payload5, |
| 878 | GICXXPred_I64_Predicate_powerOf2Minus1, |
| 879 | GICXXPred_I64_Predicate_rnum, |
| 880 | GICXXPred_I64_Predicate_shfl_uimm, |
| 881 | GICXXPred_I64_Predicate_simm5, |
| 882 | GICXXPred_I64_Predicate_simm5_plus1, |
| 883 | GICXXPred_I64_Predicate_simm5_plus1_nonzero, |
| 884 | GICXXPred_I64_Predicate_simm6, |
| 885 | GICXXPred_I64_Predicate_simm6nonzero, |
| 886 | GICXXPred_I64_Predicate_simm9_lsb0, |
| 887 | GICXXPred_I64_Predicate_simm10_lsb0000nonzero, |
| 888 | GICXXPred_I64_Predicate_simm12, |
| 889 | GICXXPred_I64_Predicate_simm12Minus1Nonzero, |
| 890 | GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1, |
| 891 | GICXXPred_I64_Predicate_simm12Plus1, |
| 892 | GICXXPred_I64_Predicate_simm12Plus1i32, |
| 893 | GICXXPred_I64_Predicate_simm12_lsb0, |
| 894 | GICXXPred_I64_Predicate_simm12_lsb00000, |
| 895 | GICXXPred_I64_Predicate_simm12_no6, |
| 896 | GICXXPred_I64_Predicate_simm12i32, |
| 897 | GICXXPred_I64_Predicate_tsimm5, |
| 898 | GICXXPred_I64_Predicate_tuimm5, |
| 899 | GICXXPred_I64_Predicate_u32simm12, |
| 900 | GICXXPred_I64_Predicate_uimm1, |
| 901 | GICXXPred_I64_Predicate_uimm2, |
| 902 | GICXXPred_I64_Predicate_uimm2_3, |
| 903 | GICXXPred_I64_Predicate_uimm2_4, |
| 904 | GICXXPred_I64_Predicate_uimm2_lsb0, |
| 905 | GICXXPred_I64_Predicate_uimm4_with_predicate, |
| 906 | GICXXPred_I64_Predicate_uimm5, |
| 907 | GICXXPred_I64_Predicate_uimm5_lsb0, |
| 908 | GICXXPred_I64_Predicate_uimm5_with_predicate, |
| 909 | GICXXPred_I64_Predicate_uimm6, |
| 910 | GICXXPred_I64_Predicate_uimm6_lsb0, |
| 911 | GICXXPred_I64_Predicate_uimm6gt32, |
| 912 | GICXXPred_I64_Predicate_uimm7_lsb00, |
| 913 | GICXXPred_I64_Predicate_uimm8_lsb00, |
| 914 | GICXXPred_I64_Predicate_uimm8_lsb000, |
| 915 | GICXXPred_I64_Predicate_uimm9_lsb000, |
| 916 | GICXXPred_I64_Predicate_uimm10_lsb00nonzero, |
| 917 | GICXXPred_I64_Predicate_uimmlog2xlen, |
| 918 | GICXXPred_I64_Predicate_uimmlog2xlennonzero, |
| 919 | }; |
| 920 | bool RISCVInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 921 | switch (PredicateID) { |
| 922 | case GICXXPred_I64_Predicate_BCLRMask: { |
| 923 | |
| 924 | if (Subtarget->is64Bit()) |
| 925 | return !isInt<12>(Imm) && isPowerOf2_64(~Imm); |
| 926 | return !isInt<12>(Imm) && isPowerOf2_32(~Imm); |
| 927 | |
| 928 | llvm_unreachable("BCLRMask should have returned"); |
| 929 | } |
| 930 | case GICXXPred_I64_Predicate_BCLRMaski32: { |
| 931 | |
| 932 | return !isInt<12>(Imm) && isPowerOf2_32(~Imm); |
| 933 | |
| 934 | } |
| 935 | case GICXXPred_I64_Predicate_SingleBitSetMask: { |
| 936 | |
| 937 | if (Subtarget->is64Bit()) |
| 938 | return !isInt<12>(Imm) && isPowerOf2_64(Imm); |
| 939 | return !isInt<12>(Imm) && isPowerOf2_32(Imm); |
| 940 | |
| 941 | llvm_unreachable("SingleBitSetMask should have returned"); |
| 942 | } |
| 943 | case GICXXPred_I64_Predicate_SingleBitSetMaski32: { |
| 944 | |
| 945 | return !isInt<12>(Imm) && isPowerOf2_32(Imm); |
| 946 | |
| 947 | } |
| 948 | case GICXXPred_I64_Predicate_byteselect: { |
| 949 | return isUInt<2>(Imm); |
| 950 | } |
| 951 | case GICXXPred_I64_Predicate_c_lui_imm: { |
| 952 | return (Imm != 0) && |
| 953 | (isUInt<5>(Imm) || |
| 954 | (Imm >= 0xfffe0 && Imm <= 0xfffff)); |
| 955 | } |
| 956 | case GICXXPred_I64_Predicate_csr_sysreg: { |
| 957 | return isUInt<12>(Imm); |
| 958 | } |
| 959 | case GICXXPred_I64_Predicate_cv_tuimm2: { |
| 960 | return isUInt<2>(Imm); |
| 961 | } |
| 962 | case GICXXPred_I64_Predicate_cv_tuimm5: { |
| 963 | return isUInt<5>(Imm); |
| 964 | } |
| 965 | case GICXXPred_I64_Predicate_cv_uimm10: { |
| 966 | return isUInt<10>(Imm); |
| 967 | } |
| 968 | case GICXXPred_I64_Predicate_immzero: { |
| 969 | return (Imm == 0); |
| 970 | } |
| 971 | case GICXXPred_I64_Predicate_payload1: { |
| 972 | return isUInt<1>(Imm); |
| 973 | } |
| 974 | case GICXXPred_I64_Predicate_payload2: { |
| 975 | return isUInt<2>(Imm); |
| 976 | } |
| 977 | case GICXXPred_I64_Predicate_payload5: { |
| 978 | return isUInt<5>(Imm); |
| 979 | } |
| 980 | case GICXXPred_I64_Predicate_powerOf2Minus1: { |
| 981 | return isPowerOf2_32(Imm+1); |
| 982 | } |
| 983 | case GICXXPred_I64_Predicate_rnum: { |
| 984 | return (Imm >= 0 && Imm <= 10); |
| 985 | } |
| 986 | case GICXXPred_I64_Predicate_shfl_uimm: { |
| 987 | |
| 988 | if (Subtarget->is64Bit()) |
| 989 | return isUInt<5>(Imm); |
| 990 | return isUInt<4>(Imm); |
| 991 | |
| 992 | llvm_unreachable("shfl_uimm should have returned"); |
| 993 | } |
| 994 | case GICXXPred_I64_Predicate_simm5: { |
| 995 | return isInt<5>(Imm); |
| 996 | } |
| 997 | case GICXXPred_I64_Predicate_simm5_plus1: { |
| 998 | return (isInt<5>(Imm) && Imm != -16) || Imm == 16; |
| 999 | } |
| 1000 | case GICXXPred_I64_Predicate_simm5_plus1_nonzero: { |
| 1001 | return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16); |
| 1002 | } |
| 1003 | case GICXXPred_I64_Predicate_simm6: { |
| 1004 | return isInt<6>(Imm); |
| 1005 | } |
| 1006 | case GICXXPred_I64_Predicate_simm6nonzero: { |
| 1007 | return (Imm != 0) && isInt<6>(Imm); |
| 1008 | } |
| 1009 | case GICXXPred_I64_Predicate_simm9_lsb0: { |
| 1010 | return isShiftedInt<8, 1>(Imm); |
| 1011 | } |
| 1012 | case GICXXPred_I64_Predicate_simm10_lsb0000nonzero: { |
| 1013 | return (Imm != 0) && isShiftedInt<6, 4>(Imm); |
| 1014 | } |
| 1015 | case GICXXPred_I64_Predicate_simm12: { |
| 1016 | return isInt<12>(Imm); |
| 1017 | } |
| 1018 | case GICXXPred_I64_Predicate_simm12Minus1Nonzero: { |
| 1019 | |
| 1020 | return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046); |
| 1021 | } |
| 1022 | case GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1: { |
| 1023 | |
| 1024 | return (Imm >= -2049 && Imm < -1) || (Imm > 0 && Imm <= 2046); |
| 1025 | } |
| 1026 | case GICXXPred_I64_Predicate_simm12Plus1: { |
| 1027 | |
| 1028 | return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048; |
| 1029 | } |
| 1030 | case GICXXPred_I64_Predicate_simm12Plus1i32: { |
| 1031 | |
| 1032 | return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048; |
| 1033 | } |
| 1034 | case GICXXPred_I64_Predicate_simm12_lsb0: { |
| 1035 | return isShiftedInt<11, 1>(Imm); |
| 1036 | } |
| 1037 | case GICXXPred_I64_Predicate_simm12_lsb00000: { |
| 1038 | return isShiftedInt<7, 5>(Imm); |
| 1039 | } |
| 1040 | case GICXXPred_I64_Predicate_simm12_no6: { |
| 1041 | |
| 1042 | return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm); |
| 1043 | } |
| 1044 | case GICXXPred_I64_Predicate_simm12i32: { |
| 1045 | return isInt<12>(Imm); |
| 1046 | } |
| 1047 | case GICXXPred_I64_Predicate_tsimm5: { |
| 1048 | return isInt<5>(Imm); |
| 1049 | } |
| 1050 | case GICXXPred_I64_Predicate_tuimm5: { |
| 1051 | return isUInt<5>(Imm); |
| 1052 | } |
| 1053 | case GICXXPred_I64_Predicate_u32simm12: { |
| 1054 | |
| 1055 | return isUInt<32>(Imm) && isInt<12>(SignExtend64<32>(Imm)); |
| 1056 | |
| 1057 | } |
| 1058 | case GICXXPred_I64_Predicate_uimm1: { |
| 1059 | return isUInt<1>(Imm); |
| 1060 | } |
| 1061 | case GICXXPred_I64_Predicate_uimm2: { |
| 1062 | return isUInt<2>(Imm); |
| 1063 | } |
| 1064 | case GICXXPred_I64_Predicate_uimm2_3: { |
| 1065 | |
| 1066 | return isShiftedUInt<2, 3>(Imm); |
| 1067 | |
| 1068 | } |
| 1069 | case GICXXPred_I64_Predicate_uimm2_4: { |
| 1070 | |
| 1071 | return isShiftedUInt<2, 4>(Imm); |
| 1072 | |
| 1073 | } |
| 1074 | case GICXXPred_I64_Predicate_uimm2_lsb0: { |
| 1075 | return isShiftedUInt<1, 1>(Imm); |
| 1076 | } |
| 1077 | case GICXXPred_I64_Predicate_uimm4_with_predicate: { |
| 1078 | return isUInt<4>(Imm); |
| 1079 | } |
| 1080 | case GICXXPred_I64_Predicate_uimm5: { |
| 1081 | return isUInt<5>(Imm); |
| 1082 | } |
| 1083 | case GICXXPred_I64_Predicate_uimm5_lsb0: { |
| 1084 | return isShiftedUInt<4, 1>(Imm); |
| 1085 | } |
| 1086 | case GICXXPred_I64_Predicate_uimm5_with_predicate: { |
| 1087 | return isUInt<5>(Imm); |
| 1088 | } |
| 1089 | case GICXXPred_I64_Predicate_uimm6: { |
| 1090 | return isUInt<6>(Imm); |
| 1091 | } |
| 1092 | case GICXXPred_I64_Predicate_uimm6_lsb0: { |
| 1093 | return isShiftedUInt<5, 1>(Imm); |
| 1094 | } |
| 1095 | case GICXXPred_I64_Predicate_uimm6gt32: { |
| 1096 | |
| 1097 | return isUInt<6>(Imm) && Imm > 32; |
| 1098 | |
| 1099 | } |
| 1100 | case GICXXPred_I64_Predicate_uimm7_lsb00: { |
| 1101 | return isShiftedUInt<5, 2>(Imm); |
| 1102 | } |
| 1103 | case GICXXPred_I64_Predicate_uimm8_lsb00: { |
| 1104 | return isShiftedUInt<6, 2>(Imm); |
| 1105 | } |
| 1106 | case GICXXPred_I64_Predicate_uimm8_lsb000: { |
| 1107 | return isShiftedUInt<5, 3>(Imm); |
| 1108 | } |
| 1109 | case GICXXPred_I64_Predicate_uimm9_lsb000: { |
| 1110 | return isShiftedUInt<6, 3>(Imm); |
| 1111 | } |
| 1112 | case GICXXPred_I64_Predicate_uimm10_lsb00nonzero: { |
| 1113 | return isShiftedUInt<8, 2>(Imm) && (Imm != 0); |
| 1114 | } |
| 1115 | case GICXXPred_I64_Predicate_uimmlog2xlen: { |
| 1116 | |
| 1117 | if (Subtarget->is64Bit()) |
| 1118 | return isUInt<6>(Imm); |
| 1119 | return isUInt<5>(Imm); |
| 1120 | |
| 1121 | llvm_unreachable("uimmlog2xlen should have returned"); |
| 1122 | } |
| 1123 | case GICXXPred_I64_Predicate_uimmlog2xlennonzero: { |
| 1124 | |
| 1125 | if (Subtarget->is64Bit()) |
| 1126 | return isUInt<6>(Imm) && (Imm != 0); |
| 1127 | return isUInt<5>(Imm) && (Imm != 0); |
| 1128 | |
| 1129 | llvm_unreachable("uimmlog2xlennonzero should have returned"); |
| 1130 | } |
| 1131 | } |
| 1132 | llvm_unreachable("Unknown predicate"); |
| 1133 | return false; |
| 1134 | } |
| 1135 | // PatFrag predicates. |
| 1136 | bool RISCVInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 1137 | llvm_unreachable("Unknown predicate"); |
| 1138 | return false; |
| 1139 | } |
| 1140 | // PatFrag predicates. |
| 1141 | enum { |
| 1142 | GICXXPred_APInt_Predicate_Shifted32OnesMask = GICXXPred_Invalid + 1, |
| 1143 | }; |
| 1144 | bool RISCVInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 1145 | switch (PredicateID) { |
| 1146 | case GICXXPred_APInt_Predicate_Shifted32OnesMask: { |
| 1147 | |
| 1148 | if (!Imm.isShiftedMask()) |
| 1149 | return false; |
| 1150 | |
| 1151 | unsigned TrailingZeros = Imm.countr_zero(); |
| 1152 | return TrailingZeros > 0 && TrailingZeros < 32 && |
| 1153 | Imm == UINT64_C(0xFFFFFFFF) << TrailingZeros; |
| 1154 | |
| 1155 | llvm_unreachable("Shifted32OnesMask should have returned"); |
| 1156 | } |
| 1157 | } |
| 1158 | llvm_unreachable("Unknown predicate"); |
| 1159 | return false; |
| 1160 | } |
| 1161 | bool RISCVInstructionSelector::testSimplePredicate(unsigned) const { |
| 1162 | llvm_unreachable("RISCVInstructionSelector does not support simple predicates!"); |
| 1163 | return false; |
| 1164 | } |
| 1165 | // Custom renderers. |
| 1166 | enum { |
| 1167 | GICR_Invalid, |
| 1168 | GICR_renderImm, |
| 1169 | GICR_renderImmPlus1, |
| 1170 | GICR_renderImmSubFrom32, |
| 1171 | GICR_renderImmSubFromXLen, |
| 1172 | GICR_renderNegImm, |
| 1173 | GICR_renderTrailingZeros, |
| 1174 | }; |
| 1175 | RISCVInstructionSelector::CustomRendererFn |
| 1176 | RISCVInstructionSelector::CustomRenderers[] = { |
| 1177 | nullptr, // GICR_Invalid |
| 1178 | &RISCVInstructionSelector::renderImm, |
| 1179 | &RISCVInstructionSelector::renderImmPlus1, |
| 1180 | &RISCVInstructionSelector::renderImmSubFrom32, |
| 1181 | &RISCVInstructionSelector::renderImmSubFromXLen, |
| 1182 | &RISCVInstructionSelector::renderNegImm, |
| 1183 | &RISCVInstructionSelector::renderTrailingZeros, |
| 1184 | }; |
| 1185 | |
| 1186 | bool RISCVInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 1187 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 1188 | MachineIRBuilder B(I); |
| 1189 | State.MIs.clear(); |
| 1190 | State.MIs.push_back(&I); |
| 1191 | |
| 1192 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 1193 | return true; |
| 1194 | } |
| 1195 | |
| 1196 | return false; |
| 1197 | } |
| 1198 | |
| 1199 | bool RISCVInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 1200 | llvm_unreachable("RISCVInstructionSelector does not support custom C++ actions!"); |
| 1201 | } |
| 1202 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 1203 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8) |
| 1204 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24) |
| 1205 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56) |
| 1206 | #else |
| 1207 | #define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val) |
| 1208 | #define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val) |
| 1209 | #define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val) |
| 1210 | #endif |
| 1211 | const uint8_t *RISCVInstructionSelector::getMatchTable() const { |
| 1212 | constexpr static uint8_t MatchTable0[] = { |
| 1213 | GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(51), GIMT_Encode2(300), /*)*//*default:*//*Label 99*/ GIMT_Encode4(319999), |
| 1214 | /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1006), |
| 1215 | /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(10348), |
| 1216 | /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(13452), |
| 1217 | /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(16357), |
| 1218 | /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(19127), |
| 1219 | /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(21897), |
| 1220 | /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(24667), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1221 | /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(27437), |
| 1222 | /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(36983), |
| 1223 | /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(44914), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1224 | /*TargetOpcode::G_BITCAST*//*Label 10*/ GIMT_Encode4(60302), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1225 | /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 11*/ GIMT_Encode4(60615), |
| 1226 | /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 12*/ GIMT_Encode4(60813), |
| 1227 | /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 13*/ GIMT_Encode4(61011), |
| 1228 | /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 14*/ GIMT_Encode4(61909), |
| 1229 | /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 15*/ GIMT_Encode4(62211), |
| 1230 | /*TargetOpcode::G_READCYCLECOUNTER*//*Label 16*/ GIMT_Encode4(62351), |
| 1231 | /*TargetOpcode::G_READSTEADYCOUNTER*//*Label 17*/ GIMT_Encode4(62390), |
| 1232 | /*TargetOpcode::G_LOAD*//*Label 18*/ GIMT_Encode4(62429), |
| 1233 | /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(66859), |
| 1234 | /*TargetOpcode::G_ZEXTLOAD*//*Label 20*/ GIMT_Encode4(67367), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1235 | /*TargetOpcode::G_STORE*//*Label 21*/ GIMT_Encode4(67875), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1236 | /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 22*/ GIMT_Encode4(71821), |
| 1237 | /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 23*/ GIMT_Encode4(76377), |
| 1238 | /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 24*/ GIMT_Encode4(80107), GIMT_Encode4(0), |
| 1239 | /*TargetOpcode::G_ATOMICRMW_AND*//*Label 25*/ GIMT_Encode4(83837), |
| 1240 | /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 26*/ GIMT_Encode4(87567), |
| 1241 | /*TargetOpcode::G_ATOMICRMW_OR*//*Label 27*/ GIMT_Encode4(87852), |
| 1242 | /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 28*/ GIMT_Encode4(91582), |
| 1243 | /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 29*/ GIMT_Encode4(95312), |
| 1244 | /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 30*/ GIMT_Encode4(99042), |
| 1245 | /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 31*/ GIMT_Encode4(102772), |
| 1246 | /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 32*/ GIMT_Encode4(106502), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1247 | /*TargetOpcode::G_FENCE*//*Label 33*/ GIMT_Encode4(110232), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1248 | /*TargetOpcode::G_INTRINSIC*//*Label 34*/ GIMT_Encode4(110450), |
| 1249 | /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 35*/ GIMT_Encode4(114630), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1250 | /*TargetOpcode::G_ANYEXT*//*Label 36*/ GIMT_Encode4(115356), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1251 | /*TargetOpcode::G_SEXT*//*Label 37*/ GIMT_Encode4(118477), GIMT_Encode4(0), |
| 1252 | /*TargetOpcode::G_ZEXT*//*Label 38*/ GIMT_Encode4(121642), |
| 1253 | /*TargetOpcode::G_SHL*//*Label 39*/ GIMT_Encode4(124858), |
| 1254 | /*TargetOpcode::G_LSHR*//*Label 40*/ GIMT_Encode4(128303), |
| 1255 | /*TargetOpcode::G_ASHR*//*Label 41*/ GIMT_Encode4(131410), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1256 | /*TargetOpcode::G_ROTR*//*Label 42*/ GIMT_Encode4(134486), |
| 1257 | /*TargetOpcode::G_ROTL*//*Label 43*/ GIMT_Encode4(137589), |
| 1258 | /*TargetOpcode::G_ICMP*//*Label 44*/ GIMT_Encode4(140655), |
| 1259 | /*TargetOpcode::G_FCMP*//*Label 45*/ GIMT_Encode4(167318), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1260 | /*TargetOpcode::G_SELECT*//*Label 46*/ GIMT_Encode4(174780), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1261 | /*TargetOpcode::G_UMULH*//*Label 47*/ GIMT_Encode4(181510), |
| 1262 | /*TargetOpcode::G_SMULH*//*Label 48*/ GIMT_Encode4(184244), |
| 1263 | /*TargetOpcode::G_UADDSAT*//*Label 49*/ GIMT_Encode4(186978), |
| 1264 | /*TargetOpcode::G_SADDSAT*//*Label 50*/ GIMT_Encode4(189764), |
| 1265 | /*TargetOpcode::G_USUBSAT*//*Label 51*/ GIMT_Encode4(192550), |
| 1266 | /*TargetOpcode::G_SSUBSAT*//*Label 52*/ GIMT_Encode4(195336), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1267 | /*TargetOpcode::G_FADD*//*Label 53*/ GIMT_Encode4(198122), |
| 1268 | /*TargetOpcode::G_FSUB*//*Label 54*/ GIMT_Encode4(200550), |
| 1269 | /*TargetOpcode::G_FMUL*//*Label 55*/ GIMT_Encode4(202978), |
| 1270 | /*TargetOpcode::G_FMA*//*Label 56*/ GIMT_Encode4(205406), GIMT_Encode4(0), |
| 1271 | /*TargetOpcode::G_FDIV*//*Label 57*/ GIMT_Encode4(222051), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1272 | /*TargetOpcode::G_FNEG*//*Label 58*/ GIMT_Encode4(224479), |
| 1273 | /*TargetOpcode::G_FPEXT*//*Label 59*/ GIMT_Encode4(226450), |
| 1274 | /*TargetOpcode::G_FPTRUNC*//*Label 60*/ GIMT_Encode4(226903), |
| 1275 | /*TargetOpcode::G_FPTOSI*//*Label 61*/ GIMT_Encode4(228899), |
| 1276 | /*TargetOpcode::G_FPTOUI*//*Label 62*/ GIMT_Encode4(234262), |
| 1277 | /*TargetOpcode::G_SITOFP*//*Label 63*/ GIMT_Encode4(239625), |
| 1278 | /*TargetOpcode::G_UITOFP*//*Label 64*/ GIMT_Encode4(245166), |
| 1279 | /*TargetOpcode::G_FABS*//*Label 65*/ GIMT_Encode4(250707), |
| 1280 | /*TargetOpcode::G_FCOPYSIGN*//*Label 66*/ GIMT_Encode4(252678), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1281 | /*TargetOpcode::G_FMINNUM*//*Label 67*/ GIMT_Encode4(258327), |
| 1282 | /*TargetOpcode::G_FMAXNUM*//*Label 68*/ GIMT_Encode4(260412), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1283 | /*TargetOpcode::G_FMINIMUM*//*Label 69*/ GIMT_Encode4(262497), |
| 1284 | /*TargetOpcode::G_FMAXIMUM*//*Label 70*/ GIMT_Encode4(262623), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1285 | /*TargetOpcode::G_SMIN*//*Label 71*/ GIMT_Encode4(262749), |
| 1286 | /*TargetOpcode::G_SMAX*//*Label 72*/ GIMT_Encode4(265525), |
| 1287 | /*TargetOpcode::G_UMIN*//*Label 73*/ GIMT_Encode4(268301), |
| 1288 | /*TargetOpcode::G_UMAX*//*Label 74*/ GIMT_Encode4(271077), |
| 1289 | /*TargetOpcode::G_ABS*//*Label 75*/ GIMT_Encode4(273853), |
| 1290 | /*TargetOpcode::G_LROUND*//*Label 76*/ GIMT_Encode4(274011), |
| 1291 | /*TargetOpcode::G_LLROUND*//*Label 77*/ GIMT_Encode4(274909), |
| 1292 | /*TargetOpcode::G_BR*//*Label 78*/ GIMT_Encode4(275211), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1293 | /*TargetOpcode::G_CTTZ*//*Label 79*/ GIMT_Encode4(275227), GIMT_Encode4(0), |
| 1294 | /*TargetOpcode::G_CTLZ*//*Label 80*/ GIMT_Encode4(277777), GIMT_Encode4(0), |
| 1295 | /*TargetOpcode::G_CTPOP*//*Label 81*/ GIMT_Encode4(280473), |
| 1296 | /*TargetOpcode::G_BSWAP*//*Label 82*/ GIMT_Encode4(283023), |
| 1297 | /*TargetOpcode::G_BITREVERSE*//*Label 83*/ GIMT_Encode4(285558), |
| 1298 | /*TargetOpcode::G_FCEIL*//*Label 84*/ GIMT_Encode4(288052), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1299 | /*TargetOpcode::G_FSQRT*//*Label 85*/ GIMT_Encode4(288250), |
| 1300 | /*TargetOpcode::G_FFLOOR*//*Label 86*/ GIMT_Encode4(290426), |
| 1301 | /*TargetOpcode::G_FRINT*//*Label 87*/ GIMT_Encode4(290624), |
| 1302 | /*TargetOpcode::G_FNEARBYINT*//*Label 88*/ GIMT_Encode4(290822), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1303 | /*TargetOpcode::G_STRICT_FADD*//*Label 89*/ GIMT_Encode4(291020), |
| 1304 | /*TargetOpcode::G_STRICT_FSUB*//*Label 90*/ GIMT_Encode4(293448), |
| 1305 | /*TargetOpcode::G_STRICT_FMUL*//*Label 91*/ GIMT_Encode4(295876), |
| 1306 | /*TargetOpcode::G_STRICT_FDIV*//*Label 92*/ GIMT_Encode4(298304), GIMT_Encode4(0), |
| 1307 | /*TargetOpcode::G_STRICT_FMA*//*Label 93*/ GIMT_Encode4(300732), |
| 1308 | /*TargetOpcode::G_STRICT_FSQRT*//*Label 94*/ GIMT_Encode4(317377), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1309 | /*TargetOpcode::G_TRAP*//*Label 95*/ GIMT_Encode4(319553), |
| 1310 | /*TargetOpcode::G_DEBUGTRAP*//*Label 96*/ GIMT_Encode4(319566), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1311 | /*RISCV::G_FCLASS*//*Label 97*/ GIMT_Encode4(319579), |
| 1312 | /*RISCV::G_READ_VLENB*//*Label 98*/ GIMT_Encode4(319939), |
| 1313 | // Label 0: @1006 |
| 1314 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 124*/ GIMT_Encode4(10347), |
| 1315 | /*GILLT_s32*//*Label 100*/ GIMT_Encode4(1141), |
| 1316 | /*GILLT_s64*//*Label 101*/ GIMT_Encode4(3639), GIMT_Encode4(0), |
| 1317 | /*GILLT_nxv1s8*//*Label 102*/ GIMT_Encode4(7817), |
| 1318 | /*GILLT_nxv1s16*//*Label 103*/ GIMT_Encode4(7932), |
| 1319 | /*GILLT_nxv1s32*//*Label 104*/ GIMT_Encode4(8047), |
| 1320 | /*GILLT_nxv1s64*//*Label 105*/ GIMT_Encode4(8162), GIMT_Encode4(0), |
| 1321 | /*GILLT_nxv2s8*//*Label 106*/ GIMT_Encode4(8277), |
| 1322 | /*GILLT_nxv2s16*//*Label 107*/ GIMT_Encode4(8392), |
| 1323 | /*GILLT_nxv2s32*//*Label 108*/ GIMT_Encode4(8507), |
| 1324 | /*GILLT_nxv2s64*//*Label 109*/ GIMT_Encode4(8622), GIMT_Encode4(0), |
| 1325 | /*GILLT_nxv4s8*//*Label 110*/ GIMT_Encode4(8737), |
| 1326 | /*GILLT_nxv4s16*//*Label 111*/ GIMT_Encode4(8852), |
| 1327 | /*GILLT_nxv4s32*//*Label 112*/ GIMT_Encode4(8967), |
| 1328 | /*GILLT_nxv4s64*//*Label 113*/ GIMT_Encode4(9082), GIMT_Encode4(0), |
| 1329 | /*GILLT_nxv8s8*//*Label 114*/ GIMT_Encode4(9197), |
| 1330 | /*GILLT_nxv8s16*//*Label 115*/ GIMT_Encode4(9312), |
| 1331 | /*GILLT_nxv8s32*//*Label 116*/ GIMT_Encode4(9427), |
| 1332 | /*GILLT_nxv8s64*//*Label 117*/ GIMT_Encode4(9542), GIMT_Encode4(0), |
| 1333 | /*GILLT_nxv16s8*//*Label 118*/ GIMT_Encode4(9657), |
| 1334 | /*GILLT_nxv16s16*//*Label 119*/ GIMT_Encode4(9772), |
| 1335 | /*GILLT_nxv16s32*//*Label 120*/ GIMT_Encode4(9887), GIMT_Encode4(0), |
| 1336 | /*GILLT_nxv32s8*//*Label 121*/ GIMT_Encode4(10002), |
| 1337 | /*GILLT_nxv32s16*//*Label 122*/ GIMT_Encode4(10117), GIMT_Encode4(0), |
| 1338 | /*GILLT_nxv64s8*//*Label 123*/ GIMT_Encode4(10232), |
| 1339 | // Label 100: @1141 |
| 1340 | GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3638), |
| 1341 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1343 | GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(1200), // Rule ID 2716 // |
| 1344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1346 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x |
| 1347 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y |
| 1348 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1349 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1350 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 1351 | // (add:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1:$pred:2:x, GPR:{ *:[i32] }:$rs2:$pred:2:y)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1354 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1355 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1356 | GIR_RootConstrainSelectedInstOperands, |
| 1357 | // GIR_Coverage, 2716, |
| 1358 | GIR_EraseRootFromParent_Done, |
| 1359 | // Label 126: @1200 |
| 1360 | GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(1248), // Rule ID 2726 // |
| 1361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1363 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x |
| 1364 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y |
| 1365 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1366 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1367 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 1368 | // (add:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1:$pred:4:x, GPR:{ *:[i32] }:$rs2:$pred:4:y)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1371 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1372 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1373 | GIR_RootConstrainSelectedInstOperands, |
| 1374 | // GIR_Coverage, 2726, |
| 1375 | GIR_EraseRootFromParent_Done, |
| 1376 | // Label 127: @1248 |
| 1377 | GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(1296), // Rule ID 2736 // |
| 1378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1380 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x |
| 1381 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y |
| 1382 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1383 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 1385 | // (add:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1:$pred:6:x, GPR:{ *:[i32] }:$rs2:$pred:6:y)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1388 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1389 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1390 | GIR_RootConstrainSelectedInstOperands, |
| 1391 | // GIR_Coverage, 2736, |
| 1392 | GIR_EraseRootFromParent_Done, |
| 1393 | // Label 128: @1296 |
| 1394 | GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(1347), // Rule ID 63003 // |
| 1395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1397 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:27:x |
| 1398 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:27:y |
| 1399 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1400 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 1401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 1402 | // (add:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1:$pred:27:x, GPR:{ *:[i32] }:$rs2:$pred:27:y)<<P:27:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh1add_op:{ *:[i32] }:$rs1, 1:{ *:[i32] }) |
| 1403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1405 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1406 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 1408 | GIR_RootConstrainSelectedInstOperands, |
| 1409 | // GIR_Coverage, 63003, |
| 1410 | GIR_EraseRootFromParent_Done, |
| 1411 | // Label 129: @1347 |
| 1412 | GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(1398), // Rule ID 63005 // |
| 1413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1415 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:28:x |
| 1416 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:28:y |
| 1417 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1418 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 1419 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 1420 | // (add:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1:$pred:28:x, GPR:{ *:[i32] }:$rs2:$pred:28:y)<<P:28:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh2add_op:{ *:[i32] }:$rs1, 2:{ *:[i32] }) |
| 1421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1423 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1424 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 1426 | GIR_RootConstrainSelectedInstOperands, |
| 1427 | // GIR_Coverage, 63005, |
| 1428 | GIR_EraseRootFromParent_Done, |
| 1429 | // Label 130: @1398 |
| 1430 | GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(1449), // Rule ID 63007 // |
| 1431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1433 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:29:x |
| 1434 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:29:y |
| 1435 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1436 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 1437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 1438 | // (add:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1:$pred:29:x, GPR:{ *:[i32] }:$rs2:$pred:29:y)<<P:29:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh3add_op:{ *:[i32] }:$rs1, 3:{ *:[i32] }) |
| 1439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1441 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1442 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1444 | GIR_RootConstrainSelectedInstOperands, |
| 1445 | // GIR_Coverage, 63007, |
| 1446 | GIR_EraseRootFromParent_Done, |
| 1447 | // Label 131: @1449 |
| 1448 | GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(1497), // Rule ID 65226 // |
| 1449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1451 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:2:y |
| 1452 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1453 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:2:x |
| 1454 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 1456 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:2:y, sh1add_op:{ *:[i32] }:$rs1:$pred:2:x)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1459 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1460 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1461 | GIR_RootConstrainSelectedInstOperands, |
| 1462 | // GIR_Coverage, 65226, |
| 1463 | GIR_EraseRootFromParent_Done, |
| 1464 | // Label 132: @1497 |
| 1465 | GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(1545), // Rule ID 65234 // |
| 1466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1468 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y |
| 1469 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1470 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x |
| 1471 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 1473 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:4:y, sh2add_op:{ *:[i32] }:$rs1:$pred:4:x)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1476 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1477 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1478 | GIR_RootConstrainSelectedInstOperands, |
| 1479 | // GIR_Coverage, 65234, |
| 1480 | GIR_EraseRootFromParent_Done, |
| 1481 | // Label 133: @1545 |
| 1482 | GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(1593), // Rule ID 65242 // |
| 1483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1485 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:6:y |
| 1486 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1487 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:6:x |
| 1488 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1489 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 1490 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:6:y, sh3add_op:{ *:[i32] }:$rs1:$pred:6:x)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1493 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1494 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1495 | GIR_RootConstrainSelectedInstOperands, |
| 1496 | // GIR_Coverage, 65242, |
| 1497 | GIR_EraseRootFromParent_Done, |
| 1498 | // Label 134: @1593 |
| 1499 | GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(1644), // Rule ID 73721 // |
| 1500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1502 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:27:y |
| 1503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1504 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:27:x |
| 1505 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 1506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 1507 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:27:y, sh1add_op:{ *:[i32] }:$rs1:$pred:27:x)<<P:27:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh1add_op:{ *:[i32] }:$rs1, 1:{ *:[i32] }) |
| 1508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1510 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1511 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 1513 | GIR_RootConstrainSelectedInstOperands, |
| 1514 | // GIR_Coverage, 73721, |
| 1515 | GIR_EraseRootFromParent_Done, |
| 1516 | // Label 135: @1644 |
| 1517 | GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(1695), // Rule ID 73723 // |
| 1518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1520 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:28:y |
| 1521 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1522 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:28:x |
| 1523 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 1524 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 1525 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:28:y, sh2add_op:{ *:[i32] }:$rs1:$pred:28:x)<<P:28:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh2add_op:{ *:[i32] }:$rs1, 2:{ *:[i32] }) |
| 1526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1528 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1529 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 1531 | GIR_RootConstrainSelectedInstOperands, |
| 1532 | // GIR_Coverage, 73723, |
| 1533 | GIR_EraseRootFromParent_Done, |
| 1534 | // Label 136: @1695 |
| 1535 | GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(1746), // Rule ID 73725 // |
| 1536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1538 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:29:y |
| 1539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1540 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:29:x |
| 1541 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 1542 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 1543 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:29:y, sh3add_op:{ *:[i32] }:$rs1:$pred:29:x)<<P:29:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh3add_op:{ *:[i32] }:$rs1, 3:{ *:[i32] }) |
| 1544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1546 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1547 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 1548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1549 | GIR_RootConstrainSelectedInstOperands, |
| 1550 | // GIR_Coverage, 73725, |
| 1551 | GIR_EraseRootFromParent_Done, |
| 1552 | // Label 137: @1746 |
| 1553 | GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(1814), // Rule ID 2710 // |
| 1554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1556 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x |
| 1557 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1558 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1559 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1560 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1561 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1562 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 1563 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y |
| 1564 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1565 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1566 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1567 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }):$pred:1:x, GPR:{ *:[i32] }:$rs2:$pred:1:y)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1570 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1571 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1572 | GIR_RootConstrainSelectedInstOperands, |
| 1573 | // GIR_Coverage, 2710, |
| 1574 | GIR_EraseRootFromParent_Done, |
| 1575 | // Label 138: @1814 |
| 1576 | GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(1882), // Rule ID 2720 // |
| 1577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1579 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x |
| 1580 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1581 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1582 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1583 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1584 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1585 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 1586 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y |
| 1587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1588 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1589 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1590 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i32] }):$pred:3:x, GPR:{ *:[i32] }:$rs2:$pred:3:y)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1593 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1594 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1595 | GIR_RootConstrainSelectedInstOperands, |
| 1596 | // GIR_Coverage, 2720, |
| 1597 | GIR_EraseRootFromParent_Done, |
| 1598 | // Label 139: @1882 |
| 1599 | GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(1950), // Rule ID 2730 // |
| 1600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1601 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1602 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x |
| 1603 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1605 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1606 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1607 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1608 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 1609 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y |
| 1610 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1611 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1612 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1613 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i32] }):$pred:5:x, GPR:{ *:[i32] }:$rs2:$pred:5:y)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1617 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1618 | GIR_RootConstrainSelectedInstOperands, |
| 1619 | // GIR_Coverage, 2730, |
| 1620 | GIR_EraseRootFromParent_Done, |
| 1621 | // Label 140: @1950 |
| 1622 | GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(2018), // Rule ID 2832 // |
| 1623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 1624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1625 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:24:x |
| 1626 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1627 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1628 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1629 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1630 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1631 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 1632 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:24:y |
| 1633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1634 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1635 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1636 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:24:x, GPR:{ *:[i32] }:$rs2:$pred:24:y)<<P:24:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1640 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1641 | GIR_RootConstrainSelectedInstOperands, |
| 1642 | // GIR_Coverage, 2832, |
| 1643 | GIR_EraseRootFromParent_Done, |
| 1644 | // Label 141: @2018 |
| 1645 | GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(2086), // Rule ID 2833 // |
| 1646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), |
| 1647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1648 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:24:x |
| 1649 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1650 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1651 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1652 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1653 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1654 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 1655 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:24:y |
| 1656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1657 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1658 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1659 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:24:x, GPR:{ *:[i32] }:$rs2:$pred:24:y)<<P:24:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1663 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1664 | GIR_RootConstrainSelectedInstOperands, |
| 1665 | // GIR_Coverage, 2833, |
| 1666 | GIR_EraseRootFromParent_Done, |
| 1667 | // Label 142: @2086 |
| 1668 | GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2154), // Rule ID 2838 // |
| 1669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 1670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1671 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:25:x |
| 1672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1675 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1677 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 1678 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:25:y |
| 1679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1680 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1681 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1682 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:25:x, GPR:{ *:[i32] }:$rs2:$pred:25:y)<<P:25:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1687 | GIR_RootConstrainSelectedInstOperands, |
| 1688 | // GIR_Coverage, 2838, |
| 1689 | GIR_EraseRootFromParent_Done, |
| 1690 | // Label 143: @2154 |
| 1691 | GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2222), // Rule ID 2839 // |
| 1692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), |
| 1693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1694 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:25:x |
| 1695 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1696 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1697 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1698 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1699 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1700 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 1701 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:25:y |
| 1702 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1703 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1704 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1705 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:25:x, GPR:{ *:[i32] }:$rs2:$pred:25:y)<<P:25:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1709 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1710 | GIR_RootConstrainSelectedInstOperands, |
| 1711 | // GIR_Coverage, 2839, |
| 1712 | GIR_EraseRootFromParent_Done, |
| 1713 | // Label 144: @2222 |
| 1714 | GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(2290), // Rule ID 2844 // |
| 1715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 1716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1717 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:26:x |
| 1718 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1719 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1720 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1721 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1722 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1723 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 1724 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:26:y |
| 1725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1726 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1727 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1728 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:26:x, GPR:{ *:[i32] }:$rs2:$pred:26:y)<<P:26:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1732 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1733 | GIR_RootConstrainSelectedInstOperands, |
| 1734 | // GIR_Coverage, 2844, |
| 1735 | GIR_EraseRootFromParent_Done, |
| 1736 | // Label 145: @2290 |
| 1737 | GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(2358), // Rule ID 2845 // |
| 1738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), |
| 1739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1740 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:26:x |
| 1741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1742 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1743 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1744 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1745 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1746 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 1747 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:26:y |
| 1748 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1749 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1750 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1751 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:26:x, GPR:{ *:[i32] }:$rs2:$pred:26:y)<<P:26:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1755 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 1756 | GIR_RootConstrainSelectedInstOperands, |
| 1757 | // GIR_Coverage, 2845, |
| 1758 | GIR_EraseRootFromParent_Done, |
| 1759 | // Label 146: @2358 |
| 1760 | GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2426), // Rule ID 65222 // |
| 1761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1763 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y |
| 1764 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1765 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:1:x |
| 1766 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1767 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1768 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1769 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1770 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1771 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 1772 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1773 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1774 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:1:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }):$pred:1:x)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1778 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1779 | GIR_RootConstrainSelectedInstOperands, |
| 1780 | // GIR_Coverage, 65222, |
| 1781 | GIR_EraseRootFromParent_Done, |
| 1782 | // Label 147: @2426 |
| 1783 | GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(2494), // Rule ID 65230 // |
| 1784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1786 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:3:y |
| 1787 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1788 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:3:x |
| 1789 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1790 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1791 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1792 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1793 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1794 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 1795 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1796 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1797 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:3:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i32] }):$pred:3:x)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1801 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1802 | GIR_RootConstrainSelectedInstOperands, |
| 1803 | // GIR_Coverage, 65230, |
| 1804 | GIR_EraseRootFromParent_Done, |
| 1805 | // Label 148: @2494 |
| 1806 | GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2562), // Rule ID 65238 // |
| 1807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), |
| 1808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1809 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y |
| 1810 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1811 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:5:x |
| 1812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1813 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1815 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1816 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1817 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 1818 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1819 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1820 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:5:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i32] }):$pred:5:x)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1824 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1825 | GIR_RootConstrainSelectedInstOperands, |
| 1826 | // GIR_Coverage, 65238, |
| 1827 | GIR_EraseRootFromParent_Done, |
| 1828 | // Label 149: @2562 |
| 1829 | GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2630), // Rule ID 65294 // |
| 1830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 1831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1832 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:24:y |
| 1833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1834 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:24:x |
| 1835 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1836 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1837 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1838 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1839 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1840 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 1841 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1842 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1843 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:24:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:24:x)<<P:24:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1847 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1848 | GIR_RootConstrainSelectedInstOperands, |
| 1849 | // GIR_Coverage, 65294, |
| 1850 | GIR_EraseRootFromParent_Done, |
| 1851 | // Label 150: @2630 |
| 1852 | GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2698), // Rule ID 65295 // |
| 1853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), |
| 1854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1855 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:24:y |
| 1856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1857 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:24:x |
| 1858 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1859 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1860 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1861 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1862 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1863 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 1864 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1865 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1866 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:24:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:24:x)<<P:24:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 1868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1869 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1870 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1871 | GIR_RootConstrainSelectedInstOperands, |
| 1872 | // GIR_Coverage, 65295, |
| 1873 | GIR_EraseRootFromParent_Done, |
| 1874 | // Label 151: @2698 |
| 1875 | GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2766), // Rule ID 65298 // |
| 1876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 1877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1878 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:25:y |
| 1879 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1880 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:25:x |
| 1881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1882 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1883 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1884 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1885 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1886 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 1887 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1888 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1889 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:25:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:25:x)<<P:25:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1893 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1894 | GIR_RootConstrainSelectedInstOperands, |
| 1895 | // GIR_Coverage, 65298, |
| 1896 | GIR_EraseRootFromParent_Done, |
| 1897 | // Label 152: @2766 |
| 1898 | GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(2834), // Rule ID 65299 // |
| 1899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), |
| 1900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1901 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:25:y |
| 1902 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1903 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:25:x |
| 1904 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1905 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1906 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1907 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1908 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1909 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 1910 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1911 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1912 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:25:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:25:x)<<P:25:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 1914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1916 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1917 | GIR_RootConstrainSelectedInstOperands, |
| 1918 | // GIR_Coverage, 65299, |
| 1919 | GIR_EraseRootFromParent_Done, |
| 1920 | // Label 153: @2834 |
| 1921 | GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(2902), // Rule ID 65302 // |
| 1922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 1923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1924 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:26:y |
| 1925 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1926 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:26:x |
| 1927 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1928 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1929 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1930 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1931 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1932 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 1933 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1934 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1935 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:26:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:26:x)<<P:26:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1939 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1940 | GIR_RootConstrainSelectedInstOperands, |
| 1941 | // GIR_Coverage, 65302, |
| 1942 | GIR_EraseRootFromParent_Done, |
| 1943 | // Label 154: @2902 |
| 1944 | GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2970), // Rule ID 65303 // |
| 1945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), |
| 1946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1947 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:26:y |
| 1948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1949 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:26:x |
| 1950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1951 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1952 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1953 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1954 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1955 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 1956 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 1957 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1958 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:26:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:26:x)<<P:26:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 1959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 1960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 1962 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 1963 | GIR_RootConstrainSelectedInstOperands, |
| 1964 | // GIR_Coverage, 65303, |
| 1965 | GIR_EraseRootFromParent_Done, |
| 1966 | // Label 155: @2970 |
| 1967 | GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(3037), // Rule ID 73719 // |
| 1968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1970 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1971 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1972 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1973 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1974 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1975 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1976 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 1977 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), |
| 1978 | // MIs[2] Operand 1 |
| 1979 | // No operand predicates |
| 1980 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1981 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1982 | // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2), GPR:{ *:[i32] }:$rs1) => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2) |
| 1983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 1984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 1985 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 1986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 1987 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 |
| 1988 | GIR_RootConstrainSelectedInstOperands, |
| 1989 | // GIR_Coverage, 73719, |
| 1990 | GIR_EraseRootFromParent_Done, |
| 1991 | // Label 156: @3037 |
| 1992 | GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(3104), // Rule ID 62999 // |
| 1993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), |
| 1994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 1996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1997 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1999 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2000 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2001 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2002 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2003 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), |
| 2004 | // MIs[2] Operand 1 |
| 2005 | // No operand predicates |
| 2006 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2007 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2)) => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2) |
| 2008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2010 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 2011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 2012 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 |
| 2013 | GIR_RootConstrainSelectedInstOperands, |
| 2014 | // GIR_Coverage, 62999, |
| 2015 | GIR_EraseRootFromParent_Done, |
| 2016 | // Label 157: @3104 |
| 2017 | GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(3146), // Rule ID 69 // |
| 2018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 2019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2020 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2021 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2022 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2023 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 2024 | // MIs[1] Operand 1 |
| 2025 | // No operand predicates |
| 2026 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2027 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) |
| 2028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 2029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2030 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 2031 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2032 | GIR_RootConstrainSelectedInstOperands, |
| 2033 | // GIR_Coverage, 69, |
| 2034 | GIR_EraseRootFromParent_Done, |
| 2035 | // Label 158: @3146 |
| 2036 | GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(3190), // Rule ID 310 // |
| 2037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 2038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2040 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2041 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2042 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12i32), |
| 2043 | // MIs[1] Operand 1 |
| 2044 | // No operand predicates |
| 2045 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2046 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12i32>>:$imm) => (ADDIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (as_i64imm:{ *:[i64] } ?:{ *:[i32] }:$imm)) |
| 2047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDIW), |
| 2048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2049 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 2050 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm |
| 2051 | GIR_RootConstrainSelectedInstOperands, |
| 2052 | // GIR_Coverage, 310, |
| 2053 | GIR_EraseRootFromParent_Done, |
| 2054 | // Label 159: @3190 |
| 2055 | GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(3251), // Rule ID 73727 // |
| 2056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode1), |
| 2057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2058 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2059 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2060 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2061 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2062 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2063 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2064 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2065 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2066 | // (add:{ *:[i32] } (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rd) => (TH_MULA:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), |
| 2068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 2069 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 2070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 2072 | GIR_RootConstrainSelectedInstOperands, |
| 2073 | // GIR_Coverage, 73727, |
| 2074 | GIR_EraseRootFromParent_Done, |
| 2075 | // Label 160: @3251 |
| 2076 | GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(3312), // Rule ID 73731 // |
| 2077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0), |
| 2078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2079 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2080 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2081 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2082 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2083 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2084 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2085 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2086 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2087 | // (add:{ *:[i32] } (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rd) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), |
| 2089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 2090 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 2091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 2093 | GIR_RootConstrainSelectedInstOperands, |
| 2094 | // GIR_Coverage, 73731, |
| 2095 | GIR_EraseRootFromParent_Done, |
| 2096 | // Label 161: @3312 |
| 2097 | GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(3373), // Rule ID 73732 // |
| 2098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1), |
| 2099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2100 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2101 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2102 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2103 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2104 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2105 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2106 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2107 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2108 | // (add:{ *:[i32] } (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rd) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), |
| 2110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 2111 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 2112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 2114 | GIR_RootConstrainSelectedInstOperands, |
| 2115 | // GIR_Coverage, 73732, |
| 2116 | GIR_EraseRootFromParent_Done, |
| 2117 | // Label 162: @3373 |
| 2118 | GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(3434), // Rule ID 63059 // |
| 2119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode1), |
| 2120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2122 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2123 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2124 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2125 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2126 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2127 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2128 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2129 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULA:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), |
| 2131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 2132 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 2133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 2135 | GIR_RootConstrainSelectedInstOperands, |
| 2136 | // GIR_Coverage, 63059, |
| 2137 | GIR_EraseRootFromParent_Done, |
| 2138 | // Label 163: @3434 |
| 2139 | GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(3495), // Rule ID 63316 // |
| 2140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0), |
| 2141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2144 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2145 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2146 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2147 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2148 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2149 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2150 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), |
| 2152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 2153 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 2154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 2156 | GIR_RootConstrainSelectedInstOperands, |
| 2157 | // GIR_Coverage, 63316, |
| 2158 | GIR_EraseRootFromParent_Done, |
| 2159 | // Label 164: @3495 |
| 2160 | GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(3556), // Rule ID 63317 // |
| 2161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1), |
| 2162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2164 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2165 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2166 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2167 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2168 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2169 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2170 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2171 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), |
| 2173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 2174 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 2175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 2177 | GIR_RootConstrainSelectedInstOperands, |
| 2178 | // GIR_Coverage, 63317, |
| 2179 | GIR_EraseRootFromParent_Done, |
| 2180 | // Label 165: @3556 |
| 2181 | GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3583), // Rule ID 67 // |
| 2182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 2183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2185 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2186 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2187 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADD), |
| 2188 | GIR_RootConstrainSelectedInstOperands, |
| 2189 | // GIR_Coverage, 67, |
| 2190 | GIR_Done, |
| 2191 | // Label 166: @3583 |
| 2192 | GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3610), // Rule ID 297 // |
| 2193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 2194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2195 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2196 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2197 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADDW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2198 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADDW), |
| 2199 | GIR_RootConstrainSelectedInstOperands, |
| 2200 | // GIR_Coverage, 297, |
| 2201 | GIR_Done, |
| 2202 | // Label 167: @3610 |
| 2203 | GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3637), // Rule ID 298 // |
| 2204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 2205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2206 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2207 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2208 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADDW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 2209 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADDW), |
| 2210 | GIR_RootConstrainSelectedInstOperands, |
| 2211 | // GIR_Coverage, 298, |
| 2212 | GIR_Done, |
| 2213 | // Label 168: @3637 |
| 2214 | GIM_Reject, |
| 2215 | // Label 125: @3638 |
| 2216 | GIM_Reject, |
| 2217 | // Label 101: @3639 |
| 2218 | GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(7816), |
| 2219 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2220 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2221 | GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3745), // Rule ID 2760 // |
| 2222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2224 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:11:x |
| 2225 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2226 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2227 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2228 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2229 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2230 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2231 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2232 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2233 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2234 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1, |
| 2235 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934591), |
| 2236 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:11:y |
| 2237 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2238 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2239 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2240 | // (add:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), 8589934591:{ *:[i64] }):$pred:11:x, GPR:{ *:[i64] }:$rs2:$pred:11:y)<<P:11:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 2242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2244 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2245 | GIR_RootConstrainSelectedInstOperands, |
| 2246 | // GIR_Coverage, 2760, |
| 2247 | GIR_EraseRootFromParent_Done, |
| 2248 | // Label 170: @3745 |
| 2249 | GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3840), // Rule ID 2762 // |
| 2250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2252 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:12:x |
| 2253 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2254 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2255 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2256 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2257 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2258 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2259 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2260 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2261 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2262 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 2, |
| 2263 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869183), |
| 2264 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:12:y |
| 2265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2266 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2267 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2268 | // (add:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), 17179869183:{ *:[i64] }):$pred:12:x, GPR:{ *:[i64] }:$rs2:$pred:12:y)<<P:12:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 2270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2272 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2273 | GIR_RootConstrainSelectedInstOperands, |
| 2274 | // GIR_Coverage, 2762, |
| 2275 | GIR_EraseRootFromParent_Done, |
| 2276 | // Label 171: @3840 |
| 2277 | GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3935), // Rule ID 2764 // |
| 2278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2280 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:13:x |
| 2281 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2282 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2283 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2284 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2285 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2286 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2287 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2288 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2289 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2290 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 3, |
| 2291 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738367), |
| 2292 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:13:y |
| 2293 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2294 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2295 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2296 | // (add:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), 34359738367:{ *:[i64] }):$pred:13:x, GPR:{ *:[i64] }:$rs2:$pred:13:y)<<P:13:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 2298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2300 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2301 | GIR_RootConstrainSelectedInstOperands, |
| 2302 | // GIR_Coverage, 2764, |
| 2303 | GIR_EraseRootFromParent_Done, |
| 2304 | // Label 172: @3935 |
| 2305 | GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(4030), // Rule ID 2751 // |
| 2306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2308 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x |
| 2309 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2310 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2311 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2312 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2313 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2314 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2315 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2316 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2317 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2318 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 2319 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 2320 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y |
| 2321 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2322 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2323 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2324 | // (add:{ *:[i64] } (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 1:{ *:[i64] }):$pred:8:x, GPR:{ *:[i64] }:$rs2:$pred:8:y)<<P:8:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 2326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2327 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2329 | GIR_RootConstrainSelectedInstOperands, |
| 2330 | // GIR_Coverage, 2751, |
| 2331 | GIR_EraseRootFromParent_Done, |
| 2332 | // Label 173: @4030 |
| 2333 | GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(4125), // Rule ID 2754 // |
| 2334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2336 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x |
| 2337 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2338 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2339 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2340 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2341 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2342 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2343 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2344 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2345 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2346 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 2347 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 2348 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y |
| 2349 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2350 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2351 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2352 | // (add:{ *:[i64] } (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 2:{ *:[i64] }):$pred:9:x, GPR:{ *:[i64] }:$rs2:$pred:9:y)<<P:9:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 2354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2356 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2357 | GIR_RootConstrainSelectedInstOperands, |
| 2358 | // GIR_Coverage, 2754, |
| 2359 | GIR_EraseRootFromParent_Done, |
| 2360 | // Label 174: @4125 |
| 2361 | GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(4220), // Rule ID 2757 // |
| 2362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2364 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x |
| 2365 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2366 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2367 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2368 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2369 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2370 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2371 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2372 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2373 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2374 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 2375 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 2376 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y |
| 2377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2378 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2379 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2380 | // (add:{ *:[i64] } (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 3:{ *:[i64] }):$pred:10:x, GPR:{ *:[i64] }:$rs2:$pred:10:y)<<P:10:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 2382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2384 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2385 | GIR_RootConstrainSelectedInstOperands, |
| 2386 | // GIR_Coverage, 2757, |
| 2387 | GIR_EraseRootFromParent_Done, |
| 2388 | // Label 175: @4220 |
| 2389 | GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(4315), // Rule ID 65252 // |
| 2390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2392 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:11:y |
| 2393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2394 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:11:x |
| 2395 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2396 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2397 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2398 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2399 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2400 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2401 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2402 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2403 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2404 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1, |
| 2405 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934591), |
| 2406 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2407 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2408 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:11:y, (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), 8589934591:{ *:[i64] }):$pred:11:x)<<P:11:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 2410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2412 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2413 | GIR_RootConstrainSelectedInstOperands, |
| 2414 | // GIR_Coverage, 65252, |
| 2415 | GIR_EraseRootFromParent_Done, |
| 2416 | // Label 176: @4315 |
| 2417 | GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(4410), // Rule ID 65254 // |
| 2418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2420 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:12:y |
| 2421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2422 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:12:x |
| 2423 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2424 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2425 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2426 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2427 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2428 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2429 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2430 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2431 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2432 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 2, |
| 2433 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869183), |
| 2434 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2435 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2436 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:12:y, (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), 17179869183:{ *:[i64] }):$pred:12:x)<<P:12:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 2438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2439 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2440 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2441 | GIR_RootConstrainSelectedInstOperands, |
| 2442 | // GIR_Coverage, 65254, |
| 2443 | GIR_EraseRootFromParent_Done, |
| 2444 | // Label 177: @4410 |
| 2445 | GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(4505), // Rule ID 65256 // |
| 2446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2448 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:13:y |
| 2449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2450 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:13:x |
| 2451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2452 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2454 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2455 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2456 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2457 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2458 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2459 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2460 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 3, |
| 2461 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738367), |
| 2462 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2463 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2464 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:13:y, (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), 34359738367:{ *:[i64] }):$pred:13:x)<<P:13:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 2466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2468 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2469 | GIR_RootConstrainSelectedInstOperands, |
| 2470 | // GIR_Coverage, 65256, |
| 2471 | GIR_EraseRootFromParent_Done, |
| 2472 | // Label 178: @4505 |
| 2473 | GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(4600), // Rule ID 65246 // |
| 2474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2476 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:8:y |
| 2477 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2478 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:8:x |
| 2479 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2480 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2481 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2482 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2483 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2484 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2485 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2486 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2487 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2488 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 2489 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 2490 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2491 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2492 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:8:y, (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 1:{ *:[i64] }):$pred:8:x)<<P:8:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 2494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2496 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2497 | GIR_RootConstrainSelectedInstOperands, |
| 2498 | // GIR_Coverage, 65246, |
| 2499 | GIR_EraseRootFromParent_Done, |
| 2500 | // Label 179: @4600 |
| 2501 | GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(4695), // Rule ID 65248 // |
| 2502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2504 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:9:y |
| 2505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2506 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:9:x |
| 2507 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2508 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2509 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2510 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2511 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2512 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2513 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2514 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2515 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2516 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 2517 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 2518 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2519 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2520 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:9:y, (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 2:{ *:[i64] }):$pred:9:x)<<P:9:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 2522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2524 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2525 | GIR_RootConstrainSelectedInstOperands, |
| 2526 | // GIR_Coverage, 65248, |
| 2527 | GIR_EraseRootFromParent_Done, |
| 2528 | // Label 180: @4695 |
| 2529 | GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(4790), // Rule ID 65250 // |
| 2530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2532 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:10:y |
| 2533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2534 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:10:x |
| 2535 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2536 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2537 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2538 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2539 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2540 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2541 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 2542 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2543 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2544 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 2545 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 2546 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2547 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2548 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:10:y, (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 3:{ *:[i64] }):$pred:10:x)<<P:10:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 2550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 2552 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2553 | GIR_RootConstrainSelectedInstOperands, |
| 2554 | // GIR_Coverage, 65250, |
| 2555 | GIR_EraseRootFromParent_Done, |
| 2556 | // Label 181: @4790 |
| 2557 | GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(4838), // Rule ID 2715 // |
| 2558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 2559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2560 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x |
| 2561 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y |
| 2562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2563 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2564 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 2565 | // (add:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1:$pred:2:x, GPR:{ *:[i64] }:$rs2:$pred:2:y)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 2567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2568 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2569 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2570 | GIR_RootConstrainSelectedInstOperands, |
| 2571 | // GIR_Coverage, 2715, |
| 2572 | GIR_EraseRootFromParent_Done, |
| 2573 | // Label 182: @4838 |
| 2574 | GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(4886), // Rule ID 2725 // |
| 2575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 2576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2577 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x |
| 2578 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y |
| 2579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2580 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 2582 | // (add:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1:$pred:4:x, GPR:{ *:[i64] }:$rs2:$pred:4:y)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 2584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2585 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2586 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2587 | GIR_RootConstrainSelectedInstOperands, |
| 2588 | // GIR_Coverage, 2725, |
| 2589 | GIR_EraseRootFromParent_Done, |
| 2590 | // Label 183: @4886 |
| 2591 | GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(4934), // Rule ID 2735 // |
| 2592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 2593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2594 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x |
| 2595 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y |
| 2596 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2597 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 2599 | // (add:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1:$pred:6:x, GPR:{ *:[i64] }:$rs2:$pred:6:y)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 2601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2602 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2603 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2604 | GIR_RootConstrainSelectedInstOperands, |
| 2605 | // GIR_Coverage, 2735, |
| 2606 | GIR_EraseRootFromParent_Done, |
| 2607 | // Label 184: @4934 |
| 2608 | GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(4982), // Rule ID 2766 // |
| 2609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2611 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:14:x |
| 2612 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:14:y |
| 2613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2614 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_uw_op), |
| 2616 | // (add:{ *:[i64] } sh1add_uw_op:{ *:[i64] }:$rs1:$pred:14:x, GPR:{ *:[i64] }:$rs2:$pred:14:y)<<P:14:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } sh1add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 2618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2619 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2620 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2621 | GIR_RootConstrainSelectedInstOperands, |
| 2622 | // GIR_Coverage, 2766, |
| 2623 | GIR_EraseRootFromParent_Done, |
| 2624 | // Label 185: @4982 |
| 2625 | GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(5030), // Rule ID 2768 // |
| 2626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2628 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:15:x |
| 2629 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:15:y |
| 2630 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2631 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_uw_op), |
| 2633 | // (add:{ *:[i64] } sh2add_uw_op:{ *:[i64] }:$rs1:$pred:15:x, GPR:{ *:[i64] }:$rs2:$pred:15:y)<<P:15:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } sh2add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 2635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2636 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2637 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2638 | GIR_RootConstrainSelectedInstOperands, |
| 2639 | // GIR_Coverage, 2768, |
| 2640 | GIR_EraseRootFromParent_Done, |
| 2641 | // Label 186: @5030 |
| 2642 | GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(5078), // Rule ID 2770 // |
| 2643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2645 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x |
| 2646 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y |
| 2647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2648 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_uw_op), |
| 2650 | // (add:{ *:[i64] } sh3add_uw_op:{ *:[i64] }:$rs1:$pred:16:x, GPR:{ *:[i64] }:$rs2:$pred:16:y)<<P:16:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } sh3add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 2652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2653 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2654 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2655 | GIR_RootConstrainSelectedInstOperands, |
| 2656 | // GIR_Coverage, 2770, |
| 2657 | GIR_EraseRootFromParent_Done, |
| 2658 | // Label 187: @5078 |
| 2659 | GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(5129), // Rule ID 63002 // |
| 2660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 2661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2662 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:27:x |
| 2663 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:27:y |
| 2664 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2665 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 2666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 2667 | // (add:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1:$pred:27:x, GPR:{ *:[i64] }:$rs2:$pred:27:y)<<P:27:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh1add_op:{ *:[i64] }:$rs1, 1:{ *:[i64] }) |
| 2668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2670 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2671 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 2673 | GIR_RootConstrainSelectedInstOperands, |
| 2674 | // GIR_Coverage, 63002, |
| 2675 | GIR_EraseRootFromParent_Done, |
| 2676 | // Label 188: @5129 |
| 2677 | GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(5180), // Rule ID 63004 // |
| 2678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 2679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2680 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:28:x |
| 2681 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:28:y |
| 2682 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2683 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 2684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 2685 | // (add:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1:$pred:28:x, GPR:{ *:[i64] }:$rs2:$pred:28:y)<<P:28:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh2add_op:{ *:[i64] }:$rs1, 2:{ *:[i64] }) |
| 2686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2688 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2689 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 2691 | GIR_RootConstrainSelectedInstOperands, |
| 2692 | // GIR_Coverage, 63004, |
| 2693 | GIR_EraseRootFromParent_Done, |
| 2694 | // Label 189: @5180 |
| 2695 | GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(5231), // Rule ID 63006 // |
| 2696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 2697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2698 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:29:x |
| 2699 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:29:y |
| 2700 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2701 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 2702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 2703 | // (add:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1:$pred:29:x, GPR:{ *:[i64] }:$rs2:$pred:29:y)<<P:29:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh3add_op:{ *:[i64] }:$rs1, 3:{ *:[i64] }) |
| 2704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2706 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2707 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 2709 | GIR_RootConstrainSelectedInstOperands, |
| 2710 | // GIR_Coverage, 63006, |
| 2711 | GIR_EraseRootFromParent_Done, |
| 2712 | // Label 190: @5231 |
| 2713 | GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(5279), // Rule ID 65225 // |
| 2714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 2715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2716 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:2:y |
| 2717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2718 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:2:x |
| 2719 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 2721 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:2:y, sh1add_op:{ *:[i64] }:$rs1:$pred:2:x)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 2723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2724 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2725 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2726 | GIR_RootConstrainSelectedInstOperands, |
| 2727 | // GIR_Coverage, 65225, |
| 2728 | GIR_EraseRootFromParent_Done, |
| 2729 | // Label 191: @5279 |
| 2730 | GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(5327), // Rule ID 65233 // |
| 2731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 2732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2733 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y |
| 2734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2735 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x |
| 2736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 2738 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:4:y, sh2add_op:{ *:[i64] }:$rs1:$pred:4:x)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 2740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2741 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2742 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2743 | GIR_RootConstrainSelectedInstOperands, |
| 2744 | // GIR_Coverage, 65233, |
| 2745 | GIR_EraseRootFromParent_Done, |
| 2746 | // Label 192: @5327 |
| 2747 | GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(5375), // Rule ID 65241 // |
| 2748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 2749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2750 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:6:y |
| 2751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2752 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:6:x |
| 2753 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 2755 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:6:y, sh3add_op:{ *:[i64] }:$rs1:$pred:6:x)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 2757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2758 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2759 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2760 | GIR_RootConstrainSelectedInstOperands, |
| 2761 | // GIR_Coverage, 65241, |
| 2762 | GIR_EraseRootFromParent_Done, |
| 2763 | // Label 193: @5375 |
| 2764 | GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(5423), // Rule ID 65258 // |
| 2765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2767 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:14:y |
| 2768 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2769 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:14:x |
| 2770 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_uw_op), |
| 2772 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:14:y, sh1add_uw_op:{ *:[i64] }:$rs1:$pred:14:x)<<P:14:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } sh1add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 2774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2775 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2776 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2777 | GIR_RootConstrainSelectedInstOperands, |
| 2778 | // GIR_Coverage, 65258, |
| 2779 | GIR_EraseRootFromParent_Done, |
| 2780 | // Label 194: @5423 |
| 2781 | GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(5471), // Rule ID 65260 // |
| 2782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2784 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:15:y |
| 2785 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2786 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:15:x |
| 2787 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_uw_op), |
| 2789 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:15:y, sh2add_uw_op:{ *:[i64] }:$rs1:$pred:15:x)<<P:15:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } sh2add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 2791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2792 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2793 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2794 | GIR_RootConstrainSelectedInstOperands, |
| 2795 | // GIR_Coverage, 65260, |
| 2796 | GIR_EraseRootFromParent_Done, |
| 2797 | // Label 195: @5471 |
| 2798 | GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(5519), // Rule ID 65262 // |
| 2799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2801 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:16:y |
| 2802 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2803 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:16:x |
| 2804 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2805 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_uw_op), |
| 2806 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:16:y, sh3add_uw_op:{ *:[i64] }:$rs1:$pred:16:x)<<P:16:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } sh3add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 2808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2809 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2810 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2811 | GIR_RootConstrainSelectedInstOperands, |
| 2812 | // GIR_Coverage, 65262, |
| 2813 | GIR_EraseRootFromParent_Done, |
| 2814 | // Label 196: @5519 |
| 2815 | GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(5570), // Rule ID 73720 // |
| 2816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 2817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2818 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:27:y |
| 2819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2820 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:27:x |
| 2821 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 2822 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), |
| 2823 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:27:y, sh1add_op:{ *:[i64] }:$rs1:$pred:27:x)<<P:27:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh1add_op:{ *:[i64] }:$rs1, 1:{ *:[i64] }) |
| 2824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2826 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2827 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 2829 | GIR_RootConstrainSelectedInstOperands, |
| 2830 | // GIR_Coverage, 73720, |
| 2831 | GIR_EraseRootFromParent_Done, |
| 2832 | // Label 197: @5570 |
| 2833 | GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(5621), // Rule ID 73722 // |
| 2834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 2835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2836 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:28:y |
| 2837 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2838 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:28:x |
| 2839 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 2840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), |
| 2841 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:28:y, sh2add_op:{ *:[i64] }:$rs1:$pred:28:x)<<P:28:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh2add_op:{ *:[i64] }:$rs1, 2:{ *:[i64] }) |
| 2842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2844 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2845 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 2847 | GIR_RootConstrainSelectedInstOperands, |
| 2848 | // GIR_Coverage, 73722, |
| 2849 | GIR_EraseRootFromParent_Done, |
| 2850 | // Label 198: @5621 |
| 2851 | GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(5672), // Rule ID 73724 // |
| 2852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 2853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2854 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:29:y |
| 2855 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2856 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:29:x |
| 2857 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), |
| 2858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), |
| 2859 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:29:y, sh3add_op:{ *:[i64] }:$rs1:$pred:29:x)<<P:29:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh3add_op:{ *:[i64] }:$rs1, 3:{ *:[i64] }) |
| 2860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 2861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2862 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 2863 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 |
| 2864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 2865 | GIR_RootConstrainSelectedInstOperands, |
| 2866 | // GIR_Coverage, 73724, |
| 2867 | GIR_EraseRootFromParent_Done, |
| 2868 | // Label 199: @5672 |
| 2869 | GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(5747), // Rule ID 2748 // |
| 2870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2872 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x |
| 2873 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2874 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2875 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2876 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2877 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2878 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), |
| 2879 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y |
| 2880 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2881 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2882 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2883 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }):$pred:7:x, GPR:{ *:[i64] }:$rs2:$pred:7:y)<<P:7:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 2884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), |
| 2885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2887 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2888 | GIR_RootConstrainSelectedInstOperands, |
| 2889 | // GIR_Coverage, 2748, |
| 2890 | GIR_EraseRootFromParent_Done, |
| 2891 | // Label 200: @5747 |
| 2892 | GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(5842), // Rule ID 2772 // |
| 2893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2895 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x |
| 2896 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2897 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2898 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2899 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2900 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2901 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967294), |
| 2902 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y |
| 2903 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2904 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2905 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2906 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967294:{ *:[i64] }):$pred:17:x, GPR:{ *:[i64] }:$rs2:$pred:17:y)<<P:17:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 2907 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 2908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 2909 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2910 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2911 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2912 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 2914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2915 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2916 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2917 | GIR_RootConstrainSelectedInstOperands, |
| 2918 | // GIR_Coverage, 2772, |
| 2919 | GIR_EraseRootFromParent_Done, |
| 2920 | // Label 201: @5842 |
| 2921 | GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(5937), // Rule ID 2774 // |
| 2922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2924 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:18:x |
| 2925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2926 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2928 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2929 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2930 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967292), |
| 2931 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:18:y |
| 2932 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2933 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2934 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2935 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967292:{ *:[i64] }):$pred:18:x, GPR:{ *:[i64] }:$rs2:$pred:18:y)<<P:18:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 2936 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 2937 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 2938 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2939 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2940 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 2941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 2943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2944 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2945 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2946 | GIR_RootConstrainSelectedInstOperands, |
| 2947 | // GIR_Coverage, 2774, |
| 2948 | GIR_EraseRootFromParent_Done, |
| 2949 | // Label 202: @5937 |
| 2950 | GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(6032), // Rule ID 2776 // |
| 2951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2953 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x |
| 2954 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2955 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2956 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2957 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2958 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2959 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967288), |
| 2960 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y |
| 2961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2962 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2963 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2964 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967288:{ *:[i64] }):$pred:19:x, GPR:{ *:[i64] }:$rs2:$pred:19:y)<<P:19:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 2965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 2966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 2967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2968 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2969 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 2970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 2972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 2973 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2974 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 2975 | GIR_RootConstrainSelectedInstOperands, |
| 2976 | // GIR_Coverage, 2776, |
| 2977 | GIR_EraseRootFromParent_Done, |
| 2978 | // Label 203: @6032 |
| 2979 | GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(6127), // Rule ID 2778 // |
| 2980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 2981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2982 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x |
| 2983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2984 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2985 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2986 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2987 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2988 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934590), |
| 2989 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y |
| 2990 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 2991 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 2992 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2993 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 8589934590:{ *:[i64] }):$pred:20:x, GPR:{ *:[i64] }:$rs2:$pred:20:y)<<P:20:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 2994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 2995 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 2996 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2997 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 2998 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 3001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3002 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3003 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3004 | GIR_RootConstrainSelectedInstOperands, |
| 3005 | // GIR_Coverage, 2778, |
| 3006 | GIR_EraseRootFromParent_Done, |
| 3007 | // Label 204: @6127 |
| 3008 | GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(6222), // Rule ID 2780 // |
| 3009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3011 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:21:x |
| 3012 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3013 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3014 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3015 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3016 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3017 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869180), |
| 3018 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:21:y |
| 3019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3020 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3021 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3022 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 17179869180:{ *:[i64] }):$pred:21:x, GPR:{ *:[i64] }:$rs2:$pred:21:y)<<P:21:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3023 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3024 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 3025 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3026 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3027 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 3028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 3030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3031 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3032 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3033 | GIR_RootConstrainSelectedInstOperands, |
| 3034 | // GIR_Coverage, 2780, |
| 3035 | GIR_EraseRootFromParent_Done, |
| 3036 | // Label 205: @6222 |
| 3037 | GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(6317), // Rule ID 2782 // |
| 3038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3040 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:22:x |
| 3041 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3042 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3043 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3044 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3045 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3046 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738360), |
| 3047 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:22:y |
| 3048 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3049 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3050 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3051 | // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 34359738360:{ *:[i64] }):$pred:22:x, GPR:{ *:[i64] }:$rs2:$pred:22:y)<<P:22:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3052 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3053 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 3054 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3055 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3056 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 3057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 3059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3060 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3061 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3062 | GIR_RootConstrainSelectedInstOperands, |
| 3063 | // GIR_Coverage, 2782, |
| 3064 | GIR_EraseRootFromParent_Done, |
| 3065 | // Label 206: @6317 |
| 3066 | GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(6385), // Rule ID 2709 // |
| 3067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 3068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3069 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x |
| 3070 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3071 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3072 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3073 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3074 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3075 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 3076 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y |
| 3077 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3078 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3079 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3080 | // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }):$pred:1:x, GPR:{ *:[i64] }:$rs2:$pred:1:y)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 3082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3084 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3085 | GIR_RootConstrainSelectedInstOperands, |
| 3086 | // GIR_Coverage, 2709, |
| 3087 | GIR_EraseRootFromParent_Done, |
| 3088 | // Label 207: @6385 |
| 3089 | GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(6453), // Rule ID 2719 // |
| 3090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 3091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3092 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x |
| 3093 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3094 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3095 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3096 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3097 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3098 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 3099 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y |
| 3100 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3101 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3102 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3103 | // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }):$pred:3:x, GPR:{ *:[i64] }:$rs2:$pred:3:y)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 3105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3107 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3108 | GIR_RootConstrainSelectedInstOperands, |
| 3109 | // GIR_Coverage, 2719, |
| 3110 | GIR_EraseRootFromParent_Done, |
| 3111 | // Label 208: @6453 |
| 3112 | GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(6521), // Rule ID 2729 // |
| 3113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 3114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3115 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x |
| 3116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3117 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3119 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3120 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3121 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 3122 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y |
| 3123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3124 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3125 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3126 | // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }):$pred:5:x, GPR:{ *:[i64] }:$rs2:$pred:5:y)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 3128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3130 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3131 | GIR_RootConstrainSelectedInstOperands, |
| 3132 | // GIR_Coverage, 2729, |
| 3133 | GIR_EraseRootFromParent_Done, |
| 3134 | // Label 209: @6521 |
| 3135 | GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(6596), // Rule ID 65244 // |
| 3136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3138 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:7:y |
| 3139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3140 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:7:x |
| 3141 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3142 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3143 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3144 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3145 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3146 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), |
| 3147 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3148 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3149 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:7:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }):$pred:7:x)<<P:7:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), |
| 3151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3153 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3154 | GIR_RootConstrainSelectedInstOperands, |
| 3155 | // GIR_Coverage, 65244, |
| 3156 | GIR_EraseRootFromParent_Done, |
| 3157 | // Label 210: @6596 |
| 3158 | GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(6691), // Rule ID 65264 // |
| 3159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3161 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:17:y |
| 3162 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3163 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:17:x |
| 3164 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3165 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3166 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3167 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3168 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3169 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967294), |
| 3170 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3171 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3172 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:17:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967294:{ *:[i64] }):$pred:17:x)<<P:17:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3173 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3174 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 3175 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3176 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3177 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 3178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 3180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3181 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3182 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3183 | GIR_RootConstrainSelectedInstOperands, |
| 3184 | // GIR_Coverage, 65264, |
| 3185 | GIR_EraseRootFromParent_Done, |
| 3186 | // Label 211: @6691 |
| 3187 | GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(6786), // Rule ID 65266 // |
| 3188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3190 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:18:y |
| 3191 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3192 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:18:x |
| 3193 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3194 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3195 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3196 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3197 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3198 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967292), |
| 3199 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3200 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3201 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:18:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967292:{ *:[i64] }):$pred:18:x)<<P:18:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 3204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3205 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3206 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 3207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 3209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3210 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3211 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3212 | GIR_RootConstrainSelectedInstOperands, |
| 3213 | // GIR_Coverage, 65266, |
| 3214 | GIR_EraseRootFromParent_Done, |
| 3215 | // Label 212: @6786 |
| 3216 | GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(6881), // Rule ID 65268 // |
| 3217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3219 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:19:y |
| 3220 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3221 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:19:x |
| 3222 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3223 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3224 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3225 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3226 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3227 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967288), |
| 3228 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3229 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3230 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:19:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967288:{ *:[i64] }):$pred:19:x)<<P:19:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3231 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3232 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 3233 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3235 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 3236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 3238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3239 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3240 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3241 | GIR_RootConstrainSelectedInstOperands, |
| 3242 | // GIR_Coverage, 65268, |
| 3243 | GIR_EraseRootFromParent_Done, |
| 3244 | // Label 213: @6881 |
| 3245 | GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(6976), // Rule ID 65270 // |
| 3246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3248 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:20:y |
| 3249 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3250 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:20:x |
| 3251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3252 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3253 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3254 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3255 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3256 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934590), |
| 3257 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3258 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3259 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:20:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 8589934590:{ *:[i64] }):$pred:20:x)<<P:20:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3260 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3261 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 3262 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3263 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3264 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 3265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), |
| 3267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3268 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3270 | GIR_RootConstrainSelectedInstOperands, |
| 3271 | // GIR_Coverage, 65270, |
| 3272 | GIR_EraseRootFromParent_Done, |
| 3273 | // Label 214: @6976 |
| 3274 | GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(7071), // Rule ID 65272 // |
| 3275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3277 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:21:y |
| 3278 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3279 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:21:x |
| 3280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3281 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3282 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3283 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3284 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3285 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869180), |
| 3286 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3287 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3288 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:21:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 17179869180:{ *:[i64] }):$pred:21:x)<<P:21:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3289 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3290 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 3291 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3292 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3293 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 3294 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), |
| 3296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3298 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3299 | GIR_RootConstrainSelectedInstOperands, |
| 3300 | // GIR_Coverage, 65272, |
| 3301 | GIR_EraseRootFromParent_Done, |
| 3302 | // Label 215: @7071 |
| 3303 | GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(7166), // Rule ID 65274 // |
| 3304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3306 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:22:y |
| 3307 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3308 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:22:x |
| 3309 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3310 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 3311 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3312 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3313 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3314 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738360), |
| 3315 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3316 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3317 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:22:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 34359738360:{ *:[i64] }):$pred:22:x)<<P:22:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) |
| 3318 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3319 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 3320 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3321 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3322 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 3323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), |
| 3325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3326 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3327 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3328 | GIR_RootConstrainSelectedInstOperands, |
| 3329 | // GIR_Coverage, 65274, |
| 3330 | GIR_EraseRootFromParent_Done, |
| 3331 | // Label 216: @7166 |
| 3332 | GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(7234), // Rule ID 65221 // |
| 3333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 3334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3335 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y |
| 3336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3337 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:1:x |
| 3338 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3339 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3340 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3341 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3342 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3343 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 3344 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3345 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3346 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:1:y, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }):$pred:1:x)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), |
| 3348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3350 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3351 | GIR_RootConstrainSelectedInstOperands, |
| 3352 | // GIR_Coverage, 65221, |
| 3353 | GIR_EraseRootFromParent_Done, |
| 3354 | // Label 217: @7234 |
| 3355 | GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(7302), // Rule ID 65229 // |
| 3356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 3357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3358 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:3:y |
| 3359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3360 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:3:x |
| 3361 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3362 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3363 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3364 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3365 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3366 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 3367 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3368 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3369 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:3:y, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }):$pred:3:x)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), |
| 3371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3373 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3374 | GIR_RootConstrainSelectedInstOperands, |
| 3375 | // GIR_Coverage, 65229, |
| 3376 | GIR_EraseRootFromParent_Done, |
| 3377 | // Label 218: @7302 |
| 3378 | GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(7370), // Rule ID 65237 // |
| 3379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), |
| 3380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3381 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y |
| 3382 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3383 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:5:x |
| 3384 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3385 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3386 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3387 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3388 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3389 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 3390 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3391 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3392 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:5:y, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }):$pred:5:x)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), |
| 3394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3396 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3397 | GIR_RootConstrainSelectedInstOperands, |
| 3398 | // GIR_Coverage, 65237, |
| 3399 | GIR_EraseRootFromParent_Done, |
| 3400 | // Label 219: @7370 |
| 3401 | GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(7437), // Rule ID 73718 // |
| 3402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 3403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3404 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3405 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3406 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3407 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3408 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3409 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3410 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3411 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), |
| 3412 | // MIs[2] Operand 1 |
| 3413 | // No operand predicates |
| 3414 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3415 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3416 | // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2), GPR:{ *:[i64] }:$rs1) => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2) |
| 3417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 3418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3419 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 3420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 3421 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 |
| 3422 | GIR_RootConstrainSelectedInstOperands, |
| 3423 | // GIR_Coverage, 73718, |
| 3424 | GIR_EraseRootFromParent_Done, |
| 3425 | // Label 220: @7437 |
| 3426 | GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(7504), // Rule ID 62998 // |
| 3427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), |
| 3428 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3429 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3430 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3431 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3432 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3433 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3434 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3435 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3436 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3437 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), |
| 3438 | // MIs[2] Operand 1 |
| 3439 | // No operand predicates |
| 3440 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3441 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2)) => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2) |
| 3442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), |
| 3443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3444 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 3446 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 |
| 3447 | GIR_RootConstrainSelectedInstOperands, |
| 3448 | // GIR_Coverage, 62998, |
| 3449 | GIR_EraseRootFromParent_Done, |
| 3450 | // Label 221: @7504 |
| 3451 | GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(7564), // Rule ID 2828 // |
| 3452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3454 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:23:x |
| 3455 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3456 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3457 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3458 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3459 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:23:y |
| 3460 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3461 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3462 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3463 | // (add:{ *:[i64] } (zext:{ *:[i64] } GPR:{ *:[i32] }:$rs1):$pred:23:x, GPR:{ *:[i64] }:$rs2:$pred:23:y)<<P:23:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), |
| 3465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3467 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3468 | GIR_RootConstrainSelectedInstOperands, |
| 3469 | // GIR_Coverage, 2828, |
| 3470 | GIR_EraseRootFromParent_Done, |
| 3471 | // Label 222: @7564 |
| 3472 | GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(7624), // Rule ID 65291 // |
| 3473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 3474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3475 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:23:y |
| 3476 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3477 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:23:x |
| 3478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3479 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3480 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3481 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3482 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), |
| 3483 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3484 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:23:y, (zext:{ *:[i64] } GPR:{ *:[i32] }:$rs1):$pred:23:x)<<P:23:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), |
| 3486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3488 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 3489 | GIR_RootConstrainSelectedInstOperands, |
| 3490 | // GIR_Coverage, 65291, |
| 3491 | GIR_EraseRootFromParent_Done, |
| 3492 | // Label 223: @7624 |
| 3493 | GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(7666), // Rule ID 68 // |
| 3494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 3495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3496 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3497 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3498 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3499 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 3500 | // MIs[1] Operand 1 |
| 3501 | // No operand predicates |
| 3502 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3503 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) => (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) |
| 3504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 3505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3506 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3507 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 3508 | GIR_RootConstrainSelectedInstOperands, |
| 3509 | // GIR_Coverage, 68, |
| 3510 | GIR_EraseRootFromParent_Done, |
| 3511 | // Label 224: @7666 |
| 3512 | GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(7727), // Rule ID 73726 // |
| 3513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode0), |
| 3514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3516 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3517 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3518 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3519 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3520 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3522 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3523 | // (add:{ *:[i64] } (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i64] }:$rd) => (TH_MULA:{ *:[i64] } GPR:{ *:[i64] }:$rd, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), |
| 3525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 3526 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 3527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 3529 | GIR_RootConstrainSelectedInstOperands, |
| 3530 | // GIR_Coverage, 73726, |
| 3531 | GIR_EraseRootFromParent_Done, |
| 3532 | // Label 225: @7727 |
| 3533 | GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(7788), // Rule ID 63058 // |
| 3534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode0), |
| 3535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3537 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3538 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3539 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3540 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 3541 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3542 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3543 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3544 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rd, (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) => (TH_MULA:{ *:[i64] } GPR:{ *:[i64] }:$rd, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), |
| 3546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 3547 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 3548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 3549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 3550 | GIR_RootConstrainSelectedInstOperands, |
| 3551 | // GIR_Coverage, 63058, |
| 3552 | GIR_EraseRootFromParent_Done, |
| 3553 | // Label 226: @7788 |
| 3554 | GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(7815), // Rule ID 66 // |
| 3555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 3556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3558 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 3559 | // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 3560 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADD), |
| 3561 | GIR_RootConstrainSelectedInstOperands, |
| 3562 | // GIR_Coverage, 66, |
| 3563 | GIR_Done, |
| 3564 | // Label 227: @7815 |
| 3565 | GIM_Reject, |
| 3566 | // Label 169: @7816 |
| 3567 | GIM_Reject, |
| 3568 | // Label 102: @7817 |
| 3569 | GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(7931), |
| 3570 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 3571 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 3572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3574 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3575 | GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(7885), // Rule ID 46578 // |
| 3576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3577 | // (add:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVADD_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 3578 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 3579 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3580 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF8), |
| 3583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3585 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3586 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3590 | GIR_RootConstrainSelectedInstOperands, |
| 3591 | // GIR_Coverage, 46578, |
| 3592 | GIR_EraseRootFromParent_Done, |
| 3593 | // Label 229: @7885 |
| 3594 | GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(7930), // Rule ID 46579 // |
| 3595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3596 | // (add:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVADD_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 3597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 3598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3600 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF8), |
| 3602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3604 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3605 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3609 | GIR_RootConstrainSelectedInstOperands, |
| 3610 | // GIR_Coverage, 46579, |
| 3611 | GIR_EraseRootFromParent_Done, |
| 3612 | // Label 230: @7930 |
| 3613 | GIM_Reject, |
| 3614 | // Label 228: @7931 |
| 3615 | GIM_Reject, |
| 3616 | // Label 103: @7932 |
| 3617 | GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(8046), |
| 3618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 3619 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 3620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3621 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3622 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3623 | GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(8000), // Rule ID 46958 // |
| 3624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3625 | // (add:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 3626 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 3627 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3628 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), |
| 3631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3632 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3633 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3634 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 3637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3638 | GIR_RootConstrainSelectedInstOperands, |
| 3639 | // GIR_Coverage, 46958, |
| 3640 | GIR_EraseRootFromParent_Done, |
| 3641 | // Label 232: @8000 |
| 3642 | GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(8045), // Rule ID 46959 // |
| 3643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3644 | // (add:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 3645 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 3646 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3647 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3648 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), |
| 3650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3651 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3652 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3653 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 3656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3657 | GIR_RootConstrainSelectedInstOperands, |
| 3658 | // GIR_Coverage, 46959, |
| 3659 | GIR_EraseRootFromParent_Done, |
| 3660 | // Label 233: @8045 |
| 3661 | GIM_Reject, |
| 3662 | // Label 231: @8046 |
| 3663 | GIM_Reject, |
| 3664 | // Label 104: @8047 |
| 3665 | GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(8161), |
| 3666 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 3667 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 3668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3669 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3670 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3671 | GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(8115), // Rule ID 46966 // |
| 3672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3673 | // (add:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 3674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 3675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3677 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), |
| 3679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3680 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3681 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3682 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 3685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3686 | GIR_RootConstrainSelectedInstOperands, |
| 3687 | // GIR_Coverage, 46966, |
| 3688 | GIR_EraseRootFromParent_Done, |
| 3689 | // Label 235: @8115 |
| 3690 | GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(8160), // Rule ID 46967 // |
| 3691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3692 | // (add:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 3693 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 3694 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3695 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), |
| 3698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3699 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3700 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3701 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 3704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3705 | GIR_RootConstrainSelectedInstOperands, |
| 3706 | // GIR_Coverage, 46967, |
| 3707 | GIR_EraseRootFromParent_Done, |
| 3708 | // Label 236: @8160 |
| 3709 | GIM_Reject, |
| 3710 | // Label 234: @8161 |
| 3711 | GIM_Reject, |
| 3712 | // Label 105: @8162 |
| 3713 | GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(8276), |
| 3714 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 3715 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 3716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3718 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3719 | GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(8230), // Rule ID 46982 // |
| 3720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 3721 | // (add:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 3722 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 3723 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3724 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3725 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 3727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3728 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3729 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3730 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 3733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3734 | GIR_RootConstrainSelectedInstOperands, |
| 3735 | // GIR_Coverage, 46982, |
| 3736 | GIR_EraseRootFromParent_Done, |
| 3737 | // Label 238: @8230 |
| 3738 | GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(8275), // Rule ID 46983 // |
| 3739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 3740 | // (add:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 3741 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 3742 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3743 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 3746 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3747 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3748 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3749 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 3752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3753 | GIR_RootConstrainSelectedInstOperands, |
| 3754 | // GIR_Coverage, 46983, |
| 3755 | GIR_EraseRootFromParent_Done, |
| 3756 | // Label 239: @8275 |
| 3757 | GIM_Reject, |
| 3758 | // Label 237: @8276 |
| 3759 | GIM_Reject, |
| 3760 | // Label 106: @8277 |
| 3761 | GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8391), |
| 3762 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 3763 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 3764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3765 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3766 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3767 | GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(8345), // Rule ID 46950 // |
| 3768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3769 | // (add:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 3770 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 3771 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3772 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3773 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), |
| 3775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3776 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3777 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3778 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3782 | GIR_RootConstrainSelectedInstOperands, |
| 3783 | // GIR_Coverage, 46950, |
| 3784 | GIR_EraseRootFromParent_Done, |
| 3785 | // Label 241: @8345 |
| 3786 | GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(8390), // Rule ID 46951 // |
| 3787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3788 | // (add:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 3789 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 3790 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3791 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3792 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), |
| 3794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3795 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3796 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3797 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3801 | GIR_RootConstrainSelectedInstOperands, |
| 3802 | // GIR_Coverage, 46951, |
| 3803 | GIR_EraseRootFromParent_Done, |
| 3804 | // Label 242: @8390 |
| 3805 | GIM_Reject, |
| 3806 | // Label 240: @8391 |
| 3807 | GIM_Reject, |
| 3808 | // Label 107: @8392 |
| 3809 | GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(8506), |
| 3810 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 3811 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 3812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3813 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3814 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3815 | GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(8460), // Rule ID 46962 // |
| 3816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3817 | // (add:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 3818 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 3819 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3820 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3821 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), |
| 3823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3824 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3825 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3826 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 3829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3830 | GIR_RootConstrainSelectedInstOperands, |
| 3831 | // GIR_Coverage, 46962, |
| 3832 | GIR_EraseRootFromParent_Done, |
| 3833 | // Label 244: @8460 |
| 3834 | GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(8505), // Rule ID 46963 // |
| 3835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3836 | // (add:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 3837 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 3838 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3839 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), |
| 3842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3843 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3844 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3845 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 3848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3849 | GIR_RootConstrainSelectedInstOperands, |
| 3850 | // GIR_Coverage, 46963, |
| 3851 | GIR_EraseRootFromParent_Done, |
| 3852 | // Label 245: @8505 |
| 3853 | GIM_Reject, |
| 3854 | // Label 243: @8506 |
| 3855 | GIM_Reject, |
| 3856 | // Label 108: @8507 |
| 3857 | GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(8621), |
| 3858 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 3859 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 3860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3862 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3863 | GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(8575), // Rule ID 46978 // |
| 3864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3865 | // (add:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 3866 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 3867 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3868 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3869 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 3871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3872 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3873 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3874 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 3877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3878 | GIR_RootConstrainSelectedInstOperands, |
| 3879 | // GIR_Coverage, 46978, |
| 3880 | GIR_EraseRootFromParent_Done, |
| 3881 | // Label 247: @8575 |
| 3882 | GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(8620), // Rule ID 46979 // |
| 3883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3884 | // (add:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 3885 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 3886 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3887 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 3890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3891 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3892 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3893 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 3896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3897 | GIR_RootConstrainSelectedInstOperands, |
| 3898 | // GIR_Coverage, 46979, |
| 3899 | GIR_EraseRootFromParent_Done, |
| 3900 | // Label 248: @8620 |
| 3901 | GIM_Reject, |
| 3902 | // Label 246: @8621 |
| 3903 | GIM_Reject, |
| 3904 | // Label 109: @8622 |
| 3905 | GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(8736), |
| 3906 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 3907 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 3908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 3909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 3910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 3911 | GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(8690), // Rule ID 47022 // |
| 3912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 3913 | // (add:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 3914 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 3915 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3916 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 3919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3920 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3921 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3922 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 3925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3926 | GIR_RootConstrainSelectedInstOperands, |
| 3927 | // GIR_Coverage, 47022, |
| 3928 | GIR_EraseRootFromParent_Done, |
| 3929 | // Label 250: @8690 |
| 3930 | GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(8735), // Rule ID 47023 // |
| 3931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 3932 | // (add:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 3933 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 3934 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3935 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3936 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 3938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3940 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3941 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 3944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3945 | GIR_RootConstrainSelectedInstOperands, |
| 3946 | // GIR_Coverage, 47023, |
| 3947 | GIR_EraseRootFromParent_Done, |
| 3948 | // Label 251: @8735 |
| 3949 | GIM_Reject, |
| 3950 | // Label 249: @8736 |
| 3951 | GIM_Reject, |
| 3952 | // Label 110: @8737 |
| 3953 | GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(8851), |
| 3954 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 3955 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 3956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3957 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3958 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 3959 | GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(8805), // Rule ID 46954 // |
| 3960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 3961 | // (add:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 3962 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 3963 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3964 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), |
| 3967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3968 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3969 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3970 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3974 | GIR_RootConstrainSelectedInstOperands, |
| 3975 | // GIR_Coverage, 46954, |
| 3976 | GIR_EraseRootFromParent_Done, |
| 3977 | // Label 253: @8805 |
| 3978 | GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(8850), // Rule ID 46955 // |
| 3979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 3980 | // (add:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 3981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 3982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), |
| 3986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 3987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3988 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 3989 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 3990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 3991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 3993 | GIR_RootConstrainSelectedInstOperands, |
| 3994 | // GIR_Coverage, 46955, |
| 3995 | GIR_EraseRootFromParent_Done, |
| 3996 | // Label 254: @8850 |
| 3997 | GIM_Reject, |
| 3998 | // Label 252: @8851 |
| 3999 | GIM_Reject, |
| 4000 | // Label 111: @8852 |
| 4001 | GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(8966), |
| 4002 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 4003 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 4004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4005 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4006 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4007 | GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(8920), // Rule ID 46974 // |
| 4008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4009 | // (add:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 4010 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 4011 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4012 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 4015 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4016 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4017 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4018 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4022 | GIR_RootConstrainSelectedInstOperands, |
| 4023 | // GIR_Coverage, 46974, |
| 4024 | GIR_EraseRootFromParent_Done, |
| 4025 | // Label 256: @8920 |
| 4026 | GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(8965), // Rule ID 46975 // |
| 4027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4028 | // (add:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 4029 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 4030 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4031 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4032 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 4034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4035 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4036 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4037 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4041 | GIR_RootConstrainSelectedInstOperands, |
| 4042 | // GIR_Coverage, 46975, |
| 4043 | GIR_EraseRootFromParent_Done, |
| 4044 | // Label 257: @8965 |
| 4045 | GIM_Reject, |
| 4046 | // Label 255: @8966 |
| 4047 | GIM_Reject, |
| 4048 | // Label 112: @8967 |
| 4049 | GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(9081), |
| 4050 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 4051 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 4052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4053 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4054 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4055 | GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(9035), // Rule ID 47010 // |
| 4056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4057 | // (add:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 4058 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 4059 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4060 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 4063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4064 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4065 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4066 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4070 | GIR_RootConstrainSelectedInstOperands, |
| 4071 | // GIR_Coverage, 47010, |
| 4072 | GIR_EraseRootFromParent_Done, |
| 4073 | // Label 259: @9035 |
| 4074 | GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(9080), // Rule ID 47011 // |
| 4075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4076 | // (add:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 4077 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 4078 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4079 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 4082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4083 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4084 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4085 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4089 | GIR_RootConstrainSelectedInstOperands, |
| 4090 | // GIR_Coverage, 47011, |
| 4091 | GIR_EraseRootFromParent_Done, |
| 4092 | // Label 260: @9080 |
| 4093 | GIM_Reject, |
| 4094 | // Label 258: @9081 |
| 4095 | GIM_Reject, |
| 4096 | // Label 113: @9082 |
| 4097 | GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(9196), |
| 4098 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 4099 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 4100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4101 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4102 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4103 | GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(9150), // Rule ID 47026 // |
| 4104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 4105 | // (add:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 4106 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 4107 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4108 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4112 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4113 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4114 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 4117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4118 | GIR_RootConstrainSelectedInstOperands, |
| 4119 | // GIR_Coverage, 47026, |
| 4120 | GIR_EraseRootFromParent_Done, |
| 4121 | // Label 262: @9150 |
| 4122 | GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(9195), // Rule ID 47027 // |
| 4123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 4124 | // (add:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 4125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 4126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4133 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 4136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4137 | GIR_RootConstrainSelectedInstOperands, |
| 4138 | // GIR_Coverage, 47027, |
| 4139 | GIR_EraseRootFromParent_Done, |
| 4140 | // Label 263: @9195 |
| 4141 | GIM_Reject, |
| 4142 | // Label 261: @9196 |
| 4143 | GIM_Reject, |
| 4144 | // Label 114: @9197 |
| 4145 | GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(9311), |
| 4146 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 4147 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 4148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4150 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4151 | GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(9265), // Rule ID 46970 // |
| 4152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4153 | // (add:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 4154 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 4155 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4156 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 4159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4160 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4161 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4162 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4166 | GIR_RootConstrainSelectedInstOperands, |
| 4167 | // GIR_Coverage, 46970, |
| 4168 | GIR_EraseRootFromParent_Done, |
| 4169 | // Label 265: @9265 |
| 4170 | GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(9310), // Rule ID 46971 // |
| 4171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4172 | // (add:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 4173 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 4174 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4175 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), |
| 4178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4179 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4180 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4181 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4185 | GIR_RootConstrainSelectedInstOperands, |
| 4186 | // GIR_Coverage, 46971, |
| 4187 | GIR_EraseRootFromParent_Done, |
| 4188 | // Label 266: @9310 |
| 4189 | GIM_Reject, |
| 4190 | // Label 264: @9311 |
| 4191 | GIM_Reject, |
| 4192 | // Label 115: @9312 |
| 4193 | GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(9426), |
| 4194 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 4195 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 4196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4198 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4199 | GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(9380), // Rule ID 46998 // |
| 4200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4201 | // (add:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 4202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 4203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 4207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4208 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4209 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4210 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4214 | GIR_RootConstrainSelectedInstOperands, |
| 4215 | // GIR_Coverage, 46998, |
| 4216 | GIR_EraseRootFromParent_Done, |
| 4217 | // Label 268: @9380 |
| 4218 | GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(9425), // Rule ID 46999 // |
| 4219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4220 | // (add:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 4221 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 4222 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4223 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 4226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4227 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4228 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4229 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4233 | GIR_RootConstrainSelectedInstOperands, |
| 4234 | // GIR_Coverage, 46999, |
| 4235 | GIR_EraseRootFromParent_Done, |
| 4236 | // Label 269: @9425 |
| 4237 | GIM_Reject, |
| 4238 | // Label 267: @9426 |
| 4239 | GIM_Reject, |
| 4240 | // Label 116: @9427 |
| 4241 | GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(9541), |
| 4242 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 4243 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 4244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4245 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4246 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4247 | GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(9495), // Rule ID 47014 // |
| 4248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4249 | // (add:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 4250 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 4251 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4252 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4256 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4257 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4258 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4262 | GIR_RootConstrainSelectedInstOperands, |
| 4263 | // GIR_Coverage, 47014, |
| 4264 | GIR_EraseRootFromParent_Done, |
| 4265 | // Label 271: @9495 |
| 4266 | GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(9540), // Rule ID 47015 // |
| 4267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4268 | // (add:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 4269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 4270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4276 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4277 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4281 | GIR_RootConstrainSelectedInstOperands, |
| 4282 | // GIR_Coverage, 47015, |
| 4283 | GIR_EraseRootFromParent_Done, |
| 4284 | // Label 272: @9540 |
| 4285 | GIM_Reject, |
| 4286 | // Label 270: @9541 |
| 4287 | GIM_Reject, |
| 4288 | // Label 117: @9542 |
| 4289 | GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(9656), |
| 4290 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 4291 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 4292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4293 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4294 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4295 | GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(9610), // Rule ID 47030 // |
| 4296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 4297 | // (add:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 4298 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 4299 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4300 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4304 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4305 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4306 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 4309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4310 | GIR_RootConstrainSelectedInstOperands, |
| 4311 | // GIR_Coverage, 47030, |
| 4312 | GIR_EraseRootFromParent_Done, |
| 4313 | // Label 274: @9610 |
| 4314 | GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(9655), // Rule ID 47031 // |
| 4315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 4316 | // (add:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 4317 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 4318 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4319 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4320 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4323 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4324 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4325 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 4328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4329 | GIR_RootConstrainSelectedInstOperands, |
| 4330 | // GIR_Coverage, 47031, |
| 4331 | GIR_EraseRootFromParent_Done, |
| 4332 | // Label 275: @9655 |
| 4333 | GIM_Reject, |
| 4334 | // Label 273: @9656 |
| 4335 | GIM_Reject, |
| 4336 | // Label 118: @9657 |
| 4337 | GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(9771), |
| 4338 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 4339 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 4340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4341 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4342 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 4343 | GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(9725), // Rule ID 46986 // |
| 4344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4345 | // (add:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 4346 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 4347 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4348 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4349 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 4351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4352 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4353 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4354 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4358 | GIR_RootConstrainSelectedInstOperands, |
| 4359 | // GIR_Coverage, 46986, |
| 4360 | GIR_EraseRootFromParent_Done, |
| 4361 | // Label 277: @9725 |
| 4362 | GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(9770), // Rule ID 46987 // |
| 4363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4364 | // (add:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 4365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 4366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), |
| 4370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4371 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4372 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4373 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4377 | GIR_RootConstrainSelectedInstOperands, |
| 4378 | // GIR_Coverage, 46987, |
| 4379 | GIR_EraseRootFromParent_Done, |
| 4380 | // Label 278: @9770 |
| 4381 | GIM_Reject, |
| 4382 | // Label 276: @9771 |
| 4383 | GIM_Reject, |
| 4384 | // Label 119: @9772 |
| 4385 | GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(9886), |
| 4386 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 4387 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 4388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4389 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4390 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4391 | GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(9840), // Rule ID 47002 // |
| 4392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4393 | // (add:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 4394 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 4395 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4396 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4400 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4401 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4402 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4406 | GIR_RootConstrainSelectedInstOperands, |
| 4407 | // GIR_Coverage, 47002, |
| 4408 | GIR_EraseRootFromParent_Done, |
| 4409 | // Label 280: @9840 |
| 4410 | GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(9885), // Rule ID 47003 // |
| 4411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4412 | // (add:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 4413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 4414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4415 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4419 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4420 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4421 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4425 | GIR_RootConstrainSelectedInstOperands, |
| 4426 | // GIR_Coverage, 47003, |
| 4427 | GIR_EraseRootFromParent_Done, |
| 4428 | // Label 281: @9885 |
| 4429 | GIM_Reject, |
| 4430 | // Label 279: @9886 |
| 4431 | GIM_Reject, |
| 4432 | // Label 120: @9887 |
| 4433 | GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(10001), |
| 4434 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 4435 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 4436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4437 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4438 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4439 | GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(9955), // Rule ID 47018 // |
| 4440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4441 | // (add:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 4442 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 4443 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4444 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4448 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4449 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4450 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4454 | GIR_RootConstrainSelectedInstOperands, |
| 4455 | // GIR_Coverage, 47018, |
| 4456 | GIR_EraseRootFromParent_Done, |
| 4457 | // Label 283: @9955 |
| 4458 | GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(10000), // Rule ID 47019 // |
| 4459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4460 | // (add:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 4461 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 4462 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4463 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4467 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4468 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4469 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4473 | GIR_RootConstrainSelectedInstOperands, |
| 4474 | // GIR_Coverage, 47019, |
| 4475 | GIR_EraseRootFromParent_Done, |
| 4476 | // Label 284: @10000 |
| 4477 | GIM_Reject, |
| 4478 | // Label 282: @10001 |
| 4479 | GIM_Reject, |
| 4480 | // Label 121: @10002 |
| 4481 | GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(10116), |
| 4482 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 4483 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 4484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4486 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 4487 | GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(10070), // Rule ID 46990 // |
| 4488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4489 | // (add:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 4490 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 4491 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4492 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4493 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4496 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4497 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4498 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4502 | GIR_RootConstrainSelectedInstOperands, |
| 4503 | // GIR_Coverage, 46990, |
| 4504 | GIR_EraseRootFromParent_Done, |
| 4505 | // Label 286: @10070 |
| 4506 | GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(10115), // Rule ID 46991 // |
| 4507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4508 | // (add:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 4509 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 4510 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4511 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), |
| 4514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4515 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4516 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4517 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4521 | GIR_RootConstrainSelectedInstOperands, |
| 4522 | // GIR_Coverage, 46991, |
| 4523 | GIR_EraseRootFromParent_Done, |
| 4524 | // Label 287: @10115 |
| 4525 | GIM_Reject, |
| 4526 | // Label 285: @10116 |
| 4527 | GIM_Reject, |
| 4528 | // Label 122: @10117 |
| 4529 | GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(10231), |
| 4530 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 4531 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 4532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4534 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4535 | GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(10185), // Rule ID 47006 // |
| 4536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4537 | // (add:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 4538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 4539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4545 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4546 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4550 | GIR_RootConstrainSelectedInstOperands, |
| 4551 | // GIR_Coverage, 47006, |
| 4552 | GIR_EraseRootFromParent_Done, |
| 4553 | // Label 289: @10185 |
| 4554 | GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(10230), // Rule ID 47007 // |
| 4555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4556 | // (add:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 4557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 4558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4564 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4565 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4569 | GIR_RootConstrainSelectedInstOperands, |
| 4570 | // GIR_Coverage, 47007, |
| 4571 | GIR_EraseRootFromParent_Done, |
| 4572 | // Label 290: @10230 |
| 4573 | GIM_Reject, |
| 4574 | // Label 288: @10231 |
| 4575 | GIM_Reject, |
| 4576 | // Label 123: @10232 |
| 4577 | GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(10346), |
| 4578 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 4579 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 4580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4582 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 4583 | GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(10300), // Rule ID 46994 // |
| 4584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4585 | // (add:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 4586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 4587 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4588 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4589 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4592 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4593 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4594 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4598 | GIR_RootConstrainSelectedInstOperands, |
| 4599 | // GIR_Coverage, 46994, |
| 4600 | GIR_EraseRootFromParent_Done, |
| 4601 | // Label 292: @10300 |
| 4602 | GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(10345), // Rule ID 46995 // |
| 4603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4604 | // (add:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 4605 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 4606 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4607 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4608 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), |
| 4610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4612 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4613 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4617 | GIR_RootConstrainSelectedInstOperands, |
| 4618 | // GIR_Coverage, 46995, |
| 4619 | GIR_EraseRootFromParent_Done, |
| 4620 | // Label 293: @10345 |
| 4621 | GIM_Reject, |
| 4622 | // Label 291: @10346 |
| 4623 | GIM_Reject, |
| 4624 | // Label 124: @10347 |
| 4625 | GIM_Reject, |
| 4626 | // Label 1: @10348 |
| 4627 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 318*/ GIMT_Encode4(13451), |
| 4628 | /*GILLT_s32*//*Label 294*/ GIMT_Encode4(10483), |
| 4629 | /*GILLT_s64*//*Label 295*/ GIMT_Encode4(10792), GIMT_Encode4(0), |
| 4630 | /*GILLT_nxv1s8*//*Label 296*/ GIMT_Encode4(10921), |
| 4631 | /*GILLT_nxv1s16*//*Label 297*/ GIMT_Encode4(11036), |
| 4632 | /*GILLT_nxv1s32*//*Label 298*/ GIMT_Encode4(11151), |
| 4633 | /*GILLT_nxv1s64*//*Label 299*/ GIMT_Encode4(11266), GIMT_Encode4(0), |
| 4634 | /*GILLT_nxv2s8*//*Label 300*/ GIMT_Encode4(11381), |
| 4635 | /*GILLT_nxv2s16*//*Label 301*/ GIMT_Encode4(11496), |
| 4636 | /*GILLT_nxv2s32*//*Label 302*/ GIMT_Encode4(11611), |
| 4637 | /*GILLT_nxv2s64*//*Label 303*/ GIMT_Encode4(11726), GIMT_Encode4(0), |
| 4638 | /*GILLT_nxv4s8*//*Label 304*/ GIMT_Encode4(11841), |
| 4639 | /*GILLT_nxv4s16*//*Label 305*/ GIMT_Encode4(11956), |
| 4640 | /*GILLT_nxv4s32*//*Label 306*/ GIMT_Encode4(12071), |
| 4641 | /*GILLT_nxv4s64*//*Label 307*/ GIMT_Encode4(12186), GIMT_Encode4(0), |
| 4642 | /*GILLT_nxv8s8*//*Label 308*/ GIMT_Encode4(12301), |
| 4643 | /*GILLT_nxv8s16*//*Label 309*/ GIMT_Encode4(12416), |
| 4644 | /*GILLT_nxv8s32*//*Label 310*/ GIMT_Encode4(12531), |
| 4645 | /*GILLT_nxv8s64*//*Label 311*/ GIMT_Encode4(12646), GIMT_Encode4(0), |
| 4646 | /*GILLT_nxv16s8*//*Label 312*/ GIMT_Encode4(12761), |
| 4647 | /*GILLT_nxv16s16*//*Label 313*/ GIMT_Encode4(12876), |
| 4648 | /*GILLT_nxv16s32*//*Label 314*/ GIMT_Encode4(12991), GIMT_Encode4(0), |
| 4649 | /*GILLT_nxv32s8*//*Label 315*/ GIMT_Encode4(13106), |
| 4650 | /*GILLT_nxv32s16*//*Label 316*/ GIMT_Encode4(13221), GIMT_Encode4(0), |
| 4651 | /*GILLT_nxv64s8*//*Label 317*/ GIMT_Encode4(13336), |
| 4652 | // Label 294: @10483 |
| 4653 | GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(10791), |
| 4654 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4655 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4657 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4658 | GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(10538), // Rule ID 65043 // |
| 4659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 4660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4661 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4662 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 4663 | // MIs[1] Operand 1 |
| 4664 | // No operand predicates |
| 4665 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4666 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm)) |
| 4667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 4668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4669 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4670 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm |
| 4671 | GIR_RootConstrainSelectedInstOperands, |
| 4672 | // GIR_Coverage, 65043, |
| 4673 | GIR_EraseRootFromParent_Done, |
| 4674 | // Label 320: @10538 |
| 4675 | GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(10574), // Rule ID 65044 // |
| 4676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 4677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4679 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1i32), |
| 4680 | // MIs[1] Operand 1 |
| 4681 | // No operand predicates |
| 4682 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4683 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1i32>>:$imm) => (ADDIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i64] } ?:{ *:[i32] }:$imm)) |
| 4684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDIW), |
| 4685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4686 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4687 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm |
| 4688 | GIR_RootConstrainSelectedInstOperands, |
| 4689 | // GIR_Coverage, 65044, |
| 4690 | GIR_EraseRootFromParent_Done, |
| 4691 | // Label 321: @10574 |
| 4692 | GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(10627), // Rule ID 63061 // |
| 4693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode1), |
| 4694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4695 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4696 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4697 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4698 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4699 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4700 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4701 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULS:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 4702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULS), |
| 4703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 4704 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 4705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 4706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 4707 | GIR_RootConstrainSelectedInstOperands, |
| 4708 | // GIR_Coverage, 63061, |
| 4709 | GIR_EraseRootFromParent_Done, |
| 4710 | // Label 322: @10627 |
| 4711 | GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(10680), // Rule ID 63318 // |
| 4712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0), |
| 4713 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4714 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4715 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4716 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4717 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4718 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4719 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4720 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULSW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 4721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULSW), |
| 4722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 4723 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 4724 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 4725 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 4726 | GIR_RootConstrainSelectedInstOperands, |
| 4727 | // GIR_Coverage, 63318, |
| 4728 | GIR_EraseRootFromParent_Done, |
| 4729 | // Label 323: @10680 |
| 4730 | GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(10733), // Rule ID 63319 // |
| 4731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1), |
| 4732 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4733 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4734 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4735 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4736 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4737 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4738 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4739 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULSW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 4740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULSW), |
| 4741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 4742 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 4743 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 4744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 4745 | GIR_RootConstrainSelectedInstOperands, |
| 4746 | // GIR_Coverage, 63319, |
| 4747 | GIR_EraseRootFromParent_Done, |
| 4748 | // Label 324: @10733 |
| 4749 | GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(10752), // Rule ID 71 // |
| 4750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 4751 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4752 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 4753 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUB), |
| 4754 | GIR_RootConstrainSelectedInstOperands, |
| 4755 | // GIR_Coverage, 71, |
| 4756 | GIR_Done, |
| 4757 | // Label 325: @10752 |
| 4758 | GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(10771), // Rule ID 299 // |
| 4759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 4760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4761 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUBW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 4762 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUBW), |
| 4763 | GIR_RootConstrainSelectedInstOperands, |
| 4764 | // GIR_Coverage, 299, |
| 4765 | GIR_Done, |
| 4766 | // Label 326: @10771 |
| 4767 | GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(10790), // Rule ID 300 // |
| 4768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 4769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4770 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUBW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 4771 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUBW), |
| 4772 | GIR_RootConstrainSelectedInstOperands, |
| 4773 | // GIR_Coverage, 300, |
| 4774 | GIR_Done, |
| 4775 | // Label 327: @10790 |
| 4776 | GIM_Reject, |
| 4777 | // Label 319: @10791 |
| 4778 | GIM_Reject, |
| 4779 | // Label 295: @10792 |
| 4780 | GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(10920), |
| 4781 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 4782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4784 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4785 | GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(10847), // Rule ID 65042 // |
| 4786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 4787 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4788 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4789 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 4790 | // MIs[1] Operand 1 |
| 4791 | // No operand predicates |
| 4792 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4793 | // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm) => (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (NegImm:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm)) |
| 4794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 4795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4796 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4797 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm |
| 4798 | GIR_RootConstrainSelectedInstOperands, |
| 4799 | // GIR_Coverage, 65042, |
| 4800 | GIR_EraseRootFromParent_Done, |
| 4801 | // Label 329: @10847 |
| 4802 | GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(10900), // Rule ID 63060 // |
| 4803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode0), |
| 4804 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4805 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4806 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 4807 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 4808 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4809 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4810 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4811 | // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rd, (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) => (TH_MULS:{ *:[i64] } GPR:{ *:[i64] }:$rd, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 4812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULS), |
| 4813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 4814 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 4815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 4816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 4817 | GIR_RootConstrainSelectedInstOperands, |
| 4818 | // GIR_Coverage, 63060, |
| 4819 | GIR_EraseRootFromParent_Done, |
| 4820 | // Label 330: @10900 |
| 4821 | GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(10919), // Rule ID 70 // |
| 4822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 4823 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 4824 | // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 4825 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUB), |
| 4826 | GIR_RootConstrainSelectedInstOperands, |
| 4827 | // GIR_Coverage, 70, |
| 4828 | GIR_Done, |
| 4829 | // Label 331: @10919 |
| 4830 | GIM_Reject, |
| 4831 | // Label 328: @10920 |
| 4832 | GIM_Reject, |
| 4833 | // Label 296: @10921 |
| 4834 | GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(11035), |
| 4835 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 4836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 4837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4838 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4839 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4840 | GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(10989), // Rule ID 47076 // |
| 4841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4842 | // (sub:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSUB_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 4843 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 4844 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4845 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF8), |
| 4848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4849 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4850 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4851 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4855 | GIR_RootConstrainSelectedInstOperands, |
| 4856 | // GIR_Coverage, 47076, |
| 4857 | GIR_EraseRootFromParent_Done, |
| 4858 | // Label 333: @10989 |
| 4859 | GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(11034), // Rule ID 47077 // |
| 4860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4861 | // (sub:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSUB_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 4862 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 4863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4864 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4865 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF8), |
| 4867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4868 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4869 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4870 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4874 | GIR_RootConstrainSelectedInstOperands, |
| 4875 | // GIR_Coverage, 47077, |
| 4876 | GIR_EraseRootFromParent_Done, |
| 4877 | // Label 334: @11034 |
| 4878 | GIM_Reject, |
| 4879 | // Label 332: @11035 |
| 4880 | GIM_Reject, |
| 4881 | // Label 297: @11036 |
| 4882 | GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(11150), |
| 4883 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 4884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 4885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4888 | GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(11104), // Rule ID 47088 // |
| 4889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4890 | // (sub:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 4891 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 4892 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4893 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), |
| 4896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4897 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4898 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4899 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4903 | GIR_RootConstrainSelectedInstOperands, |
| 4904 | // GIR_Coverage, 47088, |
| 4905 | GIR_EraseRootFromParent_Done, |
| 4906 | // Label 336: @11104 |
| 4907 | GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(11149), // Rule ID 47089 // |
| 4908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4909 | // (sub:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 4910 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 4911 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4912 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4913 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), |
| 4915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4916 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4917 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4918 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 4921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4922 | GIR_RootConstrainSelectedInstOperands, |
| 4923 | // GIR_Coverage, 47089, |
| 4924 | GIR_EraseRootFromParent_Done, |
| 4925 | // Label 337: @11149 |
| 4926 | GIM_Reject, |
| 4927 | // Label 335: @11150 |
| 4928 | GIM_Reject, |
| 4929 | // Label 298: @11151 |
| 4930 | GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(11265), |
| 4931 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 4932 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 4933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4934 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4935 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4936 | GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(11219), // Rule ID 47096 // |
| 4937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 4938 | // (sub:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 4939 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 4940 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4941 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4942 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), |
| 4944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4945 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4946 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4947 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4951 | GIR_RootConstrainSelectedInstOperands, |
| 4952 | // GIR_Coverage, 47096, |
| 4953 | GIR_EraseRootFromParent_Done, |
| 4954 | // Label 339: @11219 |
| 4955 | GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(11264), // Rule ID 47097 // |
| 4956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 4957 | // (sub:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 4958 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 4959 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4960 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), |
| 4963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4964 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4965 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4966 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 4969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4970 | GIR_RootConstrainSelectedInstOperands, |
| 4971 | // GIR_Coverage, 47097, |
| 4972 | GIR_EraseRootFromParent_Done, |
| 4973 | // Label 340: @11264 |
| 4974 | GIM_Reject, |
| 4975 | // Label 338: @11265 |
| 4976 | GIM_Reject, |
| 4977 | // Label 299: @11266 |
| 4978 | GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(11380), |
| 4979 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 4980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 4981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4983 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 4984 | GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(11334), // Rule ID 47112 // |
| 4985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 4986 | // (sub:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 4987 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 4988 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4989 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 4992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 4993 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4994 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 4995 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 4996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 4997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 4998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 4999 | GIR_RootConstrainSelectedInstOperands, |
| 5000 | // GIR_Coverage, 47112, |
| 5001 | GIR_EraseRootFromParent_Done, |
| 5002 | // Label 342: @11334 |
| 5003 | GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(11379), // Rule ID 47113 // |
| 5004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 5005 | // (sub:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 5006 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 5007 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5008 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5009 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5012 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5013 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5014 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5018 | GIR_RootConstrainSelectedInstOperands, |
| 5019 | // GIR_Coverage, 47113, |
| 5020 | GIR_EraseRootFromParent_Done, |
| 5021 | // Label 343: @11379 |
| 5022 | GIM_Reject, |
| 5023 | // Label 341: @11380 |
| 5024 | GIM_Reject, |
| 5025 | // Label 300: @11381 |
| 5026 | GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(11495), |
| 5027 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 5028 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 5029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5031 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5032 | GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(11449), // Rule ID 47080 // |
| 5033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5034 | // (sub:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 5035 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 5036 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5037 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5038 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), |
| 5040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5041 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5042 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5043 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5047 | GIR_RootConstrainSelectedInstOperands, |
| 5048 | // GIR_Coverage, 47080, |
| 5049 | GIR_EraseRootFromParent_Done, |
| 5050 | // Label 345: @11449 |
| 5051 | GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(11494), // Rule ID 47081 // |
| 5052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5053 | // (sub:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 5054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 5055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), |
| 5059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5060 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5061 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5062 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5066 | GIR_RootConstrainSelectedInstOperands, |
| 5067 | // GIR_Coverage, 47081, |
| 5068 | GIR_EraseRootFromParent_Done, |
| 5069 | // Label 346: @11494 |
| 5070 | GIM_Reject, |
| 5071 | // Label 344: @11495 |
| 5072 | GIM_Reject, |
| 5073 | // Label 301: @11496 |
| 5074 | GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(11610), |
| 5075 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 5076 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 5077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5078 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5079 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5080 | GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(11564), // Rule ID 47092 // |
| 5081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5082 | // (sub:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 5083 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 5084 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5085 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), |
| 5088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5089 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5090 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5091 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5095 | GIR_RootConstrainSelectedInstOperands, |
| 5096 | // GIR_Coverage, 47092, |
| 5097 | GIR_EraseRootFromParent_Done, |
| 5098 | // Label 348: @11564 |
| 5099 | GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(11609), // Rule ID 47093 // |
| 5100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5101 | // (sub:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 5102 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 5103 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5104 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), |
| 5107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5108 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5109 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5110 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5114 | GIR_RootConstrainSelectedInstOperands, |
| 5115 | // GIR_Coverage, 47093, |
| 5116 | GIR_EraseRootFromParent_Done, |
| 5117 | // Label 349: @11609 |
| 5118 | GIM_Reject, |
| 5119 | // Label 347: @11610 |
| 5120 | GIM_Reject, |
| 5121 | // Label 302: @11611 |
| 5122 | GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(11725), |
| 5123 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 5124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 5125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5126 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5127 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5128 | GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(11679), // Rule ID 47108 // |
| 5129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5130 | // (sub:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 5131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 5132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5138 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5139 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5143 | GIR_RootConstrainSelectedInstOperands, |
| 5144 | // GIR_Coverage, 47108, |
| 5145 | GIR_EraseRootFromParent_Done, |
| 5146 | // Label 351: @11679 |
| 5147 | GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(11724), // Rule ID 47109 // |
| 5148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5149 | // (sub:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 5150 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 5151 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5152 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5156 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5157 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5158 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5162 | GIR_RootConstrainSelectedInstOperands, |
| 5163 | // GIR_Coverage, 47109, |
| 5164 | GIR_EraseRootFromParent_Done, |
| 5165 | // Label 352: @11724 |
| 5166 | GIM_Reject, |
| 5167 | // Label 350: @11725 |
| 5168 | GIM_Reject, |
| 5169 | // Label 303: @11726 |
| 5170 | GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(11840), |
| 5171 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 5172 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 5173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5174 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5175 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5176 | GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(11794), // Rule ID 47152 // |
| 5177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 5178 | // (sub:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 5179 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 5180 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5181 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5182 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5185 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5186 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5187 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5191 | GIR_RootConstrainSelectedInstOperands, |
| 5192 | // GIR_Coverage, 47152, |
| 5193 | GIR_EraseRootFromParent_Done, |
| 5194 | // Label 354: @11794 |
| 5195 | GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(11839), // Rule ID 47153 // |
| 5196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 5197 | // (sub:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 5198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 5199 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5200 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5204 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5205 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5206 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5210 | GIR_RootConstrainSelectedInstOperands, |
| 5211 | // GIR_Coverage, 47153, |
| 5212 | GIR_EraseRootFromParent_Done, |
| 5213 | // Label 355: @11839 |
| 5214 | GIM_Reject, |
| 5215 | // Label 353: @11840 |
| 5216 | GIM_Reject, |
| 5217 | // Label 304: @11841 |
| 5218 | GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(11955), |
| 5219 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 5220 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 5221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5222 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5223 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5224 | GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(11909), // Rule ID 47084 // |
| 5225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5226 | // (sub:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 5227 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 5228 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5229 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), |
| 5232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5233 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5234 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5235 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5239 | GIR_RootConstrainSelectedInstOperands, |
| 5240 | // GIR_Coverage, 47084, |
| 5241 | GIR_EraseRootFromParent_Done, |
| 5242 | // Label 357: @11909 |
| 5243 | GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(11954), // Rule ID 47085 // |
| 5244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5245 | // (sub:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 5246 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 5247 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5248 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), |
| 5251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5252 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5253 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5254 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5258 | GIR_RootConstrainSelectedInstOperands, |
| 5259 | // GIR_Coverage, 47085, |
| 5260 | GIR_EraseRootFromParent_Done, |
| 5261 | // Label 358: @11954 |
| 5262 | GIM_Reject, |
| 5263 | // Label 356: @11955 |
| 5264 | GIM_Reject, |
| 5265 | // Label 305: @11956 |
| 5266 | GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(12070), |
| 5267 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 5268 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 5269 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5270 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5271 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5272 | GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(12024), // Rule ID 47104 // |
| 5273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5274 | // (sub:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 5275 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 5276 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5277 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5278 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5281 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5282 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5283 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5287 | GIR_RootConstrainSelectedInstOperands, |
| 5288 | // GIR_Coverage, 47104, |
| 5289 | GIR_EraseRootFromParent_Done, |
| 5290 | // Label 360: @12024 |
| 5291 | GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(12069), // Rule ID 47105 // |
| 5292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5293 | // (sub:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 5294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 5295 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5296 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5300 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5301 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5302 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5306 | GIR_RootConstrainSelectedInstOperands, |
| 5307 | // GIR_Coverage, 47105, |
| 5308 | GIR_EraseRootFromParent_Done, |
| 5309 | // Label 361: @12069 |
| 5310 | GIM_Reject, |
| 5311 | // Label 359: @12070 |
| 5312 | GIM_Reject, |
| 5313 | // Label 306: @12071 |
| 5314 | GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(12185), |
| 5315 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 5316 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 5317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5318 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5319 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5320 | GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(12139), // Rule ID 47140 // |
| 5321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5322 | // (sub:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 5323 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 5324 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5325 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5329 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5330 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5331 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5335 | GIR_RootConstrainSelectedInstOperands, |
| 5336 | // GIR_Coverage, 47140, |
| 5337 | GIR_EraseRootFromParent_Done, |
| 5338 | // Label 363: @12139 |
| 5339 | GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(12184), // Rule ID 47141 // |
| 5340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5341 | // (sub:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 5342 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 5343 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5344 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5345 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5348 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5349 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5350 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5354 | GIR_RootConstrainSelectedInstOperands, |
| 5355 | // GIR_Coverage, 47141, |
| 5356 | GIR_EraseRootFromParent_Done, |
| 5357 | // Label 364: @12184 |
| 5358 | GIM_Reject, |
| 5359 | // Label 362: @12185 |
| 5360 | GIM_Reject, |
| 5361 | // Label 307: @12186 |
| 5362 | GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(12300), |
| 5363 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 5364 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 5365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5366 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5368 | GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(12254), // Rule ID 47156 // |
| 5369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 5370 | // (sub:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 5371 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 5372 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5373 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5377 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5378 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5379 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5383 | GIR_RootConstrainSelectedInstOperands, |
| 5384 | // GIR_Coverage, 47156, |
| 5385 | GIR_EraseRootFromParent_Done, |
| 5386 | // Label 366: @12254 |
| 5387 | GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(12299), // Rule ID 47157 // |
| 5388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 5389 | // (sub:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 5390 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 5391 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5392 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5396 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5397 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5398 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5402 | GIR_RootConstrainSelectedInstOperands, |
| 5403 | // GIR_Coverage, 47157, |
| 5404 | GIR_EraseRootFromParent_Done, |
| 5405 | // Label 367: @12299 |
| 5406 | GIM_Reject, |
| 5407 | // Label 365: @12300 |
| 5408 | GIM_Reject, |
| 5409 | // Label 308: @12301 |
| 5410 | GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(12415), |
| 5411 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 5412 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 5413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5414 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5415 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 5416 | GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(12369), // Rule ID 47100 // |
| 5417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5418 | // (sub:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 5419 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 5420 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5421 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5425 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5426 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5427 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5431 | GIR_RootConstrainSelectedInstOperands, |
| 5432 | // GIR_Coverage, 47100, |
| 5433 | GIR_EraseRootFromParent_Done, |
| 5434 | // Label 369: @12369 |
| 5435 | GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(12414), // Rule ID 47101 // |
| 5436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5437 | // (sub:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 5438 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 5439 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5440 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5441 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), |
| 5443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5444 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5445 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5450 | GIR_RootConstrainSelectedInstOperands, |
| 5451 | // GIR_Coverage, 47101, |
| 5452 | GIR_EraseRootFromParent_Done, |
| 5453 | // Label 370: @12414 |
| 5454 | GIM_Reject, |
| 5455 | // Label 368: @12415 |
| 5456 | GIM_Reject, |
| 5457 | // Label 309: @12416 |
| 5458 | GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(12530), |
| 5459 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 5460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 5461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5464 | GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(12484), // Rule ID 47128 // |
| 5465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5466 | // (sub:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 5467 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 5468 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5469 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5473 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5474 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5475 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5479 | GIR_RootConstrainSelectedInstOperands, |
| 5480 | // GIR_Coverage, 47128, |
| 5481 | GIR_EraseRootFromParent_Done, |
| 5482 | // Label 372: @12484 |
| 5483 | GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(12529), // Rule ID 47129 // |
| 5484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5485 | // (sub:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 5486 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 5487 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5488 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5492 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5493 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5494 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5498 | GIR_RootConstrainSelectedInstOperands, |
| 5499 | // GIR_Coverage, 47129, |
| 5500 | GIR_EraseRootFromParent_Done, |
| 5501 | // Label 373: @12529 |
| 5502 | GIM_Reject, |
| 5503 | // Label 371: @12530 |
| 5504 | GIM_Reject, |
| 5505 | // Label 310: @12531 |
| 5506 | GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(12645), |
| 5507 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 5508 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 5509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5510 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5511 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5512 | GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(12599), // Rule ID 47144 // |
| 5513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5514 | // (sub:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 5515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 5516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5521 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5522 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5523 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5527 | GIR_RootConstrainSelectedInstOperands, |
| 5528 | // GIR_Coverage, 47144, |
| 5529 | GIR_EraseRootFromParent_Done, |
| 5530 | // Label 375: @12599 |
| 5531 | GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(12644), // Rule ID 47145 // |
| 5532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5533 | // (sub:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 5534 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 5535 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5536 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5537 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5540 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5541 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5542 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5546 | GIR_RootConstrainSelectedInstOperands, |
| 5547 | // GIR_Coverage, 47145, |
| 5548 | GIR_EraseRootFromParent_Done, |
| 5549 | // Label 376: @12644 |
| 5550 | GIM_Reject, |
| 5551 | // Label 374: @12645 |
| 5552 | GIM_Reject, |
| 5553 | // Label 311: @12646 |
| 5554 | GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(12760), |
| 5555 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 5556 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 5557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5558 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5559 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5560 | GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(12714), // Rule ID 47160 // |
| 5561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 5562 | // (sub:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 5563 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 5564 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5565 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5569 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5570 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5571 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5575 | GIR_RootConstrainSelectedInstOperands, |
| 5576 | // GIR_Coverage, 47160, |
| 5577 | GIR_EraseRootFromParent_Done, |
| 5578 | // Label 378: @12714 |
| 5579 | GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(12759), // Rule ID 47161 // |
| 5580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 5581 | // (sub:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 5582 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 5583 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5584 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5588 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5589 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5590 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 5593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5594 | GIR_RootConstrainSelectedInstOperands, |
| 5595 | // GIR_Coverage, 47161, |
| 5596 | GIR_EraseRootFromParent_Done, |
| 5597 | // Label 379: @12759 |
| 5598 | GIM_Reject, |
| 5599 | // Label 377: @12760 |
| 5600 | GIM_Reject, |
| 5601 | // Label 312: @12761 |
| 5602 | GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(12875), |
| 5603 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 5604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 5605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5606 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 5608 | GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(12829), // Rule ID 47116 // |
| 5609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5610 | // (sub:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 5611 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 5612 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5613 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5618 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5619 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5623 | GIR_RootConstrainSelectedInstOperands, |
| 5624 | // GIR_Coverage, 47116, |
| 5625 | GIR_EraseRootFromParent_Done, |
| 5626 | // Label 381: @12829 |
| 5627 | GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(12874), // Rule ID 47117 // |
| 5628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5629 | // (sub:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 5630 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 5631 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5632 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), |
| 5635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5642 | GIR_RootConstrainSelectedInstOperands, |
| 5643 | // GIR_Coverage, 47117, |
| 5644 | GIR_EraseRootFromParent_Done, |
| 5645 | // Label 382: @12874 |
| 5646 | GIM_Reject, |
| 5647 | // Label 380: @12875 |
| 5648 | GIM_Reject, |
| 5649 | // Label 313: @12876 |
| 5650 | GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(12990), |
| 5651 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 5652 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 5653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5654 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5656 | GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(12944), // Rule ID 47132 // |
| 5657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5658 | // (sub:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 5659 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 5660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5665 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5666 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5667 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5671 | GIR_RootConstrainSelectedInstOperands, |
| 5672 | // GIR_Coverage, 47132, |
| 5673 | GIR_EraseRootFromParent_Done, |
| 5674 | // Label 384: @12944 |
| 5675 | GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(12989), // Rule ID 47133 // |
| 5676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5677 | // (sub:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 5678 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 5679 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5680 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5681 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5684 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5685 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5690 | GIR_RootConstrainSelectedInstOperands, |
| 5691 | // GIR_Coverage, 47133, |
| 5692 | GIR_EraseRootFromParent_Done, |
| 5693 | // Label 385: @12989 |
| 5694 | GIM_Reject, |
| 5695 | // Label 383: @12990 |
| 5696 | GIM_Reject, |
| 5697 | // Label 314: @12991 |
| 5698 | GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(13105), |
| 5699 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 5700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 5701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5702 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5703 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5704 | GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(13059), // Rule ID 47148 // |
| 5705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5706 | // (sub:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 5707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 5708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5713 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5714 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5715 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5719 | GIR_RootConstrainSelectedInstOperands, |
| 5720 | // GIR_Coverage, 47148, |
| 5721 | GIR_EraseRootFromParent_Done, |
| 5722 | // Label 387: @13059 |
| 5723 | GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(13104), // Rule ID 47149 // |
| 5724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5725 | // (sub:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 5726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 5727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5732 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5733 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5734 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 5737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5738 | GIR_RootConstrainSelectedInstOperands, |
| 5739 | // GIR_Coverage, 47149, |
| 5740 | GIR_EraseRootFromParent_Done, |
| 5741 | // Label 388: @13104 |
| 5742 | GIM_Reject, |
| 5743 | // Label 386: @13105 |
| 5744 | GIM_Reject, |
| 5745 | // Label 315: @13106 |
| 5746 | GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(13220), |
| 5747 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 5748 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 5749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5750 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5751 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 5752 | GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(13174), // Rule ID 47120 // |
| 5753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5754 | // (sub:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 5755 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 5756 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5757 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5761 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5762 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5763 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5767 | GIR_RootConstrainSelectedInstOperands, |
| 5768 | // GIR_Coverage, 47120, |
| 5769 | GIR_EraseRootFromParent_Done, |
| 5770 | // Label 390: @13174 |
| 5771 | GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(13219), // Rule ID 47121 // |
| 5772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5773 | // (sub:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 5774 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 5775 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5776 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), |
| 5779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5780 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5781 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5782 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5786 | GIR_RootConstrainSelectedInstOperands, |
| 5787 | // GIR_Coverage, 47121, |
| 5788 | GIR_EraseRootFromParent_Done, |
| 5789 | // Label 391: @13219 |
| 5790 | GIM_Reject, |
| 5791 | // Label 389: @13220 |
| 5792 | GIM_Reject, |
| 5793 | // Label 316: @13221 |
| 5794 | GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(13335), |
| 5795 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 5796 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 5797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5800 | GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(13289), // Rule ID 47136 // |
| 5801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5802 | // (sub:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 5803 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 5804 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5805 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5806 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5809 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5810 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5811 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5815 | GIR_RootConstrainSelectedInstOperands, |
| 5816 | // GIR_Coverage, 47136, |
| 5817 | GIR_EraseRootFromParent_Done, |
| 5818 | // Label 393: @13289 |
| 5819 | GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(13334), // Rule ID 47137 // |
| 5820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5821 | // (sub:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 5822 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 5823 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5824 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5825 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5828 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5829 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5830 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 5833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5834 | GIR_RootConstrainSelectedInstOperands, |
| 5835 | // GIR_Coverage, 47137, |
| 5836 | GIR_EraseRootFromParent_Done, |
| 5837 | // Label 394: @13334 |
| 5838 | GIM_Reject, |
| 5839 | // Label 392: @13335 |
| 5840 | GIM_Reject, |
| 5841 | // Label 317: @13336 |
| 5842 | GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(13450), |
| 5843 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 5844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 5845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5847 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 5848 | GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(13404), // Rule ID 47124 // |
| 5849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 5850 | // (sub:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 5851 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 5852 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5853 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5854 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5857 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5858 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5859 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5863 | GIR_RootConstrainSelectedInstOperands, |
| 5864 | // GIR_Coverage, 47124, |
| 5865 | GIR_EraseRootFromParent_Done, |
| 5866 | // Label 396: @13404 |
| 5867 | GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(13449), // Rule ID 47125 // |
| 5868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 5869 | // (sub:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 5870 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 5871 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5872 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5873 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), |
| 5875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5876 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5877 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 5878 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 5879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 5880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 5882 | GIR_RootConstrainSelectedInstOperands, |
| 5883 | // GIR_Coverage, 47125, |
| 5884 | GIR_EraseRootFromParent_Done, |
| 5885 | // Label 397: @13449 |
| 5886 | GIM_Reject, |
| 5887 | // Label 395: @13450 |
| 5888 | GIM_Reject, |
| 5889 | // Label 318: @13451 |
| 5890 | GIM_Reject, |
| 5891 | // Label 2: @13452 |
| 5892 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 422*/ GIMT_Encode4(16356), |
| 5893 | /*GILLT_s32*//*Label 398*/ GIMT_Encode4(13587), |
| 5894 | /*GILLT_s64*//*Label 399*/ GIMT_Encode4(13657), GIMT_Encode4(0), |
| 5895 | /*GILLT_nxv1s8*//*Label 400*/ GIMT_Encode4(13826), |
| 5896 | /*GILLT_nxv1s16*//*Label 401*/ GIMT_Encode4(13941), |
| 5897 | /*GILLT_nxv1s32*//*Label 402*/ GIMT_Encode4(14056), |
| 5898 | /*GILLT_nxv1s64*//*Label 403*/ GIMT_Encode4(14171), GIMT_Encode4(0), |
| 5899 | /*GILLT_nxv2s8*//*Label 404*/ GIMT_Encode4(14286), |
| 5900 | /*GILLT_nxv2s16*//*Label 405*/ GIMT_Encode4(14401), |
| 5901 | /*GILLT_nxv2s32*//*Label 406*/ GIMT_Encode4(14516), |
| 5902 | /*GILLT_nxv2s64*//*Label 407*/ GIMT_Encode4(14631), GIMT_Encode4(0), |
| 5903 | /*GILLT_nxv4s8*//*Label 408*/ GIMT_Encode4(14746), |
| 5904 | /*GILLT_nxv4s16*//*Label 409*/ GIMT_Encode4(14861), |
| 5905 | /*GILLT_nxv4s32*//*Label 410*/ GIMT_Encode4(14976), |
| 5906 | /*GILLT_nxv4s64*//*Label 411*/ GIMT_Encode4(15091), GIMT_Encode4(0), |
| 5907 | /*GILLT_nxv8s8*//*Label 412*/ GIMT_Encode4(15206), |
| 5908 | /*GILLT_nxv8s16*//*Label 413*/ GIMT_Encode4(15321), |
| 5909 | /*GILLT_nxv8s32*//*Label 414*/ GIMT_Encode4(15436), |
| 5910 | /*GILLT_nxv8s64*//*Label 415*/ GIMT_Encode4(15551), GIMT_Encode4(0), |
| 5911 | /*GILLT_nxv16s8*//*Label 416*/ GIMT_Encode4(15666), |
| 5912 | /*GILLT_nxv16s16*//*Label 417*/ GIMT_Encode4(15781), |
| 5913 | /*GILLT_nxv16s32*//*Label 418*/ GIMT_Encode4(15896), GIMT_Encode4(0), |
| 5914 | /*GILLT_nxv32s8*//*Label 419*/ GIMT_Encode4(16011), |
| 5915 | /*GILLT_nxv32s16*//*Label 420*/ GIMT_Encode4(16126), GIMT_Encode4(0), |
| 5916 | /*GILLT_nxv64s8*//*Label 421*/ GIMT_Encode4(16241), |
| 5917 | // Label 398: @13587 |
| 5918 | GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(13656), |
| 5919 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5924 | GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(13625), // Rule ID 325 // |
| 5925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode1), |
| 5926 | // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 5927 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MUL), |
| 5928 | GIR_RootConstrainSelectedInstOperands, |
| 5929 | // GIR_Coverage, 325, |
| 5930 | GIR_Done, |
| 5931 | // Label 424: @13625 |
| 5932 | GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(13640), // Rule ID 348 // |
| 5933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_IsRV64_HwMode0), |
| 5934 | // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 5935 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULW), |
| 5936 | GIR_RootConstrainSelectedInstOperands, |
| 5937 | // GIR_Coverage, 348, |
| 5938 | GIR_Done, |
| 5939 | // Label 425: @13640 |
| 5940 | GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(13655), // Rule ID 349 // |
| 5941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_IsRV64_HwMode1), |
| 5942 | // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 5943 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULW), |
| 5944 | GIR_RootConstrainSelectedInstOperands, |
| 5945 | // GIR_Coverage, 349, |
| 5946 | GIR_Done, |
| 5947 | // Label 426: @13655 |
| 5948 | GIM_Reject, |
| 5949 | // Label 423: @13656 |
| 5950 | GIM_Reject, |
| 5951 | // Label 399: @13657 |
| 5952 | GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(13825), |
| 5953 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 5954 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5956 | GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(13801), // Rule ID 347 // |
| 5957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_IsRV64_NotHasStdExtZba_HwMode0), |
| 5958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5959 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5960 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5961 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5962 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5963 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), |
| 5964 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5965 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5966 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 5967 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 5968 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5969 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), |
| 5970 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5971 | // (mul:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })) => (MULHU:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 32:{ *:[i64] })) |
| 5972 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 5973 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 5974 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 5975 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5976 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 5977 | GIR_AddImm8, /*InsnID*/2, /*Imm*/32, |
| 5978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5979 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 5980 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5981 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 5982 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 5983 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::MULHU), |
| 5985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 5986 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 5988 | GIR_RootConstrainSelectedInstOperands, |
| 5989 | // GIR_Coverage, 347, |
| 5990 | GIR_EraseRootFromParent_Done, |
| 5991 | // Label 428: @13801 |
| 5992 | GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(13824), // Rule ID 324 // |
| 5993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode0), |
| 5994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 5996 | // (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 5997 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MUL), |
| 5998 | GIR_RootConstrainSelectedInstOperands, |
| 5999 | // GIR_Coverage, 324, |
| 6000 | GIR_Done, |
| 6001 | // Label 429: @13824 |
| 6002 | GIM_Reject, |
| 6003 | // Label 427: @13825 |
| 6004 | GIM_Reject, |
| 6005 | // Label 400: @13826 |
| 6006 | GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(13940), |
| 6007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 6008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 6009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6010 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6011 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6012 | GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(13894), // Rule ID 51480 // |
| 6013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6014 | // (mul:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMUL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 6015 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 6016 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6017 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF8), |
| 6020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6021 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6022 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6023 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6027 | GIR_RootConstrainSelectedInstOperands, |
| 6028 | // GIR_Coverage, 51480, |
| 6029 | GIR_EraseRootFromParent_Done, |
| 6030 | // Label 431: @13894 |
| 6031 | GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(13939), // Rule ID 51481 // |
| 6032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6033 | // (mul:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMUL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 6034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 6035 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6036 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6037 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF8), |
| 6039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6040 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6041 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6042 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6046 | GIR_RootConstrainSelectedInstOperands, |
| 6047 | // GIR_Coverage, 51481, |
| 6048 | GIR_EraseRootFromParent_Done, |
| 6049 | // Label 432: @13939 |
| 6050 | GIM_Reject, |
| 6051 | // Label 430: @13940 |
| 6052 | GIM_Reject, |
| 6053 | // Label 401: @13941 |
| 6054 | GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(14055), |
| 6055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 6056 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 6057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6058 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6060 | GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(14009), // Rule ID 51492 // |
| 6061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6062 | // (mul:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 6063 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 6064 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6065 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6066 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), |
| 6068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6069 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6070 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6071 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6075 | GIR_RootConstrainSelectedInstOperands, |
| 6076 | // GIR_Coverage, 51492, |
| 6077 | GIR_EraseRootFromParent_Done, |
| 6078 | // Label 434: @14009 |
| 6079 | GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(14054), // Rule ID 51493 // |
| 6080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6081 | // (mul:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 6082 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 6083 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6084 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6085 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), |
| 6087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6088 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6089 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6090 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6094 | GIR_RootConstrainSelectedInstOperands, |
| 6095 | // GIR_Coverage, 51493, |
| 6096 | GIR_EraseRootFromParent_Done, |
| 6097 | // Label 435: @14054 |
| 6098 | GIM_Reject, |
| 6099 | // Label 433: @14055 |
| 6100 | GIM_Reject, |
| 6101 | // Label 402: @14056 |
| 6102 | GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(14170), |
| 6103 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 6104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 6105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6107 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6108 | GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(14124), // Rule ID 51500 // |
| 6109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6110 | // (mul:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 6111 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 6112 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6113 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), |
| 6116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6117 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6118 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6119 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6123 | GIR_RootConstrainSelectedInstOperands, |
| 6124 | // GIR_Coverage, 51500, |
| 6125 | GIR_EraseRootFromParent_Done, |
| 6126 | // Label 437: @14124 |
| 6127 | GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(14169), // Rule ID 51501 // |
| 6128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6129 | // (mul:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 6130 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 6131 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6132 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6133 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), |
| 6135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6136 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6137 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6138 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6142 | GIR_RootConstrainSelectedInstOperands, |
| 6143 | // GIR_Coverage, 51501, |
| 6144 | GIR_EraseRootFromParent_Done, |
| 6145 | // Label 438: @14169 |
| 6146 | GIM_Reject, |
| 6147 | // Label 436: @14170 |
| 6148 | GIM_Reject, |
| 6149 | // Label 403: @14171 |
| 6150 | GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(14285), |
| 6151 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 6152 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 6153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6154 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6155 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6156 | GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(14239), // Rule ID 51516 // |
| 6157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 6158 | // (mul:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 6159 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 6160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6166 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6167 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6171 | GIR_RootConstrainSelectedInstOperands, |
| 6172 | // GIR_Coverage, 51516, |
| 6173 | GIR_EraseRootFromParent_Done, |
| 6174 | // Label 440: @14239 |
| 6175 | GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(14284), // Rule ID 51517 // |
| 6176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 6177 | // (mul:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 6178 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 6179 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6180 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6184 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6185 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6186 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6190 | GIR_RootConstrainSelectedInstOperands, |
| 6191 | // GIR_Coverage, 51517, |
| 6192 | GIR_EraseRootFromParent_Done, |
| 6193 | // Label 441: @14284 |
| 6194 | GIM_Reject, |
| 6195 | // Label 439: @14285 |
| 6196 | GIM_Reject, |
| 6197 | // Label 404: @14286 |
| 6198 | GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(14400), |
| 6199 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 6200 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 6201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6202 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6203 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6204 | GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(14354), // Rule ID 51484 // |
| 6205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6206 | // (mul:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 6207 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 6208 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6209 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), |
| 6212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6213 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6214 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6215 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6219 | GIR_RootConstrainSelectedInstOperands, |
| 6220 | // GIR_Coverage, 51484, |
| 6221 | GIR_EraseRootFromParent_Done, |
| 6222 | // Label 443: @14354 |
| 6223 | GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(14399), // Rule ID 51485 // |
| 6224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6225 | // (mul:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 6226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 6227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), |
| 6231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6232 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6233 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6234 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6238 | GIR_RootConstrainSelectedInstOperands, |
| 6239 | // GIR_Coverage, 51485, |
| 6240 | GIR_EraseRootFromParent_Done, |
| 6241 | // Label 444: @14399 |
| 6242 | GIM_Reject, |
| 6243 | // Label 442: @14400 |
| 6244 | GIM_Reject, |
| 6245 | // Label 405: @14401 |
| 6246 | GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(14515), |
| 6247 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 6248 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 6249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6250 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6251 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6252 | GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(14469), // Rule ID 51496 // |
| 6253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6254 | // (mul:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 6255 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 6256 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6257 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6258 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), |
| 6260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6261 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6262 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6263 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6267 | GIR_RootConstrainSelectedInstOperands, |
| 6268 | // GIR_Coverage, 51496, |
| 6269 | GIR_EraseRootFromParent_Done, |
| 6270 | // Label 446: @14469 |
| 6271 | GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(14514), // Rule ID 51497 // |
| 6272 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6273 | // (mul:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 6274 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 6275 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6276 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), |
| 6279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6280 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6281 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6282 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6286 | GIR_RootConstrainSelectedInstOperands, |
| 6287 | // GIR_Coverage, 51497, |
| 6288 | GIR_EraseRootFromParent_Done, |
| 6289 | // Label 447: @14514 |
| 6290 | GIM_Reject, |
| 6291 | // Label 445: @14515 |
| 6292 | GIM_Reject, |
| 6293 | // Label 406: @14516 |
| 6294 | GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(14630), |
| 6295 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 6296 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 6297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6298 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6300 | GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(14584), // Rule ID 51512 // |
| 6301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6302 | // (mul:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 6303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 6304 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6305 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6310 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6311 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6315 | GIR_RootConstrainSelectedInstOperands, |
| 6316 | // GIR_Coverage, 51512, |
| 6317 | GIR_EraseRootFromParent_Done, |
| 6318 | // Label 449: @14584 |
| 6319 | GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(14629), // Rule ID 51513 // |
| 6320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6321 | // (mul:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 6322 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 6323 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6324 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6325 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6328 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6329 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6330 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6334 | GIR_RootConstrainSelectedInstOperands, |
| 6335 | // GIR_Coverage, 51513, |
| 6336 | GIR_EraseRootFromParent_Done, |
| 6337 | // Label 450: @14629 |
| 6338 | GIM_Reject, |
| 6339 | // Label 448: @14630 |
| 6340 | GIM_Reject, |
| 6341 | // Label 407: @14631 |
| 6342 | GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(14745), |
| 6343 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 6344 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 6345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6346 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6348 | GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(14699), // Rule ID 51556 // |
| 6349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 6350 | // (mul:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 6351 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 6352 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6353 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6354 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6357 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6358 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6359 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6363 | GIR_RootConstrainSelectedInstOperands, |
| 6364 | // GIR_Coverage, 51556, |
| 6365 | GIR_EraseRootFromParent_Done, |
| 6366 | // Label 452: @14699 |
| 6367 | GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(14744), // Rule ID 51557 // |
| 6368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 6369 | // (mul:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 6370 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 6371 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6372 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6373 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6376 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6377 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6378 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6382 | GIR_RootConstrainSelectedInstOperands, |
| 6383 | // GIR_Coverage, 51557, |
| 6384 | GIR_EraseRootFromParent_Done, |
| 6385 | // Label 453: @14744 |
| 6386 | GIM_Reject, |
| 6387 | // Label 451: @14745 |
| 6388 | GIM_Reject, |
| 6389 | // Label 408: @14746 |
| 6390 | GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(14860), |
| 6391 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 6392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 6393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6394 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6395 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6396 | GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(14814), // Rule ID 51488 // |
| 6397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6398 | // (mul:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 6399 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 6400 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6401 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), |
| 6404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6405 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6406 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6407 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6411 | GIR_RootConstrainSelectedInstOperands, |
| 6412 | // GIR_Coverage, 51488, |
| 6413 | GIR_EraseRootFromParent_Done, |
| 6414 | // Label 455: @14814 |
| 6415 | GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(14859), // Rule ID 51489 // |
| 6416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6417 | // (mul:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 6418 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 6419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), |
| 6423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6424 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6425 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6426 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6430 | GIR_RootConstrainSelectedInstOperands, |
| 6431 | // GIR_Coverage, 51489, |
| 6432 | GIR_EraseRootFromParent_Done, |
| 6433 | // Label 456: @14859 |
| 6434 | GIM_Reject, |
| 6435 | // Label 454: @14860 |
| 6436 | GIM_Reject, |
| 6437 | // Label 409: @14861 |
| 6438 | GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(14975), |
| 6439 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 6440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 6441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6442 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6444 | GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(14929), // Rule ID 51508 // |
| 6445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6446 | // (mul:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 6447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 6448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6449 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6450 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6453 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6454 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6455 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6459 | GIR_RootConstrainSelectedInstOperands, |
| 6460 | // GIR_Coverage, 51508, |
| 6461 | GIR_EraseRootFromParent_Done, |
| 6462 | // Label 458: @14929 |
| 6463 | GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(14974), // Rule ID 51509 // |
| 6464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6465 | // (mul:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 6466 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 6467 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6468 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6469 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6472 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6473 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6474 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6478 | GIR_RootConstrainSelectedInstOperands, |
| 6479 | // GIR_Coverage, 51509, |
| 6480 | GIR_EraseRootFromParent_Done, |
| 6481 | // Label 459: @14974 |
| 6482 | GIM_Reject, |
| 6483 | // Label 457: @14975 |
| 6484 | GIM_Reject, |
| 6485 | // Label 410: @14976 |
| 6486 | GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(15090), |
| 6487 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 6488 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 6489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6490 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6491 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6492 | GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(15044), // Rule ID 51544 // |
| 6493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6494 | // (mul:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 6495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 6496 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6497 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6498 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6501 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6502 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6503 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6507 | GIR_RootConstrainSelectedInstOperands, |
| 6508 | // GIR_Coverage, 51544, |
| 6509 | GIR_EraseRootFromParent_Done, |
| 6510 | // Label 461: @15044 |
| 6511 | GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(15089), // Rule ID 51545 // |
| 6512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6513 | // (mul:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 6514 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 6515 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6516 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6517 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6520 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6521 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6522 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6526 | GIR_RootConstrainSelectedInstOperands, |
| 6527 | // GIR_Coverage, 51545, |
| 6528 | GIR_EraseRootFromParent_Done, |
| 6529 | // Label 462: @15089 |
| 6530 | GIM_Reject, |
| 6531 | // Label 460: @15090 |
| 6532 | GIM_Reject, |
| 6533 | // Label 411: @15091 |
| 6534 | GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(15205), |
| 6535 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 6536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 6537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6538 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6540 | GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(15159), // Rule ID 51560 // |
| 6541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 6542 | // (mul:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 6543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 6544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6550 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6551 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6555 | GIR_RootConstrainSelectedInstOperands, |
| 6556 | // GIR_Coverage, 51560, |
| 6557 | GIR_EraseRootFromParent_Done, |
| 6558 | // Label 464: @15159 |
| 6559 | GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(15204), // Rule ID 51561 // |
| 6560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 6561 | // (mul:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 6562 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 6563 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6564 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6568 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6569 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6570 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6574 | GIR_RootConstrainSelectedInstOperands, |
| 6575 | // GIR_Coverage, 51561, |
| 6576 | GIR_EraseRootFromParent_Done, |
| 6577 | // Label 465: @15204 |
| 6578 | GIM_Reject, |
| 6579 | // Label 463: @15205 |
| 6580 | GIM_Reject, |
| 6581 | // Label 412: @15206 |
| 6582 | GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(15320), |
| 6583 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 6584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 6585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6586 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 6588 | GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(15274), // Rule ID 51504 // |
| 6589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6590 | // (mul:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 6591 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 6592 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6593 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6594 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6597 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6598 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6599 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6603 | GIR_RootConstrainSelectedInstOperands, |
| 6604 | // GIR_Coverage, 51504, |
| 6605 | GIR_EraseRootFromParent_Done, |
| 6606 | // Label 467: @15274 |
| 6607 | GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(15319), // Rule ID 51505 // |
| 6608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6609 | // (mul:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 6610 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 6611 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6612 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6613 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), |
| 6615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6617 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6618 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6622 | GIR_RootConstrainSelectedInstOperands, |
| 6623 | // GIR_Coverage, 51505, |
| 6624 | GIR_EraseRootFromParent_Done, |
| 6625 | // Label 468: @15319 |
| 6626 | GIM_Reject, |
| 6627 | // Label 466: @15320 |
| 6628 | GIM_Reject, |
| 6629 | // Label 413: @15321 |
| 6630 | GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(15435), |
| 6631 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 6632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 6633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6634 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6635 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6636 | GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(15389), // Rule ID 51532 // |
| 6637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6638 | // (mul:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 6639 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 6640 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6641 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6646 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6647 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6651 | GIR_RootConstrainSelectedInstOperands, |
| 6652 | // GIR_Coverage, 51532, |
| 6653 | GIR_EraseRootFromParent_Done, |
| 6654 | // Label 470: @15389 |
| 6655 | GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(15434), // Rule ID 51533 // |
| 6656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6657 | // (mul:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 6658 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 6659 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6660 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6664 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6665 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6670 | GIR_RootConstrainSelectedInstOperands, |
| 6671 | // GIR_Coverage, 51533, |
| 6672 | GIR_EraseRootFromParent_Done, |
| 6673 | // Label 471: @15434 |
| 6674 | GIM_Reject, |
| 6675 | // Label 469: @15435 |
| 6676 | GIM_Reject, |
| 6677 | // Label 414: @15436 |
| 6678 | GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(15550), |
| 6679 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 6680 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 6681 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6682 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6684 | GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(15504), // Rule ID 51548 // |
| 6685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6686 | // (mul:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 6687 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 6688 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6689 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6690 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6693 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6694 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6695 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6699 | GIR_RootConstrainSelectedInstOperands, |
| 6700 | // GIR_Coverage, 51548, |
| 6701 | GIR_EraseRootFromParent_Done, |
| 6702 | // Label 473: @15504 |
| 6703 | GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(15549), // Rule ID 51549 // |
| 6704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6705 | // (mul:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 6706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 6707 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6708 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6713 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6714 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6718 | GIR_RootConstrainSelectedInstOperands, |
| 6719 | // GIR_Coverage, 51549, |
| 6720 | GIR_EraseRootFromParent_Done, |
| 6721 | // Label 474: @15549 |
| 6722 | GIM_Reject, |
| 6723 | // Label 472: @15550 |
| 6724 | GIM_Reject, |
| 6725 | // Label 415: @15551 |
| 6726 | GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(15665), |
| 6727 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 6728 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 6729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6730 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6731 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6732 | GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(15619), // Rule ID 51564 // |
| 6733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 6734 | // (mul:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 6735 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 6736 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6737 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 6740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6742 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6743 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6747 | GIR_RootConstrainSelectedInstOperands, |
| 6748 | // GIR_Coverage, 51564, |
| 6749 | GIR_EraseRootFromParent_Done, |
| 6750 | // Label 476: @15619 |
| 6751 | GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(15664), // Rule ID 51565 // |
| 6752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 6753 | // (mul:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 6754 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 6755 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6756 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 6759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6760 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6761 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6762 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 6765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6766 | GIR_RootConstrainSelectedInstOperands, |
| 6767 | // GIR_Coverage, 51565, |
| 6768 | GIR_EraseRootFromParent_Done, |
| 6769 | // Label 477: @15664 |
| 6770 | GIM_Reject, |
| 6771 | // Label 475: @15665 |
| 6772 | GIM_Reject, |
| 6773 | // Label 416: @15666 |
| 6774 | GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(15780), |
| 6775 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 6776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 6777 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6778 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 6780 | GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(15734), // Rule ID 51520 // |
| 6781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6782 | // (mul:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 6783 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 6784 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6785 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6786 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6789 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6790 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6791 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6795 | GIR_RootConstrainSelectedInstOperands, |
| 6796 | // GIR_Coverage, 51520, |
| 6797 | GIR_EraseRootFromParent_Done, |
| 6798 | // Label 479: @15734 |
| 6799 | GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(15779), // Rule ID 51521 // |
| 6800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6801 | // (mul:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 6802 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 6803 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6804 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6805 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), |
| 6807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6808 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6809 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6810 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6814 | GIR_RootConstrainSelectedInstOperands, |
| 6815 | // GIR_Coverage, 51521, |
| 6816 | GIR_EraseRootFromParent_Done, |
| 6817 | // Label 480: @15779 |
| 6818 | GIM_Reject, |
| 6819 | // Label 478: @15780 |
| 6820 | GIM_Reject, |
| 6821 | // Label 417: @15781 |
| 6822 | GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(15895), |
| 6823 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 6824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 6825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6828 | GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(15849), // Rule ID 51536 // |
| 6829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6830 | // (mul:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 6831 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 6832 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6833 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6834 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6837 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6838 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6839 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6843 | GIR_RootConstrainSelectedInstOperands, |
| 6844 | // GIR_Coverage, 51536, |
| 6845 | GIR_EraseRootFromParent_Done, |
| 6846 | // Label 482: @15849 |
| 6847 | GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(15894), // Rule ID 51537 // |
| 6848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6849 | // (mul:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 6850 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 6851 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6852 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6856 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6857 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6858 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6862 | GIR_RootConstrainSelectedInstOperands, |
| 6863 | // GIR_Coverage, 51537, |
| 6864 | GIR_EraseRootFromParent_Done, |
| 6865 | // Label 483: @15894 |
| 6866 | GIM_Reject, |
| 6867 | // Label 481: @15895 |
| 6868 | GIM_Reject, |
| 6869 | // Label 418: @15896 |
| 6870 | GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(16010), |
| 6871 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 6872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 6873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6875 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6876 | GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(15964), // Rule ID 51552 // |
| 6877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6878 | // (mul:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 6879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 6880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6881 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 6884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6885 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6886 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6887 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6891 | GIR_RootConstrainSelectedInstOperands, |
| 6892 | // GIR_Coverage, 51552, |
| 6893 | GIR_EraseRootFromParent_Done, |
| 6894 | // Label 485: @15964 |
| 6895 | GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(16009), // Rule ID 51553 // |
| 6896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6897 | // (mul:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 6898 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 6899 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6900 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 6903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6904 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6905 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6906 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 6909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6910 | GIR_RootConstrainSelectedInstOperands, |
| 6911 | // GIR_Coverage, 51553, |
| 6912 | GIR_EraseRootFromParent_Done, |
| 6913 | // Label 486: @16009 |
| 6914 | GIM_Reject, |
| 6915 | // Label 484: @16010 |
| 6916 | GIM_Reject, |
| 6917 | // Label 419: @16011 |
| 6918 | GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(16125), |
| 6919 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 6920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 6921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 6924 | GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(16079), // Rule ID 51524 // |
| 6925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6926 | // (mul:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 6927 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 6928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6933 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6934 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6935 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6939 | GIR_RootConstrainSelectedInstOperands, |
| 6940 | // GIR_Coverage, 51524, |
| 6941 | GIR_EraseRootFromParent_Done, |
| 6942 | // Label 488: @16079 |
| 6943 | GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(16124), // Rule ID 51525 // |
| 6944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6945 | // (mul:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 6946 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 6947 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6948 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6949 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), |
| 6951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6952 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6953 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6954 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6958 | GIR_RootConstrainSelectedInstOperands, |
| 6959 | // GIR_Coverage, 51525, |
| 6960 | GIR_EraseRootFromParent_Done, |
| 6961 | // Label 489: @16124 |
| 6962 | GIM_Reject, |
| 6963 | // Label 487: @16125 |
| 6964 | GIM_Reject, |
| 6965 | // Label 420: @16126 |
| 6966 | GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(16240), |
| 6967 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 6968 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 6969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6971 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 6972 | GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(16194), // Rule ID 51540 // |
| 6973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 6974 | // (mul:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 6975 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 6976 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6977 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 6980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 6981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6982 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 6983 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 6984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 6985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 6986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 6987 | GIR_RootConstrainSelectedInstOperands, |
| 6988 | // GIR_Coverage, 51540, |
| 6989 | GIR_EraseRootFromParent_Done, |
| 6990 | // Label 491: @16194 |
| 6991 | GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(16239), // Rule ID 51541 // |
| 6992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 6993 | // (mul:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 6994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 6995 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6996 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 6999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7000 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7001 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7002 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7006 | GIR_RootConstrainSelectedInstOperands, |
| 7007 | // GIR_Coverage, 51541, |
| 7008 | GIR_EraseRootFromParent_Done, |
| 7009 | // Label 492: @16239 |
| 7010 | GIM_Reject, |
| 7011 | // Label 490: @16240 |
| 7012 | GIM_Reject, |
| 7013 | // Label 421: @16241 |
| 7014 | GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(16355), |
| 7015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 7016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 7017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 7018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 7019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 7020 | GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(16309), // Rule ID 51528 // |
| 7021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7022 | // (mul:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 7023 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 7024 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7025 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 7028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7029 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7030 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7031 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7035 | GIR_RootConstrainSelectedInstOperands, |
| 7036 | // GIR_Coverage, 51528, |
| 7037 | GIR_EraseRootFromParent_Done, |
| 7038 | // Label 494: @16309 |
| 7039 | GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(16354), // Rule ID 51529 // |
| 7040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7041 | // (mul:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 7042 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 7043 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7044 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), |
| 7047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7048 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7049 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7050 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7054 | GIR_RootConstrainSelectedInstOperands, |
| 7055 | // GIR_Coverage, 51529, |
| 7056 | GIR_EraseRootFromParent_Done, |
| 7057 | // Label 495: @16354 |
| 7058 | GIM_Reject, |
| 7059 | // Label 493: @16355 |
| 7060 | GIM_Reject, |
| 7061 | // Label 422: @16356 |
| 7062 | GIM_Reject, |
| 7063 | // Label 3: @16357 |
| 7064 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 520*/ GIMT_Encode4(19126), |
| 7065 | /*GILLT_s32*//*Label 496*/ GIMT_Encode4(16492), |
| 7066 | /*GILLT_s64*//*Label 497*/ GIMT_Encode4(16562), GIMT_Encode4(0), |
| 7067 | /*GILLT_nxv1s8*//*Label 498*/ GIMT_Encode4(16596), |
| 7068 | /*GILLT_nxv1s16*//*Label 499*/ GIMT_Encode4(16711), |
| 7069 | /*GILLT_nxv1s32*//*Label 500*/ GIMT_Encode4(16826), |
| 7070 | /*GILLT_nxv1s64*//*Label 501*/ GIMT_Encode4(16941), GIMT_Encode4(0), |
| 7071 | /*GILLT_nxv2s8*//*Label 502*/ GIMT_Encode4(17056), |
| 7072 | /*GILLT_nxv2s16*//*Label 503*/ GIMT_Encode4(17171), |
| 7073 | /*GILLT_nxv2s32*//*Label 504*/ GIMT_Encode4(17286), |
| 7074 | /*GILLT_nxv2s64*//*Label 505*/ GIMT_Encode4(17401), GIMT_Encode4(0), |
| 7075 | /*GILLT_nxv4s8*//*Label 506*/ GIMT_Encode4(17516), |
| 7076 | /*GILLT_nxv4s16*//*Label 507*/ GIMT_Encode4(17631), |
| 7077 | /*GILLT_nxv4s32*//*Label 508*/ GIMT_Encode4(17746), |
| 7078 | /*GILLT_nxv4s64*//*Label 509*/ GIMT_Encode4(17861), GIMT_Encode4(0), |
| 7079 | /*GILLT_nxv8s8*//*Label 510*/ GIMT_Encode4(17976), |
| 7080 | /*GILLT_nxv8s16*//*Label 511*/ GIMT_Encode4(18091), |
| 7081 | /*GILLT_nxv8s32*//*Label 512*/ GIMT_Encode4(18206), |
| 7082 | /*GILLT_nxv8s64*//*Label 513*/ GIMT_Encode4(18321), GIMT_Encode4(0), |
| 7083 | /*GILLT_nxv16s8*//*Label 514*/ GIMT_Encode4(18436), |
| 7084 | /*GILLT_nxv16s16*//*Label 515*/ GIMT_Encode4(18551), |
| 7085 | /*GILLT_nxv16s32*//*Label 516*/ GIMT_Encode4(18666), GIMT_Encode4(0), |
| 7086 | /*GILLT_nxv32s8*//*Label 517*/ GIMT_Encode4(18781), |
| 7087 | /*GILLT_nxv32s16*//*Label 518*/ GIMT_Encode4(18896), GIMT_Encode4(0), |
| 7088 | /*GILLT_nxv64s8*//*Label 519*/ GIMT_Encode4(19011), |
| 7089 | // Label 496: @16492 |
| 7090 | GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(16561), |
| 7091 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 7092 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 7093 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 7094 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 7095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 7096 | GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(16530), // Rule ID 333 // |
| 7097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), |
| 7098 | // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 7099 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIV), |
| 7100 | GIR_RootConstrainSelectedInstOperands, |
| 7101 | // GIR_Coverage, 333, |
| 7102 | GIR_Done, |
| 7103 | // Label 522: @16530 |
| 7104 | GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(16545), // Rule ID 350 // |
| 7105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), |
| 7106 | // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 7107 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVW), |
| 7108 | GIR_RootConstrainSelectedInstOperands, |
| 7109 | // GIR_Coverage, 350, |
| 7110 | GIR_Done, |
| 7111 | // Label 523: @16545 |
| 7112 | GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(16560), // Rule ID 351 // |
| 7113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), |
| 7114 | // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 7115 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVW), |
| 7116 | GIR_RootConstrainSelectedInstOperands, |
| 7117 | // GIR_Coverage, 351, |
| 7118 | GIR_Done, |
| 7119 | // Label 524: @16560 |
| 7120 | GIM_Reject, |
| 7121 | // Label 521: @16561 |
| 7122 | GIM_Reject, |
| 7123 | // Label 497: @16562 |
| 7124 | GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(16595), // Rule ID 332 // |
| 7125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), |
| 7126 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 7127 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 7128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 7129 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 7130 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 7131 | // (sdiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 7132 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIV), |
| 7133 | GIR_RootConstrainSelectedInstOperands, |
| 7134 | // GIR_Coverage, 332, |
| 7135 | GIR_Done, |
| 7136 | // Label 525: @16595 |
| 7137 | GIM_Reject, |
| 7138 | // Label 498: @16596 |
| 7139 | GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(16710), |
| 7140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 7141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 7142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7144 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7145 | GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(16664), // Rule ID 51832 // |
| 7146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7147 | // (sdiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIV_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 7148 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 7149 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7150 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF8_E8), |
| 7153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7154 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7156 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7160 | GIR_RootConstrainSelectedInstOperands, |
| 7161 | // GIR_Coverage, 51832, |
| 7162 | GIR_EraseRootFromParent_Done, |
| 7163 | // Label 527: @16664 |
| 7164 | GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(16709), // Rule ID 51833 // |
| 7165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7166 | // (sdiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIV_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 7167 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 7168 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7169 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF8_E8), |
| 7172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7174 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7175 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7179 | GIR_RootConstrainSelectedInstOperands, |
| 7180 | // GIR_Coverage, 51833, |
| 7181 | GIR_EraseRootFromParent_Done, |
| 7182 | // Label 528: @16709 |
| 7183 | GIM_Reject, |
| 7184 | // Label 526: @16710 |
| 7185 | GIM_Reject, |
| 7186 | // Label 499: @16711 |
| 7187 | GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(16825), |
| 7188 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 7189 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 7190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7191 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7192 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7193 | GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(16779), // Rule ID 51844 // |
| 7194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7195 | // (sdiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIV_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 7196 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 7197 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7198 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7199 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E16), |
| 7201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7202 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7203 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7204 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7208 | GIR_RootConstrainSelectedInstOperands, |
| 7209 | // GIR_Coverage, 51844, |
| 7210 | GIR_EraseRootFromParent_Done, |
| 7211 | // Label 530: @16779 |
| 7212 | GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(16824), // Rule ID 51845 // |
| 7213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7214 | // (sdiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIV_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 7215 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 7216 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7217 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7218 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E16), |
| 7220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7221 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7222 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7223 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7227 | GIR_RootConstrainSelectedInstOperands, |
| 7228 | // GIR_Coverage, 51845, |
| 7229 | GIR_EraseRootFromParent_Done, |
| 7230 | // Label 531: @16824 |
| 7231 | GIM_Reject, |
| 7232 | // Label 529: @16825 |
| 7233 | GIM_Reject, |
| 7234 | // Label 500: @16826 |
| 7235 | GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(16940), |
| 7236 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 7237 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 7238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7241 | GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(16894), // Rule ID 51852 // |
| 7242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7243 | // (sdiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIV_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 7244 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 7245 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7246 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E32), |
| 7249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7250 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7251 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7252 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7256 | GIR_RootConstrainSelectedInstOperands, |
| 7257 | // GIR_Coverage, 51852, |
| 7258 | GIR_EraseRootFromParent_Done, |
| 7259 | // Label 533: @16894 |
| 7260 | GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(16939), // Rule ID 51853 // |
| 7261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7262 | // (sdiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIV_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 7263 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 7264 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7265 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E32), |
| 7268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7269 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7270 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7271 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7275 | GIR_RootConstrainSelectedInstOperands, |
| 7276 | // GIR_Coverage, 51853, |
| 7277 | GIR_EraseRootFromParent_Done, |
| 7278 | // Label 534: @16939 |
| 7279 | GIM_Reject, |
| 7280 | // Label 532: @16940 |
| 7281 | GIM_Reject, |
| 7282 | // Label 501: @16941 |
| 7283 | GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(17055), |
| 7284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 7285 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 7286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7287 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7288 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7289 | GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(17009), // Rule ID 51868 // |
| 7290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 7291 | // (sdiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIV_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 7292 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 7293 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7294 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7295 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E64), |
| 7297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7298 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7299 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7300 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7304 | GIR_RootConstrainSelectedInstOperands, |
| 7305 | // GIR_Coverage, 51868, |
| 7306 | GIR_EraseRootFromParent_Done, |
| 7307 | // Label 536: @17009 |
| 7308 | GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(17054), // Rule ID 51869 // |
| 7309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 7310 | // (sdiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIV_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 7311 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 7312 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7313 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E64), |
| 7316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7317 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7318 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7319 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7323 | GIR_RootConstrainSelectedInstOperands, |
| 7324 | // GIR_Coverage, 51869, |
| 7325 | GIR_EraseRootFromParent_Done, |
| 7326 | // Label 537: @17054 |
| 7327 | GIM_Reject, |
| 7328 | // Label 535: @17055 |
| 7329 | GIM_Reject, |
| 7330 | // Label 502: @17056 |
| 7331 | GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(17170), |
| 7332 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 7333 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 7334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7335 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7336 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7337 | GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(17124), // Rule ID 51836 // |
| 7338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7339 | // (sdiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIV_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 7340 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 7341 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7342 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E8), |
| 7345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7346 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7347 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7348 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7352 | GIR_RootConstrainSelectedInstOperands, |
| 7353 | // GIR_Coverage, 51836, |
| 7354 | GIR_EraseRootFromParent_Done, |
| 7355 | // Label 539: @17124 |
| 7356 | GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(17169), // Rule ID 51837 // |
| 7357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7358 | // (sdiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIV_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 7359 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 7360 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7361 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E8), |
| 7364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7365 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7366 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7367 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7371 | GIR_RootConstrainSelectedInstOperands, |
| 7372 | // GIR_Coverage, 51837, |
| 7373 | GIR_EraseRootFromParent_Done, |
| 7374 | // Label 540: @17169 |
| 7375 | GIM_Reject, |
| 7376 | // Label 538: @17170 |
| 7377 | GIM_Reject, |
| 7378 | // Label 503: @17171 |
| 7379 | GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(17285), |
| 7380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 7381 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 7382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7383 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7384 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7385 | GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(17239), // Rule ID 51848 // |
| 7386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7387 | // (sdiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIV_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 7388 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 7389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E16), |
| 7393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7394 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7395 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7396 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7400 | GIR_RootConstrainSelectedInstOperands, |
| 7401 | // GIR_Coverage, 51848, |
| 7402 | GIR_EraseRootFromParent_Done, |
| 7403 | // Label 542: @17239 |
| 7404 | GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(17284), // Rule ID 51849 // |
| 7405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7406 | // (sdiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIV_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 7407 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 7408 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7409 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E16), |
| 7412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7413 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7414 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7415 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7419 | GIR_RootConstrainSelectedInstOperands, |
| 7420 | // GIR_Coverage, 51849, |
| 7421 | GIR_EraseRootFromParent_Done, |
| 7422 | // Label 543: @17284 |
| 7423 | GIM_Reject, |
| 7424 | // Label 541: @17285 |
| 7425 | GIM_Reject, |
| 7426 | // Label 504: @17286 |
| 7427 | GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(17400), |
| 7428 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 7429 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 7430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7431 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7432 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7433 | GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(17354), // Rule ID 51864 // |
| 7434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7435 | // (sdiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIV_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 7436 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 7437 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7438 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E32), |
| 7441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7443 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7444 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7448 | GIR_RootConstrainSelectedInstOperands, |
| 7449 | // GIR_Coverage, 51864, |
| 7450 | GIR_EraseRootFromParent_Done, |
| 7451 | // Label 545: @17354 |
| 7452 | GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(17399), // Rule ID 51865 // |
| 7453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7454 | // (sdiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIV_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 7455 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 7456 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7457 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E32), |
| 7460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7462 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7463 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7467 | GIR_RootConstrainSelectedInstOperands, |
| 7468 | // GIR_Coverage, 51865, |
| 7469 | GIR_EraseRootFromParent_Done, |
| 7470 | // Label 546: @17399 |
| 7471 | GIM_Reject, |
| 7472 | // Label 544: @17400 |
| 7473 | GIM_Reject, |
| 7474 | // Label 505: @17401 |
| 7475 | GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(17515), |
| 7476 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 7477 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 7478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7479 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7480 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7481 | GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(17469), // Rule ID 51908 // |
| 7482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 7483 | // (sdiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIV_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 7484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 7485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E64), |
| 7489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7490 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7491 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7492 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7496 | GIR_RootConstrainSelectedInstOperands, |
| 7497 | // GIR_Coverage, 51908, |
| 7498 | GIR_EraseRootFromParent_Done, |
| 7499 | // Label 548: @17469 |
| 7500 | GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(17514), // Rule ID 51909 // |
| 7501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 7502 | // (sdiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIV_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 7503 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 7504 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7505 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7506 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E64), |
| 7508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7509 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7510 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7511 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7515 | GIR_RootConstrainSelectedInstOperands, |
| 7516 | // GIR_Coverage, 51909, |
| 7517 | GIR_EraseRootFromParent_Done, |
| 7518 | // Label 549: @17514 |
| 7519 | GIM_Reject, |
| 7520 | // Label 547: @17515 |
| 7521 | GIM_Reject, |
| 7522 | // Label 506: @17516 |
| 7523 | GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(17630), |
| 7524 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 7525 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 7526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7527 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7528 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7529 | GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(17584), // Rule ID 51840 // |
| 7530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7531 | // (sdiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIV_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 7532 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 7533 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7534 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E8), |
| 7537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7539 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7540 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7544 | GIR_RootConstrainSelectedInstOperands, |
| 7545 | // GIR_Coverage, 51840, |
| 7546 | GIR_EraseRootFromParent_Done, |
| 7547 | // Label 551: @17584 |
| 7548 | GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(17629), // Rule ID 51841 // |
| 7549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7550 | // (sdiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIV_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 7551 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 7552 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7553 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7554 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E8), |
| 7556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7557 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7558 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7559 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7563 | GIR_RootConstrainSelectedInstOperands, |
| 7564 | // GIR_Coverage, 51841, |
| 7565 | GIR_EraseRootFromParent_Done, |
| 7566 | // Label 552: @17629 |
| 7567 | GIM_Reject, |
| 7568 | // Label 550: @17630 |
| 7569 | GIM_Reject, |
| 7570 | // Label 507: @17631 |
| 7571 | GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(17745), |
| 7572 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 7573 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 7574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7575 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7576 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7577 | GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(17699), // Rule ID 51860 // |
| 7578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7579 | // (sdiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIV_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 7580 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 7581 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7582 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E16), |
| 7585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7586 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7587 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7588 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7592 | GIR_RootConstrainSelectedInstOperands, |
| 7593 | // GIR_Coverage, 51860, |
| 7594 | GIR_EraseRootFromParent_Done, |
| 7595 | // Label 554: @17699 |
| 7596 | GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(17744), // Rule ID 51861 // |
| 7597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7598 | // (sdiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIV_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 7599 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 7600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7602 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E16), |
| 7604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7605 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7606 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7607 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7611 | GIR_RootConstrainSelectedInstOperands, |
| 7612 | // GIR_Coverage, 51861, |
| 7613 | GIR_EraseRootFromParent_Done, |
| 7614 | // Label 555: @17744 |
| 7615 | GIM_Reject, |
| 7616 | // Label 553: @17745 |
| 7617 | GIM_Reject, |
| 7618 | // Label 508: @17746 |
| 7619 | GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(17860), |
| 7620 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 7621 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 7622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7624 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7625 | GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(17814), // Rule ID 51896 // |
| 7626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7627 | // (sdiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIV_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 7628 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 7629 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7630 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E32), |
| 7633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7634 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7635 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7636 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7640 | GIR_RootConstrainSelectedInstOperands, |
| 7641 | // GIR_Coverage, 51896, |
| 7642 | GIR_EraseRootFromParent_Done, |
| 7643 | // Label 557: @17814 |
| 7644 | GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(17859), // Rule ID 51897 // |
| 7645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7646 | // (sdiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIV_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 7647 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 7648 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E32), |
| 7652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7654 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7655 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7659 | GIR_RootConstrainSelectedInstOperands, |
| 7660 | // GIR_Coverage, 51897, |
| 7661 | GIR_EraseRootFromParent_Done, |
| 7662 | // Label 558: @17859 |
| 7663 | GIM_Reject, |
| 7664 | // Label 556: @17860 |
| 7665 | GIM_Reject, |
| 7666 | // Label 509: @17861 |
| 7667 | GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(17975), |
| 7668 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 7669 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 7670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7672 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7673 | GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(17929), // Rule ID 51912 // |
| 7674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 7675 | // (sdiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIV_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 7676 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 7677 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7678 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E64), |
| 7681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7682 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7683 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7684 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7688 | GIR_RootConstrainSelectedInstOperands, |
| 7689 | // GIR_Coverage, 51912, |
| 7690 | GIR_EraseRootFromParent_Done, |
| 7691 | // Label 560: @17929 |
| 7692 | GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(17974), // Rule ID 51913 // |
| 7693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 7694 | // (sdiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIV_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 7695 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 7696 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7697 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E64), |
| 7700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7701 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7702 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7703 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7707 | GIR_RootConstrainSelectedInstOperands, |
| 7708 | // GIR_Coverage, 51913, |
| 7709 | GIR_EraseRootFromParent_Done, |
| 7710 | // Label 561: @17974 |
| 7711 | GIM_Reject, |
| 7712 | // Label 559: @17975 |
| 7713 | GIM_Reject, |
| 7714 | // Label 510: @17976 |
| 7715 | GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(18090), |
| 7716 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 7717 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 7718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7719 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7720 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 7721 | GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(18044), // Rule ID 51856 // |
| 7722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7723 | // (sdiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIV_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 7724 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 7725 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7726 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7727 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E8), |
| 7729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7730 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7731 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7732 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7736 | GIR_RootConstrainSelectedInstOperands, |
| 7737 | // GIR_Coverage, 51856, |
| 7738 | GIR_EraseRootFromParent_Done, |
| 7739 | // Label 563: @18044 |
| 7740 | GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(18089), // Rule ID 51857 // |
| 7741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7742 | // (sdiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIV_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 7743 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 7744 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7745 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7746 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E8), |
| 7748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7749 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7750 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7751 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7755 | GIR_RootConstrainSelectedInstOperands, |
| 7756 | // GIR_Coverage, 51857, |
| 7757 | GIR_EraseRootFromParent_Done, |
| 7758 | // Label 564: @18089 |
| 7759 | GIM_Reject, |
| 7760 | // Label 562: @18090 |
| 7761 | GIM_Reject, |
| 7762 | // Label 511: @18091 |
| 7763 | GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(18205), |
| 7764 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 7765 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 7766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7767 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7768 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7769 | GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(18159), // Rule ID 51884 // |
| 7770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7771 | // (sdiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIV_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 7772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 7773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7774 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E16), |
| 7777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7778 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7779 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7780 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7784 | GIR_RootConstrainSelectedInstOperands, |
| 7785 | // GIR_Coverage, 51884, |
| 7786 | GIR_EraseRootFromParent_Done, |
| 7787 | // Label 566: @18159 |
| 7788 | GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(18204), // Rule ID 51885 // |
| 7789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7790 | // (sdiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIV_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 7791 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 7792 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7793 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7794 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E16), |
| 7796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7797 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7798 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7799 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7803 | GIR_RootConstrainSelectedInstOperands, |
| 7804 | // GIR_Coverage, 51885, |
| 7805 | GIR_EraseRootFromParent_Done, |
| 7806 | // Label 567: @18204 |
| 7807 | GIM_Reject, |
| 7808 | // Label 565: @18205 |
| 7809 | GIM_Reject, |
| 7810 | // Label 512: @18206 |
| 7811 | GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(18320), |
| 7812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 7813 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 7814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7816 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7817 | GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(18274), // Rule ID 51900 // |
| 7818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7819 | // (sdiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIV_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 7820 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 7821 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7822 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E32), |
| 7825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7826 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7827 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7828 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7832 | GIR_RootConstrainSelectedInstOperands, |
| 7833 | // GIR_Coverage, 51900, |
| 7834 | GIR_EraseRootFromParent_Done, |
| 7835 | // Label 569: @18274 |
| 7836 | GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(18319), // Rule ID 51901 // |
| 7837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7838 | // (sdiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIV_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 7839 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 7840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E32), |
| 7844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7845 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7846 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7847 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 7850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7851 | GIR_RootConstrainSelectedInstOperands, |
| 7852 | // GIR_Coverage, 51901, |
| 7853 | GIR_EraseRootFromParent_Done, |
| 7854 | // Label 570: @18319 |
| 7855 | GIM_Reject, |
| 7856 | // Label 568: @18320 |
| 7857 | GIM_Reject, |
| 7858 | // Label 513: @18321 |
| 7859 | GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(18435), |
| 7860 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 7861 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 7862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 7863 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 7864 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 7865 | GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(18389), // Rule ID 51916 // |
| 7866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 7867 | // (sdiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIV_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 7868 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 7869 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7870 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E64), |
| 7873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7874 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7875 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7876 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7880 | GIR_RootConstrainSelectedInstOperands, |
| 7881 | // GIR_Coverage, 51916, |
| 7882 | GIR_EraseRootFromParent_Done, |
| 7883 | // Label 572: @18389 |
| 7884 | GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(18434), // Rule ID 51917 // |
| 7885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 7886 | // (sdiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIV_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 7887 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 7888 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7889 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E64), |
| 7892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7893 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7894 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7895 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 7898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7899 | GIR_RootConstrainSelectedInstOperands, |
| 7900 | // GIR_Coverage, 51917, |
| 7901 | GIR_EraseRootFromParent_Done, |
| 7902 | // Label 573: @18434 |
| 7903 | GIM_Reject, |
| 7904 | // Label 571: @18435 |
| 7905 | GIM_Reject, |
| 7906 | // Label 514: @18436 |
| 7907 | GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(18550), |
| 7908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 7909 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 7910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7911 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 7913 | GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(18504), // Rule ID 51872 // |
| 7914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7915 | // (sdiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIV_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 7916 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 7917 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7918 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7919 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E8), |
| 7921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7922 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7923 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7924 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7928 | GIR_RootConstrainSelectedInstOperands, |
| 7929 | // GIR_Coverage, 51872, |
| 7930 | GIR_EraseRootFromParent_Done, |
| 7931 | // Label 575: @18504 |
| 7932 | GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(18549), // Rule ID 51873 // |
| 7933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7934 | // (sdiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIV_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 7935 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 7936 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7937 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E8), |
| 7940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7941 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7942 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7943 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7947 | GIR_RootConstrainSelectedInstOperands, |
| 7948 | // GIR_Coverage, 51873, |
| 7949 | GIR_EraseRootFromParent_Done, |
| 7950 | // Label 576: @18549 |
| 7951 | GIM_Reject, |
| 7952 | // Label 574: @18550 |
| 7953 | GIM_Reject, |
| 7954 | // Label 515: @18551 |
| 7955 | GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(18665), |
| 7956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 7957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 7958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7960 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 7961 | GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(18619), // Rule ID 51888 // |
| 7962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 7963 | // (sdiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIV_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 7964 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 7965 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7966 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E16), |
| 7969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7970 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7971 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7972 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7976 | GIR_RootConstrainSelectedInstOperands, |
| 7977 | // GIR_Coverage, 51888, |
| 7978 | GIR_EraseRootFromParent_Done, |
| 7979 | // Label 578: @18619 |
| 7980 | GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(18664), // Rule ID 51889 // |
| 7981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 7982 | // (sdiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIV_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 7983 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 7984 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7985 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E16), |
| 7988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 7989 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7990 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 7991 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 7992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 7993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 7994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 7995 | GIR_RootConstrainSelectedInstOperands, |
| 7996 | // GIR_Coverage, 51889, |
| 7997 | GIR_EraseRootFromParent_Done, |
| 7998 | // Label 579: @18664 |
| 7999 | GIM_Reject, |
| 8000 | // Label 577: @18665 |
| 8001 | GIM_Reject, |
| 8002 | // Label 516: @18666 |
| 8003 | GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(18780), |
| 8004 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 8005 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 8006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8007 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8008 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8009 | GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(18734), // Rule ID 51904 // |
| 8010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8011 | // (sdiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIV_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 8012 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 8013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E32), |
| 8017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8018 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8019 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8020 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8024 | GIR_RootConstrainSelectedInstOperands, |
| 8025 | // GIR_Coverage, 51904, |
| 8026 | GIR_EraseRootFromParent_Done, |
| 8027 | // Label 581: @18734 |
| 8028 | GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(18779), // Rule ID 51905 // |
| 8029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8030 | // (sdiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIV_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 8031 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 8032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8033 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8034 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E32), |
| 8036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8037 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8038 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8039 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8043 | GIR_RootConstrainSelectedInstOperands, |
| 8044 | // GIR_Coverage, 51905, |
| 8045 | GIR_EraseRootFromParent_Done, |
| 8046 | // Label 582: @18779 |
| 8047 | GIM_Reject, |
| 8048 | // Label 580: @18780 |
| 8049 | GIM_Reject, |
| 8050 | // Label 517: @18781 |
| 8051 | GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(18895), |
| 8052 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 8053 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 8054 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8055 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8056 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8057 | GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(18849), // Rule ID 51876 // |
| 8058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8059 | // (sdiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIV_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 8060 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 8061 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8062 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E8), |
| 8065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8066 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8067 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8068 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8072 | GIR_RootConstrainSelectedInstOperands, |
| 8073 | // GIR_Coverage, 51876, |
| 8074 | GIR_EraseRootFromParent_Done, |
| 8075 | // Label 584: @18849 |
| 8076 | GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(18894), // Rule ID 51877 // |
| 8077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8078 | // (sdiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIV_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 8079 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 8080 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8081 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8082 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E8), |
| 8084 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8085 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8086 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8087 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8091 | GIR_RootConstrainSelectedInstOperands, |
| 8092 | // GIR_Coverage, 51877, |
| 8093 | GIR_EraseRootFromParent_Done, |
| 8094 | // Label 585: @18894 |
| 8095 | GIM_Reject, |
| 8096 | // Label 583: @18895 |
| 8097 | GIM_Reject, |
| 8098 | // Label 518: @18896 |
| 8099 | GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(19010), |
| 8100 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 8101 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 8102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8103 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8104 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8105 | GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(18964), // Rule ID 51892 // |
| 8106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8107 | // (sdiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIV_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 8108 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 8109 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8110 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8111 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E16), |
| 8113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8114 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8115 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8116 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8120 | GIR_RootConstrainSelectedInstOperands, |
| 8121 | // GIR_Coverage, 51892, |
| 8122 | GIR_EraseRootFromParent_Done, |
| 8123 | // Label 587: @18964 |
| 8124 | GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(19009), // Rule ID 51893 // |
| 8125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8126 | // (sdiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIV_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 8127 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 8128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E16), |
| 8132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8133 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8134 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8135 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8139 | GIR_RootConstrainSelectedInstOperands, |
| 8140 | // GIR_Coverage, 51893, |
| 8141 | GIR_EraseRootFromParent_Done, |
| 8142 | // Label 588: @19009 |
| 8143 | GIM_Reject, |
| 8144 | // Label 586: @19010 |
| 8145 | GIM_Reject, |
| 8146 | // Label 519: @19011 |
| 8147 | GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(19125), |
| 8148 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 8149 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 8150 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8151 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8152 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8153 | GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(19079), // Rule ID 51880 // |
| 8154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8155 | // (sdiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIV_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 8156 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 8157 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8158 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E8), |
| 8161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8162 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8163 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8164 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8168 | GIR_RootConstrainSelectedInstOperands, |
| 8169 | // GIR_Coverage, 51880, |
| 8170 | GIR_EraseRootFromParent_Done, |
| 8171 | // Label 590: @19079 |
| 8172 | GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(19124), // Rule ID 51881 // |
| 8173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8174 | // (sdiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIV_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 8175 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 8176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E8), |
| 8180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8181 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8182 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8183 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8187 | GIR_RootConstrainSelectedInstOperands, |
| 8188 | // GIR_Coverage, 51881, |
| 8189 | GIR_EraseRootFromParent_Done, |
| 8190 | // Label 591: @19124 |
| 8191 | GIM_Reject, |
| 8192 | // Label 589: @19125 |
| 8193 | GIM_Reject, |
| 8194 | // Label 520: @19126 |
| 8195 | GIM_Reject, |
| 8196 | // Label 4: @19127 |
| 8197 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 616*/ GIMT_Encode4(21896), |
| 8198 | /*GILLT_s32*//*Label 592*/ GIMT_Encode4(19262), |
| 8199 | /*GILLT_s64*//*Label 593*/ GIMT_Encode4(19332), GIMT_Encode4(0), |
| 8200 | /*GILLT_nxv1s8*//*Label 594*/ GIMT_Encode4(19366), |
| 8201 | /*GILLT_nxv1s16*//*Label 595*/ GIMT_Encode4(19481), |
| 8202 | /*GILLT_nxv1s32*//*Label 596*/ GIMT_Encode4(19596), |
| 8203 | /*GILLT_nxv1s64*//*Label 597*/ GIMT_Encode4(19711), GIMT_Encode4(0), |
| 8204 | /*GILLT_nxv2s8*//*Label 598*/ GIMT_Encode4(19826), |
| 8205 | /*GILLT_nxv2s16*//*Label 599*/ GIMT_Encode4(19941), |
| 8206 | /*GILLT_nxv2s32*//*Label 600*/ GIMT_Encode4(20056), |
| 8207 | /*GILLT_nxv2s64*//*Label 601*/ GIMT_Encode4(20171), GIMT_Encode4(0), |
| 8208 | /*GILLT_nxv4s8*//*Label 602*/ GIMT_Encode4(20286), |
| 8209 | /*GILLT_nxv4s16*//*Label 603*/ GIMT_Encode4(20401), |
| 8210 | /*GILLT_nxv4s32*//*Label 604*/ GIMT_Encode4(20516), |
| 8211 | /*GILLT_nxv4s64*//*Label 605*/ GIMT_Encode4(20631), GIMT_Encode4(0), |
| 8212 | /*GILLT_nxv8s8*//*Label 606*/ GIMT_Encode4(20746), |
| 8213 | /*GILLT_nxv8s16*//*Label 607*/ GIMT_Encode4(20861), |
| 8214 | /*GILLT_nxv8s32*//*Label 608*/ GIMT_Encode4(20976), |
| 8215 | /*GILLT_nxv8s64*//*Label 609*/ GIMT_Encode4(21091), GIMT_Encode4(0), |
| 8216 | /*GILLT_nxv16s8*//*Label 610*/ GIMT_Encode4(21206), |
| 8217 | /*GILLT_nxv16s16*//*Label 611*/ GIMT_Encode4(21321), |
| 8218 | /*GILLT_nxv16s32*//*Label 612*/ GIMT_Encode4(21436), GIMT_Encode4(0), |
| 8219 | /*GILLT_nxv32s8*//*Label 613*/ GIMT_Encode4(21551), |
| 8220 | /*GILLT_nxv32s16*//*Label 614*/ GIMT_Encode4(21666), GIMT_Encode4(0), |
| 8221 | /*GILLT_nxv64s8*//*Label 615*/ GIMT_Encode4(21781), |
| 8222 | // Label 592: @19262 |
| 8223 | GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(19331), |
| 8224 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 8225 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 8227 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 8228 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 8229 | GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(19300), // Rule ID 335 // |
| 8230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), |
| 8231 | // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 8232 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVU), |
| 8233 | GIR_RootConstrainSelectedInstOperands, |
| 8234 | // GIR_Coverage, 335, |
| 8235 | GIR_Done, |
| 8236 | // Label 618: @19300 |
| 8237 | GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(19315), // Rule ID 352 // |
| 8238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), |
| 8239 | // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 8240 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVUW), |
| 8241 | GIR_RootConstrainSelectedInstOperands, |
| 8242 | // GIR_Coverage, 352, |
| 8243 | GIR_Done, |
| 8244 | // Label 619: @19315 |
| 8245 | GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(19330), // Rule ID 353 // |
| 8246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), |
| 8247 | // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 8248 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVUW), |
| 8249 | GIR_RootConstrainSelectedInstOperands, |
| 8250 | // GIR_Coverage, 353, |
| 8251 | GIR_Done, |
| 8252 | // Label 620: @19330 |
| 8253 | GIM_Reject, |
| 8254 | // Label 617: @19331 |
| 8255 | GIM_Reject, |
| 8256 | // Label 593: @19332 |
| 8257 | GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(19365), // Rule ID 334 // |
| 8258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), |
| 8259 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 8262 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 8263 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 8264 | // (udiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 8265 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVU), |
| 8266 | GIR_RootConstrainSelectedInstOperands, |
| 8267 | // GIR_Coverage, 334, |
| 8268 | GIR_Done, |
| 8269 | // Label 621: @19365 |
| 8270 | GIM_Reject, |
| 8271 | // Label 594: @19366 |
| 8272 | GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(19480), |
| 8273 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 8274 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 8275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8277 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8278 | GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(19434), // Rule ID 51744 // |
| 8279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8280 | // (udiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIVU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 8281 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 8282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF8_E8), |
| 8286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8287 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8288 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8289 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8293 | GIR_RootConstrainSelectedInstOperands, |
| 8294 | // GIR_Coverage, 51744, |
| 8295 | GIR_EraseRootFromParent_Done, |
| 8296 | // Label 623: @19434 |
| 8297 | GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(19479), // Rule ID 51745 // |
| 8298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8299 | // (udiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIVU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 8300 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 8301 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8302 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF8_E8), |
| 8305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8306 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8307 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8308 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8312 | GIR_RootConstrainSelectedInstOperands, |
| 8313 | // GIR_Coverage, 51745, |
| 8314 | GIR_EraseRootFromParent_Done, |
| 8315 | // Label 624: @19479 |
| 8316 | GIM_Reject, |
| 8317 | // Label 622: @19480 |
| 8318 | GIM_Reject, |
| 8319 | // Label 595: @19481 |
| 8320 | GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(19595), |
| 8321 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 8322 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 8323 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8324 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8325 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8326 | GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(19549), // Rule ID 51756 // |
| 8327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8328 | // (udiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIVU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 8329 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 8330 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8331 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E16), |
| 8334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8335 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8336 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8337 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8341 | GIR_RootConstrainSelectedInstOperands, |
| 8342 | // GIR_Coverage, 51756, |
| 8343 | GIR_EraseRootFromParent_Done, |
| 8344 | // Label 626: @19549 |
| 8345 | GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(19594), // Rule ID 51757 // |
| 8346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8347 | // (udiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIVU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 8348 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 8349 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8350 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E16), |
| 8353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8354 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8355 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8356 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8360 | GIR_RootConstrainSelectedInstOperands, |
| 8361 | // GIR_Coverage, 51757, |
| 8362 | GIR_EraseRootFromParent_Done, |
| 8363 | // Label 627: @19594 |
| 8364 | GIM_Reject, |
| 8365 | // Label 625: @19595 |
| 8366 | GIM_Reject, |
| 8367 | // Label 596: @19596 |
| 8368 | GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(19710), |
| 8369 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 8370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 8371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8374 | GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(19664), // Rule ID 51764 // |
| 8375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8376 | // (udiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIVU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 8377 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 8378 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8379 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E32), |
| 8382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8383 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8384 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8385 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8389 | GIR_RootConstrainSelectedInstOperands, |
| 8390 | // GIR_Coverage, 51764, |
| 8391 | GIR_EraseRootFromParent_Done, |
| 8392 | // Label 629: @19664 |
| 8393 | GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(19709), // Rule ID 51765 // |
| 8394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8395 | // (udiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIVU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 8396 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 8397 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8398 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8399 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E32), |
| 8401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8402 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8403 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8404 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8408 | GIR_RootConstrainSelectedInstOperands, |
| 8409 | // GIR_Coverage, 51765, |
| 8410 | GIR_EraseRootFromParent_Done, |
| 8411 | // Label 630: @19709 |
| 8412 | GIM_Reject, |
| 8413 | // Label 628: @19710 |
| 8414 | GIM_Reject, |
| 8415 | // Label 597: @19711 |
| 8416 | GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(19825), |
| 8417 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 8418 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 8419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8420 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8421 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8422 | GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(19779), // Rule ID 51780 // |
| 8423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 8424 | // (udiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIVU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 8425 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 8426 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8427 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8428 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E64), |
| 8430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8431 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8432 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8433 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 8436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8437 | GIR_RootConstrainSelectedInstOperands, |
| 8438 | // GIR_Coverage, 51780, |
| 8439 | GIR_EraseRootFromParent_Done, |
| 8440 | // Label 632: @19779 |
| 8441 | GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(19824), // Rule ID 51781 // |
| 8442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 8443 | // (udiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIVU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 8444 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 8445 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8446 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E64), |
| 8449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8450 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8451 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8452 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 8455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8456 | GIR_RootConstrainSelectedInstOperands, |
| 8457 | // GIR_Coverage, 51781, |
| 8458 | GIR_EraseRootFromParent_Done, |
| 8459 | // Label 633: @19824 |
| 8460 | GIM_Reject, |
| 8461 | // Label 631: @19825 |
| 8462 | GIM_Reject, |
| 8463 | // Label 598: @19826 |
| 8464 | GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(19940), |
| 8465 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 8466 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 8467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8468 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8469 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8470 | GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(19894), // Rule ID 51748 // |
| 8471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8472 | // (udiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIVU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 8473 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 8474 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8475 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E8), |
| 8478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8479 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8480 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8481 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8485 | GIR_RootConstrainSelectedInstOperands, |
| 8486 | // GIR_Coverage, 51748, |
| 8487 | GIR_EraseRootFromParent_Done, |
| 8488 | // Label 635: @19894 |
| 8489 | GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(19939), // Rule ID 51749 // |
| 8490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8491 | // (udiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIVU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 8492 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 8493 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8494 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8495 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E8), |
| 8497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8498 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8499 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8500 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8504 | GIR_RootConstrainSelectedInstOperands, |
| 8505 | // GIR_Coverage, 51749, |
| 8506 | GIR_EraseRootFromParent_Done, |
| 8507 | // Label 636: @19939 |
| 8508 | GIM_Reject, |
| 8509 | // Label 634: @19940 |
| 8510 | GIM_Reject, |
| 8511 | // Label 599: @19941 |
| 8512 | GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(20055), |
| 8513 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 8514 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 8515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8516 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8517 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8518 | GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(20009), // Rule ID 51760 // |
| 8519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8520 | // (udiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIVU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 8521 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 8522 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8523 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E16), |
| 8526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8527 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8528 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8529 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8533 | GIR_RootConstrainSelectedInstOperands, |
| 8534 | // GIR_Coverage, 51760, |
| 8535 | GIR_EraseRootFromParent_Done, |
| 8536 | // Label 638: @20009 |
| 8537 | GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(20054), // Rule ID 51761 // |
| 8538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8539 | // (udiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIVU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 8540 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 8541 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8542 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E16), |
| 8545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8546 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8547 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8548 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8552 | GIR_RootConstrainSelectedInstOperands, |
| 8553 | // GIR_Coverage, 51761, |
| 8554 | GIR_EraseRootFromParent_Done, |
| 8555 | // Label 639: @20054 |
| 8556 | GIM_Reject, |
| 8557 | // Label 637: @20055 |
| 8558 | GIM_Reject, |
| 8559 | // Label 600: @20056 |
| 8560 | GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(20170), |
| 8561 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 8562 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 8563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8564 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8565 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8566 | GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(20124), // Rule ID 51776 // |
| 8567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8568 | // (udiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIVU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 8569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 8570 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8571 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E32), |
| 8574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8575 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8576 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8577 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8581 | GIR_RootConstrainSelectedInstOperands, |
| 8582 | // GIR_Coverage, 51776, |
| 8583 | GIR_EraseRootFromParent_Done, |
| 8584 | // Label 641: @20124 |
| 8585 | GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(20169), // Rule ID 51777 // |
| 8586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8587 | // (udiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIVU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 8588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 8589 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8590 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E32), |
| 8593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8595 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8596 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8600 | GIR_RootConstrainSelectedInstOperands, |
| 8601 | // GIR_Coverage, 51777, |
| 8602 | GIR_EraseRootFromParent_Done, |
| 8603 | // Label 642: @20169 |
| 8604 | GIM_Reject, |
| 8605 | // Label 640: @20170 |
| 8606 | GIM_Reject, |
| 8607 | // Label 601: @20171 |
| 8608 | GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(20285), |
| 8609 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 8610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 8611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8612 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8614 | GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(20239), // Rule ID 51820 // |
| 8615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 8616 | // (udiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIVU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 8617 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 8618 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8619 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E64), |
| 8622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8623 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8624 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8625 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 8628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8629 | GIR_RootConstrainSelectedInstOperands, |
| 8630 | // GIR_Coverage, 51820, |
| 8631 | GIR_EraseRootFromParent_Done, |
| 8632 | // Label 644: @20239 |
| 8633 | GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(20284), // Rule ID 51821 // |
| 8634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 8635 | // (udiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIVU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 8636 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 8637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8638 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E64), |
| 8641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8642 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8643 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8644 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 8647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8648 | GIR_RootConstrainSelectedInstOperands, |
| 8649 | // GIR_Coverage, 51821, |
| 8650 | GIR_EraseRootFromParent_Done, |
| 8651 | // Label 645: @20284 |
| 8652 | GIM_Reject, |
| 8653 | // Label 643: @20285 |
| 8654 | GIM_Reject, |
| 8655 | // Label 602: @20286 |
| 8656 | GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(20400), |
| 8657 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 8658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 8659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8660 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8662 | GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(20354), // Rule ID 51752 // |
| 8663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8664 | // (udiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIVU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 8665 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 8666 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8667 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8668 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E8), |
| 8670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8671 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8672 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8673 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8677 | GIR_RootConstrainSelectedInstOperands, |
| 8678 | // GIR_Coverage, 51752, |
| 8679 | GIR_EraseRootFromParent_Done, |
| 8680 | // Label 647: @20354 |
| 8681 | GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(20399), // Rule ID 51753 // |
| 8682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8683 | // (udiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIVU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 8684 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 8685 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8686 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E8), |
| 8689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8690 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8691 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8692 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8696 | GIR_RootConstrainSelectedInstOperands, |
| 8697 | // GIR_Coverage, 51753, |
| 8698 | GIR_EraseRootFromParent_Done, |
| 8699 | // Label 648: @20399 |
| 8700 | GIM_Reject, |
| 8701 | // Label 646: @20400 |
| 8702 | GIM_Reject, |
| 8703 | // Label 603: @20401 |
| 8704 | GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(20515), |
| 8705 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 8706 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 8707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8708 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8709 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8710 | GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(20469), // Rule ID 51772 // |
| 8711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8712 | // (udiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIVU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 8713 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 8714 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8715 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E16), |
| 8718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8719 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8720 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8721 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8725 | GIR_RootConstrainSelectedInstOperands, |
| 8726 | // GIR_Coverage, 51772, |
| 8727 | GIR_EraseRootFromParent_Done, |
| 8728 | // Label 650: @20469 |
| 8729 | GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(20514), // Rule ID 51773 // |
| 8730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8731 | // (udiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIVU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 8732 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 8733 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8734 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E16), |
| 8737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8738 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8739 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8740 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8744 | GIR_RootConstrainSelectedInstOperands, |
| 8745 | // GIR_Coverage, 51773, |
| 8746 | GIR_EraseRootFromParent_Done, |
| 8747 | // Label 651: @20514 |
| 8748 | GIM_Reject, |
| 8749 | // Label 649: @20515 |
| 8750 | GIM_Reject, |
| 8751 | // Label 604: @20516 |
| 8752 | GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(20630), |
| 8753 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 8754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 8755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8757 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8758 | GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(20584), // Rule ID 51808 // |
| 8759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8760 | // (udiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIVU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 8761 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 8762 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8763 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E32), |
| 8766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8768 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8769 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8773 | GIR_RootConstrainSelectedInstOperands, |
| 8774 | // GIR_Coverage, 51808, |
| 8775 | GIR_EraseRootFromParent_Done, |
| 8776 | // Label 653: @20584 |
| 8777 | GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(20629), // Rule ID 51809 // |
| 8778 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8779 | // (udiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIVU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 8780 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 8781 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8782 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E32), |
| 8785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8786 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8787 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8788 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8792 | GIR_RootConstrainSelectedInstOperands, |
| 8793 | // GIR_Coverage, 51809, |
| 8794 | GIR_EraseRootFromParent_Done, |
| 8795 | // Label 654: @20629 |
| 8796 | GIM_Reject, |
| 8797 | // Label 652: @20630 |
| 8798 | GIM_Reject, |
| 8799 | // Label 605: @20631 |
| 8800 | GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(20745), |
| 8801 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 8802 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 8803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8804 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8806 | GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(20699), // Rule ID 51824 // |
| 8807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 8808 | // (udiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIVU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 8809 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 8810 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8811 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8812 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E64), |
| 8814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8815 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8816 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8817 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 8820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8821 | GIR_RootConstrainSelectedInstOperands, |
| 8822 | // GIR_Coverage, 51824, |
| 8823 | GIR_EraseRootFromParent_Done, |
| 8824 | // Label 656: @20699 |
| 8825 | GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(20744), // Rule ID 51825 // |
| 8826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 8827 | // (udiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIVU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 8828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 8829 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8830 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E64), |
| 8833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8835 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8836 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 8839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8840 | GIR_RootConstrainSelectedInstOperands, |
| 8841 | // GIR_Coverage, 51825, |
| 8842 | GIR_EraseRootFromParent_Done, |
| 8843 | // Label 657: @20744 |
| 8844 | GIM_Reject, |
| 8845 | // Label 655: @20745 |
| 8846 | GIM_Reject, |
| 8847 | // Label 606: @20746 |
| 8848 | GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(20860), |
| 8849 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 8850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 8851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8852 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8853 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 8854 | GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(20814), // Rule ID 51768 // |
| 8855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8856 | // (udiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIVU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 8857 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 8858 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8859 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8860 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E8), |
| 8862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8863 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8864 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8865 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8869 | GIR_RootConstrainSelectedInstOperands, |
| 8870 | // GIR_Coverage, 51768, |
| 8871 | GIR_EraseRootFromParent_Done, |
| 8872 | // Label 659: @20814 |
| 8873 | GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(20859), // Rule ID 51769 // |
| 8874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8875 | // (udiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIVU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 8876 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 8877 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8878 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E8), |
| 8881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8882 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8883 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8888 | GIR_RootConstrainSelectedInstOperands, |
| 8889 | // GIR_Coverage, 51769, |
| 8890 | GIR_EraseRootFromParent_Done, |
| 8891 | // Label 660: @20859 |
| 8892 | GIM_Reject, |
| 8893 | // Label 658: @20860 |
| 8894 | GIM_Reject, |
| 8895 | // Label 607: @20861 |
| 8896 | GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(20975), |
| 8897 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 8898 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 8899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8901 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 8902 | GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(20929), // Rule ID 51796 // |
| 8903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8904 | // (udiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIVU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 8905 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 8906 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8907 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E16), |
| 8910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8912 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8913 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8917 | GIR_RootConstrainSelectedInstOperands, |
| 8918 | // GIR_Coverage, 51796, |
| 8919 | GIR_EraseRootFromParent_Done, |
| 8920 | // Label 662: @20929 |
| 8921 | GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(20974), // Rule ID 51797 // |
| 8922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8923 | // (udiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIVU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 8924 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 8925 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8926 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E16), |
| 8929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8930 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8931 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8932 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 8935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8936 | GIR_RootConstrainSelectedInstOperands, |
| 8937 | // GIR_Coverage, 51797, |
| 8938 | GIR_EraseRootFromParent_Done, |
| 8939 | // Label 663: @20974 |
| 8940 | GIM_Reject, |
| 8941 | // Label 661: @20975 |
| 8942 | GIM_Reject, |
| 8943 | // Label 608: @20976 |
| 8944 | GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(21090), |
| 8945 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 8946 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 8947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8949 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 8950 | GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(21044), // Rule ID 51812 // |
| 8951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 8952 | // (udiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIVU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 8953 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 8954 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8955 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E32), |
| 8958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8960 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8961 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8965 | GIR_RootConstrainSelectedInstOperands, |
| 8966 | // GIR_Coverage, 51812, |
| 8967 | GIR_EraseRootFromParent_Done, |
| 8968 | // Label 665: @21044 |
| 8969 | GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(21089), // Rule ID 51813 // |
| 8970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 8971 | // (udiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIVU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 8972 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 8973 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8974 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E32), |
| 8977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 8978 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8979 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 8980 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 8981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 8982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 8983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 8984 | GIR_RootConstrainSelectedInstOperands, |
| 8985 | // GIR_Coverage, 51813, |
| 8986 | GIR_EraseRootFromParent_Done, |
| 8987 | // Label 666: @21089 |
| 8988 | GIM_Reject, |
| 8989 | // Label 664: @21090 |
| 8990 | GIM_Reject, |
| 8991 | // Label 609: @21091 |
| 8992 | GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(21205), |
| 8993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 8994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 8995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8996 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8997 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 8998 | GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(21159), // Rule ID 51828 // |
| 8999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 9000 | // (udiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIVU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 9001 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 9002 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9003 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9004 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E64), |
| 9006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9007 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9008 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9009 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9013 | GIR_RootConstrainSelectedInstOperands, |
| 9014 | // GIR_Coverage, 51828, |
| 9015 | GIR_EraseRootFromParent_Done, |
| 9016 | // Label 668: @21159 |
| 9017 | GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(21204), // Rule ID 51829 // |
| 9018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 9019 | // (udiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIVU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 9020 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 9021 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9022 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9023 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E64), |
| 9025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9026 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9027 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9028 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9032 | GIR_RootConstrainSelectedInstOperands, |
| 9033 | // GIR_Coverage, 51829, |
| 9034 | GIR_EraseRootFromParent_Done, |
| 9035 | // Label 669: @21204 |
| 9036 | GIM_Reject, |
| 9037 | // Label 667: @21205 |
| 9038 | GIM_Reject, |
| 9039 | // Label 610: @21206 |
| 9040 | GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(21320), |
| 9041 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 9042 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 9043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9044 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9045 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9046 | GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(21274), // Rule ID 51784 // |
| 9047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9048 | // (udiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIVU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9049 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 9050 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9051 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9052 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E8), |
| 9054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9055 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9056 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9057 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9061 | GIR_RootConstrainSelectedInstOperands, |
| 9062 | // GIR_Coverage, 51784, |
| 9063 | GIR_EraseRootFromParent_Done, |
| 9064 | // Label 671: @21274 |
| 9065 | GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(21319), // Rule ID 51785 // |
| 9066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9067 | // (udiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIVU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 9068 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 9069 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9070 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E8), |
| 9073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9074 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9075 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9076 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9080 | GIR_RootConstrainSelectedInstOperands, |
| 9081 | // GIR_Coverage, 51785, |
| 9082 | GIR_EraseRootFromParent_Done, |
| 9083 | // Label 672: @21319 |
| 9084 | GIM_Reject, |
| 9085 | // Label 670: @21320 |
| 9086 | GIM_Reject, |
| 9087 | // Label 611: @21321 |
| 9088 | GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(21435), |
| 9089 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 9090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 9091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9093 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9094 | GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(21389), // Rule ID 51800 // |
| 9095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9096 | // (udiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIVU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 9097 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 9098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9099 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E16), |
| 9102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9104 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9105 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9109 | GIR_RootConstrainSelectedInstOperands, |
| 9110 | // GIR_Coverage, 51800, |
| 9111 | GIR_EraseRootFromParent_Done, |
| 9112 | // Label 674: @21389 |
| 9113 | GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(21434), // Rule ID 51801 // |
| 9114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9115 | // (udiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIVU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 9116 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 9117 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9118 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9119 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E16), |
| 9121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9122 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9123 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9124 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9128 | GIR_RootConstrainSelectedInstOperands, |
| 9129 | // GIR_Coverage, 51801, |
| 9130 | GIR_EraseRootFromParent_Done, |
| 9131 | // Label 675: @21434 |
| 9132 | GIM_Reject, |
| 9133 | // Label 673: @21435 |
| 9134 | GIM_Reject, |
| 9135 | // Label 612: @21436 |
| 9136 | GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(21550), |
| 9137 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 9138 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 9139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9140 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9141 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9142 | GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(21504), // Rule ID 51816 // |
| 9143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9144 | // (udiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIVU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 9145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 9146 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9147 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9148 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E32), |
| 9150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9151 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9152 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9153 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9157 | GIR_RootConstrainSelectedInstOperands, |
| 9158 | // GIR_Coverage, 51816, |
| 9159 | GIR_EraseRootFromParent_Done, |
| 9160 | // Label 677: @21504 |
| 9161 | GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(21549), // Rule ID 51817 // |
| 9162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9163 | // (udiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIVU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 9164 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 9165 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9166 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E32), |
| 9169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9170 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9171 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9172 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9176 | GIR_RootConstrainSelectedInstOperands, |
| 9177 | // GIR_Coverage, 51817, |
| 9178 | GIR_EraseRootFromParent_Done, |
| 9179 | // Label 678: @21549 |
| 9180 | GIM_Reject, |
| 9181 | // Label 676: @21550 |
| 9182 | GIM_Reject, |
| 9183 | // Label 613: @21551 |
| 9184 | GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(21665), |
| 9185 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 9186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 9187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9190 | GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(21619), // Rule ID 51788 // |
| 9191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9192 | // (udiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIVU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9193 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 9194 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9195 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9196 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E8), |
| 9198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9199 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9200 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9201 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9205 | GIR_RootConstrainSelectedInstOperands, |
| 9206 | // GIR_Coverage, 51788, |
| 9207 | GIR_EraseRootFromParent_Done, |
| 9208 | // Label 680: @21619 |
| 9209 | GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(21664), // Rule ID 51789 // |
| 9210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9211 | // (udiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIVU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 9212 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 9213 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9214 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9215 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E8), |
| 9217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9218 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9219 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9220 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9224 | GIR_RootConstrainSelectedInstOperands, |
| 9225 | // GIR_Coverage, 51789, |
| 9226 | GIR_EraseRootFromParent_Done, |
| 9227 | // Label 681: @21664 |
| 9228 | GIM_Reject, |
| 9229 | // Label 679: @21665 |
| 9230 | GIM_Reject, |
| 9231 | // Label 614: @21666 |
| 9232 | GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(21780), |
| 9233 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 9234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 9235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9236 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9237 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9238 | GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(21734), // Rule ID 51804 // |
| 9239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9240 | // (udiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIVU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 9241 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 9242 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9243 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9244 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E16), |
| 9246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9247 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9248 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9249 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9253 | GIR_RootConstrainSelectedInstOperands, |
| 9254 | // GIR_Coverage, 51804, |
| 9255 | GIR_EraseRootFromParent_Done, |
| 9256 | // Label 683: @21734 |
| 9257 | GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(21779), // Rule ID 51805 // |
| 9258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9259 | // (udiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIVU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 9260 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 9261 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9262 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E16), |
| 9265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9266 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9267 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9268 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9272 | GIR_RootConstrainSelectedInstOperands, |
| 9273 | // GIR_Coverage, 51805, |
| 9274 | GIR_EraseRootFromParent_Done, |
| 9275 | // Label 684: @21779 |
| 9276 | GIM_Reject, |
| 9277 | // Label 682: @21780 |
| 9278 | GIM_Reject, |
| 9279 | // Label 615: @21781 |
| 9280 | GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(21895), |
| 9281 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 9282 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 9283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9284 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 9286 | GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(21849), // Rule ID 51792 // |
| 9287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9288 | // (udiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIVU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9289 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 9290 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9291 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E8), |
| 9294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9295 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9296 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9297 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9301 | GIR_RootConstrainSelectedInstOperands, |
| 9302 | // GIR_Coverage, 51792, |
| 9303 | GIR_EraseRootFromParent_Done, |
| 9304 | // Label 686: @21849 |
| 9305 | GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(21894), // Rule ID 51793 // |
| 9306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9307 | // (udiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIVU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 9308 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 9309 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9310 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9311 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E8), |
| 9313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9314 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9315 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9316 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9320 | GIR_RootConstrainSelectedInstOperands, |
| 9321 | // GIR_Coverage, 51793, |
| 9322 | GIR_EraseRootFromParent_Done, |
| 9323 | // Label 687: @21894 |
| 9324 | GIM_Reject, |
| 9325 | // Label 685: @21895 |
| 9326 | GIM_Reject, |
| 9327 | // Label 616: @21896 |
| 9328 | GIM_Reject, |
| 9329 | // Label 5: @21897 |
| 9330 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 712*/ GIMT_Encode4(24666), |
| 9331 | /*GILLT_s32*//*Label 688*/ GIMT_Encode4(22032), |
| 9332 | /*GILLT_s64*//*Label 689*/ GIMT_Encode4(22102), GIMT_Encode4(0), |
| 9333 | /*GILLT_nxv1s8*//*Label 690*/ GIMT_Encode4(22136), |
| 9334 | /*GILLT_nxv1s16*//*Label 691*/ GIMT_Encode4(22251), |
| 9335 | /*GILLT_nxv1s32*//*Label 692*/ GIMT_Encode4(22366), |
| 9336 | /*GILLT_nxv1s64*//*Label 693*/ GIMT_Encode4(22481), GIMT_Encode4(0), |
| 9337 | /*GILLT_nxv2s8*//*Label 694*/ GIMT_Encode4(22596), |
| 9338 | /*GILLT_nxv2s16*//*Label 695*/ GIMT_Encode4(22711), |
| 9339 | /*GILLT_nxv2s32*//*Label 696*/ GIMT_Encode4(22826), |
| 9340 | /*GILLT_nxv2s64*//*Label 697*/ GIMT_Encode4(22941), GIMT_Encode4(0), |
| 9341 | /*GILLT_nxv4s8*//*Label 698*/ GIMT_Encode4(23056), |
| 9342 | /*GILLT_nxv4s16*//*Label 699*/ GIMT_Encode4(23171), |
| 9343 | /*GILLT_nxv4s32*//*Label 700*/ GIMT_Encode4(23286), |
| 9344 | /*GILLT_nxv4s64*//*Label 701*/ GIMT_Encode4(23401), GIMT_Encode4(0), |
| 9345 | /*GILLT_nxv8s8*//*Label 702*/ GIMT_Encode4(23516), |
| 9346 | /*GILLT_nxv8s16*//*Label 703*/ GIMT_Encode4(23631), |
| 9347 | /*GILLT_nxv8s32*//*Label 704*/ GIMT_Encode4(23746), |
| 9348 | /*GILLT_nxv8s64*//*Label 705*/ GIMT_Encode4(23861), GIMT_Encode4(0), |
| 9349 | /*GILLT_nxv16s8*//*Label 706*/ GIMT_Encode4(23976), |
| 9350 | /*GILLT_nxv16s16*//*Label 707*/ GIMT_Encode4(24091), |
| 9351 | /*GILLT_nxv16s32*//*Label 708*/ GIMT_Encode4(24206), GIMT_Encode4(0), |
| 9352 | /*GILLT_nxv32s8*//*Label 709*/ GIMT_Encode4(24321), |
| 9353 | /*GILLT_nxv32s16*//*Label 710*/ GIMT_Encode4(24436), GIMT_Encode4(0), |
| 9354 | /*GILLT_nxv64s8*//*Label 711*/ GIMT_Encode4(24551), |
| 9355 | // Label 688: @22032 |
| 9356 | GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(22101), |
| 9357 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 9358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 9360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 9361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 9362 | GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(22070), // Rule ID 337 // |
| 9363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), |
| 9364 | // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 9365 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REM), |
| 9366 | GIR_RootConstrainSelectedInstOperands, |
| 9367 | // GIR_Coverage, 337, |
| 9368 | GIR_Done, |
| 9369 | // Label 714: @22070 |
| 9370 | GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(22085), // Rule ID 354 // |
| 9371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), |
| 9372 | // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 9373 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMW), |
| 9374 | GIR_RootConstrainSelectedInstOperands, |
| 9375 | // GIR_Coverage, 354, |
| 9376 | GIR_Done, |
| 9377 | // Label 715: @22085 |
| 9378 | GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(22100), // Rule ID 355 // |
| 9379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), |
| 9380 | // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 9381 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMW), |
| 9382 | GIR_RootConstrainSelectedInstOperands, |
| 9383 | // GIR_Coverage, 355, |
| 9384 | GIR_Done, |
| 9385 | // Label 716: @22100 |
| 9386 | GIM_Reject, |
| 9387 | // Label 713: @22101 |
| 9388 | GIM_Reject, |
| 9389 | // Label 689: @22102 |
| 9390 | GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(22135), // Rule ID 336 // |
| 9391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), |
| 9392 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9393 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 9395 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 9396 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 9397 | // (srem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 9398 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REM), |
| 9399 | GIR_RootConstrainSelectedInstOperands, |
| 9400 | // GIR_Coverage, 336, |
| 9401 | GIR_Done, |
| 9402 | // Label 717: @22135 |
| 9403 | GIM_Reject, |
| 9404 | // Label 690: @22136 |
| 9405 | GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(22250), |
| 9406 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 9407 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 9408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9409 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9410 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9411 | GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(22204), // Rule ID 52008 // |
| 9412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9413 | // (srem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREM_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9414 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 9415 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9416 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9417 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF8_E8), |
| 9419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9420 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9421 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9422 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9426 | GIR_RootConstrainSelectedInstOperands, |
| 9427 | // GIR_Coverage, 52008, |
| 9428 | GIR_EraseRootFromParent_Done, |
| 9429 | // Label 719: @22204 |
| 9430 | GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(22249), // Rule ID 52009 // |
| 9431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9432 | // (srem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREM_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 9433 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 9434 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9435 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9436 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF8_E8), |
| 9438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9439 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9440 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9441 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9445 | GIR_RootConstrainSelectedInstOperands, |
| 9446 | // GIR_Coverage, 52009, |
| 9447 | GIR_EraseRootFromParent_Done, |
| 9448 | // Label 720: @22249 |
| 9449 | GIM_Reject, |
| 9450 | // Label 718: @22250 |
| 9451 | GIM_Reject, |
| 9452 | // Label 691: @22251 |
| 9453 | GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(22365), |
| 9454 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 9455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 9456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9458 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9459 | GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(22319), // Rule ID 52020 // |
| 9460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9461 | // (srem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREM_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 9462 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 9463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9464 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9465 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E16), |
| 9467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9468 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9469 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9470 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9474 | GIR_RootConstrainSelectedInstOperands, |
| 9475 | // GIR_Coverage, 52020, |
| 9476 | GIR_EraseRootFromParent_Done, |
| 9477 | // Label 722: @22319 |
| 9478 | GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(22364), // Rule ID 52021 // |
| 9479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9480 | // (srem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREM_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 9481 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 9482 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9483 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E16), |
| 9486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9487 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9488 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9489 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9493 | GIR_RootConstrainSelectedInstOperands, |
| 9494 | // GIR_Coverage, 52021, |
| 9495 | GIR_EraseRootFromParent_Done, |
| 9496 | // Label 723: @22364 |
| 9497 | GIM_Reject, |
| 9498 | // Label 721: @22365 |
| 9499 | GIM_Reject, |
| 9500 | // Label 692: @22366 |
| 9501 | GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(22480), |
| 9502 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 9503 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 9504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9506 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9507 | GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(22434), // Rule ID 52028 // |
| 9508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9509 | // (srem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREM_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 9510 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 9511 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9512 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9513 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E32), |
| 9515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9516 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9517 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9518 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9522 | GIR_RootConstrainSelectedInstOperands, |
| 9523 | // GIR_Coverage, 52028, |
| 9524 | GIR_EraseRootFromParent_Done, |
| 9525 | // Label 725: @22434 |
| 9526 | GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(22479), // Rule ID 52029 // |
| 9527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9528 | // (srem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREM_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 9529 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 9530 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9531 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E32), |
| 9534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9535 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9536 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9537 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9541 | GIR_RootConstrainSelectedInstOperands, |
| 9542 | // GIR_Coverage, 52029, |
| 9543 | GIR_EraseRootFromParent_Done, |
| 9544 | // Label 726: @22479 |
| 9545 | GIM_Reject, |
| 9546 | // Label 724: @22480 |
| 9547 | GIM_Reject, |
| 9548 | // Label 693: @22481 |
| 9549 | GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(22595), |
| 9550 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 9551 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 9552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9553 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9554 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9555 | GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(22549), // Rule ID 52044 // |
| 9556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 9557 | // (srem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREM_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 9558 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 9559 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9560 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E64), |
| 9563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9564 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9565 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9566 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9570 | GIR_RootConstrainSelectedInstOperands, |
| 9571 | // GIR_Coverage, 52044, |
| 9572 | GIR_EraseRootFromParent_Done, |
| 9573 | // Label 728: @22549 |
| 9574 | GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(22594), // Rule ID 52045 // |
| 9575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 9576 | // (srem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREM_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 9577 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 9578 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9579 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9580 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E64), |
| 9582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9583 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9584 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9585 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9589 | GIR_RootConstrainSelectedInstOperands, |
| 9590 | // GIR_Coverage, 52045, |
| 9591 | GIR_EraseRootFromParent_Done, |
| 9592 | // Label 729: @22594 |
| 9593 | GIM_Reject, |
| 9594 | // Label 727: @22595 |
| 9595 | GIM_Reject, |
| 9596 | // Label 694: @22596 |
| 9597 | GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(22710), |
| 9598 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 9599 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 9600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9601 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9602 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9603 | GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(22664), // Rule ID 52012 // |
| 9604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9605 | // (srem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREM_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9606 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 9607 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9608 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E8), |
| 9611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9613 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9614 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9618 | GIR_RootConstrainSelectedInstOperands, |
| 9619 | // GIR_Coverage, 52012, |
| 9620 | GIR_EraseRootFromParent_Done, |
| 9621 | // Label 731: @22664 |
| 9622 | GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(22709), // Rule ID 52013 // |
| 9623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9624 | // (srem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREM_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 9625 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 9626 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9627 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E8), |
| 9630 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9631 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9632 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9633 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9637 | GIR_RootConstrainSelectedInstOperands, |
| 9638 | // GIR_Coverage, 52013, |
| 9639 | GIR_EraseRootFromParent_Done, |
| 9640 | // Label 732: @22709 |
| 9641 | GIM_Reject, |
| 9642 | // Label 730: @22710 |
| 9643 | GIM_Reject, |
| 9644 | // Label 695: @22711 |
| 9645 | GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(22825), |
| 9646 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 9647 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 9648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9649 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9650 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9651 | GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(22779), // Rule ID 52024 // |
| 9652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9653 | // (srem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREM_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 9654 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 9655 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9656 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E16), |
| 9659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9660 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9661 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9662 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9666 | GIR_RootConstrainSelectedInstOperands, |
| 9667 | // GIR_Coverage, 52024, |
| 9668 | GIR_EraseRootFromParent_Done, |
| 9669 | // Label 734: @22779 |
| 9670 | GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(22824), // Rule ID 52025 // |
| 9671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9672 | // (srem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREM_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 9673 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 9674 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9675 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E16), |
| 9678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9679 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9680 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9681 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9685 | GIR_RootConstrainSelectedInstOperands, |
| 9686 | // GIR_Coverage, 52025, |
| 9687 | GIR_EraseRootFromParent_Done, |
| 9688 | // Label 735: @22824 |
| 9689 | GIM_Reject, |
| 9690 | // Label 733: @22825 |
| 9691 | GIM_Reject, |
| 9692 | // Label 696: @22826 |
| 9693 | GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(22940), |
| 9694 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 9695 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 9696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9697 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9698 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9699 | GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(22894), // Rule ID 52040 // |
| 9700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9701 | // (srem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREM_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 9702 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 9703 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9704 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9705 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E32), |
| 9707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9708 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9709 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9710 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9714 | GIR_RootConstrainSelectedInstOperands, |
| 9715 | // GIR_Coverage, 52040, |
| 9716 | GIR_EraseRootFromParent_Done, |
| 9717 | // Label 737: @22894 |
| 9718 | GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(22939), // Rule ID 52041 // |
| 9719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9720 | // (srem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREM_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 9721 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 9722 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9723 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E32), |
| 9726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9727 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9728 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9729 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9733 | GIR_RootConstrainSelectedInstOperands, |
| 9734 | // GIR_Coverage, 52041, |
| 9735 | GIR_EraseRootFromParent_Done, |
| 9736 | // Label 738: @22939 |
| 9737 | GIM_Reject, |
| 9738 | // Label 736: @22940 |
| 9739 | GIM_Reject, |
| 9740 | // Label 697: @22941 |
| 9741 | GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(23055), |
| 9742 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 9743 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 9744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9745 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9746 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9747 | GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(23009), // Rule ID 52084 // |
| 9748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 9749 | // (srem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREM_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 9750 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 9751 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9752 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E64), |
| 9755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9756 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9757 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9758 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9762 | GIR_RootConstrainSelectedInstOperands, |
| 9763 | // GIR_Coverage, 52084, |
| 9764 | GIR_EraseRootFromParent_Done, |
| 9765 | // Label 740: @23009 |
| 9766 | GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(23054), // Rule ID 52085 // |
| 9767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 9768 | // (srem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREM_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 9769 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 9770 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9771 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9772 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E64), |
| 9774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9775 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9776 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9777 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9781 | GIR_RootConstrainSelectedInstOperands, |
| 9782 | // GIR_Coverage, 52085, |
| 9783 | GIR_EraseRootFromParent_Done, |
| 9784 | // Label 741: @23054 |
| 9785 | GIM_Reject, |
| 9786 | // Label 739: @23055 |
| 9787 | GIM_Reject, |
| 9788 | // Label 698: @23056 |
| 9789 | GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(23170), |
| 9790 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 9791 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 9792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9794 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9795 | GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(23124), // Rule ID 52016 // |
| 9796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9797 | // (srem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREM_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9798 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 9799 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9800 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9801 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E8), |
| 9803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9804 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9805 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9806 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9810 | GIR_RootConstrainSelectedInstOperands, |
| 9811 | // GIR_Coverage, 52016, |
| 9812 | GIR_EraseRootFromParent_Done, |
| 9813 | // Label 743: @23124 |
| 9814 | GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(23169), // Rule ID 52017 // |
| 9815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9816 | // (srem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREM_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 9817 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 9818 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9819 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E8), |
| 9822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9823 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9824 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9825 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9829 | GIR_RootConstrainSelectedInstOperands, |
| 9830 | // GIR_Coverage, 52017, |
| 9831 | GIR_EraseRootFromParent_Done, |
| 9832 | // Label 744: @23169 |
| 9833 | GIM_Reject, |
| 9834 | // Label 742: @23170 |
| 9835 | GIM_Reject, |
| 9836 | // Label 699: @23171 |
| 9837 | GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(23285), |
| 9838 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 9839 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 9840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9843 | GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(23239), // Rule ID 52036 // |
| 9844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9845 | // (srem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREM_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 9846 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 9847 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9848 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E16), |
| 9851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9852 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9853 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9854 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9858 | GIR_RootConstrainSelectedInstOperands, |
| 9859 | // GIR_Coverage, 52036, |
| 9860 | GIR_EraseRootFromParent_Done, |
| 9861 | // Label 746: @23239 |
| 9862 | GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(23284), // Rule ID 52037 // |
| 9863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9864 | // (srem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREM_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 9865 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 9866 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9867 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9868 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E16), |
| 9870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9871 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9872 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9873 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 9876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9877 | GIR_RootConstrainSelectedInstOperands, |
| 9878 | // GIR_Coverage, 52037, |
| 9879 | GIR_EraseRootFromParent_Done, |
| 9880 | // Label 747: @23284 |
| 9881 | GIM_Reject, |
| 9882 | // Label 745: @23285 |
| 9883 | GIM_Reject, |
| 9884 | // Label 700: @23286 |
| 9885 | GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(23400), |
| 9886 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 9887 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 9888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9889 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9890 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 9891 | GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(23354), // Rule ID 52072 // |
| 9892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9893 | // (srem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREM_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 9894 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 9895 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9896 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E32), |
| 9899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9900 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9901 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9902 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9906 | GIR_RootConstrainSelectedInstOperands, |
| 9907 | // GIR_Coverage, 52072, |
| 9908 | GIR_EraseRootFromParent_Done, |
| 9909 | // Label 749: @23354 |
| 9910 | GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(23399), // Rule ID 52073 // |
| 9911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 9912 | // (srem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREM_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 9913 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 9914 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9915 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9916 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E32), |
| 9918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9919 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9920 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9921 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 9924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9925 | GIR_RootConstrainSelectedInstOperands, |
| 9926 | // GIR_Coverage, 52073, |
| 9927 | GIR_EraseRootFromParent_Done, |
| 9928 | // Label 750: @23399 |
| 9929 | GIM_Reject, |
| 9930 | // Label 748: @23400 |
| 9931 | GIM_Reject, |
| 9932 | // Label 701: @23401 |
| 9933 | GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(23515), |
| 9934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 9935 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 9936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9937 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9938 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 9939 | GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(23469), // Rule ID 52088 // |
| 9940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 9941 | // (srem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREM_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 9942 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 9943 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9944 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E64), |
| 9947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9948 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9949 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9950 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9954 | GIR_RootConstrainSelectedInstOperands, |
| 9955 | // GIR_Coverage, 52088, |
| 9956 | GIR_EraseRootFromParent_Done, |
| 9957 | // Label 752: @23469 |
| 9958 | GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(23514), // Rule ID 52089 // |
| 9959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 9960 | // (srem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREM_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 9961 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 9962 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9963 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9964 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E64), |
| 9966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9967 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9968 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9969 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 9971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 9972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 9973 | GIR_RootConstrainSelectedInstOperands, |
| 9974 | // GIR_Coverage, 52089, |
| 9975 | GIR_EraseRootFromParent_Done, |
| 9976 | // Label 753: @23514 |
| 9977 | GIM_Reject, |
| 9978 | // Label 751: @23515 |
| 9979 | GIM_Reject, |
| 9980 | // Label 702: @23516 |
| 9981 | GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(23630), |
| 9982 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 9983 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 9984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9985 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9986 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 9987 | GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(23584), // Rule ID 52032 // |
| 9988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 9989 | // (srem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREM_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 9990 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 9991 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9992 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E8), |
| 9995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 9996 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9997 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 9998 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 9999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10002 | GIR_RootConstrainSelectedInstOperands, |
| 10003 | // GIR_Coverage, 52032, |
| 10004 | GIR_EraseRootFromParent_Done, |
| 10005 | // Label 755: @23584 |
| 10006 | GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(23629), // Rule ID 52033 // |
| 10007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10008 | // (srem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREM_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10009 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 10010 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10011 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10012 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E8), |
| 10014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10015 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10016 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10017 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10021 | GIR_RootConstrainSelectedInstOperands, |
| 10022 | // GIR_Coverage, 52033, |
| 10023 | GIR_EraseRootFromParent_Done, |
| 10024 | // Label 756: @23629 |
| 10025 | GIM_Reject, |
| 10026 | // Label 754: @23630 |
| 10027 | GIM_Reject, |
| 10028 | // Label 703: @23631 |
| 10029 | GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(23745), |
| 10030 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 10031 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 10032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10033 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10034 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10035 | GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(23699), // Rule ID 52060 // |
| 10036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10037 | // (srem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREM_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 10038 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 10039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10040 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E16), |
| 10043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10044 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10045 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10046 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10050 | GIR_RootConstrainSelectedInstOperands, |
| 10051 | // GIR_Coverage, 52060, |
| 10052 | GIR_EraseRootFromParent_Done, |
| 10053 | // Label 758: @23699 |
| 10054 | GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(23744), // Rule ID 52061 // |
| 10055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10056 | // (srem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREM_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 10057 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 10058 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10059 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10060 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E16), |
| 10062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10063 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10064 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10065 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10069 | GIR_RootConstrainSelectedInstOperands, |
| 10070 | // GIR_Coverage, 52061, |
| 10071 | GIR_EraseRootFromParent_Done, |
| 10072 | // Label 759: @23744 |
| 10073 | GIM_Reject, |
| 10074 | // Label 757: @23745 |
| 10075 | GIM_Reject, |
| 10076 | // Label 704: @23746 |
| 10077 | GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(23860), |
| 10078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 10079 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 10080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10081 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10082 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10083 | GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(23814), // Rule ID 52076 // |
| 10084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10085 | // (srem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREM_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 10086 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 10087 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10088 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E32), |
| 10091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10092 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10093 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10094 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10098 | GIR_RootConstrainSelectedInstOperands, |
| 10099 | // GIR_Coverage, 52076, |
| 10100 | GIR_EraseRootFromParent_Done, |
| 10101 | // Label 761: @23814 |
| 10102 | GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(23859), // Rule ID 52077 // |
| 10103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10104 | // (srem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREM_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 10105 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 10106 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10107 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10108 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E32), |
| 10110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10111 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10112 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10113 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10117 | GIR_RootConstrainSelectedInstOperands, |
| 10118 | // GIR_Coverage, 52077, |
| 10119 | GIR_EraseRootFromParent_Done, |
| 10120 | // Label 762: @23859 |
| 10121 | GIM_Reject, |
| 10122 | // Label 760: @23860 |
| 10123 | GIM_Reject, |
| 10124 | // Label 705: @23861 |
| 10125 | GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(23975), |
| 10126 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 10127 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 10128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10129 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10130 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10131 | GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(23929), // Rule ID 52092 // |
| 10132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 10133 | // (srem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREM_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 10134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 10135 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10136 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E64), |
| 10139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10141 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10142 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 10145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10146 | GIR_RootConstrainSelectedInstOperands, |
| 10147 | // GIR_Coverage, 52092, |
| 10148 | GIR_EraseRootFromParent_Done, |
| 10149 | // Label 764: @23929 |
| 10150 | GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(23974), // Rule ID 52093 // |
| 10151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 10152 | // (srem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREM_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 10153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 10154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E64), |
| 10158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10161 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 10164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10165 | GIR_RootConstrainSelectedInstOperands, |
| 10166 | // GIR_Coverage, 52093, |
| 10167 | GIR_EraseRootFromParent_Done, |
| 10168 | // Label 765: @23974 |
| 10169 | GIM_Reject, |
| 10170 | // Label 763: @23975 |
| 10171 | GIM_Reject, |
| 10172 | // Label 706: @23976 |
| 10173 | GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(24090), |
| 10174 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 10175 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 10176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10177 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10178 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10179 | GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(24044), // Rule ID 52048 // |
| 10180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10181 | // (srem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREM_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 10182 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 10183 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10184 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E8), |
| 10187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10188 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10189 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10190 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10194 | GIR_RootConstrainSelectedInstOperands, |
| 10195 | // GIR_Coverage, 52048, |
| 10196 | GIR_EraseRootFromParent_Done, |
| 10197 | // Label 767: @24044 |
| 10198 | GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(24089), // Rule ID 52049 // |
| 10199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10200 | // (srem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREM_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10201 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 10202 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10203 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10204 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E8), |
| 10206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10208 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10209 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10213 | GIR_RootConstrainSelectedInstOperands, |
| 10214 | // GIR_Coverage, 52049, |
| 10215 | GIR_EraseRootFromParent_Done, |
| 10216 | // Label 768: @24089 |
| 10217 | GIM_Reject, |
| 10218 | // Label 766: @24090 |
| 10219 | GIM_Reject, |
| 10220 | // Label 707: @24091 |
| 10221 | GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(24205), |
| 10222 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 10223 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 10224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10226 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10227 | GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(24159), // Rule ID 52064 // |
| 10228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10229 | // (srem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREM_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 10230 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 10231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10233 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E16), |
| 10235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10236 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10237 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10238 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10242 | GIR_RootConstrainSelectedInstOperands, |
| 10243 | // GIR_Coverage, 52064, |
| 10244 | GIR_EraseRootFromParent_Done, |
| 10245 | // Label 770: @24159 |
| 10246 | GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(24204), // Rule ID 52065 // |
| 10247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10248 | // (srem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREM_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 10249 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 10250 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10251 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E16), |
| 10254 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10255 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10256 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10257 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10261 | GIR_RootConstrainSelectedInstOperands, |
| 10262 | // GIR_Coverage, 52065, |
| 10263 | GIR_EraseRootFromParent_Done, |
| 10264 | // Label 771: @24204 |
| 10265 | GIM_Reject, |
| 10266 | // Label 769: @24205 |
| 10267 | GIM_Reject, |
| 10268 | // Label 708: @24206 |
| 10269 | GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(24320), |
| 10270 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 10271 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 10272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10274 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10275 | GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(24274), // Rule ID 52080 // |
| 10276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10277 | // (srem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREM_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 10278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 10279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E32), |
| 10283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10286 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10290 | GIR_RootConstrainSelectedInstOperands, |
| 10291 | // GIR_Coverage, 52080, |
| 10292 | GIR_EraseRootFromParent_Done, |
| 10293 | // Label 773: @24274 |
| 10294 | GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(24319), // Rule ID 52081 // |
| 10295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10296 | // (srem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREM_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 10297 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 10298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10299 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10300 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E32), |
| 10302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10303 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10304 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10305 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10309 | GIR_RootConstrainSelectedInstOperands, |
| 10310 | // GIR_Coverage, 52081, |
| 10311 | GIR_EraseRootFromParent_Done, |
| 10312 | // Label 774: @24319 |
| 10313 | GIM_Reject, |
| 10314 | // Label 772: @24320 |
| 10315 | GIM_Reject, |
| 10316 | // Label 709: @24321 |
| 10317 | GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(24435), |
| 10318 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 10319 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 10320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10321 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10322 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 10323 | GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(24389), // Rule ID 52052 // |
| 10324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10325 | // (srem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREM_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 10326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 10327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E8), |
| 10331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10332 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10333 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10334 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10338 | GIR_RootConstrainSelectedInstOperands, |
| 10339 | // GIR_Coverage, 52052, |
| 10340 | GIR_EraseRootFromParent_Done, |
| 10341 | // Label 776: @24389 |
| 10342 | GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(24434), // Rule ID 52053 // |
| 10343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10344 | // (srem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREM_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10345 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 10346 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10347 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10349 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E8), |
| 10350 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10351 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10352 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10353 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10357 | GIR_RootConstrainSelectedInstOperands, |
| 10358 | // GIR_Coverage, 52053, |
| 10359 | GIR_EraseRootFromParent_Done, |
| 10360 | // Label 777: @24434 |
| 10361 | GIM_Reject, |
| 10362 | // Label 775: @24435 |
| 10363 | GIM_Reject, |
| 10364 | // Label 710: @24436 |
| 10365 | GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(24550), |
| 10366 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 10367 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 10368 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10369 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10370 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10371 | GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(24504), // Rule ID 52068 // |
| 10372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10373 | // (srem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREM_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 10374 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 10375 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10376 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E16), |
| 10379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10380 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10381 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10382 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10386 | GIR_RootConstrainSelectedInstOperands, |
| 10387 | // GIR_Coverage, 52068, |
| 10388 | GIR_EraseRootFromParent_Done, |
| 10389 | // Label 779: @24504 |
| 10390 | GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(24549), // Rule ID 52069 // |
| 10391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10392 | // (srem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREM_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 10393 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 10394 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10395 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E16), |
| 10398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10399 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10400 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10401 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10405 | GIR_RootConstrainSelectedInstOperands, |
| 10406 | // GIR_Coverage, 52069, |
| 10407 | GIR_EraseRootFromParent_Done, |
| 10408 | // Label 780: @24549 |
| 10409 | GIM_Reject, |
| 10410 | // Label 778: @24550 |
| 10411 | GIM_Reject, |
| 10412 | // Label 711: @24551 |
| 10413 | GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(24665), |
| 10414 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 10415 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 10416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10417 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10418 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 10419 | GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(24619), // Rule ID 52056 // |
| 10420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10421 | // (srem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREM_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 10422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 10423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E8), |
| 10427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10428 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10429 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10430 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10434 | GIR_RootConstrainSelectedInstOperands, |
| 10435 | // GIR_Coverage, 52056, |
| 10436 | GIR_EraseRootFromParent_Done, |
| 10437 | // Label 782: @24619 |
| 10438 | GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(24664), // Rule ID 52057 // |
| 10439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10440 | // (srem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREM_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10441 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 10442 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10443 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E8), |
| 10446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10447 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10448 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10449 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10453 | GIR_RootConstrainSelectedInstOperands, |
| 10454 | // GIR_Coverage, 52057, |
| 10455 | GIR_EraseRootFromParent_Done, |
| 10456 | // Label 783: @24664 |
| 10457 | GIM_Reject, |
| 10458 | // Label 781: @24665 |
| 10459 | GIM_Reject, |
| 10460 | // Label 712: @24666 |
| 10461 | GIM_Reject, |
| 10462 | // Label 6: @24667 |
| 10463 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 808*/ GIMT_Encode4(27436), |
| 10464 | /*GILLT_s32*//*Label 784*/ GIMT_Encode4(24802), |
| 10465 | /*GILLT_s64*//*Label 785*/ GIMT_Encode4(24872), GIMT_Encode4(0), |
| 10466 | /*GILLT_nxv1s8*//*Label 786*/ GIMT_Encode4(24906), |
| 10467 | /*GILLT_nxv1s16*//*Label 787*/ GIMT_Encode4(25021), |
| 10468 | /*GILLT_nxv1s32*//*Label 788*/ GIMT_Encode4(25136), |
| 10469 | /*GILLT_nxv1s64*//*Label 789*/ GIMT_Encode4(25251), GIMT_Encode4(0), |
| 10470 | /*GILLT_nxv2s8*//*Label 790*/ GIMT_Encode4(25366), |
| 10471 | /*GILLT_nxv2s16*//*Label 791*/ GIMT_Encode4(25481), |
| 10472 | /*GILLT_nxv2s32*//*Label 792*/ GIMT_Encode4(25596), |
| 10473 | /*GILLT_nxv2s64*//*Label 793*/ GIMT_Encode4(25711), GIMT_Encode4(0), |
| 10474 | /*GILLT_nxv4s8*//*Label 794*/ GIMT_Encode4(25826), |
| 10475 | /*GILLT_nxv4s16*//*Label 795*/ GIMT_Encode4(25941), |
| 10476 | /*GILLT_nxv4s32*//*Label 796*/ GIMT_Encode4(26056), |
| 10477 | /*GILLT_nxv4s64*//*Label 797*/ GIMT_Encode4(26171), GIMT_Encode4(0), |
| 10478 | /*GILLT_nxv8s8*//*Label 798*/ GIMT_Encode4(26286), |
| 10479 | /*GILLT_nxv8s16*//*Label 799*/ GIMT_Encode4(26401), |
| 10480 | /*GILLT_nxv8s32*//*Label 800*/ GIMT_Encode4(26516), |
| 10481 | /*GILLT_nxv8s64*//*Label 801*/ GIMT_Encode4(26631), GIMT_Encode4(0), |
| 10482 | /*GILLT_nxv16s8*//*Label 802*/ GIMT_Encode4(26746), |
| 10483 | /*GILLT_nxv16s16*//*Label 803*/ GIMT_Encode4(26861), |
| 10484 | /*GILLT_nxv16s32*//*Label 804*/ GIMT_Encode4(26976), GIMT_Encode4(0), |
| 10485 | /*GILLT_nxv32s8*//*Label 805*/ GIMT_Encode4(27091), |
| 10486 | /*GILLT_nxv32s16*//*Label 806*/ GIMT_Encode4(27206), GIMT_Encode4(0), |
| 10487 | /*GILLT_nxv64s8*//*Label 807*/ GIMT_Encode4(27321), |
| 10488 | // Label 784: @24802 |
| 10489 | GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(24871), |
| 10490 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 10491 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 10492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 10493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 10494 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 10495 | GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(24840), // Rule ID 339 // |
| 10496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), |
| 10497 | // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 10498 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMU), |
| 10499 | GIR_RootConstrainSelectedInstOperands, |
| 10500 | // GIR_Coverage, 339, |
| 10501 | GIR_Done, |
| 10502 | // Label 810: @24840 |
| 10503 | GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(24855), // Rule ID 356 // |
| 10504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), |
| 10505 | // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 10506 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMUW), |
| 10507 | GIR_RootConstrainSelectedInstOperands, |
| 10508 | // GIR_Coverage, 356, |
| 10509 | GIR_Done, |
| 10510 | // Label 811: @24855 |
| 10511 | GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(24870), // Rule ID 357 // |
| 10512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), |
| 10513 | // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 10514 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMUW), |
| 10515 | GIR_RootConstrainSelectedInstOperands, |
| 10516 | // GIR_Coverage, 357, |
| 10517 | GIR_Done, |
| 10518 | // Label 812: @24870 |
| 10519 | GIM_Reject, |
| 10520 | // Label 809: @24871 |
| 10521 | GIM_Reject, |
| 10522 | // Label 785: @24872 |
| 10523 | GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(24905), // Rule ID 338 // |
| 10524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), |
| 10525 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10526 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 10527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 10528 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 10529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 10530 | // (urem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 10531 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMU), |
| 10532 | GIR_RootConstrainSelectedInstOperands, |
| 10533 | // GIR_Coverage, 338, |
| 10534 | GIR_Done, |
| 10535 | // Label 813: @24905 |
| 10536 | GIM_Reject, |
| 10537 | // Label 786: @24906 |
| 10538 | GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(25020), |
| 10539 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 10540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 10541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10542 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10543 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10544 | GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(24974), // Rule ID 51920 // |
| 10545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10546 | // (urem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREMU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 10547 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 10548 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10549 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10550 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF8_E8), |
| 10552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10553 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10554 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10555 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10559 | GIR_RootConstrainSelectedInstOperands, |
| 10560 | // GIR_Coverage, 51920, |
| 10561 | GIR_EraseRootFromParent_Done, |
| 10562 | // Label 815: @24974 |
| 10563 | GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(25019), // Rule ID 51921 // |
| 10564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10565 | // (urem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREMU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10566 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 10567 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10568 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10569 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF8_E8), |
| 10571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10572 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10573 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10574 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10578 | GIR_RootConstrainSelectedInstOperands, |
| 10579 | // GIR_Coverage, 51921, |
| 10580 | GIR_EraseRootFromParent_Done, |
| 10581 | // Label 816: @25019 |
| 10582 | GIM_Reject, |
| 10583 | // Label 814: @25020 |
| 10584 | GIM_Reject, |
| 10585 | // Label 787: @25021 |
| 10586 | GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(25135), |
| 10587 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 10588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 10589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10590 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10591 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10592 | GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(25089), // Rule ID 51932 // |
| 10593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10594 | // (urem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREMU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 10595 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 10596 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10597 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10598 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E16), |
| 10600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10601 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10602 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10603 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10607 | GIR_RootConstrainSelectedInstOperands, |
| 10608 | // GIR_Coverage, 51932, |
| 10609 | GIR_EraseRootFromParent_Done, |
| 10610 | // Label 818: @25089 |
| 10611 | GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(25134), // Rule ID 51933 // |
| 10612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10613 | // (urem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREMU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 10614 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 10615 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10616 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E16), |
| 10619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10621 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10622 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10626 | GIR_RootConstrainSelectedInstOperands, |
| 10627 | // GIR_Coverage, 51933, |
| 10628 | GIR_EraseRootFromParent_Done, |
| 10629 | // Label 819: @25134 |
| 10630 | GIM_Reject, |
| 10631 | // Label 817: @25135 |
| 10632 | GIM_Reject, |
| 10633 | // Label 788: @25136 |
| 10634 | GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(25250), |
| 10635 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 10636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 10637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10638 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10639 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10640 | GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(25204), // Rule ID 51940 // |
| 10641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10642 | // (urem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREMU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 10643 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 10644 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10645 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E32), |
| 10648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10649 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10650 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10651 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10655 | GIR_RootConstrainSelectedInstOperands, |
| 10656 | // GIR_Coverage, 51940, |
| 10657 | GIR_EraseRootFromParent_Done, |
| 10658 | // Label 821: @25204 |
| 10659 | GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(25249), // Rule ID 51941 // |
| 10660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10661 | // (urem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREMU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 10662 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 10663 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10664 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E32), |
| 10667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10668 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10669 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10670 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10674 | GIR_RootConstrainSelectedInstOperands, |
| 10675 | // GIR_Coverage, 51941, |
| 10676 | GIR_EraseRootFromParent_Done, |
| 10677 | // Label 822: @25249 |
| 10678 | GIM_Reject, |
| 10679 | // Label 820: @25250 |
| 10680 | GIM_Reject, |
| 10681 | // Label 789: @25251 |
| 10682 | GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(25365), |
| 10683 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 10684 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 10685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10688 | GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(25319), // Rule ID 51956 // |
| 10689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 10690 | // (urem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREMU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 10691 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 10692 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10693 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E64), |
| 10696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10697 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10698 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10699 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 10702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10703 | GIR_RootConstrainSelectedInstOperands, |
| 10704 | // GIR_Coverage, 51956, |
| 10705 | GIR_EraseRootFromParent_Done, |
| 10706 | // Label 824: @25319 |
| 10707 | GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(25364), // Rule ID 51957 // |
| 10708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 10709 | // (urem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREMU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 10710 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 10711 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E64), |
| 10715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10716 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10717 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10718 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 10721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10722 | GIR_RootConstrainSelectedInstOperands, |
| 10723 | // GIR_Coverage, 51957, |
| 10724 | GIR_EraseRootFromParent_Done, |
| 10725 | // Label 825: @25364 |
| 10726 | GIM_Reject, |
| 10727 | // Label 823: @25365 |
| 10728 | GIM_Reject, |
| 10729 | // Label 790: @25366 |
| 10730 | GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(25480), |
| 10731 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 10732 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 10733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10735 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10736 | GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(25434), // Rule ID 51924 // |
| 10737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10738 | // (urem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREMU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 10739 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 10740 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10741 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E8), |
| 10744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10745 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10746 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10747 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10751 | GIR_RootConstrainSelectedInstOperands, |
| 10752 | // GIR_Coverage, 51924, |
| 10753 | GIR_EraseRootFromParent_Done, |
| 10754 | // Label 827: @25434 |
| 10755 | GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(25479), // Rule ID 51925 // |
| 10756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10757 | // (urem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREMU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10758 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 10759 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10760 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E8), |
| 10763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10764 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10765 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10766 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10770 | GIR_RootConstrainSelectedInstOperands, |
| 10771 | // GIR_Coverage, 51925, |
| 10772 | GIR_EraseRootFromParent_Done, |
| 10773 | // Label 828: @25479 |
| 10774 | GIM_Reject, |
| 10775 | // Label 826: @25480 |
| 10776 | GIM_Reject, |
| 10777 | // Label 791: @25481 |
| 10778 | GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(25595), |
| 10779 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 10780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 10781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10782 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10783 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10784 | GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(25549), // Rule ID 51936 // |
| 10785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10786 | // (urem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREMU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 10787 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 10788 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10789 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10790 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E16), |
| 10792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10793 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10794 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10795 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10799 | GIR_RootConstrainSelectedInstOperands, |
| 10800 | // GIR_Coverage, 51936, |
| 10801 | GIR_EraseRootFromParent_Done, |
| 10802 | // Label 830: @25549 |
| 10803 | GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(25594), // Rule ID 51937 // |
| 10804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10805 | // (urem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREMU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 10806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 10807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E16), |
| 10811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10812 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10813 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10814 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10818 | GIR_RootConstrainSelectedInstOperands, |
| 10819 | // GIR_Coverage, 51937, |
| 10820 | GIR_EraseRootFromParent_Done, |
| 10821 | // Label 831: @25594 |
| 10822 | GIM_Reject, |
| 10823 | // Label 829: @25595 |
| 10824 | GIM_Reject, |
| 10825 | // Label 792: @25596 |
| 10826 | GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(25710), |
| 10827 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 10828 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 10829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10830 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10831 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10832 | GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(25664), // Rule ID 51952 // |
| 10833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10834 | // (urem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREMU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 10835 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 10836 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10837 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10838 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E32), |
| 10840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10841 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10842 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10843 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10847 | GIR_RootConstrainSelectedInstOperands, |
| 10848 | // GIR_Coverage, 51952, |
| 10849 | GIR_EraseRootFromParent_Done, |
| 10850 | // Label 833: @25664 |
| 10851 | GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(25709), // Rule ID 51953 // |
| 10852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10853 | // (urem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREMU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 10854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 10855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10857 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E32), |
| 10859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10860 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10861 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10862 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 10865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10866 | GIR_RootConstrainSelectedInstOperands, |
| 10867 | // GIR_Coverage, 51953, |
| 10868 | GIR_EraseRootFromParent_Done, |
| 10869 | // Label 834: @25709 |
| 10870 | GIM_Reject, |
| 10871 | // Label 832: @25710 |
| 10872 | GIM_Reject, |
| 10873 | // Label 793: @25711 |
| 10874 | GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(25825), |
| 10875 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 10876 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 10877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 10880 | GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(25779), // Rule ID 51996 // |
| 10881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 10882 | // (urem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREMU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 10883 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 10884 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10885 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10886 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E64), |
| 10888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10890 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10891 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 10894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10895 | GIR_RootConstrainSelectedInstOperands, |
| 10896 | // GIR_Coverage, 51996, |
| 10897 | GIR_EraseRootFromParent_Done, |
| 10898 | // Label 836: @25779 |
| 10899 | GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(25824), // Rule ID 51997 // |
| 10900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 10901 | // (urem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREMU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 10902 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 10903 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10904 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E64), |
| 10907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10909 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10910 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 10913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10914 | GIR_RootConstrainSelectedInstOperands, |
| 10915 | // GIR_Coverage, 51997, |
| 10916 | GIR_EraseRootFromParent_Done, |
| 10917 | // Label 837: @25824 |
| 10918 | GIM_Reject, |
| 10919 | // Label 835: @25825 |
| 10920 | GIM_Reject, |
| 10921 | // Label 794: @25826 |
| 10922 | GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(25940), |
| 10923 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 10924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 10925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10926 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10928 | GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(25894), // Rule ID 51928 // |
| 10929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10930 | // (urem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREMU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 10931 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 10932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10933 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E8), |
| 10936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10938 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10939 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10943 | GIR_RootConstrainSelectedInstOperands, |
| 10944 | // GIR_Coverage, 51928, |
| 10945 | GIR_EraseRootFromParent_Done, |
| 10946 | // Label 839: @25894 |
| 10947 | GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(25939), // Rule ID 51929 // |
| 10948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10949 | // (urem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREMU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 10950 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 10951 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10952 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E8), |
| 10955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10956 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10957 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10958 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10962 | GIR_RootConstrainSelectedInstOperands, |
| 10963 | // GIR_Coverage, 51929, |
| 10964 | GIR_EraseRootFromParent_Done, |
| 10965 | // Label 840: @25939 |
| 10966 | GIM_Reject, |
| 10967 | // Label 838: @25940 |
| 10968 | GIM_Reject, |
| 10969 | // Label 795: @25941 |
| 10970 | GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(26055), |
| 10971 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 10972 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 10973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10974 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10975 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 10976 | GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(26009), // Rule ID 51948 // |
| 10977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 10978 | // (urem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREMU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 10979 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 10980 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10981 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E16), |
| 10984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 10985 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10986 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 10987 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 10988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 10989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 10990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 10991 | GIR_RootConstrainSelectedInstOperands, |
| 10992 | // GIR_Coverage, 51948, |
| 10993 | GIR_EraseRootFromParent_Done, |
| 10994 | // Label 842: @26009 |
| 10995 | GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(26054), // Rule ID 51949 // |
| 10996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 10997 | // (urem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREMU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 10998 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 10999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11001 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E16), |
| 11003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11004 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11006 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11010 | GIR_RootConstrainSelectedInstOperands, |
| 11011 | // GIR_Coverage, 51949, |
| 11012 | GIR_EraseRootFromParent_Done, |
| 11013 | // Label 843: @26054 |
| 11014 | GIM_Reject, |
| 11015 | // Label 841: @26055 |
| 11016 | GIM_Reject, |
| 11017 | // Label 796: @26056 |
| 11018 | GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(26170), |
| 11019 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 11020 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 11021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11024 | GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(26124), // Rule ID 51984 // |
| 11025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11026 | // (urem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREMU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 11027 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 11028 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11029 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E32), |
| 11032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11033 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11034 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11035 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 11038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11039 | GIR_RootConstrainSelectedInstOperands, |
| 11040 | // GIR_Coverage, 51984, |
| 11041 | GIR_EraseRootFromParent_Done, |
| 11042 | // Label 845: @26124 |
| 11043 | GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(26169), // Rule ID 51985 // |
| 11044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11045 | // (urem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREMU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 11046 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 11047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11049 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E32), |
| 11051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11052 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11053 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11054 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 11057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11058 | GIR_RootConstrainSelectedInstOperands, |
| 11059 | // GIR_Coverage, 51985, |
| 11060 | GIR_EraseRootFromParent_Done, |
| 11061 | // Label 846: @26169 |
| 11062 | GIM_Reject, |
| 11063 | // Label 844: @26170 |
| 11064 | GIM_Reject, |
| 11065 | // Label 797: @26171 |
| 11066 | GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(26285), |
| 11067 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 11068 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 11069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11071 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11072 | GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(26239), // Rule ID 52000 // |
| 11073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 11074 | // (urem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREMU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 11075 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 11076 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11077 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11078 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E64), |
| 11080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11081 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11082 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11083 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 11086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11087 | GIR_RootConstrainSelectedInstOperands, |
| 11088 | // GIR_Coverage, 52000, |
| 11089 | GIR_EraseRootFromParent_Done, |
| 11090 | // Label 848: @26239 |
| 11091 | GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(26284), // Rule ID 52001 // |
| 11092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 11093 | // (urem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREMU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 11094 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 11095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E64), |
| 11099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11100 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11101 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11102 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 11105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11106 | GIR_RootConstrainSelectedInstOperands, |
| 11107 | // GIR_Coverage, 52001, |
| 11108 | GIR_EraseRootFromParent_Done, |
| 11109 | // Label 849: @26284 |
| 11110 | GIM_Reject, |
| 11111 | // Label 847: @26285 |
| 11112 | GIM_Reject, |
| 11113 | // Label 798: @26286 |
| 11114 | GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(26400), |
| 11115 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 11116 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 11117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 11118 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 11119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 11120 | GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(26354), // Rule ID 51944 // |
| 11121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11122 | // (urem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREMU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 11123 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 11124 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11125 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E8), |
| 11128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11129 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11130 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11131 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11135 | GIR_RootConstrainSelectedInstOperands, |
| 11136 | // GIR_Coverage, 51944, |
| 11137 | GIR_EraseRootFromParent_Done, |
| 11138 | // Label 851: @26354 |
| 11139 | GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(26399), // Rule ID 51945 // |
| 11140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11141 | // (urem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREMU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 11142 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 11143 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11144 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11145 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E8), |
| 11147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11148 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11149 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11150 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11154 | GIR_RootConstrainSelectedInstOperands, |
| 11155 | // GIR_Coverage, 51945, |
| 11156 | GIR_EraseRootFromParent_Done, |
| 11157 | // Label 852: @26399 |
| 11158 | GIM_Reject, |
| 11159 | // Label 850: @26400 |
| 11160 | GIM_Reject, |
| 11161 | // Label 799: @26401 |
| 11162 | GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(26515), |
| 11163 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 11164 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 11165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11167 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11168 | GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(26469), // Rule ID 51972 // |
| 11169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11170 | // (urem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREMU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 11171 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 11172 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11173 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E16), |
| 11176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11177 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11178 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11179 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11183 | GIR_RootConstrainSelectedInstOperands, |
| 11184 | // GIR_Coverage, 51972, |
| 11185 | GIR_EraseRootFromParent_Done, |
| 11186 | // Label 854: @26469 |
| 11187 | GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(26514), // Rule ID 51973 // |
| 11188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11189 | // (urem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREMU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 11190 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 11191 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11192 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E16), |
| 11195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11196 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11197 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11198 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11202 | GIR_RootConstrainSelectedInstOperands, |
| 11203 | // GIR_Coverage, 51973, |
| 11204 | GIR_EraseRootFromParent_Done, |
| 11205 | // Label 855: @26514 |
| 11206 | GIM_Reject, |
| 11207 | // Label 853: @26515 |
| 11208 | GIM_Reject, |
| 11209 | // Label 800: @26516 |
| 11210 | GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(26630), |
| 11211 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 11212 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 11213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11215 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11216 | GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(26584), // Rule ID 51988 // |
| 11217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11218 | // (urem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREMU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 11219 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 11220 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11221 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11222 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E32), |
| 11224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11225 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11226 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11227 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 11230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11231 | GIR_RootConstrainSelectedInstOperands, |
| 11232 | // GIR_Coverage, 51988, |
| 11233 | GIR_EraseRootFromParent_Done, |
| 11234 | // Label 857: @26584 |
| 11235 | GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(26629), // Rule ID 51989 // |
| 11236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11237 | // (urem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREMU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 11238 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 11239 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11240 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E32), |
| 11243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11244 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11245 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11246 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 11249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11250 | GIR_RootConstrainSelectedInstOperands, |
| 11251 | // GIR_Coverage, 51989, |
| 11252 | GIR_EraseRootFromParent_Done, |
| 11253 | // Label 858: @26629 |
| 11254 | GIM_Reject, |
| 11255 | // Label 856: @26630 |
| 11256 | GIM_Reject, |
| 11257 | // Label 801: @26631 |
| 11258 | GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(26745), |
| 11259 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 11260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 11261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11262 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11263 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11264 | GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(26699), // Rule ID 52004 // |
| 11265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 11266 | // (urem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREMU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 11267 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 11268 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11269 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11270 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E64), |
| 11272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11273 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11274 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11275 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 11278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11279 | GIR_RootConstrainSelectedInstOperands, |
| 11280 | // GIR_Coverage, 52004, |
| 11281 | GIR_EraseRootFromParent_Done, |
| 11282 | // Label 860: @26699 |
| 11283 | GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(26744), // Rule ID 52005 // |
| 11284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 11285 | // (urem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREMU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 11286 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 11287 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11288 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E64), |
| 11291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11292 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11293 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11294 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 11297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11298 | GIR_RootConstrainSelectedInstOperands, |
| 11299 | // GIR_Coverage, 52005, |
| 11300 | GIR_EraseRootFromParent_Done, |
| 11301 | // Label 861: @26744 |
| 11302 | GIM_Reject, |
| 11303 | // Label 859: @26745 |
| 11304 | GIM_Reject, |
| 11305 | // Label 802: @26746 |
| 11306 | GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(26860), |
| 11307 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 11308 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 11309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11310 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11311 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 11312 | GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(26814), // Rule ID 51960 // |
| 11313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11314 | // (urem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREMU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 11315 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 11316 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11317 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E8), |
| 11320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11321 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11322 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11323 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11327 | GIR_RootConstrainSelectedInstOperands, |
| 11328 | // GIR_Coverage, 51960, |
| 11329 | GIR_EraseRootFromParent_Done, |
| 11330 | // Label 863: @26814 |
| 11331 | GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(26859), // Rule ID 51961 // |
| 11332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11333 | // (urem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREMU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 11334 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 11335 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11336 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E8), |
| 11339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11340 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11341 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11342 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11346 | GIR_RootConstrainSelectedInstOperands, |
| 11347 | // GIR_Coverage, 51961, |
| 11348 | GIR_EraseRootFromParent_Done, |
| 11349 | // Label 864: @26859 |
| 11350 | GIM_Reject, |
| 11351 | // Label 862: @26860 |
| 11352 | GIM_Reject, |
| 11353 | // Label 803: @26861 |
| 11354 | GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(26975), |
| 11355 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 11356 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 11357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11358 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11359 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11360 | GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(26929), // Rule ID 51976 // |
| 11361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11362 | // (urem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREMU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 11363 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 11364 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11365 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11366 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E16), |
| 11368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11369 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11370 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11371 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11375 | GIR_RootConstrainSelectedInstOperands, |
| 11376 | // GIR_Coverage, 51976, |
| 11377 | GIR_EraseRootFromParent_Done, |
| 11378 | // Label 866: @26929 |
| 11379 | GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(26974), // Rule ID 51977 // |
| 11380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11381 | // (urem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREMU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 11382 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 11383 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11384 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E16), |
| 11387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11388 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11389 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11390 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11394 | GIR_RootConstrainSelectedInstOperands, |
| 11395 | // GIR_Coverage, 51977, |
| 11396 | GIR_EraseRootFromParent_Done, |
| 11397 | // Label 867: @26974 |
| 11398 | GIM_Reject, |
| 11399 | // Label 865: @26975 |
| 11400 | GIM_Reject, |
| 11401 | // Label 804: @26976 |
| 11402 | GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(27090), |
| 11403 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 11404 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 11405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11408 | GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(27044), // Rule ID 51992 // |
| 11409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11410 | // (urem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREMU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 11411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 11412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11413 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E32), |
| 11416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11417 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11418 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11419 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 11422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11423 | GIR_RootConstrainSelectedInstOperands, |
| 11424 | // GIR_Coverage, 51992, |
| 11425 | GIR_EraseRootFromParent_Done, |
| 11426 | // Label 869: @27044 |
| 11427 | GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(27089), // Rule ID 51993 // |
| 11428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11429 | // (urem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREMU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 11430 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 11431 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11432 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E32), |
| 11435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11436 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11437 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11438 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 11441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11442 | GIR_RootConstrainSelectedInstOperands, |
| 11443 | // GIR_Coverage, 51993, |
| 11444 | GIR_EraseRootFromParent_Done, |
| 11445 | // Label 870: @27089 |
| 11446 | GIM_Reject, |
| 11447 | // Label 868: @27090 |
| 11448 | GIM_Reject, |
| 11449 | // Label 805: @27091 |
| 11450 | GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(27205), |
| 11451 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 11452 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 11453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11454 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11455 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 11456 | GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(27159), // Rule ID 51964 // |
| 11457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11458 | // (urem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREMU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 11459 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 11460 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11461 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E8), |
| 11464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11465 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11466 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11467 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11471 | GIR_RootConstrainSelectedInstOperands, |
| 11472 | // GIR_Coverage, 51964, |
| 11473 | GIR_EraseRootFromParent_Done, |
| 11474 | // Label 872: @27159 |
| 11475 | GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(27204), // Rule ID 51965 // |
| 11476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11477 | // (urem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREMU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 11478 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 11479 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11480 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E8), |
| 11483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11484 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11485 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11486 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11490 | GIR_RootConstrainSelectedInstOperands, |
| 11491 | // GIR_Coverage, 51965, |
| 11492 | GIR_EraseRootFromParent_Done, |
| 11493 | // Label 873: @27204 |
| 11494 | GIM_Reject, |
| 11495 | // Label 871: @27205 |
| 11496 | GIM_Reject, |
| 11497 | // Label 806: @27206 |
| 11498 | GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(27320), |
| 11499 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 11500 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 11501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11504 | GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(27274), // Rule ID 51980 // |
| 11505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11506 | // (urem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREMU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 11507 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 11508 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11509 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11510 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E16), |
| 11512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11513 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11514 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11515 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11519 | GIR_RootConstrainSelectedInstOperands, |
| 11520 | // GIR_Coverage, 51980, |
| 11521 | GIR_EraseRootFromParent_Done, |
| 11522 | // Label 875: @27274 |
| 11523 | GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(27319), // Rule ID 51981 // |
| 11524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11525 | // (urem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREMU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 11526 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 11527 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11528 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11529 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E16), |
| 11531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11532 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11533 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11534 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 11537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11538 | GIR_RootConstrainSelectedInstOperands, |
| 11539 | // GIR_Coverage, 51981, |
| 11540 | GIR_EraseRootFromParent_Done, |
| 11541 | // Label 876: @27319 |
| 11542 | GIM_Reject, |
| 11543 | // Label 874: @27320 |
| 11544 | GIM_Reject, |
| 11545 | // Label 807: @27321 |
| 11546 | GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(27435), |
| 11547 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 11548 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 11549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11550 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 11552 | GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(27389), // Rule ID 51968 // |
| 11553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 11554 | // (urem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREMU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 11555 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 11556 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11557 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E8), |
| 11560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11561 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11562 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11563 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11567 | GIR_RootConstrainSelectedInstOperands, |
| 11568 | // GIR_Coverage, 51968, |
| 11569 | GIR_EraseRootFromParent_Done, |
| 11570 | // Label 878: @27389 |
| 11571 | GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(27434), // Rule ID 51969 // |
| 11572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 11573 | // (urem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREMU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 11574 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 11575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E8), |
| 11579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11580 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11581 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11582 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 11583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 11584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 11586 | GIR_RootConstrainSelectedInstOperands, |
| 11587 | // GIR_Coverage, 51969, |
| 11588 | GIR_EraseRootFromParent_Done, |
| 11589 | // Label 879: @27434 |
| 11590 | GIM_Reject, |
| 11591 | // Label 877: @27435 |
| 11592 | GIM_Reject, |
| 11593 | // Label 808: @27436 |
| 11594 | GIM_Reject, |
| 11595 | // Label 7: @27437 |
| 11596 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 911*/ GIMT_Encode4(36982), |
| 11597 | /*GILLT_s32*//*Label 880*/ GIMT_Encode4(27572), |
| 11598 | /*GILLT_s64*//*Label 881*/ GIMT_Encode4(29228), |
| 11599 | /*GILLT_nxv1s1*//*Label 882*/ GIMT_Encode4(30175), |
| 11600 | /*GILLT_nxv1s8*//*Label 883*/ GIMT_Encode4(30786), |
| 11601 | /*GILLT_nxv1s16*//*Label 884*/ GIMT_Encode4(30901), |
| 11602 | /*GILLT_nxv1s32*//*Label 885*/ GIMT_Encode4(31016), |
| 11603 | /*GILLT_nxv1s64*//*Label 886*/ GIMT_Encode4(31131), |
| 11604 | /*GILLT_nxv2s1*//*Label 887*/ GIMT_Encode4(31246), |
| 11605 | /*GILLT_nxv2s8*//*Label 888*/ GIMT_Encode4(31857), |
| 11606 | /*GILLT_nxv2s16*//*Label 889*/ GIMT_Encode4(31972), |
| 11607 | /*GILLT_nxv2s32*//*Label 890*/ GIMT_Encode4(32087), |
| 11608 | /*GILLT_nxv2s64*//*Label 891*/ GIMT_Encode4(32202), |
| 11609 | /*GILLT_nxv4s1*//*Label 892*/ GIMT_Encode4(32317), |
| 11610 | /*GILLT_nxv4s8*//*Label 893*/ GIMT_Encode4(32928), |
| 11611 | /*GILLT_nxv4s16*//*Label 894*/ GIMT_Encode4(33043), |
| 11612 | /*GILLT_nxv4s32*//*Label 895*/ GIMT_Encode4(33158), |
| 11613 | /*GILLT_nxv4s64*//*Label 896*/ GIMT_Encode4(33273), |
| 11614 | /*GILLT_nxv8s1*//*Label 897*/ GIMT_Encode4(33388), |
| 11615 | /*GILLT_nxv8s8*//*Label 898*/ GIMT_Encode4(33999), |
| 11616 | /*GILLT_nxv8s16*//*Label 899*/ GIMT_Encode4(34114), |
| 11617 | /*GILLT_nxv8s32*//*Label 900*/ GIMT_Encode4(34229), |
| 11618 | /*GILLT_nxv8s64*//*Label 901*/ GIMT_Encode4(34344), |
| 11619 | /*GILLT_nxv16s1*//*Label 902*/ GIMT_Encode4(34459), |
| 11620 | /*GILLT_nxv16s8*//*Label 903*/ GIMT_Encode4(35070), |
| 11621 | /*GILLT_nxv16s16*//*Label 904*/ GIMT_Encode4(35185), |
| 11622 | /*GILLT_nxv16s32*//*Label 905*/ GIMT_Encode4(35300), |
| 11623 | /*GILLT_nxv32s1*//*Label 906*/ GIMT_Encode4(35415), |
| 11624 | /*GILLT_nxv32s8*//*Label 907*/ GIMT_Encode4(36026), |
| 11625 | /*GILLT_nxv32s16*//*Label 908*/ GIMT_Encode4(36141), |
| 11626 | /*GILLT_nxv64s1*//*Label 909*/ GIMT_Encode4(36256), |
| 11627 | /*GILLT_nxv64s8*//*Label 910*/ GIMT_Encode4(36867), |
| 11628 | // Label 880: @27572 |
| 11629 | GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(29227), |
| 11630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11631 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 11632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11633 | GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(27662), // Rule ID 2621 // |
| 11634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 11635 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11636 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11637 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11638 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11639 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11640 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 11641 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 11642 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 11643 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, |
| 11644 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11646 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11647 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 11648 | // (and:{ *:[i32] } (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11651 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 11653 | GIR_RootConstrainSelectedInstOperands, |
| 11654 | // GIR_Coverage, 2621, |
| 11655 | GIR_EraseRootFromParent_Done, |
| 11656 | // Label 913: @27662 |
| 11657 | GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(27737), // Rule ID 2848 // |
| 11658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 11659 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11660 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11661 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11662 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11663 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11664 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 11665 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 11666 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 11667 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, |
| 11668 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11669 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11670 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11671 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 11672 | // (and:{ *:[i32] } (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 11673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11675 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 11677 | GIR_RootConstrainSelectedInstOperands, |
| 11678 | // GIR_Coverage, 2848, |
| 11679 | GIR_EraseRootFromParent_Done, |
| 11680 | // Label 914: @27737 |
| 11681 | GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(27812), // Rule ID 65200 // |
| 11682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 11683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11687 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11688 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11689 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 11690 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 11691 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 11692 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, |
| 11693 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11694 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11695 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 11696 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), -1:{ *:[i32] })) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11699 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 11701 | GIR_RootConstrainSelectedInstOperands, |
| 11702 | // GIR_Coverage, 65200, |
| 11703 | GIR_EraseRootFromParent_Done, |
| 11704 | // Label 915: @27812 |
| 11705 | GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(27887), // Rule ID 65304 // |
| 11706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 11707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11708 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11709 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11710 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11711 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11712 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11713 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 11714 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 11715 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 11716 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, |
| 11717 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11718 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11719 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 11720 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i32] })) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 11721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11723 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 11725 | GIR_RootConstrainSelectedInstOperands, |
| 11726 | // GIR_Coverage, 65304, |
| 11727 | GIR_EraseRootFromParent_Done, |
| 11728 | // Label 916: @27887 |
| 11729 | GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(27948), // Rule ID 2641 // |
| 11730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 11731 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 11733 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11734 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11735 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11736 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11737 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11738 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 11739 | // MIs[2] Operand 1 |
| 11740 | // No operand predicates |
| 11741 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 11742 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11743 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i32] }) => (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) |
| 11744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), |
| 11745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 11747 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 11748 | GIR_RootConstrainSelectedInstOperands, |
| 11749 | // GIR_Coverage, 2641, |
| 11750 | GIR_EraseRootFromParent_Done, |
| 11751 | // Label 917: @27948 |
| 11752 | GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(28009), // Rule ID 2856 // |
| 11753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 11754 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11755 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 11756 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11757 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 11758 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11759 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11760 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11761 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 11762 | // MIs[2] Operand 1 |
| 11763 | // No operand predicates |
| 11764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 11765 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11766 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt), 1:{ *:[i32] }) => (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) |
| 11767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), |
| 11768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11769 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 11770 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 11771 | GIR_RootConstrainSelectedInstOperands, |
| 11772 | // GIR_Coverage, 2856, |
| 11773 | GIR_EraseRootFromParent_Done, |
| 11774 | // Label 918: @28009 |
| 11775 | GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(28070), // Rule ID 2857 // |
| 11776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode1), |
| 11777 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11778 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 11779 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11780 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11781 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11782 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11783 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11784 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 11785 | // MIs[2] Operand 1 |
| 11786 | // No operand predicates |
| 11787 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 11788 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11789 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$shamt), 1:{ *:[i32] }) => (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$shamt) |
| 11790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), |
| 11791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 11793 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 11794 | GIR_RootConstrainSelectedInstOperands, |
| 11795 | // GIR_Coverage, 2857, |
| 11796 | GIR_EraseRootFromParent_Done, |
| 11797 | // Label 919: @28070 |
| 11798 | GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(28131), // Rule ID 63037 // |
| 11799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBs_HwMode1), |
| 11800 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11801 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 11802 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11803 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11804 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11805 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11806 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11807 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 11808 | // MIs[2] Operand 1 |
| 11809 | // No operand predicates |
| 11810 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 11811 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11812 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i32] }) => (TH_TST:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) |
| 11813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_TST), |
| 11814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 11816 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 11817 | GIR_RootConstrainSelectedInstOperands, |
| 11818 | // GIR_Coverage, 63037, |
| 11819 | GIR_EraseRootFromParent_Done, |
| 11820 | // Label 920: @28131 |
| 11821 | GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(28189), // Rule ID 2629 // |
| 11822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 11823 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11824 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 11825 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11826 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11827 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11828 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 11829 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11830 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 11831 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), 1:{ *:[i32] }) => (BEXT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), |
| 11833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 11835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 11836 | GIR_RootConstrainSelectedInstOperands, |
| 11837 | // GIR_Coverage, 2629, |
| 11838 | GIR_EraseRootFromParent_Done, |
| 11839 | // Label 921: @28189 |
| 11840 | GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(28247), // Rule ID 2852 // |
| 11841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 11842 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11843 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 11844 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11845 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 11846 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11847 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 11848 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11849 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 11850 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), 1:{ *:[i32] }) => (BEXT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 11851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), |
| 11852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 11854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 11855 | GIR_RootConstrainSelectedInstOperands, |
| 11856 | // GIR_Coverage, 2852, |
| 11857 | GIR_EraseRootFromParent_Done, |
| 11858 | // Label 922: @28247 |
| 11859 | GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(28299), // Rule ID 2623 // |
| 11860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 11861 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11862 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), |
| 11863 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11864 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11865 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), |
| 11866 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11868 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11869 | // (and:{ *:[i32] } (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 11874 | GIR_RootConstrainSelectedInstOperands, |
| 11875 | // GIR_Coverage, 2623, |
| 11876 | GIR_EraseRootFromParent_Done, |
| 11877 | // Label 923: @28299 |
| 11878 | GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(28351), // Rule ID 2849 // |
| 11879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 11880 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11881 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), |
| 11882 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11883 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 11884 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), |
| 11885 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11886 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11887 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11888 | // (and:{ *:[i32] } (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 11889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11891 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 11893 | GIR_RootConstrainSelectedInstOperands, |
| 11894 | // GIR_Coverage, 2849, |
| 11895 | GIR_EraseRootFromParent_Done, |
| 11896 | // Label 924: @28351 |
| 11897 | GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(28403), // Rule ID 65192 // |
| 11898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 11899 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11900 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11901 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11902 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11903 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11904 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11905 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11906 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11907 | // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 11909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11910 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 11912 | GIR_RootConstrainSelectedInstOperands, |
| 11913 | // GIR_Coverage, 65192, |
| 11914 | GIR_EraseRootFromParent_Done, |
| 11915 | // Label 925: @28403 |
| 11916 | GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(28455), // Rule ID 65275 // |
| 11917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 11918 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11919 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11920 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11921 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11922 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11923 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11924 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11925 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11926 | // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 11928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11929 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 11931 | GIR_RootConstrainSelectedInstOperands, |
| 11932 | // GIR_Coverage, 65275, |
| 11933 | GIR_EraseRootFromParent_Done, |
| 11934 | // Label 926: @28455 |
| 11935 | GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(28507), // Rule ID 65276 // |
| 11936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 11937 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11938 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11939 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11940 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11941 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11942 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 11943 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11944 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11945 | // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 11947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11948 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 11949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 11950 | GIR_RootConstrainSelectedInstOperands, |
| 11951 | // GIR_Coverage, 65276, |
| 11952 | GIR_EraseRootFromParent_Done, |
| 11953 | // Label 927: @28507 |
| 11954 | GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(28559), // Rule ID 65202 // |
| 11955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 11956 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11957 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11958 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), |
| 11959 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11960 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11961 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), |
| 11962 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11963 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11964 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i32] }:$rs2)) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 11965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11967 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 11969 | GIR_RootConstrainSelectedInstOperands, |
| 11970 | // GIR_Coverage, 65202, |
| 11971 | GIR_EraseRootFromParent_Done, |
| 11972 | // Label 928: @28559 |
| 11973 | GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(28611), // Rule ID 65305 // |
| 11974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 11975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), |
| 11978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11979 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 11980 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), |
| 11981 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11982 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 11983 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i64] }:$rs2)) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 11984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 11985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 11986 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 11987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 11988 | GIR_RootConstrainSelectedInstOperands, |
| 11989 | // GIR_Coverage, 65305, |
| 11990 | GIR_EraseRootFromParent_Done, |
| 11991 | // Label 929: @28611 |
| 11992 | GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(28663), // Rule ID 2603 // |
| 11993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 11994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 11995 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11996 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 11997 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 11998 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 11999 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12000 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12001 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12002 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 12003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 12004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12007 | GIR_RootConstrainSelectedInstOperands, |
| 12008 | // GIR_Coverage, 2603, |
| 12009 | GIR_EraseRootFromParent_Done, |
| 12010 | // Label 930: @28663 |
| 12011 | GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(28715), // Rule ID 2807 // |
| 12012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 12013 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12014 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12015 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12016 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12017 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12018 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12019 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12020 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12021 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 12022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 12023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12024 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12026 | GIR_RootConstrainSelectedInstOperands, |
| 12027 | // GIR_Coverage, 2807, |
| 12028 | GIR_EraseRootFromParent_Done, |
| 12029 | // Label 931: @28715 |
| 12030 | GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(28767), // Rule ID 2808 // |
| 12031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 12032 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12037 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12038 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12039 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12040 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 12041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 12042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12043 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12045 | GIR_RootConstrainSelectedInstOperands, |
| 12046 | // GIR_Coverage, 2808, |
| 12047 | GIR_EraseRootFromParent_Done, |
| 12048 | // Label 932: @28767 |
| 12049 | GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(28799), // Rule ID 64992 // |
| 12050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 12051 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12052 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12053 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 65535:{ *:[i32] }) => (CV_EXTHZ:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 12054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_EXTHZ), |
| 12055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12056 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12057 | GIR_RootConstrainSelectedInstOperands, |
| 12058 | // GIR_Coverage, 64992, |
| 12059 | GIR_EraseRootFromParent_Done, |
| 12060 | // Label 933: @28799 |
| 12061 | GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(28831), // Rule ID 2701 // |
| 12062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV32_HwMode0), |
| 12063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12064 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12065 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs) |
| 12066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV32), |
| 12067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12069 | GIR_RootConstrainSelectedInstOperands, |
| 12070 | // GIR_Coverage, 2701, |
| 12071 | GIR_EraseRootFromParent_Done, |
| 12072 | // Label 934: @28831 |
| 12073 | GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(28863), // Rule ID 2702 // |
| 12074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV32_HwMode1), |
| 12075 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12076 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12077 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs) |
| 12078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV32), |
| 12079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12080 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12081 | GIR_RootConstrainSelectedInstOperands, |
| 12082 | // GIR_Coverage, 2702, |
| 12083 | GIR_EraseRootFromParent_Done, |
| 12084 | // Label 935: @28863 |
| 12085 | GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(28901), // Rule ID 2704 // |
| 12086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode0), |
| 12087 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12088 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12089 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACK:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i64] }) |
| 12090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACK), |
| 12091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12092 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12093 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12094 | GIR_RootConstrainSelectedInstOperands, |
| 12095 | // GIR_Coverage, 2704, |
| 12096 | GIR_EraseRootFromParent_Done, |
| 12097 | // Label 936: @28901 |
| 12098 | GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(28939), // Rule ID 2705 // |
| 12099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode1), |
| 12100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12101 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12102 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACK:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i32] }) |
| 12103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACK), |
| 12104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12105 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12106 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12107 | GIR_RootConstrainSelectedInstOperands, |
| 12108 | // GIR_Coverage, 2705, |
| 12109 | GIR_EraseRootFromParent_Done, |
| 12110 | // Label 937: @28939 |
| 12111 | GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(28971), // Rule ID 2803 // |
| 12112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), |
| 12113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12114 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12115 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV64:{ *:[i32] } GPR:{ *:[i32] }:$rs) |
| 12116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV64), |
| 12117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12118 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12119 | GIR_RootConstrainSelectedInstOperands, |
| 12120 | // GIR_Coverage, 2803, |
| 12121 | GIR_EraseRootFromParent_Done, |
| 12122 | // Label 938: @28971 |
| 12123 | GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(29003), // Rule ID 2804 // |
| 12124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode1), |
| 12125 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12126 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12127 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV64:{ *:[i32] } GPR:{ *:[i32] }:$rs) |
| 12128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV64), |
| 12129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12130 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12131 | GIR_RootConstrainSelectedInstOperands, |
| 12132 | // GIR_Coverage, 2804, |
| 12133 | GIR_EraseRootFromParent_Done, |
| 12134 | // Label 939: @29003 |
| 12135 | GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(29041), // Rule ID 2805 // |
| 12136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode0), |
| 12137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12138 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12139 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACKW:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i64] }) |
| 12140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACKW), |
| 12141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12142 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12143 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12144 | GIR_RootConstrainSelectedInstOperands, |
| 12145 | // GIR_Coverage, 2805, |
| 12146 | GIR_EraseRootFromParent_Done, |
| 12147 | // Label 940: @29041 |
| 12148 | GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(29079), // Rule ID 2806 // |
| 12149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode1), |
| 12150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12151 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12152 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACKW:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i32] }) |
| 12153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACKW), |
| 12154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12156 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12157 | GIR_RootConstrainSelectedInstOperands, |
| 12158 | // GIR_Coverage, 2806, |
| 12159 | GIR_EraseRootFromParent_Done, |
| 12160 | // Label 941: @29079 |
| 12161 | GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(29117), // Rule ID 79 // |
| 12162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 12163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12164 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12165 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12166 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 12167 | // MIs[1] Operand 1 |
| 12168 | // No operand predicates |
| 12169 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12170 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) |
| 12171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDI), |
| 12172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12173 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12174 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 12175 | GIR_RootConstrainSelectedInstOperands, |
| 12176 | // GIR_Coverage, 79, |
| 12177 | GIR_EraseRootFromParent_Done, |
| 12178 | // Label 942: @29117 |
| 12179 | GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(29157), // Rule ID 311 // |
| 12180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 12181 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12182 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12183 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12184 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12i32), |
| 12185 | // MIs[1] Operand 1 |
| 12186 | // No operand predicates |
| 12187 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12188 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12i32>>:$imm) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (as_i64imm:{ *:[i64] } ?:{ *:[i32] }:$imm)) |
| 12189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDI), |
| 12190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12191 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12192 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm |
| 12193 | GIR_RootConstrainSelectedInstOperands, |
| 12194 | // GIR_Coverage, 311, |
| 12195 | GIR_EraseRootFromParent_Done, |
| 12196 | // Label 943: @29157 |
| 12197 | GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(29180), // Rule ID 77 // |
| 12198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 12199 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12200 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12201 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 12202 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), |
| 12203 | GIR_RootConstrainSelectedInstOperands, |
| 12204 | // GIR_Coverage, 77, |
| 12205 | GIR_Done, |
| 12206 | // Label 944: @29180 |
| 12207 | GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(29203), // Rule ID 301 // |
| 12208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 12209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12211 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 12212 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), |
| 12213 | GIR_RootConstrainSelectedInstOperands, |
| 12214 | // GIR_Coverage, 301, |
| 12215 | GIR_Done, |
| 12216 | // Label 945: @29203 |
| 12217 | GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(29226), // Rule ID 302 // |
| 12218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 12219 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12220 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12221 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 12222 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), |
| 12223 | GIR_RootConstrainSelectedInstOperands, |
| 12224 | // GIR_Coverage, 302, |
| 12225 | GIR_Done, |
| 12226 | // Label 946: @29226 |
| 12227 | GIM_Reject, |
| 12228 | // Label 912: @29227 |
| 12229 | GIM_Reject, |
| 12230 | // Label 881: @29228 |
| 12231 | GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(30174), |
| 12232 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12233 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 12234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12235 | GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(29318), // Rule ID 2620 // |
| 12236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 12237 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12238 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12239 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12240 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12241 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12242 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 12243 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12244 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 12245 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, |
| 12246 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12247 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12248 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12249 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 12250 | // (and:{ *:[i64] } (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 12252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12253 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 12255 | GIR_RootConstrainSelectedInstOperands, |
| 12256 | // GIR_Coverage, 2620, |
| 12257 | GIR_EraseRootFromParent_Done, |
| 12258 | // Label 948: @29318 |
| 12259 | GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(29393), // Rule ID 65199 // |
| 12260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 12261 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12263 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12265 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12266 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12267 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 12268 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12269 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 12270 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, |
| 12271 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12272 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12273 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 12274 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i64] })) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 12276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12277 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 12279 | GIR_RootConstrainSelectedInstOperands, |
| 12280 | // GIR_Coverage, 65199, |
| 12281 | GIR_EraseRootFromParent_Done, |
| 12282 | // Label 949: @29393 |
| 12283 | GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(29463), // Rule ID 2853 // |
| 12284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 12285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 12287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12288 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12289 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 12290 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 12291 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 12292 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12293 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 12294 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12295 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 12296 | // (and:{ *:[i64] } (anyext:{ *:[i64] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2))), 1:{ *:[i64] }) => (BEXT:{ *:[i64] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), |
| 12298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 12300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 12301 | GIR_RootConstrainSelectedInstOperands, |
| 12302 | // GIR_Coverage, 2853, |
| 12303 | GIR_EraseRootFromParent_Done, |
| 12304 | // Label 950: @29463 |
| 12305 | GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(29524), // Rule ID 2640 // |
| 12306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 12307 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12308 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 12309 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12310 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12311 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12312 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12313 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12314 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 12315 | // MIs[2] Operand 1 |
| 12316 | // No operand predicates |
| 12317 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 12318 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12319 | // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i64] }) => (BEXTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) |
| 12320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), |
| 12321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12322 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 12323 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 12324 | GIR_RootConstrainSelectedInstOperands, |
| 12325 | // GIR_Coverage, 2640, |
| 12326 | GIR_EraseRootFromParent_Done, |
| 12327 | // Label 951: @29524 |
| 12328 | GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(29585), // Rule ID 63036 // |
| 12329 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBs_HwMode0), |
| 12330 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12331 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 12332 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12333 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12334 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12335 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12336 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12337 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 12338 | // MIs[2] Operand 1 |
| 12339 | // No operand predicates |
| 12340 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 12341 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12342 | // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i64] }) => (TH_TST:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) |
| 12343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_TST), |
| 12344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 12346 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 12347 | GIR_RootConstrainSelectedInstOperands, |
| 12348 | // GIR_Coverage, 63036, |
| 12349 | GIR_EraseRootFromParent_Done, |
| 12350 | // Label 952: @29585 |
| 12351 | GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(29643), // Rule ID 2628 // |
| 12352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 12353 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12354 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 12355 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12356 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12357 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12358 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 12359 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12360 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 12361 | // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), 1:{ *:[i64] }) => (BEXT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), |
| 12363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 12365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 12366 | GIR_RootConstrainSelectedInstOperands, |
| 12367 | // GIR_Coverage, 2628, |
| 12368 | GIR_EraseRootFromParent_Done, |
| 12369 | // Label 953: @29643 |
| 12370 | GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(29695), // Rule ID 2622 // |
| 12371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 12372 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12373 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), |
| 12374 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12375 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12376 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), |
| 12377 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12378 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12379 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12380 | // (and:{ *:[i64] } (rotl:{ *:[i64] } -2:{ *:[i64] }, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i64] }:$rs1) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 12382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12383 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 12385 | GIR_RootConstrainSelectedInstOperands, |
| 12386 | // GIR_Coverage, 2622, |
| 12387 | GIR_EraseRootFromParent_Done, |
| 12388 | // Label 954: @29695 |
| 12389 | GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(29747), // Rule ID 65191 // |
| 12390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 12391 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12392 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12393 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12394 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12395 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12396 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12397 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12398 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12399 | // (and:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1) => (ANDN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 12401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12402 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12404 | GIR_RootConstrainSelectedInstOperands, |
| 12405 | // GIR_Coverage, 65191, |
| 12406 | GIR_EraseRootFromParent_Done, |
| 12407 | // Label 955: @29747 |
| 12408 | GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(29799), // Rule ID 65201 // |
| 12409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 12410 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12411 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12412 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), |
| 12413 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12414 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12415 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), |
| 12416 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12417 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12418 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (rotl:{ *:[i64] } -2:{ *:[i64] }, GPR:{ *:[i64] }:$rs2)) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), |
| 12420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12421 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 12423 | GIR_RootConstrainSelectedInstOperands, |
| 12424 | // GIR_Coverage, 65201, |
| 12425 | GIR_EraseRootFromParent_Done, |
| 12426 | // Label 956: @29799 |
| 12427 | GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(29851), // Rule ID 2602 // |
| 12428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 12429 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12430 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12431 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12432 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 12433 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 12434 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12435 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 12436 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12437 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] })) => (ANDN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), |
| 12439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12440 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12442 | GIR_RootConstrainSelectedInstOperands, |
| 12443 | // GIR_Coverage, 2602, |
| 12444 | GIR_EraseRootFromParent_Done, |
| 12445 | // Label 957: @29851 |
| 12446 | GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(29883), // Rule ID 64991 // |
| 12447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 12448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12449 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12450 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 65535:{ *:[i64] }) => (CV_EXTHZ:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 12451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_EXTHZ), |
| 12452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12453 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12454 | GIR_RootConstrainSelectedInstOperands, |
| 12455 | // GIR_Coverage, 64991, |
| 12456 | GIR_EraseRootFromParent_Done, |
| 12457 | // Label 958: @29883 |
| 12458 | GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(29940), // Rule ID 243 // |
| 12459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_NotHasStdExtZba_HwMode0), |
| 12460 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12461 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295), |
| 12462 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), 32:{ *:[i64] }) |
| 12463 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12464 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 12465 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12466 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 12467 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 12468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 12470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12471 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/32, |
| 12473 | GIR_RootConstrainSelectedInstOperands, |
| 12474 | // GIR_Coverage, 243, |
| 12475 | GIR_EraseRootFromParent_Done, |
| 12476 | // Label 959: @29940 |
| 12477 | GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(29972), // Rule ID 2703 // |
| 12478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), |
| 12479 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12480 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12481 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 65535:{ *:[i64] }) => (ZEXT_H_RV64:{ *:[i64] } GPR:{ *:[i64] }:$rs) |
| 12482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV64), |
| 12483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12484 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12485 | GIR_RootConstrainSelectedInstOperands, |
| 12486 | // GIR_Coverage, 2703, |
| 12487 | GIR_EraseRootFromParent_Done, |
| 12488 | // Label 960: @29972 |
| 12489 | GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(30010), // Rule ID 2706 // |
| 12490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode0), |
| 12491 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12492 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 12493 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 65535:{ *:[i64] }) => (PACKW:{ *:[i64] } GPR:{ *:[i64] }:$rs, X0:{ *:[i64] }) |
| 12494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACKW), |
| 12495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12496 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12497 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12498 | GIR_RootConstrainSelectedInstOperands, |
| 12499 | // GIR_Coverage, 2706, |
| 12500 | GIR_EraseRootFromParent_Done, |
| 12501 | // Label 961: @30010 |
| 12502 | GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(30048), // Rule ID 2749 // |
| 12503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 12504 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12505 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295), |
| 12506 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 4294967295:{ *:[i64] }) => (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs, X0:{ *:[i64] }) |
| 12507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), |
| 12508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12509 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 12510 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12511 | GIR_RootConstrainSelectedInstOperands, |
| 12512 | // GIR_Coverage, 2749, |
| 12513 | GIR_EraseRootFromParent_Done, |
| 12514 | // Label 962: @30048 |
| 12515 | GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(30086), // Rule ID 78 // |
| 12516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 12517 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12518 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12519 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12520 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 12521 | // MIs[1] Operand 1 |
| 12522 | // No operand predicates |
| 12523 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12524 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) |
| 12525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDI), |
| 12526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12527 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12528 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 12529 | GIR_RootConstrainSelectedInstOperands, |
| 12530 | // GIR_Coverage, 78, |
| 12531 | GIR_EraseRootFromParent_Done, |
| 12532 | // Label 963: @30086 |
| 12533 | GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(30150), // Rule ID 2746 // |
| 12534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 12535 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12536 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12537 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12538 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_Shifted32OnesMask), |
| 12539 | // MIs[1] Operand 1 |
| 12540 | // No operand predicates |
| 12541 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 12542 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_Shifted32OnesMask>><<X:TrailingZeros>>:$mask) => (SLLI_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (TrailingZeros:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_Shifted32OnesMask>>:$mask)), (TrailingZeros:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_Shifted32OnesMask>>:$mask)) |
| 12543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 12545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12546 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 12547 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTrailingZeros), // mask |
| 12548 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLI_UW), |
| 12550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12551 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12552 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTrailingZeros), // mask |
| 12553 | GIR_RootConstrainSelectedInstOperands, |
| 12554 | // GIR_Coverage, 2746, |
| 12555 | GIR_EraseRootFromParent_Done, |
| 12556 | // Label 964: @30150 |
| 12557 | GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(30173), // Rule ID 76 // |
| 12558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 12559 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12560 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 12561 | // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AND:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 12562 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), |
| 12563 | GIR_RootConstrainSelectedInstOperands, |
| 12564 | // GIR_Coverage, 76, |
| 12565 | GIR_Done, |
| 12566 | // Label 965: @30173 |
| 12567 | GIM_Reject, |
| 12568 | // Label 947: @30174 |
| 12569 | GIM_Reject, |
| 12570 | // Label 882: @30175 |
| 12571 | GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(30785), |
| 12572 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12573 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12575 | GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(30256), // Rule ID 71268 // |
| 12576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12578 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12579 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12580 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12581 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12582 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12583 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12584 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12586 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12587 | // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs2), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 12588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12590 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 12592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12594 | GIR_RootConstrainSelectedInstOperands, |
| 12595 | // GIR_Coverage, 71268, |
| 12596 | GIR_EraseRootFromParent_Done, |
| 12597 | // Label 967: @30256 |
| 12598 | GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(30322), // Rule ID 71269 // |
| 12599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12600 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12601 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12602 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12603 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12604 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12605 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12606 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 12607 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12608 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12609 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12610 | // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs2), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 12611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12613 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 12615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12617 | GIR_RootConstrainSelectedInstOperands, |
| 12618 | // GIR_Coverage, 71269, |
| 12619 | GIR_EraseRootFromParent_Done, |
| 12620 | // Label 968: @30322 |
| 12621 | GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(30388), // Rule ID 71266 // |
| 12622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12623 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12624 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12625 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12626 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12627 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12628 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12629 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12630 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12631 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12632 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12633 | // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 12634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12636 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12640 | GIR_RootConstrainSelectedInstOperands, |
| 12641 | // GIR_Coverage, 71266, |
| 12642 | GIR_EraseRootFromParent_Done, |
| 12643 | // Label 969: @30388 |
| 12644 | GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(30454), // Rule ID 71267 // |
| 12645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12647 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12648 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12649 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12650 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12651 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12652 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12653 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 12654 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12655 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12656 | // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 12657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12659 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 12660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12663 | GIR_RootConstrainSelectedInstOperands, |
| 12664 | // GIR_Coverage, 71267, |
| 12665 | GIR_EraseRootFromParent_Done, |
| 12666 | // Label 970: @30454 |
| 12667 | GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(30520), // Rule ID 71264 // |
| 12668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12669 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12670 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12671 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12672 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12673 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12674 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12675 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12676 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12677 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12678 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12679 | // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 12680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 12684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12686 | GIR_RootConstrainSelectedInstOperands, |
| 12687 | // GIR_Coverage, 71264, |
| 12688 | GIR_EraseRootFromParent_Done, |
| 12689 | // Label 971: @30520 |
| 12690 | GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(30586), // Rule ID 71265 // |
| 12691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 12700 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12701 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12702 | // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 12703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12705 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 12707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12709 | GIR_RootConstrainSelectedInstOperands, |
| 12710 | // GIR_Coverage, 71265, |
| 12711 | GIR_EraseRootFromParent_Done, |
| 12712 | // Label 972: @30586 |
| 12713 | GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(30652), // Rule ID 53796 // |
| 12714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12721 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12722 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12723 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12724 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12725 | // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 12726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12728 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12732 | GIR_RootConstrainSelectedInstOperands, |
| 12733 | // GIR_Coverage, 53796, |
| 12734 | GIR_EraseRootFromParent_Done, |
| 12735 | // Label 973: @30652 |
| 12736 | GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(30718), // Rule ID 53797 // |
| 12737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12738 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12740 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12741 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 12742 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 12743 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12744 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12745 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12746 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 12747 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12748 | // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 12749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), |
| 12750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 12753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12755 | GIR_RootConstrainSelectedInstOperands, |
| 12756 | // GIR_Coverage, 53797, |
| 12757 | GIR_EraseRootFromParent_Done, |
| 12758 | // Label 974: @30718 |
| 12759 | GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(30751), // Rule ID 53784 // |
| 12760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12761 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12762 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12763 | // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 12764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF8), |
| 12765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12767 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12770 | GIR_RootConstrainSelectedInstOperands, |
| 12771 | // GIR_Coverage, 53784, |
| 12772 | GIR_EraseRootFromParent_Done, |
| 12773 | // Label 975: @30751 |
| 12774 | GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(30784), // Rule ID 53785 // |
| 12775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12777 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12778 | // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 12779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF8), |
| 12780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12781 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12782 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12785 | GIR_RootConstrainSelectedInstOperands, |
| 12786 | // GIR_Coverage, 53785, |
| 12787 | GIR_EraseRootFromParent_Done, |
| 12788 | // Label 976: @30784 |
| 12789 | GIM_Reject, |
| 12790 | // Label 966: @30785 |
| 12791 | GIM_Reject, |
| 12792 | // Label 883: @30786 |
| 12793 | GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(30900), |
| 12794 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 12795 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 12796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12797 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12798 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12799 | GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(30854), // Rule ID 48280 // |
| 12800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12801 | // (and:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVAND_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 12802 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 12803 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12804 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12805 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF8), |
| 12807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12808 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12809 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12810 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12814 | GIR_RootConstrainSelectedInstOperands, |
| 12815 | // GIR_Coverage, 48280, |
| 12816 | GIR_EraseRootFromParent_Done, |
| 12817 | // Label 978: @30854 |
| 12818 | GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(30899), // Rule ID 48281 // |
| 12819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12820 | // (and:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVAND_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 12821 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 12822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF8), |
| 12826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12827 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12828 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12829 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12833 | GIR_RootConstrainSelectedInstOperands, |
| 12834 | // GIR_Coverage, 48281, |
| 12835 | GIR_EraseRootFromParent_Done, |
| 12836 | // Label 979: @30899 |
| 12837 | GIM_Reject, |
| 12838 | // Label 977: @30900 |
| 12839 | GIM_Reject, |
| 12840 | // Label 884: @30901 |
| 12841 | GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(31015), |
| 12842 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 12843 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 12844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12845 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12846 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12847 | GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(30969), // Rule ID 48292 // |
| 12848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12849 | // (and:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 12850 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 12851 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12852 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), |
| 12855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12856 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12857 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12858 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 12861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12862 | GIR_RootConstrainSelectedInstOperands, |
| 12863 | // GIR_Coverage, 48292, |
| 12864 | GIR_EraseRootFromParent_Done, |
| 12865 | // Label 981: @30969 |
| 12866 | GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(31014), // Rule ID 48293 // |
| 12867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12868 | // (and:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 12869 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 12870 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12871 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), |
| 12874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12875 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12876 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12877 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 12880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12881 | GIR_RootConstrainSelectedInstOperands, |
| 12882 | // GIR_Coverage, 48293, |
| 12883 | GIR_EraseRootFromParent_Done, |
| 12884 | // Label 982: @31014 |
| 12885 | GIM_Reject, |
| 12886 | // Label 980: @31015 |
| 12887 | GIM_Reject, |
| 12888 | // Label 885: @31016 |
| 12889 | GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(31130), |
| 12890 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 12891 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 12892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12893 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12894 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12895 | GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(31084), // Rule ID 48300 // |
| 12896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12897 | // (and:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 12898 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 12899 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12900 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), |
| 12903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12904 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12905 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12906 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 12909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12910 | GIR_RootConstrainSelectedInstOperands, |
| 12911 | // GIR_Coverage, 48300, |
| 12912 | GIR_EraseRootFromParent_Done, |
| 12913 | // Label 984: @31084 |
| 12914 | GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(31129), // Rule ID 48301 // |
| 12915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 12916 | // (and:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 12917 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 12918 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12919 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), |
| 12922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12923 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12924 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12925 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 12928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12929 | GIR_RootConstrainSelectedInstOperands, |
| 12930 | // GIR_Coverage, 48301, |
| 12931 | GIR_EraseRootFromParent_Done, |
| 12932 | // Label 985: @31129 |
| 12933 | GIM_Reject, |
| 12934 | // Label 983: @31130 |
| 12935 | GIM_Reject, |
| 12936 | // Label 886: @31131 |
| 12937 | GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(31245), |
| 12938 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 12939 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 12940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12941 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12942 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12943 | GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(31199), // Rule ID 48316 // |
| 12944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 12945 | // (and:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 12946 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 12947 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12948 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12949 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 12951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12952 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12953 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12954 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 12957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12958 | GIR_RootConstrainSelectedInstOperands, |
| 12959 | // GIR_Coverage, 48316, |
| 12960 | GIR_EraseRootFromParent_Done, |
| 12961 | // Label 987: @31199 |
| 12962 | GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(31244), // Rule ID 48317 // |
| 12963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 12964 | // (and:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 12965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 12966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 12970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 12971 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 12973 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 12974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 12975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 12976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 12977 | GIR_RootConstrainSelectedInstOperands, |
| 12978 | // GIR_Coverage, 48317, |
| 12979 | GIR_EraseRootFromParent_Done, |
| 12980 | // Label 988: @31244 |
| 12981 | GIM_Reject, |
| 12982 | // Label 986: @31245 |
| 12983 | GIM_Reject, |
| 12984 | // Label 887: @31246 |
| 12985 | GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(31856), |
| 12986 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 12987 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 12988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12989 | GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(31327), // Rule ID 71296 // |
| 12990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 12991 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12992 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 12993 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 12994 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 12995 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12996 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 12997 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 12998 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 12999 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13000 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13001 | // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs2), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13004 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13008 | GIR_RootConstrainSelectedInstOperands, |
| 13009 | // GIR_Coverage, 71296, |
| 13010 | GIR_EraseRootFromParent_Done, |
| 13011 | // Label 990: @31327 |
| 13012 | GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(31393), // Rule ID 71297 // |
| 13013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13014 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13015 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13016 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13017 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13018 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13019 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13020 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13021 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13022 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13023 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13024 | // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs2), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13027 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13028 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13031 | GIR_RootConstrainSelectedInstOperands, |
| 13032 | // GIR_Coverage, 71297, |
| 13033 | GIR_EraseRootFromParent_Done, |
| 13034 | // Label 991: @31393 |
| 13035 | GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(31459), // Rule ID 71294 // |
| 13036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13037 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13038 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13039 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13040 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13041 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13042 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13043 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13044 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13045 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13046 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13047 | // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13050 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13054 | GIR_RootConstrainSelectedInstOperands, |
| 13055 | // GIR_Coverage, 71294, |
| 13056 | GIR_EraseRootFromParent_Done, |
| 13057 | // Label 992: @31459 |
| 13058 | GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(31525), // Rule ID 71295 // |
| 13059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13060 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13061 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13062 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13063 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13064 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13065 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13066 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13067 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13068 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13069 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13070 | // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13073 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13077 | GIR_RootConstrainSelectedInstOperands, |
| 13078 | // GIR_Coverage, 71295, |
| 13079 | GIR_EraseRootFromParent_Done, |
| 13080 | // Label 993: @31525 |
| 13081 | GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(31591), // Rule ID 71292 // |
| 13082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13084 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13085 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13086 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13087 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13088 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13089 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13090 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13091 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13092 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13093 | // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13096 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13097 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13100 | GIR_RootConstrainSelectedInstOperands, |
| 13101 | // GIR_Coverage, 71292, |
| 13102 | GIR_EraseRootFromParent_Done, |
| 13103 | // Label 994: @31591 |
| 13104 | GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(31657), // Rule ID 71293 // |
| 13105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13107 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13108 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13109 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13110 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13111 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13112 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13113 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13114 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13115 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13116 | // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13119 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13123 | GIR_RootConstrainSelectedInstOperands, |
| 13124 | // GIR_Coverage, 71293, |
| 13125 | GIR_EraseRootFromParent_Done, |
| 13126 | // Label 995: @31657 |
| 13127 | GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(31723), // Rule ID 53814 // |
| 13128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13129 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13130 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13131 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13132 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13133 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13134 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13135 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13136 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13137 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13138 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13139 | // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13142 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13146 | GIR_RootConstrainSelectedInstOperands, |
| 13147 | // GIR_Coverage, 53814, |
| 13148 | GIR_EraseRootFromParent_Done, |
| 13149 | // Label 996: @31723 |
| 13150 | GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(31789), // Rule ID 53815 // |
| 13151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13152 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13153 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13154 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13155 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 13156 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 13157 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13158 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13159 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13160 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13161 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13162 | // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), |
| 13164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13165 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13166 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13169 | GIR_RootConstrainSelectedInstOperands, |
| 13170 | // GIR_Coverage, 53815, |
| 13171 | GIR_EraseRootFromParent_Done, |
| 13172 | // Label 997: @31789 |
| 13173 | GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(31822), // Rule ID 53802 // |
| 13174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13175 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13176 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13177 | // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF4), |
| 13179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13180 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13181 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13184 | GIR_RootConstrainSelectedInstOperands, |
| 13185 | // GIR_Coverage, 53802, |
| 13186 | GIR_EraseRootFromParent_Done, |
| 13187 | // Label 998: @31822 |
| 13188 | GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(31855), // Rule ID 53803 // |
| 13189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13190 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13191 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13192 | // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF4), |
| 13194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13196 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13199 | GIR_RootConstrainSelectedInstOperands, |
| 13200 | // GIR_Coverage, 53803, |
| 13201 | GIR_EraseRootFromParent_Done, |
| 13202 | // Label 999: @31855 |
| 13203 | GIM_Reject, |
| 13204 | // Label 989: @31856 |
| 13205 | GIM_Reject, |
| 13206 | // Label 888: @31857 |
| 13207 | GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(31971), |
| 13208 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 13209 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 13210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13211 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13212 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13213 | GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(31925), // Rule ID 48284 // |
| 13214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13215 | // (and:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 13216 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 13217 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13218 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), |
| 13221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13222 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13223 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13224 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13228 | GIR_RootConstrainSelectedInstOperands, |
| 13229 | // GIR_Coverage, 48284, |
| 13230 | GIR_EraseRootFromParent_Done, |
| 13231 | // Label 1001: @31925 |
| 13232 | GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(31970), // Rule ID 48285 // |
| 13233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13234 | // (and:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 13235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 13236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), |
| 13240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13242 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13243 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13247 | GIR_RootConstrainSelectedInstOperands, |
| 13248 | // GIR_Coverage, 48285, |
| 13249 | GIR_EraseRootFromParent_Done, |
| 13250 | // Label 1002: @31970 |
| 13251 | GIM_Reject, |
| 13252 | // Label 1000: @31971 |
| 13253 | GIM_Reject, |
| 13254 | // Label 889: @31972 |
| 13255 | GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(32086), |
| 13256 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 13257 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 13258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13261 | GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(32040), // Rule ID 48296 // |
| 13262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13263 | // (and:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 13264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 13265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), |
| 13269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13270 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13272 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 13275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13276 | GIR_RootConstrainSelectedInstOperands, |
| 13277 | // GIR_Coverage, 48296, |
| 13278 | GIR_EraseRootFromParent_Done, |
| 13279 | // Label 1004: @32040 |
| 13280 | GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(32085), // Rule ID 48297 // |
| 13281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13282 | // (and:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 13283 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 13284 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13285 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), |
| 13288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13289 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13290 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13291 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 13294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13295 | GIR_RootConstrainSelectedInstOperands, |
| 13296 | // GIR_Coverage, 48297, |
| 13297 | GIR_EraseRootFromParent_Done, |
| 13298 | // Label 1005: @32085 |
| 13299 | GIM_Reject, |
| 13300 | // Label 1003: @32086 |
| 13301 | GIM_Reject, |
| 13302 | // Label 890: @32087 |
| 13303 | GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(32201), |
| 13304 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 13305 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 13306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13307 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13308 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13309 | GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(32155), // Rule ID 48312 // |
| 13310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13311 | // (and:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 13312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 13313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13314 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13315 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 13317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13318 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13319 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13320 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 13323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13324 | GIR_RootConstrainSelectedInstOperands, |
| 13325 | // GIR_Coverage, 48312, |
| 13326 | GIR_EraseRootFromParent_Done, |
| 13327 | // Label 1007: @32155 |
| 13328 | GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(32200), // Rule ID 48313 // |
| 13329 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13330 | // (and:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 13331 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 13332 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13333 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13334 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 13336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13338 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13339 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 13342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13343 | GIR_RootConstrainSelectedInstOperands, |
| 13344 | // GIR_Coverage, 48313, |
| 13345 | GIR_EraseRootFromParent_Done, |
| 13346 | // Label 1008: @32200 |
| 13347 | GIM_Reject, |
| 13348 | // Label 1006: @32201 |
| 13349 | GIM_Reject, |
| 13350 | // Label 891: @32202 |
| 13351 | GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(32316), |
| 13352 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 13353 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 13354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 13355 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 13356 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 13357 | GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(32270), // Rule ID 48356 // |
| 13358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 13359 | // (and:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 13360 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 13361 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13362 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13363 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 13365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13366 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13367 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13368 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 13371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13372 | GIR_RootConstrainSelectedInstOperands, |
| 13373 | // GIR_Coverage, 48356, |
| 13374 | GIR_EraseRootFromParent_Done, |
| 13375 | // Label 1010: @32270 |
| 13376 | GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(32315), // Rule ID 48357 // |
| 13377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 13378 | // (and:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 13379 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 13380 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13381 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 13384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13385 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13386 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13387 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 13390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13391 | GIR_RootConstrainSelectedInstOperands, |
| 13392 | // GIR_Coverage, 48357, |
| 13393 | GIR_EraseRootFromParent_Done, |
| 13394 | // Label 1011: @32315 |
| 13395 | GIM_Reject, |
| 13396 | // Label 1009: @32316 |
| 13397 | GIM_Reject, |
| 13398 | // Label 892: @32317 |
| 13399 | GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(32927), |
| 13400 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13401 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13403 | GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(32398), // Rule ID 71324 // |
| 13404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13405 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13406 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13407 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13408 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13409 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13410 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13411 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13412 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13414 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13415 | // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs2), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13418 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13422 | GIR_RootConstrainSelectedInstOperands, |
| 13423 | // GIR_Coverage, 71324, |
| 13424 | GIR_EraseRootFromParent_Done, |
| 13425 | // Label 1013: @32398 |
| 13426 | GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(32464), // Rule ID 71325 // |
| 13427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13428 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13429 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13430 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13431 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13432 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13433 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13434 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13435 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13436 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13437 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13438 | // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs2), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13441 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13445 | GIR_RootConstrainSelectedInstOperands, |
| 13446 | // GIR_Coverage, 71325, |
| 13447 | GIR_EraseRootFromParent_Done, |
| 13448 | // Label 1014: @32464 |
| 13449 | GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(32530), // Rule ID 71322 // |
| 13450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13452 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13454 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13455 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13456 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13457 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13458 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13459 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13460 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13461 | // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13464 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13468 | GIR_RootConstrainSelectedInstOperands, |
| 13469 | // GIR_Coverage, 71322, |
| 13470 | GIR_EraseRootFromParent_Done, |
| 13471 | // Label 1015: @32530 |
| 13472 | GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(32596), // Rule ID 71323 // |
| 13473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13474 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13475 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13476 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13477 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13478 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13479 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13480 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13481 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13482 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13483 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13484 | // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13487 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13491 | GIR_RootConstrainSelectedInstOperands, |
| 13492 | // GIR_Coverage, 71323, |
| 13493 | GIR_EraseRootFromParent_Done, |
| 13494 | // Label 1016: @32596 |
| 13495 | GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(32662), // Rule ID 71320 // |
| 13496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13497 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13498 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13499 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13500 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13501 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13502 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13503 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13504 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13505 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13506 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13507 | // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13510 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13514 | GIR_RootConstrainSelectedInstOperands, |
| 13515 | // GIR_Coverage, 71320, |
| 13516 | GIR_EraseRootFromParent_Done, |
| 13517 | // Label 1017: @32662 |
| 13518 | GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(32728), // Rule ID 71321 // |
| 13519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13520 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13521 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13522 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13523 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13524 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13525 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13526 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13527 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13528 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13529 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13530 | // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13533 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13534 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13537 | GIR_RootConstrainSelectedInstOperands, |
| 13538 | // GIR_Coverage, 71321, |
| 13539 | GIR_EraseRootFromParent_Done, |
| 13540 | // Label 1018: @32728 |
| 13541 | GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(32794), // Rule ID 53832 // |
| 13542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13543 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13544 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13545 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13546 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13547 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13548 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13549 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13550 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13551 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13552 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13553 | // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13556 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13560 | GIR_RootConstrainSelectedInstOperands, |
| 13561 | // GIR_Coverage, 53832, |
| 13562 | GIR_EraseRootFromParent_Done, |
| 13563 | // Label 1019: @32794 |
| 13564 | GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(32860), // Rule ID 53833 // |
| 13565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13566 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13568 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13569 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 13570 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 13571 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13572 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13573 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13574 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13575 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13576 | // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), |
| 13578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13579 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13583 | GIR_RootConstrainSelectedInstOperands, |
| 13584 | // GIR_Coverage, 53833, |
| 13585 | GIR_EraseRootFromParent_Done, |
| 13586 | // Label 1020: @32860 |
| 13587 | GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(32893), // Rule ID 53820 // |
| 13588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13590 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13591 | // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF2), |
| 13593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13594 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13595 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13598 | GIR_RootConstrainSelectedInstOperands, |
| 13599 | // GIR_Coverage, 53820, |
| 13600 | GIR_EraseRootFromParent_Done, |
| 13601 | // Label 1021: @32893 |
| 13602 | GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(32926), // Rule ID 53821 // |
| 13603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13604 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13606 | // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF2), |
| 13608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13609 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13610 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13613 | GIR_RootConstrainSelectedInstOperands, |
| 13614 | // GIR_Coverage, 53821, |
| 13615 | GIR_EraseRootFromParent_Done, |
| 13616 | // Label 1022: @32926 |
| 13617 | GIM_Reject, |
| 13618 | // Label 1012: @32927 |
| 13619 | GIM_Reject, |
| 13620 | // Label 893: @32928 |
| 13621 | GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(33042), |
| 13622 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 13623 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 13624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13626 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13627 | GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(32996), // Rule ID 48288 // |
| 13628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13629 | // (and:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 13630 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 13631 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13632 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), |
| 13635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13642 | GIR_RootConstrainSelectedInstOperands, |
| 13643 | // GIR_Coverage, 48288, |
| 13644 | GIR_EraseRootFromParent_Done, |
| 13645 | // Label 1024: @32996 |
| 13646 | GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(33041), // Rule ID 48289 // |
| 13647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13648 | // (and:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 13649 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 13650 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13651 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13652 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), |
| 13654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13655 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13656 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13657 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13661 | GIR_RootConstrainSelectedInstOperands, |
| 13662 | // GIR_Coverage, 48289, |
| 13663 | GIR_EraseRootFromParent_Done, |
| 13664 | // Label 1025: @33041 |
| 13665 | GIM_Reject, |
| 13666 | // Label 1023: @33042 |
| 13667 | GIM_Reject, |
| 13668 | // Label 894: @33043 |
| 13669 | GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(33157), |
| 13670 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 13671 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 13672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13673 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13674 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13675 | GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(33111), // Rule ID 48308 // |
| 13676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13677 | // (and:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 13678 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 13679 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13680 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13681 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 13683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13684 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13685 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 13689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13690 | GIR_RootConstrainSelectedInstOperands, |
| 13691 | // GIR_Coverage, 48308, |
| 13692 | GIR_EraseRootFromParent_Done, |
| 13693 | // Label 1027: @33111 |
| 13694 | GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(33156), // Rule ID 48309 // |
| 13695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13696 | // (and:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 13697 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 13698 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13699 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 13702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13703 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13704 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13705 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 13708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13709 | GIR_RootConstrainSelectedInstOperands, |
| 13710 | // GIR_Coverage, 48309, |
| 13711 | GIR_EraseRootFromParent_Done, |
| 13712 | // Label 1028: @33156 |
| 13713 | GIM_Reject, |
| 13714 | // Label 1026: @33157 |
| 13715 | GIM_Reject, |
| 13716 | // Label 895: @33158 |
| 13717 | GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(33272), |
| 13718 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 13719 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 13720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 13721 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 13722 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 13723 | GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(33226), // Rule ID 48344 // |
| 13724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13725 | // (and:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 13726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 13727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 13731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13732 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13733 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13734 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 13737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13738 | GIR_RootConstrainSelectedInstOperands, |
| 13739 | // GIR_Coverage, 48344, |
| 13740 | GIR_EraseRootFromParent_Done, |
| 13741 | // Label 1030: @33226 |
| 13742 | GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(33271), // Rule ID 48345 // |
| 13743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13744 | // (and:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 13745 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 13746 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13747 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13748 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 13750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13751 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13752 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13753 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 13756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13757 | GIR_RootConstrainSelectedInstOperands, |
| 13758 | // GIR_Coverage, 48345, |
| 13759 | GIR_EraseRootFromParent_Done, |
| 13760 | // Label 1031: @33271 |
| 13761 | GIM_Reject, |
| 13762 | // Label 1029: @33272 |
| 13763 | GIM_Reject, |
| 13764 | // Label 896: @33273 |
| 13765 | GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(33387), |
| 13766 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 13767 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 13768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 13769 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 13770 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 13771 | GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(33341), // Rule ID 48360 // |
| 13772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 13773 | // (and:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 13774 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 13775 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13776 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 13779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13780 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13781 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13782 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 13785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13786 | GIR_RootConstrainSelectedInstOperands, |
| 13787 | // GIR_Coverage, 48360, |
| 13788 | GIR_EraseRootFromParent_Done, |
| 13789 | // Label 1033: @33341 |
| 13790 | GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(33386), // Rule ID 48361 // |
| 13791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 13792 | // (and:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 13793 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 13794 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13795 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13796 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 13798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13799 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13800 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13801 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 13802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 13804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 13805 | GIR_RootConstrainSelectedInstOperands, |
| 13806 | // GIR_Coverage, 48361, |
| 13807 | GIR_EraseRootFromParent_Done, |
| 13808 | // Label 1034: @33386 |
| 13809 | GIM_Reject, |
| 13810 | // Label 1032: @33387 |
| 13811 | GIM_Reject, |
| 13812 | // Label 897: @33388 |
| 13813 | GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(33998), |
| 13814 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13815 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13817 | GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(33469), // Rule ID 71352 // |
| 13818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13819 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13820 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13821 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13822 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13823 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13824 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13825 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13826 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13828 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13829 | // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs2), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13832 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13836 | GIR_RootConstrainSelectedInstOperands, |
| 13837 | // GIR_Coverage, 71352, |
| 13838 | GIR_EraseRootFromParent_Done, |
| 13839 | // Label 1036: @33469 |
| 13840 | GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(33535), // Rule ID 71353 // |
| 13841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13842 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13843 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13844 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13845 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13846 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13847 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13848 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13849 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13850 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13851 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13852 | // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs2), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13855 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13859 | GIR_RootConstrainSelectedInstOperands, |
| 13860 | // GIR_Coverage, 71353, |
| 13861 | GIR_EraseRootFromParent_Done, |
| 13862 | // Label 1037: @33535 |
| 13863 | GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(33601), // Rule ID 71350 // |
| 13864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13865 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13866 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13867 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13868 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13869 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13870 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13871 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13872 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13874 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13875 | // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13878 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13882 | GIR_RootConstrainSelectedInstOperands, |
| 13883 | // GIR_Coverage, 71350, |
| 13884 | GIR_EraseRootFromParent_Done, |
| 13885 | // Label 1038: @33601 |
| 13886 | GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(33667), // Rule ID 71351 // |
| 13887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13888 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13889 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13891 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13892 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13893 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13894 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13895 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13896 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13897 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13898 | // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13901 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 13902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13905 | GIR_RootConstrainSelectedInstOperands, |
| 13906 | // GIR_Coverage, 71351, |
| 13907 | GIR_EraseRootFromParent_Done, |
| 13908 | // Label 1039: @33667 |
| 13909 | GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(33733), // Rule ID 71348 // |
| 13910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13911 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13912 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13913 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13914 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13915 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13916 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13917 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13918 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13919 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13920 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13921 | // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13924 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13928 | GIR_RootConstrainSelectedInstOperands, |
| 13929 | // GIR_Coverage, 71348, |
| 13930 | GIR_EraseRootFromParent_Done, |
| 13931 | // Label 1040: @33733 |
| 13932 | GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(33799), // Rule ID 71349 // |
| 13933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13934 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13935 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13936 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13937 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13938 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13939 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13940 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13941 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13942 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13943 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13944 | // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13947 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 13949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13951 | GIR_RootConstrainSelectedInstOperands, |
| 13952 | // GIR_Coverage, 71349, |
| 13953 | GIR_EraseRootFromParent_Done, |
| 13954 | // Label 1041: @33799 |
| 13955 | GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(33865), // Rule ID 53850 // |
| 13956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 13957 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13959 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13960 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13961 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13962 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13963 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13964 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13965 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 13966 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13967 | // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 13968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13970 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13974 | GIR_RootConstrainSelectedInstOperands, |
| 13975 | // GIR_Coverage, 53850, |
| 13976 | GIR_EraseRootFromParent_Done, |
| 13977 | // Label 1042: @33865 |
| 13978 | GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(33931), // Rule ID 53851 // |
| 13979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 13980 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13981 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13982 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 13983 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 13984 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 13985 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 13986 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13987 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 13988 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13989 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 13990 | // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 13991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), |
| 13992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 13993 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 13994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 13995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 13996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13997 | GIR_RootConstrainSelectedInstOperands, |
| 13998 | // GIR_Coverage, 53851, |
| 13999 | GIR_EraseRootFromParent_Done, |
| 14000 | // Label 1043: @33931 |
| 14001 | GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(33964), // Rule ID 53838 // |
| 14002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14004 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14005 | // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M1), |
| 14007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14008 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14009 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14012 | GIR_RootConstrainSelectedInstOperands, |
| 14013 | // GIR_Coverage, 53838, |
| 14014 | GIR_EraseRootFromParent_Done, |
| 14015 | // Label 1044: @33964 |
| 14016 | GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(33997), // Rule ID 53839 // |
| 14017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14020 | // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M1), |
| 14022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14023 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14024 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14027 | GIR_RootConstrainSelectedInstOperands, |
| 14028 | // GIR_Coverage, 53839, |
| 14029 | GIR_EraseRootFromParent_Done, |
| 14030 | // Label 1045: @33997 |
| 14031 | GIM_Reject, |
| 14032 | // Label 1035: @33998 |
| 14033 | GIM_Reject, |
| 14034 | // Label 898: @33999 |
| 14035 | GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(34113), |
| 14036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 14037 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 14038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14040 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14041 | GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(34067), // Rule ID 48304 // |
| 14042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14043 | // (and:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 14044 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 14045 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14046 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 14049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14050 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14051 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14052 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14056 | GIR_RootConstrainSelectedInstOperands, |
| 14057 | // GIR_Coverage, 48304, |
| 14058 | GIR_EraseRootFromParent_Done, |
| 14059 | // Label 1047: @34067 |
| 14060 | GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(34112), // Rule ID 48305 // |
| 14061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14062 | // (and:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 14063 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 14064 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14065 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14066 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), |
| 14068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14069 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14070 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14071 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14075 | GIR_RootConstrainSelectedInstOperands, |
| 14076 | // GIR_Coverage, 48305, |
| 14077 | GIR_EraseRootFromParent_Done, |
| 14078 | // Label 1048: @34112 |
| 14079 | GIM_Reject, |
| 14080 | // Label 1046: @34113 |
| 14081 | GIM_Reject, |
| 14082 | // Label 899: @34114 |
| 14083 | GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(34228), |
| 14084 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 14085 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 14086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 14087 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 14088 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 14089 | GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(34182), // Rule ID 48332 // |
| 14090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14091 | // (and:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 14092 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 14093 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14094 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14095 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 14097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14098 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14099 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14100 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 14103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14104 | GIR_RootConstrainSelectedInstOperands, |
| 14105 | // GIR_Coverage, 48332, |
| 14106 | GIR_EraseRootFromParent_Done, |
| 14107 | // Label 1050: @34182 |
| 14108 | GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(34227), // Rule ID 48333 // |
| 14109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14110 | // (and:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 14111 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 14112 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14113 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 14116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14117 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14118 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14119 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 14122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14123 | GIR_RootConstrainSelectedInstOperands, |
| 14124 | // GIR_Coverage, 48333, |
| 14125 | GIR_EraseRootFromParent_Done, |
| 14126 | // Label 1051: @34227 |
| 14127 | GIM_Reject, |
| 14128 | // Label 1049: @34228 |
| 14129 | GIM_Reject, |
| 14130 | // Label 900: @34229 |
| 14131 | GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(34343), |
| 14132 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 14133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 14134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14136 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14137 | GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(34297), // Rule ID 48348 // |
| 14138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14139 | // (and:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 14140 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 14141 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14142 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 14145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14146 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14147 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14148 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 14151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14152 | GIR_RootConstrainSelectedInstOperands, |
| 14153 | // GIR_Coverage, 48348, |
| 14154 | GIR_EraseRootFromParent_Done, |
| 14155 | // Label 1053: @34297 |
| 14156 | GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(34342), // Rule ID 48349 // |
| 14157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14158 | // (and:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 14159 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 14160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 14164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14166 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14167 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 14170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14171 | GIR_RootConstrainSelectedInstOperands, |
| 14172 | // GIR_Coverage, 48349, |
| 14173 | GIR_EraseRootFromParent_Done, |
| 14174 | // Label 1054: @34342 |
| 14175 | GIM_Reject, |
| 14176 | // Label 1052: @34343 |
| 14177 | GIM_Reject, |
| 14178 | // Label 901: @34344 |
| 14179 | GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(34458), |
| 14180 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 14181 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 14182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14183 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14184 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14185 | GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(34412), // Rule ID 48364 // |
| 14186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 14187 | // (and:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 14188 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 14189 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14190 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 14193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14194 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14196 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 14199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14200 | GIR_RootConstrainSelectedInstOperands, |
| 14201 | // GIR_Coverage, 48364, |
| 14202 | GIR_EraseRootFromParent_Done, |
| 14203 | // Label 1056: @34412 |
| 14204 | GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(34457), // Rule ID 48365 // |
| 14205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 14206 | // (and:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 14207 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 14208 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14209 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 14212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14213 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14214 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14215 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 14218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14219 | GIR_RootConstrainSelectedInstOperands, |
| 14220 | // GIR_Coverage, 48365, |
| 14221 | GIR_EraseRootFromParent_Done, |
| 14222 | // Label 1057: @34457 |
| 14223 | GIM_Reject, |
| 14224 | // Label 1055: @34458 |
| 14225 | GIM_Reject, |
| 14226 | // Label 902: @34459 |
| 14227 | GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(35069), |
| 14228 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14229 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14230 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14231 | GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(34540), // Rule ID 71380 // |
| 14232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14233 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14234 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14235 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14236 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14237 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14238 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14239 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14240 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14241 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14242 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14243 | // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs2), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14246 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14250 | GIR_RootConstrainSelectedInstOperands, |
| 14251 | // GIR_Coverage, 71380, |
| 14252 | GIR_EraseRootFromParent_Done, |
| 14253 | // Label 1059: @34540 |
| 14254 | GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(34606), // Rule ID 71381 // |
| 14255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14256 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14257 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14258 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14259 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14260 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14261 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14262 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14263 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14265 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14266 | // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs2), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14269 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14273 | GIR_RootConstrainSelectedInstOperands, |
| 14274 | // GIR_Coverage, 71381, |
| 14275 | GIR_EraseRootFromParent_Done, |
| 14276 | // Label 1060: @34606 |
| 14277 | GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(34672), // Rule ID 71378 // |
| 14278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14279 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14280 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14281 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14282 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14283 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14284 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14285 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14286 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14288 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14289 | // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14292 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14296 | GIR_RootConstrainSelectedInstOperands, |
| 14297 | // GIR_Coverage, 71378, |
| 14298 | GIR_EraseRootFromParent_Done, |
| 14299 | // Label 1061: @34672 |
| 14300 | GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(34738), // Rule ID 71379 // |
| 14301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14302 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14303 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14304 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14305 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14306 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14307 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14308 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14309 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14311 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14312 | // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14315 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14319 | GIR_RootConstrainSelectedInstOperands, |
| 14320 | // GIR_Coverage, 71379, |
| 14321 | GIR_EraseRootFromParent_Done, |
| 14322 | // Label 1062: @34738 |
| 14323 | GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(34804), // Rule ID 71376 // |
| 14324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14326 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14327 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14328 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14329 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14330 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14331 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14332 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14333 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14334 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14335 | // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14338 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14342 | GIR_RootConstrainSelectedInstOperands, |
| 14343 | // GIR_Coverage, 71376, |
| 14344 | GIR_EraseRootFromParent_Done, |
| 14345 | // Label 1063: @34804 |
| 14346 | GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(34870), // Rule ID 71377 // |
| 14347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14348 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14353 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14354 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14355 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14356 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14357 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14358 | // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14361 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14362 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14365 | GIR_RootConstrainSelectedInstOperands, |
| 14366 | // GIR_Coverage, 71377, |
| 14367 | GIR_EraseRootFromParent_Done, |
| 14368 | // Label 1064: @34870 |
| 14369 | GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(34936), // Rule ID 53868 // |
| 14370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14371 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14372 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14373 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14374 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14375 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14376 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14377 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14378 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14379 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14380 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14381 | // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14384 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14388 | GIR_RootConstrainSelectedInstOperands, |
| 14389 | // GIR_Coverage, 53868, |
| 14390 | GIR_EraseRootFromParent_Done, |
| 14391 | // Label 1065: @34936 |
| 14392 | GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(35002), // Rule ID 53869 // |
| 14393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14394 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14395 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14396 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14397 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 14398 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 14399 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14400 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14401 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14402 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14403 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14404 | // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M2), |
| 14406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14407 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14411 | GIR_RootConstrainSelectedInstOperands, |
| 14412 | // GIR_Coverage, 53869, |
| 14413 | GIR_EraseRootFromParent_Done, |
| 14414 | // Label 1066: @35002 |
| 14415 | GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(35035), // Rule ID 53856 // |
| 14416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14417 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14418 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14419 | // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M2), |
| 14421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14422 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14423 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14426 | GIR_RootConstrainSelectedInstOperands, |
| 14427 | // GIR_Coverage, 53856, |
| 14428 | GIR_EraseRootFromParent_Done, |
| 14429 | // Label 1067: @35035 |
| 14430 | GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(35068), // Rule ID 53857 // |
| 14431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14432 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14434 | // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M2), |
| 14436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14437 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14438 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14441 | GIR_RootConstrainSelectedInstOperands, |
| 14442 | // GIR_Coverage, 53857, |
| 14443 | GIR_EraseRootFromParent_Done, |
| 14444 | // Label 1068: @35068 |
| 14445 | GIM_Reject, |
| 14446 | // Label 1058: @35069 |
| 14447 | GIM_Reject, |
| 14448 | // Label 903: @35070 |
| 14449 | GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(35184), |
| 14450 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 14451 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 14452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 14453 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 14454 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 14455 | GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(35138), // Rule ID 48320 // |
| 14456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14457 | // (and:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 14458 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 14459 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14460 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 14463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14464 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14465 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14470 | GIR_RootConstrainSelectedInstOperands, |
| 14471 | // GIR_Coverage, 48320, |
| 14472 | GIR_EraseRootFromParent_Done, |
| 14473 | // Label 1070: @35138 |
| 14474 | GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(35183), // Rule ID 48321 // |
| 14475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14476 | // (and:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 14477 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 14478 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14479 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), |
| 14482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14483 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14484 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14485 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14489 | GIR_RootConstrainSelectedInstOperands, |
| 14490 | // GIR_Coverage, 48321, |
| 14491 | GIR_EraseRootFromParent_Done, |
| 14492 | // Label 1071: @35183 |
| 14493 | GIM_Reject, |
| 14494 | // Label 1069: @35184 |
| 14495 | GIM_Reject, |
| 14496 | // Label 904: @35185 |
| 14497 | GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(35299), |
| 14498 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 14499 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 14500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14501 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14502 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14503 | GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(35253), // Rule ID 48336 // |
| 14504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14505 | // (and:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 14506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 14507 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 14511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14513 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 14517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14518 | GIR_RootConstrainSelectedInstOperands, |
| 14519 | // GIR_Coverage, 48336, |
| 14520 | GIR_EraseRootFromParent_Done, |
| 14521 | // Label 1073: @35253 |
| 14522 | GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(35298), // Rule ID 48337 // |
| 14523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14524 | // (and:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 14525 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 14526 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14527 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 14530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14531 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14532 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14533 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 14536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14537 | GIR_RootConstrainSelectedInstOperands, |
| 14538 | // GIR_Coverage, 48337, |
| 14539 | GIR_EraseRootFromParent_Done, |
| 14540 | // Label 1074: @35298 |
| 14541 | GIM_Reject, |
| 14542 | // Label 1072: @35299 |
| 14543 | GIM_Reject, |
| 14544 | // Label 905: @35300 |
| 14545 | GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(35414), |
| 14546 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 14547 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 14548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14549 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14550 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14551 | GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(35368), // Rule ID 48352 // |
| 14552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14553 | // (and:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 14554 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 14555 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14556 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14557 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 14559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14560 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14561 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14562 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 14565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14566 | GIR_RootConstrainSelectedInstOperands, |
| 14567 | // GIR_Coverage, 48352, |
| 14568 | GIR_EraseRootFromParent_Done, |
| 14569 | // Label 1076: @35368 |
| 14570 | GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(35413), // Rule ID 48353 // |
| 14571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14572 | // (and:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 14573 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 14574 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14575 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 14578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14579 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14580 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14581 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 14584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14585 | GIR_RootConstrainSelectedInstOperands, |
| 14586 | // GIR_Coverage, 48353, |
| 14587 | GIR_EraseRootFromParent_Done, |
| 14588 | // Label 1077: @35413 |
| 14589 | GIM_Reject, |
| 14590 | // Label 1075: @35414 |
| 14591 | GIM_Reject, |
| 14592 | // Label 906: @35415 |
| 14593 | GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(36025), |
| 14594 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14595 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14597 | GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(35496), // Rule ID 71408 // |
| 14598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14599 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14600 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14601 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14602 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14603 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14604 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14605 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14606 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14608 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14609 | // (and:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs2), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14612 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14616 | GIR_RootConstrainSelectedInstOperands, |
| 14617 | // GIR_Coverage, 71408, |
| 14618 | GIR_EraseRootFromParent_Done, |
| 14619 | // Label 1079: @35496 |
| 14620 | GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(35562), // Rule ID 71409 // |
| 14621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14622 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14623 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14624 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14625 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14626 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14627 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14628 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14629 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14630 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14631 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14632 | // (and:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs2), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14635 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14639 | GIR_RootConstrainSelectedInstOperands, |
| 14640 | // GIR_Coverage, 71409, |
| 14641 | GIR_EraseRootFromParent_Done, |
| 14642 | // Label 1080: @35562 |
| 14643 | GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(35628), // Rule ID 71406 // |
| 14644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14645 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14646 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14647 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14648 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14649 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14650 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14651 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14652 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14653 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14654 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14655 | // (and:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14658 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14662 | GIR_RootConstrainSelectedInstOperands, |
| 14663 | // GIR_Coverage, 71406, |
| 14664 | GIR_EraseRootFromParent_Done, |
| 14665 | // Label 1081: @35628 |
| 14666 | GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(35694), // Rule ID 71407 // |
| 14667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14668 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14669 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14670 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14671 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14672 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14673 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14674 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14675 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14676 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14677 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14678 | // (and:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14681 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14685 | GIR_RootConstrainSelectedInstOperands, |
| 14686 | // GIR_Coverage, 71407, |
| 14687 | GIR_EraseRootFromParent_Done, |
| 14688 | // Label 1082: @35694 |
| 14689 | GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(35760), // Rule ID 71404 // |
| 14690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14691 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14692 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14693 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14694 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14695 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14696 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14697 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14698 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14699 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14700 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14701 | // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14704 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14708 | GIR_RootConstrainSelectedInstOperands, |
| 14709 | // GIR_Coverage, 71404, |
| 14710 | GIR_EraseRootFromParent_Done, |
| 14711 | // Label 1083: @35760 |
| 14712 | GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(35826), // Rule ID 71405 // |
| 14713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14715 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14716 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14717 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14718 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14719 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14720 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14721 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14722 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14723 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14724 | // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14727 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14731 | GIR_RootConstrainSelectedInstOperands, |
| 14732 | // GIR_Coverage, 71405, |
| 14733 | GIR_EraseRootFromParent_Done, |
| 14734 | // Label 1084: @35826 |
| 14735 | GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(35892), // Rule ID 53886 // |
| 14736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14737 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14738 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14739 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14740 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14741 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14742 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14743 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14744 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14745 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14746 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14747 | // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14750 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14754 | GIR_RootConstrainSelectedInstOperands, |
| 14755 | // GIR_Coverage, 53886, |
| 14756 | GIR_EraseRootFromParent_Done, |
| 14757 | // Label 1085: @35892 |
| 14758 | GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(35958), // Rule ID 53887 // |
| 14759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14760 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14761 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14762 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14763 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 14764 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 14765 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14766 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14767 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14768 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14769 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14770 | // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M4), |
| 14772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14773 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14777 | GIR_RootConstrainSelectedInstOperands, |
| 14778 | // GIR_Coverage, 53887, |
| 14779 | GIR_EraseRootFromParent_Done, |
| 14780 | // Label 1086: @35958 |
| 14781 | GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(35991), // Rule ID 53874 // |
| 14782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14784 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14785 | // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M4), |
| 14787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14788 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14789 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14792 | GIR_RootConstrainSelectedInstOperands, |
| 14793 | // GIR_Coverage, 53874, |
| 14794 | GIR_EraseRootFromParent_Done, |
| 14795 | // Label 1087: @35991 |
| 14796 | GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(36024), // Rule ID 53875 // |
| 14797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14800 | // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M4), |
| 14802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14803 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14804 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14807 | GIR_RootConstrainSelectedInstOperands, |
| 14808 | // GIR_Coverage, 53875, |
| 14809 | GIR_EraseRootFromParent_Done, |
| 14810 | // Label 1088: @36024 |
| 14811 | GIM_Reject, |
| 14812 | // Label 1078: @36025 |
| 14813 | GIM_Reject, |
| 14814 | // Label 907: @36026 |
| 14815 | GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(36140), |
| 14816 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 14817 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 14818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14820 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 14821 | GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(36094), // Rule ID 48324 // |
| 14822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14823 | // (and:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 14824 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 14825 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14826 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 14829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14830 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14831 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14832 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14836 | GIR_RootConstrainSelectedInstOperands, |
| 14837 | // GIR_Coverage, 48324, |
| 14838 | GIR_EraseRootFromParent_Done, |
| 14839 | // Label 1090: @36094 |
| 14840 | GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(36139), // Rule ID 48325 // |
| 14841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14842 | // (and:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 14843 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 14844 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14845 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), |
| 14848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14849 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14850 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14851 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14855 | GIR_RootConstrainSelectedInstOperands, |
| 14856 | // GIR_Coverage, 48325, |
| 14857 | GIR_EraseRootFromParent_Done, |
| 14858 | // Label 1091: @36139 |
| 14859 | GIM_Reject, |
| 14860 | // Label 1089: @36140 |
| 14861 | GIM_Reject, |
| 14862 | // Label 908: @36141 |
| 14863 | GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(36255), |
| 14864 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 14865 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 14866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14867 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14868 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 14869 | GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(36209), // Rule ID 48340 // |
| 14870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14871 | // (and:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 14872 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 14873 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14874 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 14877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14878 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14879 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14880 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 14883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14884 | GIR_RootConstrainSelectedInstOperands, |
| 14885 | // GIR_Coverage, 48340, |
| 14886 | GIR_EraseRootFromParent_Done, |
| 14887 | // Label 1093: @36209 |
| 14888 | GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(36254), // Rule ID 48341 // |
| 14889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14890 | // (and:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 14891 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 14892 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14893 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 14896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14897 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14898 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 14899 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 14900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 14902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 14903 | GIR_RootConstrainSelectedInstOperands, |
| 14904 | // GIR_Coverage, 48341, |
| 14905 | GIR_EraseRootFromParent_Done, |
| 14906 | // Label 1094: @36254 |
| 14907 | GIM_Reject, |
| 14908 | // Label 1092: @36255 |
| 14909 | GIM_Reject, |
| 14910 | // Label 909: @36256 |
| 14911 | GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(36866), |
| 14912 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 14913 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 14914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14915 | GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(36337), // Rule ID 71436 // |
| 14916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14917 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14918 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14919 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 14920 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 14921 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14922 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14923 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14924 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14926 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14927 | // (and:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs2), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 14929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14930 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14934 | GIR_RootConstrainSelectedInstOperands, |
| 14935 | // GIR_Coverage, 71436, |
| 14936 | GIR_EraseRootFromParent_Done, |
| 14937 | // Label 1096: @36337 |
| 14938 | GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(36403), // Rule ID 71437 // |
| 14939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14940 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14941 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14942 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 14943 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 14944 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14945 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14946 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14947 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14948 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14949 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14950 | // (and:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs2), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 14952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14953 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 14955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14957 | GIR_RootConstrainSelectedInstOperands, |
| 14958 | // GIR_Coverage, 71437, |
| 14959 | GIR_EraseRootFromParent_Done, |
| 14960 | // Label 1097: @36403 |
| 14961 | GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(36469), // Rule ID 71434 // |
| 14962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 14963 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14964 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14965 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 14966 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 14967 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14968 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14969 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14970 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 14971 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14972 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14973 | // (and:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 14974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 14975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14976 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 14977 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 14978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 14979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14980 | GIR_RootConstrainSelectedInstOperands, |
| 14981 | // GIR_Coverage, 71434, |
| 14982 | GIR_EraseRootFromParent_Done, |
| 14983 | // Label 1098: @36469 |
| 14984 | GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(36535), // Rule ID 71435 // |
| 14985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 14986 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14987 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 14988 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 14989 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 14990 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14991 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14992 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 14993 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14994 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 14995 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 14996 | // (and:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 14997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 14998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 14999 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15003 | GIR_RootConstrainSelectedInstOperands, |
| 15004 | // GIR_Coverage, 71435, |
| 15005 | GIR_EraseRootFromParent_Done, |
| 15006 | // Label 1099: @36535 |
| 15007 | GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(36601), // Rule ID 71432 // |
| 15008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15011 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15012 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 15013 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 15014 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15015 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15016 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 15017 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15018 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15019 | // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 15021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15022 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 15024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15026 | GIR_RootConstrainSelectedInstOperands, |
| 15027 | // GIR_Coverage, 71432, |
| 15028 | GIR_EraseRootFromParent_Done, |
| 15029 | // Label 1100: @36601 |
| 15030 | GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(36667), // Rule ID 71433 // |
| 15031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15032 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 15036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 15037 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15038 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15039 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15040 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15041 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15042 | // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 15044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15045 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 15047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15049 | GIR_RootConstrainSelectedInstOperands, |
| 15050 | // GIR_Coverage, 71433, |
| 15051 | GIR_EraseRootFromParent_Done, |
| 15052 | // Label 1101: @36667 |
| 15053 | GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(36733), // Rule ID 53904 // |
| 15054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15055 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15056 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15057 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15058 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 15059 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 15060 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15061 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15062 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15063 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 15064 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15065 | // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 15067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15072 | GIR_RootConstrainSelectedInstOperands, |
| 15073 | // GIR_Coverage, 53904, |
| 15074 | GIR_EraseRootFromParent_Done, |
| 15075 | // Label 1102: @36733 |
| 15076 | GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(36799), // Rule ID 53905 // |
| 15077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15078 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15079 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15080 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15081 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 15082 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 15083 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15084 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15085 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15086 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15087 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15088 | // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M8), |
| 15090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15091 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15095 | GIR_RootConstrainSelectedInstOperands, |
| 15096 | // GIR_Coverage, 53905, |
| 15097 | GIR_EraseRootFromParent_Done, |
| 15098 | // Label 1103: @36799 |
| 15099 | GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(36832), // Rule ID 53892 // |
| 15100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15101 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15102 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15103 | // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M8), |
| 15105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15106 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15107 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15110 | GIR_RootConstrainSelectedInstOperands, |
| 15111 | // GIR_Coverage, 53892, |
| 15112 | GIR_EraseRootFromParent_Done, |
| 15113 | // Label 1104: @36832 |
| 15114 | GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(36865), // Rule ID 53893 // |
| 15115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15117 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15118 | // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_M8), |
| 15120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15121 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15122 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15125 | GIR_RootConstrainSelectedInstOperands, |
| 15126 | // GIR_Coverage, 53893, |
| 15127 | GIR_EraseRootFromParent_Done, |
| 15128 | // Label 1105: @36865 |
| 15129 | GIM_Reject, |
| 15130 | // Label 1095: @36866 |
| 15131 | GIM_Reject, |
| 15132 | // Label 910: @36867 |
| 15133 | GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(36981), |
| 15134 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 15135 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 15136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 15137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 15138 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 15139 | GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(36935), // Rule ID 48328 // |
| 15140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15141 | // (and:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 15142 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 15143 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15144 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15145 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 15147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15148 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15149 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15150 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15154 | GIR_RootConstrainSelectedInstOperands, |
| 15155 | // GIR_Coverage, 48328, |
| 15156 | GIR_EraseRootFromParent_Done, |
| 15157 | // Label 1107: @36935 |
| 15158 | GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(36980), // Rule ID 48329 // |
| 15159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15160 | // (and:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVAND_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 15161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 15162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M8), |
| 15166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15167 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15169 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15173 | GIR_RootConstrainSelectedInstOperands, |
| 15174 | // GIR_Coverage, 48329, |
| 15175 | GIR_EraseRootFromParent_Done, |
| 15176 | // Label 1108: @36980 |
| 15177 | GIM_Reject, |
| 15178 | // Label 1106: @36981 |
| 15179 | GIM_Reject, |
| 15180 | // Label 911: @36982 |
| 15181 | GIM_Reject, |
| 15182 | // Label 8: @36983 |
| 15183 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 1140*/ GIMT_Encode4(44913), |
| 15184 | /*GILLT_s32*//*Label 1109*/ GIMT_Encode4(37118), |
| 15185 | /*GILLT_s64*//*Label 1110*/ GIMT_Encode4(37814), |
| 15186 | /*GILLT_nxv1s1*//*Label 1111*/ GIMT_Encode4(38106), |
| 15187 | /*GILLT_nxv1s8*//*Label 1112*/ GIMT_Encode4(38717), |
| 15188 | /*GILLT_nxv1s16*//*Label 1113*/ GIMT_Encode4(38832), |
| 15189 | /*GILLT_nxv1s32*//*Label 1114*/ GIMT_Encode4(38947), |
| 15190 | /*GILLT_nxv1s64*//*Label 1115*/ GIMT_Encode4(39062), |
| 15191 | /*GILLT_nxv2s1*//*Label 1116*/ GIMT_Encode4(39177), |
| 15192 | /*GILLT_nxv2s8*//*Label 1117*/ GIMT_Encode4(39788), |
| 15193 | /*GILLT_nxv2s16*//*Label 1118*/ GIMT_Encode4(39903), |
| 15194 | /*GILLT_nxv2s32*//*Label 1119*/ GIMT_Encode4(40018), |
| 15195 | /*GILLT_nxv2s64*//*Label 1120*/ GIMT_Encode4(40133), |
| 15196 | /*GILLT_nxv4s1*//*Label 1121*/ GIMT_Encode4(40248), |
| 15197 | /*GILLT_nxv4s8*//*Label 1122*/ GIMT_Encode4(40859), |
| 15198 | /*GILLT_nxv4s16*//*Label 1123*/ GIMT_Encode4(40974), |
| 15199 | /*GILLT_nxv4s32*//*Label 1124*/ GIMT_Encode4(41089), |
| 15200 | /*GILLT_nxv4s64*//*Label 1125*/ GIMT_Encode4(41204), |
| 15201 | /*GILLT_nxv8s1*//*Label 1126*/ GIMT_Encode4(41319), |
| 15202 | /*GILLT_nxv8s8*//*Label 1127*/ GIMT_Encode4(41930), |
| 15203 | /*GILLT_nxv8s16*//*Label 1128*/ GIMT_Encode4(42045), |
| 15204 | /*GILLT_nxv8s32*//*Label 1129*/ GIMT_Encode4(42160), |
| 15205 | /*GILLT_nxv8s64*//*Label 1130*/ GIMT_Encode4(42275), |
| 15206 | /*GILLT_nxv16s1*//*Label 1131*/ GIMT_Encode4(42390), |
| 15207 | /*GILLT_nxv16s8*//*Label 1132*/ GIMT_Encode4(43001), |
| 15208 | /*GILLT_nxv16s16*//*Label 1133*/ GIMT_Encode4(43116), |
| 15209 | /*GILLT_nxv16s32*//*Label 1134*/ GIMT_Encode4(43231), |
| 15210 | /*GILLT_nxv32s1*//*Label 1135*/ GIMT_Encode4(43346), |
| 15211 | /*GILLT_nxv32s8*//*Label 1136*/ GIMT_Encode4(43957), |
| 15212 | /*GILLT_nxv32s16*//*Label 1137*/ GIMT_Encode4(44072), |
| 15213 | /*GILLT_nxv64s1*//*Label 1138*/ GIMT_Encode4(44187), |
| 15214 | /*GILLT_nxv64s8*//*Label 1139*/ GIMT_Encode4(44798), |
| 15215 | // Label 1109: @37118 |
| 15216 | GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(37813), |
| 15217 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 15218 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15220 | GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(37188), // Rule ID 2625 // |
| 15221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 15222 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15223 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15224 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15225 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15226 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 15227 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15228 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15229 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 15230 | // (or:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), GPR:{ *:[i32] }:$rs1) => (BSET:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 15232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15233 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 15235 | GIR_RootConstrainSelectedInstOperands, |
| 15236 | // GIR_Coverage, 2625, |
| 15237 | GIR_EraseRootFromParent_Done, |
| 15238 | // Label 1142: @37188 |
| 15239 | GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(37243), // Rule ID 2850 // |
| 15240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 15241 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15242 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15243 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15244 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15245 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 15246 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15247 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15248 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 15249 | // (or:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), GPR:{ *:[i32] }:$rs1) => (BSET:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 15251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15252 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 15254 | GIR_RootConstrainSelectedInstOperands, |
| 15255 | // GIR_Coverage, 2850, |
| 15256 | GIR_EraseRootFromParent_Done, |
| 15257 | // Label 1143: @37243 |
| 15258 | GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(37298), // Rule ID 65204 // |
| 15259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 15260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15262 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15264 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15265 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 15266 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15267 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 15268 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2))) => (BSET:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 15270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 15273 | GIR_RootConstrainSelectedInstOperands, |
| 15274 | // GIR_Coverage, 65204, |
| 15275 | GIR_EraseRootFromParent_Done, |
| 15276 | // Label 1144: @37298 |
| 15277 | GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(37353), // Rule ID 65306 // |
| 15278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 15279 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15281 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15282 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15283 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15284 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 15285 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15286 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 15287 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2))) => (BSET:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 15289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15290 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 15292 | GIR_RootConstrainSelectedInstOperands, |
| 15293 | // GIR_Coverage, 65306, |
| 15294 | GIR_EraseRootFromParent_Done, |
| 15295 | // Label 1145: @37353 |
| 15296 | GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(37405), // Rule ID 65194 // |
| 15297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 15298 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15299 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15300 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15301 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15302 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15303 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15304 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15305 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15306 | // (or:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15309 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15311 | GIR_RootConstrainSelectedInstOperands, |
| 15312 | // GIR_Coverage, 65194, |
| 15313 | GIR_EraseRootFromParent_Done, |
| 15314 | // Label 1146: @37405 |
| 15315 | GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(37457), // Rule ID 65277 // |
| 15316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 15317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15318 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15319 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15320 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15321 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15322 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15324 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15325 | // (or:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15330 | GIR_RootConstrainSelectedInstOperands, |
| 15331 | // GIR_Coverage, 65277, |
| 15332 | GIR_EraseRootFromParent_Done, |
| 15333 | // Label 1147: @37457 |
| 15334 | GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(37509), // Rule ID 65278 // |
| 15335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 15336 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15337 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15338 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15339 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15340 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15341 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15342 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15343 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15344 | // (or:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15347 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15349 | GIR_RootConstrainSelectedInstOperands, |
| 15350 | // GIR_Coverage, 65278, |
| 15351 | GIR_EraseRootFromParent_Done, |
| 15352 | // Label 1148: @37509 |
| 15353 | GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(37561), // Rule ID 2605 // |
| 15354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 15355 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15359 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15360 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15361 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15362 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15363 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15366 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15368 | GIR_RootConstrainSelectedInstOperands, |
| 15369 | // GIR_Coverage, 2605, |
| 15370 | GIR_EraseRootFromParent_Done, |
| 15371 | // Label 1149: @37561 |
| 15372 | GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(37613), // Rule ID 2809 // |
| 15373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 15374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15375 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15376 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15377 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15378 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15379 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15380 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15381 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15382 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15385 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15387 | GIR_RootConstrainSelectedInstOperands, |
| 15388 | // GIR_Coverage, 2809, |
| 15389 | GIR_EraseRootFromParent_Done, |
| 15390 | // Label 1150: @37613 |
| 15391 | GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(37665), // Rule ID 2810 // |
| 15392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 15393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15397 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15398 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15399 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15400 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15401 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15404 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15406 | GIR_RootConstrainSelectedInstOperands, |
| 15407 | // GIR_Coverage, 2810, |
| 15408 | GIR_EraseRootFromParent_Done, |
| 15409 | // Label 1151: @37665 |
| 15410 | GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(37703), // Rule ID 75 // |
| 15411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 15412 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15414 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15415 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 15416 | // MIs[1] Operand 1 |
| 15417 | // No operand predicates |
| 15418 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15419 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) => (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) |
| 15420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORI), |
| 15421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15422 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15423 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15424 | GIR_RootConstrainSelectedInstOperands, |
| 15425 | // GIR_Coverage, 75, |
| 15426 | GIR_EraseRootFromParent_Done, |
| 15427 | // Label 1152: @37703 |
| 15428 | GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(37743), // Rule ID 312 // |
| 15429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 15430 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15431 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15432 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15433 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12i32), |
| 15434 | // MIs[1] Operand 1 |
| 15435 | // No operand predicates |
| 15436 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15437 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12i32>>:$imm) => (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (as_i64imm:{ *:[i64] } ?:{ *:[i32] }:$imm)) |
| 15438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORI), |
| 15439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15440 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15441 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm |
| 15442 | GIR_RootConstrainSelectedInstOperands, |
| 15443 | // GIR_Coverage, 312, |
| 15444 | GIR_EraseRootFromParent_Done, |
| 15445 | // Label 1153: @37743 |
| 15446 | GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(37766), // Rule ID 73 // |
| 15447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 15448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15450 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15451 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::OR), |
| 15452 | GIR_RootConstrainSelectedInstOperands, |
| 15453 | // GIR_Coverage, 73, |
| 15454 | GIR_Done, |
| 15455 | // Label 1154: @37766 |
| 15456 | GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(37789), // Rule ID 303 // |
| 15457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 15458 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15459 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15460 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15461 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::OR), |
| 15462 | GIR_RootConstrainSelectedInstOperands, |
| 15463 | // GIR_Coverage, 303, |
| 15464 | GIR_Done, |
| 15465 | // Label 1155: @37789 |
| 15466 | GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(37812), // Rule ID 304 // |
| 15467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 15468 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15469 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15470 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 15471 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::OR), |
| 15472 | GIR_RootConstrainSelectedInstOperands, |
| 15473 | // GIR_Coverage, 304, |
| 15474 | GIR_Done, |
| 15475 | // Label 1156: @37812 |
| 15476 | GIM_Reject, |
| 15477 | // Label 1141: @37813 |
| 15478 | GIM_Reject, |
| 15479 | // Label 1110: @37814 |
| 15480 | GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(38105), |
| 15481 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 15482 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 15483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15484 | GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(37884), // Rule ID 2624 // |
| 15485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 15486 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15487 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15488 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15489 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15490 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 15491 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15492 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15493 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 15494 | // (or:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), GPR:{ *:[i64] }:$rs1) => (BSET:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 15496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15497 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 15499 | GIR_RootConstrainSelectedInstOperands, |
| 15500 | // GIR_Coverage, 2624, |
| 15501 | GIR_EraseRootFromParent_Done, |
| 15502 | // Label 1158: @37884 |
| 15503 | GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(37939), // Rule ID 65203 // |
| 15504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 15505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15506 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15507 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15508 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15509 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15510 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 15511 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15512 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 15513 | // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2))) => (BSET:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 15515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15516 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 15518 | GIR_RootConstrainSelectedInstOperands, |
| 15519 | // GIR_Coverage, 65203, |
| 15520 | GIR_EraseRootFromParent_Done, |
| 15521 | // Label 1159: @37939 |
| 15522 | GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(37991), // Rule ID 65193 // |
| 15523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 15524 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15525 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15526 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15527 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15528 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15529 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15530 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15531 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15532 | // (or:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1) => (ORN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15535 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15537 | GIR_RootConstrainSelectedInstOperands, |
| 15538 | // GIR_Coverage, 65193, |
| 15539 | GIR_EraseRootFromParent_Done, |
| 15540 | // Label 1160: @37991 |
| 15541 | GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(38043), // Rule ID 2604 // |
| 15542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 15543 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15544 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15545 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15546 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15547 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15548 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15549 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15550 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15551 | // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] })) => (ORN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORN), |
| 15553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15554 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15556 | GIR_RootConstrainSelectedInstOperands, |
| 15557 | // GIR_Coverage, 2604, |
| 15558 | GIR_EraseRootFromParent_Done, |
| 15559 | // Label 1161: @38043 |
| 15560 | GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(38081), // Rule ID 74 // |
| 15561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 15562 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15563 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15564 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15565 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 15566 | // MIs[1] Operand 1 |
| 15567 | // No operand predicates |
| 15568 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15569 | // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) => (ORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) |
| 15570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ORI), |
| 15571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15572 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15573 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15574 | GIR_RootConstrainSelectedInstOperands, |
| 15575 | // GIR_Coverage, 74, |
| 15576 | GIR_EraseRootFromParent_Done, |
| 15577 | // Label 1162: @38081 |
| 15578 | GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(38104), // Rule ID 72 // |
| 15579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 15580 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 15582 | // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (OR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 15583 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::OR), |
| 15584 | GIR_RootConstrainSelectedInstOperands, |
| 15585 | // GIR_Coverage, 72, |
| 15586 | GIR_Done, |
| 15587 | // Label 1163: @38104 |
| 15588 | GIM_Reject, |
| 15589 | // Label 1157: @38105 |
| 15590 | GIM_Reject, |
| 15591 | // Label 1111: @38106 |
| 15592 | GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(38716), |
| 15593 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15596 | GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(38187), // Rule ID 71274 // |
| 15597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15598 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15599 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15600 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15601 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15602 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15603 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15604 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 15605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15607 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15608 | // (or:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs2), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15611 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 15613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15615 | GIR_RootConstrainSelectedInstOperands, |
| 15616 | // GIR_Coverage, 71274, |
| 15617 | GIR_EraseRootFromParent_Done, |
| 15618 | // Label 1165: @38187 |
| 15619 | GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(38253), // Rule ID 71275 // |
| 15620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15621 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15622 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15623 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15624 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15625 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15626 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15627 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15628 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15629 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15630 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15631 | // (or:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs2), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15634 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 15636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15638 | GIR_RootConstrainSelectedInstOperands, |
| 15639 | // GIR_Coverage, 71275, |
| 15640 | GIR_EraseRootFromParent_Done, |
| 15641 | // Label 1166: @38253 |
| 15642 | GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(38319), // Rule ID 71272 // |
| 15643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15644 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15645 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15646 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15647 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15648 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15649 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15650 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15651 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 15652 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15653 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15654 | // (or:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15657 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15661 | GIR_RootConstrainSelectedInstOperands, |
| 15662 | // GIR_Coverage, 71272, |
| 15663 | GIR_EraseRootFromParent_Done, |
| 15664 | // Label 1167: @38319 |
| 15665 | GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(38385), // Rule ID 71273 // |
| 15666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15667 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15668 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15669 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15670 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15671 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15672 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15673 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15674 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15675 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15676 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15677 | // (or:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15680 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 15681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15684 | GIR_RootConstrainSelectedInstOperands, |
| 15685 | // GIR_Coverage, 71273, |
| 15686 | GIR_EraseRootFromParent_Done, |
| 15687 | // Label 1168: @38385 |
| 15688 | GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(38451), // Rule ID 71270 // |
| 15689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15690 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15691 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15692 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15693 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15694 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15695 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15696 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15697 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 15698 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15699 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15700 | // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15704 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 15705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15707 | GIR_RootConstrainSelectedInstOperands, |
| 15708 | // GIR_Coverage, 71270, |
| 15709 | GIR_EraseRootFromParent_Done, |
| 15710 | // Label 1169: @38451 |
| 15711 | GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(38517), // Rule ID 71271 // |
| 15712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15713 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15714 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15715 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15716 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15717 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15718 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15719 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15720 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15721 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15722 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15723 | // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15726 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 15728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15730 | GIR_RootConstrainSelectedInstOperands, |
| 15731 | // GIR_Coverage, 71271, |
| 15732 | GIR_EraseRootFromParent_Done, |
| 15733 | // Label 1170: @38517 |
| 15734 | GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(38583), // Rule ID 53798 // |
| 15735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15737 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15738 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15739 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15740 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15741 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15742 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15743 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15744 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 15745 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15746 | // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15749 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15750 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15753 | GIR_RootConstrainSelectedInstOperands, |
| 15754 | // GIR_Coverage, 53798, |
| 15755 | GIR_EraseRootFromParent_Done, |
| 15756 | // Label 1171: @38583 |
| 15757 | GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(38649), // Rule ID 53799 // |
| 15758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15760 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15761 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15762 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 15763 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 15764 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15765 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15766 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 15767 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15768 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 15769 | // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF8), |
| 15771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15772 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 15774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15776 | GIR_RootConstrainSelectedInstOperands, |
| 15777 | // GIR_Coverage, 53799, |
| 15778 | GIR_EraseRootFromParent_Done, |
| 15779 | // Label 1172: @38649 |
| 15780 | GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(38682), // Rule ID 53786 // |
| 15781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15782 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15783 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15784 | // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 15785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_MF8), |
| 15786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15787 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15788 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15791 | GIR_RootConstrainSelectedInstOperands, |
| 15792 | // GIR_Coverage, 53786, |
| 15793 | GIR_EraseRootFromParent_Done, |
| 15794 | // Label 1173: @38682 |
| 15795 | GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(38715), // Rule ID 53787 // |
| 15796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15797 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15798 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15799 | // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 15800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_MF8), |
| 15801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15802 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15803 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15806 | GIR_RootConstrainSelectedInstOperands, |
| 15807 | // GIR_Coverage, 53787, |
| 15808 | GIR_EraseRootFromParent_Done, |
| 15809 | // Label 1174: @38715 |
| 15810 | GIM_Reject, |
| 15811 | // Label 1164: @38716 |
| 15812 | GIM_Reject, |
| 15813 | // Label 1112: @38717 |
| 15814 | GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(38831), |
| 15815 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 15816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 15817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15818 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15819 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15820 | GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(38785), // Rule ID 48412 // |
| 15821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15822 | // (or:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVOR_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 15823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 15824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15826 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF8), |
| 15828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15829 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15830 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15831 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15835 | GIR_RootConstrainSelectedInstOperands, |
| 15836 | // GIR_Coverage, 48412, |
| 15837 | GIR_EraseRootFromParent_Done, |
| 15838 | // Label 1176: @38785 |
| 15839 | GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(38830), // Rule ID 48413 // |
| 15840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15841 | // (or:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVOR_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 15842 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 15843 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15844 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15845 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF8), |
| 15847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15848 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15849 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15850 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15854 | GIR_RootConstrainSelectedInstOperands, |
| 15855 | // GIR_Coverage, 48413, |
| 15856 | GIR_EraseRootFromParent_Done, |
| 15857 | // Label 1177: @38830 |
| 15858 | GIM_Reject, |
| 15859 | // Label 1175: @38831 |
| 15860 | GIM_Reject, |
| 15861 | // Label 1113: @38832 |
| 15862 | GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(38946), |
| 15863 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 15864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 15865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15866 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15868 | GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(38900), // Rule ID 48424 // |
| 15869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15870 | // (or:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVOR_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 15871 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 15872 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15873 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15874 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF4), |
| 15876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15877 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15878 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15879 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 15882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15883 | GIR_RootConstrainSelectedInstOperands, |
| 15884 | // GIR_Coverage, 48424, |
| 15885 | GIR_EraseRootFromParent_Done, |
| 15886 | // Label 1179: @38900 |
| 15887 | GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(38945), // Rule ID 48425 // |
| 15888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15889 | // (or:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVOR_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 15890 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 15891 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15892 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF4), |
| 15895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15896 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15897 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15898 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 15901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15902 | GIR_RootConstrainSelectedInstOperands, |
| 15903 | // GIR_Coverage, 48425, |
| 15904 | GIR_EraseRootFromParent_Done, |
| 15905 | // Label 1180: @38945 |
| 15906 | GIM_Reject, |
| 15907 | // Label 1178: @38946 |
| 15908 | GIM_Reject, |
| 15909 | // Label 1114: @38947 |
| 15910 | GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(39061), |
| 15911 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 15912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 15913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15914 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15916 | GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(39015), // Rule ID 48432 // |
| 15917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 15918 | // (or:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVOR_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 15919 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 15920 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15922 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF2), |
| 15924 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15925 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15926 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15927 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 15930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15931 | GIR_RootConstrainSelectedInstOperands, |
| 15932 | // GIR_Coverage, 48432, |
| 15933 | GIR_EraseRootFromParent_Done, |
| 15934 | // Label 1182: @39015 |
| 15935 | GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(39060), // Rule ID 48433 // |
| 15936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 15937 | // (or:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVOR_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 15938 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 15939 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15940 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF2), |
| 15943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15944 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15945 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15946 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 15949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15950 | GIR_RootConstrainSelectedInstOperands, |
| 15951 | // GIR_Coverage, 48433, |
| 15952 | GIR_EraseRootFromParent_Done, |
| 15953 | // Label 1183: @39060 |
| 15954 | GIM_Reject, |
| 15955 | // Label 1181: @39061 |
| 15956 | GIM_Reject, |
| 15957 | // Label 1115: @39062 |
| 15958 | GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(39176), |
| 15959 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 15960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 15961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15962 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15963 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 15964 | GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(39130), // Rule ID 48448 // |
| 15965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 15966 | // (or:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 15967 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 15968 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15969 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 15972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15973 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15974 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15975 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 15978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15979 | GIR_RootConstrainSelectedInstOperands, |
| 15980 | // GIR_Coverage, 48448, |
| 15981 | GIR_EraseRootFromParent_Done, |
| 15982 | // Label 1185: @39130 |
| 15983 | GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(39175), // Rule ID 48449 // |
| 15984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 15985 | // (or:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 15986 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 15987 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15988 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 15991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 15992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15993 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 15994 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 15995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 15996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 15997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 15998 | GIR_RootConstrainSelectedInstOperands, |
| 15999 | // GIR_Coverage, 48449, |
| 16000 | GIR_EraseRootFromParent_Done, |
| 16001 | // Label 1186: @39175 |
| 16002 | GIM_Reject, |
| 16003 | // Label 1184: @39176 |
| 16004 | GIM_Reject, |
| 16005 | // Label 1116: @39177 |
| 16006 | GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(39787), |
| 16007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16010 | GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(39258), // Rule ID 71302 // |
| 16011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16012 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16013 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16014 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16015 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16016 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16017 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16018 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16019 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16020 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16021 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16022 | // (or:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs2), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16025 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16029 | GIR_RootConstrainSelectedInstOperands, |
| 16030 | // GIR_Coverage, 71302, |
| 16031 | GIR_EraseRootFromParent_Done, |
| 16032 | // Label 1188: @39258 |
| 16033 | GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(39324), // Rule ID 71303 // |
| 16034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16036 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16037 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16038 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16039 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16040 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16041 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16042 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16044 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16045 | // (or:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs2), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16052 | GIR_RootConstrainSelectedInstOperands, |
| 16053 | // GIR_Coverage, 71303, |
| 16054 | GIR_EraseRootFromParent_Done, |
| 16055 | // Label 1189: @39324 |
| 16056 | GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(39390), // Rule ID 71300 // |
| 16057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16058 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16059 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16060 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16061 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16062 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16063 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16064 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16065 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16066 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16067 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16068 | // (or:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16071 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16075 | GIR_RootConstrainSelectedInstOperands, |
| 16076 | // GIR_Coverage, 71300, |
| 16077 | GIR_EraseRootFromParent_Done, |
| 16078 | // Label 1190: @39390 |
| 16079 | GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(39456), // Rule ID 71301 // |
| 16080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16081 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16082 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16083 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16084 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16085 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16086 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16087 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16088 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16089 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16090 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16091 | // (or:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16094 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16098 | GIR_RootConstrainSelectedInstOperands, |
| 16099 | // GIR_Coverage, 71301, |
| 16100 | GIR_EraseRootFromParent_Done, |
| 16101 | // Label 1191: @39456 |
| 16102 | GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(39522), // Rule ID 71298 // |
| 16103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16106 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16107 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16108 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16109 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16110 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16111 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16112 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16113 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16114 | // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16117 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16121 | GIR_RootConstrainSelectedInstOperands, |
| 16122 | // GIR_Coverage, 71298, |
| 16123 | GIR_EraseRootFromParent_Done, |
| 16124 | // Label 1192: @39522 |
| 16125 | GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(39588), // Rule ID 71299 // |
| 16126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16128 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16129 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16130 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16131 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16132 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16133 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16134 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16135 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16136 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16137 | // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16140 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16144 | GIR_RootConstrainSelectedInstOperands, |
| 16145 | // GIR_Coverage, 71299, |
| 16146 | GIR_EraseRootFromParent_Done, |
| 16147 | // Label 1193: @39588 |
| 16148 | GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(39654), // Rule ID 53816 // |
| 16149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16151 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16152 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16153 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16154 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16155 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16156 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16157 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16158 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16159 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16160 | // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16163 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16167 | GIR_RootConstrainSelectedInstOperands, |
| 16168 | // GIR_Coverage, 53816, |
| 16169 | GIR_EraseRootFromParent_Done, |
| 16170 | // Label 1194: @39654 |
| 16171 | GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(39720), // Rule ID 53817 // |
| 16172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16174 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16175 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16176 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 16177 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 16178 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16179 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16180 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16181 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16182 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16183 | // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF4), |
| 16185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16186 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16187 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16190 | GIR_RootConstrainSelectedInstOperands, |
| 16191 | // GIR_Coverage, 53817, |
| 16192 | GIR_EraseRootFromParent_Done, |
| 16193 | // Label 1195: @39720 |
| 16194 | GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(39753), // Rule ID 53804 // |
| 16195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16196 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16197 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16198 | // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_MF4), |
| 16200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16201 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16202 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16205 | GIR_RootConstrainSelectedInstOperands, |
| 16206 | // GIR_Coverage, 53804, |
| 16207 | GIR_EraseRootFromParent_Done, |
| 16208 | // Label 1196: @39753 |
| 16209 | GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(39786), // Rule ID 53805 // |
| 16210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16211 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16212 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16213 | // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_MF4), |
| 16215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16216 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16217 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16220 | GIR_RootConstrainSelectedInstOperands, |
| 16221 | // GIR_Coverage, 53805, |
| 16222 | GIR_EraseRootFromParent_Done, |
| 16223 | // Label 1197: @39786 |
| 16224 | GIM_Reject, |
| 16225 | // Label 1187: @39787 |
| 16226 | GIM_Reject, |
| 16227 | // Label 1117: @39788 |
| 16228 | GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(39902), |
| 16229 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 16230 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 16231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16232 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16234 | GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(39856), // Rule ID 48416 // |
| 16235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16236 | // (or:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVOR_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 16237 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 16238 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16239 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16240 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF4), |
| 16242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16243 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16244 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16245 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16249 | GIR_RootConstrainSelectedInstOperands, |
| 16250 | // GIR_Coverage, 48416, |
| 16251 | GIR_EraseRootFromParent_Done, |
| 16252 | // Label 1199: @39856 |
| 16253 | GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(39901), // Rule ID 48417 // |
| 16254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16255 | // (or:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVOR_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 16256 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 16257 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16258 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16259 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF4), |
| 16261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16262 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16263 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16264 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16268 | GIR_RootConstrainSelectedInstOperands, |
| 16269 | // GIR_Coverage, 48417, |
| 16270 | GIR_EraseRootFromParent_Done, |
| 16271 | // Label 1200: @39901 |
| 16272 | GIM_Reject, |
| 16273 | // Label 1198: @39902 |
| 16274 | GIM_Reject, |
| 16275 | // Label 1118: @39903 |
| 16276 | GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(40017), |
| 16277 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 16278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 16279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16280 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16282 | GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(39971), // Rule ID 48428 // |
| 16283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16284 | // (or:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVOR_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 16285 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 16286 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16287 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF2), |
| 16290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16291 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16292 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16293 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 16296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16297 | GIR_RootConstrainSelectedInstOperands, |
| 16298 | // GIR_Coverage, 48428, |
| 16299 | GIR_EraseRootFromParent_Done, |
| 16300 | // Label 1202: @39971 |
| 16301 | GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(40016), // Rule ID 48429 // |
| 16302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16303 | // (or:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVOR_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 16304 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 16305 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16306 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16307 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF2), |
| 16309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16310 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16311 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16312 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 16315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16316 | GIR_RootConstrainSelectedInstOperands, |
| 16317 | // GIR_Coverage, 48429, |
| 16318 | GIR_EraseRootFromParent_Done, |
| 16319 | // Label 1203: @40016 |
| 16320 | GIM_Reject, |
| 16321 | // Label 1201: @40017 |
| 16322 | GIM_Reject, |
| 16323 | // Label 1119: @40018 |
| 16324 | GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(40132), |
| 16325 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 16326 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 16327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16328 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16329 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16330 | GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(40086), // Rule ID 48444 // |
| 16331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16332 | // (or:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 16333 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 16334 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16335 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 16338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16339 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16340 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16341 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 16344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16345 | GIR_RootConstrainSelectedInstOperands, |
| 16346 | // GIR_Coverage, 48444, |
| 16347 | GIR_EraseRootFromParent_Done, |
| 16348 | // Label 1205: @40086 |
| 16349 | GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(40131), // Rule ID 48445 // |
| 16350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16351 | // (or:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 16352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 16353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16354 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16355 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 16357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16358 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16359 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16360 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 16363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16364 | GIR_RootConstrainSelectedInstOperands, |
| 16365 | // GIR_Coverage, 48445, |
| 16366 | GIR_EraseRootFromParent_Done, |
| 16367 | // Label 1206: @40131 |
| 16368 | GIM_Reject, |
| 16369 | // Label 1204: @40132 |
| 16370 | GIM_Reject, |
| 16371 | // Label 1120: @40133 |
| 16372 | GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(40247), |
| 16373 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 16374 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 16375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 16376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 16377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 16378 | GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(40201), // Rule ID 48488 // |
| 16379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 16380 | // (or:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 16381 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 16382 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 16386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16387 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16388 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16389 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 16392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16393 | GIR_RootConstrainSelectedInstOperands, |
| 16394 | // GIR_Coverage, 48488, |
| 16395 | GIR_EraseRootFromParent_Done, |
| 16396 | // Label 1208: @40201 |
| 16397 | GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(40246), // Rule ID 48489 // |
| 16398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 16399 | // (or:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 16400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 16401 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16402 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 16405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16406 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16407 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16408 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 16411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16412 | GIR_RootConstrainSelectedInstOperands, |
| 16413 | // GIR_Coverage, 48489, |
| 16414 | GIR_EraseRootFromParent_Done, |
| 16415 | // Label 1209: @40246 |
| 16416 | GIM_Reject, |
| 16417 | // Label 1207: @40247 |
| 16418 | GIM_Reject, |
| 16419 | // Label 1121: @40248 |
| 16420 | GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(40858), |
| 16421 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16422 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16423 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16424 | GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(40329), // Rule ID 71330 // |
| 16425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16426 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16427 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16428 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16429 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16430 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16431 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16432 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16433 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16434 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16435 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16436 | // (or:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs2), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16439 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16443 | GIR_RootConstrainSelectedInstOperands, |
| 16444 | // GIR_Coverage, 71330, |
| 16445 | GIR_EraseRootFromParent_Done, |
| 16446 | // Label 1211: @40329 |
| 16447 | GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(40395), // Rule ID 71331 // |
| 16448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16449 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16450 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16451 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16452 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16453 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16454 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16455 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16456 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16458 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16459 | // (or:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs2), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16462 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16466 | GIR_RootConstrainSelectedInstOperands, |
| 16467 | // GIR_Coverage, 71331, |
| 16468 | GIR_EraseRootFromParent_Done, |
| 16469 | // Label 1212: @40395 |
| 16470 | GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(40461), // Rule ID 71328 // |
| 16471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16472 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16473 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16474 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16475 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16476 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16477 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16478 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16479 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16480 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16481 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16482 | // (or:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16485 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16489 | GIR_RootConstrainSelectedInstOperands, |
| 16490 | // GIR_Coverage, 71328, |
| 16491 | GIR_EraseRootFromParent_Done, |
| 16492 | // Label 1213: @40461 |
| 16493 | GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(40527), // Rule ID 71329 // |
| 16494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16496 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16497 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16498 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16499 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16500 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16501 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16502 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16504 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16505 | // (or:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16508 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16512 | GIR_RootConstrainSelectedInstOperands, |
| 16513 | // GIR_Coverage, 71329, |
| 16514 | GIR_EraseRootFromParent_Done, |
| 16515 | // Label 1214: @40527 |
| 16516 | GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(40593), // Rule ID 71326 // |
| 16517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16518 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16519 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16520 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16521 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16522 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16523 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16524 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16525 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16526 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16527 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16528 | // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16531 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16535 | GIR_RootConstrainSelectedInstOperands, |
| 16536 | // GIR_Coverage, 71326, |
| 16537 | GIR_EraseRootFromParent_Done, |
| 16538 | // Label 1215: @40593 |
| 16539 | GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(40659), // Rule ID 71327 // |
| 16540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16541 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16542 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16543 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16544 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16545 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16546 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16547 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16548 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16549 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16550 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16551 | // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16554 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16558 | GIR_RootConstrainSelectedInstOperands, |
| 16559 | // GIR_Coverage, 71327, |
| 16560 | GIR_EraseRootFromParent_Done, |
| 16561 | // Label 1216: @40659 |
| 16562 | GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(40725), // Rule ID 53834 // |
| 16563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16564 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16568 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16569 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16570 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16571 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16572 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16573 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16574 | // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16576 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16577 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16581 | GIR_RootConstrainSelectedInstOperands, |
| 16582 | // GIR_Coverage, 53834, |
| 16583 | GIR_EraseRootFromParent_Done, |
| 16584 | // Label 1217: @40725 |
| 16585 | GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(40791), // Rule ID 53835 // |
| 16586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16587 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16589 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16590 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 16591 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 16592 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16593 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16594 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16595 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16596 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16597 | // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_MF2), |
| 16599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16600 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16604 | GIR_RootConstrainSelectedInstOperands, |
| 16605 | // GIR_Coverage, 53835, |
| 16606 | GIR_EraseRootFromParent_Done, |
| 16607 | // Label 1218: @40791 |
| 16608 | GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(40824), // Rule ID 53822 // |
| 16609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16610 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16611 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16612 | // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_MF2), |
| 16614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16616 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16619 | GIR_RootConstrainSelectedInstOperands, |
| 16620 | // GIR_Coverage, 53822, |
| 16621 | GIR_EraseRootFromParent_Done, |
| 16622 | // Label 1219: @40824 |
| 16623 | GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(40857), // Rule ID 53823 // |
| 16624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16626 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16627 | // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_MF2), |
| 16629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16630 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16631 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16634 | GIR_RootConstrainSelectedInstOperands, |
| 16635 | // GIR_Coverage, 53823, |
| 16636 | GIR_EraseRootFromParent_Done, |
| 16637 | // Label 1220: @40857 |
| 16638 | GIM_Reject, |
| 16639 | // Label 1210: @40858 |
| 16640 | GIM_Reject, |
| 16641 | // Label 1122: @40859 |
| 16642 | GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(40973), |
| 16643 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 16644 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 16645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16646 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16648 | GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(40927), // Rule ID 48420 // |
| 16649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16650 | // (or:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVOR_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 16651 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 16652 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16653 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16654 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF2), |
| 16656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16657 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16658 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16659 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16663 | GIR_RootConstrainSelectedInstOperands, |
| 16664 | // GIR_Coverage, 48420, |
| 16665 | GIR_EraseRootFromParent_Done, |
| 16666 | // Label 1222: @40927 |
| 16667 | GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(40972), // Rule ID 48421 // |
| 16668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16669 | // (or:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVOR_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 16670 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 16671 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16672 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16673 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_MF2), |
| 16675 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16676 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16677 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16678 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16682 | GIR_RootConstrainSelectedInstOperands, |
| 16683 | // GIR_Coverage, 48421, |
| 16684 | GIR_EraseRootFromParent_Done, |
| 16685 | // Label 1223: @40972 |
| 16686 | GIM_Reject, |
| 16687 | // Label 1221: @40973 |
| 16688 | GIM_Reject, |
| 16689 | // Label 1123: @40974 |
| 16690 | GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(41088), |
| 16691 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 16692 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 16693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16696 | GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(41042), // Rule ID 48440 // |
| 16697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16698 | // (or:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 16699 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 16700 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16701 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16702 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 16704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16705 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16706 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16707 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 16710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16711 | GIR_RootConstrainSelectedInstOperands, |
| 16712 | // GIR_Coverage, 48440, |
| 16713 | GIR_EraseRootFromParent_Done, |
| 16714 | // Label 1225: @41042 |
| 16715 | GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(41087), // Rule ID 48441 // |
| 16716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16717 | // (or:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 16718 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 16719 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16720 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 16723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16725 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16726 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 16729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16730 | GIR_RootConstrainSelectedInstOperands, |
| 16731 | // GIR_Coverage, 48441, |
| 16732 | GIR_EraseRootFromParent_Done, |
| 16733 | // Label 1226: @41087 |
| 16734 | GIM_Reject, |
| 16735 | // Label 1224: @41088 |
| 16736 | GIM_Reject, |
| 16737 | // Label 1124: @41089 |
| 16738 | GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(41203), |
| 16739 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 16740 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 16741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 16742 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 16743 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 16744 | GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(41157), // Rule ID 48476 // |
| 16745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16746 | // (or:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 16747 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 16748 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16749 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 16752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16753 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16754 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16755 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 16758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16759 | GIR_RootConstrainSelectedInstOperands, |
| 16760 | // GIR_Coverage, 48476, |
| 16761 | GIR_EraseRootFromParent_Done, |
| 16762 | // Label 1228: @41157 |
| 16763 | GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(41202), // Rule ID 48477 // |
| 16764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16765 | // (or:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 16766 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 16767 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16768 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16769 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 16771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16772 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16773 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16774 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 16777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16778 | GIR_RootConstrainSelectedInstOperands, |
| 16779 | // GIR_Coverage, 48477, |
| 16780 | GIR_EraseRootFromParent_Done, |
| 16781 | // Label 1229: @41202 |
| 16782 | GIM_Reject, |
| 16783 | // Label 1227: @41203 |
| 16784 | GIM_Reject, |
| 16785 | // Label 1125: @41204 |
| 16786 | GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(41318), |
| 16787 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 16788 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 16789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 16790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 16791 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 16792 | GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(41272), // Rule ID 48492 // |
| 16793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 16794 | // (or:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 16795 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 16796 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16797 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 16800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16801 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16802 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16803 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 16806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16807 | GIR_RootConstrainSelectedInstOperands, |
| 16808 | // GIR_Coverage, 48492, |
| 16809 | GIR_EraseRootFromParent_Done, |
| 16810 | // Label 1231: @41272 |
| 16811 | GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(41317), // Rule ID 48493 // |
| 16812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 16813 | // (or:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 16814 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 16815 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16816 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16817 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 16819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16820 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16821 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16822 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 16823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 16825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 16826 | GIR_RootConstrainSelectedInstOperands, |
| 16827 | // GIR_Coverage, 48493, |
| 16828 | GIR_EraseRootFromParent_Done, |
| 16829 | // Label 1232: @41317 |
| 16830 | GIM_Reject, |
| 16831 | // Label 1230: @41318 |
| 16832 | GIM_Reject, |
| 16833 | // Label 1126: @41319 |
| 16834 | GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(41929), |
| 16835 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16838 | GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(41400), // Rule ID 71358 // |
| 16839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16840 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16841 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16842 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16843 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16844 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16845 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16846 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16847 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16848 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16849 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16850 | // (or:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs2), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16853 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16857 | GIR_RootConstrainSelectedInstOperands, |
| 16858 | // GIR_Coverage, 71358, |
| 16859 | GIR_EraseRootFromParent_Done, |
| 16860 | // Label 1234: @41400 |
| 16861 | GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(41466), // Rule ID 71359 // |
| 16862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16863 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16864 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16865 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16866 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16867 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16868 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16869 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16870 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16871 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16872 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16873 | // (or:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs2), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16876 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16880 | GIR_RootConstrainSelectedInstOperands, |
| 16881 | // GIR_Coverage, 71359, |
| 16882 | GIR_EraseRootFromParent_Done, |
| 16883 | // Label 1235: @41466 |
| 16884 | GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(41532), // Rule ID 71356 // |
| 16885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16887 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16889 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16890 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16891 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16892 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16893 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16894 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16895 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16896 | // (or:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16899 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16903 | GIR_RootConstrainSelectedInstOperands, |
| 16904 | // GIR_Coverage, 71356, |
| 16905 | GIR_EraseRootFromParent_Done, |
| 16906 | // Label 1236: @41532 |
| 16907 | GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(41598), // Rule ID 71357 // |
| 16908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16909 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 16910 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16911 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16912 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16913 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16914 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16915 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16916 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16917 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16918 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16919 | // (or:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16922 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 16923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16926 | GIR_RootConstrainSelectedInstOperands, |
| 16927 | // GIR_Coverage, 71357, |
| 16928 | GIR_EraseRootFromParent_Done, |
| 16929 | // Label 1237: @41598 |
| 16930 | GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(41664), // Rule ID 71354 // |
| 16931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16932 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16934 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16935 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16936 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16937 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16938 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16939 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16940 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16941 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16942 | // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16945 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16949 | GIR_RootConstrainSelectedInstOperands, |
| 16950 | // GIR_Coverage, 71354, |
| 16951 | GIR_EraseRootFromParent_Done, |
| 16952 | // Label 1238: @41664 |
| 16953 | GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(41730), // Rule ID 71355 // |
| 16954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 16955 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16956 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16957 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16958 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16959 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16960 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16961 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16962 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 16963 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16964 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16965 | // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 16966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16968 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 16970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16972 | GIR_RootConstrainSelectedInstOperands, |
| 16973 | // GIR_Coverage, 71355, |
| 16974 | GIR_EraseRootFromParent_Done, |
| 16975 | // Label 1239: @41730 |
| 16976 | GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(41796), // Rule ID 53852 // |
| 16977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 16978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16979 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16980 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 16981 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 16982 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 16983 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 16984 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16985 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 16986 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 16987 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16988 | // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 16989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 16990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 16991 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 16992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 16993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 16994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16995 | GIR_RootConstrainSelectedInstOperands, |
| 16996 | // GIR_Coverage, 53852, |
| 16997 | GIR_EraseRootFromParent_Done, |
| 16998 | // Label 1240: @41796 |
| 16999 | GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(41862), // Rule ID 53853 // |
| 17000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17003 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 17005 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 17006 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17007 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17008 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17009 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17010 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17011 | // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M1), |
| 17013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17014 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17018 | GIR_RootConstrainSelectedInstOperands, |
| 17019 | // GIR_Coverage, 53853, |
| 17020 | GIR_EraseRootFromParent_Done, |
| 17021 | // Label 1241: @41862 |
| 17022 | GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(41895), // Rule ID 53840 // |
| 17023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17024 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17025 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17026 | // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M1), |
| 17028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17029 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17030 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17033 | GIR_RootConstrainSelectedInstOperands, |
| 17034 | // GIR_Coverage, 53840, |
| 17035 | GIR_EraseRootFromParent_Done, |
| 17036 | // Label 1242: @41895 |
| 17037 | GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(41928), // Rule ID 53841 // |
| 17038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17040 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17041 | // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M1), |
| 17043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17044 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17045 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17048 | GIR_RootConstrainSelectedInstOperands, |
| 17049 | // GIR_Coverage, 53841, |
| 17050 | GIR_EraseRootFromParent_Done, |
| 17051 | // Label 1243: @41928 |
| 17052 | GIM_Reject, |
| 17053 | // Label 1233: @41929 |
| 17054 | GIM_Reject, |
| 17055 | // Label 1127: @41930 |
| 17056 | GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(42044), |
| 17057 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 17058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 17059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17060 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17061 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17062 | GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(41998), // Rule ID 48436 // |
| 17063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17064 | // (or:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 17065 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 17066 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17067 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17068 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 17070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17071 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17072 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17073 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17077 | GIR_RootConstrainSelectedInstOperands, |
| 17078 | // GIR_Coverage, 48436, |
| 17079 | GIR_EraseRootFromParent_Done, |
| 17080 | // Label 1245: @41998 |
| 17081 | GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(42043), // Rule ID 48437 // |
| 17082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17083 | // (or:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVOR_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 17084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 17085 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17086 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M1), |
| 17089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17090 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17091 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17092 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17096 | GIR_RootConstrainSelectedInstOperands, |
| 17097 | // GIR_Coverage, 48437, |
| 17098 | GIR_EraseRootFromParent_Done, |
| 17099 | // Label 1246: @42043 |
| 17100 | GIM_Reject, |
| 17101 | // Label 1244: @42044 |
| 17102 | GIM_Reject, |
| 17103 | // Label 1128: @42045 |
| 17104 | GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(42159), |
| 17105 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 17106 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 17107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 17108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 17109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 17110 | GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(42113), // Rule ID 48464 // |
| 17111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17112 | // (or:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 17113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 17114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 17118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17119 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17120 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17121 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 17124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17125 | GIR_RootConstrainSelectedInstOperands, |
| 17126 | // GIR_Coverage, 48464, |
| 17127 | GIR_EraseRootFromParent_Done, |
| 17128 | // Label 1248: @42113 |
| 17129 | GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(42158), // Rule ID 48465 // |
| 17130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17131 | // (or:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 17132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 17133 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17134 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 17137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17138 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17139 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17140 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 17143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17144 | GIR_RootConstrainSelectedInstOperands, |
| 17145 | // GIR_Coverage, 48465, |
| 17146 | GIR_EraseRootFromParent_Done, |
| 17147 | // Label 1249: @42158 |
| 17148 | GIM_Reject, |
| 17149 | // Label 1247: @42159 |
| 17150 | GIM_Reject, |
| 17151 | // Label 1129: @42160 |
| 17152 | GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(42274), |
| 17153 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 17154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 17155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17157 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17158 | GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(42228), // Rule ID 48480 // |
| 17159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17160 | // (or:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 17161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 17162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 17166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17167 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17169 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 17172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17173 | GIR_RootConstrainSelectedInstOperands, |
| 17174 | // GIR_Coverage, 48480, |
| 17175 | GIR_EraseRootFromParent_Done, |
| 17176 | // Label 1251: @42228 |
| 17177 | GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(42273), // Rule ID 48481 // |
| 17178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17179 | // (or:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 17180 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 17181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 17185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17187 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17188 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 17191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17192 | GIR_RootConstrainSelectedInstOperands, |
| 17193 | // GIR_Coverage, 48481, |
| 17194 | GIR_EraseRootFromParent_Done, |
| 17195 | // Label 1252: @42273 |
| 17196 | GIM_Reject, |
| 17197 | // Label 1250: @42274 |
| 17198 | GIM_Reject, |
| 17199 | // Label 1130: @42275 |
| 17200 | GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(42389), |
| 17201 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 17202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 17203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17204 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17205 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17206 | GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(42343), // Rule ID 48496 // |
| 17207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 17208 | // (or:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 17209 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 17210 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17211 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17212 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 17214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17215 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17216 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17217 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 17220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17221 | GIR_RootConstrainSelectedInstOperands, |
| 17222 | // GIR_Coverage, 48496, |
| 17223 | GIR_EraseRootFromParent_Done, |
| 17224 | // Label 1254: @42343 |
| 17225 | GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(42388), // Rule ID 48497 // |
| 17226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 17227 | // (or:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 17228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 17229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17230 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 17233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17234 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17235 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17236 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 17239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17240 | GIR_RootConstrainSelectedInstOperands, |
| 17241 | // GIR_Coverage, 48497, |
| 17242 | GIR_EraseRootFromParent_Done, |
| 17243 | // Label 1255: @42388 |
| 17244 | GIM_Reject, |
| 17245 | // Label 1253: @42389 |
| 17246 | GIM_Reject, |
| 17247 | // Label 1131: @42390 |
| 17248 | GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(43000), |
| 17249 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17252 | GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(42471), // Rule ID 71386 // |
| 17253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17255 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17257 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17259 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17261 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17262 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17263 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17264 | // (or:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs2), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17267 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17271 | GIR_RootConstrainSelectedInstOperands, |
| 17272 | // GIR_Coverage, 71386, |
| 17273 | GIR_EraseRootFromParent_Done, |
| 17274 | // Label 1257: @42471 |
| 17275 | GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(42537), // Rule ID 71387 // |
| 17276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17277 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17278 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17279 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17280 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17281 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17282 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17283 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17284 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17286 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17287 | // (or:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs2), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17290 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17294 | GIR_RootConstrainSelectedInstOperands, |
| 17295 | // GIR_Coverage, 71387, |
| 17296 | GIR_EraseRootFromParent_Done, |
| 17297 | // Label 1258: @42537 |
| 17298 | GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(42603), // Rule ID 71384 // |
| 17299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17300 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17301 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17302 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17303 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17304 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17305 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17306 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17307 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17308 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17309 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17310 | // (or:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17313 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17317 | GIR_RootConstrainSelectedInstOperands, |
| 17318 | // GIR_Coverage, 71384, |
| 17319 | GIR_EraseRootFromParent_Done, |
| 17320 | // Label 1259: @42603 |
| 17321 | GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(42669), // Rule ID 71385 // |
| 17322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17323 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17324 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17325 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17326 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17327 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17328 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17329 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17330 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17331 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17332 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17333 | // (or:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv16i1] }:$rs1) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17336 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17340 | GIR_RootConstrainSelectedInstOperands, |
| 17341 | // GIR_Coverage, 71385, |
| 17342 | GIR_EraseRootFromParent_Done, |
| 17343 | // Label 1260: @42669 |
| 17344 | GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(42735), // Rule ID 71382 // |
| 17345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17346 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17347 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17348 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17349 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17350 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17351 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17352 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17353 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17354 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17355 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17356 | // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17359 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17363 | GIR_RootConstrainSelectedInstOperands, |
| 17364 | // GIR_Coverage, 71382, |
| 17365 | GIR_EraseRootFromParent_Done, |
| 17366 | // Label 1261: @42735 |
| 17367 | GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(42801), // Rule ID 71383 // |
| 17368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17369 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17371 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17372 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17373 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17374 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17375 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17376 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17377 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17378 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17379 | // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17382 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17386 | GIR_RootConstrainSelectedInstOperands, |
| 17387 | // GIR_Coverage, 71383, |
| 17388 | GIR_EraseRootFromParent_Done, |
| 17389 | // Label 1262: @42801 |
| 17390 | GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(42867), // Rule ID 53870 // |
| 17391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17393 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17394 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17395 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17396 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17397 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17398 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17399 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17400 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17401 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17402 | // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17405 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17409 | GIR_RootConstrainSelectedInstOperands, |
| 17410 | // GIR_Coverage, 53870, |
| 17411 | GIR_EraseRootFromParent_Done, |
| 17412 | // Label 1263: @42867 |
| 17413 | GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(42933), // Rule ID 53871 // |
| 17414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17415 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17416 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17417 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17418 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 17419 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 17420 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17421 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17422 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17423 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17424 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17425 | // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M2), |
| 17427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17428 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17432 | GIR_RootConstrainSelectedInstOperands, |
| 17433 | // GIR_Coverage, 53871, |
| 17434 | GIR_EraseRootFromParent_Done, |
| 17435 | // Label 1264: @42933 |
| 17436 | GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(42966), // Rule ID 53858 // |
| 17437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17438 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17439 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17440 | // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M2), |
| 17442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17443 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17444 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17447 | GIR_RootConstrainSelectedInstOperands, |
| 17448 | // GIR_Coverage, 53858, |
| 17449 | GIR_EraseRootFromParent_Done, |
| 17450 | // Label 1265: @42966 |
| 17451 | GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(42999), // Rule ID 53859 // |
| 17452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17453 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17454 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17455 | // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M2), |
| 17457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17458 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17459 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17462 | GIR_RootConstrainSelectedInstOperands, |
| 17463 | // GIR_Coverage, 53859, |
| 17464 | GIR_EraseRootFromParent_Done, |
| 17465 | // Label 1266: @42999 |
| 17466 | GIM_Reject, |
| 17467 | // Label 1256: @43000 |
| 17468 | GIM_Reject, |
| 17469 | // Label 1132: @43001 |
| 17470 | GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(43115), |
| 17471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 17472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 17473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 17474 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 17475 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 17476 | GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(43069), // Rule ID 48452 // |
| 17477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17478 | // (or:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 17479 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 17480 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17481 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 17484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17485 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17486 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17487 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17491 | GIR_RootConstrainSelectedInstOperands, |
| 17492 | // GIR_Coverage, 48452, |
| 17493 | GIR_EraseRootFromParent_Done, |
| 17494 | // Label 1268: @43069 |
| 17495 | GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(43114), // Rule ID 48453 // |
| 17496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17497 | // (or:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVOR_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 17498 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 17499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M2), |
| 17503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17504 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17505 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17510 | GIR_RootConstrainSelectedInstOperands, |
| 17511 | // GIR_Coverage, 48453, |
| 17512 | GIR_EraseRootFromParent_Done, |
| 17513 | // Label 1269: @43114 |
| 17514 | GIM_Reject, |
| 17515 | // Label 1267: @43115 |
| 17516 | GIM_Reject, |
| 17517 | // Label 1133: @43116 |
| 17518 | GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(43230), |
| 17519 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 17520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 17521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17524 | GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(43184), // Rule ID 48468 // |
| 17525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17526 | // (or:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 17527 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 17528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17529 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 17532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17534 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17535 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 17538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17539 | GIR_RootConstrainSelectedInstOperands, |
| 17540 | // GIR_Coverage, 48468, |
| 17541 | GIR_EraseRootFromParent_Done, |
| 17542 | // Label 1271: @43184 |
| 17543 | GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(43229), // Rule ID 48469 // |
| 17544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17545 | // (or:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 17546 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 17547 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17548 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 17551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17552 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17553 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17554 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 17557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17558 | GIR_RootConstrainSelectedInstOperands, |
| 17559 | // GIR_Coverage, 48469, |
| 17560 | GIR_EraseRootFromParent_Done, |
| 17561 | // Label 1272: @43229 |
| 17562 | GIM_Reject, |
| 17563 | // Label 1270: @43230 |
| 17564 | GIM_Reject, |
| 17565 | // Label 1134: @43231 |
| 17566 | GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(43345), |
| 17567 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 17568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 17569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17570 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17571 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17572 | GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(43299), // Rule ID 48484 // |
| 17573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17574 | // (or:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 17575 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 17576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17577 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 17580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17581 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17582 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17583 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 17586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17587 | GIR_RootConstrainSelectedInstOperands, |
| 17588 | // GIR_Coverage, 48484, |
| 17589 | GIR_EraseRootFromParent_Done, |
| 17590 | // Label 1274: @43299 |
| 17591 | GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(43344), // Rule ID 48485 // |
| 17592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17593 | // (or:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 17594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 17595 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17596 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 17599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17600 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17601 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17602 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 17605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17606 | GIR_RootConstrainSelectedInstOperands, |
| 17607 | // GIR_Coverage, 48485, |
| 17608 | GIR_EraseRootFromParent_Done, |
| 17609 | // Label 1275: @43344 |
| 17610 | GIM_Reject, |
| 17611 | // Label 1273: @43345 |
| 17612 | GIM_Reject, |
| 17613 | // Label 1135: @43346 |
| 17614 | GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(43956), |
| 17615 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17618 | GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(43427), // Rule ID 71414 // |
| 17619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17620 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17621 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17622 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17623 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17624 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17625 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17626 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17627 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17628 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17629 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17630 | // (or:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs2), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17632 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17633 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17637 | GIR_RootConstrainSelectedInstOperands, |
| 17638 | // GIR_Coverage, 71414, |
| 17639 | GIR_EraseRootFromParent_Done, |
| 17640 | // Label 1277: @43427 |
| 17641 | GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(43493), // Rule ID 71415 // |
| 17642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17643 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17644 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17645 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17646 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17647 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17648 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17649 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17650 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17651 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17652 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17653 | // (or:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs2), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17656 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17660 | GIR_RootConstrainSelectedInstOperands, |
| 17661 | // GIR_Coverage, 71415, |
| 17662 | GIR_EraseRootFromParent_Done, |
| 17663 | // Label 1278: @43493 |
| 17664 | GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(43559), // Rule ID 71412 // |
| 17665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17666 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17667 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17668 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17669 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17670 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17671 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17672 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17673 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17674 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17675 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17676 | // (or:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17679 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17683 | GIR_RootConstrainSelectedInstOperands, |
| 17684 | // GIR_Coverage, 71412, |
| 17685 | GIR_EraseRootFromParent_Done, |
| 17686 | // Label 1279: @43559 |
| 17687 | GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(43625), // Rule ID 71413 // |
| 17688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17689 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17690 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17691 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17692 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17693 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17694 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17695 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17696 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17698 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17699 | // (or:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv32i1] }:$rs1) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17702 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17703 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17706 | GIR_RootConstrainSelectedInstOperands, |
| 17707 | // GIR_Coverage, 71413, |
| 17708 | GIR_EraseRootFromParent_Done, |
| 17709 | // Label 1280: @43625 |
| 17710 | GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(43691), // Rule ID 71410 // |
| 17711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17713 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17714 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17715 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17716 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17717 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17718 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17719 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17721 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17722 | // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17725 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17729 | GIR_RootConstrainSelectedInstOperands, |
| 17730 | // GIR_Coverage, 71410, |
| 17731 | GIR_EraseRootFromParent_Done, |
| 17732 | // Label 1281: @43691 |
| 17733 | GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(43757), // Rule ID 71411 // |
| 17734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17735 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17736 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17737 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17738 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17739 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17740 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17741 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17742 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17743 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17744 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17745 | // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17748 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17752 | GIR_RootConstrainSelectedInstOperands, |
| 17753 | // GIR_Coverage, 71411, |
| 17754 | GIR_EraseRootFromParent_Done, |
| 17755 | // Label 1282: @43757 |
| 17756 | GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(43823), // Rule ID 53888 // |
| 17757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17758 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17759 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17760 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17761 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17762 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17763 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17764 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17765 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17766 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17767 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17768 | // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17771 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17775 | GIR_RootConstrainSelectedInstOperands, |
| 17776 | // GIR_Coverage, 53888, |
| 17777 | GIR_EraseRootFromParent_Done, |
| 17778 | // Label 1283: @43823 |
| 17779 | GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(43889), // Rule ID 53889 // |
| 17780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17782 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17783 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17784 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 17785 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 17786 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17787 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17788 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17789 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17790 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17791 | // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M4), |
| 17793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17794 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17798 | GIR_RootConstrainSelectedInstOperands, |
| 17799 | // GIR_Coverage, 53889, |
| 17800 | GIR_EraseRootFromParent_Done, |
| 17801 | // Label 1284: @43889 |
| 17802 | GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(43922), // Rule ID 53876 // |
| 17803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17804 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17806 | // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M4), |
| 17808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17809 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17810 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17813 | GIR_RootConstrainSelectedInstOperands, |
| 17814 | // GIR_Coverage, 53876, |
| 17815 | GIR_EraseRootFromParent_Done, |
| 17816 | // Label 1285: @43922 |
| 17817 | GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(43955), // Rule ID 53877 // |
| 17818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17820 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17821 | // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M4), |
| 17823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17824 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17825 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17828 | GIR_RootConstrainSelectedInstOperands, |
| 17829 | // GIR_Coverage, 53877, |
| 17830 | GIR_EraseRootFromParent_Done, |
| 17831 | // Label 1286: @43955 |
| 17832 | GIM_Reject, |
| 17833 | // Label 1276: @43956 |
| 17834 | GIM_Reject, |
| 17835 | // Label 1136: @43957 |
| 17836 | GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(44071), |
| 17837 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 17838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 17839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17840 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17841 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 17842 | GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(44025), // Rule ID 48456 // |
| 17843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17844 | // (or:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 17845 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 17846 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17847 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 17850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17851 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17852 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17853 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17857 | GIR_RootConstrainSelectedInstOperands, |
| 17858 | // GIR_Coverage, 48456, |
| 17859 | GIR_EraseRootFromParent_Done, |
| 17860 | // Label 1288: @44025 |
| 17861 | GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(44070), // Rule ID 48457 // |
| 17862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17863 | // (or:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVOR_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 17864 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 17865 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17866 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M4), |
| 17869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17870 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17871 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17876 | GIR_RootConstrainSelectedInstOperands, |
| 17877 | // GIR_Coverage, 48457, |
| 17878 | GIR_EraseRootFromParent_Done, |
| 17879 | // Label 1289: @44070 |
| 17880 | GIM_Reject, |
| 17881 | // Label 1287: @44071 |
| 17882 | GIM_Reject, |
| 17883 | // Label 1137: @44072 |
| 17884 | GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(44186), |
| 17885 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 17886 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 17887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 17890 | GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(44140), // Rule ID 48472 // |
| 17891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17892 | // (or:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 17893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 17894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 17898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17900 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17901 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 17904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17905 | GIR_RootConstrainSelectedInstOperands, |
| 17906 | // GIR_Coverage, 48472, |
| 17907 | GIR_EraseRootFromParent_Done, |
| 17908 | // Label 1291: @44140 |
| 17909 | GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(44185), // Rule ID 48473 // |
| 17910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17911 | // (or:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 17912 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 17913 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17914 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 17917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17918 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17919 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 17920 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 17921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 17923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 17924 | GIR_RootConstrainSelectedInstOperands, |
| 17925 | // GIR_Coverage, 48473, |
| 17926 | GIR_EraseRootFromParent_Done, |
| 17927 | // Label 1292: @44185 |
| 17928 | GIM_Reject, |
| 17929 | // Label 1290: @44186 |
| 17930 | GIM_Reject, |
| 17931 | // Label 1138: @44187 |
| 17932 | GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(44797), |
| 17933 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 17934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 17935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17936 | GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(44268), // Rule ID 71442 // |
| 17937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17938 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17939 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17940 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 17941 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 17942 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17943 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17944 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17945 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17946 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17947 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17948 | // (or:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs2), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 17950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17951 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17955 | GIR_RootConstrainSelectedInstOperands, |
| 17956 | // GIR_Coverage, 71442, |
| 17957 | GIR_EraseRootFromParent_Done, |
| 17958 | // Label 1294: @44268 |
| 17959 | GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(44334), // Rule ID 71443 // |
| 17960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 17961 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17962 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17963 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 17964 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 17965 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17966 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17967 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 17968 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17970 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17971 | // (or:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs2), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 17972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 17973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17974 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 17976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 17977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17978 | GIR_RootConstrainSelectedInstOperands, |
| 17979 | // GIR_Coverage, 71443, |
| 17980 | GIR_EraseRootFromParent_Done, |
| 17981 | // Label 1295: @44334 |
| 17982 | GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(44400), // Rule ID 71440 // |
| 17983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 17984 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17985 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 17986 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 17987 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 17988 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17989 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 17990 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 17991 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 17992 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 17993 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 17994 | // (or:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 17995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 17996 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 17997 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 17998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 17999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18001 | GIR_RootConstrainSelectedInstOperands, |
| 18002 | // GIR_Coverage, 71440, |
| 18003 | GIR_EraseRootFromParent_Done, |
| 18004 | // Label 1296: @44400 |
| 18005 | GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(44466), // Rule ID 71441 // |
| 18006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18007 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18008 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18009 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 18010 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 18011 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18012 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 18013 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18014 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18015 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18016 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18017 | // (or:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv64i1] }:$rs1) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 18019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18020 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 18021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18024 | GIR_RootConstrainSelectedInstOperands, |
| 18025 | // GIR_Coverage, 71441, |
| 18026 | GIR_EraseRootFromParent_Done, |
| 18027 | // Label 1297: @44466 |
| 18028 | GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(44532), // Rule ID 71438 // |
| 18029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18031 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18032 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18033 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 18034 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 18035 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 18036 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18037 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18038 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18039 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18040 | // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 18042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18043 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18047 | GIR_RootConstrainSelectedInstOperands, |
| 18048 | // GIR_Coverage, 71438, |
| 18049 | GIR_EraseRootFromParent_Done, |
| 18050 | // Label 1298: @44532 |
| 18051 | GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(44598), // Rule ID 71439 // |
| 18052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18053 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18054 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18055 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18056 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 18057 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 18058 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 18059 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18060 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18061 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18062 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18063 | // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 18065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18066 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18070 | GIR_RootConstrainSelectedInstOperands, |
| 18071 | // GIR_Coverage, 71439, |
| 18072 | GIR_EraseRootFromParent_Done, |
| 18073 | // Label 1299: @44598 |
| 18074 | GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(44664), // Rule ID 53906 // |
| 18075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18076 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18077 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18078 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18079 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 18080 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 18081 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18082 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 18083 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18084 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18085 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18086 | // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }))) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 18088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18089 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18093 | GIR_RootConstrainSelectedInstOperands, |
| 18094 | // GIR_Coverage, 53906, |
| 18095 | GIR_EraseRootFromParent_Done, |
| 18096 | // Label 1300: @44664 |
| 18097 | GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(44730), // Rule ID 53907 // |
| 18098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18099 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18100 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18101 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18102 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 18103 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 18104 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18105 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 18106 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18107 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18108 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18109 | // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }))) => (PseudoVMORN_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMORN_MM_M8), |
| 18111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18112 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18116 | GIR_RootConstrainSelectedInstOperands, |
| 18117 | // GIR_Coverage, 53907, |
| 18118 | GIR_EraseRootFromParent_Done, |
| 18119 | // Label 1301: @44730 |
| 18120 | GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(44763), // Rule ID 53894 // |
| 18121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18122 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18124 | // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M8), |
| 18126 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18127 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18128 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18131 | GIR_RootConstrainSelectedInstOperands, |
| 18132 | // GIR_Coverage, 53894, |
| 18133 | GIR_EraseRootFromParent_Done, |
| 18134 | // Label 1302: @44763 |
| 18135 | GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(44796), // Rule ID 53895 // |
| 18136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18138 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18139 | // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMOR_MM_M8), |
| 18141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18142 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18143 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18146 | GIR_RootConstrainSelectedInstOperands, |
| 18147 | // GIR_Coverage, 53895, |
| 18148 | GIR_EraseRootFromParent_Done, |
| 18149 | // Label 1303: @44796 |
| 18150 | GIM_Reject, |
| 18151 | // Label 1293: @44797 |
| 18152 | GIM_Reject, |
| 18153 | // Label 1139: @44798 |
| 18154 | GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(44912), |
| 18155 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 18156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 18157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 18158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 18159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 18160 | GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(44866), // Rule ID 48460 // |
| 18161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18162 | // (or:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 18163 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 18164 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 18165 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18166 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 18168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18169 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18170 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18171 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 18174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 18175 | GIR_RootConstrainSelectedInstOperands, |
| 18176 | // GIR_Coverage, 48460, |
| 18177 | GIR_EraseRootFromParent_Done, |
| 18178 | // Label 1305: @44866 |
| 18179 | GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(44911), // Rule ID 48461 // |
| 18180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18181 | // (or:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVOR_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 18182 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 18183 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 18184 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVOR_VV_M8), |
| 18187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18188 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18189 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18190 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 18193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 18194 | GIR_RootConstrainSelectedInstOperands, |
| 18195 | // GIR_Coverage, 48461, |
| 18196 | GIR_EraseRootFromParent_Done, |
| 18197 | // Label 1306: @44911 |
| 18198 | GIM_Reject, |
| 18199 | // Label 1304: @44912 |
| 18200 | GIM_Reject, |
| 18201 | // Label 1140: @44913 |
| 18202 | GIM_Reject, |
| 18203 | // Label 9: @44914 |
| 18204 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 1338*/ GIMT_Encode4(60301), |
| 18205 | /*GILLT_s32*//*Label 1307*/ GIMT_Encode4(45049), |
| 18206 | /*GILLT_s64*//*Label 1308*/ GIMT_Encode4(46068), |
| 18207 | /*GILLT_nxv1s1*//*Label 1309*/ GIMT_Encode4(46494), |
| 18208 | /*GILLT_nxv1s8*//*Label 1310*/ GIMT_Encode4(48105), |
| 18209 | /*GILLT_nxv1s16*//*Label 1311*/ GIMT_Encode4(48220), |
| 18210 | /*GILLT_nxv1s32*//*Label 1312*/ GIMT_Encode4(48335), |
| 18211 | /*GILLT_nxv1s64*//*Label 1313*/ GIMT_Encode4(48450), |
| 18212 | /*GILLT_nxv2s1*//*Label 1314*/ GIMT_Encode4(48565), |
| 18213 | /*GILLT_nxv2s8*//*Label 1315*/ GIMT_Encode4(50176), |
| 18214 | /*GILLT_nxv2s16*//*Label 1316*/ GIMT_Encode4(50291), |
| 18215 | /*GILLT_nxv2s32*//*Label 1317*/ GIMT_Encode4(50406), |
| 18216 | /*GILLT_nxv2s64*//*Label 1318*/ GIMT_Encode4(50521), |
| 18217 | /*GILLT_nxv4s1*//*Label 1319*/ GIMT_Encode4(50636), |
| 18218 | /*GILLT_nxv4s8*//*Label 1320*/ GIMT_Encode4(52247), |
| 18219 | /*GILLT_nxv4s16*//*Label 1321*/ GIMT_Encode4(52362), |
| 18220 | /*GILLT_nxv4s32*//*Label 1322*/ GIMT_Encode4(52477), |
| 18221 | /*GILLT_nxv4s64*//*Label 1323*/ GIMT_Encode4(52592), |
| 18222 | /*GILLT_nxv8s1*//*Label 1324*/ GIMT_Encode4(52707), |
| 18223 | /*GILLT_nxv8s8*//*Label 1325*/ GIMT_Encode4(54318), |
| 18224 | /*GILLT_nxv8s16*//*Label 1326*/ GIMT_Encode4(54433), |
| 18225 | /*GILLT_nxv8s32*//*Label 1327*/ GIMT_Encode4(54548), |
| 18226 | /*GILLT_nxv8s64*//*Label 1328*/ GIMT_Encode4(54663), |
| 18227 | /*GILLT_nxv16s1*//*Label 1329*/ GIMT_Encode4(54778), |
| 18228 | /*GILLT_nxv16s8*//*Label 1330*/ GIMT_Encode4(56389), |
| 18229 | /*GILLT_nxv16s16*//*Label 1331*/ GIMT_Encode4(56504), |
| 18230 | /*GILLT_nxv16s32*//*Label 1332*/ GIMT_Encode4(56619), |
| 18231 | /*GILLT_nxv32s1*//*Label 1333*/ GIMT_Encode4(56734), |
| 18232 | /*GILLT_nxv32s8*//*Label 1334*/ GIMT_Encode4(58345), |
| 18233 | /*GILLT_nxv32s16*//*Label 1335*/ GIMT_Encode4(58460), |
| 18234 | /*GILLT_nxv64s1*//*Label 1336*/ GIMT_Encode4(58575), |
| 18235 | /*GILLT_nxv64s8*//*Label 1337*/ GIMT_Encode4(60186), |
| 18236 | // Label 1307: @45049 |
| 18237 | GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(46067), |
| 18238 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 18239 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18241 | GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(45143), // Rule ID 2633 // |
| 18242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 18243 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18244 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18245 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18246 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18247 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 18248 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18249 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18250 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18251 | // (xor:{ *:[i32] } (shl:{ *:[i32] } -1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), -1:{ *:[i32] }) => (ADDI:{ *:[i32] } (BSET:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs2), -1:{ *:[i32] }) |
| 18252 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18253 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 18254 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18255 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18256 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18257 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 18259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18260 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18262 | GIR_RootConstrainSelectedInstOperands, |
| 18263 | // GIR_Coverage, 2633, |
| 18264 | GIR_EraseRootFromParent_Done, |
| 18265 | // Label 1340: @45143 |
| 18266 | GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(45222), // Rule ID 2855 // |
| 18267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 18268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18269 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18271 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18272 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 18273 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18274 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18275 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18276 | // (xor:{ *:[i32] } (shl:{ *:[i32] } -1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i32] }) => (ADDI:{ *:[i32] } (BSET:{ *:[i32] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs2), -1:{ *:[i64] }) |
| 18277 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18278 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 18279 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18280 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18281 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18282 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 18284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18285 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18287 | GIR_RootConstrainSelectedInstOperands, |
| 18288 | // GIR_Coverage, 2855, |
| 18289 | GIR_EraseRootFromParent_Done, |
| 18290 | // Label 1341: @45222 |
| 18291 | GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(45277), // Rule ID 2627 // |
| 18292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 18293 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18294 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18295 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18296 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18297 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 18298 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18299 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18300 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18301 | // (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), GPR:{ *:[i32] }:$rs1) => (BINV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BINV), |
| 18303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18304 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 18305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18306 | GIR_RootConstrainSelectedInstOperands, |
| 18307 | // GIR_Coverage, 2627, |
| 18308 | GIR_EraseRootFromParent_Done, |
| 18309 | // Label 1342: @45277 |
| 18310 | GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(45332), // Rule ID 2851 // |
| 18311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 18312 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18313 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18314 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18315 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18316 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 18317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18318 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18319 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18320 | // (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), GPR:{ *:[i32] }:$rs1) => (BINV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BINV), |
| 18322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18323 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 18324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18325 | GIR_RootConstrainSelectedInstOperands, |
| 18326 | // GIR_Coverage, 2851, |
| 18327 | GIR_EraseRootFromParent_Done, |
| 18328 | // Label 1343: @45332 |
| 18329 | GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(45387), // Rule ID 65206 // |
| 18330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 18331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18335 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18336 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 18337 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18338 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18339 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2))) => (BINV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BINV), |
| 18341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18342 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18344 | GIR_RootConstrainSelectedInstOperands, |
| 18345 | // GIR_Coverage, 65206, |
| 18346 | GIR_EraseRootFromParent_Done, |
| 18347 | // Label 1344: @45387 |
| 18348 | GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(45442), // Rule ID 65307 // |
| 18349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 18350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18351 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18352 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18353 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18354 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18355 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 18356 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18357 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18358 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2))) => (BINV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BINV), |
| 18360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18361 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18363 | GIR_RootConstrainSelectedInstOperands, |
| 18364 | // GIR_Coverage, 65307, |
| 18365 | GIR_EraseRootFromParent_Done, |
| 18366 | // Label 1345: @45442 |
| 18367 | GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(45494), // Rule ID 65198 // |
| 18368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 18369 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18370 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18371 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18372 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18373 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18374 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18376 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18377 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs2) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18381 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18382 | GIR_RootConstrainSelectedInstOperands, |
| 18383 | // GIR_Coverage, 65198, |
| 18384 | GIR_EraseRootFromParent_Done, |
| 18385 | // Label 1346: @45494 |
| 18386 | GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(45546), // Rule ID 65281 // |
| 18387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 18388 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18389 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18390 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18391 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18392 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18393 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18395 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18396 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs2) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18400 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18401 | GIR_RootConstrainSelectedInstOperands, |
| 18402 | // GIR_Coverage, 65281, |
| 18403 | GIR_EraseRootFromParent_Done, |
| 18404 | // Label 1347: @45546 |
| 18405 | GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(45598), // Rule ID 65282 // |
| 18406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 18407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18408 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18410 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18411 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18412 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18414 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18415 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs2) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18419 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18420 | GIR_RootConstrainSelectedInstOperands, |
| 18421 | // GIR_Coverage, 65282, |
| 18422 | GIR_EraseRootFromParent_Done, |
| 18423 | // Label 1348: @45598 |
| 18424 | GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(45653), // Rule ID 65196 // |
| 18425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 18426 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18427 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18428 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18429 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18430 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18431 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18432 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18433 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18434 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), -1:{ *:[i32] }) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18439 | GIR_RootConstrainSelectedInstOperands, |
| 18440 | // GIR_Coverage, 65196, |
| 18441 | GIR_EraseRootFromParent_Done, |
| 18442 | // Label 1349: @45653 |
| 18443 | GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(45708), // Rule ID 65279 // |
| 18444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 18445 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18446 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18447 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18448 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18449 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18450 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18451 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18452 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18453 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), -1:{ *:[i32] }) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18458 | GIR_RootConstrainSelectedInstOperands, |
| 18459 | // GIR_Coverage, 65279, |
| 18460 | GIR_EraseRootFromParent_Done, |
| 18461 | // Label 1350: @45708 |
| 18462 | GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(45763), // Rule ID 65280 // |
| 18463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 18464 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18465 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18466 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18467 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18468 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18469 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18470 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18471 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18472 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), -1:{ *:[i32] }) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18477 | GIR_RootConstrainSelectedInstOperands, |
| 18478 | // GIR_Coverage, 65280, |
| 18479 | GIR_EraseRootFromParent_Done, |
| 18480 | // Label 1351: @45763 |
| 18481 | GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(45815), // Rule ID 2607 // |
| 18482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 18483 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18484 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18485 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18486 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18487 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18488 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18489 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18490 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18491 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18494 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18496 | GIR_RootConstrainSelectedInstOperands, |
| 18497 | // GIR_Coverage, 2607, |
| 18498 | GIR_EraseRootFromParent_Done, |
| 18499 | // Label 1352: @45815 |
| 18500 | GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(45867), // Rule ID 2811 // |
| 18501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 18502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18503 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18504 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18505 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18506 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18507 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18508 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18509 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18510 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18513 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18515 | GIR_RootConstrainSelectedInstOperands, |
| 18516 | // GIR_Coverage, 2811, |
| 18517 | GIR_EraseRootFromParent_Done, |
| 18518 | // Label 1353: @45867 |
| 18519 | GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(45919), // Rule ID 2812 // |
| 18520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 18521 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18522 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18523 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18524 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 18525 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18526 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18527 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18528 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18529 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18532 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18534 | GIR_RootConstrainSelectedInstOperands, |
| 18535 | // GIR_Coverage, 2812, |
| 18536 | GIR_EraseRootFromParent_Done, |
| 18537 | // Label 1354: @45919 |
| 18538 | GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(45957), // Rule ID 83 // |
| 18539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 18540 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18542 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18543 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 18544 | // MIs[1] Operand 1 |
| 18545 | // No operand predicates |
| 18546 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18547 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) => (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) |
| 18548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 18549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18550 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18551 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18552 | GIR_RootConstrainSelectedInstOperands, |
| 18553 | // GIR_Coverage, 83, |
| 18554 | GIR_EraseRootFromParent_Done, |
| 18555 | // Label 1355: @45957 |
| 18556 | GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(45997), // Rule ID 313 // |
| 18557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 18558 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18559 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18560 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18561 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12i32), |
| 18562 | // MIs[1] Operand 1 |
| 18563 | // No operand predicates |
| 18564 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18565 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12i32>>:$imm) => (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (as_i64imm:{ *:[i64] } ?:{ *:[i32] }:$imm)) |
| 18566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 18567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18568 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18569 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm |
| 18570 | GIR_RootConstrainSelectedInstOperands, |
| 18571 | // GIR_Coverage, 313, |
| 18572 | GIR_EraseRootFromParent_Done, |
| 18573 | // Label 1356: @45997 |
| 18574 | GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(46020), // Rule ID 81 // |
| 18575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 18576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18578 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18579 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 18580 | GIR_RootConstrainSelectedInstOperands, |
| 18581 | // GIR_Coverage, 81, |
| 18582 | GIR_Done, |
| 18583 | // Label 1357: @46020 |
| 18584 | GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(46043), // Rule ID 305 // |
| 18585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 18586 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18588 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18589 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 18590 | GIR_RootConstrainSelectedInstOperands, |
| 18591 | // GIR_Coverage, 305, |
| 18592 | GIR_Done, |
| 18593 | // Label 1358: @46043 |
| 18594 | GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(46066), // Rule ID 306 // |
| 18595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 18596 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18597 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18598 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 18599 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 18600 | GIR_RootConstrainSelectedInstOperands, |
| 18601 | // GIR_Coverage, 306, |
| 18602 | GIR_Done, |
| 18603 | // Label 1359: @46066 |
| 18604 | GIM_Reject, |
| 18605 | // Label 1339: @46067 |
| 18606 | GIM_Reject, |
| 18607 | // Label 1308: @46068 |
| 18608 | GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(46493), |
| 18609 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 18610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 18611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18612 | GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(46162), // Rule ID 2632 // |
| 18613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 18614 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18615 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18616 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 18617 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18618 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 18619 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18620 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18621 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18622 | // (xor:{ *:[i64] } (shl:{ *:[i64] } -1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i64] }) => (ADDI:{ *:[i64] } (BSET:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs2), -1:{ *:[i64] }) |
| 18623 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18624 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 18625 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18626 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18627 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 18630 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18631 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18633 | GIR_RootConstrainSelectedInstOperands, |
| 18634 | // GIR_Coverage, 2632, |
| 18635 | GIR_EraseRootFromParent_Done, |
| 18636 | // Label 1361: @46162 |
| 18637 | GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(46217), // Rule ID 2626 // |
| 18638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 18639 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18640 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18641 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 18642 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18643 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 18644 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18645 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18646 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18647 | // (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), GPR:{ *:[i64] }:$rs1) => (BINV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BINV), |
| 18649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18650 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 18651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18652 | GIR_RootConstrainSelectedInstOperands, |
| 18653 | // GIR_Coverage, 2626, |
| 18654 | GIR_EraseRootFromParent_Done, |
| 18655 | // Label 1362: @46217 |
| 18656 | GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(46272), // Rule ID 65205 // |
| 18657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 18658 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18659 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18660 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 18661 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 18662 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18663 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1, |
| 18664 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18665 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 18666 | // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2))) => (BINV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BINV), |
| 18668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18669 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 18671 | GIR_RootConstrainSelectedInstOperands, |
| 18672 | // GIR_Coverage, 65205, |
| 18673 | GIR_EraseRootFromParent_Done, |
| 18674 | // Label 1363: @46272 |
| 18675 | GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(46324), // Rule ID 65197 // |
| 18676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 18677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 18680 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18681 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18682 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18684 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18685 | // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) => (XNOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18689 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18690 | GIR_RootConstrainSelectedInstOperands, |
| 18691 | // GIR_Coverage, 65197, |
| 18692 | GIR_EraseRootFromParent_Done, |
| 18693 | // Label 1364: @46324 |
| 18694 | GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(46379), // Rule ID 65195 // |
| 18695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 18696 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18697 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18698 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 18699 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18700 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18701 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18702 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 18703 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18704 | // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), -1:{ *:[i64] }) => (XNOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18709 | GIR_RootConstrainSelectedInstOperands, |
| 18710 | // GIR_Coverage, 65195, |
| 18711 | GIR_EraseRootFromParent_Done, |
| 18712 | // Label 1365: @46379 |
| 18713 | GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(46431), // Rule ID 2606 // |
| 18714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 18715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 18719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18721 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 18722 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18723 | // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] })) => (XNOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XNOR), |
| 18725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18726 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 18728 | GIR_RootConstrainSelectedInstOperands, |
| 18729 | // GIR_Coverage, 2606, |
| 18730 | GIR_EraseRootFromParent_Done, |
| 18731 | // Label 1366: @46431 |
| 18732 | GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(46469), // Rule ID 82 // |
| 18733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 18734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18735 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18736 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 18737 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 18738 | // MIs[1] Operand 1 |
| 18739 | // No operand predicates |
| 18740 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 18741 | // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) => (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) |
| 18742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 18743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18744 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 18745 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 18746 | GIR_RootConstrainSelectedInstOperands, |
| 18747 | // GIR_Coverage, 82, |
| 18748 | GIR_EraseRootFromParent_Done, |
| 18749 | // Label 1367: @46469 |
| 18750 | GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(46492), // Rule ID 80 // |
| 18751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 18752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 18754 | // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 18755 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 18756 | GIR_RootConstrainSelectedInstOperands, |
| 18757 | // GIR_Coverage, 80, |
| 18758 | GIR_Done, |
| 18759 | // Label 1368: @46492 |
| 18760 | GIM_Reject, |
| 18761 | // Label 1360: @46493 |
| 18762 | GIM_Reject, |
| 18763 | // Label 1309: @46494 |
| 18764 | GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(48104), |
| 18765 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18766 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18768 | GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(46578), // Rule ID 53790 // |
| 18769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18770 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18771 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 18772 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18773 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18774 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18775 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18776 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 18777 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18778 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18779 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18780 | // (xor:{ *:[nxv1i1] } (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18781 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 18782 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18783 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18784 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18787 | GIR_RootConstrainSelectedInstOperands, |
| 18788 | // GIR_Coverage, 53790, |
| 18789 | GIR_EraseRootFromParent_Done, |
| 18790 | // Label 1370: @46578 |
| 18791 | GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(46647), // Rule ID 53791 // |
| 18792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 18795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18796 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18797 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18798 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18799 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 18800 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18801 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18802 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18803 | // (xor:{ *:[nxv1i1] } (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 18805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18810 | GIR_RootConstrainSelectedInstOperands, |
| 18811 | // GIR_Coverage, 53791, |
| 18812 | GIR_EraseRootFromParent_Done, |
| 18813 | // Label 1371: @46647 |
| 18814 | GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(46716), // Rule ID 53792 // |
| 18815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18816 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18817 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 18818 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18819 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18820 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18821 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18822 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 18823 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18824 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18825 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18826 | // (xor:{ *:[nxv1i1] } (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF8), |
| 18828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18833 | GIR_RootConstrainSelectedInstOperands, |
| 18834 | // GIR_Coverage, 53792, |
| 18835 | GIR_EraseRootFromParent_Done, |
| 18836 | // Label 1372: @46716 |
| 18837 | GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(46785), // Rule ID 53793 // |
| 18838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18839 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18840 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 18841 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18842 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18843 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18844 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18845 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 18846 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18847 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18848 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18849 | // (xor:{ *:[nxv1i1] } (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF8), |
| 18851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18856 | GIR_RootConstrainSelectedInstOperands, |
| 18857 | // GIR_Coverage, 53793, |
| 18858 | GIR_EraseRootFromParent_Done, |
| 18859 | // Label 1373: @46785 |
| 18860 | GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(46851), // Rule ID 71256 // |
| 18861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18862 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18863 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18864 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18865 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18866 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 18867 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18868 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18869 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18870 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18871 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18872 | // (xor:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs1), VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 18874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 18876 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18879 | GIR_RootConstrainSelectedInstOperands, |
| 18880 | // GIR_Coverage, 71256, |
| 18881 | GIR_EraseRootFromParent_Done, |
| 18882 | // Label 1374: @46851 |
| 18883 | GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(46917), // Rule ID 71257 // |
| 18884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18885 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18886 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18887 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18888 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18889 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 18890 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18891 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18892 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18893 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18894 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18895 | // (xor:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs1), VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 18897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 18899 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18902 | GIR_RootConstrainSelectedInstOperands, |
| 18903 | // GIR_Coverage, 71257, |
| 18904 | GIR_EraseRootFromParent_Done, |
| 18905 | // Label 1375: @46917 |
| 18906 | GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(46983), // Rule ID 71254 // |
| 18907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18909 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18911 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18912 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18913 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 18914 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18915 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18916 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18917 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18918 | // (xor:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 18920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18922 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18925 | GIR_RootConstrainSelectedInstOperands, |
| 18926 | // GIR_Coverage, 71254, |
| 18927 | GIR_EraseRootFromParent_Done, |
| 18928 | // Label 1376: @46983 |
| 18929 | GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(47049), // Rule ID 71255 // |
| 18930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18932 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18934 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18935 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18936 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 18937 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18938 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18940 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18941 | // (xor:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 18943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18945 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 18946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18948 | GIR_RootConstrainSelectedInstOperands, |
| 18949 | // GIR_Coverage, 71255, |
| 18950 | GIR_EraseRootFromParent_Done, |
| 18951 | // Label 1377: @47049 |
| 18952 | GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(47118), // Rule ID 53794 // |
| 18953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 18954 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18955 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18956 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18957 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18958 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18959 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18960 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 18961 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18962 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 18963 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18964 | // (xor:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 18965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 18966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18971 | GIR_RootConstrainSelectedInstOperands, |
| 18972 | // GIR_Coverage, 53794, |
| 18973 | GIR_EraseRootFromParent_Done, |
| 18974 | // Label 1378: @47118 |
| 18975 | GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(47187), // Rule ID 53795 // |
| 18976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 18977 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18978 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 18979 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 18980 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 18981 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18982 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 18983 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 18984 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 18985 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 18986 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 18987 | // (xor:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 18988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 18989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 18990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 18991 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 18992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 18993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18994 | GIR_RootConstrainSelectedInstOperands, |
| 18995 | // GIR_Coverage, 53795, |
| 18996 | GIR_EraseRootFromParent_Done, |
| 18997 | // Label 1379: @47187 |
| 18998 | GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(47256), // Rule ID 71250 // |
| 18999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19000 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19001 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19002 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19003 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19004 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 19005 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19006 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19007 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19008 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19009 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19010 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 19012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19017 | GIR_RootConstrainSelectedInstOperands, |
| 19018 | // GIR_Coverage, 71250, |
| 19019 | GIR_EraseRootFromParent_Done, |
| 19020 | // Label 1380: @47256 |
| 19021 | GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(47325), // Rule ID 71251 // |
| 19022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19023 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19024 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19025 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19026 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19027 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 19028 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19029 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19030 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19031 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19032 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19033 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 19035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19040 | GIR_RootConstrainSelectedInstOperands, |
| 19041 | // GIR_Coverage, 71251, |
| 19042 | GIR_EraseRootFromParent_Done, |
| 19043 | // Label 1381: @47325 |
| 19044 | GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(47394), // Rule ID 71252 // |
| 19045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19046 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19047 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19048 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19049 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19050 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 19051 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19052 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19053 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19054 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19055 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19056 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF8), |
| 19058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19063 | GIR_RootConstrainSelectedInstOperands, |
| 19064 | // GIR_Coverage, 71252, |
| 19065 | GIR_EraseRootFromParent_Done, |
| 19066 | // Label 1382: @47394 |
| 19067 | GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(47463), // Rule ID 71253 // |
| 19068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19069 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19070 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19071 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19072 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19073 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 19074 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19075 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19076 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19077 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19078 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19079 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF8), |
| 19081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19086 | GIR_RootConstrainSelectedInstOperands, |
| 19087 | // GIR_Coverage, 71253, |
| 19088 | GIR_EraseRootFromParent_Done, |
| 19089 | // Label 1383: @47463 |
| 19090 | GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(47532), // Rule ID 71258 // |
| 19091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19092 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19093 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19094 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19095 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19096 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19097 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19098 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19099 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19100 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19101 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19102 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 19104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19109 | GIR_RootConstrainSelectedInstOperands, |
| 19110 | // GIR_Coverage, 71258, |
| 19111 | GIR_EraseRootFromParent_Done, |
| 19112 | // Label 1384: @47532 |
| 19113 | GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(47601), // Rule ID 71259 // |
| 19114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19115 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19116 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19117 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19118 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19119 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19120 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19121 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19122 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19123 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19124 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19125 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 19127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19132 | GIR_RootConstrainSelectedInstOperands, |
| 19133 | // GIR_Coverage, 71259, |
| 19134 | GIR_EraseRootFromParent_Done, |
| 19135 | // Label 1385: @47601 |
| 19136 | GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(47667), // Rule ID 71262 // |
| 19137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19138 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19140 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19141 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19142 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19143 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 19144 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19145 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19146 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19147 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19148 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs1)) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 19150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 19152 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19155 | GIR_RootConstrainSelectedInstOperands, |
| 19156 | // GIR_Coverage, 71262, |
| 19157 | GIR_EraseRootFromParent_Done, |
| 19158 | // Label 1386: @47667 |
| 19159 | GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(47733), // Rule ID 71263 // |
| 19160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19161 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19163 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19164 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19165 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19166 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 19167 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19168 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19169 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19170 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19171 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs1)) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 19173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 19175 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19178 | GIR_RootConstrainSelectedInstOperands, |
| 19179 | // GIR_Coverage, 71263, |
| 19180 | GIR_EraseRootFromParent_Done, |
| 19181 | // Label 1387: @47733 |
| 19182 | GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(47799), // Rule ID 71260 // |
| 19183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19185 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19186 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19187 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19188 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19189 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19190 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 19191 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19192 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19193 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19194 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 19196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19198 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19201 | GIR_RootConstrainSelectedInstOperands, |
| 19202 | // GIR_Coverage, 71260, |
| 19203 | GIR_EraseRootFromParent_Done, |
| 19204 | // Label 1388: @47799 |
| 19205 | GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(47865), // Rule ID 71261 // |
| 19206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19207 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19209 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19210 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 19211 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, |
| 19212 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19213 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 19214 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19215 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19216 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19217 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF8), |
| 19219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19221 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19224 | GIR_RootConstrainSelectedInstOperands, |
| 19225 | // GIR_Coverage, 71261, |
| 19226 | GIR_EraseRootFromParent_Done, |
| 19227 | // Label 1389: @47865 |
| 19228 | GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(47908), // Rule ID 71276 // |
| 19229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19230 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19231 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19232 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19234 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 19235 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs, VR:{ *:[nxv1i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 19237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19238 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 19239 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 19240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19242 | GIR_RootConstrainSelectedInstOperands, |
| 19243 | // GIR_Coverage, 71276, |
| 19244 | GIR_EraseRootFromParent_Done, |
| 19245 | // Label 1390: @47908 |
| 19246 | GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(47951), // Rule ID 71277 // |
| 19247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19248 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19249 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19250 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19251 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19252 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 19253 | // (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs, VR:{ *:[nxv1i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 19255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19256 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 19257 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 19258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19260 | GIR_RootConstrainSelectedInstOperands, |
| 19261 | // GIR_Coverage, 71277, |
| 19262 | GIR_EraseRootFromParent_Done, |
| 19263 | // Label 1391: @47951 |
| 19264 | GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(47994), // Rule ID 53800 // |
| 19265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19266 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19267 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19268 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19269 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19270 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 19271 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs, VR:{ *:[nxv1i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 19273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19274 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 19275 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 19276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19278 | GIR_RootConstrainSelectedInstOperands, |
| 19279 | // GIR_Coverage, 53800, |
| 19280 | GIR_EraseRootFromParent_Done, |
| 19281 | // Label 1392: @47994 |
| 19282 | GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(48037), // Rule ID 53801 // |
| 19283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19284 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19288 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 19289 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs, VR:{ *:[nxv1i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF8), |
| 19291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19292 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 19293 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 19294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19296 | GIR_RootConstrainSelectedInstOperands, |
| 19297 | // GIR_Coverage, 53801, |
| 19298 | GIR_EraseRootFromParent_Done, |
| 19299 | // Label 1393: @48037 |
| 19300 | GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(48070), // Rule ID 53788 // |
| 19301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19303 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19304 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMXOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_MF8), |
| 19306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19307 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19308 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19311 | GIR_RootConstrainSelectedInstOperands, |
| 19312 | // GIR_Coverage, 53788, |
| 19313 | GIR_EraseRootFromParent_Done, |
| 19314 | // Label 1394: @48070 |
| 19315 | GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(48103), // Rule ID 53789 // |
| 19316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19319 | // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMXOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_MF8), |
| 19321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19322 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19323 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19326 | GIR_RootConstrainSelectedInstOperands, |
| 19327 | // GIR_Coverage, 53789, |
| 19328 | GIR_EraseRootFromParent_Done, |
| 19329 | // Label 1395: @48103 |
| 19330 | GIM_Reject, |
| 19331 | // Label 1369: @48104 |
| 19332 | GIM_Reject, |
| 19333 | // Label 1310: @48105 |
| 19334 | GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(48219), |
| 19335 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 19336 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 19337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19338 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19340 | GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(48173), // Rule ID 48544 // |
| 19341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19342 | // (xor:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVXOR_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 19343 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 19344 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19345 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19346 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF8), |
| 19348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19350 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19351 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19355 | GIR_RootConstrainSelectedInstOperands, |
| 19356 | // GIR_Coverage, 48544, |
| 19357 | GIR_EraseRootFromParent_Done, |
| 19358 | // Label 1397: @48173 |
| 19359 | GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(48218), // Rule ID 48545 // |
| 19360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19361 | // (xor:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVXOR_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 19362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 19363 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19364 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF8), |
| 19367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19368 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19369 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19374 | GIR_RootConstrainSelectedInstOperands, |
| 19375 | // GIR_Coverage, 48545, |
| 19376 | GIR_EraseRootFromParent_Done, |
| 19377 | // Label 1398: @48218 |
| 19378 | GIM_Reject, |
| 19379 | // Label 1396: @48219 |
| 19380 | GIM_Reject, |
| 19381 | // Label 1311: @48220 |
| 19382 | GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(48334), |
| 19383 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 19384 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 19385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19386 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19387 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19388 | GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(48288), // Rule ID 48556 // |
| 19389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19390 | // (xor:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVXOR_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 19391 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 19392 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19393 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19394 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF4), |
| 19396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19397 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19398 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19399 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 19402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19403 | GIR_RootConstrainSelectedInstOperands, |
| 19404 | // GIR_Coverage, 48556, |
| 19405 | GIR_EraseRootFromParent_Done, |
| 19406 | // Label 1400: @48288 |
| 19407 | GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(48333), // Rule ID 48557 // |
| 19408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19409 | // (xor:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVXOR_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 19410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 19411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF4), |
| 19415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19416 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19417 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19418 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 19421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19422 | GIR_RootConstrainSelectedInstOperands, |
| 19423 | // GIR_Coverage, 48557, |
| 19424 | GIR_EraseRootFromParent_Done, |
| 19425 | // Label 1401: @48333 |
| 19426 | GIM_Reject, |
| 19427 | // Label 1399: @48334 |
| 19428 | GIM_Reject, |
| 19429 | // Label 1312: @48335 |
| 19430 | GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(48449), |
| 19431 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 19432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 19433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19435 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19436 | GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(48403), // Rule ID 48564 // |
| 19437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19438 | // (xor:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVXOR_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 19439 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 19440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19441 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF2), |
| 19444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19445 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19446 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19447 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 19450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19451 | GIR_RootConstrainSelectedInstOperands, |
| 19452 | // GIR_Coverage, 48564, |
| 19453 | GIR_EraseRootFromParent_Done, |
| 19454 | // Label 1403: @48403 |
| 19455 | GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(48448), // Rule ID 48565 // |
| 19456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19457 | // (xor:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVXOR_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 19458 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 19459 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19460 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF2), |
| 19463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19464 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19465 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 19469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19470 | GIR_RootConstrainSelectedInstOperands, |
| 19471 | // GIR_Coverage, 48565, |
| 19472 | GIR_EraseRootFromParent_Done, |
| 19473 | // Label 1404: @48448 |
| 19474 | GIM_Reject, |
| 19475 | // Label 1402: @48449 |
| 19476 | GIM_Reject, |
| 19477 | // Label 1313: @48450 |
| 19478 | GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(48564), |
| 19479 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 19480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 19481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19484 | GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(48518), // Rule ID 48580 // |
| 19485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 19486 | // (xor:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 19487 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 19488 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19489 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 19492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19493 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19494 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19495 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 19498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19499 | GIR_RootConstrainSelectedInstOperands, |
| 19500 | // GIR_Coverage, 48580, |
| 19501 | GIR_EraseRootFromParent_Done, |
| 19502 | // Label 1406: @48518 |
| 19503 | GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(48563), // Rule ID 48581 // |
| 19504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 19505 | // (xor:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 19506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 19507 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 19508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 19511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19513 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 19514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 19517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 19518 | GIR_RootConstrainSelectedInstOperands, |
| 19519 | // GIR_Coverage, 48581, |
| 19520 | GIR_EraseRootFromParent_Done, |
| 19521 | // Label 1407: @48563 |
| 19522 | GIM_Reject, |
| 19523 | // Label 1405: @48564 |
| 19524 | GIM_Reject, |
| 19525 | // Label 1314: @48565 |
| 19526 | GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(50175), |
| 19527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19528 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19530 | GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(48649), // Rule ID 53808 // |
| 19531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19532 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19533 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 19534 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19535 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19536 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19537 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19538 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19539 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19540 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19541 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19542 | // (xor:{ *:[nxv2i1] } (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 19544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 19547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19549 | GIR_RootConstrainSelectedInstOperands, |
| 19550 | // GIR_Coverage, 53808, |
| 19551 | GIR_EraseRootFromParent_Done, |
| 19552 | // Label 1409: @48649 |
| 19553 | GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(48718), // Rule ID 53809 // |
| 19554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19555 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19556 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 19557 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19558 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19559 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19560 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19561 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19562 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19563 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19564 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19565 | // (xor:{ *:[nxv2i1] } (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 19567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 19570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19572 | GIR_RootConstrainSelectedInstOperands, |
| 19573 | // GIR_Coverage, 53809, |
| 19574 | GIR_EraseRootFromParent_Done, |
| 19575 | // Label 1410: @48718 |
| 19576 | GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(48787), // Rule ID 53810 // |
| 19577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19578 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19579 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 19580 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19581 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19582 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19583 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19584 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19585 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19586 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19587 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19588 | // (xor:{ *:[nxv2i1] } (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF4), |
| 19590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19592 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 19593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19595 | GIR_RootConstrainSelectedInstOperands, |
| 19596 | // GIR_Coverage, 53810, |
| 19597 | GIR_EraseRootFromParent_Done, |
| 19598 | // Label 1411: @48787 |
| 19599 | GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(48856), // Rule ID 53811 // |
| 19600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19601 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19602 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 19603 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19604 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19606 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19607 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19608 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19609 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19610 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19611 | // (xor:{ *:[nxv2i1] } (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF4), |
| 19613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 19616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19618 | GIR_RootConstrainSelectedInstOperands, |
| 19619 | // GIR_Coverage, 53811, |
| 19620 | GIR_EraseRootFromParent_Done, |
| 19621 | // Label 1412: @48856 |
| 19622 | GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(48922), // Rule ID 71284 // |
| 19623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19624 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19625 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19626 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19627 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19628 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 19629 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19630 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19631 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19632 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19633 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19634 | // (xor:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs1), VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 19638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19641 | GIR_RootConstrainSelectedInstOperands, |
| 19642 | // GIR_Coverage, 71284, |
| 19643 | GIR_EraseRootFromParent_Done, |
| 19644 | // Label 1413: @48922 |
| 19645 | GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(48988), // Rule ID 71285 // |
| 19646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19647 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19648 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19649 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19650 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19651 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 19652 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19653 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19654 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19656 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19657 | // (xor:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs1), VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 19661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19664 | GIR_RootConstrainSelectedInstOperands, |
| 19665 | // GIR_Coverage, 71285, |
| 19666 | GIR_EraseRootFromParent_Done, |
| 19667 | // Label 1414: @48988 |
| 19668 | GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(49054), // Rule ID 71282 // |
| 19669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19670 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19671 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19672 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19673 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19674 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 19676 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19678 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19679 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19680 | // (xor:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19684 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19687 | GIR_RootConstrainSelectedInstOperands, |
| 19688 | // GIR_Coverage, 71282, |
| 19689 | GIR_EraseRootFromParent_Done, |
| 19690 | // Label 1415: @49054 |
| 19691 | GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(49120), // Rule ID 71283 // |
| 19692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19697 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19698 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 19699 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19700 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19702 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19703 | // (xor:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19707 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 19708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19710 | GIR_RootConstrainSelectedInstOperands, |
| 19711 | // GIR_Coverage, 71283, |
| 19712 | GIR_EraseRootFromParent_Done, |
| 19713 | // Label 1416: @49120 |
| 19714 | GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(49189), // Rule ID 53812 // |
| 19715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19721 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19722 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19723 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19724 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19725 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19726 | // (xor:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 19731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19733 | GIR_RootConstrainSelectedInstOperands, |
| 19734 | // GIR_Coverage, 53812, |
| 19735 | GIR_EraseRootFromParent_Done, |
| 19736 | // Label 1417: @49189 |
| 19737 | GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(49258), // Rule ID 53813 // |
| 19738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19740 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19741 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19742 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19743 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19745 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19746 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19747 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19748 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19749 | // (xor:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 19754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19756 | GIR_RootConstrainSelectedInstOperands, |
| 19757 | // GIR_Coverage, 53813, |
| 19758 | GIR_EraseRootFromParent_Done, |
| 19759 | // Label 1418: @49258 |
| 19760 | GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(49327), // Rule ID 71278 // |
| 19761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19763 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19765 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19766 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 19767 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19768 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19769 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19770 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19771 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19772 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 19774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19776 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19779 | GIR_RootConstrainSelectedInstOperands, |
| 19780 | // GIR_Coverage, 71278, |
| 19781 | GIR_EraseRootFromParent_Done, |
| 19782 | // Label 1419: @49327 |
| 19783 | GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(49396), // Rule ID 71279 // |
| 19784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19785 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19786 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19787 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19788 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19789 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 19790 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19791 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19792 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19793 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19794 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19795 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 19797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19802 | GIR_RootConstrainSelectedInstOperands, |
| 19803 | // GIR_Coverage, 71279, |
| 19804 | GIR_EraseRootFromParent_Done, |
| 19805 | // Label 1420: @49396 |
| 19806 | GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(49465), // Rule ID 71280 // |
| 19807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19808 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19809 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19810 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19811 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19812 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 19813 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19814 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19815 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19816 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19817 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19818 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF4), |
| 19820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19825 | GIR_RootConstrainSelectedInstOperands, |
| 19826 | // GIR_Coverage, 71280, |
| 19827 | GIR_EraseRootFromParent_Done, |
| 19828 | // Label 1421: @49465 |
| 19829 | GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(49534), // Rule ID 71281 // |
| 19830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19831 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19832 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19833 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19834 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19835 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 19836 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19837 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19838 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19839 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19840 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19841 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF4), |
| 19843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19848 | GIR_RootConstrainSelectedInstOperands, |
| 19849 | // GIR_Coverage, 71281, |
| 19850 | GIR_EraseRootFromParent_Done, |
| 19851 | // Label 1422: @49534 |
| 19852 | GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(49603), // Rule ID 71286 // |
| 19853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19854 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19855 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19856 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19857 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19858 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19859 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19860 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19861 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19862 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19863 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19864 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19871 | GIR_RootConstrainSelectedInstOperands, |
| 19872 | // GIR_Coverage, 71286, |
| 19873 | GIR_EraseRootFromParent_Done, |
| 19874 | // Label 1423: @49603 |
| 19875 | GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(49672), // Rule ID 71287 // |
| 19876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19877 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19878 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19879 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 19880 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 19881 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19882 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19883 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19884 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19885 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19886 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19887 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 19891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 19892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19894 | GIR_RootConstrainSelectedInstOperands, |
| 19895 | // GIR_Coverage, 71287, |
| 19896 | GIR_EraseRootFromParent_Done, |
| 19897 | // Label 1424: @49672 |
| 19898 | GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(49738), // Rule ID 71290 // |
| 19899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19901 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19902 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19903 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19904 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19905 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 19906 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19907 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19908 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19909 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19910 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs1)) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 19914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19917 | GIR_RootConstrainSelectedInstOperands, |
| 19918 | // GIR_Coverage, 71290, |
| 19919 | GIR_EraseRootFromParent_Done, |
| 19920 | // Label 1425: @49738 |
| 19921 | GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(49804), // Rule ID 71291 // |
| 19922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19924 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19925 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19926 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19927 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19928 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 19929 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19930 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19931 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19932 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19933 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs1)) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 19937 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19940 | GIR_RootConstrainSelectedInstOperands, |
| 19941 | // GIR_Coverage, 71291, |
| 19942 | GIR_EraseRootFromParent_Done, |
| 19943 | // Label 1426: @49804 |
| 19944 | GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(49870), // Rule ID 71288 // |
| 19945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19948 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19949 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19950 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19951 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19952 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 19953 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19954 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 19955 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19956 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19960 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19963 | GIR_RootConstrainSelectedInstOperands, |
| 19964 | // GIR_Coverage, 71288, |
| 19965 | GIR_EraseRootFromParent_Done, |
| 19966 | // Label 1427: @49870 |
| 19967 | GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(49936), // Rule ID 71289 // |
| 19968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 19969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19970 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 19971 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 19972 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 19973 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, |
| 19974 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19975 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 19976 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19977 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 19978 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 19979 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 19980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF4), |
| 19981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 19982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 19983 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 19984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 19985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19986 | GIR_RootConstrainSelectedInstOperands, |
| 19987 | // GIR_Coverage, 71289, |
| 19988 | GIR_EraseRootFromParent_Done, |
| 19989 | // Label 1428: @49936 |
| 19990 | GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(49979), // Rule ID 71304 // |
| 19991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 19992 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19993 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 19994 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 19995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 19996 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 19997 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs, VR:{ *:[nxv2i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 19998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 19999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20000 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20001 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20004 | GIR_RootConstrainSelectedInstOperands, |
| 20005 | // GIR_Coverage, 71304, |
| 20006 | GIR_EraseRootFromParent_Done, |
| 20007 | // Label 1429: @49979 |
| 20008 | GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(50022), // Rule ID 71305 // |
| 20009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20011 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20012 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20014 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20015 | // (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs, VR:{ *:[nxv2i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 20017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20018 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20019 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20022 | GIR_RootConstrainSelectedInstOperands, |
| 20023 | // GIR_Coverage, 71305, |
| 20024 | GIR_EraseRootFromParent_Done, |
| 20025 | // Label 1430: @50022 |
| 20026 | GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(50065), // Rule ID 53818 // |
| 20027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20028 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20029 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20030 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20031 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20032 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20033 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs, VR:{ *:[nxv2i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 20035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20036 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20037 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20040 | GIR_RootConstrainSelectedInstOperands, |
| 20041 | // GIR_Coverage, 53818, |
| 20042 | GIR_EraseRootFromParent_Done, |
| 20043 | // Label 1431: @50065 |
| 20044 | GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(50108), // Rule ID 53819 // |
| 20045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20046 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20050 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20051 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs, VR:{ *:[nxv2i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF4), |
| 20053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20054 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20055 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20058 | GIR_RootConstrainSelectedInstOperands, |
| 20059 | // GIR_Coverage, 53819, |
| 20060 | GIR_EraseRootFromParent_Done, |
| 20061 | // Label 1432: @50108 |
| 20062 | GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(50141), // Rule ID 53806 // |
| 20063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20064 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20066 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMXOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_MF4), |
| 20068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20069 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20070 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20073 | GIR_RootConstrainSelectedInstOperands, |
| 20074 | // GIR_Coverage, 53806, |
| 20075 | GIR_EraseRootFromParent_Done, |
| 20076 | // Label 1433: @50141 |
| 20077 | GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(50174), // Rule ID 53807 // |
| 20078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20080 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20081 | // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMXOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_MF4), |
| 20083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20084 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20085 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20088 | GIR_RootConstrainSelectedInstOperands, |
| 20089 | // GIR_Coverage, 53807, |
| 20090 | GIR_EraseRootFromParent_Done, |
| 20091 | // Label 1434: @50174 |
| 20092 | GIM_Reject, |
| 20093 | // Label 1408: @50175 |
| 20094 | GIM_Reject, |
| 20095 | // Label 1315: @50176 |
| 20096 | GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(50290), |
| 20097 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 20098 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 20099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20101 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20102 | GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(50244), // Rule ID 48548 // |
| 20103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20104 | // (xor:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVXOR_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 20105 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 20106 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20107 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20108 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF4), |
| 20110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20111 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20112 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20113 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20117 | GIR_RootConstrainSelectedInstOperands, |
| 20118 | // GIR_Coverage, 48548, |
| 20119 | GIR_EraseRootFromParent_Done, |
| 20120 | // Label 1436: @50244 |
| 20121 | GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(50289), // Rule ID 48549 // |
| 20122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20123 | // (xor:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVXOR_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 20124 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 20125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF4), |
| 20129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20130 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20131 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20132 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20136 | GIR_RootConstrainSelectedInstOperands, |
| 20137 | // GIR_Coverage, 48549, |
| 20138 | GIR_EraseRootFromParent_Done, |
| 20139 | // Label 1437: @50289 |
| 20140 | GIM_Reject, |
| 20141 | // Label 1435: @50290 |
| 20142 | GIM_Reject, |
| 20143 | // Label 1316: @50291 |
| 20144 | GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(50405), |
| 20145 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 20146 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 20147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20148 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20150 | GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(50359), // Rule ID 48560 // |
| 20151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20152 | // (xor:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVXOR_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 20153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 20154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF2), |
| 20158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20161 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 20164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20165 | GIR_RootConstrainSelectedInstOperands, |
| 20166 | // GIR_Coverage, 48560, |
| 20167 | GIR_EraseRootFromParent_Done, |
| 20168 | // Label 1439: @50359 |
| 20169 | GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(50404), // Rule ID 48561 // |
| 20170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20171 | // (xor:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVXOR_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 20172 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 20173 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20174 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF2), |
| 20177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20179 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20180 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 20183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20184 | GIR_RootConstrainSelectedInstOperands, |
| 20185 | // GIR_Coverage, 48561, |
| 20186 | GIR_EraseRootFromParent_Done, |
| 20187 | // Label 1440: @50404 |
| 20188 | GIM_Reject, |
| 20189 | // Label 1438: @50405 |
| 20190 | GIM_Reject, |
| 20191 | // Label 1317: @50406 |
| 20192 | GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(50520), |
| 20193 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 20194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 20195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20196 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20197 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20198 | GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(50474), // Rule ID 48576 // |
| 20199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20200 | // (xor:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 20201 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 20202 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20203 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20204 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 20206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20208 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20209 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 20212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20213 | GIR_RootConstrainSelectedInstOperands, |
| 20214 | // GIR_Coverage, 48576, |
| 20215 | GIR_EraseRootFromParent_Done, |
| 20216 | // Label 1442: @50474 |
| 20217 | GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(50519), // Rule ID 48577 // |
| 20218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20219 | // (xor:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 20220 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 20221 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20222 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20223 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 20225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20226 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20227 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20228 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 20231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20232 | GIR_RootConstrainSelectedInstOperands, |
| 20233 | // GIR_Coverage, 48577, |
| 20234 | GIR_EraseRootFromParent_Done, |
| 20235 | // Label 1443: @50519 |
| 20236 | GIM_Reject, |
| 20237 | // Label 1441: @50520 |
| 20238 | GIM_Reject, |
| 20239 | // Label 1318: @50521 |
| 20240 | GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(50635), |
| 20241 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 20242 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 20243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 20244 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 20245 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 20246 | GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(50589), // Rule ID 48620 // |
| 20247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 20248 | // (xor:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 20249 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 20250 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20251 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 20254 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20255 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20256 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20257 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 20260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20261 | GIR_RootConstrainSelectedInstOperands, |
| 20262 | // GIR_Coverage, 48620, |
| 20263 | GIR_EraseRootFromParent_Done, |
| 20264 | // Label 1445: @50589 |
| 20265 | GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(50634), // Rule ID 48621 // |
| 20266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 20267 | // (xor:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 20268 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 20269 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 20273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20274 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20275 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20276 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 20279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20280 | GIR_RootConstrainSelectedInstOperands, |
| 20281 | // GIR_Coverage, 48621, |
| 20282 | GIR_EraseRootFromParent_Done, |
| 20283 | // Label 1446: @50634 |
| 20284 | GIM_Reject, |
| 20285 | // Label 1444: @50635 |
| 20286 | GIM_Reject, |
| 20287 | // Label 1319: @50636 |
| 20288 | GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(52246), |
| 20289 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20292 | GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(50720), // Rule ID 53826 // |
| 20293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20294 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20295 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 20296 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20297 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20298 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20299 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20300 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20301 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20302 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20303 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20304 | // (xor:{ *:[nxv4i1] } (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20307 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 20309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20311 | GIR_RootConstrainSelectedInstOperands, |
| 20312 | // GIR_Coverage, 53826, |
| 20313 | GIR_EraseRootFromParent_Done, |
| 20314 | // Label 1448: @50720 |
| 20315 | GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(50789), // Rule ID 53827 // |
| 20316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20318 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 20319 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20320 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20321 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20322 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20323 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20324 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20325 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20326 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20327 | // (xor:{ *:[nxv4i1] } (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 20332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20334 | GIR_RootConstrainSelectedInstOperands, |
| 20335 | // GIR_Coverage, 53827, |
| 20336 | GIR_EraseRootFromParent_Done, |
| 20337 | // Label 1449: @50789 |
| 20338 | GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(50858), // Rule ID 53828 // |
| 20339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20340 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20341 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 20342 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20343 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20344 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20345 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20346 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20347 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20348 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20349 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20350 | // (xor:{ *:[nxv4i1] } (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF2), |
| 20352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20353 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20354 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 20355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20357 | GIR_RootConstrainSelectedInstOperands, |
| 20358 | // GIR_Coverage, 53828, |
| 20359 | GIR_EraseRootFromParent_Done, |
| 20360 | // Label 1450: @50858 |
| 20361 | GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(50927), // Rule ID 53829 // |
| 20362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20363 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20364 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 20365 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20366 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20367 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20368 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20369 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20370 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20371 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20372 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20373 | // (xor:{ *:[nxv4i1] } (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF2), |
| 20375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 20378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20380 | GIR_RootConstrainSelectedInstOperands, |
| 20381 | // GIR_Coverage, 53829, |
| 20382 | GIR_EraseRootFromParent_Done, |
| 20383 | // Label 1451: @50927 |
| 20384 | GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(50993), // Rule ID 71312 // |
| 20385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20386 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20387 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20388 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20389 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20390 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 20391 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20392 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20393 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20395 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20396 | // (xor:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs1), VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 20400 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20403 | GIR_RootConstrainSelectedInstOperands, |
| 20404 | // GIR_Coverage, 71312, |
| 20405 | GIR_EraseRootFromParent_Done, |
| 20406 | // Label 1452: @50993 |
| 20407 | GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(51059), // Rule ID 71313 // |
| 20408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20409 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20410 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20411 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20412 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20413 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 20414 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20415 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20416 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20417 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20418 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20419 | // (xor:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs1), VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 20423 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20426 | GIR_RootConstrainSelectedInstOperands, |
| 20427 | // GIR_Coverage, 71313, |
| 20428 | GIR_EraseRootFromParent_Done, |
| 20429 | // Label 1453: @51059 |
| 20430 | GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(51125), // Rule ID 71310 // |
| 20431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20433 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20435 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20436 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20437 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 20438 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20439 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20440 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20441 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20442 | // (xor:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20449 | GIR_RootConstrainSelectedInstOperands, |
| 20450 | // GIR_Coverage, 71310, |
| 20451 | GIR_EraseRootFromParent_Done, |
| 20452 | // Label 1454: @51125 |
| 20453 | GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(51191), // Rule ID 71311 // |
| 20454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20455 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20456 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20457 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20458 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20459 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20460 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 20461 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20462 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20464 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20465 | // (xor:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20469 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20472 | GIR_RootConstrainSelectedInstOperands, |
| 20473 | // GIR_Coverage, 71311, |
| 20474 | GIR_EraseRootFromParent_Done, |
| 20475 | // Label 1455: @51191 |
| 20476 | GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(51260), // Rule ID 53830 // |
| 20477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20479 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20480 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20481 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20482 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20483 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20484 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20485 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20486 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20487 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20488 | // (xor:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20491 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 20493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20495 | GIR_RootConstrainSelectedInstOperands, |
| 20496 | // GIR_Coverage, 53830, |
| 20497 | GIR_EraseRootFromParent_Done, |
| 20498 | // Label 1456: @51260 |
| 20499 | GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(51329), // Rule ID 53831 // |
| 20500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20501 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20502 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20503 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20504 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20505 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20506 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20507 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20508 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20509 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20510 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20511 | // (xor:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 20516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20518 | GIR_RootConstrainSelectedInstOperands, |
| 20519 | // GIR_Coverage, 53831, |
| 20520 | GIR_EraseRootFromParent_Done, |
| 20521 | // Label 1457: @51329 |
| 20522 | GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(51398), // Rule ID 71306 // |
| 20523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20524 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20525 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20526 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20527 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20528 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 20529 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20530 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20531 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20532 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20533 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20534 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 20538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 20539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20541 | GIR_RootConstrainSelectedInstOperands, |
| 20542 | // GIR_Coverage, 71306, |
| 20543 | GIR_EraseRootFromParent_Done, |
| 20544 | // Label 1458: @51398 |
| 20545 | GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(51467), // Rule ID 71307 // |
| 20546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20547 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20548 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20549 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20550 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20551 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 20552 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20553 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20554 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20555 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20556 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20557 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20560 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 20561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 20562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20564 | GIR_RootConstrainSelectedInstOperands, |
| 20565 | // GIR_Coverage, 71307, |
| 20566 | GIR_EraseRootFromParent_Done, |
| 20567 | // Label 1459: @51467 |
| 20568 | GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(51536), // Rule ID 71308 // |
| 20569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20570 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20571 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20572 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20573 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20574 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 20575 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20576 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20577 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20578 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20579 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20580 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF2), |
| 20582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20583 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 20584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 20585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20587 | GIR_RootConstrainSelectedInstOperands, |
| 20588 | // GIR_Coverage, 71308, |
| 20589 | GIR_EraseRootFromParent_Done, |
| 20590 | // Label 1460: @51536 |
| 20591 | GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(51605), // Rule ID 71309 // |
| 20592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20593 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20594 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20595 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20596 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20597 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 20598 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20599 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20600 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20601 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20602 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20603 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_MF2), |
| 20605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 20607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 20608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20610 | GIR_RootConstrainSelectedInstOperands, |
| 20611 | // GIR_Coverage, 71309, |
| 20612 | GIR_EraseRootFromParent_Done, |
| 20613 | // Label 1461: @51605 |
| 20614 | GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(51674), // Rule ID 71314 // |
| 20615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20616 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20617 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20618 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20619 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20620 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20621 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20622 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20623 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20624 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20625 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20626 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20629 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 20630 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 20631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20633 | GIR_RootConstrainSelectedInstOperands, |
| 20634 | // GIR_Coverage, 71314, |
| 20635 | GIR_EraseRootFromParent_Done, |
| 20636 | // Label 1462: @51674 |
| 20637 | GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(51743), // Rule ID 71315 // |
| 20638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20639 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20640 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20641 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20642 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 20643 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20644 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20645 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20646 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20647 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20648 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20649 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 20653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 20654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20656 | GIR_RootConstrainSelectedInstOperands, |
| 20657 | // GIR_Coverage, 71315, |
| 20658 | GIR_EraseRootFromParent_Done, |
| 20659 | // Label 1463: @51743 |
| 20660 | GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(51809), // Rule ID 71318 // |
| 20661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20662 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20663 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20664 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20665 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20666 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20667 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 20668 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20669 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20670 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20671 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20672 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs1)) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 20676 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 20677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20679 | GIR_RootConstrainSelectedInstOperands, |
| 20680 | // GIR_Coverage, 71318, |
| 20681 | GIR_EraseRootFromParent_Done, |
| 20682 | // Label 1464: @51809 |
| 20683 | GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(51875), // Rule ID 71319 // |
| 20684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20688 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20689 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20690 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 20691 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20692 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20693 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20694 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20695 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs1)) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 20699 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 20700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20702 | GIR_RootConstrainSelectedInstOperands, |
| 20703 | // GIR_Coverage, 71319, |
| 20704 | GIR_EraseRootFromParent_Done, |
| 20705 | // Label 1465: @51875 |
| 20706 | GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(51941), // Rule ID 71316 // |
| 20707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20708 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20710 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20711 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20712 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20713 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20714 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 20715 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20716 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20717 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20718 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20722 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 20723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20725 | GIR_RootConstrainSelectedInstOperands, |
| 20726 | // GIR_Coverage, 71316, |
| 20727 | GIR_EraseRootFromParent_Done, |
| 20728 | // Label 1466: @51941 |
| 20729 | GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(52007), // Rule ID 71317 // |
| 20730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20731 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20732 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20733 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 20734 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 20735 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, |
| 20736 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20737 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 20738 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20739 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20740 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20741 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_MF2), |
| 20743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 20745 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 20746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20748 | GIR_RootConstrainSelectedInstOperands, |
| 20749 | // GIR_Coverage, 71317, |
| 20750 | GIR_EraseRootFromParent_Done, |
| 20751 | // Label 1467: @52007 |
| 20752 | GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(52050), // Rule ID 71332 // |
| 20753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20754 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20755 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20756 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20757 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20758 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20759 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs, VR:{ *:[nxv4i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20762 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20763 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20766 | GIR_RootConstrainSelectedInstOperands, |
| 20767 | // GIR_Coverage, 71332, |
| 20768 | GIR_EraseRootFromParent_Done, |
| 20769 | // Label 1468: @52050 |
| 20770 | GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(52093), // Rule ID 71333 // |
| 20771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20772 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20773 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20774 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20776 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20777 | // (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs, VR:{ *:[nxv4i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20780 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20781 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 20782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20784 | GIR_RootConstrainSelectedInstOperands, |
| 20785 | // GIR_Coverage, 71333, |
| 20786 | GIR_EraseRootFromParent_Done, |
| 20787 | // Label 1469: @52093 |
| 20788 | GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(52136), // Rule ID 53836 // |
| 20789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20791 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20792 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20793 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20794 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20795 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs, VR:{ *:[nxv4i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20798 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20799 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20802 | GIR_RootConstrainSelectedInstOperands, |
| 20803 | // GIR_Coverage, 53836, |
| 20804 | GIR_EraseRootFromParent_Done, |
| 20805 | // Label 1470: @52136 |
| 20806 | GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(52179), // Rule ID 53837 // |
| 20807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20808 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20809 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 20810 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 20811 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20812 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20813 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs, VR:{ *:[nxv4i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_MF2), |
| 20815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20816 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20817 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 20818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20820 | GIR_RootConstrainSelectedInstOperands, |
| 20821 | // GIR_Coverage, 53837, |
| 20822 | GIR_EraseRootFromParent_Done, |
| 20823 | // Label 1471: @52179 |
| 20824 | GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(52212), // Rule ID 53824 // |
| 20825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20828 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMXOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 20829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_MF2), |
| 20830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20831 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20832 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20835 | GIR_RootConstrainSelectedInstOperands, |
| 20836 | // GIR_Coverage, 53824, |
| 20837 | GIR_EraseRootFromParent_Done, |
| 20838 | // Label 1472: @52212 |
| 20839 | GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(52245), // Rule ID 53825 // |
| 20840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20843 | // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMXOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 20844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_MF2), |
| 20845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20846 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20847 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20850 | GIR_RootConstrainSelectedInstOperands, |
| 20851 | // GIR_Coverage, 53825, |
| 20852 | GIR_EraseRootFromParent_Done, |
| 20853 | // Label 1473: @52245 |
| 20854 | GIM_Reject, |
| 20855 | // Label 1447: @52246 |
| 20856 | GIM_Reject, |
| 20857 | // Label 1320: @52247 |
| 20858 | GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(52361), |
| 20859 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 20860 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 20861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20862 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20863 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20864 | GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(52315), // Rule ID 48552 // |
| 20865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20866 | // (xor:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVXOR_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 20867 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 20868 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20869 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF2), |
| 20872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20873 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20874 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20875 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20879 | GIR_RootConstrainSelectedInstOperands, |
| 20880 | // GIR_Coverage, 48552, |
| 20881 | GIR_EraseRootFromParent_Done, |
| 20882 | // Label 1475: @52315 |
| 20883 | GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(52360), // Rule ID 48553 // |
| 20884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20885 | // (xor:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVXOR_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 20886 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 20887 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20888 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_MF2), |
| 20891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20892 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20893 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20894 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20898 | GIR_RootConstrainSelectedInstOperands, |
| 20899 | // GIR_Coverage, 48553, |
| 20900 | GIR_EraseRootFromParent_Done, |
| 20901 | // Label 1476: @52360 |
| 20902 | GIM_Reject, |
| 20903 | // Label 1474: @52361 |
| 20904 | GIM_Reject, |
| 20905 | // Label 1321: @52362 |
| 20906 | GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(52476), |
| 20907 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 20908 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 20909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20911 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 20912 | GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(52430), // Rule ID 48572 // |
| 20913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20914 | // (xor:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 20915 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 20916 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20917 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20918 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 20920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20921 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20922 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20923 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 20926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20927 | GIR_RootConstrainSelectedInstOperands, |
| 20928 | // GIR_Coverage, 48572, |
| 20929 | GIR_EraseRootFromParent_Done, |
| 20930 | // Label 1478: @52430 |
| 20931 | GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(52475), // Rule ID 48573 // |
| 20932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20933 | // (xor:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 20934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 20935 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20936 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20937 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 20939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20940 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20941 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20942 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 20945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20946 | GIR_RootConstrainSelectedInstOperands, |
| 20947 | // GIR_Coverage, 48573, |
| 20948 | GIR_EraseRootFromParent_Done, |
| 20949 | // Label 1479: @52475 |
| 20950 | GIM_Reject, |
| 20951 | // Label 1477: @52476 |
| 20952 | GIM_Reject, |
| 20953 | // Label 1322: @52477 |
| 20954 | GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(52591), |
| 20955 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 20956 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 20957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 20958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 20959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 20960 | GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(52545), // Rule ID 48608 // |
| 20961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 20962 | // (xor:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 20963 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 20964 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20965 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20966 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 20968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20969 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20970 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20971 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 20974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20975 | GIR_RootConstrainSelectedInstOperands, |
| 20976 | // GIR_Coverage, 48608, |
| 20977 | GIR_EraseRootFromParent_Done, |
| 20978 | // Label 1481: @52545 |
| 20979 | GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(52590), // Rule ID 48609 // |
| 20980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 20981 | // (xor:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 20982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 20983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 20984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 20987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20988 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20989 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 20990 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 20991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 20992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 20993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 20994 | GIR_RootConstrainSelectedInstOperands, |
| 20995 | // GIR_Coverage, 48609, |
| 20996 | GIR_EraseRootFromParent_Done, |
| 20997 | // Label 1482: @52590 |
| 20998 | GIM_Reject, |
| 20999 | // Label 1480: @52591 |
| 21000 | GIM_Reject, |
| 21001 | // Label 1323: @52592 |
| 21002 | GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(52706), |
| 21003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 21004 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 21005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 21006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 21007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 21008 | GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(52660), // Rule ID 48624 // |
| 21009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 21010 | // (xor:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 21011 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 21012 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21013 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21014 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 21016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21017 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21018 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21019 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 21022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21023 | GIR_RootConstrainSelectedInstOperands, |
| 21024 | // GIR_Coverage, 48624, |
| 21025 | GIR_EraseRootFromParent_Done, |
| 21026 | // Label 1484: @52660 |
| 21027 | GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(52705), // Rule ID 48625 // |
| 21028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 21029 | // (xor:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 21030 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 21031 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21032 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21033 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 21035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21036 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21037 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21038 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 21041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21042 | GIR_RootConstrainSelectedInstOperands, |
| 21043 | // GIR_Coverage, 48625, |
| 21044 | GIR_EraseRootFromParent_Done, |
| 21045 | // Label 1485: @52705 |
| 21046 | GIM_Reject, |
| 21047 | // Label 1483: @52706 |
| 21048 | GIM_Reject, |
| 21049 | // Label 1324: @52707 |
| 21050 | GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(54317), |
| 21051 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21052 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21054 | GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(52791), // Rule ID 53844 // |
| 21055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21056 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21057 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 21058 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21059 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21060 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21061 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21062 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21063 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21064 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21065 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21066 | // (xor:{ *:[nxv8i1] } (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21073 | GIR_RootConstrainSelectedInstOperands, |
| 21074 | // GIR_Coverage, 53844, |
| 21075 | GIR_EraseRootFromParent_Done, |
| 21076 | // Label 1487: @52791 |
| 21077 | GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(52860), // Rule ID 53845 // |
| 21078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21079 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21080 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 21081 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21082 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21083 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21084 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21085 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21086 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21087 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21088 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21089 | // (xor:{ *:[nxv8i1] } (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21096 | GIR_RootConstrainSelectedInstOperands, |
| 21097 | // GIR_Coverage, 53845, |
| 21098 | GIR_EraseRootFromParent_Done, |
| 21099 | // Label 1488: @52860 |
| 21100 | GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(52929), // Rule ID 53846 // |
| 21101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21102 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21103 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 21104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21106 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21107 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21108 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21109 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21110 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21111 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21112 | // (xor:{ *:[nxv8i1] } (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M1), |
| 21114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21119 | GIR_RootConstrainSelectedInstOperands, |
| 21120 | // GIR_Coverage, 53846, |
| 21121 | GIR_EraseRootFromParent_Done, |
| 21122 | // Label 1489: @52929 |
| 21123 | GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(52998), // Rule ID 53847 // |
| 21124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21125 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21126 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 21127 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21128 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21129 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21130 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21131 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21132 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21133 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21134 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21135 | // (xor:{ *:[nxv8i1] } (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M1), |
| 21137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21142 | GIR_RootConstrainSelectedInstOperands, |
| 21143 | // GIR_Coverage, 53847, |
| 21144 | GIR_EraseRootFromParent_Done, |
| 21145 | // Label 1490: @52998 |
| 21146 | GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(53064), // Rule ID 71340 // |
| 21147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21148 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21149 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21150 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21151 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21152 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 21153 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21154 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21155 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21156 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21157 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21158 | // (xor:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs1), VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21161 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 21162 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21165 | GIR_RootConstrainSelectedInstOperands, |
| 21166 | // GIR_Coverage, 71340, |
| 21167 | GIR_EraseRootFromParent_Done, |
| 21168 | // Label 1491: @53064 |
| 21169 | GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(53130), // Rule ID 71341 // |
| 21170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21171 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21172 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21173 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21174 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21175 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 21176 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21177 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21178 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21180 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21181 | // (xor:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs1), VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 21185 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21188 | GIR_RootConstrainSelectedInstOperands, |
| 21189 | // GIR_Coverage, 71341, |
| 21190 | GIR_EraseRootFromParent_Done, |
| 21191 | // Label 1492: @53130 |
| 21192 | GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(53196), // Rule ID 71338 // |
| 21193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21194 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21195 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21196 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21197 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21198 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21199 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 21200 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21201 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21202 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21203 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21204 | // (xor:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21208 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21211 | GIR_RootConstrainSelectedInstOperands, |
| 21212 | // GIR_Coverage, 71338, |
| 21213 | GIR_EraseRootFromParent_Done, |
| 21214 | // Label 1493: @53196 |
| 21215 | GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(53262), // Rule ID 71339 // |
| 21216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21217 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21218 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21219 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21220 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21221 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21222 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 21223 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21224 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21225 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21226 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21227 | // (xor:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21231 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21234 | GIR_RootConstrainSelectedInstOperands, |
| 21235 | // GIR_Coverage, 71339, |
| 21236 | GIR_EraseRootFromParent_Done, |
| 21237 | // Label 1494: @53262 |
| 21238 | GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(53331), // Rule ID 53848 // |
| 21239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21240 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21241 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21242 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21243 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21244 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21245 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21246 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21247 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21248 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21249 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21250 | // (xor:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21257 | GIR_RootConstrainSelectedInstOperands, |
| 21258 | // GIR_Coverage, 53848, |
| 21259 | GIR_EraseRootFromParent_Done, |
| 21260 | // Label 1495: @53331 |
| 21261 | GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(53400), // Rule ID 53849 // |
| 21262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21263 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21264 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21265 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21266 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21267 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21268 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21269 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21270 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21271 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21272 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21273 | // (xor:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21280 | GIR_RootConstrainSelectedInstOperands, |
| 21281 | // GIR_Coverage, 53849, |
| 21282 | GIR_EraseRootFromParent_Done, |
| 21283 | // Label 1496: @53400 |
| 21284 | GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(53469), // Rule ID 71334 // |
| 21285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21286 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21287 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21288 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21289 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21290 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 21291 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21292 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21293 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21294 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21295 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21296 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 21300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 21301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21303 | GIR_RootConstrainSelectedInstOperands, |
| 21304 | // GIR_Coverage, 71334, |
| 21305 | GIR_EraseRootFromParent_Done, |
| 21306 | // Label 1497: @53469 |
| 21307 | GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(53538), // Rule ID 71335 // |
| 21308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21309 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21310 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21311 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21312 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21313 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 21314 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21315 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21316 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21317 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21318 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21319 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21322 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 21323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 21324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21326 | GIR_RootConstrainSelectedInstOperands, |
| 21327 | // GIR_Coverage, 71335, |
| 21328 | GIR_EraseRootFromParent_Done, |
| 21329 | // Label 1498: @53538 |
| 21330 | GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(53607), // Rule ID 71336 // |
| 21331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21335 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21336 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 21337 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21338 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21339 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21340 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21341 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21342 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M1), |
| 21344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 21346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 21347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21349 | GIR_RootConstrainSelectedInstOperands, |
| 21350 | // GIR_Coverage, 71336, |
| 21351 | GIR_EraseRootFromParent_Done, |
| 21352 | // Label 1499: @53607 |
| 21353 | GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(53676), // Rule ID 71337 // |
| 21354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21355 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21356 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21357 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21358 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21359 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 21360 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21361 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21362 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21363 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21364 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21365 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M1), |
| 21367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 21369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 21370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21372 | GIR_RootConstrainSelectedInstOperands, |
| 21373 | // GIR_Coverage, 71337, |
| 21374 | GIR_EraseRootFromParent_Done, |
| 21375 | // Label 1500: @53676 |
| 21376 | GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(53745), // Rule ID 71342 // |
| 21377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21378 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21379 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21380 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21381 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21382 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21383 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21384 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21385 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21386 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21387 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21388 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 21392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 21393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21395 | GIR_RootConstrainSelectedInstOperands, |
| 21396 | // GIR_Coverage, 71342, |
| 21397 | GIR_EraseRootFromParent_Done, |
| 21398 | // Label 1501: @53745 |
| 21399 | GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(53814), // Rule ID 71343 // |
| 21400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21401 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21402 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21403 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21404 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21405 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21406 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21407 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21408 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21409 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21410 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21411 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 21415 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 21416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21418 | GIR_RootConstrainSelectedInstOperands, |
| 21419 | // GIR_Coverage, 71343, |
| 21420 | GIR_EraseRootFromParent_Done, |
| 21421 | // Label 1502: @53814 |
| 21422 | GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(53880), // Rule ID 71346 // |
| 21423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21424 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21425 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21426 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21427 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21428 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21429 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 21430 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21431 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21432 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21433 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21434 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs1)) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 21438 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 21439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21441 | GIR_RootConstrainSelectedInstOperands, |
| 21442 | // GIR_Coverage, 71346, |
| 21443 | GIR_EraseRootFromParent_Done, |
| 21444 | // Label 1503: @53880 |
| 21445 | GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(53946), // Rule ID 71347 // |
| 21446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21447 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21448 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21449 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21450 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21451 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21452 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 21453 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21454 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21455 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21456 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21457 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs1)) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 21461 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 21462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21464 | GIR_RootConstrainSelectedInstOperands, |
| 21465 | // GIR_Coverage, 71347, |
| 21466 | GIR_EraseRootFromParent_Done, |
| 21467 | // Label 1504: @53946 |
| 21468 | GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(54012), // Rule ID 71344 // |
| 21469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21471 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21472 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21473 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21474 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21475 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21476 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 21477 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21478 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21479 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21480 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21484 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 21485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21487 | GIR_RootConstrainSelectedInstOperands, |
| 21488 | // GIR_Coverage, 71344, |
| 21489 | GIR_EraseRootFromParent_Done, |
| 21490 | // Label 1505: @54012 |
| 21491 | GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(54078), // Rule ID 71345 // |
| 21492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21494 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21495 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21496 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 21497 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, |
| 21498 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21499 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 21500 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21501 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21502 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21503 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M1), |
| 21505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21507 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 21508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21510 | GIR_RootConstrainSelectedInstOperands, |
| 21511 | // GIR_Coverage, 71345, |
| 21512 | GIR_EraseRootFromParent_Done, |
| 21513 | // Label 1506: @54078 |
| 21514 | GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(54121), // Rule ID 71360 // |
| 21515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21517 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21518 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21519 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21520 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21521 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs, VR:{ *:[nxv8i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21524 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 21525 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 21526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21528 | GIR_RootConstrainSelectedInstOperands, |
| 21529 | // GIR_Coverage, 71360, |
| 21530 | GIR_EraseRootFromParent_Done, |
| 21531 | // Label 1507: @54121 |
| 21532 | GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(54164), // Rule ID 71361 // |
| 21533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21534 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21535 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21536 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21538 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21539 | // (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs, VR:{ *:[nxv8i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21542 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 21543 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 21544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21546 | GIR_RootConstrainSelectedInstOperands, |
| 21547 | // GIR_Coverage, 71361, |
| 21548 | GIR_EraseRootFromParent_Done, |
| 21549 | // Label 1508: @54164 |
| 21550 | GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(54207), // Rule ID 53854 // |
| 21551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21553 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21554 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21555 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21556 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21557 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs, VR:{ *:[nxv8i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 21561 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 21562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21564 | GIR_RootConstrainSelectedInstOperands, |
| 21565 | // GIR_Coverage, 53854, |
| 21566 | GIR_EraseRootFromParent_Done, |
| 21567 | // Label 1509: @54207 |
| 21568 | GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(54250), // Rule ID 53855 // |
| 21569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21570 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21571 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21572 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21573 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21574 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21575 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs, VR:{ *:[nxv8i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M1), |
| 21577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21578 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 21579 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 21580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21582 | GIR_RootConstrainSelectedInstOperands, |
| 21583 | // GIR_Coverage, 53855, |
| 21584 | GIR_EraseRootFromParent_Done, |
| 21585 | // Label 1510: @54250 |
| 21586 | GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(54283), // Rule ID 53842 // |
| 21587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21589 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21590 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMXOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M1), |
| 21592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21593 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21594 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21597 | GIR_RootConstrainSelectedInstOperands, |
| 21598 | // GIR_Coverage, 53842, |
| 21599 | GIR_EraseRootFromParent_Done, |
| 21600 | // Label 1511: @54283 |
| 21601 | GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(54316), // Rule ID 53843 // |
| 21602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21603 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21604 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21605 | // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2) => (PseudoVMXOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M1), |
| 21607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21608 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21609 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21612 | GIR_RootConstrainSelectedInstOperands, |
| 21613 | // GIR_Coverage, 53843, |
| 21614 | GIR_EraseRootFromParent_Done, |
| 21615 | // Label 1512: @54316 |
| 21616 | GIM_Reject, |
| 21617 | // Label 1486: @54317 |
| 21618 | GIM_Reject, |
| 21619 | // Label 1325: @54318 |
| 21620 | GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(54432), |
| 21621 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 21622 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 21623 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21624 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21625 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21626 | GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(54386), // Rule ID 48568 // |
| 21627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21628 | // (xor:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 21629 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 21630 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21631 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 21634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21635 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21636 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21637 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21641 | GIR_RootConstrainSelectedInstOperands, |
| 21642 | // GIR_Coverage, 48568, |
| 21643 | GIR_EraseRootFromParent_Done, |
| 21644 | // Label 1514: @54386 |
| 21645 | GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(54431), // Rule ID 48569 // |
| 21646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21647 | // (xor:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVXOR_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 21648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 21649 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M1), |
| 21653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21654 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21655 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21656 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21660 | GIR_RootConstrainSelectedInstOperands, |
| 21661 | // GIR_Coverage, 48569, |
| 21662 | GIR_EraseRootFromParent_Done, |
| 21663 | // Label 1515: @54431 |
| 21664 | GIM_Reject, |
| 21665 | // Label 1513: @54432 |
| 21666 | GIM_Reject, |
| 21667 | // Label 1326: @54433 |
| 21668 | GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(54547), |
| 21669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 21670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 21671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 21672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 21673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 21674 | GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(54501), // Rule ID 48596 // |
| 21675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21676 | // (xor:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 21677 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 21678 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21679 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 21682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21683 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21684 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21685 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 21688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21689 | GIR_RootConstrainSelectedInstOperands, |
| 21690 | // GIR_Coverage, 48596, |
| 21691 | GIR_EraseRootFromParent_Done, |
| 21692 | // Label 1517: @54501 |
| 21693 | GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(54546), // Rule ID 48597 // |
| 21694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21695 | // (xor:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 21696 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 21697 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 21701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21702 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21704 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 21707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21708 | GIR_RootConstrainSelectedInstOperands, |
| 21709 | // GIR_Coverage, 48597, |
| 21710 | GIR_EraseRootFromParent_Done, |
| 21711 | // Label 1518: @54546 |
| 21712 | GIM_Reject, |
| 21713 | // Label 1516: @54547 |
| 21714 | GIM_Reject, |
| 21715 | // Label 1327: @54548 |
| 21716 | GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(54662), |
| 21717 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 21718 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 21719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 21720 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 21721 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 21722 | GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(54616), // Rule ID 48612 // |
| 21723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21724 | // (xor:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 21725 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 21726 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21727 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 21730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21731 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21732 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21733 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 21736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21737 | GIR_RootConstrainSelectedInstOperands, |
| 21738 | // GIR_Coverage, 48612, |
| 21739 | GIR_EraseRootFromParent_Done, |
| 21740 | // Label 1520: @54616 |
| 21741 | GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(54661), // Rule ID 48613 // |
| 21742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21743 | // (xor:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 21744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 21745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21747 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 21749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21750 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21752 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 21755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21756 | GIR_RootConstrainSelectedInstOperands, |
| 21757 | // GIR_Coverage, 48613, |
| 21758 | GIR_EraseRootFromParent_Done, |
| 21759 | // Label 1521: @54661 |
| 21760 | GIM_Reject, |
| 21761 | // Label 1519: @54662 |
| 21762 | GIM_Reject, |
| 21763 | // Label 1328: @54663 |
| 21764 | GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(54777), |
| 21765 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 21766 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 21767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 21768 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 21769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 21770 | GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(54731), // Rule ID 48628 // |
| 21771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 21772 | // (xor:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 21773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 21774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 21778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21781 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 21784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21785 | GIR_RootConstrainSelectedInstOperands, |
| 21786 | // GIR_Coverage, 48628, |
| 21787 | GIR_EraseRootFromParent_Done, |
| 21788 | // Label 1523: @54731 |
| 21789 | GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(54776), // Rule ID 48629 // |
| 21790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 21791 | // (xor:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 21792 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 21793 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21794 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 21797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21798 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21799 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 21800 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 21803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 21804 | GIR_RootConstrainSelectedInstOperands, |
| 21805 | // GIR_Coverage, 48629, |
| 21806 | GIR_EraseRootFromParent_Done, |
| 21807 | // Label 1524: @54776 |
| 21808 | GIM_Reject, |
| 21809 | // Label 1522: @54777 |
| 21810 | GIM_Reject, |
| 21811 | // Label 1329: @54778 |
| 21812 | GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(56388), |
| 21813 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21816 | GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(54862), // Rule ID 53862 // |
| 21817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21818 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21819 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 21820 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21821 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21822 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21823 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21824 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21825 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21826 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21827 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21828 | // (xor:{ *:[nxv16i1] } (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 21830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21835 | GIR_RootConstrainSelectedInstOperands, |
| 21836 | // GIR_Coverage, 53862, |
| 21837 | GIR_EraseRootFromParent_Done, |
| 21838 | // Label 1526: @54862 |
| 21839 | GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(54931), // Rule ID 53863 // |
| 21840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21841 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21842 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 21843 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21844 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21845 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21846 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21847 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21848 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21849 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21850 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21851 | // (xor:{ *:[nxv16i1] } (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 21853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21858 | GIR_RootConstrainSelectedInstOperands, |
| 21859 | // GIR_Coverage, 53863, |
| 21860 | GIR_EraseRootFromParent_Done, |
| 21861 | // Label 1527: @54931 |
| 21862 | GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(55000), // Rule ID 53864 // |
| 21863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21865 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 21866 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21867 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21868 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21869 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21870 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21871 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21872 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21873 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21874 | // (xor:{ *:[nxv16i1] } (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M2), |
| 21876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21881 | GIR_RootConstrainSelectedInstOperands, |
| 21882 | // GIR_Coverage, 53864, |
| 21883 | GIR_EraseRootFromParent_Done, |
| 21884 | // Label 1528: @55000 |
| 21885 | GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(55069), // Rule ID 53865 // |
| 21886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21887 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21888 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 21889 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21890 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21891 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21892 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21893 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 21894 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21895 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21896 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21897 | // (xor:{ *:[nxv16i1] } (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M2), |
| 21899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 21902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21904 | GIR_RootConstrainSelectedInstOperands, |
| 21905 | // GIR_Coverage, 53865, |
| 21906 | GIR_EraseRootFromParent_Done, |
| 21907 | // Label 1529: @55069 |
| 21908 | GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(55135), // Rule ID 71368 // |
| 21909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21910 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21911 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21912 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21913 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21914 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 21915 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21916 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21917 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21918 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21919 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21920 | // (xor:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs1), VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 21922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 21924 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21927 | GIR_RootConstrainSelectedInstOperands, |
| 21928 | // GIR_Coverage, 71368, |
| 21929 | GIR_EraseRootFromParent_Done, |
| 21930 | // Label 1530: @55135 |
| 21931 | GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(55201), // Rule ID 71369 // |
| 21932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21934 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21935 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21936 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21937 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 21938 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21939 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21940 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21941 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21942 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21943 | // (xor:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs1), VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 21945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 21947 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21950 | GIR_RootConstrainSelectedInstOperands, |
| 21951 | // GIR_Coverage, 71369, |
| 21952 | GIR_EraseRootFromParent_Done, |
| 21953 | // Label 1531: @55201 |
| 21954 | GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(55267), // Rule ID 71366 // |
| 21955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 21956 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21957 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21958 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21959 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21960 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21961 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 21962 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21963 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 21964 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21965 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21966 | // (xor:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 21967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 21968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21970 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21973 | GIR_RootConstrainSelectedInstOperands, |
| 21974 | // GIR_Coverage, 71366, |
| 21975 | GIR_EraseRootFromParent_Done, |
| 21976 | // Label 1532: @55267 |
| 21977 | GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(55333), // Rule ID 71367 // |
| 21978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 21979 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21980 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 21981 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 21982 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 21983 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21984 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 21985 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 21986 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 21987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 21988 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21989 | // (xor:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 21990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 21991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 21992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 21993 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 21994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 21995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21996 | GIR_RootConstrainSelectedInstOperands, |
| 21997 | // GIR_Coverage, 71367, |
| 21998 | GIR_EraseRootFromParent_Done, |
| 21999 | // Label 1533: @55333 |
| 22000 | GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(55402), // Rule ID 53866 // |
| 22001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22003 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22005 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22006 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22007 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22008 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22009 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22010 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22011 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22012 | // (xor:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22019 | GIR_RootConstrainSelectedInstOperands, |
| 22020 | // GIR_Coverage, 53866, |
| 22021 | GIR_EraseRootFromParent_Done, |
| 22022 | // Label 1534: @55402 |
| 22023 | GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(55471), // Rule ID 53867 // |
| 22024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22025 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22026 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22027 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22028 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22029 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22030 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22031 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22032 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22033 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22034 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22035 | // (xor:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22038 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22042 | GIR_RootConstrainSelectedInstOperands, |
| 22043 | // GIR_Coverage, 53867, |
| 22044 | GIR_EraseRootFromParent_Done, |
| 22045 | // Label 1535: @55471 |
| 22046 | GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(55540), // Rule ID 71362 // |
| 22047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22048 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22049 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22050 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22051 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22052 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 22053 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22054 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22055 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22056 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22057 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22058 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 22060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22065 | GIR_RootConstrainSelectedInstOperands, |
| 22066 | // GIR_Coverage, 71362, |
| 22067 | GIR_EraseRootFromParent_Done, |
| 22068 | // Label 1536: @55540 |
| 22069 | GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(55609), // Rule ID 71363 // |
| 22070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22072 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22074 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22075 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 22076 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22077 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22078 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22079 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22080 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22081 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 22083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22088 | GIR_RootConstrainSelectedInstOperands, |
| 22089 | // GIR_Coverage, 71363, |
| 22090 | GIR_EraseRootFromParent_Done, |
| 22091 | // Label 1537: @55609 |
| 22092 | GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(55678), // Rule ID 71364 // |
| 22093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22094 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22095 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22096 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22097 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22098 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 22099 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22100 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22101 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22102 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22103 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22104 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M2), |
| 22106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22107 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22111 | GIR_RootConstrainSelectedInstOperands, |
| 22112 | // GIR_Coverage, 71364, |
| 22113 | GIR_EraseRootFromParent_Done, |
| 22114 | // Label 1538: @55678 |
| 22115 | GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(55747), // Rule ID 71365 // |
| 22116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22117 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22118 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22119 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22120 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22121 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 22122 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22123 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22124 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22125 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22126 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22127 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M2), |
| 22129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22131 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22134 | GIR_RootConstrainSelectedInstOperands, |
| 22135 | // GIR_Coverage, 71365, |
| 22136 | GIR_EraseRootFromParent_Done, |
| 22137 | // Label 1539: @55747 |
| 22138 | GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(55816), // Rule ID 71370 // |
| 22139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22141 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22143 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22144 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22145 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22146 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22147 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22148 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22149 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22150 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22157 | GIR_RootConstrainSelectedInstOperands, |
| 22158 | // GIR_Coverage, 71370, |
| 22159 | GIR_EraseRootFromParent_Done, |
| 22160 | // Label 1540: @55816 |
| 22161 | GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(55885), // Rule ID 71371 // |
| 22162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22163 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22164 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22165 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22166 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22167 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22168 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22169 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22170 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22171 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22172 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22173 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22180 | GIR_RootConstrainSelectedInstOperands, |
| 22181 | // GIR_Coverage, 71371, |
| 22182 | GIR_EraseRootFromParent_Done, |
| 22183 | // Label 1541: @55885 |
| 22184 | GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(55951), // Rule ID 71374 // |
| 22185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22186 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22187 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22188 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22189 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22190 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22191 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22192 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22193 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22194 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22195 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22196 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs1)) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 22200 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22203 | GIR_RootConstrainSelectedInstOperands, |
| 22204 | // GIR_Coverage, 71374, |
| 22205 | GIR_EraseRootFromParent_Done, |
| 22206 | // Label 1542: @55951 |
| 22207 | GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(56017), // Rule ID 71375 // |
| 22208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22211 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22213 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22214 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22215 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22216 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22217 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22218 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22219 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs1)) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 22223 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22226 | GIR_RootConstrainSelectedInstOperands, |
| 22227 | // GIR_Coverage, 71375, |
| 22228 | GIR_EraseRootFromParent_Done, |
| 22229 | // Label 1543: @56017 |
| 22230 | GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(56083), // Rule ID 71372 // |
| 22231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22232 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22233 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22234 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22235 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22236 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22237 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22238 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22239 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22240 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22241 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22242 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22246 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22249 | GIR_RootConstrainSelectedInstOperands, |
| 22250 | // GIR_Coverage, 71372, |
| 22251 | GIR_EraseRootFromParent_Done, |
| 22252 | // Label 1544: @56083 |
| 22253 | GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(56149), // Rule ID 71373 // |
| 22254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22255 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22256 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22257 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22258 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 22259 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1, |
| 22260 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22261 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22262 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22263 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22264 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22265 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs2, (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M2), |
| 22267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22272 | GIR_RootConstrainSelectedInstOperands, |
| 22273 | // GIR_Coverage, 71373, |
| 22274 | GIR_EraseRootFromParent_Done, |
| 22275 | // Label 1545: @56149 |
| 22276 | GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(56192), // Rule ID 71388 // |
| 22277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22278 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22279 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22280 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22282 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22283 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv16i1] }:$rs) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs, VR:{ *:[nxv16i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 22285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22286 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 22287 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 22288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22290 | GIR_RootConstrainSelectedInstOperands, |
| 22291 | // GIR_Coverage, 71388, |
| 22292 | GIR_EraseRootFromParent_Done, |
| 22293 | // Label 1546: @56192 |
| 22294 | GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(56235), // Rule ID 71389 // |
| 22295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22296 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22297 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22298 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22300 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22301 | // (xor:{ *:[nxv16i1] } (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv16i1] }:$rs) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs, VR:{ *:[nxv16i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 22303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22304 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 22305 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 22306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22308 | GIR_RootConstrainSelectedInstOperands, |
| 22309 | // GIR_Coverage, 71389, |
| 22310 | GIR_EraseRootFromParent_Done, |
| 22311 | // Label 1547: @56235 |
| 22312 | GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(56278), // Rule ID 53872 // |
| 22313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22315 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22316 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22317 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22318 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22319 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs, VR:{ *:[nxv16i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 22321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22322 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 22323 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 22324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22326 | GIR_RootConstrainSelectedInstOperands, |
| 22327 | // GIR_Coverage, 53872, |
| 22328 | GIR_EraseRootFromParent_Done, |
| 22329 | // Label 1548: @56278 |
| 22330 | GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(56321), // Rule ID 53873 // |
| 22331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22332 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22333 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22334 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22335 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22336 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22337 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs, (riscv_vmset_vl:{ *:[nxv16i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs, VR:{ *:[nxv16i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M2), |
| 22339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22340 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 22341 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 22342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22344 | GIR_RootConstrainSelectedInstOperands, |
| 22345 | // GIR_Coverage, 53873, |
| 22346 | GIR_EraseRootFromParent_Done, |
| 22347 | // Label 1549: @56321 |
| 22348 | GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(56354), // Rule ID 53860 // |
| 22349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22351 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22352 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMXOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M2), |
| 22354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22355 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22356 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22359 | GIR_RootConstrainSelectedInstOperands, |
| 22360 | // GIR_Coverage, 53860, |
| 22361 | GIR_EraseRootFromParent_Done, |
| 22362 | // Label 1550: @56354 |
| 22363 | GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(56387), // Rule ID 53861 // |
| 22364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22365 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22366 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22367 | // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2) => (PseudoVMXOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M2), |
| 22369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22370 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22371 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22374 | GIR_RootConstrainSelectedInstOperands, |
| 22375 | // GIR_Coverage, 53861, |
| 22376 | GIR_EraseRootFromParent_Done, |
| 22377 | // Label 1551: @56387 |
| 22378 | GIM_Reject, |
| 22379 | // Label 1525: @56388 |
| 22380 | GIM_Reject, |
| 22381 | // Label 1330: @56389 |
| 22382 | GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(56503), |
| 22383 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 22384 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 22385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 22386 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 22387 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 22388 | GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(56457), // Rule ID 48584 // |
| 22389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22390 | // (xor:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 22391 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 22392 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22393 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22394 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 22396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22397 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22398 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22399 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22403 | GIR_RootConstrainSelectedInstOperands, |
| 22404 | // GIR_Coverage, 48584, |
| 22405 | GIR_EraseRootFromParent_Done, |
| 22406 | // Label 1553: @56457 |
| 22407 | GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(56502), // Rule ID 48585 // |
| 22408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22409 | // (xor:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVXOR_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 22410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 22411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M2), |
| 22415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22416 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22417 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22418 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22422 | GIR_RootConstrainSelectedInstOperands, |
| 22423 | // GIR_Coverage, 48585, |
| 22424 | GIR_EraseRootFromParent_Done, |
| 22425 | // Label 1554: @56502 |
| 22426 | GIM_Reject, |
| 22427 | // Label 1552: @56503 |
| 22428 | GIM_Reject, |
| 22429 | // Label 1331: @56504 |
| 22430 | GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(56618), |
| 22431 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 22432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 22433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 22434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 22435 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 22436 | GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(56572), // Rule ID 48600 // |
| 22437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22438 | // (xor:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 22439 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 22440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22441 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 22444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22445 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22446 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22447 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 22450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22451 | GIR_RootConstrainSelectedInstOperands, |
| 22452 | // GIR_Coverage, 48600, |
| 22453 | GIR_EraseRootFromParent_Done, |
| 22454 | // Label 1556: @56572 |
| 22455 | GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(56617), // Rule ID 48601 // |
| 22456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22457 | // (xor:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 22458 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 22459 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22460 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 22463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22464 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22465 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 22469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22470 | GIR_RootConstrainSelectedInstOperands, |
| 22471 | // GIR_Coverage, 48601, |
| 22472 | GIR_EraseRootFromParent_Done, |
| 22473 | // Label 1557: @56617 |
| 22474 | GIM_Reject, |
| 22475 | // Label 1555: @56618 |
| 22476 | GIM_Reject, |
| 22477 | // Label 1332: @56619 |
| 22478 | GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(56733), |
| 22479 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 22480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 22481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 22482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 22483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 22484 | GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(56687), // Rule ID 48616 // |
| 22485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22486 | // (xor:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 22487 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 22488 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22489 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 22492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22493 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22494 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22495 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 22498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22499 | GIR_RootConstrainSelectedInstOperands, |
| 22500 | // GIR_Coverage, 48616, |
| 22501 | GIR_EraseRootFromParent_Done, |
| 22502 | // Label 1559: @56687 |
| 22503 | GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(56732), // Rule ID 48617 // |
| 22504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22505 | // (xor:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 22506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 22507 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 22511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22513 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 22514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 22517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 22518 | GIR_RootConstrainSelectedInstOperands, |
| 22519 | // GIR_Coverage, 48617, |
| 22520 | GIR_EraseRootFromParent_Done, |
| 22521 | // Label 1560: @56732 |
| 22522 | GIM_Reject, |
| 22523 | // Label 1558: @56733 |
| 22524 | GIM_Reject, |
| 22525 | // Label 1333: @56734 |
| 22526 | GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(58344), |
| 22527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22528 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22530 | GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(56818), // Rule ID 53880 // |
| 22531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22532 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22533 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 22534 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22535 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22536 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22537 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22538 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22539 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22540 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22541 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22542 | // (xor:{ *:[nxv32i1] } (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 22544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22549 | GIR_RootConstrainSelectedInstOperands, |
| 22550 | // GIR_Coverage, 53880, |
| 22551 | GIR_EraseRootFromParent_Done, |
| 22552 | // Label 1562: @56818 |
| 22553 | GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(56887), // Rule ID 53881 // |
| 22554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22555 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22556 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 22557 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22558 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22559 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22560 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22561 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22562 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22563 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22564 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22565 | // (xor:{ *:[nxv32i1] } (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 22567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22572 | GIR_RootConstrainSelectedInstOperands, |
| 22573 | // GIR_Coverage, 53881, |
| 22574 | GIR_EraseRootFromParent_Done, |
| 22575 | // Label 1563: @56887 |
| 22576 | GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(56956), // Rule ID 53882 // |
| 22577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22578 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22579 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 22580 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22581 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22582 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22583 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22584 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22585 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22586 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22587 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22588 | // (xor:{ *:[nxv32i1] } (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M4), |
| 22590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22592 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22595 | GIR_RootConstrainSelectedInstOperands, |
| 22596 | // GIR_Coverage, 53882, |
| 22597 | GIR_EraseRootFromParent_Done, |
| 22598 | // Label 1564: @56956 |
| 22599 | GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(57025), // Rule ID 53883 // |
| 22600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22601 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22602 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 22603 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22604 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22606 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22607 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22608 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22609 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22610 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22611 | // (xor:{ *:[nxv32i1] } (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M4), |
| 22613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22618 | GIR_RootConstrainSelectedInstOperands, |
| 22619 | // GIR_Coverage, 53883, |
| 22620 | GIR_EraseRootFromParent_Done, |
| 22621 | // Label 1565: @57025 |
| 22622 | GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(57091), // Rule ID 71396 // |
| 22623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22624 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22625 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22626 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22627 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22628 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22629 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22630 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22631 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22632 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22633 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22634 | // (xor:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs1), VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 22638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22641 | GIR_RootConstrainSelectedInstOperands, |
| 22642 | // GIR_Coverage, 71396, |
| 22643 | GIR_EraseRootFromParent_Done, |
| 22644 | // Label 1566: @57091 |
| 22645 | GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(57157), // Rule ID 71397 // |
| 22646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22647 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22648 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22649 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22650 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22651 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22652 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22653 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22654 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22656 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22657 | // (xor:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs1), VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 22661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22664 | GIR_RootConstrainSelectedInstOperands, |
| 22665 | // GIR_Coverage, 71397, |
| 22666 | GIR_EraseRootFromParent_Done, |
| 22667 | // Label 1567: @57157 |
| 22668 | GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(57223), // Rule ID 71394 // |
| 22669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22670 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22671 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22672 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22673 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22674 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22676 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22678 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22679 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22680 | // (xor:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22684 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22687 | GIR_RootConstrainSelectedInstOperands, |
| 22688 | // GIR_Coverage, 71394, |
| 22689 | GIR_EraseRootFromParent_Done, |
| 22690 | // Label 1568: @57223 |
| 22691 | GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(57289), // Rule ID 71395 // |
| 22692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22697 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22698 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22699 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22700 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22702 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22703 | // (xor:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22707 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 22708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22710 | GIR_RootConstrainSelectedInstOperands, |
| 22711 | // GIR_Coverage, 71395, |
| 22712 | GIR_EraseRootFromParent_Done, |
| 22713 | // Label 1569: @57289 |
| 22714 | GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(57358), // Rule ID 53884 // |
| 22715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22721 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22722 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22723 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22724 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22725 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22726 | // (xor:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22733 | GIR_RootConstrainSelectedInstOperands, |
| 22734 | // GIR_Coverage, 53884, |
| 22735 | GIR_EraseRootFromParent_Done, |
| 22736 | // Label 1570: @57358 |
| 22737 | GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(57427), // Rule ID 53885 // |
| 22738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22740 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22741 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22742 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22743 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22745 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22746 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22747 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22748 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22749 | // (xor:{ *:[nxv32i1] } (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 22754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22756 | GIR_RootConstrainSelectedInstOperands, |
| 22757 | // GIR_Coverage, 53885, |
| 22758 | GIR_EraseRootFromParent_Done, |
| 22759 | // Label 1571: @57427 |
| 22760 | GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(57496), // Rule ID 71390 // |
| 22761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22763 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22765 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22766 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 22767 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22768 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22769 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22770 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22771 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22772 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 22774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22776 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22779 | GIR_RootConstrainSelectedInstOperands, |
| 22780 | // GIR_Coverage, 71390, |
| 22781 | GIR_EraseRootFromParent_Done, |
| 22782 | // Label 1572: @57496 |
| 22783 | GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(57565), // Rule ID 71391 // |
| 22784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22785 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22786 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22787 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22788 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22789 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 22790 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22791 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22792 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22793 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22794 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22795 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 22797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22802 | GIR_RootConstrainSelectedInstOperands, |
| 22803 | // GIR_Coverage, 71391, |
| 22804 | GIR_EraseRootFromParent_Done, |
| 22805 | // Label 1573: @57565 |
| 22806 | GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(57634), // Rule ID 71392 // |
| 22807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22808 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22809 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22810 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22811 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22812 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 22813 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22814 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22815 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22816 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22817 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22818 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M4), |
| 22820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22825 | GIR_RootConstrainSelectedInstOperands, |
| 22826 | // GIR_Coverage, 71392, |
| 22827 | GIR_EraseRootFromParent_Done, |
| 22828 | // Label 1574: @57634 |
| 22829 | GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(57703), // Rule ID 71393 // |
| 22830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22831 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22832 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22833 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22834 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22835 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 22836 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22837 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22838 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22839 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22840 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22841 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M4), |
| 22843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22848 | GIR_RootConstrainSelectedInstOperands, |
| 22849 | // GIR_Coverage, 71393, |
| 22850 | GIR_EraseRootFromParent_Done, |
| 22851 | // Label 1575: @57703 |
| 22852 | GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(57772), // Rule ID 71398 // |
| 22853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22854 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22855 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22856 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22857 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22858 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22859 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22860 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22861 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22862 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22863 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22864 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22871 | GIR_RootConstrainSelectedInstOperands, |
| 22872 | // GIR_Coverage, 71398, |
| 22873 | GIR_EraseRootFromParent_Done, |
| 22874 | // Label 1576: @57772 |
| 22875 | GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(57841), // Rule ID 71399 // |
| 22876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22877 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22878 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22879 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22880 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 22881 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22882 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22883 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22884 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22885 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22886 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22887 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 22891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 22892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22894 | GIR_RootConstrainSelectedInstOperands, |
| 22895 | // GIR_Coverage, 71399, |
| 22896 | GIR_EraseRootFromParent_Done, |
| 22897 | // Label 1577: @57841 |
| 22898 | GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(57907), // Rule ID 71402 // |
| 22899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22901 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22902 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22903 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22904 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22905 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22906 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22907 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22908 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22909 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22910 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs1)) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 22914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22917 | GIR_RootConstrainSelectedInstOperands, |
| 22918 | // GIR_Coverage, 71402, |
| 22919 | GIR_EraseRootFromParent_Done, |
| 22920 | // Label 1578: @57907 |
| 22921 | GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(57973), // Rule ID 71403 // |
| 22922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22924 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22925 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22926 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22927 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22928 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22929 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22930 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22931 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22932 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22933 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs1)) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 22937 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22940 | GIR_RootConstrainSelectedInstOperands, |
| 22941 | // GIR_Coverage, 71403, |
| 22942 | GIR_EraseRootFromParent_Done, |
| 22943 | // Label 1579: @57973 |
| 22944 | GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(58039), // Rule ID 71400 // |
| 22945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22948 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22949 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22950 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22951 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22952 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22953 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22954 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22955 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22956 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22960 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22963 | GIR_RootConstrainSelectedInstOperands, |
| 22964 | // GIR_Coverage, 71400, |
| 22965 | GIR_EraseRootFromParent_Done, |
| 22966 | // Label 1580: @58039 |
| 22967 | GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(58105), // Rule ID 71401 // |
| 22968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 22969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22970 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22971 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 22972 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 22973 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv32s1, |
| 22974 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22975 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22976 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22977 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22978 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 22979 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs2, (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 22980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M4), |
| 22981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 22982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 22983 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 22984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 22985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22986 | GIR_RootConstrainSelectedInstOperands, |
| 22987 | // GIR_Coverage, 71401, |
| 22988 | GIR_EraseRootFromParent_Done, |
| 22989 | // Label 1581: @58105 |
| 22990 | GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(58148), // Rule ID 71416 // |
| 22991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 22992 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22993 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 22994 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 22996 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22997 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv32i1] }:$rs) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs, VR:{ *:[nxv32i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 22998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 22999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23000 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23001 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23004 | GIR_RootConstrainSelectedInstOperands, |
| 23005 | // GIR_Coverage, 71416, |
| 23006 | GIR_EraseRootFromParent_Done, |
| 23007 | // Label 1582: @58148 |
| 23008 | GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(58191), // Rule ID 71417 // |
| 23009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23011 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23012 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23014 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23015 | // (xor:{ *:[nxv32i1] } (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv32i1] }:$rs) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs, VR:{ *:[nxv32i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 23017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23018 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23019 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23022 | GIR_RootConstrainSelectedInstOperands, |
| 23023 | // GIR_Coverage, 71417, |
| 23024 | GIR_EraseRootFromParent_Done, |
| 23025 | // Label 1583: @58191 |
| 23026 | GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(58234), // Rule ID 53890 // |
| 23027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23028 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23029 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23030 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23031 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23032 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23033 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs, VR:{ *:[nxv32i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 23035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23036 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23037 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23040 | GIR_RootConstrainSelectedInstOperands, |
| 23041 | // GIR_Coverage, 53890, |
| 23042 | GIR_EraseRootFromParent_Done, |
| 23043 | // Label 1584: @58234 |
| 23044 | GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(58277), // Rule ID 53891 // |
| 23045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23046 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23050 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23051 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs, (riscv_vmset_vl:{ *:[nxv32i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs, VR:{ *:[nxv32i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M4), |
| 23053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23054 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23055 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23058 | GIR_RootConstrainSelectedInstOperands, |
| 23059 | // GIR_Coverage, 53891, |
| 23060 | GIR_EraseRootFromParent_Done, |
| 23061 | // Label 1585: @58277 |
| 23062 | GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(58310), // Rule ID 53878 // |
| 23063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23064 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23066 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMXOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M4), |
| 23068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23069 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23070 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23073 | GIR_RootConstrainSelectedInstOperands, |
| 23074 | // GIR_Coverage, 53878, |
| 23075 | GIR_EraseRootFromParent_Done, |
| 23076 | // Label 1586: @58310 |
| 23077 | GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(58343), // Rule ID 53879 // |
| 23078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23080 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23081 | // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2) => (PseudoVMXOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M4), |
| 23083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23084 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23085 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23088 | GIR_RootConstrainSelectedInstOperands, |
| 23089 | // GIR_Coverage, 53879, |
| 23090 | GIR_EraseRootFromParent_Done, |
| 23091 | // Label 1587: @58343 |
| 23092 | GIM_Reject, |
| 23093 | // Label 1561: @58344 |
| 23094 | GIM_Reject, |
| 23095 | // Label 1334: @58345 |
| 23096 | GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(58459), |
| 23097 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 23098 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 23099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 23100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 23101 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 23102 | GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(58413), // Rule ID 48588 // |
| 23103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23104 | // (xor:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 23105 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 23106 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23107 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23108 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 23110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23111 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23112 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23113 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23117 | GIR_RootConstrainSelectedInstOperands, |
| 23118 | // GIR_Coverage, 48588, |
| 23119 | GIR_EraseRootFromParent_Done, |
| 23120 | // Label 1589: @58413 |
| 23121 | GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(58458), // Rule ID 48589 // |
| 23122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23123 | // (xor:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVXOR_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 23124 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 23125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M4), |
| 23129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23130 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23131 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23132 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23136 | GIR_RootConstrainSelectedInstOperands, |
| 23137 | // GIR_Coverage, 48589, |
| 23138 | GIR_EraseRootFromParent_Done, |
| 23139 | // Label 1590: @58458 |
| 23140 | GIM_Reject, |
| 23141 | // Label 1588: @58459 |
| 23142 | GIM_Reject, |
| 23143 | // Label 1335: @58460 |
| 23144 | GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(58574), |
| 23145 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 23146 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 23147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 23148 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 23149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 23150 | GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(58528), // Rule ID 48604 // |
| 23151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23152 | // (xor:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 23153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 23154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 23158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23161 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 23164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23165 | GIR_RootConstrainSelectedInstOperands, |
| 23166 | // GIR_Coverage, 48604, |
| 23167 | GIR_EraseRootFromParent_Done, |
| 23168 | // Label 1592: @58528 |
| 23169 | GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(58573), // Rule ID 48605 // |
| 23170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23171 | // (xor:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 23172 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 23173 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23174 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 23177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23179 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23180 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 23183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23184 | GIR_RootConstrainSelectedInstOperands, |
| 23185 | // GIR_Coverage, 48605, |
| 23186 | GIR_EraseRootFromParent_Done, |
| 23187 | // Label 1593: @58573 |
| 23188 | GIM_Reject, |
| 23189 | // Label 1591: @58574 |
| 23190 | GIM_Reject, |
| 23191 | // Label 1336: @58575 |
| 23192 | GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(60185), |
| 23193 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23196 | GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(58659), // Rule ID 53898 // |
| 23197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23198 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23199 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 23200 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23201 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23202 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23203 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23204 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23205 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23206 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23207 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23208 | // (xor:{ *:[nxv64i1] } (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 23213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23215 | GIR_RootConstrainSelectedInstOperands, |
| 23216 | // GIR_Coverage, 53898, |
| 23217 | GIR_EraseRootFromParent_Done, |
| 23218 | // Label 1595: @58659 |
| 23219 | GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(58728), // Rule ID 53899 // |
| 23220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23221 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23222 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 23223 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23224 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23225 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23226 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23227 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23228 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23229 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23230 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23231 | // (xor:{ *:[nxv64i1] } (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23234 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 23236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23238 | GIR_RootConstrainSelectedInstOperands, |
| 23239 | // GIR_Coverage, 53899, |
| 23240 | GIR_EraseRootFromParent_Done, |
| 23241 | // Label 1596: @58728 |
| 23242 | GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(58797), // Rule ID 53900 // |
| 23243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23244 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23245 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 23246 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23247 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23248 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23249 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23250 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23251 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23252 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23253 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23254 | // (xor:{ *:[nxv64i1] } (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })) => (PseudoVMNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M8), |
| 23256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23257 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 23259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23261 | GIR_RootConstrainSelectedInstOperands, |
| 23262 | // GIR_Coverage, 53900, |
| 23263 | GIR_EraseRootFromParent_Done, |
| 23264 | // Label 1597: @58797 |
| 23265 | GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(58866), // Rule ID 53901 // |
| 23266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23267 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23268 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 23269 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23270 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23271 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23272 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23273 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23274 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23275 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23276 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23277 | // (xor:{ *:[nxv64i1] } (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })) => (PseudoVMNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M8), |
| 23279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23280 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 23282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23284 | GIR_RootConstrainSelectedInstOperands, |
| 23285 | // GIR_Coverage, 53901, |
| 23286 | GIR_EraseRootFromParent_Done, |
| 23287 | // Label 1598: @58866 |
| 23288 | GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(58932), // Rule ID 71424 // |
| 23289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23290 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23291 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23292 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23293 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23294 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23295 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23296 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23297 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23298 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23299 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23300 | // (xor:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs1), VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 23304 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23307 | GIR_RootConstrainSelectedInstOperands, |
| 23308 | // GIR_Coverage, 71424, |
| 23309 | GIR_EraseRootFromParent_Done, |
| 23310 | // Label 1599: @58932 |
| 23311 | GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(58998), // Rule ID 71425 // |
| 23312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23316 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23317 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23318 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23319 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23320 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23321 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23322 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23323 | // (xor:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs1), VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23326 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 23327 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23330 | GIR_RootConstrainSelectedInstOperands, |
| 23331 | // GIR_Coverage, 71425, |
| 23332 | GIR_EraseRootFromParent_Done, |
| 23333 | // Label 1600: @58998 |
| 23334 | GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(59064), // Rule ID 71422 // |
| 23335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23336 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23337 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23338 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23339 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23340 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23341 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 23342 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23343 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23344 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23345 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23346 | // (xor:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23350 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23353 | GIR_RootConstrainSelectedInstOperands, |
| 23354 | // GIR_Coverage, 71422, |
| 23355 | GIR_EraseRootFromParent_Done, |
| 23356 | // Label 1601: @59064 |
| 23357 | GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(59130), // Rule ID 71423 // |
| 23358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23359 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23360 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23361 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23362 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23363 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23364 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 23365 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23366 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23368 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23369 | // (xor:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23373 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23376 | GIR_RootConstrainSelectedInstOperands, |
| 23377 | // GIR_Coverage, 71423, |
| 23378 | GIR_EraseRootFromParent_Done, |
| 23379 | // Label 1602: @59130 |
| 23380 | GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(59199), // Rule ID 53902 // |
| 23381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23382 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23383 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23384 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23385 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23386 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23387 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23388 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23389 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23390 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23391 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23392 | // (xor:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 23397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23399 | GIR_RootConstrainSelectedInstOperands, |
| 23400 | // GIR_Coverage, 53902, |
| 23401 | GIR_EraseRootFromParent_Done, |
| 23402 | // Label 1603: @59199 |
| 23403 | GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(59268), // Rule ID 53903 // |
| 23404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23405 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23406 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23407 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23408 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23409 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23410 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23411 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23412 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23413 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23414 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23415 | // (xor:{ *:[nxv64i1] } (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2), (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 |
| 23420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23422 | GIR_RootConstrainSelectedInstOperands, |
| 23423 | // GIR_Coverage, 53903, |
| 23424 | GIR_EraseRootFromParent_Done, |
| 23425 | // Label 1604: @59268 |
| 23426 | GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(59337), // Rule ID 71418 // |
| 23427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23428 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23429 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23430 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23431 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23432 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 23433 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23434 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23435 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23436 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23437 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23438 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 23442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 23443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23445 | GIR_RootConstrainSelectedInstOperands, |
| 23446 | // GIR_Coverage, 71418, |
| 23447 | GIR_EraseRootFromParent_Done, |
| 23448 | // Label 1605: @59337 |
| 23449 | GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(59406), // Rule ID 71419 // |
| 23450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23452 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23454 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23455 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 23456 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23457 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23458 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23459 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23460 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23461 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 23465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 23466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23468 | GIR_RootConstrainSelectedInstOperands, |
| 23469 | // GIR_Coverage, 71419, |
| 23470 | GIR_EraseRootFromParent_Done, |
| 23471 | // Label 1606: @59406 |
| 23472 | GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(59475), // Rule ID 71420 // |
| 23473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23474 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23475 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23476 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23477 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23478 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 23479 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23480 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23481 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23482 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23483 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23484 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M8), |
| 23486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 23488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 23489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23491 | GIR_RootConstrainSelectedInstOperands, |
| 23492 | // GIR_Coverage, 71420, |
| 23493 | GIR_EraseRootFromParent_Done, |
| 23494 | // Label 1607: @59475 |
| 23495 | GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(59544), // Rule ID 71421 // |
| 23496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23497 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23498 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23499 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23500 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23501 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 23502 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23503 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23504 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23505 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23506 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23507 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNOR_MM_M8), |
| 23509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23510 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 23511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 23512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23514 | GIR_RootConstrainSelectedInstOperands, |
| 23515 | // GIR_Coverage, 71421, |
| 23516 | GIR_EraseRootFromParent_Done, |
| 23517 | // Label 1608: @59544 |
| 23518 | GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(59613), // Rule ID 71426 // |
| 23519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23520 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23521 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23522 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23523 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23524 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23525 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23526 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23527 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23528 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23529 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23530 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 23534 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 23535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23537 | GIR_RootConstrainSelectedInstOperands, |
| 23538 | // GIR_Coverage, 71426, |
| 23539 | GIR_EraseRootFromParent_Done, |
| 23540 | // Label 1609: @59613 |
| 23541 | GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(59682), // Rule ID 71427 // |
| 23542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23543 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23544 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23545 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23546 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 23547 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23548 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23549 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23550 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23551 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23552 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23553 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 |
| 23557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs2 |
| 23558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23560 | GIR_RootConstrainSelectedInstOperands, |
| 23561 | // GIR_Coverage, 71427, |
| 23562 | GIR_EraseRootFromParent_Done, |
| 23563 | // Label 1610: @59682 |
| 23564 | GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(59748), // Rule ID 71430 // |
| 23565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23566 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23568 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23569 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23570 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23571 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23572 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23573 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23574 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23575 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23576 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs1)) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 23580 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 23581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23583 | GIR_RootConstrainSelectedInstOperands, |
| 23584 | // GIR_Coverage, 71430, |
| 23585 | GIR_EraseRootFromParent_Done, |
| 23586 | // Label 1611: @59748 |
| 23587 | GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(59814), // Rule ID 71431 // |
| 23588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23590 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23591 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23592 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23593 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23594 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23595 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23596 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23597 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23598 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23599 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs1)) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs1 |
| 23603 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 23604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23606 | GIR_RootConstrainSelectedInstOperands, |
| 23607 | // GIR_Coverage, 71431, |
| 23608 | GIR_EraseRootFromParent_Done, |
| 23609 | // Label 1612: @59814 |
| 23610 | GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(59880), // Rule ID 71428 // |
| 23611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23612 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23613 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23614 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23615 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23616 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23617 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23618 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 23619 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23620 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23621 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23622 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }))) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23626 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 23627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23629 | GIR_RootConstrainSelectedInstOperands, |
| 23630 | // GIR_Coverage, 71428, |
| 23631 | GIR_EraseRootFromParent_Done, |
| 23632 | // Label 1613: @59880 |
| 23633 | GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(59946), // Rule ID 71429 // |
| 23634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23635 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 23638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 23639 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv64s1, |
| 23640 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23641 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 23642 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23643 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 23644 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 23645 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs2, (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }))) => (PseudoVMXNOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXNOR_MM_M8), |
| 23647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 23649 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 23650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23652 | GIR_RootConstrainSelectedInstOperands, |
| 23653 | // GIR_Coverage, 71429, |
| 23654 | GIR_EraseRootFromParent_Done, |
| 23655 | // Label 1614: @59946 |
| 23656 | GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(59989), // Rule ID 71444 // |
| 23657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23658 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23659 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23660 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23662 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23663 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv64i1] }:$rs) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs, VR:{ *:[nxv64i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23667 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23670 | GIR_RootConstrainSelectedInstOperands, |
| 23671 | // GIR_Coverage, 71444, |
| 23672 | GIR_EraseRootFromParent_Done, |
| 23673 | // Label 1615: @59989 |
| 23674 | GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(60032), // Rule ID 71445 // |
| 23675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23676 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23677 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23678 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23680 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23681 | // (xor:{ *:[nxv64i1] } (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv64i1] }:$rs) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs, VR:{ *:[nxv64i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23684 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23685 | GIR_RootToRootCopy, /*OpIdx*/2, // rs |
| 23686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23688 | GIR_RootConstrainSelectedInstOperands, |
| 23689 | // GIR_Coverage, 71445, |
| 23690 | GIR_EraseRootFromParent_Done, |
| 23691 | // Label 1616: @60032 |
| 23692 | GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(60075), // Rule ID 53908 // |
| 23693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23695 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23696 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23697 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23698 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23699 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i64] })) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs, VR:{ *:[nxv64i1] }:$rs, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23702 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23706 | GIR_RootConstrainSelectedInstOperands, |
| 23707 | // GIR_Coverage, 53908, |
| 23708 | GIR_EraseRootFromParent_Done, |
| 23709 | // Label 1617: @60075 |
| 23710 | GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(60118), // Rule ID 53909 // |
| 23711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23713 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23714 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(RISCV::G_VMSET_VL), |
| 23715 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23716 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23717 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs, (riscv_vmset_vl:{ *:[nxv64i1] } srcvalue:{ *:[i32] })) => (PseudoVMNAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs, VR:{ *:[nxv64i1] }:$rs, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMNAND_MM_M8), |
| 23719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23720 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23721 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 23722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23724 | GIR_RootConstrainSelectedInstOperands, |
| 23725 | // GIR_Coverage, 53909, |
| 23726 | GIR_EraseRootFromParent_Done, |
| 23727 | // Label 1618: @60118 |
| 23728 | GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(60151), // Rule ID 53896 // |
| 23729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23730 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23731 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23732 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMXOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) |
| 23733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M8), |
| 23734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23735 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23736 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23739 | GIR_RootConstrainSelectedInstOperands, |
| 23740 | // GIR_Coverage, 53896, |
| 23741 | GIR_EraseRootFromParent_Done, |
| 23742 | // Label 1619: @60151 |
| 23743 | GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(60184), // Rule ID 53897 // |
| 23744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23745 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23746 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 23747 | // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2) => (PseudoVMXOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 23748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMXOR_MM_M8), |
| 23749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23750 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23751 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23754 | GIR_RootConstrainSelectedInstOperands, |
| 23755 | // GIR_Coverage, 53897, |
| 23756 | GIR_EraseRootFromParent_Done, |
| 23757 | // Label 1620: @60184 |
| 23758 | GIM_Reject, |
| 23759 | // Label 1594: @60185 |
| 23760 | GIM_Reject, |
| 23761 | // Label 1337: @60186 |
| 23762 | GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(60300), |
| 23763 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 23764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 23765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 23766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 23767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 23768 | GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(60254), // Rule ID 48592 // |
| 23769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 23770 | // (xor:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 23771 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 23772 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23773 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23774 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 23776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23777 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23778 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23779 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23783 | GIR_RootConstrainSelectedInstOperands, |
| 23784 | // GIR_Coverage, 48592, |
| 23785 | GIR_EraseRootFromParent_Done, |
| 23786 | // Label 1622: @60254 |
| 23787 | GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(60299), // Rule ID 48593 // |
| 23788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 23789 | // (xor:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVXOR_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 23790 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 23791 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23792 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVXOR_VV_M8), |
| 23795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23796 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23797 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23798 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 23799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 23800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 23802 | GIR_RootConstrainSelectedInstOperands, |
| 23803 | // GIR_Coverage, 48593, |
| 23804 | GIR_EraseRootFromParent_Done, |
| 23805 | // Label 1623: @60299 |
| 23806 | GIM_Reject, |
| 23807 | // Label 1621: @60300 |
| 23808 | GIM_Reject, |
| 23809 | // Label 1338: @60301 |
| 23810 | GIM_Reject, |
| 23811 | // Label 10: @60302 |
| 23812 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 1626*/ GIMT_Encode4(60614), |
| 23813 | /*GILLT_s32*//*Label 1624*/ GIMT_Encode4(60321), |
| 23814 | /*GILLT_s64*//*Label 1625*/ GIMT_Encode4(60504), |
| 23815 | // Label 1624: @60321 |
| 23816 | GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(60503), |
| 23817 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 23818 | GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(60352), // Rule ID 1514 // |
| 23819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 23820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 23821 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23822 | // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1) |
| 23823 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMV_W_X), |
| 23824 | GIR_RootConstrainSelectedInstOperands, |
| 23825 | // GIR_Coverage, 1514, |
| 23826 | GIR_Done, |
| 23827 | // Label 1628: @60352 |
| 23828 | GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(60375), // Rule ID 1515 // |
| 23829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 23830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 23831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23832 | // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1) |
| 23833 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMV_W_X), |
| 23834 | GIR_RootConstrainSelectedInstOperands, |
| 23835 | // GIR_Coverage, 1515, |
| 23836 | GIR_Done, |
| 23837 | // Label 1629: @60375 |
| 23838 | GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(60398), // Rule ID 1516 // |
| 23839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 23840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 23842 | // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) |
| 23843 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMV_X_W), |
| 23844 | GIR_RootConstrainSelectedInstOperands, |
| 23845 | // GIR_Coverage, 1516, |
| 23846 | GIR_Done, |
| 23847 | // Label 1630: @60398 |
| 23848 | GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(60421), // Rule ID 1517 // |
| 23849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 23850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23851 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 23852 | // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) |
| 23853 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMV_X_W), |
| 23854 | GIR_RootConstrainSelectedInstOperands, |
| 23855 | // GIR_Coverage, 1517, |
| 23856 | GIR_Done, |
| 23857 | // Label 1631: @60421 |
| 23858 | GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(60448), // Rule ID 1518 // |
| 23859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 23860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 23861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23862 | // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$rs1, GPRF32:{ *:[i32] }) |
| 23863 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23864 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 23865 | // GIR_Coverage, 1518, |
| 23866 | GIR_Done, |
| 23867 | // Label 1632: @60448 |
| 23868 | GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(60475), // Rule ID 1519 // |
| 23869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 23870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 23871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23872 | // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$rs1, GPRF32:{ *:[i32] }) |
| 23873 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23874 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 23875 | // GIR_Coverage, 1519, |
| 23876 | GIR_Done, |
| 23877 | // Label 1633: @60475 |
| 23878 | GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(60502), // Rule ID 1520 // |
| 23879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx), |
| 23880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 23882 | // (bitconvert:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1, GPR:{ *:[i32] }) |
| 23883 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23884 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRRegClassID), |
| 23885 | // GIR_Coverage, 1520, |
| 23886 | GIR_Done, |
| 23887 | // Label 1634: @60502 |
| 23888 | GIM_Reject, |
| 23889 | // Label 1627: @60503 |
| 23890 | GIM_Reject, |
| 23891 | // Label 1625: @60504 |
| 23892 | GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(60613), |
| 23893 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 23894 | GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(60535), // Rule ID 1954 // |
| 23895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 23896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 23897 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23898 | // (bitconvert:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i64] }:$rs1) |
| 23899 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMV_D_X), |
| 23900 | GIR_RootConstrainSelectedInstOperands, |
| 23901 | // GIR_Coverage, 1954, |
| 23902 | GIR_Done, |
| 23903 | // Label 1636: @60535 |
| 23904 | GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(60558), // Rule ID 1955 // |
| 23905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 23906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23907 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 23908 | // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) |
| 23909 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMV_X_D), |
| 23910 | GIR_RootConstrainSelectedInstOperands, |
| 23911 | // GIR_Coverage, 1955, |
| 23912 | GIR_Done, |
| 23913 | // Label 1637: @60558 |
| 23914 | GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(60585), // Rule ID 1982 // |
| 23915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 23916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23917 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23918 | // (bitconvert:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (COPY_TO_REGCLASS:{ *:[f64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }) |
| 23919 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23920 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRRegClassID), |
| 23921 | // GIR_Coverage, 1982, |
| 23922 | GIR_Done, |
| 23923 | // Label 1638: @60585 |
| 23924 | GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(60612), // Rule ID 1983 // |
| 23925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 23926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23927 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 23928 | // (bitconvert:{ *:[i64] } GPR:{ *:[f64] }:$rs1) => (COPY_TO_REGCLASS:{ *:[i64] } GPR:{ *:[f64] }:$rs1, GPR:{ *:[i32] }) |
| 23929 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23930 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRRegClassID), |
| 23931 | // GIR_Coverage, 1983, |
| 23932 | GIR_Done, |
| 23933 | // Label 1639: @60612 |
| 23934 | GIM_Reject, |
| 23935 | // Label 1635: @60613 |
| 23936 | GIM_Reject, |
| 23937 | // Label 1626: @60614 |
| 23938 | GIM_Reject, |
| 23939 | // Label 11: @60615 |
| 23940 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 1643*/ GIMT_Encode4(60812), |
| 23941 | /*GILLT_s16*//*Label 1640*/ GIMT_Encode4(60638), |
| 23942 | /*GILLT_s32*//*Label 1641*/ GIMT_Encode4(60696), |
| 23943 | /*GILLT_s64*//*Label 1642*/ GIMT_Encode4(60754), |
| 23944 | // Label 1640: @60638 |
| 23945 | GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(60695), |
| 23946 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 23947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 23948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 23949 | GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(60674), // Rule ID 2592 // |
| 23950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 23951 | // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 23952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 23953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23954 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23956 | GIR_RootConstrainSelectedInstOperands, |
| 23957 | // GIR_Coverage, 2592, |
| 23958 | GIR_EraseRootFromParent_Done, |
| 23959 | // Label 1645: @60674 |
| 23960 | GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(60694), // Rule ID 2593 // |
| 23961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 23962 | // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 1:{ *:[i32] }) |
| 23963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 23964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23965 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23967 | GIR_RootConstrainSelectedInstOperands, |
| 23968 | // GIR_Coverage, 2593, |
| 23969 | GIR_EraseRootFromParent_Done, |
| 23970 | // Label 1646: @60694 |
| 23971 | GIM_Reject, |
| 23972 | // Label 1644: @60695 |
| 23973 | GIM_Reject, |
| 23974 | // Label 1641: @60696 |
| 23975 | GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(60753), |
| 23976 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 23977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 23978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 23979 | GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(60732), // Rule ID 2514 // |
| 23980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode0), |
| 23981 | // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 23982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 23983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23984 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23986 | GIR_RootConstrainSelectedInstOperands, |
| 23987 | // GIR_Coverage, 2514, |
| 23988 | GIR_EraseRootFromParent_Done, |
| 23989 | // Label 1648: @60732 |
| 23990 | GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(60752), // Rule ID 2515 // |
| 23991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode1), |
| 23992 | // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 1:{ *:[i32] }) |
| 23993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 23994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 23995 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 23996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23997 | GIR_RootConstrainSelectedInstOperands, |
| 23998 | // GIR_Coverage, 2515, |
| 23999 | GIR_EraseRootFromParent_Done, |
| 24000 | // Label 1649: @60752 |
| 24001 | GIM_Reject, |
| 24002 | // Label 1647: @60753 |
| 24003 | GIM_Reject, |
| 24004 | // Label 1642: @60754 |
| 24005 | GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(60811), |
| 24006 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24008 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24009 | GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(60790), // Rule ID 2552 // |
| 24010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 24011 | // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 24012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 24013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24014 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24016 | GIR_RootConstrainSelectedInstOperands, |
| 24017 | // GIR_Coverage, 2552, |
| 24018 | GIR_EraseRootFromParent_Done, |
| 24019 | // Label 1651: @60790 |
| 24020 | GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(60810), // Rule ID 2553 // |
| 24021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 24022 | // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) |
| 24023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 24024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24025 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24027 | GIR_RootConstrainSelectedInstOperands, |
| 24028 | // GIR_Coverage, 2553, |
| 24029 | GIR_EraseRootFromParent_Done, |
| 24030 | // Label 1652: @60810 |
| 24031 | GIM_Reject, |
| 24032 | // Label 1650: @60811 |
| 24033 | GIM_Reject, |
| 24034 | // Label 1643: @60812 |
| 24035 | GIM_Reject, |
| 24036 | // Label 12: @60813 |
| 24037 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 1656*/ GIMT_Encode4(61010), |
| 24038 | /*GILLT_s16*//*Label 1653*/ GIMT_Encode4(60836), |
| 24039 | /*GILLT_s32*//*Label 1654*/ GIMT_Encode4(60894), |
| 24040 | /*GILLT_s64*//*Label 1655*/ GIMT_Encode4(60952), |
| 24041 | // Label 1653: @60836 |
| 24042 | GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(60893), |
| 24043 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24045 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24046 | GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(60872), // Rule ID 2576 // |
| 24047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 24048 | // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 24049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 24050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24051 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 24053 | GIR_RootConstrainSelectedInstOperands, |
| 24054 | // GIR_Coverage, 2576, |
| 24055 | GIR_EraseRootFromParent_Done, |
| 24056 | // Label 1658: @60872 |
| 24057 | GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(60892), // Rule ID 2577 // |
| 24058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 24059 | // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 4:{ *:[i32] }) |
| 24060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 24061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24062 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 24064 | GIR_RootConstrainSelectedInstOperands, |
| 24065 | // GIR_Coverage, 2577, |
| 24066 | GIR_EraseRootFromParent_Done, |
| 24067 | // Label 1659: @60892 |
| 24068 | GIM_Reject, |
| 24069 | // Label 1657: @60893 |
| 24070 | GIM_Reject, |
| 24071 | // Label 1654: @60894 |
| 24072 | GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(60951), |
| 24073 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 24075 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 24076 | GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(60930), // Rule ID 2502 // |
| 24077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode0), |
| 24078 | // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 4:{ *:[i64] }) |
| 24079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 24080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24081 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 24083 | GIR_RootConstrainSelectedInstOperands, |
| 24084 | // GIR_Coverage, 2502, |
| 24085 | GIR_EraseRootFromParent_Done, |
| 24086 | // Label 1661: @60930 |
| 24087 | GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(60950), // Rule ID 2503 // |
| 24088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode1), |
| 24089 | // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 4:{ *:[i32] }) |
| 24090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 24091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24092 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 24094 | GIR_RootConstrainSelectedInstOperands, |
| 24095 | // GIR_Coverage, 2503, |
| 24096 | GIR_EraseRootFromParent_Done, |
| 24097 | // Label 1662: @60950 |
| 24098 | GIM_Reject, |
| 24099 | // Label 1660: @60951 |
| 24100 | GIM_Reject, |
| 24101 | // Label 1655: @60952 |
| 24102 | GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(61009), |
| 24103 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24105 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24106 | GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(60988), // Rule ID 2536 // |
| 24107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 24108 | // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 24109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 24110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24111 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 24113 | GIR_RootConstrainSelectedInstOperands, |
| 24114 | // GIR_Coverage, 2536, |
| 24115 | GIR_EraseRootFromParent_Done, |
| 24116 | // Label 1664: @60988 |
| 24117 | GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(61008), // Rule ID 2537 // |
| 24118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 24119 | // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 4:{ *:[i32] }) |
| 24120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 24121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24122 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 24124 | GIR_RootConstrainSelectedInstOperands, |
| 24125 | // GIR_Coverage, 2537, |
| 24126 | GIR_EraseRootFromParent_Done, |
| 24127 | // Label 1665: @61008 |
| 24128 | GIM_Reject, |
| 24129 | // Label 1663: @61009 |
| 24130 | GIM_Reject, |
| 24131 | // Label 1656: @61010 |
| 24132 | GIM_Reject, |
| 24133 | // Label 13: @61011 |
| 24134 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 1668*/ GIMT_Encode4(61908), |
| 24135 | /*GILLT_s32*//*Label 1666*/ GIMT_Encode4(61030), |
| 24136 | /*GILLT_s64*//*Label 1667*/ GIMT_Encode4(61615), |
| 24137 | // Label 1666: @61030 |
| 24138 | GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(61061), // Rule ID 1533 // |
| 24139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 24140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 24143 | // (lrint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 24144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 24145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24146 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24148 | GIR_RootConstrainSelectedInstOperands, |
| 24149 | // GIR_Coverage, 1533, |
| 24150 | GIR_EraseRootFromParent_Done, |
| 24151 | // Label 1669: @61061 |
| 24152 | GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(61092), // Rule ID 1534 // |
| 24153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 24154 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 24157 | // (lrint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 24158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 24159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24162 | GIR_RootConstrainSelectedInstOperands, |
| 24163 | // GIR_Coverage, 1534, |
| 24164 | GIR_EraseRootFromParent_Done, |
| 24165 | // Label 1670: @61092 |
| 24166 | GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(61123), // Rule ID 1559 // |
| 24167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 24168 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24169 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24170 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 24171 | // (lrint:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 24172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 24173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24174 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24176 | GIR_RootConstrainSelectedInstOperands, |
| 24177 | // GIR_Coverage, 1559, |
| 24178 | GIR_EraseRootFromParent_Done, |
| 24179 | // Label 1671: @61123 |
| 24180 | GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(61154), // Rule ID 1560 // |
| 24181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 24182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 24185 | // (lrint:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 24186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 24187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24188 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24190 | GIR_RootConstrainSelectedInstOperands, |
| 24191 | // GIR_Coverage, 1560, |
| 24192 | GIR_EraseRootFromParent_Done, |
| 24193 | // Label 1672: @61154 |
| 24194 | GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(61185), // Rule ID 1914 // |
| 24195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 24196 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24198 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24199 | // (lrint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 24200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D), |
| 24201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24202 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24204 | GIR_RootConstrainSelectedInstOperands, |
| 24205 | // GIR_Coverage, 1914, |
| 24206 | GIR_EraseRootFromParent_Done, |
| 24207 | // Label 1673: @61185 |
| 24208 | GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(61216), // Rule ID 1915 // |
| 24209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 24210 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24213 | // (lrint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 24214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D), |
| 24215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24216 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24218 | GIR_RootConstrainSelectedInstOperands, |
| 24219 | // GIR_Coverage, 1915, |
| 24220 | GIR_EraseRootFromParent_Done, |
| 24221 | // Label 1674: @61216 |
| 24222 | GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(61247), // Rule ID 1940 // |
| 24223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 24224 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24226 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 24227 | // (lrint:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_W_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 24228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D_IN32X), |
| 24229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24230 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24232 | GIR_RootConstrainSelectedInstOperands, |
| 24233 | // GIR_Coverage, 1940, |
| 24234 | GIR_EraseRootFromParent_Done, |
| 24235 | // Label 1675: @61247 |
| 24236 | GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(61278), // Rule ID 1941 // |
| 24237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 24238 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24240 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 24241 | // (lrint:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_W_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 24242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D_IN32X), |
| 24243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24244 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24246 | GIR_RootConstrainSelectedInstOperands, |
| 24247 | // GIR_Coverage, 1941, |
| 24248 | GIR_EraseRootFromParent_Done, |
| 24249 | // Label 1676: @61278 |
| 24250 | GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(61309), // Rule ID 2250 // |
| 24251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 24252 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24255 | // (lrint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 24256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H), |
| 24257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24258 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24260 | GIR_RootConstrainSelectedInstOperands, |
| 24261 | // GIR_Coverage, 2250, |
| 24262 | GIR_EraseRootFromParent_Done, |
| 24263 | // Label 1677: @61309 |
| 24264 | GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(61340), // Rule ID 2251 // |
| 24265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 24266 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24268 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24269 | // (lrint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 24270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H), |
| 24271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24272 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24274 | GIR_RootConstrainSelectedInstOperands, |
| 24275 | // GIR_Coverage, 2251, |
| 24276 | GIR_EraseRootFromParent_Done, |
| 24277 | // Label 1678: @61340 |
| 24278 | GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(61371), // Rule ID 2276 // |
| 24279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 24280 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24282 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24283 | // (lrint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 24284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H_INX), |
| 24285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24286 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24288 | GIR_RootConstrainSelectedInstOperands, |
| 24289 | // GIR_Coverage, 2276, |
| 24290 | GIR_EraseRootFromParent_Done, |
| 24291 | // Label 1679: @61371 |
| 24292 | GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(61402), // Rule ID 2277 // |
| 24293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 24294 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24296 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24297 | // (lrint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 24298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H_INX), |
| 24299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24300 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24302 | GIR_RootConstrainSelectedInstOperands, |
| 24303 | // GIR_Coverage, 2277, |
| 24304 | GIR_EraseRootFromParent_Done, |
| 24305 | // Label 1680: @61402 |
| 24306 | GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(61455), // Rule ID 2382 // |
| 24307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0), |
| 24308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24310 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24311 | // (lrint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 7:{ *:[i64] }) |
| 24312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 24314 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24315 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24316 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24317 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 24319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24320 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24322 | GIR_RootConstrainSelectedInstOperands, |
| 24323 | // GIR_Coverage, 2382, |
| 24324 | GIR_EraseRootFromParent_Done, |
| 24325 | // Label 1681: @61455 |
| 24326 | GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(61508), // Rule ID 2383 // |
| 24327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1), |
| 24328 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24330 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24331 | // (lrint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 7:{ *:[i32] }) |
| 24332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 24334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24335 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24336 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 24339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24340 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24342 | GIR_RootConstrainSelectedInstOperands, |
| 24343 | // GIR_Coverage, 2383, |
| 24344 | GIR_EraseRootFromParent_Done, |
| 24345 | // Label 1682: @61508 |
| 24346 | GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(61561), // Rule ID 2406 // |
| 24347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0), |
| 24348 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24351 | // (lrint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 7:{ *:[i64] }) |
| 24352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 24354 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24355 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24356 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 24359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24360 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24362 | GIR_RootConstrainSelectedInstOperands, |
| 24363 | // GIR_Coverage, 2406, |
| 24364 | GIR_EraseRootFromParent_Done, |
| 24365 | // Label 1683: @61561 |
| 24366 | GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(61614), // Rule ID 2407 // |
| 24367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1), |
| 24368 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24370 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24371 | // (lrint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 7:{ *:[i32] }) |
| 24372 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24373 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 24374 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24375 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24376 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 24379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24380 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24382 | GIR_RootConstrainSelectedInstOperands, |
| 24383 | // GIR_Coverage, 2407, |
| 24384 | GIR_EraseRootFromParent_Done, |
| 24385 | // Label 1684: @61614 |
| 24386 | GIM_Reject, |
| 24387 | // Label 1667: @61615 |
| 24388 | GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(61646), // Rule ID 1586 // |
| 24389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 24390 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 24393 | // (lrint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_L_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 24394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 24395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24396 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24398 | GIR_RootConstrainSelectedInstOperands, |
| 24399 | // GIR_Coverage, 1586, |
| 24400 | GIR_EraseRootFromParent_Done, |
| 24401 | // Label 1685: @61646 |
| 24402 | GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(61677), // Rule ID 1614 // |
| 24403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 24404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 24405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 24407 | // (lrint:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 24408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 24409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24410 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24412 | GIR_RootConstrainSelectedInstOperands, |
| 24413 | // GIR_Coverage, 1614, |
| 24414 | GIR_EraseRootFromParent_Done, |
| 24415 | // Label 1686: @61677 |
| 24416 | GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(61708), // Rule ID 1971 // |
| 24417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 24418 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24420 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24421 | // (lrint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 24422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D), |
| 24423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24424 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24426 | GIR_RootConstrainSelectedInstOperands, |
| 24427 | // GIR_Coverage, 1971, |
| 24428 | GIR_EraseRootFromParent_Done, |
| 24429 | // Label 1687: @61708 |
| 24430 | GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(61739), // Rule ID 1999 // |
| 24431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 24432 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24435 | // (lrint:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_L_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 24436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D_INX), |
| 24437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24438 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24440 | GIR_RootConstrainSelectedInstOperands, |
| 24441 | // GIR_Coverage, 1999, |
| 24442 | GIR_EraseRootFromParent_Done, |
| 24443 | // Label 1688: @61739 |
| 24444 | GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(61770), // Rule ID 2301 // |
| 24445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 24446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24449 | // (lrint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 24450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H), |
| 24451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24452 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24454 | GIR_RootConstrainSelectedInstOperands, |
| 24455 | // GIR_Coverage, 2301, |
| 24456 | GIR_EraseRootFromParent_Done, |
| 24457 | // Label 1689: @61770 |
| 24458 | GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(61801), // Rule ID 2327 // |
| 24459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 24460 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24463 | // (lrint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 24464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H_INX), |
| 24465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24466 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24468 | GIR_RootConstrainSelectedInstOperands, |
| 24469 | // GIR_Coverage, 2327, |
| 24470 | GIR_EraseRootFromParent_Done, |
| 24471 | // Label 1690: @61801 |
| 24472 | GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(61854), // Rule ID 2425 // |
| 24473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 24474 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24476 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24477 | // (lrint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_S:{ *:[i64] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 7:{ *:[i64] }) |
| 24478 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24479 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 24480 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24481 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24482 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 24485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24486 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24488 | GIR_RootConstrainSelectedInstOperands, |
| 24489 | // GIR_Coverage, 2425, |
| 24490 | GIR_EraseRootFromParent_Done, |
| 24491 | // Label 1691: @61854 |
| 24492 | GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(61907), // Rule ID 2441 // |
| 24493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 24494 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24496 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24497 | // (lrint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 7:{ *:[i64] }) |
| 24498 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 24500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24501 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24502 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24503 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 24505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24506 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24508 | GIR_RootConstrainSelectedInstOperands, |
| 24509 | // GIR_Coverage, 2441, |
| 24510 | GIR_EraseRootFromParent_Done, |
| 24511 | // Label 1692: @61907 |
| 24512 | GIM_Reject, |
| 24513 | // Label 1668: @61908 |
| 24514 | GIM_Reject, |
| 24515 | // Label 14: @61909 |
| 24516 | GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(62210), |
| 24517 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 24518 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 1697*/ GIMT_Encode4(62209), |
| 24519 | /*GILLT_s16*//*Label 1694*/ GIMT_Encode4(61940), |
| 24520 | /*GILLT_s32*//*Label 1695*/ GIMT_Encode4(62091), |
| 24521 | /*GILLT_s64*//*Label 1696*/ GIMT_Encode4(62150), |
| 24522 | // Label 1694: @61940 |
| 24523 | GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(62090), |
| 24524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24525 | GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(61973), // Rule ID 2303 // |
| 24526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 24527 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24528 | // (llrint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 24529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H), |
| 24530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24531 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24533 | GIR_RootConstrainSelectedInstOperands, |
| 24534 | // GIR_Coverage, 2303, |
| 24535 | GIR_EraseRootFromParent_Done, |
| 24536 | // Label 1699: @61973 |
| 24537 | GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(61997), // Rule ID 2329 // |
| 24538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 24539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24540 | // (llrint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 24541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H_INX), |
| 24542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24543 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24545 | GIR_RootConstrainSelectedInstOperands, |
| 24546 | // GIR_Coverage, 2329, |
| 24547 | GIR_EraseRootFromParent_Done, |
| 24548 | // Label 1700: @61997 |
| 24549 | GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(62043), // Rule ID 2427 // |
| 24550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 24551 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24552 | // (llrint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_S:{ *:[i64] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 7:{ *:[i64] }) |
| 24553 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 24555 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24556 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24557 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 24560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24561 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24563 | GIR_RootConstrainSelectedInstOperands, |
| 24564 | // GIR_Coverage, 2427, |
| 24565 | GIR_EraseRootFromParent_Done, |
| 24566 | // Label 1701: @62043 |
| 24567 | GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(62089), // Rule ID 2443 // |
| 24568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 24569 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24570 | // (llrint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 7:{ *:[i64] }) |
| 24571 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24572 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 24573 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24574 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 24575 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 24576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 24578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24579 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24581 | GIR_RootConstrainSelectedInstOperands, |
| 24582 | // GIR_Coverage, 2443, |
| 24583 | GIR_EraseRootFromParent_Done, |
| 24584 | // Label 1702: @62089 |
| 24585 | GIM_Reject, |
| 24586 | // Label 1698: @62090 |
| 24587 | GIM_Reject, |
| 24588 | // Label 1695: @62091 |
| 24589 | GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(62149), |
| 24590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24591 | GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(62124), // Rule ID 1588 // |
| 24592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 24593 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 24594 | // (llrint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_L_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 24595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 24596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24597 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24599 | GIR_RootConstrainSelectedInstOperands, |
| 24600 | // GIR_Coverage, 1588, |
| 24601 | GIR_EraseRootFromParent_Done, |
| 24602 | // Label 1704: @62124 |
| 24603 | GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(62148), // Rule ID 1616 // |
| 24604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 24605 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 24606 | // (llrint:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 24607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 24608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24609 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24611 | GIR_RootConstrainSelectedInstOperands, |
| 24612 | // GIR_Coverage, 1616, |
| 24613 | GIR_EraseRootFromParent_Done, |
| 24614 | // Label 1705: @62148 |
| 24615 | GIM_Reject, |
| 24616 | // Label 1703: @62149 |
| 24617 | GIM_Reject, |
| 24618 | // Label 1696: @62150 |
| 24619 | GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(62208), |
| 24620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24621 | GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(62183), // Rule ID 1973 // |
| 24622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 24623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24624 | // (llrint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 24625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D), |
| 24626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24627 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24629 | GIR_RootConstrainSelectedInstOperands, |
| 24630 | // GIR_Coverage, 1973, |
| 24631 | GIR_EraseRootFromParent_Done, |
| 24632 | // Label 1707: @62183 |
| 24633 | GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(62207), // Rule ID 2001 // |
| 24634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 24635 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24636 | // (llrint:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_L_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 24637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D_INX), |
| 24638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24639 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 24641 | GIR_RootConstrainSelectedInstOperands, |
| 24642 | // GIR_Coverage, 2001, |
| 24643 | GIR_EraseRootFromParent_Done, |
| 24644 | // Label 1708: @62207 |
| 24645 | GIM_Reject, |
| 24646 | // Label 1706: @62208 |
| 24647 | GIM_Reject, |
| 24648 | // Label 1697: @62209 |
| 24649 | GIM_Reject, |
| 24650 | // Label 1693: @62210 |
| 24651 | GIM_Reject, |
| 24652 | // Label 15: @62211 |
| 24653 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 1711*/ GIMT_Encode4(62350), |
| 24654 | /*GILLT_s16*//*Label 1709*/ GIMT_Encode4(62234), GIMT_Encode4(0), |
| 24655 | /*GILLT_s64*//*Label 1710*/ GIMT_Encode4(62292), |
| 24656 | // Label 1709: @62234 |
| 24657 | GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(62291), |
| 24658 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 24659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24660 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24661 | GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(62270), // Rule ID 2580 // |
| 24662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 24663 | // (froundeven:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 0:{ *:[i64] }) |
| 24664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 24665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24666 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24668 | GIR_RootConstrainSelectedInstOperands, |
| 24669 | // GIR_Coverage, 2580, |
| 24670 | GIR_EraseRootFromParent_Done, |
| 24671 | // Label 1713: @62270 |
| 24672 | GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(62290), // Rule ID 2581 // |
| 24673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 24674 | // (froundeven:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 0:{ *:[i32] }) |
| 24675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 24676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24677 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24679 | GIR_RootConstrainSelectedInstOperands, |
| 24680 | // GIR_Coverage, 2581, |
| 24681 | GIR_EraseRootFromParent_Done, |
| 24682 | // Label 1714: @62290 |
| 24683 | GIM_Reject, |
| 24684 | // Label 1712: @62291 |
| 24685 | GIM_Reject, |
| 24686 | // Label 1710: @62292 |
| 24687 | GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(62349), |
| 24688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 24689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24690 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 24691 | GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(62328), // Rule ID 2540 // |
| 24692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 24693 | // (froundeven:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 0:{ *:[i64] }) |
| 24694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 24695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24696 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24698 | GIR_RootConstrainSelectedInstOperands, |
| 24699 | // GIR_Coverage, 2540, |
| 24700 | GIR_EraseRootFromParent_Done, |
| 24701 | // Label 1716: @62328 |
| 24702 | GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(62348), // Rule ID 2541 // |
| 24703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 24704 | // (froundeven:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 0:{ *:[i32] }) |
| 24705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 24706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24707 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 24708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24709 | GIR_RootConstrainSelectedInstOperands, |
| 24710 | // GIR_Coverage, 2541, |
| 24711 | GIR_EraseRootFromParent_Done, |
| 24712 | // Label 1717: @62348 |
| 24713 | GIM_Reject, |
| 24714 | // Label 1715: @62349 |
| 24715 | GIM_Reject, |
| 24716 | // Label 1711: @62350 |
| 24717 | GIM_Reject, |
| 24718 | // Label 16: @62351 |
| 24719 | GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(62389), // Rule ID 270 // |
| 24720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 24721 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 24722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24723 | // (readcyclecounter:{ *:[i64] }) => (CSRRS:{ *:[i64] } 3072:{ *:[i64] }, X0:{ *:[i64] }) |
| 24724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CSRRS), |
| 24725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24726 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3072), |
| 24727 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24728 | GIR_RootConstrainSelectedInstOperands, |
| 24729 | // GIR_Coverage, 270, |
| 24730 | GIR_EraseRootFromParent_Done, |
| 24731 | // Label 1718: @62389 |
| 24732 | GIM_Reject, |
| 24733 | // Label 17: @62390 |
| 24734 | GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(62428), // Rule ID 271 // |
| 24735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 24736 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 24737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24738 | // (readsteadycounter:{ *:[i64] }) => (CSRRS:{ *:[i64] } 3073:{ *:[i64] }, X0:{ *:[i64] }) |
| 24739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CSRRS), |
| 24740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24741 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3073), |
| 24742 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24743 | GIR_RootConstrainSelectedInstOperands, |
| 24744 | // GIR_Coverage, 271, |
| 24745 | GIR_EraseRootFromParent_Done, |
| 24746 | // Label 1719: @62428 |
| 24747 | GIM_Reject, |
| 24748 | // Label 18: @62429 |
| 24749 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(34), /*)*//*default:*//*Label 1754*/ GIMT_Encode4(66858), |
| 24750 | /*GILLT_p0s32*//*Label 1720*/ GIMT_Encode4(62576), |
| 24751 | /*GILLT_p0s64*//*Label 1721*/ GIMT_Encode4(62670), |
| 24752 | /*GILLT_s16*//*Label 1722*/ GIMT_Encode4(62764), |
| 24753 | /*GILLT_s32*//*Label 1723*/ GIMT_Encode4(63084), |
| 24754 | /*GILLT_s64*//*Label 1724*/ GIMT_Encode4(64267), |
| 24755 | /*GILLT_nxv1s1*//*Label 1725*/ GIMT_Encode4(64862), |
| 24756 | /*GILLT_nxv1s8*//*Label 1726*/ GIMT_Encode4(64929), |
| 24757 | /*GILLT_nxv1s16*//*Label 1727*/ GIMT_Encode4(64996), |
| 24758 | /*GILLT_nxv1s32*//*Label 1728*/ GIMT_Encode4(65163), |
| 24759 | /*GILLT_nxv1s64*//*Label 1729*/ GIMT_Encode4(65283), |
| 24760 | /*GILLT_nxv2s1*//*Label 1730*/ GIMT_Encode4(65339), |
| 24761 | /*GILLT_nxv2s8*//*Label 1731*/ GIMT_Encode4(65406), |
| 24762 | /*GILLT_nxv2s16*//*Label 1732*/ GIMT_Encode4(65473), |
| 24763 | /*GILLT_nxv2s32*//*Label 1733*/ GIMT_Encode4(65640), |
| 24764 | /*GILLT_nxv2s64*//*Label 1734*/ GIMT_Encode4(65696), |
| 24765 | /*GILLT_nxv4s1*//*Label 1735*/ GIMT_Encode4(65752), |
| 24766 | /*GILLT_nxv4s8*//*Label 1736*/ GIMT_Encode4(65819), |
| 24767 | /*GILLT_nxv4s16*//*Label 1737*/ GIMT_Encode4(65886), |
| 24768 | /*GILLT_nxv4s32*//*Label 1738*/ GIMT_Encode4(65957), |
| 24769 | /*GILLT_nxv4s64*//*Label 1739*/ GIMT_Encode4(66013), |
| 24770 | /*GILLT_nxv8s1*//*Label 1740*/ GIMT_Encode4(66069), |
| 24771 | /*GILLT_nxv8s8*//*Label 1741*/ GIMT_Encode4(66136), |
| 24772 | /*GILLT_nxv8s16*//*Label 1742*/ GIMT_Encode4(66171), |
| 24773 | /*GILLT_nxv8s32*//*Label 1743*/ GIMT_Encode4(66242), |
| 24774 | /*GILLT_nxv8s64*//*Label 1744*/ GIMT_Encode4(66298), |
| 24775 | /*GILLT_nxv16s1*//*Label 1745*/ GIMT_Encode4(66354), |
| 24776 | /*GILLT_nxv16s8*//*Label 1746*/ GIMT_Encode4(66421), |
| 24777 | /*GILLT_nxv16s16*//*Label 1747*/ GIMT_Encode4(66456), |
| 24778 | /*GILLT_nxv16s32*//*Label 1748*/ GIMT_Encode4(66527), |
| 24779 | /*GILLT_nxv32s1*//*Label 1749*/ GIMT_Encode4(66583), |
| 24780 | /*GILLT_nxv32s8*//*Label 1750*/ GIMT_Encode4(66650), |
| 24781 | /*GILLT_nxv32s16*//*Label 1751*/ GIMT_Encode4(66685), |
| 24782 | /*GILLT_nxv64s1*//*Label 1752*/ GIMT_Encode4(66756), |
| 24783 | /*GILLT_nxv64s8*//*Label 1753*/ GIMT_Encode4(66823), |
| 24784 | // Label 1720: @62576 |
| 24785 | GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(62669), |
| 24786 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24787 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24790 | GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(62632), // Rule ID 65132 // |
| 24791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV32_HwMode1), |
| 24792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24793 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 24794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 24795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24798 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24799 | GIR_RootConstrainSelectedInstOperands, |
| 24800 | // GIR_Coverage, 65132, |
| 24801 | GIR_EraseRootFromParent_Done, |
| 24802 | // Label 1756: @62632 |
| 24803 | GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(62668), // Rule ID 65136 // |
| 24804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 24805 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24806 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 24807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LD), |
| 24808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24811 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24812 | GIR_RootConstrainSelectedInstOperands, |
| 24813 | // GIR_Coverage, 65136, |
| 24814 | GIR_EraseRootFromParent_Done, |
| 24815 | // Label 1757: @62668 |
| 24816 | GIM_Reject, |
| 24817 | // Label 1755: @62669 |
| 24818 | GIM_Reject, |
| 24819 | // Label 1721: @62670 |
| 24820 | GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(62763), |
| 24821 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24825 | GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(62726), // Rule ID 65131 // |
| 24826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV32_HwMode0), |
| 24827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24828 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 24829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 24830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24833 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24834 | GIR_RootConstrainSelectedInstOperands, |
| 24835 | // GIR_Coverage, 65131, |
| 24836 | GIR_EraseRootFromParent_Done, |
| 24837 | // Label 1759: @62726 |
| 24838 | GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(62762), // Rule ID 65135 // |
| 24839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 24840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24841 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 24842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LD), |
| 24843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24846 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24847 | GIR_RootConstrainSelectedInstOperands, |
| 24848 | // GIR_Coverage, 65135, |
| 24849 | GIR_EraseRootFromParent_Done, |
| 24850 | // Label 1760: @62762 |
| 24851 | GIM_Reject, |
| 24852 | // Label 1758: @62763 |
| 24853 | GIM_Reject, |
| 24854 | // Label 1722: @62764 |
| 24855 | GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(63083), |
| 24856 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24857 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24858 | GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(62820), // Rule ID 2198 // |
| 24859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode0), |
| 24860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24861 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24862 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24863 | // (ld:{ *:[f16] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLH:{ *:[f16] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 24864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLH), |
| 24865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24868 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24869 | GIR_RootConstrainSelectedInstOperands, |
| 24870 | // GIR_Coverage, 2198, |
| 24871 | GIR_EraseRootFromParent_Done, |
| 24872 | // Label 1762: @62820 |
| 24873 | GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(62864), // Rule ID 2199 // |
| 24874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode1), |
| 24875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24876 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24878 | // (ld:{ *:[f16] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLH:{ *:[f16] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 24879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLH), |
| 24880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24883 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24884 | GIR_RootConstrainSelectedInstOperands, |
| 24885 | // GIR_Coverage, 2199, |
| 24886 | GIR_EraseRootFromParent_Done, |
| 24887 | // Label 1763: @62864 |
| 24888 | GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(62929), // Rule ID 2202 // |
| 24889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode0), |
| 24890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24891 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24893 | // (ld:{ *:[f16] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (COPY_TO_REGCLASS:{ *:[f16] } (LH:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPRF16:{ *:[i32] }) |
| 24894 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24895 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 24896 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24897 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24898 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24899 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24900 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24903 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24904 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24905 | // GIR_Coverage, 2202, |
| 24906 | GIR_EraseRootFromParent_Done, |
| 24907 | // Label 1764: @62929 |
| 24908 | GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(62994), // Rule ID 2203 // |
| 24909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode1), |
| 24910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24912 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24913 | // (ld:{ *:[f16] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (COPY_TO_REGCLASS:{ *:[f16] } (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPRF16:{ *:[i32] }) |
| 24914 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24915 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 24916 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24917 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24918 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24919 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 24922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24923 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24924 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 24925 | // GIR_Coverage, 2203, |
| 24926 | GIR_EraseRootFromParent_Done, |
| 24927 | // Label 1765: @62994 |
| 24928 | GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(63038), // Rule ID 2452 // |
| 24929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode0), |
| 24930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24931 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24933 | // (ld:{ *:[bf16] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLH:{ *:[bf16] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 24934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLH), |
| 24935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24938 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24939 | GIR_RootConstrainSelectedInstOperands, |
| 24940 | // GIR_Coverage, 2452, |
| 24941 | GIR_EraseRootFromParent_Done, |
| 24942 | // Label 1766: @63038 |
| 24943 | GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(63082), // Rule ID 2453 // |
| 24944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode1), |
| 24945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 24946 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24948 | // (ld:{ *:[bf16] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLH:{ *:[bf16] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 24949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLH), |
| 24950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24953 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24954 | GIR_RootConstrainSelectedInstOperands, |
| 24955 | // GIR_Coverage, 2453, |
| 24956 | GIR_EraseRootFromParent_Done, |
| 24957 | // Label 1767: @63082 |
| 24958 | GIM_Reject, |
| 24959 | // Label 1761: @63083 |
| 24960 | GIM_Reject, |
| 24961 | // Label 1723: @63084 |
| 24962 | GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(63138), // Rule ID 359 // |
| 24963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 24964 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 24965 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24968 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24969 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 24970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 24971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24974 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24975 | GIR_RootConstrainSelectedInstOperands, |
| 24976 | // GIR_Coverage, 359, |
| 24977 | GIR_EraseRootFromParent_Done, |
| 24978 | // Label 1768: @63138 |
| 24979 | GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(63192), // Rule ID 361 // |
| 24980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 24981 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 24982 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 24984 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24985 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 24986 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 24987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 24988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 24989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 24990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 24991 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24992 | GIR_RootConstrainSelectedInstOperands, |
| 24993 | // GIR_Coverage, 361, |
| 24994 | GIR_EraseRootFromParent_Done, |
| 24995 | // Label 1769: @63192 |
| 24996 | GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(63246), // Rule ID 363 // |
| 24997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 24998 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 24999 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25001 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25003 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25008 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25009 | GIR_RootConstrainSelectedInstOperands, |
| 25010 | // GIR_Coverage, 363, |
| 25011 | GIR_EraseRootFromParent_Done, |
| 25012 | // Label 1770: @63246 |
| 25013 | GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(63300), // Rule ID 880 // |
| 25014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 25015 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25016 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25018 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25020 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 25022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25025 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25026 | GIR_RootConstrainSelectedInstOperands, |
| 25027 | // GIR_Coverage, 880, |
| 25028 | GIR_EraseRootFromParent_Done, |
| 25029 | // Label 1771: @63300 |
| 25030 | GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(63354), // Rule ID 881 // |
| 25031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 25032 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25033 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25035 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25036 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25037 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 25039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25042 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25043 | GIR_RootConstrainSelectedInstOperands, |
| 25044 | // GIR_Coverage, 881, |
| 25045 | GIR_EraseRootFromParent_Done, |
| 25046 | // Label 1772: @63354 |
| 25047 | GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(63408), // Rule ID 882 // |
| 25048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 25049 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25050 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25052 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25054 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25059 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25060 | GIR_RootConstrainSelectedInstOperands, |
| 25061 | // GIR_Coverage, 882, |
| 25062 | GIR_EraseRootFromParent_Done, |
| 25063 | // Label 1773: @63408 |
| 25064 | GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(63462), // Rule ID 883 // |
| 25065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 25066 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25067 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25069 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25070 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25071 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25077 | GIR_RootConstrainSelectedInstOperands, |
| 25078 | // GIR_Coverage, 883, |
| 25079 | GIR_EraseRootFromParent_Done, |
| 25080 | // Label 1774: @63462 |
| 25081 | GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(63516), // Rule ID 884 // |
| 25082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 25083 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 25084 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25087 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25088 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25094 | GIR_RootConstrainSelectedInstOperands, |
| 25095 | // GIR_Coverage, 884, |
| 25096 | GIR_EraseRootFromParent_Done, |
| 25097 | // Label 1775: @63516 |
| 25098 | GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(63570), // Rule ID 885 // |
| 25099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 25100 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 25101 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25103 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25104 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25105 | // (atomic_load:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25110 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25111 | GIR_RootConstrainSelectedInstOperands, |
| 25112 | // GIR_Coverage, 885, |
| 25113 | GIR_EraseRootFromParent_Done, |
| 25114 | // Label 1776: @63570 |
| 25115 | GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(63621), // Rule ID 223 // |
| 25116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 25117 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25118 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25120 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25121 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25122 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25127 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25128 | GIR_RootConstrainSelectedInstOperands, |
| 25129 | // GIR_Coverage, 223, |
| 25130 | GIR_EraseRootFromParent_Done, |
| 25131 | // Label 1777: @63621 |
| 25132 | GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(63672), // Rule ID 224 // |
| 25133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 25134 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25135 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25138 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25139 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25144 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25145 | GIR_RootConstrainSelectedInstOperands, |
| 25146 | // GIR_Coverage, 224, |
| 25147 | GIR_EraseRootFromParent_Done, |
| 25148 | // Label 1778: @63672 |
| 25149 | GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(63723), // Rule ID 1504 // |
| 25150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 25151 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25152 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 25154 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25155 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25156 | // (ld:{ *:[f32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLW), |
| 25158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25161 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25162 | GIR_RootConstrainSelectedInstOperands, |
| 25163 | // GIR_Coverage, 1504, |
| 25164 | GIR_EraseRootFromParent_Done, |
| 25165 | // Label 1779: @63723 |
| 25166 | GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(63774), // Rule ID 1505 // |
| 25167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 25168 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25169 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 25171 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25173 | // (ld:{ *:[f32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLW), |
| 25175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25178 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25179 | GIR_RootConstrainSelectedInstOperands, |
| 25180 | // GIR_Coverage, 1505, |
| 25181 | GIR_EraseRootFromParent_Done, |
| 25182 | // Label 1780: @63774 |
| 25183 | GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(63846), // Rule ID 1510 // |
| 25184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 25185 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25186 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 25188 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25189 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25190 | // (ld:{ *:[f32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (COPY_TO_REGCLASS:{ *:[f32] } (LW:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPRF32:{ *:[i32] }) |
| 25191 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 25192 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25193 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25194 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25195 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25196 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25197 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 25199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25200 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25201 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 25202 | // GIR_Coverage, 1510, |
| 25203 | GIR_EraseRootFromParent_Done, |
| 25204 | // Label 1781: @63846 |
| 25205 | GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(63918), // Rule ID 1511 // |
| 25206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 25207 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25208 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 25210 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25211 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25212 | // (ld:{ *:[f32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (COPY_TO_REGCLASS:{ *:[f32] } (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPRF32:{ *:[i32] }) |
| 25213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 25214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25216 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25217 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25218 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 25221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25222 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25223 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 25224 | // GIR_Coverage, 1511, |
| 25225 | GIR_EraseRootFromParent_Done, |
| 25226 | // Label 1782: @63918 |
| 25227 | GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(63976), // Rule ID 218 // |
| 25228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 25229 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25230 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25231 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25235 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 25237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25240 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25241 | GIR_RootConstrainSelectedInstOperands, |
| 25242 | // GIR_Coverage, 218, |
| 25243 | GIR_EraseRootFromParent_Done, |
| 25244 | // Label 1783: @63976 |
| 25245 | GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(64034), // Rule ID 222 // |
| 25246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 25247 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25248 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25249 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25251 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25253 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25258 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25259 | GIR_RootConstrainSelectedInstOperands, |
| 25260 | // GIR_Coverage, 222, |
| 25261 | GIR_EraseRootFromParent_Done, |
| 25262 | // Label 1784: @64034 |
| 25263 | GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(64092), // Rule ID 279 // |
| 25264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 25265 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25266 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25267 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25269 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25270 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25271 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 25273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25276 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25277 | GIR_RootConstrainSelectedInstOperands, |
| 25278 | // GIR_Coverage, 279, |
| 25279 | GIR_EraseRootFromParent_Done, |
| 25280 | // Label 1785: @64092 |
| 25281 | GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(64150), // Rule ID 280 // |
| 25282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 25283 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25284 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25285 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25289 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 25291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25294 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25295 | GIR_RootConstrainSelectedInstOperands, |
| 25296 | // GIR_Coverage, 280, |
| 25297 | GIR_EraseRootFromParent_Done, |
| 25298 | // Label 1786: @64150 |
| 25299 | GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(64208), // Rule ID 283 // |
| 25300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 25301 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25302 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25305 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25307 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25313 | GIR_RootConstrainSelectedInstOperands, |
| 25314 | // GIR_Coverage, 283, |
| 25315 | GIR_EraseRootFromParent_Done, |
| 25316 | // Label 1787: @64208 |
| 25317 | GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(64266), // Rule ID 284 // |
| 25318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 25319 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25320 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25325 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25330 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25331 | GIR_RootConstrainSelectedInstOperands, |
| 25332 | // GIR_Coverage, 284, |
| 25333 | GIR_EraseRootFromParent_Done, |
| 25334 | // Label 1788: @64266 |
| 25335 | GIM_Reject, |
| 25336 | // Label 1724: @64267 |
| 25337 | GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(64321), // Rule ID 358 // |
| 25338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 25339 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25340 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25342 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25343 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25344 | // (atomic_load:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 25346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25350 | GIR_RootConstrainSelectedInstOperands, |
| 25351 | // GIR_Coverage, 358, |
| 25352 | GIR_EraseRootFromParent_Done, |
| 25353 | // Label 1789: @64321 |
| 25354 | GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(64375), // Rule ID 360 // |
| 25355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 25356 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25357 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25359 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25361 | // (atomic_load:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25366 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25367 | GIR_RootConstrainSelectedInstOperands, |
| 25368 | // GIR_Coverage, 360, |
| 25369 | GIR_EraseRootFromParent_Done, |
| 25370 | // Label 1790: @64375 |
| 25371 | GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(64429), // Rule ID 362 // |
| 25372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 25373 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 25374 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25378 | // (atomic_load:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25384 | GIR_RootConstrainSelectedInstOperands, |
| 25385 | // GIR_Coverage, 362, |
| 25386 | GIR_EraseRootFromParent_Done, |
| 25387 | // Label 1791: @64429 |
| 25388 | GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(64483), // Rule ID 370 // |
| 25389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_IsRV64_HwMode0), |
| 25390 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 25391 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 25392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25393 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25395 | // (atomic_load:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LD), |
| 25397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25401 | GIR_RootConstrainSelectedInstOperands, |
| 25402 | // GIR_Coverage, 370, |
| 25403 | GIR_EraseRootFromParent_Done, |
| 25404 | // Label 1792: @64483 |
| 25405 | GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(64534), // Rule ID 267 // |
| 25406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 25407 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25408 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25410 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25412 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LD), |
| 25414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25418 | GIR_RootConstrainSelectedInstOperands, |
| 25419 | // GIR_Coverage, 267, |
| 25420 | GIR_EraseRootFromParent_Done, |
| 25421 | // Label 1793: @64534 |
| 25422 | GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(64585), // Rule ID 1889 // |
| 25423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 25424 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25425 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 25427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25429 | // (ld:{ *:[f64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLD), |
| 25431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25435 | GIR_RootConstrainSelectedInstOperands, |
| 25436 | // GIR_Coverage, 1889, |
| 25437 | GIR_EraseRootFromParent_Done, |
| 25438 | // Label 1794: @64585 |
| 25439 | GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(64636), // Rule ID 1890 // |
| 25440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 25441 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25442 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 25444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25446 | // (ld:{ *:[f64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 25447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLD), |
| 25448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25451 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25452 | GIR_RootConstrainSelectedInstOperands, |
| 25453 | // GIR_Coverage, 1890, |
| 25454 | GIR_EraseRootFromParent_Done, |
| 25455 | // Label 1795: @64636 |
| 25456 | GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(64687), // Rule ID 1894 // |
| 25457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 25458 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25459 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25462 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25463 | // (ld:{ *:[f64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LD), |
| 25465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25468 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25469 | GIR_RootConstrainSelectedInstOperands, |
| 25470 | // GIR_Coverage, 1894, |
| 25471 | GIR_EraseRootFromParent_Done, |
| 25472 | // Label 1796: @64687 |
| 25473 | GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(64745), // Rule ID 217 // |
| 25474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 25475 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25476 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 25477 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25480 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25481 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 25483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25487 | GIR_RootConstrainSelectedInstOperands, |
| 25488 | // GIR_Coverage, 217, |
| 25489 | GIR_EraseRootFromParent_Done, |
| 25490 | // Label 1797: @64745 |
| 25491 | GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(64803), // Rule ID 221 // |
| 25492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 25493 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25494 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 25495 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25498 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25499 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 25501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25505 | GIR_RootConstrainSelectedInstOperands, |
| 25506 | // GIR_Coverage, 221, |
| 25507 | GIR_EraseRootFromParent_Done, |
| 25508 | // Label 1798: @64803 |
| 25509 | GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(64861), // Rule ID 265 // |
| 25510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 25511 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25512 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 25513 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 25517 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 25518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 25519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 25521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 25522 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25523 | GIR_RootConstrainSelectedInstOperands, |
| 25524 | // GIR_Coverage, 265, |
| 25525 | GIR_EraseRootFromParent_Done, |
| 25526 | // Label 1799: @64861 |
| 25527 | GIM_Reject, |
| 25528 | // Label 1725: @64862 |
| 25529 | GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(64928), // Rule ID 46575 // |
| 25530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25531 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25532 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25534 | // MIs[0] rs1 |
| 25535 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25537 | // (ld:{ *:[nxv1i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B1:{ *:[nxv1i1] } (IMPLICIT_DEF:{ *:[nxv1i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 25538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1, |
| 25539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B1), |
| 25543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25545 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25550 | GIR_RootConstrainSelectedInstOperands, |
| 25551 | // GIR_Coverage, 46575, |
| 25552 | GIR_EraseRootFromParent_Done, |
| 25553 | // Label 1800: @64928 |
| 25554 | GIM_Reject, |
| 25555 | // Label 1726: @64929 |
| 25556 | GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(64995), // Rule ID 46567 // |
| 25557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25558 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25559 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25561 | // MIs[0] rs1 |
| 25562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25563 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25564 | // (ld:{ *:[nxv1i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE8_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 25565 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 25566 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25567 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25568 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE8_V_MF8), |
| 25570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25571 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25572 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25577 | GIR_RootConstrainSelectedInstOperands, |
| 25578 | // GIR_Coverage, 46567, |
| 25579 | GIR_EraseRootFromParent_Done, |
| 25580 | // Label 1801: @64995 |
| 25581 | GIM_Reject, |
| 25582 | // Label 1727: @64996 |
| 25583 | GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(65162), |
| 25584 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25585 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25587 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25589 | GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(65067), // Rule ID 46771 // |
| 25590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25591 | // (ld:{ *:[nxv1i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE16_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 25592 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 25593 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25594 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE16_V_MF4), |
| 25597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25598 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25599 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 25602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25603 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25604 | GIR_RootConstrainSelectedInstOperands, |
| 25605 | // GIR_Coverage, 46771, |
| 25606 | GIR_EraseRootFromParent_Done, |
| 25607 | // Label 1803: @65067 |
| 25608 | GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(65114), // Rule ID 46783 // |
| 25609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 25610 | // (ld:{ *:[nxv1f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE16_V_MF4:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 25611 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 25612 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25613 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE16_V_MF4), |
| 25616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25618 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 25621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25623 | GIR_RootConstrainSelectedInstOperands, |
| 25624 | // GIR_Coverage, 46783, |
| 25625 | GIR_EraseRootFromParent_Done, |
| 25626 | // Label 1804: @65114 |
| 25627 | GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(65161), // Rule ID 46795 // |
| 25628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 25629 | // (ld:{ *:[nxv1bf16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE16_V_MF4:{ *:[nxv1bf16] } (IMPLICIT_DEF:{ *:[nxv1bf16] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 25630 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 25631 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25632 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE16_V_MF4), |
| 25635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 25640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25641 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25642 | GIR_RootConstrainSelectedInstOperands, |
| 25643 | // GIR_Coverage, 46795, |
| 25644 | GIR_EraseRootFromParent_Done, |
| 25645 | // Label 1805: @65161 |
| 25646 | GIM_Reject, |
| 25647 | // Label 1802: @65162 |
| 25648 | GIM_Reject, |
| 25649 | // Label 1728: @65163 |
| 25650 | GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(65282), |
| 25651 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25652 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25655 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25656 | GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(65234), // Rule ID 46779 // |
| 25657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25658 | // (ld:{ *:[nxv1i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE32_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 25659 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 25660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE32_V_MF2), |
| 25664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25665 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25666 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 25669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25670 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25671 | GIR_RootConstrainSelectedInstOperands, |
| 25672 | // GIR_Coverage, 46779, |
| 25673 | GIR_EraseRootFromParent_Done, |
| 25674 | // Label 1807: @65234 |
| 25675 | GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(65281), // Rule ID 46791 // |
| 25676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 25677 | // (ld:{ *:[nxv1f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE32_V_MF2:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 25678 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 25679 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25680 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25681 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE32_V_MF2), |
| 25683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25684 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25685 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 25688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25689 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25690 | GIR_RootConstrainSelectedInstOperands, |
| 25691 | // GIR_Coverage, 46791, |
| 25692 | GIR_EraseRootFromParent_Done, |
| 25693 | // Label 1808: @65281 |
| 25694 | GIM_Reject, |
| 25695 | // Label 1806: @65282 |
| 25696 | GIM_Reject, |
| 25697 | // Label 1729: @65283 |
| 25698 | GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(65338), |
| 25699 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25700 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25702 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25703 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25704 | GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(65322), // Rule ID 46811 // |
| 25705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 25706 | // (ld:{ *:[nxv1i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE64_V:{ *:[nxv1i64] } GPR:{ *:[i32] }:$rs1) |
| 25707 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE64_V), |
| 25708 | GIR_RootConstrainSelectedInstOperands, |
| 25709 | // GIR_Coverage, 46811, |
| 25710 | GIR_Done, |
| 25711 | // Label 1810: @65322 |
| 25712 | GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(65337), // Rule ID 46827 // |
| 25713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 25714 | // (ld:{ *:[nxv1f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE64_V:{ *:[nxv1f64] } GPR:{ *:[i32] }:$rs1) |
| 25715 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE64_V), |
| 25716 | GIR_RootConstrainSelectedInstOperands, |
| 25717 | // GIR_Coverage, 46827, |
| 25718 | GIR_Done, |
| 25719 | // Label 1811: @65337 |
| 25720 | GIM_Reject, |
| 25721 | // Label 1809: @65338 |
| 25722 | GIM_Reject, |
| 25723 | // Label 1730: @65339 |
| 25724 | GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(65405), // Rule ID 46927 // |
| 25725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25726 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25727 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25729 | // MIs[0] rs1 |
| 25730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25731 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25732 | // (ld:{ *:[nxv2i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B2:{ *:[nxv2i1] } (IMPLICIT_DEF:{ *:[nxv2i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 25733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s1, |
| 25734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B2), |
| 25738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25739 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25740 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25745 | GIR_RootConstrainSelectedInstOperands, |
| 25746 | // GIR_Coverage, 46927, |
| 25747 | GIR_EraseRootFromParent_Done, |
| 25748 | // Label 1812: @65405 |
| 25749 | GIM_Reject, |
| 25750 | // Label 1731: @65406 |
| 25751 | GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(65472), // Rule ID 46763 // |
| 25752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25753 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25754 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25756 | // MIs[0] rs1 |
| 25757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25758 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25759 | // (ld:{ *:[nxv2i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE8_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 25760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 25761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25762 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE8_V_MF4), |
| 25765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25767 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25771 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25772 | GIR_RootConstrainSelectedInstOperands, |
| 25773 | // GIR_Coverage, 46763, |
| 25774 | GIR_EraseRootFromParent_Done, |
| 25775 | // Label 1813: @65472 |
| 25776 | GIM_Reject, |
| 25777 | // Label 1732: @65473 |
| 25778 | GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(65639), |
| 25779 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25780 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25782 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25784 | GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(65544), // Rule ID 46775 // |
| 25785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25786 | // (ld:{ *:[nxv2i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE16_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 25787 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 25788 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25789 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25790 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE16_V_MF2), |
| 25792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25793 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25794 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 25797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25798 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25799 | GIR_RootConstrainSelectedInstOperands, |
| 25800 | // GIR_Coverage, 46775, |
| 25801 | GIR_EraseRootFromParent_Done, |
| 25802 | // Label 1815: @65544 |
| 25803 | GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(65591), // Rule ID 46787 // |
| 25804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 25805 | // (ld:{ *:[nxv2f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE16_V_MF2:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 25806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 25807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE16_V_MF2), |
| 25811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25812 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25813 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 25816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25818 | GIR_RootConstrainSelectedInstOperands, |
| 25819 | // GIR_Coverage, 46787, |
| 25820 | GIR_EraseRootFromParent_Done, |
| 25821 | // Label 1816: @65591 |
| 25822 | GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(65638), // Rule ID 46799 // |
| 25823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 25824 | // (ld:{ *:[nxv2bf16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE16_V_MF2:{ *:[nxv2bf16] } (IMPLICIT_DEF:{ *:[nxv2bf16] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 25825 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 25826 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25827 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25828 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE16_V_MF2), |
| 25830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25831 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25832 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 25835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25837 | GIR_RootConstrainSelectedInstOperands, |
| 25838 | // GIR_Coverage, 46799, |
| 25839 | GIR_EraseRootFromParent_Done, |
| 25840 | // Label 1817: @65638 |
| 25841 | GIM_Reject, |
| 25842 | // Label 1814: @65639 |
| 25843 | GIM_Reject, |
| 25844 | // Label 1733: @65640 |
| 25845 | GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(65695), |
| 25846 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25847 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25849 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25851 | GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(65679), // Rule ID 46807 // |
| 25852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25853 | // (ld:{ *:[nxv2i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE32_V:{ *:[nxv2i32] } GPR:{ *:[i32] }:$rs1) |
| 25854 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE32_V), |
| 25855 | GIR_RootConstrainSelectedInstOperands, |
| 25856 | // GIR_Coverage, 46807, |
| 25857 | GIR_Done, |
| 25858 | // Label 1819: @65679 |
| 25859 | GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(65694), // Rule ID 46823 // |
| 25860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 25861 | // (ld:{ *:[nxv2f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE32_V:{ *:[nxv2f32] } GPR:{ *:[i32] }:$rs1) |
| 25862 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE32_V), |
| 25863 | GIR_RootConstrainSelectedInstOperands, |
| 25864 | // GIR_Coverage, 46823, |
| 25865 | GIR_Done, |
| 25866 | // Label 1820: @65694 |
| 25867 | GIM_Reject, |
| 25868 | // Label 1818: @65695 |
| 25869 | GIM_Reject, |
| 25870 | // Label 1734: @65696 |
| 25871 | GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(65751), |
| 25872 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25873 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 25875 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25877 | GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(65735), // Rule ID 46867 // |
| 25878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 25879 | // (ld:{ *:[nxv2i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE64_V:{ *:[nxv2i64] } GPR:{ *:[i32] }:$rs1) |
| 25880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE64_V), |
| 25881 | GIR_RootConstrainSelectedInstOperands, |
| 25882 | // GIR_Coverage, 46867, |
| 25883 | GIR_Done, |
| 25884 | // Label 1822: @65735 |
| 25885 | GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(65750), // Rule ID 46903 // |
| 25886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 25887 | // (ld:{ *:[nxv2f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE64_V:{ *:[nxv2f64] } GPR:{ *:[i32] }:$rs1) |
| 25888 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE64_V), |
| 25889 | GIR_RootConstrainSelectedInstOperands, |
| 25890 | // GIR_Coverage, 46903, |
| 25891 | GIR_Done, |
| 25892 | // Label 1823: @65750 |
| 25893 | GIM_Reject, |
| 25894 | // Label 1821: @65751 |
| 25895 | GIM_Reject, |
| 25896 | // Label 1735: @65752 |
| 25897 | GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(65818), // Rule ID 46931 // |
| 25898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25899 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25900 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25902 | // MIs[0] rs1 |
| 25903 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25904 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25905 | // (ld:{ *:[nxv4i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B4:{ *:[nxv4i1] } (IMPLICIT_DEF:{ *:[nxv4i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 25906 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s1, |
| 25907 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25908 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25909 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B4), |
| 25911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25912 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25913 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25918 | GIR_RootConstrainSelectedInstOperands, |
| 25919 | // GIR_Coverage, 46931, |
| 25920 | GIR_EraseRootFromParent_Done, |
| 25921 | // Label 1824: @65818 |
| 25922 | GIM_Reject, |
| 25923 | // Label 1736: @65819 |
| 25924 | GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(65885), // Rule ID 46767 // |
| 25925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25926 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25927 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25929 | // MIs[0] rs1 |
| 25930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25931 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25932 | // (ld:{ *:[nxv4i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLE8_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 25933 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 25934 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25935 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25936 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLE8_V_MF2), |
| 25938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 25939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25940 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 25941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 25942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 25944 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25945 | GIR_RootConstrainSelectedInstOperands, |
| 25946 | // GIR_Coverage, 46767, |
| 25947 | GIR_EraseRootFromParent_Done, |
| 25948 | // Label 1825: @65885 |
| 25949 | GIM_Reject, |
| 25950 | // Label 1737: @65886 |
| 25951 | GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(65956), |
| 25952 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25953 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 25955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25956 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25957 | GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(65925), // Rule ID 46803 // |
| 25958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25959 | // (ld:{ *:[nxv4i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE16_V:{ *:[nxv4i16] } GPR:{ *:[i32] }:$rs1) |
| 25960 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE16_V), |
| 25961 | GIR_RootConstrainSelectedInstOperands, |
| 25962 | // GIR_Coverage, 46803, |
| 25963 | GIR_Done, |
| 25964 | // Label 1827: @65925 |
| 25965 | GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(65940), // Rule ID 46815 // |
| 25966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 25967 | // (ld:{ *:[nxv4bf16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE16_V:{ *:[nxv4bf16] } GPR:{ *:[i32] }:$rs1) |
| 25968 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE16_V), |
| 25969 | GIR_RootConstrainSelectedInstOperands, |
| 25970 | // GIR_Coverage, 46815, |
| 25971 | GIR_Done, |
| 25972 | // Label 1828: @65940 |
| 25973 | GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(65955), // Rule ID 46819 // |
| 25974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 25975 | // (ld:{ *:[nxv4f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE16_V:{ *:[nxv4f16] } GPR:{ *:[i32] }:$rs1) |
| 25976 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE16_V), |
| 25977 | GIR_RootConstrainSelectedInstOperands, |
| 25978 | // GIR_Coverage, 46819, |
| 25979 | GIR_Done, |
| 25980 | // Label 1829: @65955 |
| 25981 | GIM_Reject, |
| 25982 | // Label 1826: @65956 |
| 25983 | GIM_Reject, |
| 25984 | // Label 1738: @65957 |
| 25985 | GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(66012), |
| 25986 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 25989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 25990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 25991 | GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(65996), // Rule ID 46855 // |
| 25992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 25993 | // (ld:{ *:[nxv4i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE32_V:{ *:[nxv4i32] } GPR:{ *:[i32] }:$rs1) |
| 25994 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE32_V), |
| 25995 | GIR_RootConstrainSelectedInstOperands, |
| 25996 | // GIR_Coverage, 46855, |
| 25997 | GIR_Done, |
| 25998 | // Label 1831: @65996 |
| 25999 | GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(66011), // Rule ID 46891 // |
| 26000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 26001 | // (ld:{ *:[nxv4f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE32_V:{ *:[nxv4f32] } GPR:{ *:[i32] }:$rs1) |
| 26002 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE32_V), |
| 26003 | GIR_RootConstrainSelectedInstOperands, |
| 26004 | // GIR_Coverage, 46891, |
| 26005 | GIR_Done, |
| 26006 | // Label 1832: @66011 |
| 26007 | GIM_Reject, |
| 26008 | // Label 1830: @66012 |
| 26009 | GIM_Reject, |
| 26010 | // Label 1739: @66013 |
| 26011 | GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(66068), |
| 26012 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26013 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 26015 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26017 | GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(66052), // Rule ID 46871 // |
| 26018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 26019 | // (ld:{ *:[nxv4i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE64_V:{ *:[nxv4i64] } GPR:{ *:[i32] }:$rs1) |
| 26020 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE64_V), |
| 26021 | GIR_RootConstrainSelectedInstOperands, |
| 26022 | // GIR_Coverage, 46871, |
| 26023 | GIR_Done, |
| 26024 | // Label 1834: @66052 |
| 26025 | GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(66067), // Rule ID 46907 // |
| 26026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 26027 | // (ld:{ *:[nxv4f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE64_V:{ *:[nxv4f64] } GPR:{ *:[i32] }:$rs1) |
| 26028 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE64_V), |
| 26029 | GIR_RootConstrainSelectedInstOperands, |
| 26030 | // GIR_Coverage, 46907, |
| 26031 | GIR_Done, |
| 26032 | // Label 1835: @66067 |
| 26033 | GIM_Reject, |
| 26034 | // Label 1833: @66068 |
| 26035 | GIM_Reject, |
| 26036 | // Label 1740: @66069 |
| 26037 | GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(66135), // Rule ID 46935 // |
| 26038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26039 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26040 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 26042 | // MIs[0] rs1 |
| 26043 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26044 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26045 | // (ld:{ *:[nxv8i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B8:{ *:[nxv8i1] } (IMPLICIT_DEF:{ *:[nxv8i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 26046 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s1, |
| 26047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26049 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B8), |
| 26051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26052 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26053 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 26054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 26055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 26057 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26058 | GIR_RootConstrainSelectedInstOperands, |
| 26059 | // GIR_Coverage, 46935, |
| 26060 | GIR_EraseRootFromParent_Done, |
| 26061 | // Label 1836: @66135 |
| 26062 | GIM_Reject, |
| 26063 | // Label 1741: @66136 |
| 26064 | GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(66170), // Rule ID 46571 // |
| 26065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26066 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26067 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 26069 | // MIs[0] rs1 |
| 26070 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26071 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26072 | // (ld:{ *:[nxv8i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL1RE8_V:{ *:[nxv8i8] } GPR:{ *:[i32] }:$rs1) |
| 26073 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL1RE8_V), |
| 26074 | GIR_RootConstrainSelectedInstOperands, |
| 26075 | // GIR_Coverage, 46571, |
| 26076 | GIR_Done, |
| 26077 | // Label 1837: @66170 |
| 26078 | GIM_Reject, |
| 26079 | // Label 1742: @66171 |
| 26080 | GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(66241), |
| 26081 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26082 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 26084 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26085 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26086 | GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(66210), // Rule ID 46843 // |
| 26087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26088 | // (ld:{ *:[nxv8i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE16_V:{ *:[nxv8i16] } GPR:{ *:[i32] }:$rs1) |
| 26089 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE16_V), |
| 26090 | GIR_RootConstrainSelectedInstOperands, |
| 26091 | // GIR_Coverage, 46843, |
| 26092 | GIR_Done, |
| 26093 | // Label 1839: @66210 |
| 26094 | GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(66225), // Rule ID 46879 // |
| 26095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 26096 | // (ld:{ *:[nxv8f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE16_V:{ *:[nxv8f16] } GPR:{ *:[i32] }:$rs1) |
| 26097 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE16_V), |
| 26098 | GIR_RootConstrainSelectedInstOperands, |
| 26099 | // GIR_Coverage, 46879, |
| 26100 | GIR_Done, |
| 26101 | // Label 1840: @66225 |
| 26102 | GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(66240), // Rule ID 46915 // |
| 26103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 26104 | // (ld:{ *:[nxv8bf16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE16_V:{ *:[nxv8bf16] } GPR:{ *:[i32] }:$rs1) |
| 26105 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE16_V), |
| 26106 | GIR_RootConstrainSelectedInstOperands, |
| 26107 | // GIR_Coverage, 46915, |
| 26108 | GIR_Done, |
| 26109 | // Label 1841: @66240 |
| 26110 | GIM_Reject, |
| 26111 | // Label 1838: @66241 |
| 26112 | GIM_Reject, |
| 26113 | // Label 1743: @66242 |
| 26114 | GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(66297), |
| 26115 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26116 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 26118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26119 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26120 | GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(66281), // Rule ID 46859 // |
| 26121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26122 | // (ld:{ *:[nxv8i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE32_V:{ *:[nxv8i32] } GPR:{ *:[i32] }:$rs1) |
| 26123 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE32_V), |
| 26124 | GIR_RootConstrainSelectedInstOperands, |
| 26125 | // GIR_Coverage, 46859, |
| 26126 | GIR_Done, |
| 26127 | // Label 1843: @66281 |
| 26128 | GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(66296), // Rule ID 46895 // |
| 26129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 26130 | // (ld:{ *:[nxv8f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE32_V:{ *:[nxv8f32] } GPR:{ *:[i32] }:$rs1) |
| 26131 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE32_V), |
| 26132 | GIR_RootConstrainSelectedInstOperands, |
| 26133 | // GIR_Coverage, 46895, |
| 26134 | GIR_Done, |
| 26135 | // Label 1844: @66296 |
| 26136 | GIM_Reject, |
| 26137 | // Label 1842: @66297 |
| 26138 | GIM_Reject, |
| 26139 | // Label 1744: @66298 |
| 26140 | GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(66353), |
| 26141 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26142 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 26144 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26145 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26146 | GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(66337), // Rule ID 46875 // |
| 26147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 26148 | // (ld:{ *:[nxv8i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE64_V:{ *:[nxv8i64] } GPR:{ *:[i32] }:$rs1) |
| 26149 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE64_V), |
| 26150 | GIR_RootConstrainSelectedInstOperands, |
| 26151 | // GIR_Coverage, 46875, |
| 26152 | GIR_Done, |
| 26153 | // Label 1846: @66337 |
| 26154 | GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(66352), // Rule ID 46911 // |
| 26155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 26156 | // (ld:{ *:[nxv8f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE64_V:{ *:[nxv8f64] } GPR:{ *:[i32] }:$rs1) |
| 26157 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE64_V), |
| 26158 | GIR_RootConstrainSelectedInstOperands, |
| 26159 | // GIR_Coverage, 46911, |
| 26160 | GIR_Done, |
| 26161 | // Label 1847: @66352 |
| 26162 | GIM_Reject, |
| 26163 | // Label 1845: @66353 |
| 26164 | GIM_Reject, |
| 26165 | // Label 1745: @66354 |
| 26166 | GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(66420), // Rule ID 46939 // |
| 26167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26168 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26169 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 26171 | // MIs[0] rs1 |
| 26172 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26174 | // (ld:{ *:[nxv16i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B16:{ *:[nxv16i1] } (IMPLICIT_DEF:{ *:[nxv16i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 26175 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s1, |
| 26176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B16), |
| 26180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26181 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26182 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 26183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 26184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 26186 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26187 | GIR_RootConstrainSelectedInstOperands, |
| 26188 | // GIR_Coverage, 46939, |
| 26189 | GIR_EraseRootFromParent_Done, |
| 26190 | // Label 1848: @66420 |
| 26191 | GIM_Reject, |
| 26192 | // Label 1746: @66421 |
| 26193 | GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(66455), // Rule ID 46831 // |
| 26194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26195 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26196 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 26198 | // MIs[0] rs1 |
| 26199 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26201 | // (ld:{ *:[nxv16i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL2RE8_V:{ *:[nxv16i8] } GPR:{ *:[i32] }:$rs1) |
| 26202 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL2RE8_V), |
| 26203 | GIR_RootConstrainSelectedInstOperands, |
| 26204 | // GIR_Coverage, 46831, |
| 26205 | GIR_Done, |
| 26206 | // Label 1849: @66455 |
| 26207 | GIM_Reject, |
| 26208 | // Label 1747: @66456 |
| 26209 | GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(66526), |
| 26210 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26211 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 26213 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26215 | GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(66495), // Rule ID 46847 // |
| 26216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26217 | // (ld:{ *:[nxv16i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE16_V:{ *:[nxv16i16] } GPR:{ *:[i32] }:$rs1) |
| 26218 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE16_V), |
| 26219 | GIR_RootConstrainSelectedInstOperands, |
| 26220 | // GIR_Coverage, 46847, |
| 26221 | GIR_Done, |
| 26222 | // Label 1851: @66495 |
| 26223 | GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(66510), // Rule ID 46883 // |
| 26224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 26225 | // (ld:{ *:[nxv16f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE16_V:{ *:[nxv16f16] } GPR:{ *:[i32] }:$rs1) |
| 26226 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE16_V), |
| 26227 | GIR_RootConstrainSelectedInstOperands, |
| 26228 | // GIR_Coverage, 46883, |
| 26229 | GIR_Done, |
| 26230 | // Label 1852: @66510 |
| 26231 | GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(66525), // Rule ID 46919 // |
| 26232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 26233 | // (ld:{ *:[nxv16bf16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE16_V:{ *:[nxv16bf16] } GPR:{ *:[i32] }:$rs1) |
| 26234 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE16_V), |
| 26235 | GIR_RootConstrainSelectedInstOperands, |
| 26236 | // GIR_Coverage, 46919, |
| 26237 | GIR_Done, |
| 26238 | // Label 1853: @66525 |
| 26239 | GIM_Reject, |
| 26240 | // Label 1850: @66526 |
| 26241 | GIM_Reject, |
| 26242 | // Label 1748: @66527 |
| 26243 | GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(66582), |
| 26244 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26245 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 26247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26248 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26249 | GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(66566), // Rule ID 46863 // |
| 26250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26251 | // (ld:{ *:[nxv16i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE32_V:{ *:[nxv16i32] } GPR:{ *:[i32] }:$rs1) |
| 26252 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE32_V), |
| 26253 | GIR_RootConstrainSelectedInstOperands, |
| 26254 | // GIR_Coverage, 46863, |
| 26255 | GIR_Done, |
| 26256 | // Label 1855: @66566 |
| 26257 | GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(66581), // Rule ID 46899 // |
| 26258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 26259 | // (ld:{ *:[nxv16f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE32_V:{ *:[nxv16f32] } GPR:{ *:[i32] }:$rs1) |
| 26260 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE32_V), |
| 26261 | GIR_RootConstrainSelectedInstOperands, |
| 26262 | // GIR_Coverage, 46899, |
| 26263 | GIR_Done, |
| 26264 | // Label 1856: @66581 |
| 26265 | GIM_Reject, |
| 26266 | // Label 1854: @66582 |
| 26267 | GIM_Reject, |
| 26268 | // Label 1749: @66583 |
| 26269 | GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(66649), // Rule ID 46943 // |
| 26270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26271 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26272 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26273 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 26274 | // MIs[0] rs1 |
| 26275 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26277 | // (ld:{ *:[nxv32i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B32:{ *:[nxv32i1] } (IMPLICIT_DEF:{ *:[nxv32i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 26278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s1, |
| 26279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B32), |
| 26283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 26286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 26287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 26289 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26290 | GIR_RootConstrainSelectedInstOperands, |
| 26291 | // GIR_Coverage, 46943, |
| 26292 | GIR_EraseRootFromParent_Done, |
| 26293 | // Label 1857: @66649 |
| 26294 | GIM_Reject, |
| 26295 | // Label 1750: @66650 |
| 26296 | GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(66684), // Rule ID 46835 // |
| 26297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26298 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26299 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 26301 | // MIs[0] rs1 |
| 26302 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26303 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26304 | // (ld:{ *:[nxv32i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL4RE8_V:{ *:[nxv32i8] } GPR:{ *:[i32] }:$rs1) |
| 26305 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL4RE8_V), |
| 26306 | GIR_RootConstrainSelectedInstOperands, |
| 26307 | // GIR_Coverage, 46835, |
| 26308 | GIR_Done, |
| 26309 | // Label 1858: @66684 |
| 26310 | GIM_Reject, |
| 26311 | // Label 1751: @66685 |
| 26312 | GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(66755), |
| 26313 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26314 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26315 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 26316 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26318 | GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(66724), // Rule ID 46851 // |
| 26319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26320 | // (ld:{ *:[nxv32i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE16_V:{ *:[nxv32i16] } GPR:{ *:[i32] }:$rs1) |
| 26321 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE16_V), |
| 26322 | GIR_RootConstrainSelectedInstOperands, |
| 26323 | // GIR_Coverage, 46851, |
| 26324 | GIR_Done, |
| 26325 | // Label 1860: @66724 |
| 26326 | GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(66739), // Rule ID 46887 // |
| 26327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 26328 | // (ld:{ *:[nxv32f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE16_V:{ *:[nxv32f16] } GPR:{ *:[i32] }:$rs1) |
| 26329 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE16_V), |
| 26330 | GIR_RootConstrainSelectedInstOperands, |
| 26331 | // GIR_Coverage, 46887, |
| 26332 | GIR_Done, |
| 26333 | // Label 1861: @66739 |
| 26334 | GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(66754), // Rule ID 46923 // |
| 26335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 26336 | // (ld:{ *:[nxv32bf16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE16_V:{ *:[nxv32bf16] } GPR:{ *:[i32] }:$rs1) |
| 26337 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE16_V), |
| 26338 | GIR_RootConstrainSelectedInstOperands, |
| 26339 | // GIR_Coverage, 46923, |
| 26340 | GIR_Done, |
| 26341 | // Label 1862: @66754 |
| 26342 | GIM_Reject, |
| 26343 | // Label 1859: @66755 |
| 26344 | GIM_Reject, |
| 26345 | // Label 1752: @66756 |
| 26346 | GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(66822), // Rule ID 46947 // |
| 26347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26348 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26349 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 26351 | // MIs[0] rs1 |
| 26352 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26353 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26354 | // (ld:{ *:[nxv64i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (PseudoVLM_V_B64:{ *:[nxv64i1] } (IMPLICIT_DEF:{ *:[nxv64i1] }), GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 26355 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s1, |
| 26356 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26357 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVLM_V_B64), |
| 26360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26361 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26362 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 26363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 26364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 26366 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26367 | GIR_RootConstrainSelectedInstOperands, |
| 26368 | // GIR_Coverage, 46947, |
| 26369 | GIR_EraseRootFromParent_Done, |
| 26370 | // Label 1863: @66822 |
| 26371 | GIM_Reject, |
| 26372 | // Label 1753: @66823 |
| 26373 | GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(66857), // Rule ID 46839 // |
| 26374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 26375 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26376 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 26378 | // MIs[0] rs1 |
| 26379 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 26380 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26381 | // (ld:{ *:[nxv64i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (VL8RE8_V:{ *:[nxv64i8] } GPR:{ *:[i32] }:$rs1) |
| 26382 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VL8RE8_V), |
| 26383 | GIR_RootConstrainSelectedInstOperands, |
| 26384 | // GIR_Coverage, 46839, |
| 26385 | GIR_Done, |
| 26386 | // Label 1864: @66857 |
| 26387 | GIM_Reject, |
| 26388 | // Label 1754: @66858 |
| 26389 | GIM_Reject, |
| 26390 | // Label 19: @66859 |
| 26391 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 1867*/ GIMT_Encode4(67366), |
| 26392 | /*GILLT_s32*//*Label 1865*/ GIMT_Encode4(66878), |
| 26393 | /*GILLT_s64*//*Label 1866*/ GIMT_Encode4(67203), |
| 26394 | // Label 1865: @66878 |
| 26395 | GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(66932), // Rule ID 216 // |
| 26396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 26397 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26398 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26402 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 26404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26407 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26408 | GIR_RootConstrainSelectedInstOperands, |
| 26409 | // GIR_Coverage, 216, |
| 26410 | GIR_EraseRootFromParent_Done, |
| 26411 | // Label 1868: @66932 |
| 26412 | GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(66986), // Rule ID 220 // |
| 26413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 26414 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26415 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26417 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26418 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26419 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 26421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26424 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26425 | GIR_RootConstrainSelectedInstOperands, |
| 26426 | // GIR_Coverage, 220, |
| 26427 | GIR_EraseRootFromParent_Done, |
| 26428 | // Label 1869: @66986 |
| 26429 | GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(67040), // Rule ID 277 // |
| 26430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26431 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26432 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26434 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26436 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 26438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26442 | GIR_RootConstrainSelectedInstOperands, |
| 26443 | // GIR_Coverage, 277, |
| 26444 | GIR_EraseRootFromParent_Done, |
| 26445 | // Label 1870: @67040 |
| 26446 | GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(67094), // Rule ID 278 // |
| 26447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 26448 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26449 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26451 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26452 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26453 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 26455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26458 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26459 | GIR_RootConstrainSelectedInstOperands, |
| 26460 | // GIR_Coverage, 278, |
| 26461 | GIR_EraseRootFromParent_Done, |
| 26462 | // Label 1871: @67094 |
| 26463 | GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(67148), // Rule ID 281 // |
| 26464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26465 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26466 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26468 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26469 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26470 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 26472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26475 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26476 | GIR_RootConstrainSelectedInstOperands, |
| 26477 | // GIR_Coverage, 281, |
| 26478 | GIR_EraseRootFromParent_Done, |
| 26479 | // Label 1872: @67148 |
| 26480 | GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(67202), // Rule ID 282 // |
| 26481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 26482 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26483 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26485 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26486 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26487 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 26489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26493 | GIR_RootConstrainSelectedInstOperands, |
| 26494 | // GIR_Coverage, 282, |
| 26495 | GIR_EraseRootFromParent_Done, |
| 26496 | // Label 1873: @67202 |
| 26497 | GIM_Reject, |
| 26498 | // Label 1866: @67203 |
| 26499 | GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(67257), // Rule ID 215 // |
| 26500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 26501 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26502 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26504 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26505 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26506 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LB), |
| 26508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26511 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26512 | GIR_RootConstrainSelectedInstOperands, |
| 26513 | // GIR_Coverage, 215, |
| 26514 | GIR_EraseRootFromParent_Done, |
| 26515 | // Label 1874: @67257 |
| 26516 | GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(67311), // Rule ID 219 // |
| 26517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 26518 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26519 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26521 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26523 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LH), |
| 26525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26529 | GIR_RootConstrainSelectedInstOperands, |
| 26530 | // GIR_Coverage, 219, |
| 26531 | GIR_EraseRootFromParent_Done, |
| 26532 | // Label 1875: @67311 |
| 26533 | GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(67365), // Rule ID 264 // |
| 26534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26535 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 26536 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26540 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LW), |
| 26542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26546 | GIR_RootConstrainSelectedInstOperands, |
| 26547 | // GIR_Coverage, 264, |
| 26548 | GIR_EraseRootFromParent_Done, |
| 26549 | // Label 1876: @67365 |
| 26550 | GIM_Reject, |
| 26551 | // Label 1867: @67366 |
| 26552 | GIM_Reject, |
| 26553 | // Label 20: @67367 |
| 26554 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 1879*/ GIMT_Encode4(67874), |
| 26555 | /*GILLT_s32*//*Label 1877*/ GIMT_Encode4(67386), |
| 26556 | /*GILLT_s64*//*Label 1878*/ GIMT_Encode4(67711), |
| 26557 | // Label 1877: @67386 |
| 26558 | GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(67440), // Rule ID 226 // |
| 26559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 26560 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26561 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26563 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26564 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26565 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 26567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26571 | GIR_RootConstrainSelectedInstOperands, |
| 26572 | // GIR_Coverage, 226, |
| 26573 | GIR_EraseRootFromParent_Done, |
| 26574 | // Label 1880: @67440 |
| 26575 | GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(67494), // Rule ID 228 // |
| 26576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 26577 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26582 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LHU), |
| 26584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26587 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26588 | GIR_RootConstrainSelectedInstOperands, |
| 26589 | // GIR_Coverage, 228, |
| 26590 | GIR_EraseRootFromParent_Done, |
| 26591 | // Label 1881: @67494 |
| 26592 | GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(67548), // Rule ID 285 // |
| 26593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26594 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26595 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26597 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26599 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 26601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26605 | GIR_RootConstrainSelectedInstOperands, |
| 26606 | // GIR_Coverage, 285, |
| 26607 | GIR_EraseRootFromParent_Done, |
| 26608 | // Label 1882: @67548 |
| 26609 | GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(67602), // Rule ID 286 // |
| 26610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 26611 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26614 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26616 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 26618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26621 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26622 | GIR_RootConstrainSelectedInstOperands, |
| 26623 | // GIR_Coverage, 286, |
| 26624 | GIR_EraseRootFromParent_Done, |
| 26625 | // Label 1883: @67602 |
| 26626 | GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(67656), // Rule ID 287 // |
| 26627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26628 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26629 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26633 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LHU), |
| 26635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26638 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26639 | GIR_RootConstrainSelectedInstOperands, |
| 26640 | // GIR_Coverage, 287, |
| 26641 | GIR_EraseRootFromParent_Done, |
| 26642 | // Label 1884: @67656 |
| 26643 | GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(67710), // Rule ID 288 // |
| 26644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 26645 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26646 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26648 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26650 | // (ld:{ *:[i32] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LHU), |
| 26652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26655 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26656 | GIR_RootConstrainSelectedInstOperands, |
| 26657 | // GIR_Coverage, 288, |
| 26658 | GIR_EraseRootFromParent_Done, |
| 26659 | // Label 1885: @67710 |
| 26660 | GIM_Reject, |
| 26661 | // Label 1878: @67711 |
| 26662 | GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(67765), // Rule ID 225 // |
| 26663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 26664 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26665 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26667 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26669 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LBU), |
| 26671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26675 | GIR_RootConstrainSelectedInstOperands, |
| 26676 | // GIR_Coverage, 225, |
| 26677 | GIR_EraseRootFromParent_Done, |
| 26678 | // Label 1886: @67765 |
| 26679 | GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(67819), // Rule ID 227 // |
| 26680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 26681 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26682 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26686 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LHU), |
| 26688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26692 | GIR_RootConstrainSelectedInstOperands, |
| 26693 | // GIR_Coverage, 227, |
| 26694 | GIR_EraseRootFromParent_Done, |
| 26695 | // Label 1887: @67819 |
| 26696 | GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(67873), // Rule ID 266 // |
| 26697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26698 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 26699 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26701 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26703 | // (ld:{ *:[i64] } (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::LWU), |
| 26705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 26706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26708 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26709 | GIR_RootConstrainSelectedInstOperands, |
| 26710 | // GIR_Coverage, 266, |
| 26711 | GIR_EraseRootFromParent_Done, |
| 26712 | // Label 1888: @67873 |
| 26713 | GIM_Reject, |
| 26714 | // Label 1879: @67874 |
| 26715 | GIM_Reject, |
| 26716 | // Label 21: @67875 |
| 26717 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(34), /*)*//*default:*//*Label 1923*/ GIMT_Encode4(71820), |
| 26718 | /*GILLT_p0s32*//*Label 1889*/ GIMT_Encode4(68022), |
| 26719 | /*GILLT_p0s64*//*Label 1890*/ GIMT_Encode4(68116), |
| 26720 | /*GILLT_s16*//*Label 1891*/ GIMT_Encode4(68210), |
| 26721 | /*GILLT_s32*//*Label 1892*/ GIMT_Encode4(68526), |
| 26722 | /*GILLT_s64*//*Label 1893*/ GIMT_Encode4(69705), |
| 26723 | /*GILLT_nxv1s1*//*Label 1894*/ GIMT_Encode4(70300), |
| 26724 | /*GILLT_nxv1s8*//*Label 1895*/ GIMT_Encode4(70343), |
| 26725 | /*GILLT_nxv1s16*//*Label 1896*/ GIMT_Encode4(70386), |
| 26726 | /*GILLT_nxv1s32*//*Label 1897*/ GIMT_Encode4(70489), |
| 26727 | /*GILLT_nxv1s64*//*Label 1898*/ GIMT_Encode4(70565), |
| 26728 | /*GILLT_nxv2s1*//*Label 1899*/ GIMT_Encode4(70617), |
| 26729 | /*GILLT_nxv2s8*//*Label 1900*/ GIMT_Encode4(70660), |
| 26730 | /*GILLT_nxv2s16*//*Label 1901*/ GIMT_Encode4(70703), |
| 26731 | /*GILLT_nxv2s32*//*Label 1902*/ GIMT_Encode4(70806), |
| 26732 | /*GILLT_nxv2s64*//*Label 1903*/ GIMT_Encode4(70858), |
| 26733 | /*GILLT_nxv4s1*//*Label 1904*/ GIMT_Encode4(70910), |
| 26734 | /*GILLT_nxv4s8*//*Label 1905*/ GIMT_Encode4(70953), |
| 26735 | /*GILLT_nxv4s16*//*Label 1906*/ GIMT_Encode4(70996), |
| 26736 | /*GILLT_nxv4s32*//*Label 1907*/ GIMT_Encode4(71063), |
| 26737 | /*GILLT_nxv4s64*//*Label 1908*/ GIMT_Encode4(71115), |
| 26738 | /*GILLT_nxv8s1*//*Label 1909*/ GIMT_Encode4(71167), |
| 26739 | /*GILLT_nxv8s8*//*Label 1910*/ GIMT_Encode4(71210), |
| 26740 | /*GILLT_nxv8s16*//*Label 1911*/ GIMT_Encode4(71241), |
| 26741 | /*GILLT_nxv8s32*//*Label 1912*/ GIMT_Encode4(71308), |
| 26742 | /*GILLT_nxv8s64*//*Label 1913*/ GIMT_Encode4(71360), |
| 26743 | /*GILLT_nxv16s1*//*Label 1914*/ GIMT_Encode4(71412), |
| 26744 | /*GILLT_nxv16s8*//*Label 1915*/ GIMT_Encode4(71455), |
| 26745 | /*GILLT_nxv16s16*//*Label 1916*/ GIMT_Encode4(71486), |
| 26746 | /*GILLT_nxv16s32*//*Label 1917*/ GIMT_Encode4(71553), |
| 26747 | /*GILLT_nxv32s1*//*Label 1918*/ GIMT_Encode4(71605), |
| 26748 | /*GILLT_nxv32s8*//*Label 1919*/ GIMT_Encode4(71648), |
| 26749 | /*GILLT_nxv32s16*//*Label 1920*/ GIMT_Encode4(71679), |
| 26750 | /*GILLT_nxv64s1*//*Label 1921*/ GIMT_Encode4(71746), |
| 26751 | /*GILLT_nxv64s8*//*Label 1922*/ GIMT_Encode4(71789), |
| 26752 | // Label 1889: @68022 |
| 26753 | GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(68115), |
| 26754 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26755 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26758 | GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(68078), // Rule ID 65134 // |
| 26759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV32_HwMode1), |
| 26760 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26761 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 26763 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26766 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26767 | GIR_RootConstrainSelectedInstOperands, |
| 26768 | // GIR_Coverage, 65134, |
| 26769 | GIR_EraseRootFromParent_Done, |
| 26770 | // Label 1925: @68078 |
| 26771 | GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(68114), // Rule ID 65138 // |
| 26772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 26773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26774 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SD), |
| 26776 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26780 | GIR_RootConstrainSelectedInstOperands, |
| 26781 | // GIR_Coverage, 65138, |
| 26782 | GIR_EraseRootFromParent_Done, |
| 26783 | // Label 1926: @68114 |
| 26784 | GIM_Reject, |
| 26785 | // Label 1924: @68115 |
| 26786 | GIM_Reject, |
| 26787 | // Label 1890: @68116 |
| 26788 | GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(68209), |
| 26789 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26792 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26793 | GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(68172), // Rule ID 65133 // |
| 26794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV32_HwMode0), |
| 26795 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26796 | // (st GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 26798 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26801 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26802 | GIR_RootConstrainSelectedInstOperands, |
| 26803 | // GIR_Coverage, 65133, |
| 26804 | GIR_EraseRootFromParent_Done, |
| 26805 | // Label 1928: @68172 |
| 26806 | GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(68208), // Rule ID 65137 // |
| 26807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 26808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26809 | // (st GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SD), |
| 26811 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26815 | GIR_RootConstrainSelectedInstOperands, |
| 26816 | // GIR_Coverage, 65137, |
| 26817 | GIR_EraseRootFromParent_Done, |
| 26818 | // Label 1929: @68208 |
| 26819 | GIM_Reject, |
| 26820 | // Label 1927: @68209 |
| 26821 | GIM_Reject, |
| 26822 | // Label 1891: @68210 |
| 26823 | GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(68525), |
| 26824 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26825 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26826 | GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(68266), // Rule ID 2200 // |
| 26827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode0), |
| 26828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 26829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26831 | // (st FPR16:{ *:[f16] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSH FPR16:{ *:[f16] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSH), |
| 26833 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26837 | GIR_RootConstrainSelectedInstOperands, |
| 26838 | // GIR_Coverage, 2200, |
| 26839 | GIR_EraseRootFromParent_Done, |
| 26840 | // Label 1931: @68266 |
| 26841 | GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(68310), // Rule ID 2201 // |
| 26842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode1), |
| 26843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 26844 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26845 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26846 | // (st FPR16:{ *:[f16] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSH FPR16:{ *:[f16] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSH), |
| 26848 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26852 | GIR_RootConstrainSelectedInstOperands, |
| 26853 | // GIR_Coverage, 2201, |
| 26854 | GIR_EraseRootFromParent_Done, |
| 26855 | // Label 1932: @68310 |
| 26856 | GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(68373), // Rule ID 2204 // |
| 26857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode0), |
| 26858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 26859 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26861 | // (st FPR16INX:{ *:[f16] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SH (COPY_TO_REGCLASS:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs2, GPR:{ *:[i32] }), GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26862 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26864 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26865 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // rs2 |
| 26866 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 26868 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26871 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26872 | GIR_RootConstrainSelectedInstOperands, |
| 26873 | // GIR_Coverage, 2204, |
| 26874 | GIR_EraseRootFromParent_Done, |
| 26875 | // Label 1933: @68373 |
| 26876 | GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(68436), // Rule ID 2205 // |
| 26877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode1), |
| 26878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 26879 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26881 | // (st FPR16INX:{ *:[f16] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SH (COPY_TO_REGCLASS:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs2, GPR:{ *:[i32] }), GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26882 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26883 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26884 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26885 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // rs2 |
| 26886 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 26888 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26892 | GIR_RootConstrainSelectedInstOperands, |
| 26893 | // GIR_Coverage, 2205, |
| 26894 | GIR_EraseRootFromParent_Done, |
| 26895 | // Label 1934: @68436 |
| 26896 | GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(68480), // Rule ID 2454 // |
| 26897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode0), |
| 26898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 26899 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26901 | // (st FPR16:{ *:[bf16] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSH FPR16:{ *:[bf16] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSH), |
| 26903 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26906 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26907 | GIR_RootConstrainSelectedInstOperands, |
| 26908 | // GIR_Coverage, 2454, |
| 26909 | GIR_EraseRootFromParent_Done, |
| 26910 | // Label 1935: @68480 |
| 26911 | GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(68524), // Rule ID 2455 // |
| 26912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode1), |
| 26913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 26914 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26916 | // (st FPR16:{ *:[bf16] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSH FPR16:{ *:[bf16] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSH), |
| 26918 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26922 | GIR_RootConstrainSelectedInstOperands, |
| 26923 | // GIR_Coverage, 2455, |
| 26924 | GIR_EraseRootFromParent_Done, |
| 26925 | // Label 1936: @68524 |
| 26926 | GIM_Reject, |
| 26927 | // Label 1930: @68525 |
| 26928 | GIM_Reject, |
| 26929 | // Label 1892: @68526 |
| 26930 | GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(68580), // Rule ID 365 // |
| 26931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 26932 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26933 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 26934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26935 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26936 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26937 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_8>> => (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 26939 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26943 | GIR_RootConstrainSelectedInstOperands, |
| 26944 | // GIR_Coverage, 365, |
| 26945 | GIR_EraseRootFromParent_Done, |
| 26946 | // Label 1937: @68580 |
| 26947 | GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(68634), // Rule ID 367 // |
| 26948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 26949 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 26950 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 26951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26954 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_16>> => (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 26956 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26959 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26960 | GIR_RootConstrainSelectedInstOperands, |
| 26961 | // GIR_Coverage, 367, |
| 26962 | GIR_EraseRootFromParent_Done, |
| 26963 | // Label 1938: @68634 |
| 26964 | GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(68688), // Rule ID 369 // |
| 26965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 26966 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 26967 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 26968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26971 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_32>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 26972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 26973 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26976 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26977 | GIR_RootConstrainSelectedInstOperands, |
| 26978 | // GIR_Coverage, 369, |
| 26979 | GIR_EraseRootFromParent_Done, |
| 26980 | // Label 1939: @68688 |
| 26981 | GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(68742), // Rule ID 886 // |
| 26982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 26983 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 26984 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 26985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 26986 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 26988 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_8>> => (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 26989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 26990 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 26991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 26992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 26993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26994 | GIR_RootConstrainSelectedInstOperands, |
| 26995 | // GIR_Coverage, 886, |
| 26996 | GIR_EraseRootFromParent_Done, |
| 26997 | // Label 1940: @68742 |
| 26998 | GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(68796), // Rule ID 887 // |
| 26999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 27000 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 27001 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27003 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27004 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27005 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_8>> => (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 27007 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27011 | GIR_RootConstrainSelectedInstOperands, |
| 27012 | // GIR_Coverage, 887, |
| 27013 | GIR_EraseRootFromParent_Done, |
| 27014 | // Label 1941: @68796 |
| 27015 | GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(68850), // Rule ID 888 // |
| 27016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 27017 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27018 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27021 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27022 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_16>> => (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27024 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27027 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27028 | GIR_RootConstrainSelectedInstOperands, |
| 27029 | // GIR_Coverage, 888, |
| 27030 | GIR_EraseRootFromParent_Done, |
| 27031 | // Label 1942: @68850 |
| 27032 | GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(68904), // Rule ID 889 // |
| 27033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 27034 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27035 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27039 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_16>> => (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27041 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27044 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27045 | GIR_RootConstrainSelectedInstOperands, |
| 27046 | // GIR_Coverage, 889, |
| 27047 | GIR_EraseRootFromParent_Done, |
| 27048 | // Label 1943: @68904 |
| 27049 | GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(68958), // Rule ID 890 // |
| 27050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 27051 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 27052 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27054 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27055 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27056 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_32>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27058 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27061 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27062 | GIR_RootConstrainSelectedInstOperands, |
| 27063 | // GIR_Coverage, 890, |
| 27064 | GIR_EraseRootFromParent_Done, |
| 27065 | // Label 1944: @68958 |
| 27066 | GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(69012), // Rule ID 891 // |
| 27067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode1), |
| 27068 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 27069 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27071 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27073 | // (atomic_store GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_32>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27075 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27079 | GIR_RootConstrainSelectedInstOperands, |
| 27080 | // GIR_Coverage, 891, |
| 27081 | GIR_EraseRootFromParent_Done, |
| 27082 | // Label 1945: @69012 |
| 27083 | GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(69063), // Rule ID 233 // |
| 27084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 27085 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27090 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27092 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27095 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27096 | GIR_RootConstrainSelectedInstOperands, |
| 27097 | // GIR_Coverage, 233, |
| 27098 | GIR_EraseRootFromParent_Done, |
| 27099 | // Label 1946: @69063 |
| 27100 | GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(69114), // Rule ID 234 // |
| 27101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 27102 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27103 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27105 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27107 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27109 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27112 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27113 | GIR_RootConstrainSelectedInstOperands, |
| 27114 | // GIR_Coverage, 234, |
| 27115 | GIR_EraseRootFromParent_Done, |
| 27116 | // Label 1947: @69114 |
| 27117 | GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(69165), // Rule ID 1506 // |
| 27118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 27119 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27120 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 27122 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27124 | // (st FPR32:{ *:[f32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSW), |
| 27126 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27129 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27130 | GIR_RootConstrainSelectedInstOperands, |
| 27131 | // GIR_Coverage, 1506, |
| 27132 | GIR_EraseRootFromParent_Done, |
| 27133 | // Label 1948: @69165 |
| 27134 | GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(69216), // Rule ID 1507 // |
| 27135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 27136 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27137 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 27139 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27140 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27141 | // (st FPR32:{ *:[f32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSW), |
| 27143 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27146 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27147 | GIR_RootConstrainSelectedInstOperands, |
| 27148 | // GIR_Coverage, 1507, |
| 27149 | GIR_EraseRootFromParent_Done, |
| 27150 | // Label 1949: @69216 |
| 27151 | GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(69286), // Rule ID 1512 // |
| 27152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 27153 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27154 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 27156 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27158 | // (st FPR32INX:{ *:[f32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW (COPY_TO_REGCLASS:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs2, GPR:{ *:[i32] }), GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27159 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 27160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 27161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27162 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // rs2 |
| 27163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 27164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27168 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27169 | GIR_RootConstrainSelectedInstOperands, |
| 27170 | // GIR_Coverage, 1512, |
| 27171 | GIR_EraseRootFromParent_Done, |
| 27172 | // Label 1950: @69286 |
| 27173 | GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(69356), // Rule ID 1513 // |
| 27174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 27175 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27176 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 27178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27180 | // (st FPR32INX:{ *:[f32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW (COPY_TO_REGCLASS:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs2, GPR:{ *:[i32] }), GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27181 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 27182 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 27183 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27184 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // rs2 |
| 27185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 27186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27187 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27190 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27191 | GIR_RootConstrainSelectedInstOperands, |
| 27192 | // GIR_Coverage, 1513, |
| 27193 | GIR_EraseRootFromParent_Done, |
| 27194 | // Label 1951: @69356 |
| 27195 | GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(69414), // Rule ID 230 // |
| 27196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 27197 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27198 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 27199 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27201 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27203 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 27205 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27208 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27209 | GIR_RootConstrainSelectedInstOperands, |
| 27210 | // GIR_Coverage, 230, |
| 27211 | GIR_EraseRootFromParent_Done, |
| 27212 | // Label 1952: @69414 |
| 27213 | GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(69472), // Rule ID 232 // |
| 27214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 27215 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27216 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27217 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27221 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27223 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27226 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27227 | GIR_RootConstrainSelectedInstOperands, |
| 27228 | // GIR_Coverage, 232, |
| 27229 | GIR_EraseRootFromParent_Done, |
| 27230 | // Label 1953: @69472 |
| 27231 | GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(69530), // Rule ID 289 // |
| 27232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 27233 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27234 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 27235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27238 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27239 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 27241 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27245 | GIR_RootConstrainSelectedInstOperands, |
| 27246 | // GIR_Coverage, 289, |
| 27247 | GIR_EraseRootFromParent_Done, |
| 27248 | // Label 1954: @69530 |
| 27249 | GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(69588), // Rule ID 290 // |
| 27250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 27251 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27252 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 27253 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27255 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27256 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27257 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 27259 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27262 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27263 | GIR_RootConstrainSelectedInstOperands, |
| 27264 | // GIR_Coverage, 290, |
| 27265 | GIR_EraseRootFromParent_Done, |
| 27266 | // Label 1955: @69588 |
| 27267 | GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(69646), // Rule ID 291 // |
| 27268 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 27269 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27270 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27271 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27273 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27275 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27277 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27281 | GIR_RootConstrainSelectedInstOperands, |
| 27282 | // GIR_Coverage, 291, |
| 27283 | GIR_EraseRootFromParent_Done, |
| 27284 | // Label 1956: @69646 |
| 27285 | GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(69704), // Rule ID 292 // |
| 27286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 27287 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27288 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27289 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27291 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27293 | // (st GPR:{ *:[i32] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27295 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27298 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27299 | GIR_RootConstrainSelectedInstOperands, |
| 27300 | // GIR_Coverage, 292, |
| 27301 | GIR_EraseRootFromParent_Done, |
| 27302 | // Label 1957: @69704 |
| 27303 | GIM_Reject, |
| 27304 | // Label 1893: @69705 |
| 27305 | GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(69759), // Rule ID 364 // |
| 27306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 27307 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 27308 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27310 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27311 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27312 | // (atomic_store GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_8>> => (SB GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 27314 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27317 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27318 | GIR_RootConstrainSelectedInstOperands, |
| 27319 | // GIR_Coverage, 364, |
| 27320 | GIR_EraseRootFromParent_Done, |
| 27321 | // Label 1958: @69759 |
| 27322 | GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(69813), // Rule ID 366 // |
| 27323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 27324 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27325 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27327 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27329 | // (atomic_store GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_16>> => (SH GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27331 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27334 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27335 | GIR_RootConstrainSelectedInstOperands, |
| 27336 | // GIR_Coverage, 366, |
| 27337 | GIR_EraseRootFromParent_Done, |
| 27338 | // Label 1959: @69813 |
| 27339 | GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(69867), // Rule ID 368 // |
| 27340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_HwMode0), |
| 27341 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 27342 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27344 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27346 | // (atomic_store GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_32>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27348 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27351 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27352 | GIR_RootConstrainSelectedInstOperands, |
| 27353 | // GIR_Coverage, 368, |
| 27354 | GIR_EraseRootFromParent_Done, |
| 27355 | // Label 1960: @69867 |
| 27356 | GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(69921), // Rule ID 371 // |
| 27357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicLdSt_IsRV64_HwMode0), |
| 27358 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 27359 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 27360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27361 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27363 | // (atomic_store GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_store_64>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SD), |
| 27365 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27368 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27369 | GIR_RootConstrainSelectedInstOperands, |
| 27370 | // GIR_Coverage, 371, |
| 27371 | GIR_EraseRootFromParent_Done, |
| 27372 | // Label 1961: @69921 |
| 27373 | GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(69972), // Rule ID 269 // |
| 27374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 27375 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27376 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27378 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27379 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27380 | // (st GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SD), |
| 27382 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27385 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27386 | GIR_RootConstrainSelectedInstOperands, |
| 27387 | // GIR_Coverage, 269, |
| 27388 | GIR_EraseRootFromParent_Done, |
| 27389 | // Label 1962: @69972 |
| 27390 | GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(70023), // Rule ID 1891 // |
| 27391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 27392 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27393 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 27395 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27397 | // (st FPR64:{ *:[f64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSD), |
| 27399 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27402 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27403 | GIR_RootConstrainSelectedInstOperands, |
| 27404 | // GIR_Coverage, 1891, |
| 27405 | GIR_EraseRootFromParent_Done, |
| 27406 | // Label 1963: @70023 |
| 27407 | GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(70074), // Rule ID 1892 // |
| 27408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 27409 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27410 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 27412 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27414 | // (st FPR64:{ *:[f64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 27415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSD), |
| 27416 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27420 | GIR_RootConstrainSelectedInstOperands, |
| 27421 | // GIR_Coverage, 1892, |
| 27422 | GIR_EraseRootFromParent_Done, |
| 27423 | // Label 1964: @70074 |
| 27424 | GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(70125), // Rule ID 1895 // |
| 27425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 27426 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27427 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27428 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27429 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27430 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27431 | // (st GPR:{ *:[f64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SD), |
| 27433 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27436 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27437 | GIR_RootConstrainSelectedInstOperands, |
| 27438 | // GIR_Coverage, 1895, |
| 27439 | GIR_EraseRootFromParent_Done, |
| 27440 | // Label 1965: @70125 |
| 27441 | GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(70183), // Rule ID 229 // |
| 27442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 27443 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27444 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 27445 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27447 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27449 | // (st GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (SB GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SB), |
| 27451 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27454 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27455 | GIR_RootConstrainSelectedInstOperands, |
| 27456 | // GIR_Coverage, 229, |
| 27457 | GIR_EraseRootFromParent_Done, |
| 27458 | // Label 1966: @70183 |
| 27459 | GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(70241), // Rule ID 231 // |
| 27460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 27461 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27462 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 27463 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27465 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27466 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27467 | // (st GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (SH GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH), |
| 27469 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27472 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27473 | GIR_RootConstrainSelectedInstOperands, |
| 27474 | // GIR_Coverage, 231, |
| 27475 | GIR_EraseRootFromParent_Done, |
| 27476 | // Label 1967: @70241 |
| 27477 | GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(70299), // Rule ID 268 // |
| 27478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 27479 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27480 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 27481 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27483 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIAddrRegImm), |
| 27485 | // (st GPR:{ *:[i64] }:$rs2, (AddrRegImm:{ *:[iPTR] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 27486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SW), |
| 27487 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs1 |
| 27489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // imm12 |
| 27490 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27491 | GIR_RootConstrainSelectedInstOperands, |
| 27492 | // GIR_Coverage, 268, |
| 27493 | GIR_EraseRootFromParent_Done, |
| 27494 | // Label 1968: @70299 |
| 27495 | GIM_Reject, |
| 27496 | // Label 1894: @70300 |
| 27497 | GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(70342), // Rule ID 46577 // |
| 27498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27499 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27500 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27501 | // MIs[0] rs1 |
| 27502 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27504 | // (st nxv1i1:{ *:[nxv1i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B1 VR:{ *:[nxv1i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 27505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B1), |
| 27506 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27507 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27510 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27511 | GIR_RootConstrainSelectedInstOperands, |
| 27512 | // GIR_Coverage, 46577, |
| 27513 | GIR_EraseRootFromParent_Done, |
| 27514 | // Label 1969: @70342 |
| 27515 | GIM_Reject, |
| 27516 | // Label 1895: @70343 |
| 27517 | GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(70385), // Rule ID 46569 // |
| 27518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27519 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27520 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27521 | // MIs[0] rs1 |
| 27522 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27523 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27524 | // (st nxv1i8:{ *:[nxv1i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE8_V_MF8 VR:{ *:[nxv1i8] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 27525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE8_V_MF8), |
| 27526 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27527 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 27530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27531 | GIR_RootConstrainSelectedInstOperands, |
| 27532 | // GIR_Coverage, 46569, |
| 27533 | GIR_EraseRootFromParent_Done, |
| 27534 | // Label 1970: @70385 |
| 27535 | GIM_Reject, |
| 27536 | // Label 1896: @70386 |
| 27537 | GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(70488), |
| 27538 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27539 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27540 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27541 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27542 | GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(70433), // Rule ID 46773 // |
| 27543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27544 | // (st nxv1i16:{ *:[nxv1i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE16_V_MF4 VR:{ *:[nxv1i16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 27545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE16_V_MF4), |
| 27546 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27547 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 27550 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27551 | GIR_RootConstrainSelectedInstOperands, |
| 27552 | // GIR_Coverage, 46773, |
| 27553 | GIR_EraseRootFromParent_Done, |
| 27554 | // Label 1972: @70433 |
| 27555 | GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(70460), // Rule ID 46785 // |
| 27556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 27557 | // (st nxv1f16:{ *:[nxv1f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE16_V_MF4 VR:{ *:[nxv1f16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 27558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE16_V_MF4), |
| 27559 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 27563 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27564 | GIR_RootConstrainSelectedInstOperands, |
| 27565 | // GIR_Coverage, 46785, |
| 27566 | GIR_EraseRootFromParent_Done, |
| 27567 | // Label 1973: @70460 |
| 27568 | GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(70487), // Rule ID 46797 // |
| 27569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 27570 | // (st nxv1bf16:{ *:[nxv1bf16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE16_V_MF4 VR:{ *:[nxv1bf16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 27571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE16_V_MF4), |
| 27572 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27573 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 27576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27577 | GIR_RootConstrainSelectedInstOperands, |
| 27578 | // GIR_Coverage, 46797, |
| 27579 | GIR_EraseRootFromParent_Done, |
| 27580 | // Label 1974: @70487 |
| 27581 | GIM_Reject, |
| 27582 | // Label 1971: @70488 |
| 27583 | GIM_Reject, |
| 27584 | // Label 1897: @70489 |
| 27585 | GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(70564), |
| 27586 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27587 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27588 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27590 | GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(70536), // Rule ID 46781 // |
| 27591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27592 | // (st nxv1i32:{ *:[nxv1i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE32_V_MF2 VR:{ *:[nxv1i32] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 27593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE32_V_MF2), |
| 27594 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27595 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 27598 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27599 | GIR_RootConstrainSelectedInstOperands, |
| 27600 | // GIR_Coverage, 46781, |
| 27601 | GIR_EraseRootFromParent_Done, |
| 27602 | // Label 1976: @70536 |
| 27603 | GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(70563), // Rule ID 46793 // |
| 27604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 27605 | // (st nxv1f32:{ *:[nxv1f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE32_V_MF2 VR:{ *:[nxv1f32] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 27606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE32_V_MF2), |
| 27607 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27608 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 27611 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27612 | GIR_RootConstrainSelectedInstOperands, |
| 27613 | // GIR_Coverage, 46793, |
| 27614 | GIR_EraseRootFromParent_Done, |
| 27615 | // Label 1977: @70563 |
| 27616 | GIM_Reject, |
| 27617 | // Label 1975: @70564 |
| 27618 | GIM_Reject, |
| 27619 | // Label 1898: @70565 |
| 27620 | GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(70616), |
| 27621 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27622 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27623 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27624 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27625 | GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(70600), // Rule ID 46813 // |
| 27626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 27627 | // (st nxv1i64:{ *:[nxv1i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv1i64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27628 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27629 | GIR_RootConstrainSelectedInstOperands, |
| 27630 | // GIR_Coverage, 46813, |
| 27631 | GIR_Done, |
| 27632 | // Label 1979: @70600 |
| 27633 | GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(70615), // Rule ID 46829 // |
| 27634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 27635 | // (st nxv1f64:{ *:[nxv1f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv1f64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27636 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27637 | GIR_RootConstrainSelectedInstOperands, |
| 27638 | // GIR_Coverage, 46829, |
| 27639 | GIR_Done, |
| 27640 | // Label 1980: @70615 |
| 27641 | GIM_Reject, |
| 27642 | // Label 1978: @70616 |
| 27643 | GIM_Reject, |
| 27644 | // Label 1899: @70617 |
| 27645 | GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(70659), // Rule ID 46929 // |
| 27646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27647 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27648 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27649 | // MIs[0] rs1 |
| 27650 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27652 | // (st nxv2i1:{ *:[nxv2i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B2 VR:{ *:[nxv2i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 27653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B2), |
| 27654 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27655 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27659 | GIR_RootConstrainSelectedInstOperands, |
| 27660 | // GIR_Coverage, 46929, |
| 27661 | GIR_EraseRootFromParent_Done, |
| 27662 | // Label 1981: @70659 |
| 27663 | GIM_Reject, |
| 27664 | // Label 1900: @70660 |
| 27665 | GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(70702), // Rule ID 46765 // |
| 27666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27667 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27668 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27669 | // MIs[0] rs1 |
| 27670 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27672 | // (st nxv2i8:{ *:[nxv2i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE8_V_MF4 VR:{ *:[nxv2i8] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 27673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE8_V_MF4), |
| 27674 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27675 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 27678 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27679 | GIR_RootConstrainSelectedInstOperands, |
| 27680 | // GIR_Coverage, 46765, |
| 27681 | GIR_EraseRootFromParent_Done, |
| 27682 | // Label 1982: @70702 |
| 27683 | GIM_Reject, |
| 27684 | // Label 1901: @70703 |
| 27685 | GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(70805), |
| 27686 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27687 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27688 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27689 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27690 | GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(70750), // Rule ID 46777 // |
| 27691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27692 | // (st nxv2i16:{ *:[nxv2i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE16_V_MF2 VR:{ *:[nxv2i16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 27693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE16_V_MF2), |
| 27694 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27695 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 27698 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27699 | GIR_RootConstrainSelectedInstOperands, |
| 27700 | // GIR_Coverage, 46777, |
| 27701 | GIR_EraseRootFromParent_Done, |
| 27702 | // Label 1984: @70750 |
| 27703 | GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(70777), // Rule ID 46789 // |
| 27704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 27705 | // (st nxv2f16:{ *:[nxv2f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE16_V_MF2 VR:{ *:[nxv2f16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 27706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE16_V_MF2), |
| 27707 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27708 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 27711 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27712 | GIR_RootConstrainSelectedInstOperands, |
| 27713 | // GIR_Coverage, 46789, |
| 27714 | GIR_EraseRootFromParent_Done, |
| 27715 | // Label 1985: @70777 |
| 27716 | GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(70804), // Rule ID 46801 // |
| 27717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 27718 | // (st nxv2bf16:{ *:[nxv2bf16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE16_V_MF2 VR:{ *:[nxv2bf16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 27719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE16_V_MF2), |
| 27720 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27721 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 27724 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27725 | GIR_RootConstrainSelectedInstOperands, |
| 27726 | // GIR_Coverage, 46801, |
| 27727 | GIR_EraseRootFromParent_Done, |
| 27728 | // Label 1986: @70804 |
| 27729 | GIM_Reject, |
| 27730 | // Label 1983: @70805 |
| 27731 | GIM_Reject, |
| 27732 | // Label 1902: @70806 |
| 27733 | GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(70857), |
| 27734 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27735 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27736 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27737 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27738 | GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(70841), // Rule ID 46809 // |
| 27739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27740 | // (st nxv2i32:{ *:[nxv2i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv2i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27742 | GIR_RootConstrainSelectedInstOperands, |
| 27743 | // GIR_Coverage, 46809, |
| 27744 | GIR_Done, |
| 27745 | // Label 1988: @70841 |
| 27746 | GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(70856), // Rule ID 46825 // |
| 27747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 27748 | // (st nxv2f32:{ *:[nxv2f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv2f32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27749 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27750 | GIR_RootConstrainSelectedInstOperands, |
| 27751 | // GIR_Coverage, 46825, |
| 27752 | GIR_Done, |
| 27753 | // Label 1989: @70856 |
| 27754 | GIM_Reject, |
| 27755 | // Label 1987: @70857 |
| 27756 | GIM_Reject, |
| 27757 | // Label 1903: @70858 |
| 27758 | GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(70909), |
| 27759 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27760 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27761 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27763 | GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(70893), // Rule ID 46869 // |
| 27764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 27765 | // (st nxv2i64:{ *:[nxv2i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv2i64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27766 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27767 | GIR_RootConstrainSelectedInstOperands, |
| 27768 | // GIR_Coverage, 46869, |
| 27769 | GIR_Done, |
| 27770 | // Label 1991: @70893 |
| 27771 | GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(70908), // Rule ID 46905 // |
| 27772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 27773 | // (st nxv2f64:{ *:[nxv2f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv2f64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27774 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27775 | GIR_RootConstrainSelectedInstOperands, |
| 27776 | // GIR_Coverage, 46905, |
| 27777 | GIR_Done, |
| 27778 | // Label 1992: @70908 |
| 27779 | GIM_Reject, |
| 27780 | // Label 1990: @70909 |
| 27781 | GIM_Reject, |
| 27782 | // Label 1904: @70910 |
| 27783 | GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(70952), // Rule ID 46933 // |
| 27784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27785 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27786 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27787 | // MIs[0] rs1 |
| 27788 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27789 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27790 | // (st nxv4i1:{ *:[nxv4i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B4 VR:{ *:[nxv4i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 27791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B4), |
| 27792 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27793 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27796 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27797 | GIR_RootConstrainSelectedInstOperands, |
| 27798 | // GIR_Coverage, 46933, |
| 27799 | GIR_EraseRootFromParent_Done, |
| 27800 | // Label 1993: @70952 |
| 27801 | GIM_Reject, |
| 27802 | // Label 1905: @70953 |
| 27803 | GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(70995), // Rule ID 46769 // |
| 27804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27805 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27806 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27807 | // MIs[0] rs1 |
| 27808 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27809 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27810 | // (st nxv4i8:{ *:[nxv4i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSE8_V_MF2 VR:{ *:[nxv4i8] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 27811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSE8_V_MF2), |
| 27812 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27813 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 27816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27817 | GIR_RootConstrainSelectedInstOperands, |
| 27818 | // GIR_Coverage, 46769, |
| 27819 | GIR_EraseRootFromParent_Done, |
| 27820 | // Label 1994: @70995 |
| 27821 | GIM_Reject, |
| 27822 | // Label 1906: @70996 |
| 27823 | GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(71062), |
| 27824 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27825 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27826 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27828 | GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(71031), // Rule ID 46805 // |
| 27829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27830 | // (st nxv4i16:{ *:[nxv4i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv4i16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27831 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27832 | GIR_RootConstrainSelectedInstOperands, |
| 27833 | // GIR_Coverage, 46805, |
| 27834 | GIR_Done, |
| 27835 | // Label 1996: @71031 |
| 27836 | GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(71046), // Rule ID 46817 // |
| 27837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 27838 | // (st nxv4bf16:{ *:[nxv4bf16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv4bf16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27839 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27840 | GIR_RootConstrainSelectedInstOperands, |
| 27841 | // GIR_Coverage, 46817, |
| 27842 | GIR_Done, |
| 27843 | // Label 1997: @71046 |
| 27844 | GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(71061), // Rule ID 46821 // |
| 27845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 27846 | // (st nxv4f16:{ *:[nxv4f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv4f16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27847 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27848 | GIR_RootConstrainSelectedInstOperands, |
| 27849 | // GIR_Coverage, 46821, |
| 27850 | GIR_Done, |
| 27851 | // Label 1998: @71061 |
| 27852 | GIM_Reject, |
| 27853 | // Label 1995: @71062 |
| 27854 | GIM_Reject, |
| 27855 | // Label 1907: @71063 |
| 27856 | GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(71114), |
| 27857 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27858 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27859 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27860 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27861 | GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(71098), // Rule ID 46857 // |
| 27862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27863 | // (st nxv4i32:{ *:[nxv4i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv4i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27864 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27865 | GIR_RootConstrainSelectedInstOperands, |
| 27866 | // GIR_Coverage, 46857, |
| 27867 | GIR_Done, |
| 27868 | // Label 2000: @71098 |
| 27869 | GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(71113), // Rule ID 46893 // |
| 27870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 27871 | // (st nxv4f32:{ *:[nxv4f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv4f32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27872 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27873 | GIR_RootConstrainSelectedInstOperands, |
| 27874 | // GIR_Coverage, 46893, |
| 27875 | GIR_Done, |
| 27876 | // Label 2001: @71113 |
| 27877 | GIM_Reject, |
| 27878 | // Label 1999: @71114 |
| 27879 | GIM_Reject, |
| 27880 | // Label 1908: @71115 |
| 27881 | GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(71166), |
| 27882 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27883 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27884 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27885 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27886 | GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(71150), // Rule ID 46873 // |
| 27887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 27888 | // (st nxv4i64:{ *:[nxv4i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv4i64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27889 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 27890 | GIR_RootConstrainSelectedInstOperands, |
| 27891 | // GIR_Coverage, 46873, |
| 27892 | GIR_Done, |
| 27893 | // Label 2003: @71150 |
| 27894 | GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(71165), // Rule ID 46909 // |
| 27895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 27896 | // (st nxv4f64:{ *:[nxv4f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv4f64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27897 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 27898 | GIR_RootConstrainSelectedInstOperands, |
| 27899 | // GIR_Coverage, 46909, |
| 27900 | GIR_Done, |
| 27901 | // Label 2004: @71165 |
| 27902 | GIM_Reject, |
| 27903 | // Label 2002: @71166 |
| 27904 | GIM_Reject, |
| 27905 | // Label 1909: @71167 |
| 27906 | GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(71209), // Rule ID 46937 // |
| 27907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27908 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27909 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27910 | // MIs[0] rs1 |
| 27911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27912 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27913 | // (st nxv8i1:{ *:[nxv8i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B8 VR:{ *:[nxv8i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 27914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B8), |
| 27915 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 27916 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 27917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 27918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27919 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27920 | GIR_RootConstrainSelectedInstOperands, |
| 27921 | // GIR_Coverage, 46937, |
| 27922 | GIR_EraseRootFromParent_Done, |
| 27923 | // Label 2005: @71209 |
| 27924 | GIM_Reject, |
| 27925 | // Label 1910: @71210 |
| 27926 | GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(71240), // Rule ID 46573 // |
| 27927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27928 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27930 | // MIs[0] rs1 |
| 27931 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27932 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27933 | // (st nxv8i8:{ *:[nxv8i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS1R_V VR:{ *:[nxv8i8] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27934 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS1R_V), |
| 27935 | GIR_RootConstrainSelectedInstOperands, |
| 27936 | // GIR_Coverage, 46573, |
| 27937 | GIR_Done, |
| 27938 | // Label 2006: @71240 |
| 27939 | GIM_Reject, |
| 27940 | // Label 1911: @71241 |
| 27941 | GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(71307), |
| 27942 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27943 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27944 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27945 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27946 | GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(71276), // Rule ID 46845 // |
| 27947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27948 | // (st nxv8i16:{ *:[nxv8i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv8i16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27949 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27950 | GIR_RootConstrainSelectedInstOperands, |
| 27951 | // GIR_Coverage, 46845, |
| 27952 | GIR_Done, |
| 27953 | // Label 2008: @71276 |
| 27954 | GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(71291), // Rule ID 46881 // |
| 27955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 27956 | // (st nxv8f16:{ *:[nxv8f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv8f16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27957 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27958 | GIR_RootConstrainSelectedInstOperands, |
| 27959 | // GIR_Coverage, 46881, |
| 27960 | GIR_Done, |
| 27961 | // Label 2009: @71291 |
| 27962 | GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(71306), // Rule ID 46917 // |
| 27963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 27964 | // (st nxv8bf16:{ *:[nxv8bf16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv8bf16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27965 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 27966 | GIR_RootConstrainSelectedInstOperands, |
| 27967 | // GIR_Coverage, 46917, |
| 27968 | GIR_Done, |
| 27969 | // Label 2010: @71306 |
| 27970 | GIM_Reject, |
| 27971 | // Label 2007: @71307 |
| 27972 | GIM_Reject, |
| 27973 | // Label 1912: @71308 |
| 27974 | GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(71359), |
| 27975 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 27978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 27979 | GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(71343), // Rule ID 46861 // |
| 27980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 27981 | // (st nxv8i32:{ *:[nxv8i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv8i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27982 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 27983 | GIR_RootConstrainSelectedInstOperands, |
| 27984 | // GIR_Coverage, 46861, |
| 27985 | GIR_Done, |
| 27986 | // Label 2012: @71343 |
| 27987 | GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(71358), // Rule ID 46897 // |
| 27988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 27989 | // (st nxv8f32:{ *:[nxv8f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv8f32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 27990 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 27991 | GIR_RootConstrainSelectedInstOperands, |
| 27992 | // GIR_Coverage, 46897, |
| 27993 | GIR_Done, |
| 27994 | // Label 2013: @71358 |
| 27995 | GIM_Reject, |
| 27996 | // Label 2011: @71359 |
| 27997 | GIM_Reject, |
| 27998 | // Label 1913: @71360 |
| 27999 | GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(71411), |
| 28000 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28001 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28004 | GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(71395), // Rule ID 46877 // |
| 28005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 28006 | // (st nxv8i64:{ *:[nxv8i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv8i64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28007 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28008 | GIR_RootConstrainSelectedInstOperands, |
| 28009 | // GIR_Coverage, 46877, |
| 28010 | GIR_Done, |
| 28011 | // Label 2015: @71395 |
| 28012 | GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(71410), // Rule ID 46913 // |
| 28013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 28014 | // (st nxv8f64:{ *:[nxv8f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv8f64] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28015 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28016 | GIR_RootConstrainSelectedInstOperands, |
| 28017 | // GIR_Coverage, 46913, |
| 28018 | GIR_Done, |
| 28019 | // Label 2016: @71410 |
| 28020 | GIM_Reject, |
| 28021 | // Label 2014: @71411 |
| 28022 | GIM_Reject, |
| 28023 | // Label 1914: @71412 |
| 28024 | GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(71454), // Rule ID 46941 // |
| 28025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28026 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28027 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28028 | // MIs[0] rs1 |
| 28029 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28031 | // (st nxv16i1:{ *:[nxv16i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B16 VR:{ *:[nxv16i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 28032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B16), |
| 28033 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 28034 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 28035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 28036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28037 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28038 | GIR_RootConstrainSelectedInstOperands, |
| 28039 | // GIR_Coverage, 46941, |
| 28040 | GIR_EraseRootFromParent_Done, |
| 28041 | // Label 2017: @71454 |
| 28042 | GIM_Reject, |
| 28043 | // Label 1915: @71455 |
| 28044 | GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(71485), // Rule ID 46833 // |
| 28045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28046 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28047 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28048 | // MIs[0] rs1 |
| 28049 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28050 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28051 | // (st nxv16i8:{ *:[nxv16i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS2R_V VRM2:{ *:[nxv16i8] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28052 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS2R_V), |
| 28053 | GIR_RootConstrainSelectedInstOperands, |
| 28054 | // GIR_Coverage, 46833, |
| 28055 | GIR_Done, |
| 28056 | // Label 2018: @71485 |
| 28057 | GIM_Reject, |
| 28058 | // Label 1916: @71486 |
| 28059 | GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(71552), |
| 28060 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28061 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28064 | GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(71521), // Rule ID 46849 // |
| 28065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28066 | // (st nxv16i16:{ *:[nxv16i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv16i16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28067 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 28068 | GIR_RootConstrainSelectedInstOperands, |
| 28069 | // GIR_Coverage, 46849, |
| 28070 | GIR_Done, |
| 28071 | // Label 2020: @71521 |
| 28072 | GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(71536), // Rule ID 46885 // |
| 28073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 28074 | // (st nxv16f16:{ *:[nxv16f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv16f16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28075 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 28076 | GIR_RootConstrainSelectedInstOperands, |
| 28077 | // GIR_Coverage, 46885, |
| 28078 | GIR_Done, |
| 28079 | // Label 2021: @71536 |
| 28080 | GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(71551), // Rule ID 46921 // |
| 28081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 28082 | // (st nxv16bf16:{ *:[nxv16bf16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv16bf16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28083 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 28084 | GIR_RootConstrainSelectedInstOperands, |
| 28085 | // GIR_Coverage, 46921, |
| 28086 | GIR_Done, |
| 28087 | // Label 2022: @71551 |
| 28088 | GIM_Reject, |
| 28089 | // Label 2019: @71552 |
| 28090 | GIM_Reject, |
| 28091 | // Label 1917: @71553 |
| 28092 | GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(71604), |
| 28093 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28094 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28095 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28096 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28097 | GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(71588), // Rule ID 46865 // |
| 28098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28099 | // (st nxv16i32:{ *:[nxv16i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv16i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28100 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28101 | GIR_RootConstrainSelectedInstOperands, |
| 28102 | // GIR_Coverage, 46865, |
| 28103 | GIR_Done, |
| 28104 | // Label 2024: @71588 |
| 28105 | GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(71603), // Rule ID 46901 // |
| 28106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 28107 | // (st nxv16f32:{ *:[nxv16f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv16f32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28108 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28109 | GIR_RootConstrainSelectedInstOperands, |
| 28110 | // GIR_Coverage, 46901, |
| 28111 | GIR_Done, |
| 28112 | // Label 2025: @71603 |
| 28113 | GIM_Reject, |
| 28114 | // Label 2023: @71604 |
| 28115 | GIM_Reject, |
| 28116 | // Label 1918: @71605 |
| 28117 | GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(71647), // Rule ID 46945 // |
| 28118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28119 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28120 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28121 | // MIs[0] rs1 |
| 28122 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28124 | // (st nxv32i1:{ *:[nxv32i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B32 VR:{ *:[nxv32i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 28125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B32), |
| 28126 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 28127 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 28128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 28129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28130 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28131 | GIR_RootConstrainSelectedInstOperands, |
| 28132 | // GIR_Coverage, 46945, |
| 28133 | GIR_EraseRootFromParent_Done, |
| 28134 | // Label 2026: @71647 |
| 28135 | GIM_Reject, |
| 28136 | // Label 1919: @71648 |
| 28137 | GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(71678), // Rule ID 46837 // |
| 28138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28139 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28141 | // MIs[0] rs1 |
| 28142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28144 | // (st nxv32i8:{ *:[nxv32i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS4R_V VRM4:{ *:[nxv32i8] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28145 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS4R_V), |
| 28146 | GIR_RootConstrainSelectedInstOperands, |
| 28147 | // GIR_Coverage, 46837, |
| 28148 | GIR_Done, |
| 28149 | // Label 2027: @71678 |
| 28150 | GIM_Reject, |
| 28151 | // Label 1920: @71679 |
| 28152 | GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(71745), |
| 28153 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28154 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28155 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28157 | GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(71714), // Rule ID 46853 // |
| 28158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28159 | // (st nxv32i16:{ *:[nxv32i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv32i16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28160 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28161 | GIR_RootConstrainSelectedInstOperands, |
| 28162 | // GIR_Coverage, 46853, |
| 28163 | GIR_Done, |
| 28164 | // Label 2029: @71714 |
| 28165 | GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(71729), // Rule ID 46889 // |
| 28166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 28167 | // (st nxv32f16:{ *:[nxv32f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv32f16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28168 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28169 | GIR_RootConstrainSelectedInstOperands, |
| 28170 | // GIR_Coverage, 46889, |
| 28171 | GIR_Done, |
| 28172 | // Label 2030: @71729 |
| 28173 | GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(71744), // Rule ID 46925 // |
| 28174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 28175 | // (st nxv32bf16:{ *:[nxv32bf16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv32bf16] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28176 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28177 | GIR_RootConstrainSelectedInstOperands, |
| 28178 | // GIR_Coverage, 46925, |
| 28179 | GIR_Done, |
| 28180 | // Label 2031: @71744 |
| 28181 | GIM_Reject, |
| 28182 | // Label 2028: @71745 |
| 28183 | GIM_Reject, |
| 28184 | // Label 1921: @71746 |
| 28185 | GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(71788), // Rule ID 46949 // |
| 28186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28187 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28188 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28189 | // MIs[0] rs1 |
| 28190 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28191 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28192 | // (st nxv64i1:{ *:[nxv64i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (PseudoVSM_V_B64 VR:{ *:[nxv64i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] }) |
| 28193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSM_V_B64), |
| 28194 | GIR_RootToRootCopy, /*OpIdx*/0, // rs2 |
| 28195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 28196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 28197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28198 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28199 | GIR_RootConstrainSelectedInstOperands, |
| 28200 | // GIR_Coverage, 46949, |
| 28201 | GIR_EraseRootFromParent_Done, |
| 28202 | // Label 2032: @71788 |
| 28203 | GIM_Reject, |
| 28204 | // Label 1922: @71789 |
| 28205 | GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(71819), // Rule ID 46841 // |
| 28206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 28207 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28208 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28209 | // MIs[0] rs1 |
| 28210 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28211 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28212 | // (st nxv64i8:{ *:[nxv64i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (VS8R_V VRM8:{ *:[nxv64i8] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 28213 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::VS8R_V), |
| 28214 | GIR_RootConstrainSelectedInstOperands, |
| 28215 | // GIR_Coverage, 46841, |
| 28216 | GIR_Done, |
| 28217 | // Label 2033: @71819 |
| 28218 | GIM_Reject, |
| 28219 | // Label 1923: @71820 |
| 28220 | GIM_Reject, |
| 28221 | // Label 22: @71821 |
| 28222 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2036*/ GIMT_Encode4(76376), |
| 28223 | /*GILLT_s32*//*Label 2034*/ GIMT_Encode4(71840), |
| 28224 | /*GILLT_s64*//*Label 2035*/ GIMT_Encode4(74163), |
| 28225 | // Label 2034: @71840 |
| 28226 | GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(74162), |
| 28227 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28228 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28229 | GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(71917), // Rule ID 674 // |
| 28230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NoStdExtZacas_HwMode1), |
| 28231 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28232 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28233 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28234 | // MIs[0] addr |
| 28235 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28236 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28237 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28238 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28239 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] }) |
| 28240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28243 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28244 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28245 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28246 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 28248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28249 | GIR_RootConstrainSelectedInstOperands, |
| 28250 | // GIR_Coverage, 674, |
| 28251 | GIR_EraseRootFromParent_Done, |
| 28252 | // Label 2038: @71917 |
| 28253 | GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(71983), // Rule ID 676 // |
| 28254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NoStdExtZacas_HwMode1), |
| 28255 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28256 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28257 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28258 | // MIs[0] addr |
| 28259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28261 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28262 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28263 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] }) |
| 28264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28267 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28268 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28269 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28270 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 28272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28273 | GIR_RootConstrainSelectedInstOperands, |
| 28274 | // GIR_Coverage, 676, |
| 28275 | GIR_EraseRootFromParent_Done, |
| 28276 | // Label 2039: @71983 |
| 28277 | GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(72049), // Rule ID 678 // |
| 28278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NoStdExtZacas_HwMode1), |
| 28279 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28280 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28282 | // MIs[0] addr |
| 28283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28284 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28286 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28287 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] }) |
| 28288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28291 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28292 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28293 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28294 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 28296 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28297 | GIR_RootConstrainSelectedInstOperands, |
| 28298 | // GIR_Coverage, 678, |
| 28299 | GIR_EraseRootFromParent_Done, |
| 28300 | // Label 2040: @72049 |
| 28301 | GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(72115), // Rule ID 680 // |
| 28302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NoStdExtZacas_HwMode1), |
| 28303 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28304 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28306 | // MIs[0] addr |
| 28307 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28308 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28309 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28310 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28311 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] }) |
| 28312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28315 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28316 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28317 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28318 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 28320 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28321 | GIR_RootConstrainSelectedInstOperands, |
| 28322 | // GIR_Coverage, 680, |
| 28323 | GIR_EraseRootFromParent_Done, |
| 28324 | // Label 2041: @72115 |
| 28325 | GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(72181), // Rule ID 682 // |
| 28326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NoStdExtZacas_HwMode1), |
| 28327 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28328 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28330 | // MIs[0] addr |
| 28331 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28332 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28333 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28334 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28335 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] }) |
| 28336 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28339 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28340 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28341 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28342 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 28344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28345 | GIR_RootConstrainSelectedInstOperands, |
| 28346 | // GIR_Coverage, 682, |
| 28347 | GIR_EraseRootFromParent_Done, |
| 28348 | // Label 2042: @72181 |
| 28349 | GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(72247), // Rule ID 871 // |
| 28350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_HwMode1), |
| 28351 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28352 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28354 | // MIs[0] addr |
| 28355 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28356 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28358 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28359 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] }) |
| 28360 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28363 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28364 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28365 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28366 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 28368 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28369 | GIR_RootConstrainSelectedInstOperands, |
| 28370 | // GIR_Coverage, 871, |
| 28371 | GIR_EraseRootFromParent_Done, |
| 28372 | // Label 2043: @72247 |
| 28373 | GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(72313), // Rule ID 873 // |
| 28374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_HwMode1), |
| 28375 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28376 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28378 | // MIs[0] addr |
| 28379 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28380 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28381 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28382 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28383 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] }) |
| 28384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28387 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28388 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28389 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28390 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 28392 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28393 | GIR_RootConstrainSelectedInstOperands, |
| 28394 | // GIR_Coverage, 873, |
| 28395 | GIR_EraseRootFromParent_Done, |
| 28396 | // Label 2044: @72313 |
| 28397 | GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(72379), // Rule ID 875 // |
| 28398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_HwMode1), |
| 28399 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28400 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28401 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28402 | // MIs[0] addr |
| 28403 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28404 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28405 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28406 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28407 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] }) |
| 28408 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28411 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28412 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28413 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28414 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 28416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28417 | GIR_RootConstrainSelectedInstOperands, |
| 28418 | // GIR_Coverage, 875, |
| 28419 | GIR_EraseRootFromParent_Done, |
| 28420 | // Label 2045: @72379 |
| 28421 | GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(72445), // Rule ID 877 // |
| 28422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_HwMode1), |
| 28423 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28424 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28426 | // MIs[0] addr |
| 28427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28430 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28431 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] }) |
| 28432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28435 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28436 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28437 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28438 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 28440 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28441 | GIR_RootConstrainSelectedInstOperands, |
| 28442 | // GIR_Coverage, 877, |
| 28443 | GIR_EraseRootFromParent_Done, |
| 28444 | // Label 2046: @72445 |
| 28445 | GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(72511), // Rule ID 879 // |
| 28446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_HwMode1), |
| 28447 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28448 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28450 | // MIs[0] addr |
| 28451 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28452 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28454 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28455 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] }) |
| 28456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 28457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCmpXchg32), |
| 28458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 28459 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 28460 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28461 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28462 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 28464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28465 | GIR_RootConstrainSelectedInstOperands, |
| 28466 | // GIR_Coverage, 879, |
| 28467 | GIR_EraseRootFromParent_Done, |
| 28468 | // Label 2047: @72511 |
| 28469 | GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(72566), // Rule ID 893 // |
| 28470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28471 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28472 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28474 | // MIs[0] addr |
| 28475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28476 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28477 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28478 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28479 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (AMOCAS_W:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 28481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28482 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28483 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28484 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28486 | GIR_RootConstrainSelectedInstOperands, |
| 28487 | // GIR_Coverage, 893, |
| 28488 | GIR_EraseRootFromParent_Done, |
| 28489 | // Label 2048: @72566 |
| 28490 | GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(72621), // Rule ID 895 // |
| 28491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28492 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28493 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28495 | // MIs[0] addr |
| 28496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28497 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28498 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28499 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28500 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (AMOCAS_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_AQ), |
| 28502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28503 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28504 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28505 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28507 | GIR_RootConstrainSelectedInstOperands, |
| 28508 | // GIR_Coverage, 895, |
| 28509 | GIR_EraseRootFromParent_Done, |
| 28510 | // Label 2049: @72621 |
| 28511 | GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(72676), // Rule ID 897 // |
| 28512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28513 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28514 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28516 | // MIs[0] addr |
| 28517 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28518 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28519 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28520 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28521 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (AMOCAS_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_RL), |
| 28523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28524 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28525 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28526 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28527 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28528 | GIR_RootConstrainSelectedInstOperands, |
| 28529 | // GIR_Coverage, 897, |
| 28530 | GIR_EraseRootFromParent_Done, |
| 28531 | // Label 2050: @72676 |
| 28532 | GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(72731), // Rule ID 899 // |
| 28533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28534 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28535 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28537 | // MIs[0] addr |
| 28538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28540 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28541 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28542 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (AMOCAS_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_AQ_RL), |
| 28544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28545 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28546 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28547 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28549 | GIR_RootConstrainSelectedInstOperands, |
| 28550 | // GIR_Coverage, 899, |
| 28551 | GIR_EraseRootFromParent_Done, |
| 28552 | // Label 2051: @72731 |
| 28553 | GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(72786), // Rule ID 901 // |
| 28554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28555 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28556 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28558 | // MIs[0] addr |
| 28559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28560 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28562 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28563 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (AMOCAS_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_AQ_RL), |
| 28565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28566 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28567 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28568 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28570 | GIR_RootConstrainSelectedInstOperands, |
| 28571 | // GIR_Coverage, 901, |
| 28572 | GIR_EraseRootFromParent_Done, |
| 28573 | // Label 2052: @72786 |
| 28574 | GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(72841), // Rule ID 903 // |
| 28575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28576 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28577 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28579 | // MIs[0] addr |
| 28580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28582 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28583 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28584 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (AMOCAS_W:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 28586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28587 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28588 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28589 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28590 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28591 | GIR_RootConstrainSelectedInstOperands, |
| 28592 | // GIR_Coverage, 903, |
| 28593 | GIR_EraseRootFromParent_Done, |
| 28594 | // Label 2053: @72841 |
| 28595 | GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(72896), // Rule ID 905 // |
| 28596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28597 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28598 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28600 | // MIs[0] addr |
| 28601 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28602 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28603 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28604 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28605 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (AMOCAS_W:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 28607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28608 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28609 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28610 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28611 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28612 | GIR_RootConstrainSelectedInstOperands, |
| 28613 | // GIR_Coverage, 905, |
| 28614 | GIR_EraseRootFromParent_Done, |
| 28615 | // Label 2054: @72896 |
| 28616 | GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(72951), // Rule ID 907 // |
| 28617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28618 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28619 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28621 | // MIs[0] addr |
| 28622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28624 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28625 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28626 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (AMOCAS_W:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 28628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28629 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28630 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28631 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28632 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28633 | GIR_RootConstrainSelectedInstOperands, |
| 28634 | // GIR_Coverage, 907, |
| 28635 | GIR_EraseRootFromParent_Done, |
| 28636 | // Label 2055: @72951 |
| 28637 | GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(73006), // Rule ID 909 // |
| 28638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28639 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28640 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28642 | // MIs[0] addr |
| 28643 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28644 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28646 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28647 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (AMOCAS_W:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 28649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28650 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28651 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28652 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28653 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28654 | GIR_RootConstrainSelectedInstOperands, |
| 28655 | // GIR_Coverage, 909, |
| 28656 | GIR_EraseRootFromParent_Done, |
| 28657 | // Label 2056: @73006 |
| 28658 | GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(73061), // Rule ID 911 // |
| 28659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28660 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 28661 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28663 | // MIs[0] addr |
| 28664 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28665 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28666 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28667 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28668 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (AMOCAS_W:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 28670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28671 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28672 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28673 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28675 | GIR_RootConstrainSelectedInstOperands, |
| 28676 | // GIR_Coverage, 911, |
| 28677 | GIR_EraseRootFromParent_Done, |
| 28678 | // Label 2057: @73061 |
| 28679 | GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(73116), // Rule ID 1283 // |
| 28680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28681 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28682 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28684 | // MIs[0] addr |
| 28685 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28688 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28689 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>> => (AMOCAS_B:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 28691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28692 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28693 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28694 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28696 | GIR_RootConstrainSelectedInstOperands, |
| 28697 | // GIR_Coverage, 1283, |
| 28698 | GIR_EraseRootFromParent_Done, |
| 28699 | // Label 2058: @73116 |
| 28700 | GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(73171), // Rule ID 1285 // |
| 28701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28702 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28703 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28705 | // MIs[0] addr |
| 28706 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28708 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28709 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28710 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>> => (AMOCAS_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_AQ), |
| 28712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28713 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28714 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28715 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28717 | GIR_RootConstrainSelectedInstOperands, |
| 28718 | // GIR_Coverage, 1285, |
| 28719 | GIR_EraseRootFromParent_Done, |
| 28720 | // Label 2059: @73171 |
| 28721 | GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(73226), // Rule ID 1287 // |
| 28722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28723 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28724 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28726 | // MIs[0] addr |
| 28727 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28730 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28731 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>> => (AMOCAS_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_RL), |
| 28733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28734 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28735 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28736 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28737 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28738 | GIR_RootConstrainSelectedInstOperands, |
| 28739 | // GIR_Coverage, 1287, |
| 28740 | GIR_EraseRootFromParent_Done, |
| 28741 | // Label 2060: @73226 |
| 28742 | GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(73281), // Rule ID 1289 // |
| 28743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28744 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28745 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28747 | // MIs[0] addr |
| 28748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28750 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28751 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28752 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>> => (AMOCAS_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_AQ_RL), |
| 28754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28755 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28756 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28757 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28758 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28759 | GIR_RootConstrainSelectedInstOperands, |
| 28760 | // GIR_Coverage, 1289, |
| 28761 | GIR_EraseRootFromParent_Done, |
| 28762 | // Label 2061: @73281 |
| 28763 | GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(73336), // Rule ID 1291 // |
| 28764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28765 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28766 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28768 | // MIs[0] addr |
| 28769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28771 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28772 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28773 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>> => (AMOCAS_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_AQ_RL), |
| 28775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28776 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28777 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28778 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28780 | GIR_RootConstrainSelectedInstOperands, |
| 28781 | // GIR_Coverage, 1291, |
| 28782 | GIR_EraseRootFromParent_Done, |
| 28783 | // Label 2062: @73336 |
| 28784 | GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(73391), // Rule ID 1293 // |
| 28785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28786 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28787 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28789 | // MIs[0] addr |
| 28790 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28791 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28792 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28793 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28794 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>> => (AMOCAS_B:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 28796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28797 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28798 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28799 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28801 | GIR_RootConstrainSelectedInstOperands, |
| 28802 | // GIR_Coverage, 1293, |
| 28803 | GIR_EraseRootFromParent_Done, |
| 28804 | // Label 2063: @73391 |
| 28805 | GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(73446), // Rule ID 1295 // |
| 28806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28807 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28808 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28810 | // MIs[0] addr |
| 28811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28812 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28813 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28814 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28815 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>> => (AMOCAS_B:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 28817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28818 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28819 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28820 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28821 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28822 | GIR_RootConstrainSelectedInstOperands, |
| 28823 | // GIR_Coverage, 1295, |
| 28824 | GIR_EraseRootFromParent_Done, |
| 28825 | // Label 2064: @73446 |
| 28826 | GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(73501), // Rule ID 1297 // |
| 28827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28828 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28829 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28831 | // MIs[0] addr |
| 28832 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28834 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28835 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28836 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>> => (AMOCAS_B:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 28838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28839 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28840 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28841 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28842 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28843 | GIR_RootConstrainSelectedInstOperands, |
| 28844 | // GIR_Coverage, 1297, |
| 28845 | GIR_EraseRootFromParent_Done, |
| 28846 | // Label 2065: @73501 |
| 28847 | GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(73556), // Rule ID 1299 // |
| 28848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28849 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28850 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28852 | // MIs[0] addr |
| 28853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28854 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28855 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28856 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28857 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>> => (AMOCAS_B:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 28859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28860 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28861 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28862 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28864 | GIR_RootConstrainSelectedInstOperands, |
| 28865 | // GIR_Coverage, 1299, |
| 28866 | GIR_EraseRootFromParent_Done, |
| 28867 | // Label 2066: @73556 |
| 28868 | GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(73611), // Rule ID 1301 // |
| 28869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28870 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 28871 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28873 | // MIs[0] addr |
| 28874 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28875 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28876 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28877 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28878 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>> => (AMOCAS_B:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 28880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28881 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28882 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28883 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28884 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28885 | GIR_RootConstrainSelectedInstOperands, |
| 28886 | // GIR_Coverage, 1301, |
| 28887 | GIR_EraseRootFromParent_Done, |
| 28888 | // Label 2067: @73611 |
| 28889 | GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(73666), // Rule ID 1303 // |
| 28890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28891 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 28892 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28894 | // MIs[0] addr |
| 28895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28896 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28897 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28898 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28899 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>> => (AMOCAS_H:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 28901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28902 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28903 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28904 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28905 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28906 | GIR_RootConstrainSelectedInstOperands, |
| 28907 | // GIR_Coverage, 1303, |
| 28908 | GIR_EraseRootFromParent_Done, |
| 28909 | // Label 2068: @73666 |
| 28910 | GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(73721), // Rule ID 1305 // |
| 28911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28912 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 28913 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 28914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28915 | // MIs[0] addr |
| 28916 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28917 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28918 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28919 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28920 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>> => (AMOCAS_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_AQ), |
| 28922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28923 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28924 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28925 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28927 | GIR_RootConstrainSelectedInstOperands, |
| 28928 | // GIR_Coverage, 1305, |
| 28929 | GIR_EraseRootFromParent_Done, |
| 28930 | // Label 2069: @73721 |
| 28931 | GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(73776), // Rule ID 1307 // |
| 28932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28933 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 28934 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 28935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28936 | // MIs[0] addr |
| 28937 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28938 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28940 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28941 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>> => (AMOCAS_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_RL), |
| 28943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28944 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28945 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28946 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28948 | GIR_RootConstrainSelectedInstOperands, |
| 28949 | // GIR_Coverage, 1307, |
| 28950 | GIR_EraseRootFromParent_Done, |
| 28951 | // Label 2070: @73776 |
| 28952 | GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(73831), // Rule ID 1309 // |
| 28953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28954 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 28955 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 28956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28957 | // MIs[0] addr |
| 28958 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28960 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28961 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28962 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>> => (AMOCAS_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_AQ_RL), |
| 28964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28965 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28966 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28967 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28968 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28969 | GIR_RootConstrainSelectedInstOperands, |
| 28970 | // GIR_Coverage, 1309, |
| 28971 | GIR_EraseRootFromParent_Done, |
| 28972 | // Label 2071: @73831 |
| 28973 | GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(73886), // Rule ID 1311 // |
| 28974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1), |
| 28975 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 28976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 28977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28978 | // MIs[0] addr |
| 28979 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 28980 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28982 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28983 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>> => (AMOCAS_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 28984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_AQ_RL), |
| 28985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 28986 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 28987 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 28988 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 28989 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28990 | GIR_RootConstrainSelectedInstOperands, |
| 28991 | // GIR_Coverage, 1311, |
| 28992 | GIR_EraseRootFromParent_Done, |
| 28993 | // Label 2072: @73886 |
| 28994 | GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(73941), // Rule ID 1313 // |
| 28995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 28996 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 28997 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 28998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 28999 | // MIs[0] addr |
| 29000 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29002 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29003 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29004 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>> => (AMOCAS_H:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 29005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29007 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29008 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29009 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29011 | GIR_RootConstrainSelectedInstOperands, |
| 29012 | // GIR_Coverage, 1313, |
| 29013 | GIR_EraseRootFromParent_Done, |
| 29014 | // Label 2073: @73941 |
| 29015 | GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(73996), // Rule ID 1315 // |
| 29016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 29017 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29018 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29020 | // MIs[0] addr |
| 29021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29025 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>> => (AMOCAS_H:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 29026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29028 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29029 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29030 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29032 | GIR_RootConstrainSelectedInstOperands, |
| 29033 | // GIR_Coverage, 1315, |
| 29034 | GIR_EraseRootFromParent_Done, |
| 29035 | // Label 2074: @73996 |
| 29036 | GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(74051), // Rule ID 1317 // |
| 29037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 29038 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29039 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29041 | // MIs[0] addr |
| 29042 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29043 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29044 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29045 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29046 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>> => (AMOCAS_H:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 29047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29049 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29050 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29051 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29053 | GIR_RootConstrainSelectedInstOperands, |
| 29054 | // GIR_Coverage, 1317, |
| 29055 | GIR_EraseRootFromParent_Done, |
| 29056 | // Label 2075: @74051 |
| 29057 | GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(74106), // Rule ID 1319 // |
| 29058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 29059 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29060 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29062 | // MIs[0] addr |
| 29063 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29064 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29066 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29067 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>> => (AMOCAS_H:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 29068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29070 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29071 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29072 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29073 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29074 | GIR_RootConstrainSelectedInstOperands, |
| 29075 | // GIR_Coverage, 1319, |
| 29076 | GIR_EraseRootFromParent_Done, |
| 29077 | // Label 2076: @74106 |
| 29078 | GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(74161), // Rule ID 1321 // |
| 29079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1), |
| 29080 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29081 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29083 | // MIs[0] addr |
| 29084 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29085 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29086 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29087 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29088 | // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>> => (AMOCAS_H:{ *:[i32] } GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$new) |
| 29089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29091 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29092 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29093 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29094 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29095 | GIR_RootConstrainSelectedInstOperands, |
| 29096 | // GIR_Coverage, 1321, |
| 29097 | GIR_EraseRootFromParent_Done, |
| 29098 | // Label 2077: @74161 |
| 29099 | GIM_Reject, |
| 29100 | // Label 2037: @74162 |
| 29101 | GIM_Reject, |
| 29102 | // Label 2035: @74163 |
| 29103 | GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(76375), |
| 29104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 29105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 29106 | GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(74229), // Rule ID 892 // |
| 29107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29108 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29109 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29111 | // MIs[0] addr |
| 29112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29114 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29115 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29116 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (AMOCAS_W:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 29118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29119 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29120 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29121 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29123 | GIR_RootConstrainSelectedInstOperands, |
| 29124 | // GIR_Coverage, 892, |
| 29125 | GIR_EraseRootFromParent_Done, |
| 29126 | // Label 2079: @74229 |
| 29127 | GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(74284), // Rule ID 894 // |
| 29128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29129 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29130 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29132 | // MIs[0] addr |
| 29133 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29134 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29135 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29136 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29137 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (AMOCAS_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_AQ), |
| 29139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29140 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29141 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29142 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29143 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29144 | GIR_RootConstrainSelectedInstOperands, |
| 29145 | // GIR_Coverage, 894, |
| 29146 | GIR_EraseRootFromParent_Done, |
| 29147 | // Label 2080: @74284 |
| 29148 | GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(74339), // Rule ID 896 // |
| 29149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29150 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29151 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29153 | // MIs[0] addr |
| 29154 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29155 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29156 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29157 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29158 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (AMOCAS_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_RL), |
| 29160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29161 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29162 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29163 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29165 | GIR_RootConstrainSelectedInstOperands, |
| 29166 | // GIR_Coverage, 896, |
| 29167 | GIR_EraseRootFromParent_Done, |
| 29168 | // Label 2081: @74339 |
| 29169 | GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(74394), // Rule ID 898 // |
| 29170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29171 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29172 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29174 | // MIs[0] addr |
| 29175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29176 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29177 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29178 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29179 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (AMOCAS_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_AQ_RL), |
| 29181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29182 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29183 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29184 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29185 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29186 | GIR_RootConstrainSelectedInstOperands, |
| 29187 | // GIR_Coverage, 898, |
| 29188 | GIR_EraseRootFromParent_Done, |
| 29189 | // Label 2082: @74394 |
| 29190 | GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(74449), // Rule ID 900 // |
| 29191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29192 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29193 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29195 | // MIs[0] addr |
| 29196 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29198 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29199 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29200 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (AMOCAS_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W_AQ_RL), |
| 29202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29203 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29204 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29205 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29207 | GIR_RootConstrainSelectedInstOperands, |
| 29208 | // GIR_Coverage, 900, |
| 29209 | GIR_EraseRootFromParent_Done, |
| 29210 | // Label 2083: @74449 |
| 29211 | GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(74504), // Rule ID 902 // |
| 29212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29213 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29214 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29216 | // MIs[0] addr |
| 29217 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29218 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29220 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29221 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (AMOCAS_W:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 29223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29224 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29225 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29226 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29228 | GIR_RootConstrainSelectedInstOperands, |
| 29229 | // GIR_Coverage, 902, |
| 29230 | GIR_EraseRootFromParent_Done, |
| 29231 | // Label 2084: @74504 |
| 29232 | GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(74559), // Rule ID 904 // |
| 29233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29234 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29237 | // MIs[0] addr |
| 29238 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29241 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29242 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (AMOCAS_W:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 29244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29245 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29246 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29247 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29249 | GIR_RootConstrainSelectedInstOperands, |
| 29250 | // GIR_Coverage, 904, |
| 29251 | GIR_EraseRootFromParent_Done, |
| 29252 | // Label 2085: @74559 |
| 29253 | GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(74614), // Rule ID 906 // |
| 29254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29255 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29256 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29257 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29258 | // MIs[0] addr |
| 29259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29261 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29262 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29263 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (AMOCAS_W:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 29265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29266 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29267 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29268 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29269 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29270 | GIR_RootConstrainSelectedInstOperands, |
| 29271 | // GIR_Coverage, 906, |
| 29272 | GIR_EraseRootFromParent_Done, |
| 29273 | // Label 2086: @74614 |
| 29274 | GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(74669), // Rule ID 908 // |
| 29275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29276 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29277 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29279 | // MIs[0] addr |
| 29280 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29281 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29282 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29283 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29284 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (AMOCAS_W:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 29286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29287 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29288 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29289 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29291 | GIR_RootConstrainSelectedInstOperands, |
| 29292 | // GIR_Coverage, 908, |
| 29293 | GIR_EraseRootFromParent_Done, |
| 29294 | // Label 2087: @74669 |
| 29295 | GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(74724), // Rule ID 910 // |
| 29296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29297 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29298 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29300 | // MIs[0] addr |
| 29301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29303 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29304 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29305 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (AMOCAS_W:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_W), |
| 29307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29308 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29309 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29310 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29311 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29312 | GIR_RootConstrainSelectedInstOperands, |
| 29313 | // GIR_Coverage, 910, |
| 29314 | GIR_EraseRootFromParent_Done, |
| 29315 | // Label 2088: @74724 |
| 29316 | GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(74779), // Rule ID 912 // |
| 29317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0), |
| 29318 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29319 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29321 | // MIs[0] addr |
| 29322 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29323 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29324 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29325 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29326 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_monotonic>> => (AMOCAS_D_RV64:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64), |
| 29328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29329 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29330 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29331 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29332 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29333 | GIR_RootConstrainSelectedInstOperands, |
| 29334 | // GIR_Coverage, 912, |
| 29335 | GIR_EraseRootFromParent_Done, |
| 29336 | // Label 2089: @74779 |
| 29337 | GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(74834), // Rule ID 913 // |
| 29338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0), |
| 29339 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29340 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29342 | // MIs[0] addr |
| 29343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29344 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29346 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29347 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acquire>> => (AMOCAS_D_RV64_AQ:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64_AQ), |
| 29349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29350 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29351 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29352 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29354 | GIR_RootConstrainSelectedInstOperands, |
| 29355 | // GIR_Coverage, 913, |
| 29356 | GIR_EraseRootFromParent_Done, |
| 29357 | // Label 2090: @74834 |
| 29358 | GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(74889), // Rule ID 914 // |
| 29359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0), |
| 29360 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29361 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29363 | // MIs[0] addr |
| 29364 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29365 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29366 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29367 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29368 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_release>> => (AMOCAS_D_RV64_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64_RL), |
| 29370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29371 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29372 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29373 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29374 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29375 | GIR_RootConstrainSelectedInstOperands, |
| 29376 | // GIR_Coverage, 914, |
| 29377 | GIR_EraseRootFromParent_Done, |
| 29378 | // Label 2091: @74889 |
| 29379 | GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(74944), // Rule ID 915 // |
| 29380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0), |
| 29381 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29382 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29384 | // MIs[0] addr |
| 29385 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29386 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29387 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29388 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29389 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acq_rel>> => (AMOCAS_D_RV64_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64_AQ_RL), |
| 29391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29392 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29393 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29394 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29395 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29396 | GIR_RootConstrainSelectedInstOperands, |
| 29397 | // GIR_Coverage, 915, |
| 29398 | GIR_EraseRootFromParent_Done, |
| 29399 | // Label 2092: @74944 |
| 29400 | GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(74999), // Rule ID 916 // |
| 29401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0), |
| 29402 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29403 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29405 | // MIs[0] addr |
| 29406 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29407 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29408 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29409 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29410 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_seq_cst>> => (AMOCAS_D_RV64_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64_AQ_RL), |
| 29412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29413 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29414 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29415 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29417 | GIR_RootConstrainSelectedInstOperands, |
| 29418 | // GIR_Coverage, 916, |
| 29419 | GIR_EraseRootFromParent_Done, |
| 29420 | // Label 2093: @74999 |
| 29421 | GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(75054), // Rule ID 917 // |
| 29422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0), |
| 29423 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29424 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29426 | // MIs[0] addr |
| 29427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29430 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29431 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_monotonic>> => (AMOCAS_D_RV64:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64), |
| 29433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29434 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29435 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29436 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29437 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29438 | GIR_RootConstrainSelectedInstOperands, |
| 29439 | // GIR_Coverage, 917, |
| 29440 | GIR_EraseRootFromParent_Done, |
| 29441 | // Label 2094: @75054 |
| 29442 | GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(75109), // Rule ID 918 // |
| 29443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0), |
| 29444 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29445 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29447 | // MIs[0] addr |
| 29448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29450 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29451 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29452 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acquire>> => (AMOCAS_D_RV64:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64), |
| 29454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29455 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29456 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29457 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29458 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29459 | GIR_RootConstrainSelectedInstOperands, |
| 29460 | // GIR_Coverage, 918, |
| 29461 | GIR_EraseRootFromParent_Done, |
| 29462 | // Label 2095: @75109 |
| 29463 | GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(75164), // Rule ID 919 // |
| 29464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0), |
| 29465 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29466 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29468 | // MIs[0] addr |
| 29469 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29471 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29472 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29473 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_release>> => (AMOCAS_D_RV64:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64), |
| 29475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29476 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29477 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29478 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29479 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29480 | GIR_RootConstrainSelectedInstOperands, |
| 29481 | // GIR_Coverage, 919, |
| 29482 | GIR_EraseRootFromParent_Done, |
| 29483 | // Label 2096: @75164 |
| 29484 | GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(75219), // Rule ID 920 // |
| 29485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0), |
| 29486 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29487 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29489 | // MIs[0] addr |
| 29490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29491 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29492 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29493 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29494 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acq_rel>> => (AMOCAS_D_RV64:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64), |
| 29496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29497 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29498 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29499 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29501 | GIR_RootConstrainSelectedInstOperands, |
| 29502 | // GIR_Coverage, 920, |
| 29503 | GIR_EraseRootFromParent_Done, |
| 29504 | // Label 2097: @75219 |
| 29505 | GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(75274), // Rule ID 921 // |
| 29506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0), |
| 29507 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 29508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29510 | // MIs[0] addr |
| 29511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29512 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29513 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29514 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29515 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_seq_cst>> => (AMOCAS_D_RV64:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_D_RV64), |
| 29517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29518 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29519 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29520 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29522 | GIR_RootConstrainSelectedInstOperands, |
| 29523 | // GIR_Coverage, 921, |
| 29524 | GIR_EraseRootFromParent_Done, |
| 29525 | // Label 2098: @75274 |
| 29526 | GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(75329), // Rule ID 1282 // |
| 29527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29528 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29529 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29531 | // MIs[0] addr |
| 29532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29534 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29535 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29536 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>> => (AMOCAS_B:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 29538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29539 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29540 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29541 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29542 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29543 | GIR_RootConstrainSelectedInstOperands, |
| 29544 | // GIR_Coverage, 1282, |
| 29545 | GIR_EraseRootFromParent_Done, |
| 29546 | // Label 2099: @75329 |
| 29547 | GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(75384), // Rule ID 1284 // |
| 29548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29549 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29550 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29552 | // MIs[0] addr |
| 29553 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29554 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29555 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29556 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29557 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>> => (AMOCAS_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_AQ), |
| 29559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29560 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29561 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29562 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29563 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29564 | GIR_RootConstrainSelectedInstOperands, |
| 29565 | // GIR_Coverage, 1284, |
| 29566 | GIR_EraseRootFromParent_Done, |
| 29567 | // Label 2100: @75384 |
| 29568 | GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(75439), // Rule ID 1286 // |
| 29569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29570 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29571 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29573 | // MIs[0] addr |
| 29574 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29575 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29576 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29577 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29578 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>> => (AMOCAS_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_RL), |
| 29580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29581 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29582 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29583 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29584 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29585 | GIR_RootConstrainSelectedInstOperands, |
| 29586 | // GIR_Coverage, 1286, |
| 29587 | GIR_EraseRootFromParent_Done, |
| 29588 | // Label 2101: @75439 |
| 29589 | GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(75494), // Rule ID 1288 // |
| 29590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29591 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29592 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29594 | // MIs[0] addr |
| 29595 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29596 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29597 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29598 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29599 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>> => (AMOCAS_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_AQ_RL), |
| 29601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29602 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29603 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29604 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29605 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29606 | GIR_RootConstrainSelectedInstOperands, |
| 29607 | // GIR_Coverage, 1288, |
| 29608 | GIR_EraseRootFromParent_Done, |
| 29609 | // Label 2102: @75494 |
| 29610 | GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(75549), // Rule ID 1290 // |
| 29611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29612 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29613 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29615 | // MIs[0] addr |
| 29616 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29617 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29618 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29619 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29620 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>> => (AMOCAS_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B_AQ_RL), |
| 29622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29623 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29624 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29625 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29627 | GIR_RootConstrainSelectedInstOperands, |
| 29628 | // GIR_Coverage, 1290, |
| 29629 | GIR_EraseRootFromParent_Done, |
| 29630 | // Label 2103: @75549 |
| 29631 | GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(75604), // Rule ID 1292 // |
| 29632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29633 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29634 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29636 | // MIs[0] addr |
| 29637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29638 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29639 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29640 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29641 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>> => (AMOCAS_B:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 29643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29644 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29645 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29646 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29648 | GIR_RootConstrainSelectedInstOperands, |
| 29649 | // GIR_Coverage, 1292, |
| 29650 | GIR_EraseRootFromParent_Done, |
| 29651 | // Label 2104: @75604 |
| 29652 | GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(75659), // Rule ID 1294 // |
| 29653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29654 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29655 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29657 | // MIs[0] addr |
| 29658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29660 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29661 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29662 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>> => (AMOCAS_B:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 29664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29665 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29666 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29667 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29669 | GIR_RootConstrainSelectedInstOperands, |
| 29670 | // GIR_Coverage, 1294, |
| 29671 | GIR_EraseRootFromParent_Done, |
| 29672 | // Label 2105: @75659 |
| 29673 | GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(75714), // Rule ID 1296 // |
| 29674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29675 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29676 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29678 | // MIs[0] addr |
| 29679 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29682 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29683 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>> => (AMOCAS_B:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 29685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29686 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29687 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29688 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29689 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29690 | GIR_RootConstrainSelectedInstOperands, |
| 29691 | // GIR_Coverage, 1296, |
| 29692 | GIR_EraseRootFromParent_Done, |
| 29693 | // Label 2106: @75714 |
| 29694 | GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(75769), // Rule ID 1298 // |
| 29695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29696 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29697 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29699 | // MIs[0] addr |
| 29700 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29701 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29702 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29703 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29704 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>> => (AMOCAS_B:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 29706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29707 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29708 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29709 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29710 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29711 | GIR_RootConstrainSelectedInstOperands, |
| 29712 | // GIR_Coverage, 1298, |
| 29713 | GIR_EraseRootFromParent_Done, |
| 29714 | // Label 2107: @75769 |
| 29715 | GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(75824), // Rule ID 1300 // |
| 29716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29717 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 29718 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29720 | // MIs[0] addr |
| 29721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29722 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29724 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29725 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>> => (AMOCAS_B:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_B), |
| 29727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29728 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29729 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29730 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29731 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29732 | GIR_RootConstrainSelectedInstOperands, |
| 29733 | // GIR_Coverage, 1300, |
| 29734 | GIR_EraseRootFromParent_Done, |
| 29735 | // Label 2108: @75824 |
| 29736 | GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(75879), // Rule ID 1302 // |
| 29737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29738 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29739 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29741 | // MIs[0] addr |
| 29742 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29743 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29744 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29745 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29746 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>> => (AMOCAS_H:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29749 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29750 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29751 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29752 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29753 | GIR_RootConstrainSelectedInstOperands, |
| 29754 | // GIR_Coverage, 1302, |
| 29755 | GIR_EraseRootFromParent_Done, |
| 29756 | // Label 2109: @75879 |
| 29757 | GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(75934), // Rule ID 1304 // |
| 29758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29759 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29760 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29762 | // MIs[0] addr |
| 29763 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29764 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29765 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29766 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29767 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>> => (AMOCAS_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_AQ), |
| 29769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29770 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29771 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29772 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29774 | GIR_RootConstrainSelectedInstOperands, |
| 29775 | // GIR_Coverage, 1304, |
| 29776 | GIR_EraseRootFromParent_Done, |
| 29777 | // Label 2110: @75934 |
| 29778 | GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(75989), // Rule ID 1306 // |
| 29779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29780 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29781 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29783 | // MIs[0] addr |
| 29784 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29785 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29786 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29787 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29788 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>> => (AMOCAS_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_RL), |
| 29790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29791 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29792 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29793 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29794 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29795 | GIR_RootConstrainSelectedInstOperands, |
| 29796 | // GIR_Coverage, 1306, |
| 29797 | GIR_EraseRootFromParent_Done, |
| 29798 | // Label 2111: @75989 |
| 29799 | GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(76044), // Rule ID 1308 // |
| 29800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29801 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29802 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29804 | // MIs[0] addr |
| 29805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29806 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29807 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29808 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29809 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>> => (AMOCAS_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_AQ_RL), |
| 29811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29812 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29813 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29814 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29815 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29816 | GIR_RootConstrainSelectedInstOperands, |
| 29817 | // GIR_Coverage, 1308, |
| 29818 | GIR_EraseRootFromParent_Done, |
| 29819 | // Label 2112: @76044 |
| 29820 | GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(76099), // Rule ID 1310 // |
| 29821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0), |
| 29822 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29823 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29825 | // MIs[0] addr |
| 29826 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29828 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29829 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29830 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>> => (AMOCAS_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H_AQ_RL), |
| 29832 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29833 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29834 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29835 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29837 | GIR_RootConstrainSelectedInstOperands, |
| 29838 | // GIR_Coverage, 1310, |
| 29839 | GIR_EraseRootFromParent_Done, |
| 29840 | // Label 2113: @76099 |
| 29841 | GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(76154), // Rule ID 1312 // |
| 29842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29843 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29844 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29846 | // MIs[0] addr |
| 29847 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29849 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29850 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29851 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>> => (AMOCAS_H:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29854 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29855 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29856 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29857 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29858 | GIR_RootConstrainSelectedInstOperands, |
| 29859 | // GIR_Coverage, 1312, |
| 29860 | GIR_EraseRootFromParent_Done, |
| 29861 | // Label 2114: @76154 |
| 29862 | GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(76209), // Rule ID 1314 // |
| 29863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29864 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29865 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29867 | // MIs[0] addr |
| 29868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29870 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29871 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29872 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>> => (AMOCAS_H:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29875 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29876 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29877 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29878 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29879 | GIR_RootConstrainSelectedInstOperands, |
| 29880 | // GIR_Coverage, 1314, |
| 29881 | GIR_EraseRootFromParent_Done, |
| 29882 | // Label 2115: @76209 |
| 29883 | GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(76264), // Rule ID 1316 // |
| 29884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29885 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29886 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29888 | // MIs[0] addr |
| 29889 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29890 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29891 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29892 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29893 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>> => (AMOCAS_H:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29896 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29897 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29898 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29899 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29900 | GIR_RootConstrainSelectedInstOperands, |
| 29901 | // GIR_Coverage, 1316, |
| 29902 | GIR_EraseRootFromParent_Done, |
| 29903 | // Label 2116: @76264 |
| 29904 | GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(76319), // Rule ID 1318 // |
| 29905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29906 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29907 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 29908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29909 | // MIs[0] addr |
| 29910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29911 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29913 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29914 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>> => (AMOCAS_H:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29917 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29918 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29919 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29921 | GIR_RootConstrainSelectedInstOperands, |
| 29922 | // GIR_Coverage, 1318, |
| 29923 | GIR_EraseRootFromParent_Done, |
| 29924 | // Label 2117: @76319 |
| 29925 | GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(76374), // Rule ID 1320 // |
| 29926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0), |
| 29927 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 29928 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 29929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29930 | // MIs[0] addr |
| 29931 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29932 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29933 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29934 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29935 | // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>> => (AMOCAS_H:{ *:[i64] } GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$new) |
| 29936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AMOCAS_H), |
| 29937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 29938 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 29939 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 29940 | GIR_RootToRootCopy, /*OpIdx*/3, // new |
| 29941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29942 | GIR_RootConstrainSelectedInstOperands, |
| 29943 | // GIR_Coverage, 1320, |
| 29944 | GIR_EraseRootFromParent_Done, |
| 29945 | // Label 2118: @76374 |
| 29946 | GIM_Reject, |
| 29947 | // Label 2078: @76375 |
| 29948 | GIM_Reject, |
| 29949 | // Label 2036: @76376 |
| 29950 | GIM_Reject, |
| 29951 | // Label 23: @76377 |
| 29952 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2121*/ GIMT_Encode4(80106), |
| 29953 | /*GILLT_s32*//*Label 2119*/ GIMT_Encode4(76396), |
| 29954 | /*GILLT_s64*//*Label 2120*/ GIMT_Encode4(78456), |
| 29955 | // Label 2119: @76396 |
| 29956 | GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(78455), |
| 29957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29958 | GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(76445), // Rule ID 373 // |
| 29959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 29960 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29961 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 29962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29963 | // MIs[0] rs1 |
| 29964 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29965 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29966 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29967 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 29968 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 29969 | GIR_RootConstrainSelectedInstOperands, |
| 29970 | // GIR_Coverage, 373, |
| 29971 | GIR_Done, |
| 29972 | // Label 2123: @76445 |
| 29973 | GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(76486), // Rule ID 375 // |
| 29974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 29975 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 29977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29978 | // MIs[0] rs1 |
| 29979 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29980 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29982 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 29983 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ), |
| 29984 | GIR_RootConstrainSelectedInstOperands, |
| 29985 | // GIR_Coverage, 375, |
| 29986 | GIR_Done, |
| 29987 | // Label 2124: @76486 |
| 29988 | GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(76527), // Rule ID 377 // |
| 29989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 29990 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 29991 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 29992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29993 | // MIs[0] rs1 |
| 29994 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 29995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29996 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 29997 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 29998 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_RL), |
| 29999 | GIR_RootConstrainSelectedInstOperands, |
| 30000 | // GIR_Coverage, 377, |
| 30001 | GIR_Done, |
| 30002 | // Label 2125: @76527 |
| 30003 | GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(76568), // Rule ID 379 // |
| 30004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30005 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30008 | // MIs[0] rs1 |
| 30009 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30010 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30011 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30012 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30013 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30014 | GIR_RootConstrainSelectedInstOperands, |
| 30015 | // GIR_Coverage, 379, |
| 30016 | GIR_Done, |
| 30017 | // Label 2126: @76568 |
| 30018 | GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(76609), // Rule ID 381 // |
| 30019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30020 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30021 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30023 | // MIs[0] rs1 |
| 30024 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30025 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30026 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30027 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30028 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30029 | GIR_RootConstrainSelectedInstOperands, |
| 30030 | // GIR_Coverage, 381, |
| 30031 | GIR_Done, |
| 30032 | // Label 2127: @76609 |
| 30033 | GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(76650), // Rule ID 383 // |
| 30034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30035 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30036 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30038 | // MIs[0] rs1 |
| 30039 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30040 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30041 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30042 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30043 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30044 | GIR_RootConstrainSelectedInstOperands, |
| 30045 | // GIR_Coverage, 383, |
| 30046 | GIR_Done, |
| 30047 | // Label 2128: @76650 |
| 30048 | GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(76691), // Rule ID 385 // |
| 30049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30050 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30051 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30053 | // MIs[0] rs1 |
| 30054 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30055 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30056 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30057 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30058 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30059 | GIR_RootConstrainSelectedInstOperands, |
| 30060 | // GIR_Coverage, 385, |
| 30061 | GIR_Done, |
| 30062 | // Label 2129: @76691 |
| 30063 | GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(76732), // Rule ID 387 // |
| 30064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30065 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30068 | // MIs[0] rs1 |
| 30069 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30071 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30072 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30073 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30074 | GIR_RootConstrainSelectedInstOperands, |
| 30075 | // GIR_Coverage, 387, |
| 30076 | GIR_Done, |
| 30077 | // Label 2130: @76732 |
| 30078 | GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(76773), // Rule ID 389 // |
| 30079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30080 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30081 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30083 | // MIs[0] rs1 |
| 30084 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30085 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30086 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30087 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30088 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30089 | GIR_RootConstrainSelectedInstOperands, |
| 30090 | // GIR_Coverage, 389, |
| 30091 | GIR_Done, |
| 30092 | // Label 2131: @76773 |
| 30093 | GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(76814), // Rule ID 391 // |
| 30094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30095 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30096 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30098 | // MIs[0] rs1 |
| 30099 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30101 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30102 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30103 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30104 | GIR_RootConstrainSelectedInstOperands, |
| 30105 | // GIR_Coverage, 391, |
| 30106 | GIR_Done, |
| 30107 | // Label 2132: @76814 |
| 30108 | GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(76855), // Rule ID 690 // |
| 30109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30110 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30111 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30113 | // MIs[0] rs1 |
| 30114 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30115 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30116 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30117 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30118 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30119 | GIR_RootConstrainSelectedInstOperands, |
| 30120 | // GIR_Coverage, 690, |
| 30121 | GIR_Done, |
| 30122 | // Label 2133: @76855 |
| 30123 | GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(76896), // Rule ID 691 // |
| 30124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30125 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30126 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30128 | // MIs[0] rs1 |
| 30129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30130 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30131 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30132 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30133 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30134 | GIR_RootConstrainSelectedInstOperands, |
| 30135 | // GIR_Coverage, 691, |
| 30136 | GIR_Done, |
| 30137 | // Label 2134: @76896 |
| 30138 | GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(76937), // Rule ID 692 // |
| 30139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30140 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30141 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30143 | // MIs[0] rs1 |
| 30144 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30145 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30146 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30147 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30148 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ), |
| 30149 | GIR_RootConstrainSelectedInstOperands, |
| 30150 | // GIR_Coverage, 692, |
| 30151 | GIR_Done, |
| 30152 | // Label 2135: @76937 |
| 30153 | GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(76978), // Rule ID 693 // |
| 30154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30155 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30156 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30158 | // MIs[0] rs1 |
| 30159 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30160 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30162 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30163 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ), |
| 30164 | GIR_RootConstrainSelectedInstOperands, |
| 30165 | // GIR_Coverage, 693, |
| 30166 | GIR_Done, |
| 30167 | // Label 2136: @76978 |
| 30168 | GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(77019), // Rule ID 694 // |
| 30169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30170 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30171 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30173 | // MIs[0] rs1 |
| 30174 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30175 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30176 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30177 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30178 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_RL), |
| 30179 | GIR_RootConstrainSelectedInstOperands, |
| 30180 | // GIR_Coverage, 694, |
| 30181 | GIR_Done, |
| 30182 | // Label 2137: @77019 |
| 30183 | GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(77060), // Rule ID 695 // |
| 30184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30185 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30186 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30188 | // MIs[0] rs1 |
| 30189 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30190 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30191 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30192 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30193 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_RL), |
| 30194 | GIR_RootConstrainSelectedInstOperands, |
| 30195 | // GIR_Coverage, 695, |
| 30196 | GIR_Done, |
| 30197 | // Label 2138: @77060 |
| 30198 | GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(77101), // Rule ID 696 // |
| 30199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30200 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30201 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30203 | // MIs[0] rs1 |
| 30204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30205 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30206 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30207 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30208 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30209 | GIR_RootConstrainSelectedInstOperands, |
| 30210 | // GIR_Coverage, 696, |
| 30211 | GIR_Done, |
| 30212 | // Label 2139: @77101 |
| 30213 | GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(77142), // Rule ID 697 // |
| 30214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30215 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30216 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30218 | // MIs[0] rs1 |
| 30219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30220 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30221 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30222 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30223 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30224 | GIR_RootConstrainSelectedInstOperands, |
| 30225 | // GIR_Coverage, 697, |
| 30226 | GIR_Done, |
| 30227 | // Label 2140: @77142 |
| 30228 | GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(77183), // Rule ID 698 // |
| 30229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30230 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30231 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30233 | // MIs[0] rs1 |
| 30234 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30235 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30236 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30237 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30238 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30239 | GIR_RootConstrainSelectedInstOperands, |
| 30240 | // GIR_Coverage, 698, |
| 30241 | GIR_Done, |
| 30242 | // Label 2141: @77183 |
| 30243 | GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(77224), // Rule ID 699 // |
| 30244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 30245 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30246 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30248 | // MIs[0] rs1 |
| 30249 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30250 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30251 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30252 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30253 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30254 | GIR_RootConstrainSelectedInstOperands, |
| 30255 | // GIR_Coverage, 699, |
| 30256 | GIR_Done, |
| 30257 | // Label 2142: @77224 |
| 30258 | GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(77265), // Rule ID 700 // |
| 30259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30260 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30261 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30263 | // MIs[0] rs1 |
| 30264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30265 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30266 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30267 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30268 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30269 | GIR_RootConstrainSelectedInstOperands, |
| 30270 | // GIR_Coverage, 700, |
| 30271 | GIR_Done, |
| 30272 | // Label 2143: @77265 |
| 30273 | GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(77306), // Rule ID 701 // |
| 30274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30275 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30276 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30278 | // MIs[0] rs1 |
| 30279 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30280 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30282 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30283 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30284 | GIR_RootConstrainSelectedInstOperands, |
| 30285 | // GIR_Coverage, 701, |
| 30286 | GIR_Done, |
| 30287 | // Label 2144: @77306 |
| 30288 | GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(77347), // Rule ID 702 // |
| 30289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30290 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30291 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30293 | // MIs[0] rs1 |
| 30294 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30295 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30296 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30297 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30298 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30299 | GIR_RootConstrainSelectedInstOperands, |
| 30300 | // GIR_Coverage, 702, |
| 30301 | GIR_Done, |
| 30302 | // Label 2145: @77347 |
| 30303 | GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(77388), // Rule ID 703 // |
| 30304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30305 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30306 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30308 | // MIs[0] rs1 |
| 30309 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30310 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30311 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30312 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30313 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30314 | GIR_RootConstrainSelectedInstOperands, |
| 30315 | // GIR_Coverage, 703, |
| 30316 | GIR_Done, |
| 30317 | // Label 2146: @77388 |
| 30318 | GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(77429), // Rule ID 704 // |
| 30319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30320 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30323 | // MIs[0] rs1 |
| 30324 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30326 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30327 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30328 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30329 | GIR_RootConstrainSelectedInstOperands, |
| 30330 | // GIR_Coverage, 704, |
| 30331 | GIR_Done, |
| 30332 | // Label 2147: @77429 |
| 30333 | GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(77470), // Rule ID 705 // |
| 30334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30335 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30336 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30338 | // MIs[0] rs1 |
| 30339 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30340 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30341 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30342 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30343 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30344 | GIR_RootConstrainSelectedInstOperands, |
| 30345 | // GIR_Coverage, 705, |
| 30346 | GIR_Done, |
| 30347 | // Label 2148: @77470 |
| 30348 | GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(77511), // Rule ID 706 // |
| 30349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30350 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30351 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30353 | // MIs[0] rs1 |
| 30354 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30355 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30356 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30357 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30358 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30359 | GIR_RootConstrainSelectedInstOperands, |
| 30360 | // GIR_Coverage, 706, |
| 30361 | GIR_Done, |
| 30362 | // Label 2149: @77511 |
| 30363 | GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(77552), // Rule ID 707 // |
| 30364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30365 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30366 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30368 | // MIs[0] rs1 |
| 30369 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30370 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30371 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30372 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30373 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30374 | GIR_RootConstrainSelectedInstOperands, |
| 30375 | // GIR_Coverage, 707, |
| 30376 | GIR_Done, |
| 30377 | // Label 2150: @77552 |
| 30378 | GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(77593), // Rule ID 708 // |
| 30379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30380 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30381 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30383 | // MIs[0] rs1 |
| 30384 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30385 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30386 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30387 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30388 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30389 | GIR_RootConstrainSelectedInstOperands, |
| 30390 | // GIR_Coverage, 708, |
| 30391 | GIR_Done, |
| 30392 | // Label 2151: @77593 |
| 30393 | GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(77634), // Rule ID 709 // |
| 30394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 30395 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30396 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30398 | // MIs[0] rs1 |
| 30399 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30400 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30402 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30403 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30404 | GIR_RootConstrainSelectedInstOperands, |
| 30405 | // GIR_Coverage, 709, |
| 30406 | GIR_Done, |
| 30407 | // Label 2152: @77634 |
| 30408 | GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(77675), // Rule ID 923 // |
| 30409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30410 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30411 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30413 | // MIs[0] rs1 |
| 30414 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30415 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30416 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30417 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>> => (AMOSWAP_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 30419 | GIR_RootConstrainSelectedInstOperands, |
| 30420 | // GIR_Coverage, 923, |
| 30421 | GIR_Done, |
| 30422 | // Label 2153: @77675 |
| 30423 | GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(77716), // Rule ID 925 // |
| 30424 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30425 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30426 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30428 | // MIs[0] rs1 |
| 30429 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30430 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30431 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30432 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>> => (AMOSWAP_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30433 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_AQ), |
| 30434 | GIR_RootConstrainSelectedInstOperands, |
| 30435 | // GIR_Coverage, 925, |
| 30436 | GIR_Done, |
| 30437 | // Label 2154: @77716 |
| 30438 | GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(77757), // Rule ID 927 // |
| 30439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30440 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30441 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30443 | // MIs[0] rs1 |
| 30444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30445 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30446 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30447 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>> => (AMOSWAP_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30448 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_RL), |
| 30449 | GIR_RootConstrainSelectedInstOperands, |
| 30450 | // GIR_Coverage, 927, |
| 30451 | GIR_Done, |
| 30452 | // Label 2155: @77757 |
| 30453 | GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(77798), // Rule ID 929 // |
| 30454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30455 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30456 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30458 | // MIs[0] rs1 |
| 30459 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30460 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30462 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>> => (AMOSWAP_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30463 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_AQ_RL), |
| 30464 | GIR_RootConstrainSelectedInstOperands, |
| 30465 | // GIR_Coverage, 929, |
| 30466 | GIR_Done, |
| 30467 | // Label 2156: @77798 |
| 30468 | GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(77839), // Rule ID 931 // |
| 30469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30470 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30471 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30473 | // MIs[0] rs1 |
| 30474 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30475 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30476 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30477 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>> => (AMOSWAP_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30478 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_AQ_RL), |
| 30479 | GIR_RootConstrainSelectedInstOperands, |
| 30480 | // GIR_Coverage, 931, |
| 30481 | GIR_Done, |
| 30482 | // Label 2157: @77839 |
| 30483 | GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(77880), // Rule ID 933 // |
| 30484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30485 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30486 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30488 | // MIs[0] rs1 |
| 30489 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30490 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30491 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30492 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>> => (AMOSWAP_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30493 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 30494 | GIR_RootConstrainSelectedInstOperands, |
| 30495 | // GIR_Coverage, 933, |
| 30496 | GIR_Done, |
| 30497 | // Label 2158: @77880 |
| 30498 | GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(77921), // Rule ID 935 // |
| 30499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30500 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30501 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30503 | // MIs[0] rs1 |
| 30504 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30506 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30507 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>> => (AMOSWAP_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30508 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 30509 | GIR_RootConstrainSelectedInstOperands, |
| 30510 | // GIR_Coverage, 935, |
| 30511 | GIR_Done, |
| 30512 | // Label 2159: @77921 |
| 30513 | GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(77962), // Rule ID 937 // |
| 30514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30515 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30516 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30518 | // MIs[0] rs1 |
| 30519 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30520 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30522 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>> => (AMOSWAP_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30523 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 30524 | GIR_RootConstrainSelectedInstOperands, |
| 30525 | // GIR_Coverage, 937, |
| 30526 | GIR_Done, |
| 30527 | // Label 2160: @77962 |
| 30528 | GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(78003), // Rule ID 939 // |
| 30529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30530 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30531 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30533 | // MIs[0] rs1 |
| 30534 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30535 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30536 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30537 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>> => (AMOSWAP_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30538 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 30539 | GIR_RootConstrainSelectedInstOperands, |
| 30540 | // GIR_Coverage, 939, |
| 30541 | GIR_Done, |
| 30542 | // Label 2161: @78003 |
| 30543 | GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(78044), // Rule ID 941 // |
| 30544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30545 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 30546 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30548 | // MIs[0] rs1 |
| 30549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30550 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30552 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>> => (AMOSWAP_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30553 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 30554 | GIR_RootConstrainSelectedInstOperands, |
| 30555 | // GIR_Coverage, 941, |
| 30556 | GIR_Done, |
| 30557 | // Label 2162: @78044 |
| 30558 | GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(78085), // Rule ID 1103 // |
| 30559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30560 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30561 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30563 | // MIs[0] rs1 |
| 30564 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30566 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30567 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>> => (AMOSWAP_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30568 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 30569 | GIR_RootConstrainSelectedInstOperands, |
| 30570 | // GIR_Coverage, 1103, |
| 30571 | GIR_Done, |
| 30572 | // Label 2163: @78085 |
| 30573 | GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(78126), // Rule ID 1105 // |
| 30574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30575 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30576 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30578 | // MIs[0] rs1 |
| 30579 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30580 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30582 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>> => (AMOSWAP_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30583 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_AQ), |
| 30584 | GIR_RootConstrainSelectedInstOperands, |
| 30585 | // GIR_Coverage, 1105, |
| 30586 | GIR_Done, |
| 30587 | // Label 2164: @78126 |
| 30588 | GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(78167), // Rule ID 1107 // |
| 30589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30590 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30591 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30593 | // MIs[0] rs1 |
| 30594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30596 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30597 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>> => (AMOSWAP_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30598 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_RL), |
| 30599 | GIR_RootConstrainSelectedInstOperands, |
| 30600 | // GIR_Coverage, 1107, |
| 30601 | GIR_Done, |
| 30602 | // Label 2165: @78167 |
| 30603 | GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(78208), // Rule ID 1109 // |
| 30604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30605 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30606 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30608 | // MIs[0] rs1 |
| 30609 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30610 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30611 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30612 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>> => (AMOSWAP_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30613 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_AQ_RL), |
| 30614 | GIR_RootConstrainSelectedInstOperands, |
| 30615 | // GIR_Coverage, 1109, |
| 30616 | GIR_Done, |
| 30617 | // Label 2166: @78208 |
| 30618 | GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(78249), // Rule ID 1111 // |
| 30619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 30620 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30621 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30623 | // MIs[0] rs1 |
| 30624 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30626 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30627 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>> => (AMOSWAP_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30628 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_AQ_RL), |
| 30629 | GIR_RootConstrainSelectedInstOperands, |
| 30630 | // GIR_Coverage, 1111, |
| 30631 | GIR_Done, |
| 30632 | // Label 2167: @78249 |
| 30633 | GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(78290), // Rule ID 1113 // |
| 30634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30635 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30636 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30638 | // MIs[0] rs1 |
| 30639 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30640 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30642 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>> => (AMOSWAP_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30643 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 30644 | GIR_RootConstrainSelectedInstOperands, |
| 30645 | // GIR_Coverage, 1113, |
| 30646 | GIR_Done, |
| 30647 | // Label 2168: @78290 |
| 30648 | GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(78331), // Rule ID 1115 // |
| 30649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30650 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30651 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30653 | // MIs[0] rs1 |
| 30654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30655 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30657 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>> => (AMOSWAP_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30658 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 30659 | GIR_RootConstrainSelectedInstOperands, |
| 30660 | // GIR_Coverage, 1115, |
| 30661 | GIR_Done, |
| 30662 | // Label 2169: @78331 |
| 30663 | GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(78372), // Rule ID 1117 // |
| 30664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30665 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30666 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30668 | // MIs[0] rs1 |
| 30669 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30670 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30671 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30672 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>> => (AMOSWAP_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30673 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 30674 | GIR_RootConstrainSelectedInstOperands, |
| 30675 | // GIR_Coverage, 1117, |
| 30676 | GIR_Done, |
| 30677 | // Label 2170: @78372 |
| 30678 | GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(78413), // Rule ID 1119 // |
| 30679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30680 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30681 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30683 | // MIs[0] rs1 |
| 30684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30686 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30687 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>> => (AMOSWAP_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30688 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 30689 | GIR_RootConstrainSelectedInstOperands, |
| 30690 | // GIR_Coverage, 1119, |
| 30691 | GIR_Done, |
| 30692 | // Label 2171: @78413 |
| 30693 | GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(78454), // Rule ID 1121 // |
| 30694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 30695 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 30696 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30698 | // MIs[0] rs1 |
| 30699 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 30700 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30702 | // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>> => (AMOSWAP_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 30703 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 30704 | GIR_RootConstrainSelectedInstOperands, |
| 30705 | // GIR_Coverage, 1121, |
| 30706 | GIR_Done, |
| 30707 | // Label 2172: @78454 |
| 30708 | GIM_Reject, |
| 30709 | // Label 2122: @78455 |
| 30710 | GIM_Reject, |
| 30711 | // Label 2120: @78456 |
| 30712 | GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(80105), |
| 30713 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 30714 | GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(78505), // Rule ID 372 // |
| 30715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30716 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30717 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30719 | // MIs[0] rs1 |
| 30720 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30721 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30722 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30723 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30724 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30725 | GIR_RootConstrainSelectedInstOperands, |
| 30726 | // GIR_Coverage, 372, |
| 30727 | GIR_Done, |
| 30728 | // Label 2174: @78505 |
| 30729 | GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(78546), // Rule ID 374 // |
| 30730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30731 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30734 | // MIs[0] rs1 |
| 30735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30738 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30739 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ), |
| 30740 | GIR_RootConstrainSelectedInstOperands, |
| 30741 | // GIR_Coverage, 374, |
| 30742 | GIR_Done, |
| 30743 | // Label 2175: @78546 |
| 30744 | GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(78587), // Rule ID 376 // |
| 30745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30746 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30749 | // MIs[0] rs1 |
| 30750 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30752 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30753 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30754 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_RL), |
| 30755 | GIR_RootConstrainSelectedInstOperands, |
| 30756 | // GIR_Coverage, 376, |
| 30757 | GIR_Done, |
| 30758 | // Label 2176: @78587 |
| 30759 | GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(78628), // Rule ID 378 // |
| 30760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30761 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30762 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30764 | // MIs[0] rs1 |
| 30765 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30768 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30769 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30770 | GIR_RootConstrainSelectedInstOperands, |
| 30771 | // GIR_Coverage, 378, |
| 30772 | GIR_Done, |
| 30773 | // Label 2177: @78628 |
| 30774 | GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(78669), // Rule ID 380 // |
| 30775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 30776 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30777 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30779 | // MIs[0] rs1 |
| 30780 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30782 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30783 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30784 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W_AQ_RL), |
| 30785 | GIR_RootConstrainSelectedInstOperands, |
| 30786 | // GIR_Coverage, 380, |
| 30787 | GIR_Done, |
| 30788 | // Label 2178: @78669 |
| 30789 | GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(78710), // Rule ID 382 // |
| 30790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30791 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30792 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30794 | // MIs[0] rs1 |
| 30795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30798 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30799 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30800 | GIR_RootConstrainSelectedInstOperands, |
| 30801 | // GIR_Coverage, 382, |
| 30802 | GIR_Done, |
| 30803 | // Label 2179: @78710 |
| 30804 | GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(78751), // Rule ID 384 // |
| 30805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30806 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30807 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30809 | // MIs[0] rs1 |
| 30810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30812 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30813 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30814 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30815 | GIR_RootConstrainSelectedInstOperands, |
| 30816 | // GIR_Coverage, 384, |
| 30817 | GIR_Done, |
| 30818 | // Label 2180: @78751 |
| 30819 | GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(78792), // Rule ID 386 // |
| 30820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30821 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30824 | // MIs[0] rs1 |
| 30825 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30828 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30829 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30830 | GIR_RootConstrainSelectedInstOperands, |
| 30831 | // GIR_Coverage, 386, |
| 30832 | GIR_Done, |
| 30833 | // Label 2181: @78792 |
| 30834 | GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(78833), // Rule ID 388 // |
| 30835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30836 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30837 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30839 | // MIs[0] rs1 |
| 30840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30843 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30844 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30845 | GIR_RootConstrainSelectedInstOperands, |
| 30846 | // GIR_Coverage, 388, |
| 30847 | GIR_Done, |
| 30848 | // Label 2182: @78833 |
| 30849 | GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(78874), // Rule ID 390 // |
| 30850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 30851 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 30852 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30854 | // MIs[0] rs1 |
| 30855 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30857 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30858 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30859 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_W), |
| 30860 | GIR_RootConstrainSelectedInstOperands, |
| 30861 | // GIR_Coverage, 390, |
| 30862 | GIR_Done, |
| 30863 | // Label 2183: @78874 |
| 30864 | GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(78915), // Rule ID 552 // |
| 30865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 30866 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30867 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30869 | // MIs[0] rs1 |
| 30870 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30872 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30873 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_monotonic>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30874 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D), |
| 30875 | GIR_RootConstrainSelectedInstOperands, |
| 30876 | // GIR_Coverage, 552, |
| 30877 | GIR_Done, |
| 30878 | // Label 2184: @78915 |
| 30879 | GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(78956), // Rule ID 553 // |
| 30880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 30881 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30882 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30884 | // MIs[0] rs1 |
| 30885 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30888 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acquire>> => (AMOSWAP_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30889 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D_AQ), |
| 30890 | GIR_RootConstrainSelectedInstOperands, |
| 30891 | // GIR_Coverage, 553, |
| 30892 | GIR_Done, |
| 30893 | // Label 2185: @78956 |
| 30894 | GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(78997), // Rule ID 554 // |
| 30895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 30896 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30897 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30899 | // MIs[0] rs1 |
| 30900 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30901 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30902 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30903 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_release>> => (AMOSWAP_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30904 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D_RL), |
| 30905 | GIR_RootConstrainSelectedInstOperands, |
| 30906 | // GIR_Coverage, 554, |
| 30907 | GIR_Done, |
| 30908 | // Label 2186: @78997 |
| 30909 | GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(79038), // Rule ID 555 // |
| 30910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 30911 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30912 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30914 | // MIs[0] rs1 |
| 30915 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30916 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30917 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30918 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30919 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D_AQ_RL), |
| 30920 | GIR_RootConstrainSelectedInstOperands, |
| 30921 | // GIR_Coverage, 555, |
| 30922 | GIR_Done, |
| 30923 | // Label 2187: @79038 |
| 30924 | GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(79079), // Rule ID 556 // |
| 30925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 30926 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30927 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 30928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30929 | // MIs[0] rs1 |
| 30930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30931 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30932 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30933 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30934 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D_AQ_RL), |
| 30935 | GIR_RootConstrainSelectedInstOperands, |
| 30936 | // GIR_Coverage, 556, |
| 30937 | GIR_Done, |
| 30938 | // Label 2188: @79079 |
| 30939 | GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(79120), // Rule ID 557 // |
| 30940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 30941 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30942 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 30943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30944 | // MIs[0] rs1 |
| 30945 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30948 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_monotonic>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30949 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D), |
| 30950 | GIR_RootConstrainSelectedInstOperands, |
| 30951 | // GIR_Coverage, 557, |
| 30952 | GIR_Done, |
| 30953 | // Label 2189: @79120 |
| 30954 | GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(79161), // Rule ID 558 // |
| 30955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 30956 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30957 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 30958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30959 | // MIs[0] rs1 |
| 30960 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30961 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30962 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30963 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acquire>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30964 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D), |
| 30965 | GIR_RootConstrainSelectedInstOperands, |
| 30966 | // GIR_Coverage, 558, |
| 30967 | GIR_Done, |
| 30968 | // Label 2190: @79161 |
| 30969 | GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(79202), // Rule ID 559 // |
| 30970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 30971 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30972 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 30973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30974 | // MIs[0] rs1 |
| 30975 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30976 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30977 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30978 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_release>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30979 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D), |
| 30980 | GIR_RootConstrainSelectedInstOperands, |
| 30981 | // GIR_Coverage, 559, |
| 30982 | GIR_Done, |
| 30983 | // Label 2191: @79202 |
| 30984 | GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(79243), // Rule ID 560 // |
| 30985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 30986 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 30987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 30988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30989 | // MIs[0] rs1 |
| 30990 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30991 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30992 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 30993 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acq_rel>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 30994 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D), |
| 30995 | GIR_RootConstrainSelectedInstOperands, |
| 30996 | // GIR_Coverage, 560, |
| 30997 | GIR_Done, |
| 30998 | // Label 2192: @79243 |
| 30999 | GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(79284), // Rule ID 561 // |
| 31000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 31001 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 31002 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31004 | // MIs[0] rs1 |
| 31005 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31008 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_seq_cst>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31009 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_D), |
| 31010 | GIR_RootConstrainSelectedInstOperands, |
| 31011 | // GIR_Coverage, 561, |
| 31012 | GIR_Done, |
| 31013 | // Label 2193: @79284 |
| 31014 | GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(79325), // Rule ID 922 // |
| 31015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31016 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31017 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31019 | // MIs[0] rs1 |
| 31020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31021 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31022 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31023 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>> => (AMOSWAP_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31024 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 31025 | GIR_RootConstrainSelectedInstOperands, |
| 31026 | // GIR_Coverage, 922, |
| 31027 | GIR_Done, |
| 31028 | // Label 2194: @79325 |
| 31029 | GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(79366), // Rule ID 924 // |
| 31030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31031 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31032 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31034 | // MIs[0] rs1 |
| 31035 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31036 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31038 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>> => (AMOSWAP_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31039 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_AQ), |
| 31040 | GIR_RootConstrainSelectedInstOperands, |
| 31041 | // GIR_Coverage, 924, |
| 31042 | GIR_Done, |
| 31043 | // Label 2195: @79366 |
| 31044 | GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(79407), // Rule ID 926 // |
| 31045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31046 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31047 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31048 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31049 | // MIs[0] rs1 |
| 31050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31051 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31052 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31053 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>> => (AMOSWAP_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31054 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_RL), |
| 31055 | GIR_RootConstrainSelectedInstOperands, |
| 31056 | // GIR_Coverage, 926, |
| 31057 | GIR_Done, |
| 31058 | // Label 2196: @79407 |
| 31059 | GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(79448), // Rule ID 928 // |
| 31060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31061 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31062 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31064 | // MIs[0] rs1 |
| 31065 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31066 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31067 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31068 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>> => (AMOSWAP_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31069 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_AQ_RL), |
| 31070 | GIR_RootConstrainSelectedInstOperands, |
| 31071 | // GIR_Coverage, 928, |
| 31072 | GIR_Done, |
| 31073 | // Label 2197: @79448 |
| 31074 | GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(79489), // Rule ID 930 // |
| 31075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31076 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31077 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31079 | // MIs[0] rs1 |
| 31080 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31081 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31082 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31083 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>> => (AMOSWAP_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31084 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B_AQ_RL), |
| 31085 | GIR_RootConstrainSelectedInstOperands, |
| 31086 | // GIR_Coverage, 930, |
| 31087 | GIR_Done, |
| 31088 | // Label 2198: @79489 |
| 31089 | GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(79530), // Rule ID 932 // |
| 31090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31091 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31092 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31093 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31094 | // MIs[0] rs1 |
| 31095 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31096 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31097 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31098 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>> => (AMOSWAP_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31099 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 31100 | GIR_RootConstrainSelectedInstOperands, |
| 31101 | // GIR_Coverage, 932, |
| 31102 | GIR_Done, |
| 31103 | // Label 2199: @79530 |
| 31104 | GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(79571), // Rule ID 934 // |
| 31105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31106 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31107 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31109 | // MIs[0] rs1 |
| 31110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31111 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31112 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31113 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>> => (AMOSWAP_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31114 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 31115 | GIR_RootConstrainSelectedInstOperands, |
| 31116 | // GIR_Coverage, 934, |
| 31117 | GIR_Done, |
| 31118 | // Label 2200: @79571 |
| 31119 | GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(79612), // Rule ID 936 // |
| 31120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31121 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31122 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31124 | // MIs[0] rs1 |
| 31125 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31126 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31127 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31128 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>> => (AMOSWAP_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31129 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 31130 | GIR_RootConstrainSelectedInstOperands, |
| 31131 | // GIR_Coverage, 936, |
| 31132 | GIR_Done, |
| 31133 | // Label 2201: @79612 |
| 31134 | GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(79653), // Rule ID 938 // |
| 31135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31136 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31137 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31139 | // MIs[0] rs1 |
| 31140 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31141 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31142 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31143 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>> => (AMOSWAP_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31144 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 31145 | GIR_RootConstrainSelectedInstOperands, |
| 31146 | // GIR_Coverage, 938, |
| 31147 | GIR_Done, |
| 31148 | // Label 2202: @79653 |
| 31149 | GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(79694), // Rule ID 940 // |
| 31150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31151 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31152 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31154 | // MIs[0] rs1 |
| 31155 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31157 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31158 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>> => (AMOSWAP_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31159 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_B), |
| 31160 | GIR_RootConstrainSelectedInstOperands, |
| 31161 | // GIR_Coverage, 940, |
| 31162 | GIR_Done, |
| 31163 | // Label 2203: @79694 |
| 31164 | GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(79735), // Rule ID 1102 // |
| 31165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31166 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31167 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31169 | // MIs[0] rs1 |
| 31170 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31171 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31172 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31173 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>> => (AMOSWAP_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31174 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 31175 | GIR_RootConstrainSelectedInstOperands, |
| 31176 | // GIR_Coverage, 1102, |
| 31177 | GIR_Done, |
| 31178 | // Label 2204: @79735 |
| 31179 | GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(79776), // Rule ID 1104 // |
| 31180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31181 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31182 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31184 | // MIs[0] rs1 |
| 31185 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31186 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31187 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31188 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>> => (AMOSWAP_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31189 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_AQ), |
| 31190 | GIR_RootConstrainSelectedInstOperands, |
| 31191 | // GIR_Coverage, 1104, |
| 31192 | GIR_Done, |
| 31193 | // Label 2205: @79776 |
| 31194 | GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(79817), // Rule ID 1106 // |
| 31195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31196 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31197 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31199 | // MIs[0] rs1 |
| 31200 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31201 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31202 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31203 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>> => (AMOSWAP_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31204 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_RL), |
| 31205 | GIR_RootConstrainSelectedInstOperands, |
| 31206 | // GIR_Coverage, 1106, |
| 31207 | GIR_Done, |
| 31208 | // Label 2206: @79817 |
| 31209 | GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(79858), // Rule ID 1108 // |
| 31210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31211 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31212 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31214 | // MIs[0] rs1 |
| 31215 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31216 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31218 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>> => (AMOSWAP_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31219 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_AQ_RL), |
| 31220 | GIR_RootConstrainSelectedInstOperands, |
| 31221 | // GIR_Coverage, 1108, |
| 31222 | GIR_Done, |
| 31223 | // Label 2207: @79858 |
| 31224 | GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(79899), // Rule ID 1110 // |
| 31225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 31226 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31227 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31228 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31229 | // MIs[0] rs1 |
| 31230 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31231 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31232 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31233 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>> => (AMOSWAP_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31234 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H_AQ_RL), |
| 31235 | GIR_RootConstrainSelectedInstOperands, |
| 31236 | // GIR_Coverage, 1110, |
| 31237 | GIR_Done, |
| 31238 | // Label 2208: @79899 |
| 31239 | GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(79940), // Rule ID 1112 // |
| 31240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31241 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31244 | // MIs[0] rs1 |
| 31245 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31246 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31247 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31248 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>> => (AMOSWAP_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31249 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 31250 | GIR_RootConstrainSelectedInstOperands, |
| 31251 | // GIR_Coverage, 1112, |
| 31252 | GIR_Done, |
| 31253 | // Label 2209: @79940 |
| 31254 | GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(79981), // Rule ID 1114 // |
| 31255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31256 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31257 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31259 | // MIs[0] rs1 |
| 31260 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31261 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31262 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31263 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>> => (AMOSWAP_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31264 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 31265 | GIR_RootConstrainSelectedInstOperands, |
| 31266 | // GIR_Coverage, 1114, |
| 31267 | GIR_Done, |
| 31268 | // Label 2210: @79981 |
| 31269 | GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(80022), // Rule ID 1116 // |
| 31270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31271 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31272 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31273 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31274 | // MIs[0] rs1 |
| 31275 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31277 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31278 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>> => (AMOSWAP_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31279 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 31280 | GIR_RootConstrainSelectedInstOperands, |
| 31281 | // GIR_Coverage, 1116, |
| 31282 | GIR_Done, |
| 31283 | // Label 2211: @80022 |
| 31284 | GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(80063), // Rule ID 1118 // |
| 31285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31286 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31287 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31289 | // MIs[0] rs1 |
| 31290 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31291 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31292 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31293 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>> => (AMOSWAP_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31294 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 31295 | GIR_RootConstrainSelectedInstOperands, |
| 31296 | // GIR_Coverage, 1118, |
| 31297 | GIR_Done, |
| 31298 | // Label 2212: @80063 |
| 31299 | GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(80104), // Rule ID 1120 // |
| 31300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 31301 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31304 | // MIs[0] rs1 |
| 31305 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31308 | // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>> => (AMOSWAP_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 31309 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOSWAP_H), |
| 31310 | GIR_RootConstrainSelectedInstOperands, |
| 31311 | // GIR_Coverage, 1120, |
| 31312 | GIR_Done, |
| 31313 | // Label 2213: @80104 |
| 31314 | GIM_Reject, |
| 31315 | // Label 2173: @80105 |
| 31316 | GIM_Reject, |
| 31317 | // Label 2121: @80106 |
| 31318 | GIM_Reject, |
| 31319 | // Label 24: @80107 |
| 31320 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2216*/ GIMT_Encode4(83836), |
| 31321 | /*GILLT_s32*//*Label 2214*/ GIMT_Encode4(80126), |
| 31322 | /*GILLT_s64*//*Label 2215*/ GIMT_Encode4(82186), |
| 31323 | // Label 2214: @80126 |
| 31324 | GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(82185), |
| 31325 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 31326 | GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(80175), // Rule ID 393 // |
| 31327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31328 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31329 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31331 | // MIs[0] rs1 |
| 31332 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31333 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31334 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31335 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31336 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31337 | GIR_RootConstrainSelectedInstOperands, |
| 31338 | // GIR_Coverage, 393, |
| 31339 | GIR_Done, |
| 31340 | // Label 2218: @80175 |
| 31341 | GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(80216), // Rule ID 395 // |
| 31342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31343 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31344 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31346 | // MIs[0] rs1 |
| 31347 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31348 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31349 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31350 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31351 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ), |
| 31352 | GIR_RootConstrainSelectedInstOperands, |
| 31353 | // GIR_Coverage, 395, |
| 31354 | GIR_Done, |
| 31355 | // Label 2219: @80216 |
| 31356 | GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(80257), // Rule ID 397 // |
| 31357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31358 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31359 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31361 | // MIs[0] rs1 |
| 31362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31363 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31364 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31365 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31366 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_RL), |
| 31367 | GIR_RootConstrainSelectedInstOperands, |
| 31368 | // GIR_Coverage, 397, |
| 31369 | GIR_Done, |
| 31370 | // Label 2220: @80257 |
| 31371 | GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(80298), // Rule ID 399 // |
| 31372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31373 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31374 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31376 | // MIs[0] rs1 |
| 31377 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31378 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31379 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31380 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31381 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 31382 | GIR_RootConstrainSelectedInstOperands, |
| 31383 | // GIR_Coverage, 399, |
| 31384 | GIR_Done, |
| 31385 | // Label 2221: @80298 |
| 31386 | GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(80339), // Rule ID 401 // |
| 31387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31388 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31389 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31391 | // MIs[0] rs1 |
| 31392 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31395 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31396 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 31397 | GIR_RootConstrainSelectedInstOperands, |
| 31398 | // GIR_Coverage, 401, |
| 31399 | GIR_Done, |
| 31400 | // Label 2222: @80339 |
| 31401 | GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(80380), // Rule ID 403 // |
| 31402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31403 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31404 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31406 | // MIs[0] rs1 |
| 31407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31409 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31410 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31411 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31412 | GIR_RootConstrainSelectedInstOperands, |
| 31413 | // GIR_Coverage, 403, |
| 31414 | GIR_Done, |
| 31415 | // Label 2223: @80380 |
| 31416 | GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(80421), // Rule ID 405 // |
| 31417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31418 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31419 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31421 | // MIs[0] rs1 |
| 31422 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31423 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31424 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31425 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31426 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31427 | GIR_RootConstrainSelectedInstOperands, |
| 31428 | // GIR_Coverage, 405, |
| 31429 | GIR_Done, |
| 31430 | // Label 2224: @80421 |
| 31431 | GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(80462), // Rule ID 407 // |
| 31432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31433 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31434 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31436 | // MIs[0] rs1 |
| 31437 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31438 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31439 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31440 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31441 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31442 | GIR_RootConstrainSelectedInstOperands, |
| 31443 | // GIR_Coverage, 407, |
| 31444 | GIR_Done, |
| 31445 | // Label 2225: @80462 |
| 31446 | GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(80503), // Rule ID 409 // |
| 31447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31448 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31449 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31451 | // MIs[0] rs1 |
| 31452 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31453 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31454 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31455 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31456 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31457 | GIR_RootConstrainSelectedInstOperands, |
| 31458 | // GIR_Coverage, 409, |
| 31459 | GIR_Done, |
| 31460 | // Label 2226: @80503 |
| 31461 | GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(80544), // Rule ID 411 // |
| 31462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31463 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31464 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31466 | // MIs[0] rs1 |
| 31467 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31468 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31469 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31470 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31471 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31472 | GIR_RootConstrainSelectedInstOperands, |
| 31473 | // GIR_Coverage, 411, |
| 31474 | GIR_Done, |
| 31475 | // Label 2227: @80544 |
| 31476 | GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(80585), // Rule ID 710 // |
| 31477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 31478 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31479 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31481 | // MIs[0] rs1 |
| 31482 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31483 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31484 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31485 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31486 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31487 | GIR_RootConstrainSelectedInstOperands, |
| 31488 | // GIR_Coverage, 710, |
| 31489 | GIR_Done, |
| 31490 | // Label 2228: @80585 |
| 31491 | GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(80626), // Rule ID 711 // |
| 31492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31493 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31494 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31496 | // MIs[0] rs1 |
| 31497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31498 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31499 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31500 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31501 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31502 | GIR_RootConstrainSelectedInstOperands, |
| 31503 | // GIR_Coverage, 711, |
| 31504 | GIR_Done, |
| 31505 | // Label 2229: @80626 |
| 31506 | GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(80667), // Rule ID 712 // |
| 31507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 31508 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31509 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31511 | // MIs[0] rs1 |
| 31512 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31513 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31514 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31515 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31516 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ), |
| 31517 | GIR_RootConstrainSelectedInstOperands, |
| 31518 | // GIR_Coverage, 712, |
| 31519 | GIR_Done, |
| 31520 | // Label 2230: @80667 |
| 31521 | GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(80708), // Rule ID 713 // |
| 31522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31523 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31524 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31526 | // MIs[0] rs1 |
| 31527 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31528 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31530 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31531 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ), |
| 31532 | GIR_RootConstrainSelectedInstOperands, |
| 31533 | // GIR_Coverage, 713, |
| 31534 | GIR_Done, |
| 31535 | // Label 2231: @80708 |
| 31536 | GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(80749), // Rule ID 714 // |
| 31537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 31538 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31539 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31541 | // MIs[0] rs1 |
| 31542 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31543 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31544 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31545 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31546 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_RL), |
| 31547 | GIR_RootConstrainSelectedInstOperands, |
| 31548 | // GIR_Coverage, 714, |
| 31549 | GIR_Done, |
| 31550 | // Label 2232: @80749 |
| 31551 | GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(80790), // Rule ID 715 // |
| 31552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31553 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31554 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31556 | // MIs[0] rs1 |
| 31557 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31558 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31559 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31560 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31561 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_RL), |
| 31562 | GIR_RootConstrainSelectedInstOperands, |
| 31563 | // GIR_Coverage, 715, |
| 31564 | GIR_Done, |
| 31565 | // Label 2233: @80790 |
| 31566 | GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(80831), // Rule ID 716 // |
| 31567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 31568 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31569 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31571 | // MIs[0] rs1 |
| 31572 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31574 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31575 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31576 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 31577 | GIR_RootConstrainSelectedInstOperands, |
| 31578 | // GIR_Coverage, 716, |
| 31579 | GIR_Done, |
| 31580 | // Label 2234: @80831 |
| 31581 | GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(80872), // Rule ID 717 // |
| 31582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31583 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31584 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31586 | // MIs[0] rs1 |
| 31587 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31589 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31590 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31591 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 31592 | GIR_RootConstrainSelectedInstOperands, |
| 31593 | // GIR_Coverage, 717, |
| 31594 | GIR_Done, |
| 31595 | // Label 2235: @80872 |
| 31596 | GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(80913), // Rule ID 718 // |
| 31597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 31598 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31599 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31601 | // MIs[0] rs1 |
| 31602 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31603 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31604 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31605 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31606 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 31607 | GIR_RootConstrainSelectedInstOperands, |
| 31608 | // GIR_Coverage, 718, |
| 31609 | GIR_Done, |
| 31610 | // Label 2236: @80913 |
| 31611 | GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(80954), // Rule ID 719 // |
| 31612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 31613 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31614 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31616 | // MIs[0] rs1 |
| 31617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31619 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31620 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31621 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 31622 | GIR_RootConstrainSelectedInstOperands, |
| 31623 | // GIR_Coverage, 719, |
| 31624 | GIR_Done, |
| 31625 | // Label 2237: @80954 |
| 31626 | GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(80995), // Rule ID 720 // |
| 31627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 31628 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31629 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31631 | // MIs[0] rs1 |
| 31632 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31635 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31636 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31637 | GIR_RootConstrainSelectedInstOperands, |
| 31638 | // GIR_Coverage, 720, |
| 31639 | GIR_Done, |
| 31640 | // Label 2238: @80995 |
| 31641 | GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(81036), // Rule ID 721 // |
| 31642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31643 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31644 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31646 | // MIs[0] rs1 |
| 31647 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31649 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31650 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31651 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31652 | GIR_RootConstrainSelectedInstOperands, |
| 31653 | // GIR_Coverage, 721, |
| 31654 | GIR_Done, |
| 31655 | // Label 2239: @81036 |
| 31656 | GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(81077), // Rule ID 722 // |
| 31657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 31658 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31659 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31661 | // MIs[0] rs1 |
| 31662 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31664 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31665 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31666 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31667 | GIR_RootConstrainSelectedInstOperands, |
| 31668 | // GIR_Coverage, 722, |
| 31669 | GIR_Done, |
| 31670 | // Label 2240: @81077 |
| 31671 | GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(81118), // Rule ID 723 // |
| 31672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31673 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31674 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31676 | // MIs[0] rs1 |
| 31677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31678 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31680 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31681 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31682 | GIR_RootConstrainSelectedInstOperands, |
| 31683 | // GIR_Coverage, 723, |
| 31684 | GIR_Done, |
| 31685 | // Label 2241: @81118 |
| 31686 | GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(81159), // Rule ID 724 // |
| 31687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 31688 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31689 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31691 | // MIs[0] rs1 |
| 31692 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31693 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31694 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31695 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31696 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31697 | GIR_RootConstrainSelectedInstOperands, |
| 31698 | // GIR_Coverage, 724, |
| 31699 | GIR_Done, |
| 31700 | // Label 2242: @81159 |
| 31701 | GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(81200), // Rule ID 725 // |
| 31702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31703 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31704 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31706 | // MIs[0] rs1 |
| 31707 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31708 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31709 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31710 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31711 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31712 | GIR_RootConstrainSelectedInstOperands, |
| 31713 | // GIR_Coverage, 725, |
| 31714 | GIR_Done, |
| 31715 | // Label 2243: @81200 |
| 31716 | GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(81241), // Rule ID 726 // |
| 31717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 31718 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31719 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31721 | // MIs[0] rs1 |
| 31722 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31723 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31724 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31725 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31726 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31727 | GIR_RootConstrainSelectedInstOperands, |
| 31728 | // GIR_Coverage, 726, |
| 31729 | GIR_Done, |
| 31730 | // Label 2244: @81241 |
| 31731 | GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(81282), // Rule ID 727 // |
| 31732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31733 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31734 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31736 | // MIs[0] rs1 |
| 31737 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31738 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31739 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31740 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31742 | GIR_RootConstrainSelectedInstOperands, |
| 31743 | // GIR_Coverage, 727, |
| 31744 | GIR_Done, |
| 31745 | // Label 2245: @81282 |
| 31746 | GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(81323), // Rule ID 728 // |
| 31747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 31748 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31749 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31751 | // MIs[0] rs1 |
| 31752 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31753 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31754 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31755 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31756 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31757 | GIR_RootConstrainSelectedInstOperands, |
| 31758 | // GIR_Coverage, 728, |
| 31759 | GIR_Done, |
| 31760 | // Label 2246: @81323 |
| 31761 | GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(81364), // Rule ID 729 // |
| 31762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 31763 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 31764 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31766 | // MIs[0] rs1 |
| 31767 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31768 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31770 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31771 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 31772 | GIR_RootConstrainSelectedInstOperands, |
| 31773 | // GIR_Coverage, 729, |
| 31774 | GIR_Done, |
| 31775 | // Label 2247: @81364 |
| 31776 | GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(81405), // Rule ID 943 // |
| 31777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31778 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31779 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31781 | // MIs[0] rs1 |
| 31782 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31784 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31785 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>> => (AMOADD_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31786 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 31787 | GIR_RootConstrainSelectedInstOperands, |
| 31788 | // GIR_Coverage, 943, |
| 31789 | GIR_Done, |
| 31790 | // Label 2248: @81405 |
| 31791 | GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(81446), // Rule ID 945 // |
| 31792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31793 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31794 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31796 | // MIs[0] rs1 |
| 31797 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31800 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>> => (AMOADD_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31801 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_AQ), |
| 31802 | GIR_RootConstrainSelectedInstOperands, |
| 31803 | // GIR_Coverage, 945, |
| 31804 | GIR_Done, |
| 31805 | // Label 2249: @81446 |
| 31806 | GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(81487), // Rule ID 947 // |
| 31807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31808 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31809 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31811 | // MIs[0] rs1 |
| 31812 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31813 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31814 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31815 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>> => (AMOADD_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31816 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_RL), |
| 31817 | GIR_RootConstrainSelectedInstOperands, |
| 31818 | // GIR_Coverage, 947, |
| 31819 | GIR_Done, |
| 31820 | // Label 2250: @81487 |
| 31821 | GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(81528), // Rule ID 949 // |
| 31822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31823 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31824 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31826 | // MIs[0] rs1 |
| 31827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31828 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31829 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31830 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>> => (AMOADD_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31831 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_AQ_RL), |
| 31832 | GIR_RootConstrainSelectedInstOperands, |
| 31833 | // GIR_Coverage, 949, |
| 31834 | GIR_Done, |
| 31835 | // Label 2251: @81528 |
| 31836 | GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(81569), // Rule ID 951 // |
| 31837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31838 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31839 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31841 | // MIs[0] rs1 |
| 31842 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31843 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31844 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31845 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>> => (AMOADD_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31846 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_AQ_RL), |
| 31847 | GIR_RootConstrainSelectedInstOperands, |
| 31848 | // GIR_Coverage, 951, |
| 31849 | GIR_Done, |
| 31850 | // Label 2252: @81569 |
| 31851 | GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(81610), // Rule ID 953 // |
| 31852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 31853 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31854 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31856 | // MIs[0] rs1 |
| 31857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31858 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31859 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31860 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>> => (AMOADD_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31861 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 31862 | GIR_RootConstrainSelectedInstOperands, |
| 31863 | // GIR_Coverage, 953, |
| 31864 | GIR_Done, |
| 31865 | // Label 2253: @81610 |
| 31866 | GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(81651), // Rule ID 955 // |
| 31867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 31868 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31869 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31871 | // MIs[0] rs1 |
| 31872 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31873 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31875 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>> => (AMOADD_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31876 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 31877 | GIR_RootConstrainSelectedInstOperands, |
| 31878 | // GIR_Coverage, 955, |
| 31879 | GIR_Done, |
| 31880 | // Label 2254: @81651 |
| 31881 | GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(81692), // Rule ID 957 // |
| 31882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 31883 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31884 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31886 | // MIs[0] rs1 |
| 31887 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31890 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>> => (AMOADD_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31891 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 31892 | GIR_RootConstrainSelectedInstOperands, |
| 31893 | // GIR_Coverage, 957, |
| 31894 | GIR_Done, |
| 31895 | // Label 2255: @81692 |
| 31896 | GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(81733), // Rule ID 959 // |
| 31897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 31898 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31899 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31901 | // MIs[0] rs1 |
| 31902 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31903 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31904 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31905 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>> => (AMOADD_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31906 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 31907 | GIR_RootConstrainSelectedInstOperands, |
| 31908 | // GIR_Coverage, 959, |
| 31909 | GIR_Done, |
| 31910 | // Label 2256: @81733 |
| 31911 | GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(81774), // Rule ID 961 // |
| 31912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 31913 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 31914 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31916 | // MIs[0] rs1 |
| 31917 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31920 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>> => (AMOADD_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31921 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 31922 | GIR_RootConstrainSelectedInstOperands, |
| 31923 | // GIR_Coverage, 961, |
| 31924 | GIR_Done, |
| 31925 | // Label 2257: @81774 |
| 31926 | GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(81815), // Rule ID 1123 // |
| 31927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31928 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 31930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31931 | // MIs[0] rs1 |
| 31932 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31934 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31935 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>> => (AMOADD_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31936 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 31937 | GIR_RootConstrainSelectedInstOperands, |
| 31938 | // GIR_Coverage, 1123, |
| 31939 | GIR_Done, |
| 31940 | // Label 2258: @81815 |
| 31941 | GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(81856), // Rule ID 1125 // |
| 31942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31943 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31944 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 31945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31946 | // MIs[0] rs1 |
| 31947 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31949 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31950 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>> => (AMOADD_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31951 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_AQ), |
| 31952 | GIR_RootConstrainSelectedInstOperands, |
| 31953 | // GIR_Coverage, 1125, |
| 31954 | GIR_Done, |
| 31955 | // Label 2259: @81856 |
| 31956 | GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(81897), // Rule ID 1127 // |
| 31957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31958 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31959 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 31960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31961 | // MIs[0] rs1 |
| 31962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31963 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31964 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31965 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>> => (AMOADD_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31966 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_RL), |
| 31967 | GIR_RootConstrainSelectedInstOperands, |
| 31968 | // GIR_Coverage, 1127, |
| 31969 | GIR_Done, |
| 31970 | // Label 2260: @81897 |
| 31971 | GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(81938), // Rule ID 1129 // |
| 31972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31973 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31974 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 31975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31976 | // MIs[0] rs1 |
| 31977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31980 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>> => (AMOADD_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31981 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_AQ_RL), |
| 31982 | GIR_RootConstrainSelectedInstOperands, |
| 31983 | // GIR_Coverage, 1129, |
| 31984 | GIR_Done, |
| 31985 | // Label 2261: @81938 |
| 31986 | GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(81979), // Rule ID 1131 // |
| 31987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 31988 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 31989 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 31990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31991 | // MIs[0] rs1 |
| 31992 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 31993 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31994 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 31995 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>> => (AMOADD_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 31996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_AQ_RL), |
| 31997 | GIR_RootConstrainSelectedInstOperands, |
| 31998 | // GIR_Coverage, 1131, |
| 31999 | GIR_Done, |
| 32000 | // Label 2262: @81979 |
| 32001 | GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(82020), // Rule ID 1133 // |
| 32002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 32003 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32004 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32006 | // MIs[0] rs1 |
| 32007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32008 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32009 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32010 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>> => (AMOADD_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32011 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32012 | GIR_RootConstrainSelectedInstOperands, |
| 32013 | // GIR_Coverage, 1133, |
| 32014 | GIR_Done, |
| 32015 | // Label 2263: @82020 |
| 32016 | GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(82061), // Rule ID 1135 // |
| 32017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 32018 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32019 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32021 | // MIs[0] rs1 |
| 32022 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32023 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32024 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32025 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>> => (AMOADD_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32026 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32027 | GIR_RootConstrainSelectedInstOperands, |
| 32028 | // GIR_Coverage, 1135, |
| 32029 | GIR_Done, |
| 32030 | // Label 2264: @82061 |
| 32031 | GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(82102), // Rule ID 1137 // |
| 32032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 32033 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32034 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32036 | // MIs[0] rs1 |
| 32037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32038 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32040 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>> => (AMOADD_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32041 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32042 | GIR_RootConstrainSelectedInstOperands, |
| 32043 | // GIR_Coverage, 1137, |
| 32044 | GIR_Done, |
| 32045 | // Label 2265: @82102 |
| 32046 | GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(82143), // Rule ID 1139 // |
| 32047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 32048 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32049 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32051 | // MIs[0] rs1 |
| 32052 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32053 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32054 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32055 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>> => (AMOADD_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32056 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32057 | GIR_RootConstrainSelectedInstOperands, |
| 32058 | // GIR_Coverage, 1139, |
| 32059 | GIR_Done, |
| 32060 | // Label 2266: @82143 |
| 32061 | GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(82184), // Rule ID 1141 // |
| 32062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 32063 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32064 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32066 | // MIs[0] rs1 |
| 32067 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32068 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32069 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32070 | // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>> => (AMOADD_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32071 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32072 | GIR_RootConstrainSelectedInstOperands, |
| 32073 | // GIR_Coverage, 1141, |
| 32074 | GIR_Done, |
| 32075 | // Label 2267: @82184 |
| 32076 | GIM_Reject, |
| 32077 | // Label 2217: @82185 |
| 32078 | GIM_Reject, |
| 32079 | // Label 2215: @82186 |
| 32080 | GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(83835), |
| 32081 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 32082 | GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(82235), // Rule ID 392 // |
| 32083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32084 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32085 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32087 | // MIs[0] rs1 |
| 32088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32089 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32090 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32091 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32092 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 32093 | GIR_RootConstrainSelectedInstOperands, |
| 32094 | // GIR_Coverage, 392, |
| 32095 | GIR_Done, |
| 32096 | // Label 2269: @82235 |
| 32097 | GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(82276), // Rule ID 394 // |
| 32098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32099 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32100 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32102 | // MIs[0] rs1 |
| 32103 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32106 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32107 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ), |
| 32108 | GIR_RootConstrainSelectedInstOperands, |
| 32109 | // GIR_Coverage, 394, |
| 32110 | GIR_Done, |
| 32111 | // Label 2270: @82276 |
| 32112 | GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(82317), // Rule ID 396 // |
| 32113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32114 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32115 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32117 | // MIs[0] rs1 |
| 32118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32119 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32120 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32121 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32122 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_RL), |
| 32123 | GIR_RootConstrainSelectedInstOperands, |
| 32124 | // GIR_Coverage, 396, |
| 32125 | GIR_Done, |
| 32126 | // Label 2271: @82317 |
| 32127 | GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(82358), // Rule ID 398 // |
| 32128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32129 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32130 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32132 | // MIs[0] rs1 |
| 32133 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32134 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32135 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32136 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32137 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 32138 | GIR_RootConstrainSelectedInstOperands, |
| 32139 | // GIR_Coverage, 398, |
| 32140 | GIR_Done, |
| 32141 | // Label 2272: @82358 |
| 32142 | GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(82399), // Rule ID 400 // |
| 32143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32144 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32147 | // MIs[0] rs1 |
| 32148 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32150 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32151 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32152 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W_AQ_RL), |
| 32153 | GIR_RootConstrainSelectedInstOperands, |
| 32154 | // GIR_Coverage, 400, |
| 32155 | GIR_Done, |
| 32156 | // Label 2273: @82399 |
| 32157 | GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(82440), // Rule ID 402 // |
| 32158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 32159 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32160 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32162 | // MIs[0] rs1 |
| 32163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32164 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32165 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32166 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32167 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 32168 | GIR_RootConstrainSelectedInstOperands, |
| 32169 | // GIR_Coverage, 402, |
| 32170 | GIR_Done, |
| 32171 | // Label 2274: @82440 |
| 32172 | GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(82481), // Rule ID 404 // |
| 32173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 32174 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32175 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32177 | // MIs[0] rs1 |
| 32178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32179 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32180 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32181 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32182 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 32183 | GIR_RootConstrainSelectedInstOperands, |
| 32184 | // GIR_Coverage, 404, |
| 32185 | GIR_Done, |
| 32186 | // Label 2275: @82481 |
| 32187 | GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(82522), // Rule ID 406 // |
| 32188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 32189 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32190 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32191 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32192 | // MIs[0] rs1 |
| 32193 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32194 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32195 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32196 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32197 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 32198 | GIR_RootConstrainSelectedInstOperands, |
| 32199 | // GIR_Coverage, 406, |
| 32200 | GIR_Done, |
| 32201 | // Label 2276: @82522 |
| 32202 | GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(82563), // Rule ID 408 // |
| 32203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 32204 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32205 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32207 | // MIs[0] rs1 |
| 32208 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32211 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32212 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 32213 | GIR_RootConstrainSelectedInstOperands, |
| 32214 | // GIR_Coverage, 408, |
| 32215 | GIR_Done, |
| 32216 | // Label 2277: @82563 |
| 32217 | GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(82604), // Rule ID 410 // |
| 32218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 32219 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32220 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32222 | // MIs[0] rs1 |
| 32223 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32224 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32225 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32226 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32227 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_W), |
| 32228 | GIR_RootConstrainSelectedInstOperands, |
| 32229 | // GIR_Coverage, 410, |
| 32230 | GIR_Done, |
| 32231 | // Label 2278: @82604 |
| 32232 | GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(82645), // Rule ID 562 // |
| 32233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 32234 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32237 | // MIs[0] rs1 |
| 32238 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32241 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_monotonic>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32242 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D), |
| 32243 | GIR_RootConstrainSelectedInstOperands, |
| 32244 | // GIR_Coverage, 562, |
| 32245 | GIR_Done, |
| 32246 | // Label 2279: @82645 |
| 32247 | GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(82686), // Rule ID 563 // |
| 32248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 32249 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32250 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32252 | // MIs[0] rs1 |
| 32253 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32256 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acquire>> => (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32257 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D_AQ), |
| 32258 | GIR_RootConstrainSelectedInstOperands, |
| 32259 | // GIR_Coverage, 563, |
| 32260 | GIR_Done, |
| 32261 | // Label 2280: @82686 |
| 32262 | GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(82727), // Rule ID 564 // |
| 32263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 32264 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32265 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32267 | // MIs[0] rs1 |
| 32268 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32269 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32270 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32271 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_release>> => (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32272 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D_RL), |
| 32273 | GIR_RootConstrainSelectedInstOperands, |
| 32274 | // GIR_Coverage, 564, |
| 32275 | GIR_Done, |
| 32276 | // Label 2281: @82727 |
| 32277 | GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(82768), // Rule ID 565 // |
| 32278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 32279 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32280 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32282 | // MIs[0] rs1 |
| 32283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32284 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32286 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32287 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D_AQ_RL), |
| 32288 | GIR_RootConstrainSelectedInstOperands, |
| 32289 | // GIR_Coverage, 565, |
| 32290 | GIR_Done, |
| 32291 | // Label 2282: @82768 |
| 32292 | GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(82809), // Rule ID 566 // |
| 32293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 32294 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32295 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32297 | // MIs[0] rs1 |
| 32298 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32299 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32300 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32301 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32302 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D_AQ_RL), |
| 32303 | GIR_RootConstrainSelectedInstOperands, |
| 32304 | // GIR_Coverage, 566, |
| 32305 | GIR_Done, |
| 32306 | // Label 2283: @82809 |
| 32307 | GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(82850), // Rule ID 567 // |
| 32308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 32309 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32310 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32312 | // MIs[0] rs1 |
| 32313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32315 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32316 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_monotonic>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32317 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D), |
| 32318 | GIR_RootConstrainSelectedInstOperands, |
| 32319 | // GIR_Coverage, 567, |
| 32320 | GIR_Done, |
| 32321 | // Label 2284: @82850 |
| 32322 | GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(82891), // Rule ID 568 // |
| 32323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 32324 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32325 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32327 | // MIs[0] rs1 |
| 32328 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32329 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32330 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32331 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acquire>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32332 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D), |
| 32333 | GIR_RootConstrainSelectedInstOperands, |
| 32334 | // GIR_Coverage, 568, |
| 32335 | GIR_Done, |
| 32336 | // Label 2285: @82891 |
| 32337 | GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(82932), // Rule ID 569 // |
| 32338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 32339 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32340 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32342 | // MIs[0] rs1 |
| 32343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32344 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32346 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_release>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32347 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D), |
| 32348 | GIR_RootConstrainSelectedInstOperands, |
| 32349 | // GIR_Coverage, 569, |
| 32350 | GIR_Done, |
| 32351 | // Label 2286: @82932 |
| 32352 | GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(82973), // Rule ID 570 // |
| 32353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 32354 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32355 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32357 | // MIs[0] rs1 |
| 32358 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32361 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acq_rel>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32362 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D), |
| 32363 | GIR_RootConstrainSelectedInstOperands, |
| 32364 | // GIR_Coverage, 570, |
| 32365 | GIR_Done, |
| 32366 | // Label 2287: @82973 |
| 32367 | GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(83014), // Rule ID 571 // |
| 32368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 32369 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 32370 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32372 | // MIs[0] rs1 |
| 32373 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32376 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_seq_cst>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32377 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_D), |
| 32378 | GIR_RootConstrainSelectedInstOperands, |
| 32379 | // GIR_Coverage, 571, |
| 32380 | GIR_Done, |
| 32381 | // Label 2288: @83014 |
| 32382 | GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(83055), // Rule ID 942 // |
| 32383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32384 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32385 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32387 | // MIs[0] rs1 |
| 32388 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32389 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32390 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32391 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>> => (AMOADD_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32392 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 32393 | GIR_RootConstrainSelectedInstOperands, |
| 32394 | // GIR_Coverage, 942, |
| 32395 | GIR_Done, |
| 32396 | // Label 2289: @83055 |
| 32397 | GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(83096), // Rule ID 944 // |
| 32398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32399 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32400 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32401 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32402 | // MIs[0] rs1 |
| 32403 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32404 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32405 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32406 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>> => (AMOADD_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32407 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_AQ), |
| 32408 | GIR_RootConstrainSelectedInstOperands, |
| 32409 | // GIR_Coverage, 944, |
| 32410 | GIR_Done, |
| 32411 | // Label 2290: @83096 |
| 32412 | GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(83137), // Rule ID 946 // |
| 32413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32414 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32415 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32417 | // MIs[0] rs1 |
| 32418 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32419 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32420 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32421 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>> => (AMOADD_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32422 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_RL), |
| 32423 | GIR_RootConstrainSelectedInstOperands, |
| 32424 | // GIR_Coverage, 946, |
| 32425 | GIR_Done, |
| 32426 | // Label 2291: @83137 |
| 32427 | GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(83178), // Rule ID 948 // |
| 32428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32429 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32430 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32432 | // MIs[0] rs1 |
| 32433 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32435 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32436 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>> => (AMOADD_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32437 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_AQ_RL), |
| 32438 | GIR_RootConstrainSelectedInstOperands, |
| 32439 | // GIR_Coverage, 948, |
| 32440 | GIR_Done, |
| 32441 | // Label 2292: @83178 |
| 32442 | GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(83219), // Rule ID 950 // |
| 32443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32444 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32445 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32447 | // MIs[0] rs1 |
| 32448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32450 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32451 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>> => (AMOADD_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32452 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B_AQ_RL), |
| 32453 | GIR_RootConstrainSelectedInstOperands, |
| 32454 | // GIR_Coverage, 950, |
| 32455 | GIR_Done, |
| 32456 | // Label 2293: @83219 |
| 32457 | GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(83260), // Rule ID 952 // |
| 32458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32459 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32460 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32462 | // MIs[0] rs1 |
| 32463 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32464 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32465 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32466 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>> => (AMOADD_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32467 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 32468 | GIR_RootConstrainSelectedInstOperands, |
| 32469 | // GIR_Coverage, 952, |
| 32470 | GIR_Done, |
| 32471 | // Label 2294: @83260 |
| 32472 | GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(83301), // Rule ID 954 // |
| 32473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32474 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32475 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32477 | // MIs[0] rs1 |
| 32478 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32479 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32480 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32481 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>> => (AMOADD_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32482 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 32483 | GIR_RootConstrainSelectedInstOperands, |
| 32484 | // GIR_Coverage, 954, |
| 32485 | GIR_Done, |
| 32486 | // Label 2295: @83301 |
| 32487 | GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(83342), // Rule ID 956 // |
| 32488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32489 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32490 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32492 | // MIs[0] rs1 |
| 32493 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32494 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32495 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32496 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>> => (AMOADD_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32497 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 32498 | GIR_RootConstrainSelectedInstOperands, |
| 32499 | // GIR_Coverage, 956, |
| 32500 | GIR_Done, |
| 32501 | // Label 2296: @83342 |
| 32502 | GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(83383), // Rule ID 958 // |
| 32503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32504 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32505 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32507 | // MIs[0] rs1 |
| 32508 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32509 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32510 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32511 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>> => (AMOADD_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32512 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 32513 | GIR_RootConstrainSelectedInstOperands, |
| 32514 | // GIR_Coverage, 958, |
| 32515 | GIR_Done, |
| 32516 | // Label 2297: @83383 |
| 32517 | GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(83424), // Rule ID 960 // |
| 32518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32519 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 32520 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32522 | // MIs[0] rs1 |
| 32523 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32524 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32525 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32526 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>> => (AMOADD_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32527 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_B), |
| 32528 | GIR_RootConstrainSelectedInstOperands, |
| 32529 | // GIR_Coverage, 960, |
| 32530 | GIR_Done, |
| 32531 | // Label 2298: @83424 |
| 32532 | GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(83465), // Rule ID 1122 // |
| 32533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32534 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32535 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32537 | // MIs[0] rs1 |
| 32538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32540 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32541 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>> => (AMOADD_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32542 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32543 | GIR_RootConstrainSelectedInstOperands, |
| 32544 | // GIR_Coverage, 1122, |
| 32545 | GIR_Done, |
| 32546 | // Label 2299: @83465 |
| 32547 | GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(83506), // Rule ID 1124 // |
| 32548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32549 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32550 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32552 | // MIs[0] rs1 |
| 32553 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32554 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32555 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32556 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>> => (AMOADD_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32557 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_AQ), |
| 32558 | GIR_RootConstrainSelectedInstOperands, |
| 32559 | // GIR_Coverage, 1124, |
| 32560 | GIR_Done, |
| 32561 | // Label 2300: @83506 |
| 32562 | GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(83547), // Rule ID 1126 // |
| 32563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32564 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32565 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32567 | // MIs[0] rs1 |
| 32568 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32569 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32570 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32571 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>> => (AMOADD_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32572 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_RL), |
| 32573 | GIR_RootConstrainSelectedInstOperands, |
| 32574 | // GIR_Coverage, 1126, |
| 32575 | GIR_Done, |
| 32576 | // Label 2301: @83547 |
| 32577 | GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(83588), // Rule ID 1128 // |
| 32578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32579 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32580 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32581 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32582 | // MIs[0] rs1 |
| 32583 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32586 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>> => (AMOADD_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32587 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_AQ_RL), |
| 32588 | GIR_RootConstrainSelectedInstOperands, |
| 32589 | // GIR_Coverage, 1128, |
| 32590 | GIR_Done, |
| 32591 | // Label 2302: @83588 |
| 32592 | GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(83629), // Rule ID 1130 // |
| 32593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 32594 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32595 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32597 | // MIs[0] rs1 |
| 32598 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32599 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32600 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32601 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>> => (AMOADD_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32602 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H_AQ_RL), |
| 32603 | GIR_RootConstrainSelectedInstOperands, |
| 32604 | // GIR_Coverage, 1130, |
| 32605 | GIR_Done, |
| 32606 | // Label 2303: @83629 |
| 32607 | GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(83670), // Rule ID 1132 // |
| 32608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32609 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32610 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32612 | // MIs[0] rs1 |
| 32613 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32614 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32615 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32616 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>> => (AMOADD_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32617 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32618 | GIR_RootConstrainSelectedInstOperands, |
| 32619 | // GIR_Coverage, 1132, |
| 32620 | GIR_Done, |
| 32621 | // Label 2304: @83670 |
| 32622 | GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(83711), // Rule ID 1134 // |
| 32623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32624 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32625 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32627 | // MIs[0] rs1 |
| 32628 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32629 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32630 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32631 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>> => (AMOADD_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32632 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32633 | GIR_RootConstrainSelectedInstOperands, |
| 32634 | // GIR_Coverage, 1134, |
| 32635 | GIR_Done, |
| 32636 | // Label 2305: @83711 |
| 32637 | GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(83752), // Rule ID 1136 // |
| 32638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32639 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32640 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32642 | // MIs[0] rs1 |
| 32643 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32644 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32646 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>> => (AMOADD_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32647 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32648 | GIR_RootConstrainSelectedInstOperands, |
| 32649 | // GIR_Coverage, 1136, |
| 32650 | GIR_Done, |
| 32651 | // Label 2306: @83752 |
| 32652 | GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(83793), // Rule ID 1138 // |
| 32653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32654 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32655 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32657 | // MIs[0] rs1 |
| 32658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32660 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32661 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>> => (AMOADD_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32662 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32663 | GIR_RootConstrainSelectedInstOperands, |
| 32664 | // GIR_Coverage, 1138, |
| 32665 | GIR_Done, |
| 32666 | // Label 2307: @83793 |
| 32667 | GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(83834), // Rule ID 1140 // |
| 32668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 32669 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 32670 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32672 | // MIs[0] rs1 |
| 32673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32674 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32675 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32676 | // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>> => (AMOADD_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 32677 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOADD_H), |
| 32678 | GIR_RootConstrainSelectedInstOperands, |
| 32679 | // GIR_Coverage, 1140, |
| 32680 | GIR_Done, |
| 32681 | // Label 2308: @83834 |
| 32682 | GIM_Reject, |
| 32683 | // Label 2268: @83835 |
| 32684 | GIM_Reject, |
| 32685 | // Label 2216: @83836 |
| 32686 | GIM_Reject, |
| 32687 | // Label 25: @83837 |
| 32688 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2311*/ GIMT_Encode4(87566), |
| 32689 | /*GILLT_s32*//*Label 2309*/ GIMT_Encode4(83856), |
| 32690 | /*GILLT_s64*//*Label 2310*/ GIMT_Encode4(85916), |
| 32691 | // Label 2309: @83856 |
| 32692 | GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(85915), |
| 32693 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32694 | GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(83905), // Rule ID 413 // |
| 32695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32696 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32697 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32699 | // MIs[0] rs1 |
| 32700 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32701 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32702 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32703 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32704 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32705 | GIR_RootConstrainSelectedInstOperands, |
| 32706 | // GIR_Coverage, 413, |
| 32707 | GIR_Done, |
| 32708 | // Label 2313: @83905 |
| 32709 | GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(83946), // Rule ID 415 // |
| 32710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32711 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32712 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32714 | // MIs[0] rs1 |
| 32715 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32716 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32717 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32718 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32719 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ), |
| 32720 | GIR_RootConstrainSelectedInstOperands, |
| 32721 | // GIR_Coverage, 415, |
| 32722 | GIR_Done, |
| 32723 | // Label 2314: @83946 |
| 32724 | GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(83987), // Rule ID 417 // |
| 32725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32726 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32727 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32729 | // MIs[0] rs1 |
| 32730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32731 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32732 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32733 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32734 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_RL), |
| 32735 | GIR_RootConstrainSelectedInstOperands, |
| 32736 | // GIR_Coverage, 417, |
| 32737 | GIR_Done, |
| 32738 | // Label 2315: @83987 |
| 32739 | GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(84028), // Rule ID 419 // |
| 32740 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32741 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32742 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32744 | // MIs[0] rs1 |
| 32745 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32746 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32747 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32748 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32749 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 32750 | GIR_RootConstrainSelectedInstOperands, |
| 32751 | // GIR_Coverage, 419, |
| 32752 | GIR_Done, |
| 32753 | // Label 2316: @84028 |
| 32754 | GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(84069), // Rule ID 421 // |
| 32755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32756 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32757 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32759 | // MIs[0] rs1 |
| 32760 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32761 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32762 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32763 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 32765 | GIR_RootConstrainSelectedInstOperands, |
| 32766 | // GIR_Coverage, 421, |
| 32767 | GIR_Done, |
| 32768 | // Label 2317: @84069 |
| 32769 | GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(84110), // Rule ID 423 // |
| 32770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 32771 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32772 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32774 | // MIs[0] rs1 |
| 32775 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32777 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32778 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32779 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32780 | GIR_RootConstrainSelectedInstOperands, |
| 32781 | // GIR_Coverage, 423, |
| 32782 | GIR_Done, |
| 32783 | // Label 2318: @84110 |
| 32784 | GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(84151), // Rule ID 425 // |
| 32785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 32786 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32787 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32789 | // MIs[0] rs1 |
| 32790 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32791 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32792 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32793 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32794 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32795 | GIR_RootConstrainSelectedInstOperands, |
| 32796 | // GIR_Coverage, 425, |
| 32797 | GIR_Done, |
| 32798 | // Label 2319: @84151 |
| 32799 | GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(84192), // Rule ID 427 // |
| 32800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 32801 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32802 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32804 | // MIs[0] rs1 |
| 32805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32806 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32807 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32808 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32809 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32810 | GIR_RootConstrainSelectedInstOperands, |
| 32811 | // GIR_Coverage, 427, |
| 32812 | GIR_Done, |
| 32813 | // Label 2320: @84192 |
| 32814 | GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(84233), // Rule ID 429 // |
| 32815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 32816 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32817 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32819 | // MIs[0] rs1 |
| 32820 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32821 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32822 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32823 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32824 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32825 | GIR_RootConstrainSelectedInstOperands, |
| 32826 | // GIR_Coverage, 429, |
| 32827 | GIR_Done, |
| 32828 | // Label 2321: @84233 |
| 32829 | GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(84274), // Rule ID 431 // |
| 32830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 32831 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32832 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32833 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32834 | // MIs[0] rs1 |
| 32835 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32837 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32838 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32839 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32840 | GIR_RootConstrainSelectedInstOperands, |
| 32841 | // GIR_Coverage, 431, |
| 32842 | GIR_Done, |
| 32843 | // Label 2322: @84274 |
| 32844 | GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(84315), // Rule ID 730 // |
| 32845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32846 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32847 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32849 | // MIs[0] rs1 |
| 32850 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32851 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32852 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32853 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32854 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32855 | GIR_RootConstrainSelectedInstOperands, |
| 32856 | // GIR_Coverage, 730, |
| 32857 | GIR_Done, |
| 32858 | // Label 2323: @84315 |
| 32859 | GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(84356), // Rule ID 731 // |
| 32860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32861 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32862 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32864 | // MIs[0] rs1 |
| 32865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32866 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32868 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32869 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 32870 | GIR_RootConstrainSelectedInstOperands, |
| 32871 | // GIR_Coverage, 731, |
| 32872 | GIR_Done, |
| 32873 | // Label 2324: @84356 |
| 32874 | GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(84397), // Rule ID 732 // |
| 32875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32876 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32877 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32879 | // MIs[0] rs1 |
| 32880 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32882 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32883 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32884 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ), |
| 32885 | GIR_RootConstrainSelectedInstOperands, |
| 32886 | // GIR_Coverage, 732, |
| 32887 | GIR_Done, |
| 32888 | // Label 2325: @84397 |
| 32889 | GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(84438), // Rule ID 733 // |
| 32890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32891 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32892 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 32893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32894 | // MIs[0] rs1 |
| 32895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32896 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32897 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32898 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32899 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ), |
| 32900 | GIR_RootConstrainSelectedInstOperands, |
| 32901 | // GIR_Coverage, 733, |
| 32902 | GIR_Done, |
| 32903 | // Label 2326: @84438 |
| 32904 | GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(84479), // Rule ID 734 // |
| 32905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32906 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32907 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32909 | // MIs[0] rs1 |
| 32910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32911 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32913 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32914 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_RL), |
| 32915 | GIR_RootConstrainSelectedInstOperands, |
| 32916 | // GIR_Coverage, 734, |
| 32917 | GIR_Done, |
| 32918 | // Label 2327: @84479 |
| 32919 | GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(84520), // Rule ID 735 // |
| 32920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32921 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32922 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 32923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32924 | // MIs[0] rs1 |
| 32925 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32926 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32928 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32929 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_RL), |
| 32930 | GIR_RootConstrainSelectedInstOperands, |
| 32931 | // GIR_Coverage, 735, |
| 32932 | GIR_Done, |
| 32933 | // Label 2328: @84520 |
| 32934 | GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(84561), // Rule ID 736 // |
| 32935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32936 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32937 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32939 | // MIs[0] rs1 |
| 32940 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32941 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32942 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32943 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32944 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 32945 | GIR_RootConstrainSelectedInstOperands, |
| 32946 | // GIR_Coverage, 736, |
| 32947 | GIR_Done, |
| 32948 | // Label 2329: @84561 |
| 32949 | GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(84602), // Rule ID 737 // |
| 32950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32951 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32952 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 32953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32954 | // MIs[0] rs1 |
| 32955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32956 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32957 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32958 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32959 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 32960 | GIR_RootConstrainSelectedInstOperands, |
| 32961 | // GIR_Coverage, 737, |
| 32962 | GIR_Done, |
| 32963 | // Label 2330: @84602 |
| 32964 | GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(84643), // Rule ID 738 // |
| 32965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 32966 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32967 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32969 | // MIs[0] rs1 |
| 32970 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32971 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32972 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32973 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32974 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 32975 | GIR_RootConstrainSelectedInstOperands, |
| 32976 | // GIR_Coverage, 738, |
| 32977 | GIR_Done, |
| 32978 | // Label 2331: @84643 |
| 32979 | GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(84684), // Rule ID 739 // |
| 32980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 32981 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32982 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 32983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32984 | // MIs[0] rs1 |
| 32985 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 32986 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32988 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 32989 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 32990 | GIR_RootConstrainSelectedInstOperands, |
| 32991 | // GIR_Coverage, 739, |
| 32992 | GIR_Done, |
| 32993 | // Label 2332: @84684 |
| 32994 | GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(84725), // Rule ID 740 // |
| 32995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 32996 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 32997 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 32998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 32999 | // MIs[0] rs1 |
| 33000 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33002 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33003 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33004 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33005 | GIR_RootConstrainSelectedInstOperands, |
| 33006 | // GIR_Coverage, 740, |
| 33007 | GIR_Done, |
| 33008 | // Label 2333: @84725 |
| 33009 | GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(84766), // Rule ID 741 // |
| 33010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 33011 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33012 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33014 | // MIs[0] rs1 |
| 33015 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33017 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33018 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33019 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33020 | GIR_RootConstrainSelectedInstOperands, |
| 33021 | // GIR_Coverage, 741, |
| 33022 | GIR_Done, |
| 33023 | // Label 2334: @84766 |
| 33024 | GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(84807), // Rule ID 742 // |
| 33025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33026 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33027 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33029 | // MIs[0] rs1 |
| 33030 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33033 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33034 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33035 | GIR_RootConstrainSelectedInstOperands, |
| 33036 | // GIR_Coverage, 742, |
| 33037 | GIR_Done, |
| 33038 | // Label 2335: @84807 |
| 33039 | GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(84848), // Rule ID 743 // |
| 33040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 33041 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33042 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33044 | // MIs[0] rs1 |
| 33045 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33046 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33047 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33048 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33049 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33050 | GIR_RootConstrainSelectedInstOperands, |
| 33051 | // GIR_Coverage, 743, |
| 33052 | GIR_Done, |
| 33053 | // Label 2336: @84848 |
| 33054 | GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(84889), // Rule ID 744 // |
| 33055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33056 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33057 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33059 | // MIs[0] rs1 |
| 33060 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33061 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33062 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33063 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33064 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33065 | GIR_RootConstrainSelectedInstOperands, |
| 33066 | // GIR_Coverage, 744, |
| 33067 | GIR_Done, |
| 33068 | // Label 2337: @84889 |
| 33069 | GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(84930), // Rule ID 745 // |
| 33070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 33071 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33072 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33074 | // MIs[0] rs1 |
| 33075 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33076 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33077 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33078 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33079 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33080 | GIR_RootConstrainSelectedInstOperands, |
| 33081 | // GIR_Coverage, 745, |
| 33082 | GIR_Done, |
| 33083 | // Label 2338: @84930 |
| 33084 | GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(84971), // Rule ID 746 // |
| 33085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33086 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33087 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33089 | // MIs[0] rs1 |
| 33090 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33091 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33092 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33093 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33094 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33095 | GIR_RootConstrainSelectedInstOperands, |
| 33096 | // GIR_Coverage, 746, |
| 33097 | GIR_Done, |
| 33098 | // Label 2339: @84971 |
| 33099 | GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(85012), // Rule ID 747 // |
| 33100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 33101 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33102 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33104 | // MIs[0] rs1 |
| 33105 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33107 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33108 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33109 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33110 | GIR_RootConstrainSelectedInstOperands, |
| 33111 | // GIR_Coverage, 747, |
| 33112 | GIR_Done, |
| 33113 | // Label 2340: @85012 |
| 33114 | GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(85053), // Rule ID 748 // |
| 33115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33116 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33117 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33119 | // MIs[0] rs1 |
| 33120 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33122 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33123 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33124 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33125 | GIR_RootConstrainSelectedInstOperands, |
| 33126 | // GIR_Coverage, 748, |
| 33127 | GIR_Done, |
| 33128 | // Label 2341: @85053 |
| 33129 | GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(85094), // Rule ID 749 // |
| 33130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 33131 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33132 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33134 | // MIs[0] rs1 |
| 33135 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33136 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33137 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33138 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33139 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33140 | GIR_RootConstrainSelectedInstOperands, |
| 33141 | // GIR_Coverage, 749, |
| 33142 | GIR_Done, |
| 33143 | // Label 2342: @85094 |
| 33144 | GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(85135), // Rule ID 963 // |
| 33145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33146 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33147 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33149 | // MIs[0] rs1 |
| 33150 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33151 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33152 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33153 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>> => (AMOAND_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33154 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33155 | GIR_RootConstrainSelectedInstOperands, |
| 33156 | // GIR_Coverage, 963, |
| 33157 | GIR_Done, |
| 33158 | // Label 2343: @85135 |
| 33159 | GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(85176), // Rule ID 965 // |
| 33160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33161 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33162 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33164 | // MIs[0] rs1 |
| 33165 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33167 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33168 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>> => (AMOAND_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33169 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_AQ), |
| 33170 | GIR_RootConstrainSelectedInstOperands, |
| 33171 | // GIR_Coverage, 965, |
| 33172 | GIR_Done, |
| 33173 | // Label 2344: @85176 |
| 33174 | GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(85217), // Rule ID 967 // |
| 33175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33176 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33177 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33179 | // MIs[0] rs1 |
| 33180 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33181 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33182 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33183 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>> => (AMOAND_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33184 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_RL), |
| 33185 | GIR_RootConstrainSelectedInstOperands, |
| 33186 | // GIR_Coverage, 967, |
| 33187 | GIR_Done, |
| 33188 | // Label 2345: @85217 |
| 33189 | GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(85258), // Rule ID 969 // |
| 33190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33191 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33192 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33193 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33194 | // MIs[0] rs1 |
| 33195 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33196 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33197 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33198 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>> => (AMOAND_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33199 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_AQ_RL), |
| 33200 | GIR_RootConstrainSelectedInstOperands, |
| 33201 | // GIR_Coverage, 969, |
| 33202 | GIR_Done, |
| 33203 | // Label 2346: @85258 |
| 33204 | GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(85299), // Rule ID 971 // |
| 33205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33206 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33207 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33209 | // MIs[0] rs1 |
| 33210 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33211 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33212 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33213 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>> => (AMOAND_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33214 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_AQ_RL), |
| 33215 | GIR_RootConstrainSelectedInstOperands, |
| 33216 | // GIR_Coverage, 971, |
| 33217 | GIR_Done, |
| 33218 | // Label 2347: @85299 |
| 33219 | GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(85340), // Rule ID 973 // |
| 33220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33221 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33222 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33224 | // MIs[0] rs1 |
| 33225 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33226 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33227 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33228 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>> => (AMOAND_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33229 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33230 | GIR_RootConstrainSelectedInstOperands, |
| 33231 | // GIR_Coverage, 973, |
| 33232 | GIR_Done, |
| 33233 | // Label 2348: @85340 |
| 33234 | GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(85381), // Rule ID 975 // |
| 33235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33236 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33237 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33239 | // MIs[0] rs1 |
| 33240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33241 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33242 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33243 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>> => (AMOAND_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33244 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33245 | GIR_RootConstrainSelectedInstOperands, |
| 33246 | // GIR_Coverage, 975, |
| 33247 | GIR_Done, |
| 33248 | // Label 2349: @85381 |
| 33249 | GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(85422), // Rule ID 977 // |
| 33250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33251 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33252 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33254 | // MIs[0] rs1 |
| 33255 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33258 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>> => (AMOAND_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33259 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33260 | GIR_RootConstrainSelectedInstOperands, |
| 33261 | // GIR_Coverage, 977, |
| 33262 | GIR_Done, |
| 33263 | // Label 2350: @85422 |
| 33264 | GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(85463), // Rule ID 979 // |
| 33265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33266 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33267 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33269 | // MIs[0] rs1 |
| 33270 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33271 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33272 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33273 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>> => (AMOAND_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33274 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33275 | GIR_RootConstrainSelectedInstOperands, |
| 33276 | // GIR_Coverage, 979, |
| 33277 | GIR_Done, |
| 33278 | // Label 2351: @85463 |
| 33279 | GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(85504), // Rule ID 981 // |
| 33280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33281 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33282 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33284 | // MIs[0] rs1 |
| 33285 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33288 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>> => (AMOAND_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33289 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33290 | GIR_RootConstrainSelectedInstOperands, |
| 33291 | // GIR_Coverage, 981, |
| 33292 | GIR_Done, |
| 33293 | // Label 2352: @85504 |
| 33294 | GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(85545), // Rule ID 1143 // |
| 33295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33296 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33297 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33299 | // MIs[0] rs1 |
| 33300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33301 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33302 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33303 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>> => (AMOAND_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33304 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33305 | GIR_RootConstrainSelectedInstOperands, |
| 33306 | // GIR_Coverage, 1143, |
| 33307 | GIR_Done, |
| 33308 | // Label 2353: @85545 |
| 33309 | GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(85586), // Rule ID 1145 // |
| 33310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33311 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33312 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33314 | // MIs[0] rs1 |
| 33315 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33316 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33318 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>> => (AMOAND_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33319 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_AQ), |
| 33320 | GIR_RootConstrainSelectedInstOperands, |
| 33321 | // GIR_Coverage, 1145, |
| 33322 | GIR_Done, |
| 33323 | // Label 2354: @85586 |
| 33324 | GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(85627), // Rule ID 1147 // |
| 33325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33326 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33327 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33329 | // MIs[0] rs1 |
| 33330 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33332 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33333 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>> => (AMOAND_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33334 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_RL), |
| 33335 | GIR_RootConstrainSelectedInstOperands, |
| 33336 | // GIR_Coverage, 1147, |
| 33337 | GIR_Done, |
| 33338 | // Label 2355: @85627 |
| 33339 | GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(85668), // Rule ID 1149 // |
| 33340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33341 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33344 | // MIs[0] rs1 |
| 33345 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33346 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33348 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>> => (AMOAND_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33349 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_AQ_RL), |
| 33350 | GIR_RootConstrainSelectedInstOperands, |
| 33351 | // GIR_Coverage, 1149, |
| 33352 | GIR_Done, |
| 33353 | // Label 2356: @85668 |
| 33354 | GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(85709), // Rule ID 1151 // |
| 33355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 33356 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33357 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33359 | // MIs[0] rs1 |
| 33360 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33361 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33362 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33363 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>> => (AMOAND_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33364 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_AQ_RL), |
| 33365 | GIR_RootConstrainSelectedInstOperands, |
| 33366 | // GIR_Coverage, 1151, |
| 33367 | GIR_Done, |
| 33368 | // Label 2357: @85709 |
| 33369 | GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(85750), // Rule ID 1153 // |
| 33370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33371 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33372 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33374 | // MIs[0] rs1 |
| 33375 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33378 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>> => (AMOAND_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33380 | GIR_RootConstrainSelectedInstOperands, |
| 33381 | // GIR_Coverage, 1153, |
| 33382 | GIR_Done, |
| 33383 | // Label 2358: @85750 |
| 33384 | GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(85791), // Rule ID 1155 // |
| 33385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33386 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33387 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33389 | // MIs[0] rs1 |
| 33390 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33391 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33392 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33393 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>> => (AMOAND_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33394 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33395 | GIR_RootConstrainSelectedInstOperands, |
| 33396 | // GIR_Coverage, 1155, |
| 33397 | GIR_Done, |
| 33398 | // Label 2359: @85791 |
| 33399 | GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(85832), // Rule ID 1157 // |
| 33400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33401 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33402 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33404 | // MIs[0] rs1 |
| 33405 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33408 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>> => (AMOAND_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33409 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33410 | GIR_RootConstrainSelectedInstOperands, |
| 33411 | // GIR_Coverage, 1157, |
| 33412 | GIR_Done, |
| 33413 | // Label 2360: @85832 |
| 33414 | GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(85873), // Rule ID 1159 // |
| 33415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33416 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33419 | // MIs[0] rs1 |
| 33420 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33422 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33423 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>> => (AMOAND_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33424 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33425 | GIR_RootConstrainSelectedInstOperands, |
| 33426 | // GIR_Coverage, 1159, |
| 33427 | GIR_Done, |
| 33428 | // Label 2361: @85873 |
| 33429 | GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(85914), // Rule ID 1161 // |
| 33430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 33431 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33432 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33434 | // MIs[0] rs1 |
| 33435 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33436 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33437 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33438 | // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>> => (AMOAND_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 33439 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33440 | GIR_RootConstrainSelectedInstOperands, |
| 33441 | // GIR_Coverage, 1161, |
| 33442 | GIR_Done, |
| 33443 | // Label 2362: @85914 |
| 33444 | GIM_Reject, |
| 33445 | // Label 2312: @85915 |
| 33446 | GIM_Reject, |
| 33447 | // Label 2310: @85916 |
| 33448 | GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(87565), |
| 33449 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 33450 | GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(85965), // Rule ID 412 // |
| 33451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 33452 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33453 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33455 | // MIs[0] rs1 |
| 33456 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33458 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33459 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33460 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33461 | GIR_RootConstrainSelectedInstOperands, |
| 33462 | // GIR_Coverage, 412, |
| 33463 | GIR_Done, |
| 33464 | // Label 2364: @85965 |
| 33465 | GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(86006), // Rule ID 414 // |
| 33466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 33467 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33468 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33470 | // MIs[0] rs1 |
| 33471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33472 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33474 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33475 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ), |
| 33476 | GIR_RootConstrainSelectedInstOperands, |
| 33477 | // GIR_Coverage, 414, |
| 33478 | GIR_Done, |
| 33479 | // Label 2365: @86006 |
| 33480 | GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(86047), // Rule ID 416 // |
| 33481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 33482 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33483 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33485 | // MIs[0] rs1 |
| 33486 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33487 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33488 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33489 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33490 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_RL), |
| 33491 | GIR_RootConstrainSelectedInstOperands, |
| 33492 | // GIR_Coverage, 416, |
| 33493 | GIR_Done, |
| 33494 | // Label 2366: @86047 |
| 33495 | GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(86088), // Rule ID 418 // |
| 33496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 33497 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33498 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33500 | // MIs[0] rs1 |
| 33501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33504 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33505 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 33506 | GIR_RootConstrainSelectedInstOperands, |
| 33507 | // GIR_Coverage, 418, |
| 33508 | GIR_Done, |
| 33509 | // Label 2367: @86088 |
| 33510 | GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(86129), // Rule ID 420 // |
| 33511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 33512 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33513 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33515 | // MIs[0] rs1 |
| 33516 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33517 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33518 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33519 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33520 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W_AQ_RL), |
| 33521 | GIR_RootConstrainSelectedInstOperands, |
| 33522 | // GIR_Coverage, 420, |
| 33523 | GIR_Done, |
| 33524 | // Label 2368: @86129 |
| 33525 | GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(86170), // Rule ID 422 // |
| 33526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33527 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33530 | // MIs[0] rs1 |
| 33531 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33532 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33533 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33534 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33535 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33536 | GIR_RootConstrainSelectedInstOperands, |
| 33537 | // GIR_Coverage, 422, |
| 33538 | GIR_Done, |
| 33539 | // Label 2369: @86170 |
| 33540 | GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(86211), // Rule ID 424 // |
| 33541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33542 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33543 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33545 | // MIs[0] rs1 |
| 33546 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33547 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33548 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33549 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33550 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33551 | GIR_RootConstrainSelectedInstOperands, |
| 33552 | // GIR_Coverage, 424, |
| 33553 | GIR_Done, |
| 33554 | // Label 2370: @86211 |
| 33555 | GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(86252), // Rule ID 426 // |
| 33556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33557 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33558 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33560 | // MIs[0] rs1 |
| 33561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33562 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33563 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33564 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33565 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33566 | GIR_RootConstrainSelectedInstOperands, |
| 33567 | // GIR_Coverage, 426, |
| 33568 | GIR_Done, |
| 33569 | // Label 2371: @86252 |
| 33570 | GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(86293), // Rule ID 428 // |
| 33571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33572 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33573 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33575 | // MIs[0] rs1 |
| 33576 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33577 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33578 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33579 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33580 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33581 | GIR_RootConstrainSelectedInstOperands, |
| 33582 | // GIR_Coverage, 428, |
| 33583 | GIR_Done, |
| 33584 | // Label 2372: @86293 |
| 33585 | GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(86334), // Rule ID 430 // |
| 33586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 33587 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 33588 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33590 | // MIs[0] rs1 |
| 33591 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33592 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33594 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33595 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_W), |
| 33596 | GIR_RootConstrainSelectedInstOperands, |
| 33597 | // GIR_Coverage, 430, |
| 33598 | GIR_Done, |
| 33599 | // Label 2373: @86334 |
| 33600 | GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(86375), // Rule ID 572 // |
| 33601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 33602 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33603 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33605 | // MIs[0] rs1 |
| 33606 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33607 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33608 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33609 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_monotonic>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33610 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D), |
| 33611 | GIR_RootConstrainSelectedInstOperands, |
| 33612 | // GIR_Coverage, 572, |
| 33613 | GIR_Done, |
| 33614 | // Label 2374: @86375 |
| 33615 | GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(86416), // Rule ID 573 // |
| 33616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 33617 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33618 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33620 | // MIs[0] rs1 |
| 33621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33622 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33623 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33624 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acquire>> => (AMOAND_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33625 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D_AQ), |
| 33626 | GIR_RootConstrainSelectedInstOperands, |
| 33627 | // GIR_Coverage, 573, |
| 33628 | GIR_Done, |
| 33629 | // Label 2375: @86416 |
| 33630 | GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(86457), // Rule ID 574 // |
| 33631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 33632 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33633 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33635 | // MIs[0] rs1 |
| 33636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33637 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33638 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33639 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_release>> => (AMOAND_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33640 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D_RL), |
| 33641 | GIR_RootConstrainSelectedInstOperands, |
| 33642 | // GIR_Coverage, 574, |
| 33643 | GIR_Done, |
| 33644 | // Label 2376: @86457 |
| 33645 | GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(86498), // Rule ID 575 // |
| 33646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 33647 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33648 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33650 | // MIs[0] rs1 |
| 33651 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33652 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33653 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33654 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33655 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D_AQ_RL), |
| 33656 | GIR_RootConstrainSelectedInstOperands, |
| 33657 | // GIR_Coverage, 575, |
| 33658 | GIR_Done, |
| 33659 | // Label 2377: @86498 |
| 33660 | GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(86539), // Rule ID 576 // |
| 33661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 33662 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33663 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33665 | // MIs[0] rs1 |
| 33666 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33667 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33668 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33669 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33670 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D_AQ_RL), |
| 33671 | GIR_RootConstrainSelectedInstOperands, |
| 33672 | // GIR_Coverage, 576, |
| 33673 | GIR_Done, |
| 33674 | // Label 2378: @86539 |
| 33675 | GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(86580), // Rule ID 577 // |
| 33676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 33677 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33678 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33680 | // MIs[0] rs1 |
| 33681 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33682 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33684 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_monotonic>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33685 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D), |
| 33686 | GIR_RootConstrainSelectedInstOperands, |
| 33687 | // GIR_Coverage, 577, |
| 33688 | GIR_Done, |
| 33689 | // Label 2379: @86580 |
| 33690 | GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(86621), // Rule ID 578 // |
| 33691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 33692 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33693 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33695 | // MIs[0] rs1 |
| 33696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33697 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33698 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33699 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acquire>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33700 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D), |
| 33701 | GIR_RootConstrainSelectedInstOperands, |
| 33702 | // GIR_Coverage, 578, |
| 33703 | GIR_Done, |
| 33704 | // Label 2380: @86621 |
| 33705 | GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(86662), // Rule ID 579 // |
| 33706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 33707 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33708 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33710 | // MIs[0] rs1 |
| 33711 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33714 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_release>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33715 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D), |
| 33716 | GIR_RootConstrainSelectedInstOperands, |
| 33717 | // GIR_Coverage, 579, |
| 33718 | GIR_Done, |
| 33719 | // Label 2381: @86662 |
| 33720 | GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(86703), // Rule ID 580 // |
| 33721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 33722 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33723 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33725 | // MIs[0] rs1 |
| 33726 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33727 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33728 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33729 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acq_rel>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33730 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D), |
| 33731 | GIR_RootConstrainSelectedInstOperands, |
| 33732 | // GIR_Coverage, 580, |
| 33733 | GIR_Done, |
| 33734 | // Label 2382: @86703 |
| 33735 | GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(86744), // Rule ID 581 // |
| 33736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 33737 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 33738 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33740 | // MIs[0] rs1 |
| 33741 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33742 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33743 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33744 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_seq_cst>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33745 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_D), |
| 33746 | GIR_RootConstrainSelectedInstOperands, |
| 33747 | // GIR_Coverage, 581, |
| 33748 | GIR_Done, |
| 33749 | // Label 2383: @86744 |
| 33750 | GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(86785), // Rule ID 962 // |
| 33751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33752 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33753 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33755 | // MIs[0] rs1 |
| 33756 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33757 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33758 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33759 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>> => (AMOAND_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33760 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33761 | GIR_RootConstrainSelectedInstOperands, |
| 33762 | // GIR_Coverage, 962, |
| 33763 | GIR_Done, |
| 33764 | // Label 2384: @86785 |
| 33765 | GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(86826), // Rule ID 964 // |
| 33766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33767 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33768 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33770 | // MIs[0] rs1 |
| 33771 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33772 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33774 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>> => (AMOAND_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33775 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_AQ), |
| 33776 | GIR_RootConstrainSelectedInstOperands, |
| 33777 | // GIR_Coverage, 964, |
| 33778 | GIR_Done, |
| 33779 | // Label 2385: @86826 |
| 33780 | GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(86867), // Rule ID 966 // |
| 33781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33782 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33783 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33785 | // MIs[0] rs1 |
| 33786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33787 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33788 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33789 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>> => (AMOAND_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33790 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_RL), |
| 33791 | GIR_RootConstrainSelectedInstOperands, |
| 33792 | // GIR_Coverage, 966, |
| 33793 | GIR_Done, |
| 33794 | // Label 2386: @86867 |
| 33795 | GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(86908), // Rule ID 968 // |
| 33796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33797 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33798 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33800 | // MIs[0] rs1 |
| 33801 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33802 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33804 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>> => (AMOAND_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33805 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_AQ_RL), |
| 33806 | GIR_RootConstrainSelectedInstOperands, |
| 33807 | // GIR_Coverage, 968, |
| 33808 | GIR_Done, |
| 33809 | // Label 2387: @86908 |
| 33810 | GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(86949), // Rule ID 970 // |
| 33811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33812 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33813 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33815 | // MIs[0] rs1 |
| 33816 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33817 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33818 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33819 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>> => (AMOAND_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33820 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B_AQ_RL), |
| 33821 | GIR_RootConstrainSelectedInstOperands, |
| 33822 | // GIR_Coverage, 970, |
| 33823 | GIR_Done, |
| 33824 | // Label 2388: @86949 |
| 33825 | GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(86990), // Rule ID 972 // |
| 33826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33827 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33830 | // MIs[0] rs1 |
| 33831 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33832 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33833 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33834 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>> => (AMOAND_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33835 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33836 | GIR_RootConstrainSelectedInstOperands, |
| 33837 | // GIR_Coverage, 972, |
| 33838 | GIR_Done, |
| 33839 | // Label 2389: @86990 |
| 33840 | GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(87031), // Rule ID 974 // |
| 33841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33842 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33843 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33845 | // MIs[0] rs1 |
| 33846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33847 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33848 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33849 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>> => (AMOAND_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33850 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33851 | GIR_RootConstrainSelectedInstOperands, |
| 33852 | // GIR_Coverage, 974, |
| 33853 | GIR_Done, |
| 33854 | // Label 2390: @87031 |
| 33855 | GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(87072), // Rule ID 976 // |
| 33856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33857 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33858 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33860 | // MIs[0] rs1 |
| 33861 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33862 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33863 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33864 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>> => (AMOAND_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33865 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33866 | GIR_RootConstrainSelectedInstOperands, |
| 33867 | // GIR_Coverage, 976, |
| 33868 | GIR_Done, |
| 33869 | // Label 2391: @87072 |
| 33870 | GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(87113), // Rule ID 978 // |
| 33871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33872 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33873 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33875 | // MIs[0] rs1 |
| 33876 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33877 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33878 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33879 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>> => (AMOAND_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33881 | GIR_RootConstrainSelectedInstOperands, |
| 33882 | // GIR_Coverage, 978, |
| 33883 | GIR_Done, |
| 33884 | // Label 2392: @87113 |
| 33885 | GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(87154), // Rule ID 980 // |
| 33886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33887 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 33888 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33890 | // MIs[0] rs1 |
| 33891 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33892 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33893 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33894 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>> => (AMOAND_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33895 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_B), |
| 33896 | GIR_RootConstrainSelectedInstOperands, |
| 33897 | // GIR_Coverage, 980, |
| 33898 | GIR_Done, |
| 33899 | // Label 2393: @87154 |
| 33900 | GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(87195), // Rule ID 1142 // |
| 33901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33902 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33903 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33905 | // MIs[0] rs1 |
| 33906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33907 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33908 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33909 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>> => (AMOAND_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33910 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33911 | GIR_RootConstrainSelectedInstOperands, |
| 33912 | // GIR_Coverage, 1142, |
| 33913 | GIR_Done, |
| 33914 | // Label 2394: @87195 |
| 33915 | GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(87236), // Rule ID 1144 // |
| 33916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33917 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33918 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33920 | // MIs[0] rs1 |
| 33921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33924 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>> => (AMOAND_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33925 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_AQ), |
| 33926 | GIR_RootConstrainSelectedInstOperands, |
| 33927 | // GIR_Coverage, 1144, |
| 33928 | GIR_Done, |
| 33929 | // Label 2395: @87236 |
| 33930 | GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(87277), // Rule ID 1146 // |
| 33931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33932 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33933 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 33934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33935 | // MIs[0] rs1 |
| 33936 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33937 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33938 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33939 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>> => (AMOAND_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33940 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_RL), |
| 33941 | GIR_RootConstrainSelectedInstOperands, |
| 33942 | // GIR_Coverage, 1146, |
| 33943 | GIR_Done, |
| 33944 | // Label 2396: @87277 |
| 33945 | GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(87318), // Rule ID 1148 // |
| 33946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33947 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33948 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 33949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33950 | // MIs[0] rs1 |
| 33951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33952 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33953 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33954 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>> => (AMOAND_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33955 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_AQ_RL), |
| 33956 | GIR_RootConstrainSelectedInstOperands, |
| 33957 | // GIR_Coverage, 1148, |
| 33958 | GIR_Done, |
| 33959 | // Label 2397: @87318 |
| 33960 | GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(87359), // Rule ID 1150 // |
| 33961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 33962 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33963 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 33964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33965 | // MIs[0] rs1 |
| 33966 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33967 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33968 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33969 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>> => (AMOAND_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33970 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H_AQ_RL), |
| 33971 | GIR_RootConstrainSelectedInstOperands, |
| 33972 | // GIR_Coverage, 1150, |
| 33973 | GIR_Done, |
| 33974 | // Label 2398: @87359 |
| 33975 | GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(87400), // Rule ID 1152 // |
| 33976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33977 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33978 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 33979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33980 | // MIs[0] rs1 |
| 33981 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33983 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33984 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>> => (AMOAND_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 33985 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 33986 | GIR_RootConstrainSelectedInstOperands, |
| 33987 | // GIR_Coverage, 1152, |
| 33988 | GIR_Done, |
| 33989 | // Label 2399: @87400 |
| 33990 | GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(87441), // Rule ID 1154 // |
| 33991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 33992 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 33993 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 33994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33995 | // MIs[0] rs1 |
| 33996 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33997 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33998 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 33999 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>> => (AMOAND_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34000 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 34001 | GIR_RootConstrainSelectedInstOperands, |
| 34002 | // GIR_Coverage, 1154, |
| 34003 | GIR_Done, |
| 34004 | // Label 2400: @87441 |
| 34005 | GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(87482), // Rule ID 1156 // |
| 34006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 34007 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34008 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34010 | // MIs[0] rs1 |
| 34011 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34012 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34014 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>> => (AMOAND_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34015 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 34016 | GIR_RootConstrainSelectedInstOperands, |
| 34017 | // GIR_Coverage, 1156, |
| 34018 | GIR_Done, |
| 34019 | // Label 2401: @87482 |
| 34020 | GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(87523), // Rule ID 1158 // |
| 34021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 34022 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34023 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34025 | // MIs[0] rs1 |
| 34026 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34027 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34028 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34029 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>> => (AMOAND_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34030 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 34031 | GIR_RootConstrainSelectedInstOperands, |
| 34032 | // GIR_Coverage, 1158, |
| 34033 | GIR_Done, |
| 34034 | // Label 2402: @87523 |
| 34035 | GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(87564), // Rule ID 1160 // |
| 34036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 34037 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34038 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34040 | // MIs[0] rs1 |
| 34041 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34042 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34044 | // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>> => (AMOAND_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34045 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOAND_H), |
| 34046 | GIR_RootConstrainSelectedInstOperands, |
| 34047 | // GIR_Coverage, 1160, |
| 34048 | GIR_Done, |
| 34049 | // Label 2403: @87564 |
| 34050 | GIM_Reject, |
| 34051 | // Label 2363: @87565 |
| 34052 | GIM_Reject, |
| 34053 | // Label 2311: @87566 |
| 34054 | GIM_Reject, |
| 34055 | // Label 26: @87567 |
| 34056 | GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(87851), |
| 34057 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 34058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 34059 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34060 | GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(87638), // Rule ID 643 // |
| 34061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 34062 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34064 | // MIs[0] addr |
| 34065 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34066 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34067 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34068 | // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>><<P:Predicate_atomic_load_nand_i32_monotonic>> => (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 2:{ *:[i32] }) |
| 34069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 34070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoAtomicLoadNand32), |
| 34071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 34072 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 34073 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 34074 | GIR_RootToRootCopy, /*OpIdx*/2, // incr |
| 34075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 34076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34077 | GIR_RootConstrainSelectedInstOperands, |
| 34078 | // GIR_Coverage, 643, |
| 34079 | GIR_EraseRootFromParent_Done, |
| 34080 | // Label 2405: @87638 |
| 34081 | GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(87691), // Rule ID 645 // |
| 34082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 34083 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34085 | // MIs[0] addr |
| 34086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34087 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34088 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34089 | // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>><<P:Predicate_atomic_load_nand_i32_acquire>> => (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 4:{ *:[i32] }) |
| 34090 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 34091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoAtomicLoadNand32), |
| 34092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 34093 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 34094 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 34095 | GIR_RootToRootCopy, /*OpIdx*/2, // incr |
| 34096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 34097 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34098 | GIR_RootConstrainSelectedInstOperands, |
| 34099 | // GIR_Coverage, 645, |
| 34100 | GIR_EraseRootFromParent_Done, |
| 34101 | // Label 2406: @87691 |
| 34102 | GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(87744), // Rule ID 647 // |
| 34103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 34104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34106 | // MIs[0] addr |
| 34107 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34110 | // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>><<P:Predicate_atomic_load_nand_i32_release>> => (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 5:{ *:[i32] }) |
| 34111 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 34112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoAtomicLoadNand32), |
| 34113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 34114 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 34115 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 34116 | GIR_RootToRootCopy, /*OpIdx*/2, // incr |
| 34117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 34118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34119 | GIR_RootConstrainSelectedInstOperands, |
| 34120 | // GIR_Coverage, 647, |
| 34121 | GIR_EraseRootFromParent_Done, |
| 34122 | // Label 2407: @87744 |
| 34123 | GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(87797), // Rule ID 649 // |
| 34124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 34125 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34127 | // MIs[0] addr |
| 34128 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34129 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34130 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34131 | // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>><<P:Predicate_atomic_load_nand_i32_acq_rel>> => (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 6:{ *:[i32] }) |
| 34132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 34133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoAtomicLoadNand32), |
| 34134 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 34135 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 34136 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 34137 | GIR_RootToRootCopy, /*OpIdx*/2, // incr |
| 34138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 34139 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34140 | GIR_RootConstrainSelectedInstOperands, |
| 34141 | // GIR_Coverage, 649, |
| 34142 | GIR_EraseRootFromParent_Done, |
| 34143 | // Label 2408: @87797 |
| 34144 | GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(87850), // Rule ID 651 // |
| 34145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 34146 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34148 | // MIs[0] addr |
| 34149 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34151 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34152 | // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>><<P:Predicate_atomic_load_nand_i32_seq_cst>> => (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 7:{ *:[i32] }) |
| 34153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 34154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoAtomicLoadNand32), |
| 34155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 34156 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 34157 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 34158 | GIR_RootToRootCopy, /*OpIdx*/2, // incr |
| 34159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 34160 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34161 | GIR_RootConstrainSelectedInstOperands, |
| 34162 | // GIR_Coverage, 651, |
| 34163 | GIR_EraseRootFromParent_Done, |
| 34164 | // Label 2409: @87850 |
| 34165 | GIM_Reject, |
| 34166 | // Label 2404: @87851 |
| 34167 | GIM_Reject, |
| 34168 | // Label 27: @87852 |
| 34169 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2412*/ GIMT_Encode4(91581), |
| 34170 | /*GILLT_s32*//*Label 2410*/ GIMT_Encode4(87871), |
| 34171 | /*GILLT_s64*//*Label 2411*/ GIMT_Encode4(89931), |
| 34172 | // Label 2410: @87871 |
| 34173 | GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(89930), |
| 34174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 34175 | GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(87920), // Rule ID 433 // |
| 34176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34177 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34178 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34180 | // MIs[0] rs1 |
| 34181 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34182 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34183 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34184 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34185 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34186 | GIR_RootConstrainSelectedInstOperands, |
| 34187 | // GIR_Coverage, 433, |
| 34188 | GIR_Done, |
| 34189 | // Label 2414: @87920 |
| 34190 | GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(87961), // Rule ID 435 // |
| 34191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34192 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34193 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34195 | // MIs[0] rs1 |
| 34196 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34198 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34199 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34200 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ), |
| 34201 | GIR_RootConstrainSelectedInstOperands, |
| 34202 | // GIR_Coverage, 435, |
| 34203 | GIR_Done, |
| 34204 | // Label 2415: @87961 |
| 34205 | GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(88002), // Rule ID 437 // |
| 34206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34207 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34208 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34210 | // MIs[0] rs1 |
| 34211 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34213 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34214 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34215 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_RL), |
| 34216 | GIR_RootConstrainSelectedInstOperands, |
| 34217 | // GIR_Coverage, 437, |
| 34218 | GIR_Done, |
| 34219 | // Label 2416: @88002 |
| 34220 | GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(88043), // Rule ID 439 // |
| 34221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34222 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34223 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34225 | // MIs[0] rs1 |
| 34226 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34227 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34228 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34229 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34230 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34231 | GIR_RootConstrainSelectedInstOperands, |
| 34232 | // GIR_Coverage, 439, |
| 34233 | GIR_Done, |
| 34234 | // Label 2417: @88043 |
| 34235 | GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(88084), // Rule ID 441 // |
| 34236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34237 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34238 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34240 | // MIs[0] rs1 |
| 34241 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34242 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34243 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34244 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34245 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34246 | GIR_RootConstrainSelectedInstOperands, |
| 34247 | // GIR_Coverage, 441, |
| 34248 | GIR_Done, |
| 34249 | // Label 2418: @88084 |
| 34250 | GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(88125), // Rule ID 443 // |
| 34251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34252 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34253 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34255 | // MIs[0] rs1 |
| 34256 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34257 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34258 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34259 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34260 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34261 | GIR_RootConstrainSelectedInstOperands, |
| 34262 | // GIR_Coverage, 443, |
| 34263 | GIR_Done, |
| 34264 | // Label 2419: @88125 |
| 34265 | GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(88166), // Rule ID 445 // |
| 34266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34267 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34268 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34269 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34270 | // MIs[0] rs1 |
| 34271 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34274 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34275 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34276 | GIR_RootConstrainSelectedInstOperands, |
| 34277 | // GIR_Coverage, 445, |
| 34278 | GIR_Done, |
| 34279 | // Label 2420: @88166 |
| 34280 | GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(88207), // Rule ID 447 // |
| 34281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34282 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34283 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34285 | // MIs[0] rs1 |
| 34286 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34287 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34288 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34289 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34290 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34291 | GIR_RootConstrainSelectedInstOperands, |
| 34292 | // GIR_Coverage, 447, |
| 34293 | GIR_Done, |
| 34294 | // Label 2421: @88207 |
| 34295 | GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(88248), // Rule ID 449 // |
| 34296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34297 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34298 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34300 | // MIs[0] rs1 |
| 34301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34303 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34304 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34305 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34306 | GIR_RootConstrainSelectedInstOperands, |
| 34307 | // GIR_Coverage, 449, |
| 34308 | GIR_Done, |
| 34309 | // Label 2422: @88248 |
| 34310 | GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(88289), // Rule ID 451 // |
| 34311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34312 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34313 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34315 | // MIs[0] rs1 |
| 34316 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34319 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34320 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34321 | GIR_RootConstrainSelectedInstOperands, |
| 34322 | // GIR_Coverage, 451, |
| 34323 | GIR_Done, |
| 34324 | // Label 2423: @88289 |
| 34325 | GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(88330), // Rule ID 750 // |
| 34326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34327 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34328 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34330 | // MIs[0] rs1 |
| 34331 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34332 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34333 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34334 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34335 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34336 | GIR_RootConstrainSelectedInstOperands, |
| 34337 | // GIR_Coverage, 750, |
| 34338 | GIR_Done, |
| 34339 | // Label 2424: @88330 |
| 34340 | GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(88371), // Rule ID 751 // |
| 34341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34342 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34343 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34345 | // MIs[0] rs1 |
| 34346 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34347 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34348 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34349 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34350 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34351 | GIR_RootConstrainSelectedInstOperands, |
| 34352 | // GIR_Coverage, 751, |
| 34353 | GIR_Done, |
| 34354 | // Label 2425: @88371 |
| 34355 | GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(88412), // Rule ID 752 // |
| 34356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34357 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34358 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34360 | // MIs[0] rs1 |
| 34361 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34362 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34363 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34364 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34365 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ), |
| 34366 | GIR_RootConstrainSelectedInstOperands, |
| 34367 | // GIR_Coverage, 752, |
| 34368 | GIR_Done, |
| 34369 | // Label 2426: @88412 |
| 34370 | GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(88453), // Rule ID 753 // |
| 34371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34372 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34373 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34375 | // MIs[0] rs1 |
| 34376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34377 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34378 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34379 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34380 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ), |
| 34381 | GIR_RootConstrainSelectedInstOperands, |
| 34382 | // GIR_Coverage, 753, |
| 34383 | GIR_Done, |
| 34384 | // Label 2427: @88453 |
| 34385 | GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(88494), // Rule ID 754 // |
| 34386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34387 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34388 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34390 | // MIs[0] rs1 |
| 34391 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34394 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34395 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_RL), |
| 34396 | GIR_RootConstrainSelectedInstOperands, |
| 34397 | // GIR_Coverage, 754, |
| 34398 | GIR_Done, |
| 34399 | // Label 2428: @88494 |
| 34400 | GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(88535), // Rule ID 755 // |
| 34401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34402 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34403 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34405 | // MIs[0] rs1 |
| 34406 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34407 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34408 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34409 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34410 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_RL), |
| 34411 | GIR_RootConstrainSelectedInstOperands, |
| 34412 | // GIR_Coverage, 755, |
| 34413 | GIR_Done, |
| 34414 | // Label 2429: @88535 |
| 34415 | GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(88576), // Rule ID 756 // |
| 34416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34417 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34418 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34420 | // MIs[0] rs1 |
| 34421 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34422 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34423 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34424 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34425 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34426 | GIR_RootConstrainSelectedInstOperands, |
| 34427 | // GIR_Coverage, 756, |
| 34428 | GIR_Done, |
| 34429 | // Label 2430: @88576 |
| 34430 | GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(88617), // Rule ID 757 // |
| 34431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34432 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34433 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34435 | // MIs[0] rs1 |
| 34436 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34437 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34438 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34439 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34440 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34441 | GIR_RootConstrainSelectedInstOperands, |
| 34442 | // GIR_Coverage, 757, |
| 34443 | GIR_Done, |
| 34444 | // Label 2431: @88617 |
| 34445 | GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(88658), // Rule ID 758 // |
| 34446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34447 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34448 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34450 | // MIs[0] rs1 |
| 34451 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34452 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34454 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34455 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34456 | GIR_RootConstrainSelectedInstOperands, |
| 34457 | // GIR_Coverage, 758, |
| 34458 | GIR_Done, |
| 34459 | // Label 2432: @88658 |
| 34460 | GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(88699), // Rule ID 759 // |
| 34461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 34462 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34463 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34465 | // MIs[0] rs1 |
| 34466 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34467 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34468 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34469 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34470 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34471 | GIR_RootConstrainSelectedInstOperands, |
| 34472 | // GIR_Coverage, 759, |
| 34473 | GIR_Done, |
| 34474 | // Label 2433: @88699 |
| 34475 | GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(88740), // Rule ID 760 // |
| 34476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 34477 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34480 | // MIs[0] rs1 |
| 34481 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34484 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34485 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34486 | GIR_RootConstrainSelectedInstOperands, |
| 34487 | // GIR_Coverage, 760, |
| 34488 | GIR_Done, |
| 34489 | // Label 2434: @88740 |
| 34490 | GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(88781), // Rule ID 761 // |
| 34491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34492 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34493 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34495 | // MIs[0] rs1 |
| 34496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34497 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34498 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34499 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34500 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34501 | GIR_RootConstrainSelectedInstOperands, |
| 34502 | // GIR_Coverage, 761, |
| 34503 | GIR_Done, |
| 34504 | // Label 2435: @88781 |
| 34505 | GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(88822), // Rule ID 762 // |
| 34506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 34507 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34510 | // MIs[0] rs1 |
| 34511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34512 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34513 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34514 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34515 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34516 | GIR_RootConstrainSelectedInstOperands, |
| 34517 | // GIR_Coverage, 762, |
| 34518 | GIR_Done, |
| 34519 | // Label 2436: @88822 |
| 34520 | GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(88863), // Rule ID 763 // |
| 34521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34522 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34523 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34525 | // MIs[0] rs1 |
| 34526 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34527 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34528 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34529 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34530 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34531 | GIR_RootConstrainSelectedInstOperands, |
| 34532 | // GIR_Coverage, 763, |
| 34533 | GIR_Done, |
| 34534 | // Label 2437: @88863 |
| 34535 | GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(88904), // Rule ID 764 // |
| 34536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 34537 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34538 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34539 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34540 | // MIs[0] rs1 |
| 34541 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34542 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34543 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34544 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34545 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34546 | GIR_RootConstrainSelectedInstOperands, |
| 34547 | // GIR_Coverage, 764, |
| 34548 | GIR_Done, |
| 34549 | // Label 2438: @88904 |
| 34550 | GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(88945), // Rule ID 765 // |
| 34551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34552 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34553 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34555 | // MIs[0] rs1 |
| 34556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34558 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34559 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34560 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34561 | GIR_RootConstrainSelectedInstOperands, |
| 34562 | // GIR_Coverage, 765, |
| 34563 | GIR_Done, |
| 34564 | // Label 2439: @88945 |
| 34565 | GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(88986), // Rule ID 766 // |
| 34566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 34567 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34568 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34570 | // MIs[0] rs1 |
| 34571 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34572 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34574 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34575 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34576 | GIR_RootConstrainSelectedInstOperands, |
| 34577 | // GIR_Coverage, 766, |
| 34578 | GIR_Done, |
| 34579 | // Label 2440: @88986 |
| 34580 | GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(89027), // Rule ID 767 // |
| 34581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34582 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34583 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34585 | // MIs[0] rs1 |
| 34586 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34587 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34588 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34589 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34590 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34591 | GIR_RootConstrainSelectedInstOperands, |
| 34592 | // GIR_Coverage, 767, |
| 34593 | GIR_Done, |
| 34594 | // Label 2441: @89027 |
| 34595 | GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(89068), // Rule ID 768 // |
| 34596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 34597 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34598 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34600 | // MIs[0] rs1 |
| 34601 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34602 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34603 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34604 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34605 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34606 | GIR_RootConstrainSelectedInstOperands, |
| 34607 | // GIR_Coverage, 768, |
| 34608 | GIR_Done, |
| 34609 | // Label 2442: @89068 |
| 34610 | GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(89109), // Rule ID 769 // |
| 34611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 34612 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34613 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34615 | // MIs[0] rs1 |
| 34616 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34617 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34618 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34619 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34620 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34621 | GIR_RootConstrainSelectedInstOperands, |
| 34622 | // GIR_Coverage, 769, |
| 34623 | GIR_Done, |
| 34624 | // Label 2443: @89109 |
| 34625 | GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(89150), // Rule ID 983 // |
| 34626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34627 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34628 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34630 | // MIs[0] rs1 |
| 34631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34632 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34634 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>> => (AMOOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34635 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 34636 | GIR_RootConstrainSelectedInstOperands, |
| 34637 | // GIR_Coverage, 983, |
| 34638 | GIR_Done, |
| 34639 | // Label 2444: @89150 |
| 34640 | GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(89191), // Rule ID 985 // |
| 34641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34642 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34643 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34645 | // MIs[0] rs1 |
| 34646 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34647 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34648 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34649 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>> => (AMOOR_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34650 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_AQ), |
| 34651 | GIR_RootConstrainSelectedInstOperands, |
| 34652 | // GIR_Coverage, 985, |
| 34653 | GIR_Done, |
| 34654 | // Label 2445: @89191 |
| 34655 | GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(89232), // Rule ID 987 // |
| 34656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34657 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34658 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34660 | // MIs[0] rs1 |
| 34661 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34662 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34663 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34664 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>> => (AMOOR_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34665 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_RL), |
| 34666 | GIR_RootConstrainSelectedInstOperands, |
| 34667 | // GIR_Coverage, 987, |
| 34668 | GIR_Done, |
| 34669 | // Label 2446: @89232 |
| 34670 | GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(89273), // Rule ID 989 // |
| 34671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34672 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34673 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34675 | // MIs[0] rs1 |
| 34676 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34677 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34678 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34679 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>> => (AMOOR_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34680 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_AQ_RL), |
| 34681 | GIR_RootConstrainSelectedInstOperands, |
| 34682 | // GIR_Coverage, 989, |
| 34683 | GIR_Done, |
| 34684 | // Label 2447: @89273 |
| 34685 | GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(89314), // Rule ID 991 // |
| 34686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34687 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34688 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34690 | // MIs[0] rs1 |
| 34691 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34694 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>> => (AMOOR_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34695 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_AQ_RL), |
| 34696 | GIR_RootConstrainSelectedInstOperands, |
| 34697 | // GIR_Coverage, 991, |
| 34698 | GIR_Done, |
| 34699 | // Label 2448: @89314 |
| 34700 | GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(89355), // Rule ID 993 // |
| 34701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34702 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34703 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34705 | // MIs[0] rs1 |
| 34706 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34708 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34709 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>> => (AMOOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34710 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 34711 | GIR_RootConstrainSelectedInstOperands, |
| 34712 | // GIR_Coverage, 993, |
| 34713 | GIR_Done, |
| 34714 | // Label 2449: @89355 |
| 34715 | GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(89396), // Rule ID 995 // |
| 34716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34717 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34718 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34720 | // MIs[0] rs1 |
| 34721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34722 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34724 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>> => (AMOOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34725 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 34726 | GIR_RootConstrainSelectedInstOperands, |
| 34727 | // GIR_Coverage, 995, |
| 34728 | GIR_Done, |
| 34729 | // Label 2450: @89396 |
| 34730 | GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(89437), // Rule ID 997 // |
| 34731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34732 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34733 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34735 | // MIs[0] rs1 |
| 34736 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34737 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34738 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34739 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>> => (AMOOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34740 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 34741 | GIR_RootConstrainSelectedInstOperands, |
| 34742 | // GIR_Coverage, 997, |
| 34743 | GIR_Done, |
| 34744 | // Label 2451: @89437 |
| 34745 | GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(89478), // Rule ID 999 // |
| 34746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34747 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34748 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34750 | // MIs[0] rs1 |
| 34751 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34754 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>> => (AMOOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34755 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 34756 | GIR_RootConstrainSelectedInstOperands, |
| 34757 | // GIR_Coverage, 999, |
| 34758 | GIR_Done, |
| 34759 | // Label 2452: @89478 |
| 34760 | GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(89519), // Rule ID 1001 // |
| 34761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34762 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 34763 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34765 | // MIs[0] rs1 |
| 34766 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34767 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34768 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34769 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>> => (AMOOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34770 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 34771 | GIR_RootConstrainSelectedInstOperands, |
| 34772 | // GIR_Coverage, 1001, |
| 34773 | GIR_Done, |
| 34774 | // Label 2453: @89519 |
| 34775 | GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(89560), // Rule ID 1163 // |
| 34776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34777 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34778 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34780 | // MIs[0] rs1 |
| 34781 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34782 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34783 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34784 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>> => (AMOOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34785 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 34786 | GIR_RootConstrainSelectedInstOperands, |
| 34787 | // GIR_Coverage, 1163, |
| 34788 | GIR_Done, |
| 34789 | // Label 2454: @89560 |
| 34790 | GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(89601), // Rule ID 1165 // |
| 34791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34792 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34793 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34795 | // MIs[0] rs1 |
| 34796 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34797 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34798 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34799 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>> => (AMOOR_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34800 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_AQ), |
| 34801 | GIR_RootConstrainSelectedInstOperands, |
| 34802 | // GIR_Coverage, 1165, |
| 34803 | GIR_Done, |
| 34804 | // Label 2455: @89601 |
| 34805 | GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(89642), // Rule ID 1167 // |
| 34806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34807 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34808 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34810 | // MIs[0] rs1 |
| 34811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34812 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34813 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34814 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>> => (AMOOR_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34815 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_RL), |
| 34816 | GIR_RootConstrainSelectedInstOperands, |
| 34817 | // GIR_Coverage, 1167, |
| 34818 | GIR_Done, |
| 34819 | // Label 2456: @89642 |
| 34820 | GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(89683), // Rule ID 1169 // |
| 34821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34822 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34823 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34825 | // MIs[0] rs1 |
| 34826 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34828 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34829 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>> => (AMOOR_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34830 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_AQ_RL), |
| 34831 | GIR_RootConstrainSelectedInstOperands, |
| 34832 | // GIR_Coverage, 1169, |
| 34833 | GIR_Done, |
| 34834 | // Label 2457: @89683 |
| 34835 | GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(89724), // Rule ID 1171 // |
| 34836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 34837 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34838 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34840 | // MIs[0] rs1 |
| 34841 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34842 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34844 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>> => (AMOOR_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34845 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_AQ_RL), |
| 34846 | GIR_RootConstrainSelectedInstOperands, |
| 34847 | // GIR_Coverage, 1171, |
| 34848 | GIR_Done, |
| 34849 | // Label 2458: @89724 |
| 34850 | GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(89765), // Rule ID 1173 // |
| 34851 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34852 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34853 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34855 | // MIs[0] rs1 |
| 34856 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34858 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34859 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>> => (AMOOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34860 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 34861 | GIR_RootConstrainSelectedInstOperands, |
| 34862 | // GIR_Coverage, 1173, |
| 34863 | GIR_Done, |
| 34864 | // Label 2459: @89765 |
| 34865 | GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(89806), // Rule ID 1175 // |
| 34866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34867 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34868 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34870 | // MIs[0] rs1 |
| 34871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34874 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>> => (AMOOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34875 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 34876 | GIR_RootConstrainSelectedInstOperands, |
| 34877 | // GIR_Coverage, 1175, |
| 34878 | GIR_Done, |
| 34879 | // Label 2460: @89806 |
| 34880 | GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(89847), // Rule ID 1177 // |
| 34881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34882 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34883 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34885 | // MIs[0] rs1 |
| 34886 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34887 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34888 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34889 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>> => (AMOOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34890 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 34891 | GIR_RootConstrainSelectedInstOperands, |
| 34892 | // GIR_Coverage, 1177, |
| 34893 | GIR_Done, |
| 34894 | // Label 2461: @89847 |
| 34895 | GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(89888), // Rule ID 1179 // |
| 34896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34897 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34898 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34900 | // MIs[0] rs1 |
| 34901 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34902 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34903 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34904 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>> => (AMOOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34905 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 34906 | GIR_RootConstrainSelectedInstOperands, |
| 34907 | // GIR_Coverage, 1179, |
| 34908 | GIR_Done, |
| 34909 | // Label 2462: @89888 |
| 34910 | GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(89929), // Rule ID 1181 // |
| 34911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 34912 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 34913 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34915 | // MIs[0] rs1 |
| 34916 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34917 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34918 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34919 | // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>> => (AMOOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 34920 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 34921 | GIR_RootConstrainSelectedInstOperands, |
| 34922 | // GIR_Coverage, 1181, |
| 34923 | GIR_Done, |
| 34924 | // Label 2463: @89929 |
| 34925 | GIM_Reject, |
| 34926 | // Label 2413: @89930 |
| 34927 | GIM_Reject, |
| 34928 | // Label 2411: @89931 |
| 34929 | GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(91580), |
| 34930 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 34931 | GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(89980), // Rule ID 432 // |
| 34932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34933 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34934 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 34935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34936 | // MIs[0] rs1 |
| 34937 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34938 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34940 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34941 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 34942 | GIR_RootConstrainSelectedInstOperands, |
| 34943 | // GIR_Coverage, 432, |
| 34944 | GIR_Done, |
| 34945 | // Label 2465: @89980 |
| 34946 | GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(90021), // Rule ID 434 // |
| 34947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34948 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 34950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34951 | // MIs[0] rs1 |
| 34952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34953 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34954 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34955 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34956 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ), |
| 34957 | GIR_RootConstrainSelectedInstOperands, |
| 34958 | // GIR_Coverage, 434, |
| 34959 | GIR_Done, |
| 34960 | // Label 2466: @90021 |
| 34961 | GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(90062), // Rule ID 436 // |
| 34962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34963 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34964 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 34965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34966 | // MIs[0] rs1 |
| 34967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34968 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34970 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34971 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_RL), |
| 34972 | GIR_RootConstrainSelectedInstOperands, |
| 34973 | // GIR_Coverage, 436, |
| 34974 | GIR_Done, |
| 34975 | // Label 2467: @90062 |
| 34976 | GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(90103), // Rule ID 438 // |
| 34977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34978 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34979 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 34980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34981 | // MIs[0] rs1 |
| 34982 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34983 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34985 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 34986 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 34987 | GIR_RootConstrainSelectedInstOperands, |
| 34988 | // GIR_Coverage, 438, |
| 34989 | GIR_Done, |
| 34990 | // Label 2468: @90103 |
| 34991 | GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(90144), // Rule ID 440 // |
| 34992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 34993 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 34994 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 34995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34996 | // MIs[0] rs1 |
| 34997 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34998 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 34999 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35000 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35001 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W_AQ_RL), |
| 35002 | GIR_RootConstrainSelectedInstOperands, |
| 35003 | // GIR_Coverage, 440, |
| 35004 | GIR_Done, |
| 35005 | // Label 2469: @90144 |
| 35006 | GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(90185), // Rule ID 442 // |
| 35007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35008 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35009 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35011 | // MIs[0] rs1 |
| 35012 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35013 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35014 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35015 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35016 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 35017 | GIR_RootConstrainSelectedInstOperands, |
| 35018 | // GIR_Coverage, 442, |
| 35019 | GIR_Done, |
| 35020 | // Label 2470: @90185 |
| 35021 | GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(90226), // Rule ID 444 // |
| 35022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35023 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35024 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35026 | // MIs[0] rs1 |
| 35027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35028 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35029 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35030 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35031 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 35032 | GIR_RootConstrainSelectedInstOperands, |
| 35033 | // GIR_Coverage, 444, |
| 35034 | GIR_Done, |
| 35035 | // Label 2471: @90226 |
| 35036 | GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(90267), // Rule ID 446 // |
| 35037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35038 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35039 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35041 | // MIs[0] rs1 |
| 35042 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35043 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35044 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35045 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35046 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 35047 | GIR_RootConstrainSelectedInstOperands, |
| 35048 | // GIR_Coverage, 446, |
| 35049 | GIR_Done, |
| 35050 | // Label 2472: @90267 |
| 35051 | GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(90308), // Rule ID 448 // |
| 35052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35053 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35054 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35056 | // MIs[0] rs1 |
| 35057 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35058 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35060 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35061 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 35062 | GIR_RootConstrainSelectedInstOperands, |
| 35063 | // GIR_Coverage, 448, |
| 35064 | GIR_Done, |
| 35065 | // Label 2473: @90308 |
| 35066 | GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(90349), // Rule ID 450 // |
| 35067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35068 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35069 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35071 | // MIs[0] rs1 |
| 35072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35073 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35074 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35075 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35076 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_W), |
| 35077 | GIR_RootConstrainSelectedInstOperands, |
| 35078 | // GIR_Coverage, 450, |
| 35079 | GIR_Done, |
| 35080 | // Label 2474: @90349 |
| 35081 | GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(90390), // Rule ID 582 // |
| 35082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 35083 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35086 | // MIs[0] rs1 |
| 35087 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35088 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35089 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35090 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_monotonic>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35091 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D), |
| 35092 | GIR_RootConstrainSelectedInstOperands, |
| 35093 | // GIR_Coverage, 582, |
| 35094 | GIR_Done, |
| 35095 | // Label 2475: @90390 |
| 35096 | GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(90431), // Rule ID 583 // |
| 35097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 35098 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35099 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35101 | // MIs[0] rs1 |
| 35102 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35103 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35104 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35105 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acquire>> => (AMOOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35106 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D_AQ), |
| 35107 | GIR_RootConstrainSelectedInstOperands, |
| 35108 | // GIR_Coverage, 583, |
| 35109 | GIR_Done, |
| 35110 | // Label 2476: @90431 |
| 35111 | GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(90472), // Rule ID 584 // |
| 35112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 35113 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35114 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35116 | // MIs[0] rs1 |
| 35117 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35118 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35120 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_release>> => (AMOOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35121 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D_RL), |
| 35122 | GIR_RootConstrainSelectedInstOperands, |
| 35123 | // GIR_Coverage, 584, |
| 35124 | GIR_Done, |
| 35125 | // Label 2477: @90472 |
| 35126 | GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(90513), // Rule ID 585 // |
| 35127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 35128 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35129 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35131 | // MIs[0] rs1 |
| 35132 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35133 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35134 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35135 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35136 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D_AQ_RL), |
| 35137 | GIR_RootConstrainSelectedInstOperands, |
| 35138 | // GIR_Coverage, 585, |
| 35139 | GIR_Done, |
| 35140 | // Label 2478: @90513 |
| 35141 | GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(90554), // Rule ID 586 // |
| 35142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 35143 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35144 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35146 | // MIs[0] rs1 |
| 35147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35148 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35150 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35151 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D_AQ_RL), |
| 35152 | GIR_RootConstrainSelectedInstOperands, |
| 35153 | // GIR_Coverage, 586, |
| 35154 | GIR_Done, |
| 35155 | // Label 2479: @90554 |
| 35156 | GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(90595), // Rule ID 587 // |
| 35157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 35158 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35159 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35161 | // MIs[0] rs1 |
| 35162 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35164 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35165 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_monotonic>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35166 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D), |
| 35167 | GIR_RootConstrainSelectedInstOperands, |
| 35168 | // GIR_Coverage, 587, |
| 35169 | GIR_Done, |
| 35170 | // Label 2480: @90595 |
| 35171 | GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(90636), // Rule ID 588 // |
| 35172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 35173 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35174 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35176 | // MIs[0] rs1 |
| 35177 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35180 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acquire>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35181 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D), |
| 35182 | GIR_RootConstrainSelectedInstOperands, |
| 35183 | // GIR_Coverage, 588, |
| 35184 | GIR_Done, |
| 35185 | // Label 2481: @90636 |
| 35186 | GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(90677), // Rule ID 589 // |
| 35187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 35188 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35189 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35191 | // MIs[0] rs1 |
| 35192 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35193 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35194 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35195 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_release>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35196 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D), |
| 35197 | GIR_RootConstrainSelectedInstOperands, |
| 35198 | // GIR_Coverage, 589, |
| 35199 | GIR_Done, |
| 35200 | // Label 2482: @90677 |
| 35201 | GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(90718), // Rule ID 590 // |
| 35202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 35203 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35204 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35206 | // MIs[0] rs1 |
| 35207 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35208 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35209 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35210 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acq_rel>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35211 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D), |
| 35212 | GIR_RootConstrainSelectedInstOperands, |
| 35213 | // GIR_Coverage, 590, |
| 35214 | GIR_Done, |
| 35215 | // Label 2483: @90718 |
| 35216 | GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(90759), // Rule ID 591 // |
| 35217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 35218 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 35219 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35221 | // MIs[0] rs1 |
| 35222 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35223 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35224 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35225 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_seq_cst>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35226 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_D), |
| 35227 | GIR_RootConstrainSelectedInstOperands, |
| 35228 | // GIR_Coverage, 591, |
| 35229 | GIR_Done, |
| 35230 | // Label 2484: @90759 |
| 35231 | GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(90800), // Rule ID 982 // |
| 35232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35233 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35234 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35236 | // MIs[0] rs1 |
| 35237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35238 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35240 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>> => (AMOOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35241 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 35242 | GIR_RootConstrainSelectedInstOperands, |
| 35243 | // GIR_Coverage, 982, |
| 35244 | GIR_Done, |
| 35245 | // Label 2485: @90800 |
| 35246 | GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(90841), // Rule ID 984 // |
| 35247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35248 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35249 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35251 | // MIs[0] rs1 |
| 35252 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35253 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35254 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35255 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>> => (AMOOR_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35256 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_AQ), |
| 35257 | GIR_RootConstrainSelectedInstOperands, |
| 35258 | // GIR_Coverage, 984, |
| 35259 | GIR_Done, |
| 35260 | // Label 2486: @90841 |
| 35261 | GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(90882), // Rule ID 986 // |
| 35262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35263 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35264 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35266 | // MIs[0] rs1 |
| 35267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35268 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35269 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35270 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>> => (AMOOR_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35271 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_RL), |
| 35272 | GIR_RootConstrainSelectedInstOperands, |
| 35273 | // GIR_Coverage, 986, |
| 35274 | GIR_Done, |
| 35275 | // Label 2487: @90882 |
| 35276 | GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(90923), // Rule ID 988 // |
| 35277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35278 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35279 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35281 | // MIs[0] rs1 |
| 35282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35284 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35285 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>> => (AMOOR_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35286 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_AQ_RL), |
| 35287 | GIR_RootConstrainSelectedInstOperands, |
| 35288 | // GIR_Coverage, 988, |
| 35289 | GIR_Done, |
| 35290 | // Label 2488: @90923 |
| 35291 | GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(90964), // Rule ID 990 // |
| 35292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35293 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35294 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35296 | // MIs[0] rs1 |
| 35297 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35298 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35300 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>> => (AMOOR_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35301 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B_AQ_RL), |
| 35302 | GIR_RootConstrainSelectedInstOperands, |
| 35303 | // GIR_Coverage, 990, |
| 35304 | GIR_Done, |
| 35305 | // Label 2489: @90964 |
| 35306 | GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(91005), // Rule ID 992 // |
| 35307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35308 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35309 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35311 | // MIs[0] rs1 |
| 35312 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35313 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35314 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35315 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>> => (AMOOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35316 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 35317 | GIR_RootConstrainSelectedInstOperands, |
| 35318 | // GIR_Coverage, 992, |
| 35319 | GIR_Done, |
| 35320 | // Label 2490: @91005 |
| 35321 | GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(91046), // Rule ID 994 // |
| 35322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35323 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35324 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35326 | // MIs[0] rs1 |
| 35327 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35328 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35329 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35330 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>> => (AMOOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35331 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 35332 | GIR_RootConstrainSelectedInstOperands, |
| 35333 | // GIR_Coverage, 994, |
| 35334 | GIR_Done, |
| 35335 | // Label 2491: @91046 |
| 35336 | GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(91087), // Rule ID 996 // |
| 35337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35338 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35339 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35341 | // MIs[0] rs1 |
| 35342 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35343 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35344 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35345 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>> => (AMOOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35346 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 35347 | GIR_RootConstrainSelectedInstOperands, |
| 35348 | // GIR_Coverage, 996, |
| 35349 | GIR_Done, |
| 35350 | // Label 2492: @91087 |
| 35351 | GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(91128), // Rule ID 998 // |
| 35352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35353 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35354 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35356 | // MIs[0] rs1 |
| 35357 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35358 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35359 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35360 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>> => (AMOOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35361 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 35362 | GIR_RootConstrainSelectedInstOperands, |
| 35363 | // GIR_Coverage, 998, |
| 35364 | GIR_Done, |
| 35365 | // Label 2493: @91128 |
| 35366 | GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(91169), // Rule ID 1000 // |
| 35367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35368 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35369 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35371 | // MIs[0] rs1 |
| 35372 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35373 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35374 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35375 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>> => (AMOOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35376 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_B), |
| 35377 | GIR_RootConstrainSelectedInstOperands, |
| 35378 | // GIR_Coverage, 1000, |
| 35379 | GIR_Done, |
| 35380 | // Label 2494: @91169 |
| 35381 | GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(91210), // Rule ID 1162 // |
| 35382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35383 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35384 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35386 | // MIs[0] rs1 |
| 35387 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35388 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35389 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35390 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>> => (AMOOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35391 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 35392 | GIR_RootConstrainSelectedInstOperands, |
| 35393 | // GIR_Coverage, 1162, |
| 35394 | GIR_Done, |
| 35395 | // Label 2495: @91210 |
| 35396 | GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(91251), // Rule ID 1164 // |
| 35397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35398 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35399 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35401 | // MIs[0] rs1 |
| 35402 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35403 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35404 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35405 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>> => (AMOOR_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35406 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_AQ), |
| 35407 | GIR_RootConstrainSelectedInstOperands, |
| 35408 | // GIR_Coverage, 1164, |
| 35409 | GIR_Done, |
| 35410 | // Label 2496: @91251 |
| 35411 | GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(91292), // Rule ID 1166 // |
| 35412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35413 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35414 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35416 | // MIs[0] rs1 |
| 35417 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35418 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35419 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35420 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>> => (AMOOR_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35421 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_RL), |
| 35422 | GIR_RootConstrainSelectedInstOperands, |
| 35423 | // GIR_Coverage, 1166, |
| 35424 | GIR_Done, |
| 35425 | // Label 2497: @91292 |
| 35426 | GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(91333), // Rule ID 1168 // |
| 35427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35428 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35429 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35431 | // MIs[0] rs1 |
| 35432 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35433 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35434 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35435 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>> => (AMOOR_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35436 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_AQ_RL), |
| 35437 | GIR_RootConstrainSelectedInstOperands, |
| 35438 | // GIR_Coverage, 1168, |
| 35439 | GIR_Done, |
| 35440 | // Label 2498: @91333 |
| 35441 | GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(91374), // Rule ID 1170 // |
| 35442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 35443 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35444 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35446 | // MIs[0] rs1 |
| 35447 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35450 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>> => (AMOOR_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35451 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H_AQ_RL), |
| 35452 | GIR_RootConstrainSelectedInstOperands, |
| 35453 | // GIR_Coverage, 1170, |
| 35454 | GIR_Done, |
| 35455 | // Label 2499: @91374 |
| 35456 | GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(91415), // Rule ID 1172 // |
| 35457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35458 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35459 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35461 | // MIs[0] rs1 |
| 35462 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35463 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35464 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35465 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>> => (AMOOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35466 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 35467 | GIR_RootConstrainSelectedInstOperands, |
| 35468 | // GIR_Coverage, 1172, |
| 35469 | GIR_Done, |
| 35470 | // Label 2500: @91415 |
| 35471 | GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(91456), // Rule ID 1174 // |
| 35472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35473 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35474 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35476 | // MIs[0] rs1 |
| 35477 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35478 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35479 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35480 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>> => (AMOOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35481 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 35482 | GIR_RootConstrainSelectedInstOperands, |
| 35483 | // GIR_Coverage, 1174, |
| 35484 | GIR_Done, |
| 35485 | // Label 2501: @91456 |
| 35486 | GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(91497), // Rule ID 1176 // |
| 35487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35488 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35489 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35491 | // MIs[0] rs1 |
| 35492 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35494 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35495 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>> => (AMOOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35496 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 35497 | GIR_RootConstrainSelectedInstOperands, |
| 35498 | // GIR_Coverage, 1176, |
| 35499 | GIR_Done, |
| 35500 | // Label 2502: @91497 |
| 35501 | GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(91538), // Rule ID 1178 // |
| 35502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35503 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35504 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35506 | // MIs[0] rs1 |
| 35507 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35508 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35509 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35510 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>> => (AMOOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35511 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 35512 | GIR_RootConstrainSelectedInstOperands, |
| 35513 | // GIR_Coverage, 1178, |
| 35514 | GIR_Done, |
| 35515 | // Label 2503: @91538 |
| 35516 | GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(91579), // Rule ID 1180 // |
| 35517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 35518 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 35519 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35521 | // MIs[0] rs1 |
| 35522 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35523 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35524 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35525 | // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>> => (AMOOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 35526 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOOR_H), |
| 35527 | GIR_RootConstrainSelectedInstOperands, |
| 35528 | // GIR_Coverage, 1180, |
| 35529 | GIR_Done, |
| 35530 | // Label 2504: @91579 |
| 35531 | GIM_Reject, |
| 35532 | // Label 2464: @91580 |
| 35533 | GIM_Reject, |
| 35534 | // Label 2412: @91581 |
| 35535 | GIM_Reject, |
| 35536 | // Label 28: @91582 |
| 35537 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2507*/ GIMT_Encode4(95311), |
| 35538 | /*GILLT_s32*//*Label 2505*/ GIMT_Encode4(91601), |
| 35539 | /*GILLT_s64*//*Label 2506*/ GIMT_Encode4(93661), |
| 35540 | // Label 2505: @91601 |
| 35541 | GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(93660), |
| 35542 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35543 | GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(91650), // Rule ID 453 // |
| 35544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35545 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35546 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35548 | // MIs[0] rs1 |
| 35549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35550 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35552 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35553 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35554 | GIR_RootConstrainSelectedInstOperands, |
| 35555 | // GIR_Coverage, 453, |
| 35556 | GIR_Done, |
| 35557 | // Label 2509: @91650 |
| 35558 | GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(91691), // Rule ID 455 // |
| 35559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35560 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35561 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35563 | // MIs[0] rs1 |
| 35564 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35566 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35567 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35568 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ), |
| 35569 | GIR_RootConstrainSelectedInstOperands, |
| 35570 | // GIR_Coverage, 455, |
| 35571 | GIR_Done, |
| 35572 | // Label 2510: @91691 |
| 35573 | GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(91732), // Rule ID 457 // |
| 35574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35575 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35576 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35578 | // MIs[0] rs1 |
| 35579 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35580 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35582 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35583 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_RL), |
| 35584 | GIR_RootConstrainSelectedInstOperands, |
| 35585 | // GIR_Coverage, 457, |
| 35586 | GIR_Done, |
| 35587 | // Label 2511: @91732 |
| 35588 | GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(91773), // Rule ID 459 // |
| 35589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35590 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35591 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35593 | // MIs[0] rs1 |
| 35594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35596 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35597 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35598 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 35599 | GIR_RootConstrainSelectedInstOperands, |
| 35600 | // GIR_Coverage, 459, |
| 35601 | GIR_Done, |
| 35602 | // Label 2512: @91773 |
| 35603 | GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(91814), // Rule ID 461 // |
| 35604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35605 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35606 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35608 | // MIs[0] rs1 |
| 35609 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35610 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35611 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35612 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35613 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 35614 | GIR_RootConstrainSelectedInstOperands, |
| 35615 | // GIR_Coverage, 461, |
| 35616 | GIR_Done, |
| 35617 | // Label 2513: @91814 |
| 35618 | GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(91855), // Rule ID 463 // |
| 35619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35620 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35621 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35623 | // MIs[0] rs1 |
| 35624 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35626 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35627 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35628 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35629 | GIR_RootConstrainSelectedInstOperands, |
| 35630 | // GIR_Coverage, 463, |
| 35631 | GIR_Done, |
| 35632 | // Label 2514: @91855 |
| 35633 | GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(91896), // Rule ID 465 // |
| 35634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35635 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35636 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35638 | // MIs[0] rs1 |
| 35639 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35640 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35642 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35643 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35644 | GIR_RootConstrainSelectedInstOperands, |
| 35645 | // GIR_Coverage, 465, |
| 35646 | GIR_Done, |
| 35647 | // Label 2515: @91896 |
| 35648 | GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(91937), // Rule ID 467 // |
| 35649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35650 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35651 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35653 | // MIs[0] rs1 |
| 35654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35655 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35657 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35658 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35659 | GIR_RootConstrainSelectedInstOperands, |
| 35660 | // GIR_Coverage, 467, |
| 35661 | GIR_Done, |
| 35662 | // Label 2516: @91937 |
| 35663 | GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(91978), // Rule ID 469 // |
| 35664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35665 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35666 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35668 | // MIs[0] rs1 |
| 35669 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35670 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35671 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35672 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35673 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35674 | GIR_RootConstrainSelectedInstOperands, |
| 35675 | // GIR_Coverage, 469, |
| 35676 | GIR_Done, |
| 35677 | // Label 2517: @91978 |
| 35678 | GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(92019), // Rule ID 471 // |
| 35679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35680 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35681 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35683 | // MIs[0] rs1 |
| 35684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35686 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35687 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35688 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35689 | GIR_RootConstrainSelectedInstOperands, |
| 35690 | // GIR_Coverage, 471, |
| 35691 | GIR_Done, |
| 35692 | // Label 2518: @92019 |
| 35693 | GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(92060), // Rule ID 770 // |
| 35694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 35695 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35696 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35698 | // MIs[0] rs1 |
| 35699 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35700 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35702 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35703 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35704 | GIR_RootConstrainSelectedInstOperands, |
| 35705 | // GIR_Coverage, 770, |
| 35706 | GIR_Done, |
| 35707 | // Label 2519: @92060 |
| 35708 | GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(92101), // Rule ID 771 // |
| 35709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35710 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35711 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35713 | // MIs[0] rs1 |
| 35714 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35716 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35717 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35718 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35719 | GIR_RootConstrainSelectedInstOperands, |
| 35720 | // GIR_Coverage, 771, |
| 35721 | GIR_Done, |
| 35722 | // Label 2520: @92101 |
| 35723 | GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(92142), // Rule ID 772 // |
| 35724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 35725 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35726 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35728 | // MIs[0] rs1 |
| 35729 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35730 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35731 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35732 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35733 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ), |
| 35734 | GIR_RootConstrainSelectedInstOperands, |
| 35735 | // GIR_Coverage, 772, |
| 35736 | GIR_Done, |
| 35737 | // Label 2521: @92142 |
| 35738 | GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(92183), // Rule ID 773 // |
| 35739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35740 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35741 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35743 | // MIs[0] rs1 |
| 35744 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35745 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35746 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35747 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35748 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ), |
| 35749 | GIR_RootConstrainSelectedInstOperands, |
| 35750 | // GIR_Coverage, 773, |
| 35751 | GIR_Done, |
| 35752 | // Label 2522: @92183 |
| 35753 | GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(92224), // Rule ID 774 // |
| 35754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 35755 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35756 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35758 | // MIs[0] rs1 |
| 35759 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35760 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35762 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35763 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_RL), |
| 35764 | GIR_RootConstrainSelectedInstOperands, |
| 35765 | // GIR_Coverage, 774, |
| 35766 | GIR_Done, |
| 35767 | // Label 2523: @92224 |
| 35768 | GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(92265), // Rule ID 775 // |
| 35769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35770 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35773 | // MIs[0] rs1 |
| 35774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35776 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35777 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35778 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_RL), |
| 35779 | GIR_RootConstrainSelectedInstOperands, |
| 35780 | // GIR_Coverage, 775, |
| 35781 | GIR_Done, |
| 35782 | // Label 2524: @92265 |
| 35783 | GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(92306), // Rule ID 776 // |
| 35784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 35785 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35786 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35788 | // MIs[0] rs1 |
| 35789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35791 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35792 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35793 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 35794 | GIR_RootConstrainSelectedInstOperands, |
| 35795 | // GIR_Coverage, 776, |
| 35796 | GIR_Done, |
| 35797 | // Label 2525: @92306 |
| 35798 | GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(92347), // Rule ID 777 // |
| 35799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35800 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35801 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35803 | // MIs[0] rs1 |
| 35804 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35806 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35807 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35808 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 35809 | GIR_RootConstrainSelectedInstOperands, |
| 35810 | // GIR_Coverage, 777, |
| 35811 | GIR_Done, |
| 35812 | // Label 2526: @92347 |
| 35813 | GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(92388), // Rule ID 778 // |
| 35814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 35815 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35816 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35818 | // MIs[0] rs1 |
| 35819 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35820 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35821 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35822 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35823 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 35824 | GIR_RootConstrainSelectedInstOperands, |
| 35825 | // GIR_Coverage, 778, |
| 35826 | GIR_Done, |
| 35827 | // Label 2527: @92388 |
| 35828 | GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(92429), // Rule ID 779 // |
| 35829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 35830 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35831 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35833 | // MIs[0] rs1 |
| 35834 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35835 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35836 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35837 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35838 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 35839 | GIR_RootConstrainSelectedInstOperands, |
| 35840 | // GIR_Coverage, 779, |
| 35841 | GIR_Done, |
| 35842 | // Label 2528: @92429 |
| 35843 | GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(92470), // Rule ID 780 // |
| 35844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35845 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35846 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35848 | // MIs[0] rs1 |
| 35849 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35851 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35852 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35853 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35854 | GIR_RootConstrainSelectedInstOperands, |
| 35855 | // GIR_Coverage, 780, |
| 35856 | GIR_Done, |
| 35857 | // Label 2529: @92470 |
| 35858 | GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(92511), // Rule ID 781 // |
| 35859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35860 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35861 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35863 | // MIs[0] rs1 |
| 35864 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35865 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35866 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35867 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35868 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35869 | GIR_RootConstrainSelectedInstOperands, |
| 35870 | // GIR_Coverage, 781, |
| 35871 | GIR_Done, |
| 35872 | // Label 2530: @92511 |
| 35873 | GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(92552), // Rule ID 782 // |
| 35874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35875 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35876 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35878 | // MIs[0] rs1 |
| 35879 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35880 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35881 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35882 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35883 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35884 | GIR_RootConstrainSelectedInstOperands, |
| 35885 | // GIR_Coverage, 782, |
| 35886 | GIR_Done, |
| 35887 | // Label 2531: @92552 |
| 35888 | GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(92593), // Rule ID 783 // |
| 35889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35890 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35891 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 35892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35893 | // MIs[0] rs1 |
| 35894 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35895 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35896 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35897 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35898 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35899 | GIR_RootConstrainSelectedInstOperands, |
| 35900 | // GIR_Coverage, 783, |
| 35901 | GIR_Done, |
| 35902 | // Label 2532: @92593 |
| 35903 | GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(92634), // Rule ID 784 // |
| 35904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35905 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35906 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35908 | // MIs[0] rs1 |
| 35909 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35911 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35912 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35913 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35914 | GIR_RootConstrainSelectedInstOperands, |
| 35915 | // GIR_Coverage, 784, |
| 35916 | GIR_Done, |
| 35917 | // Label 2533: @92634 |
| 35918 | GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(92675), // Rule ID 785 // |
| 35919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35920 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35921 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 35922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35923 | // MIs[0] rs1 |
| 35924 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35925 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35926 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35927 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35928 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35929 | GIR_RootConstrainSelectedInstOperands, |
| 35930 | // GIR_Coverage, 785, |
| 35931 | GIR_Done, |
| 35932 | // Label 2534: @92675 |
| 35933 | GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(92716), // Rule ID 786 // |
| 35934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35935 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35936 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35938 | // MIs[0] rs1 |
| 35939 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35940 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35941 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35942 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35943 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35944 | GIR_RootConstrainSelectedInstOperands, |
| 35945 | // GIR_Coverage, 786, |
| 35946 | GIR_Done, |
| 35947 | // Label 2535: @92716 |
| 35948 | GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(92757), // Rule ID 787 // |
| 35949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35950 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35951 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 35952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35953 | // MIs[0] rs1 |
| 35954 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35955 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35956 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35957 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35958 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35959 | GIR_RootConstrainSelectedInstOperands, |
| 35960 | // GIR_Coverage, 787, |
| 35961 | GIR_Done, |
| 35962 | // Label 2536: @92757 |
| 35963 | GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(92798), // Rule ID 788 // |
| 35964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 35965 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35966 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35968 | // MIs[0] rs1 |
| 35969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 35970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35971 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35972 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35973 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35974 | GIR_RootConstrainSelectedInstOperands, |
| 35975 | // GIR_Coverage, 788, |
| 35976 | GIR_Done, |
| 35977 | // Label 2537: @92798 |
| 35978 | GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(92839), // Rule ID 789 // |
| 35979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 35980 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 35981 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 35982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35983 | // MIs[0] rs1 |
| 35984 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 35985 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35986 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35987 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 35988 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 35989 | GIR_RootConstrainSelectedInstOperands, |
| 35990 | // GIR_Coverage, 789, |
| 35991 | GIR_Done, |
| 35992 | // Label 2538: @92839 |
| 35993 | GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(92880), // Rule ID 1003 // |
| 35994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 35995 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 35996 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 35997 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 35998 | // MIs[0] rs1 |
| 35999 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36000 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36001 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36002 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>> => (AMOXOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36003 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36004 | GIR_RootConstrainSelectedInstOperands, |
| 36005 | // GIR_Coverage, 1003, |
| 36006 | GIR_Done, |
| 36007 | // Label 2539: @92880 |
| 36008 | GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(92921), // Rule ID 1005 // |
| 36009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36010 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36011 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36013 | // MIs[0] rs1 |
| 36014 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36015 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36016 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36017 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>> => (AMOXOR_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36018 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_AQ), |
| 36019 | GIR_RootConstrainSelectedInstOperands, |
| 36020 | // GIR_Coverage, 1005, |
| 36021 | GIR_Done, |
| 36022 | // Label 2540: @92921 |
| 36023 | GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(92962), // Rule ID 1007 // |
| 36024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36025 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36026 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36028 | // MIs[0] rs1 |
| 36029 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36031 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36032 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>> => (AMOXOR_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36033 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_RL), |
| 36034 | GIR_RootConstrainSelectedInstOperands, |
| 36035 | // GIR_Coverage, 1007, |
| 36036 | GIR_Done, |
| 36037 | // Label 2541: @92962 |
| 36038 | GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(93003), // Rule ID 1009 // |
| 36039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36040 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36041 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36043 | // MIs[0] rs1 |
| 36044 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36045 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36046 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36047 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>> => (AMOXOR_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36048 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_AQ_RL), |
| 36049 | GIR_RootConstrainSelectedInstOperands, |
| 36050 | // GIR_Coverage, 1009, |
| 36051 | GIR_Done, |
| 36052 | // Label 2542: @93003 |
| 36053 | GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(93044), // Rule ID 1011 // |
| 36054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36055 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36056 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36058 | // MIs[0] rs1 |
| 36059 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36060 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36061 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36062 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>> => (AMOXOR_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36063 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_AQ_RL), |
| 36064 | GIR_RootConstrainSelectedInstOperands, |
| 36065 | // GIR_Coverage, 1011, |
| 36066 | GIR_Done, |
| 36067 | // Label 2543: @93044 |
| 36068 | GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(93085), // Rule ID 1013 // |
| 36069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36070 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36071 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36073 | // MIs[0] rs1 |
| 36074 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36075 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36076 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36077 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>> => (AMOXOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36078 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36079 | GIR_RootConstrainSelectedInstOperands, |
| 36080 | // GIR_Coverage, 1013, |
| 36081 | GIR_Done, |
| 36082 | // Label 2544: @93085 |
| 36083 | GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(93126), // Rule ID 1015 // |
| 36084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36085 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36088 | // MIs[0] rs1 |
| 36089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36090 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36091 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36092 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>> => (AMOXOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36093 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36094 | GIR_RootConstrainSelectedInstOperands, |
| 36095 | // GIR_Coverage, 1015, |
| 36096 | GIR_Done, |
| 36097 | // Label 2545: @93126 |
| 36098 | GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(93167), // Rule ID 1017 // |
| 36099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36100 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36101 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36103 | // MIs[0] rs1 |
| 36104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36105 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36106 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36107 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>> => (AMOXOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36108 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36109 | GIR_RootConstrainSelectedInstOperands, |
| 36110 | // GIR_Coverage, 1017, |
| 36111 | GIR_Done, |
| 36112 | // Label 2546: @93167 |
| 36113 | GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(93208), // Rule ID 1019 // |
| 36114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36115 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36116 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36118 | // MIs[0] rs1 |
| 36119 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36120 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36121 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36122 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>> => (AMOXOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36123 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36124 | GIR_RootConstrainSelectedInstOperands, |
| 36125 | // GIR_Coverage, 1019, |
| 36126 | GIR_Done, |
| 36127 | // Label 2547: @93208 |
| 36128 | GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(93249), // Rule ID 1021 // |
| 36129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36130 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36131 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36133 | // MIs[0] rs1 |
| 36134 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36136 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36137 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>> => (AMOXOR_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36138 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36139 | GIR_RootConstrainSelectedInstOperands, |
| 36140 | // GIR_Coverage, 1021, |
| 36141 | GIR_Done, |
| 36142 | // Label 2548: @93249 |
| 36143 | GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(93290), // Rule ID 1183 // |
| 36144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36145 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36146 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36148 | // MIs[0] rs1 |
| 36149 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36151 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36152 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>> => (AMOXOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36153 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36154 | GIR_RootConstrainSelectedInstOperands, |
| 36155 | // GIR_Coverage, 1183, |
| 36156 | GIR_Done, |
| 36157 | // Label 2549: @93290 |
| 36158 | GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(93331), // Rule ID 1185 // |
| 36159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36160 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36161 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36163 | // MIs[0] rs1 |
| 36164 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36165 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36166 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36167 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>> => (AMOXOR_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36168 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_AQ), |
| 36169 | GIR_RootConstrainSelectedInstOperands, |
| 36170 | // GIR_Coverage, 1185, |
| 36171 | GIR_Done, |
| 36172 | // Label 2550: @93331 |
| 36173 | GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(93372), // Rule ID 1187 // |
| 36174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36175 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36176 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36178 | // MIs[0] rs1 |
| 36179 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36181 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36182 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>> => (AMOXOR_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36183 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_RL), |
| 36184 | GIR_RootConstrainSelectedInstOperands, |
| 36185 | // GIR_Coverage, 1187, |
| 36186 | GIR_Done, |
| 36187 | // Label 2551: @93372 |
| 36188 | GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(93413), // Rule ID 1189 // |
| 36189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36190 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36191 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36193 | // MIs[0] rs1 |
| 36194 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36195 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36196 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36197 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>> => (AMOXOR_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36198 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_AQ_RL), |
| 36199 | GIR_RootConstrainSelectedInstOperands, |
| 36200 | // GIR_Coverage, 1189, |
| 36201 | GIR_Done, |
| 36202 | // Label 2552: @93413 |
| 36203 | GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(93454), // Rule ID 1191 // |
| 36204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 36205 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36206 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36208 | // MIs[0] rs1 |
| 36209 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36210 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36211 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36212 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>> => (AMOXOR_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36213 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_AQ_RL), |
| 36214 | GIR_RootConstrainSelectedInstOperands, |
| 36215 | // GIR_Coverage, 1191, |
| 36216 | GIR_Done, |
| 36217 | // Label 2553: @93454 |
| 36218 | GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(93495), // Rule ID 1193 // |
| 36219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36220 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36221 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36223 | // MIs[0] rs1 |
| 36224 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36226 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36227 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>> => (AMOXOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36228 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36229 | GIR_RootConstrainSelectedInstOperands, |
| 36230 | // GIR_Coverage, 1193, |
| 36231 | GIR_Done, |
| 36232 | // Label 2554: @93495 |
| 36233 | GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(93536), // Rule ID 1195 // |
| 36234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36235 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36236 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36238 | // MIs[0] rs1 |
| 36239 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36240 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36241 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36242 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>> => (AMOXOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36243 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36244 | GIR_RootConstrainSelectedInstOperands, |
| 36245 | // GIR_Coverage, 1195, |
| 36246 | GIR_Done, |
| 36247 | // Label 2555: @93536 |
| 36248 | GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(93577), // Rule ID 1197 // |
| 36249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36250 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36251 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36253 | // MIs[0] rs1 |
| 36254 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36255 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36256 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36257 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>> => (AMOXOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36258 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36259 | GIR_RootConstrainSelectedInstOperands, |
| 36260 | // GIR_Coverage, 1197, |
| 36261 | GIR_Done, |
| 36262 | // Label 2556: @93577 |
| 36263 | GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(93618), // Rule ID 1199 // |
| 36264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36265 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36266 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36268 | // MIs[0] rs1 |
| 36269 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36270 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36271 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36272 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>> => (AMOXOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36273 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36274 | GIR_RootConstrainSelectedInstOperands, |
| 36275 | // GIR_Coverage, 1199, |
| 36276 | GIR_Done, |
| 36277 | // Label 2557: @93618 |
| 36278 | GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(93659), // Rule ID 1201 // |
| 36279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 36280 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36281 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36283 | // MIs[0] rs1 |
| 36284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36285 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36286 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36287 | // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>> => (AMOXOR_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36288 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36289 | GIR_RootConstrainSelectedInstOperands, |
| 36290 | // GIR_Coverage, 1201, |
| 36291 | GIR_Done, |
| 36292 | // Label 2558: @93659 |
| 36293 | GIM_Reject, |
| 36294 | // Label 2508: @93660 |
| 36295 | GIM_Reject, |
| 36296 | // Label 2506: @93661 |
| 36297 | GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(95310), |
| 36298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36299 | GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(93710), // Rule ID 452 // |
| 36300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 36301 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36304 | // MIs[0] rs1 |
| 36305 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36308 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36309 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 36310 | GIR_RootConstrainSelectedInstOperands, |
| 36311 | // GIR_Coverage, 452, |
| 36312 | GIR_Done, |
| 36313 | // Label 2560: @93710 |
| 36314 | GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(93751), // Rule ID 454 // |
| 36315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 36316 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36317 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36319 | // MIs[0] rs1 |
| 36320 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36321 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36322 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36323 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36324 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ), |
| 36325 | GIR_RootConstrainSelectedInstOperands, |
| 36326 | // GIR_Coverage, 454, |
| 36327 | GIR_Done, |
| 36328 | // Label 2561: @93751 |
| 36329 | GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(93792), // Rule ID 456 // |
| 36330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 36331 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36332 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36334 | // MIs[0] rs1 |
| 36335 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36338 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36339 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_RL), |
| 36340 | GIR_RootConstrainSelectedInstOperands, |
| 36341 | // GIR_Coverage, 456, |
| 36342 | GIR_Done, |
| 36343 | // Label 2562: @93792 |
| 36344 | GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(93833), // Rule ID 458 // |
| 36345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 36346 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36347 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36349 | // MIs[0] rs1 |
| 36350 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36351 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36352 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36353 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36354 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 36355 | GIR_RootConstrainSelectedInstOperands, |
| 36356 | // GIR_Coverage, 458, |
| 36357 | GIR_Done, |
| 36358 | // Label 2563: @93833 |
| 36359 | GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(93874), // Rule ID 460 // |
| 36360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 36361 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36362 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36364 | // MIs[0] rs1 |
| 36365 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36366 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36368 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36369 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W_AQ_RL), |
| 36370 | GIR_RootConstrainSelectedInstOperands, |
| 36371 | // GIR_Coverage, 460, |
| 36372 | GIR_Done, |
| 36373 | // Label 2564: @93874 |
| 36374 | GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(93915), // Rule ID 462 // |
| 36375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 36376 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36377 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36379 | // MIs[0] rs1 |
| 36380 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36382 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36383 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36384 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 36385 | GIR_RootConstrainSelectedInstOperands, |
| 36386 | // GIR_Coverage, 462, |
| 36387 | GIR_Done, |
| 36388 | // Label 2565: @93915 |
| 36389 | GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(93956), // Rule ID 464 // |
| 36390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 36391 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36392 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36394 | // MIs[0] rs1 |
| 36395 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36396 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36397 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36398 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36399 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 36400 | GIR_RootConstrainSelectedInstOperands, |
| 36401 | // GIR_Coverage, 464, |
| 36402 | GIR_Done, |
| 36403 | // Label 2566: @93956 |
| 36404 | GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(93997), // Rule ID 466 // |
| 36405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 36406 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36407 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36409 | // MIs[0] rs1 |
| 36410 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36411 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36412 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36413 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36414 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 36415 | GIR_RootConstrainSelectedInstOperands, |
| 36416 | // GIR_Coverage, 466, |
| 36417 | GIR_Done, |
| 36418 | // Label 2567: @93997 |
| 36419 | GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(94038), // Rule ID 468 // |
| 36420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 36421 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36422 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36423 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36424 | // MIs[0] rs1 |
| 36425 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36426 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36427 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36428 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36429 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 36430 | GIR_RootConstrainSelectedInstOperands, |
| 36431 | // GIR_Coverage, 468, |
| 36432 | GIR_Done, |
| 36433 | // Label 2568: @94038 |
| 36434 | GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(94079), // Rule ID 470 // |
| 36435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 36436 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36437 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36439 | // MIs[0] rs1 |
| 36440 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36441 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36442 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36443 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36444 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_W), |
| 36445 | GIR_RootConstrainSelectedInstOperands, |
| 36446 | // GIR_Coverage, 470, |
| 36447 | GIR_Done, |
| 36448 | // Label 2569: @94079 |
| 36449 | GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(94120), // Rule ID 592 // |
| 36450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 36451 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36452 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36454 | // MIs[0] rs1 |
| 36455 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36456 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36458 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_monotonic>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36459 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D), |
| 36460 | GIR_RootConstrainSelectedInstOperands, |
| 36461 | // GIR_Coverage, 592, |
| 36462 | GIR_Done, |
| 36463 | // Label 2570: @94120 |
| 36464 | GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(94161), // Rule ID 593 // |
| 36465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 36466 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36467 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36469 | // MIs[0] rs1 |
| 36470 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36471 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36472 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36473 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acquire>> => (AMOXOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36474 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D_AQ), |
| 36475 | GIR_RootConstrainSelectedInstOperands, |
| 36476 | // GIR_Coverage, 593, |
| 36477 | GIR_Done, |
| 36478 | // Label 2571: @94161 |
| 36479 | GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(94202), // Rule ID 594 // |
| 36480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 36481 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36482 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36484 | // MIs[0] rs1 |
| 36485 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36486 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36487 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36488 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_release>> => (AMOXOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36489 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D_RL), |
| 36490 | GIR_RootConstrainSelectedInstOperands, |
| 36491 | // GIR_Coverage, 594, |
| 36492 | GIR_Done, |
| 36493 | // Label 2572: @94202 |
| 36494 | GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(94243), // Rule ID 595 // |
| 36495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 36496 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36497 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36499 | // MIs[0] rs1 |
| 36500 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36501 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36502 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36503 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36504 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D_AQ_RL), |
| 36505 | GIR_RootConstrainSelectedInstOperands, |
| 36506 | // GIR_Coverage, 595, |
| 36507 | GIR_Done, |
| 36508 | // Label 2573: @94243 |
| 36509 | GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(94284), // Rule ID 596 // |
| 36510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 36511 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36512 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36513 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36514 | // MIs[0] rs1 |
| 36515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36516 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36517 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36518 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36519 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D_AQ_RL), |
| 36520 | GIR_RootConstrainSelectedInstOperands, |
| 36521 | // GIR_Coverage, 596, |
| 36522 | GIR_Done, |
| 36523 | // Label 2574: @94284 |
| 36524 | GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(94325), // Rule ID 597 // |
| 36525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 36526 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36527 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36529 | // MIs[0] rs1 |
| 36530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36531 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36532 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36533 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_monotonic>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36534 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D), |
| 36535 | GIR_RootConstrainSelectedInstOperands, |
| 36536 | // GIR_Coverage, 597, |
| 36537 | GIR_Done, |
| 36538 | // Label 2575: @94325 |
| 36539 | GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(94366), // Rule ID 598 // |
| 36540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 36541 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36544 | // MIs[0] rs1 |
| 36545 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36546 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36547 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36548 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acquire>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36549 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D), |
| 36550 | GIR_RootConstrainSelectedInstOperands, |
| 36551 | // GIR_Coverage, 598, |
| 36552 | GIR_Done, |
| 36553 | // Label 2576: @94366 |
| 36554 | GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(94407), // Rule ID 599 // |
| 36555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 36556 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36559 | // MIs[0] rs1 |
| 36560 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36561 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36563 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_release>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36564 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D), |
| 36565 | GIR_RootConstrainSelectedInstOperands, |
| 36566 | // GIR_Coverage, 599, |
| 36567 | GIR_Done, |
| 36568 | // Label 2577: @94407 |
| 36569 | GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(94448), // Rule ID 600 // |
| 36570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 36571 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36572 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36574 | // MIs[0] rs1 |
| 36575 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36578 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acq_rel>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36579 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D), |
| 36580 | GIR_RootConstrainSelectedInstOperands, |
| 36581 | // GIR_Coverage, 600, |
| 36582 | GIR_Done, |
| 36583 | // Label 2578: @94448 |
| 36584 | GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(94489), // Rule ID 601 // |
| 36585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 36586 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 36587 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36589 | // MIs[0] rs1 |
| 36590 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36591 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36592 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36593 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_seq_cst>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36594 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_D), |
| 36595 | GIR_RootConstrainSelectedInstOperands, |
| 36596 | // GIR_Coverage, 601, |
| 36597 | GIR_Done, |
| 36598 | // Label 2579: @94489 |
| 36599 | GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(94530), // Rule ID 1002 // |
| 36600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36601 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36602 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36604 | // MIs[0] rs1 |
| 36605 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36606 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36608 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>> => (AMOXOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36609 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36610 | GIR_RootConstrainSelectedInstOperands, |
| 36611 | // GIR_Coverage, 1002, |
| 36612 | GIR_Done, |
| 36613 | // Label 2580: @94530 |
| 36614 | GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(94571), // Rule ID 1004 // |
| 36615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36616 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36617 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36619 | // MIs[0] rs1 |
| 36620 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36621 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36622 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36623 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>> => (AMOXOR_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36624 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_AQ), |
| 36625 | GIR_RootConstrainSelectedInstOperands, |
| 36626 | // GIR_Coverage, 1004, |
| 36627 | GIR_Done, |
| 36628 | // Label 2581: @94571 |
| 36629 | GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(94612), // Rule ID 1006 // |
| 36630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36631 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36632 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36634 | // MIs[0] rs1 |
| 36635 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36636 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36637 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36638 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>> => (AMOXOR_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36639 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_RL), |
| 36640 | GIR_RootConstrainSelectedInstOperands, |
| 36641 | // GIR_Coverage, 1006, |
| 36642 | GIR_Done, |
| 36643 | // Label 2582: @94612 |
| 36644 | GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(94653), // Rule ID 1008 // |
| 36645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36646 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36647 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36649 | // MIs[0] rs1 |
| 36650 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36652 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36653 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>> => (AMOXOR_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36654 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_AQ_RL), |
| 36655 | GIR_RootConstrainSelectedInstOperands, |
| 36656 | // GIR_Coverage, 1008, |
| 36657 | GIR_Done, |
| 36658 | // Label 2583: @94653 |
| 36659 | GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(94694), // Rule ID 1010 // |
| 36660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36661 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36662 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36664 | // MIs[0] rs1 |
| 36665 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36666 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36667 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36668 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>> => (AMOXOR_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36669 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B_AQ_RL), |
| 36670 | GIR_RootConstrainSelectedInstOperands, |
| 36671 | // GIR_Coverage, 1010, |
| 36672 | GIR_Done, |
| 36673 | // Label 2584: @94694 |
| 36674 | GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(94735), // Rule ID 1012 // |
| 36675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36676 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36677 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36679 | // MIs[0] rs1 |
| 36680 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36681 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36682 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36683 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>> => (AMOXOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36684 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36685 | GIR_RootConstrainSelectedInstOperands, |
| 36686 | // GIR_Coverage, 1012, |
| 36687 | GIR_Done, |
| 36688 | // Label 2585: @94735 |
| 36689 | GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(94776), // Rule ID 1014 // |
| 36690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36691 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36694 | // MIs[0] rs1 |
| 36695 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36696 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36698 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>> => (AMOXOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36699 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36700 | GIR_RootConstrainSelectedInstOperands, |
| 36701 | // GIR_Coverage, 1014, |
| 36702 | GIR_Done, |
| 36703 | // Label 2586: @94776 |
| 36704 | GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(94817), // Rule ID 1016 // |
| 36705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36706 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36707 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36709 | // MIs[0] rs1 |
| 36710 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36711 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36712 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36713 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>> => (AMOXOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36714 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36715 | GIR_RootConstrainSelectedInstOperands, |
| 36716 | // GIR_Coverage, 1016, |
| 36717 | GIR_Done, |
| 36718 | // Label 2587: @94817 |
| 36719 | GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(94858), // Rule ID 1018 // |
| 36720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36721 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36722 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36724 | // MIs[0] rs1 |
| 36725 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36727 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36728 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>> => (AMOXOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36729 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36730 | GIR_RootConstrainSelectedInstOperands, |
| 36731 | // GIR_Coverage, 1018, |
| 36732 | GIR_Done, |
| 36733 | // Label 2588: @94858 |
| 36734 | GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(94899), // Rule ID 1020 // |
| 36735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36736 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 36737 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36739 | // MIs[0] rs1 |
| 36740 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36741 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36742 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36743 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>> => (AMOXOR_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36744 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_B), |
| 36745 | GIR_RootConstrainSelectedInstOperands, |
| 36746 | // GIR_Coverage, 1020, |
| 36747 | GIR_Done, |
| 36748 | // Label 2589: @94899 |
| 36749 | GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(94940), // Rule ID 1182 // |
| 36750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36751 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36754 | // MIs[0] rs1 |
| 36755 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36757 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36758 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>> => (AMOXOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36759 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36760 | GIR_RootConstrainSelectedInstOperands, |
| 36761 | // GIR_Coverage, 1182, |
| 36762 | GIR_Done, |
| 36763 | // Label 2590: @94940 |
| 36764 | GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(94981), // Rule ID 1184 // |
| 36765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36766 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36767 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36769 | // MIs[0] rs1 |
| 36770 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36772 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36773 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>> => (AMOXOR_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36774 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_AQ), |
| 36775 | GIR_RootConstrainSelectedInstOperands, |
| 36776 | // GIR_Coverage, 1184, |
| 36777 | GIR_Done, |
| 36778 | // Label 2591: @94981 |
| 36779 | GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(95022), // Rule ID 1186 // |
| 36780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36781 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36782 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36784 | // MIs[0] rs1 |
| 36785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36786 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36787 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36788 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>> => (AMOXOR_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36789 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_RL), |
| 36790 | GIR_RootConstrainSelectedInstOperands, |
| 36791 | // GIR_Coverage, 1186, |
| 36792 | GIR_Done, |
| 36793 | // Label 2592: @95022 |
| 36794 | GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(95063), // Rule ID 1188 // |
| 36795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36796 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36797 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36799 | // MIs[0] rs1 |
| 36800 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36801 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36802 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36803 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>> => (AMOXOR_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36804 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_AQ_RL), |
| 36805 | GIR_RootConstrainSelectedInstOperands, |
| 36806 | // GIR_Coverage, 1188, |
| 36807 | GIR_Done, |
| 36808 | // Label 2593: @95063 |
| 36809 | GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(95104), // Rule ID 1190 // |
| 36810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 36811 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36812 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36814 | // MIs[0] rs1 |
| 36815 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36816 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36817 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36818 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>> => (AMOXOR_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36819 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H_AQ_RL), |
| 36820 | GIR_RootConstrainSelectedInstOperands, |
| 36821 | // GIR_Coverage, 1190, |
| 36822 | GIR_Done, |
| 36823 | // Label 2594: @95104 |
| 36824 | GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(95145), // Rule ID 1192 // |
| 36825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36826 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36827 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36829 | // MIs[0] rs1 |
| 36830 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36833 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>> => (AMOXOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36834 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36835 | GIR_RootConstrainSelectedInstOperands, |
| 36836 | // GIR_Coverage, 1192, |
| 36837 | GIR_Done, |
| 36838 | // Label 2595: @95145 |
| 36839 | GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(95186), // Rule ID 1194 // |
| 36840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36841 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36842 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36844 | // MIs[0] rs1 |
| 36845 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36847 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36848 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>> => (AMOXOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36849 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36850 | GIR_RootConstrainSelectedInstOperands, |
| 36851 | // GIR_Coverage, 1194, |
| 36852 | GIR_Done, |
| 36853 | // Label 2596: @95186 |
| 36854 | GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(95227), // Rule ID 1196 // |
| 36855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36856 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36857 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36859 | // MIs[0] rs1 |
| 36860 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36862 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36863 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>> => (AMOXOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36864 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36865 | GIR_RootConstrainSelectedInstOperands, |
| 36866 | // GIR_Coverage, 1196, |
| 36867 | GIR_Done, |
| 36868 | // Label 2597: @95227 |
| 36869 | GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(95268), // Rule ID 1198 // |
| 36870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36871 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36872 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36874 | // MIs[0] rs1 |
| 36875 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36877 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36878 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>> => (AMOXOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36879 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36880 | GIR_RootConstrainSelectedInstOperands, |
| 36881 | // GIR_Coverage, 1198, |
| 36882 | GIR_Done, |
| 36883 | // Label 2598: @95268 |
| 36884 | GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(95309), // Rule ID 1200 // |
| 36885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 36886 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 36887 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36889 | // MIs[0] rs1 |
| 36890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36892 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36893 | // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>> => (AMOXOR_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 36894 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOXOR_H), |
| 36895 | GIR_RootConstrainSelectedInstOperands, |
| 36896 | // GIR_Coverage, 1200, |
| 36897 | GIR_Done, |
| 36898 | // Label 2599: @95309 |
| 36899 | GIM_Reject, |
| 36900 | // Label 2559: @95310 |
| 36901 | GIM_Reject, |
| 36902 | // Label 2507: @95311 |
| 36903 | GIM_Reject, |
| 36904 | // Label 29: @95312 |
| 36905 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2602*/ GIMT_Encode4(99041), |
| 36906 | /*GILLT_s32*//*Label 2600*/ GIMT_Encode4(95331), |
| 36907 | /*GILLT_s64*//*Label 2601*/ GIMT_Encode4(97391), |
| 36908 | // Label 2600: @95331 |
| 36909 | GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(97390), |
| 36910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36911 | GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(95380), // Rule ID 473 // |
| 36912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 36913 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36914 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36916 | // MIs[0] rs1 |
| 36917 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36920 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36921 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 36922 | GIR_RootConstrainSelectedInstOperands, |
| 36923 | // GIR_Coverage, 473, |
| 36924 | GIR_Done, |
| 36925 | // Label 2604: @95380 |
| 36926 | GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(95421), // Rule ID 475 // |
| 36927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 36928 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 36930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36931 | // MIs[0] rs1 |
| 36932 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36934 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36935 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36936 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ), |
| 36937 | GIR_RootConstrainSelectedInstOperands, |
| 36938 | // GIR_Coverage, 475, |
| 36939 | GIR_Done, |
| 36940 | // Label 2605: @95421 |
| 36941 | GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(95462), // Rule ID 477 // |
| 36942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 36943 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36944 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 36945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36946 | // MIs[0] rs1 |
| 36947 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36949 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36950 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36951 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_RL), |
| 36952 | GIR_RootConstrainSelectedInstOperands, |
| 36953 | // GIR_Coverage, 477, |
| 36954 | GIR_Done, |
| 36955 | // Label 2606: @95462 |
| 36956 | GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(95503), // Rule ID 479 // |
| 36957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 36958 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36959 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 36960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36961 | // MIs[0] rs1 |
| 36962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36963 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36964 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36965 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36966 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 36967 | GIR_RootConstrainSelectedInstOperands, |
| 36968 | // GIR_Coverage, 479, |
| 36969 | GIR_Done, |
| 36970 | // Label 2607: @95503 |
| 36971 | GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(95544), // Rule ID 481 // |
| 36972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 36973 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36974 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 36975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36976 | // MIs[0] rs1 |
| 36977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36980 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36981 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 36982 | GIR_RootConstrainSelectedInstOperands, |
| 36983 | // GIR_Coverage, 481, |
| 36984 | GIR_Done, |
| 36985 | // Label 2608: @95544 |
| 36986 | GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(95585), // Rule ID 483 // |
| 36987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 36988 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 36989 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 36990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36991 | // MIs[0] rs1 |
| 36992 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 36993 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36994 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 36995 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 36996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 36997 | GIR_RootConstrainSelectedInstOperands, |
| 36998 | // GIR_Coverage, 483, |
| 36999 | GIR_Done, |
| 37000 | // Label 2609: @95585 |
| 37001 | GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(95626), // Rule ID 485 // |
| 37002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37003 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37004 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37006 | // MIs[0] rs1 |
| 37007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37008 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37009 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37010 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37011 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37012 | GIR_RootConstrainSelectedInstOperands, |
| 37013 | // GIR_Coverage, 485, |
| 37014 | GIR_Done, |
| 37015 | // Label 2610: @95626 |
| 37016 | GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(95667), // Rule ID 487 // |
| 37017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37018 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37019 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37021 | // MIs[0] rs1 |
| 37022 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37023 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37024 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37025 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37026 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37027 | GIR_RootConstrainSelectedInstOperands, |
| 37028 | // GIR_Coverage, 487, |
| 37029 | GIR_Done, |
| 37030 | // Label 2611: @95667 |
| 37031 | GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(95708), // Rule ID 489 // |
| 37032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37033 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37034 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37036 | // MIs[0] rs1 |
| 37037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37038 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37040 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37041 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37042 | GIR_RootConstrainSelectedInstOperands, |
| 37043 | // GIR_Coverage, 489, |
| 37044 | GIR_Done, |
| 37045 | // Label 2612: @95708 |
| 37046 | GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(95749), // Rule ID 491 // |
| 37047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37048 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37049 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37051 | // MIs[0] rs1 |
| 37052 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37053 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37054 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37055 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37056 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37057 | GIR_RootConstrainSelectedInstOperands, |
| 37058 | // GIR_Coverage, 491, |
| 37059 | GIR_Done, |
| 37060 | // Label 2613: @95749 |
| 37061 | GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(95790), // Rule ID 790 // |
| 37062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37063 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37064 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37066 | // MIs[0] rs1 |
| 37067 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37068 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37069 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37070 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37071 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37072 | GIR_RootConstrainSelectedInstOperands, |
| 37073 | // GIR_Coverage, 790, |
| 37074 | GIR_Done, |
| 37075 | // Label 2614: @95790 |
| 37076 | GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(95831), // Rule ID 791 // |
| 37077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 37078 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37079 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37081 | // MIs[0] rs1 |
| 37082 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37084 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37085 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37086 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37087 | GIR_RootConstrainSelectedInstOperands, |
| 37088 | // GIR_Coverage, 791, |
| 37089 | GIR_Done, |
| 37090 | // Label 2615: @95831 |
| 37091 | GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(95872), // Rule ID 792 // |
| 37092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37093 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37094 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37096 | // MIs[0] rs1 |
| 37097 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37098 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37099 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37100 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37101 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ), |
| 37102 | GIR_RootConstrainSelectedInstOperands, |
| 37103 | // GIR_Coverage, 792, |
| 37104 | GIR_Done, |
| 37105 | // Label 2616: @95872 |
| 37106 | GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(95913), // Rule ID 793 // |
| 37107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 37108 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37109 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37111 | // MIs[0] rs1 |
| 37112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37114 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37115 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37116 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ), |
| 37117 | GIR_RootConstrainSelectedInstOperands, |
| 37118 | // GIR_Coverage, 793, |
| 37119 | GIR_Done, |
| 37120 | // Label 2617: @95913 |
| 37121 | GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(95954), // Rule ID 794 // |
| 37122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37123 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37126 | // MIs[0] rs1 |
| 37127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37129 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37130 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37131 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_RL), |
| 37132 | GIR_RootConstrainSelectedInstOperands, |
| 37133 | // GIR_Coverage, 794, |
| 37134 | GIR_Done, |
| 37135 | // Label 2618: @95954 |
| 37136 | GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(95995), // Rule ID 795 // |
| 37137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 37138 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37139 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37141 | // MIs[0] rs1 |
| 37142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37144 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37145 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37146 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_RL), |
| 37147 | GIR_RootConstrainSelectedInstOperands, |
| 37148 | // GIR_Coverage, 795, |
| 37149 | GIR_Done, |
| 37150 | // Label 2619: @95995 |
| 37151 | GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(96036), // Rule ID 796 // |
| 37152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37153 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37154 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37156 | // MIs[0] rs1 |
| 37157 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37160 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37161 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 37162 | GIR_RootConstrainSelectedInstOperands, |
| 37163 | // GIR_Coverage, 796, |
| 37164 | GIR_Done, |
| 37165 | // Label 2620: @96036 |
| 37166 | GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(96077), // Rule ID 797 // |
| 37167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 37168 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37169 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37171 | // MIs[0] rs1 |
| 37172 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37174 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37175 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37176 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 37177 | GIR_RootConstrainSelectedInstOperands, |
| 37178 | // GIR_Coverage, 797, |
| 37179 | GIR_Done, |
| 37180 | // Label 2621: @96077 |
| 37181 | GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(96118), // Rule ID 798 // |
| 37182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37183 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37184 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37186 | // MIs[0] rs1 |
| 37187 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37190 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37191 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 37192 | GIR_RootConstrainSelectedInstOperands, |
| 37193 | // GIR_Coverage, 798, |
| 37194 | GIR_Done, |
| 37195 | // Label 2622: @96118 |
| 37196 | GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(96159), // Rule ID 799 // |
| 37197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 37198 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37199 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37201 | // MIs[0] rs1 |
| 37202 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37203 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37204 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37205 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37206 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 37207 | GIR_RootConstrainSelectedInstOperands, |
| 37208 | // GIR_Coverage, 799, |
| 37209 | GIR_Done, |
| 37210 | // Label 2623: @96159 |
| 37211 | GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(96200), // Rule ID 800 // |
| 37212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37213 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37214 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37216 | // MIs[0] rs1 |
| 37217 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37218 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37220 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37221 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37222 | GIR_RootConstrainSelectedInstOperands, |
| 37223 | // GIR_Coverage, 800, |
| 37224 | GIR_Done, |
| 37225 | // Label 2624: @96200 |
| 37226 | GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(96241), // Rule ID 801 // |
| 37227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37228 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37229 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37230 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37231 | // MIs[0] rs1 |
| 37232 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37233 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37234 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37235 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37236 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37237 | GIR_RootConstrainSelectedInstOperands, |
| 37238 | // GIR_Coverage, 801, |
| 37239 | GIR_Done, |
| 37240 | // Label 2625: @96241 |
| 37241 | GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(96282), // Rule ID 802 // |
| 37242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37243 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37244 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37246 | // MIs[0] rs1 |
| 37247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37248 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37249 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37250 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37251 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37252 | GIR_RootConstrainSelectedInstOperands, |
| 37253 | // GIR_Coverage, 802, |
| 37254 | GIR_Done, |
| 37255 | // Label 2626: @96282 |
| 37256 | GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(96323), // Rule ID 803 // |
| 37257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37258 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37259 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37261 | // MIs[0] rs1 |
| 37262 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37263 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37265 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37266 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37267 | GIR_RootConstrainSelectedInstOperands, |
| 37268 | // GIR_Coverage, 803, |
| 37269 | GIR_Done, |
| 37270 | // Label 2627: @96323 |
| 37271 | GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(96364), // Rule ID 804 // |
| 37272 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37273 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37274 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37276 | // MIs[0] rs1 |
| 37277 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37278 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37279 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37280 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37281 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37282 | GIR_RootConstrainSelectedInstOperands, |
| 37283 | // GIR_Coverage, 804, |
| 37284 | GIR_Done, |
| 37285 | // Label 2628: @96364 |
| 37286 | GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(96405), // Rule ID 805 // |
| 37287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37288 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37289 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37291 | // MIs[0] rs1 |
| 37292 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37293 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37294 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37295 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37296 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37297 | GIR_RootConstrainSelectedInstOperands, |
| 37298 | // GIR_Coverage, 805, |
| 37299 | GIR_Done, |
| 37300 | // Label 2629: @96405 |
| 37301 | GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(96446), // Rule ID 806 // |
| 37302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37303 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37304 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37306 | // MIs[0] rs1 |
| 37307 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37308 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37309 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37310 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37311 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37312 | GIR_RootConstrainSelectedInstOperands, |
| 37313 | // GIR_Coverage, 806, |
| 37314 | GIR_Done, |
| 37315 | // Label 2630: @96446 |
| 37316 | GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(96487), // Rule ID 807 // |
| 37317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37318 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37319 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37321 | // MIs[0] rs1 |
| 37322 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37323 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37324 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37325 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37326 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37327 | GIR_RootConstrainSelectedInstOperands, |
| 37328 | // GIR_Coverage, 807, |
| 37329 | GIR_Done, |
| 37330 | // Label 2631: @96487 |
| 37331 | GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(96528), // Rule ID 808 // |
| 37332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37333 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37334 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37336 | // MIs[0] rs1 |
| 37337 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37338 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37340 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37341 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37342 | GIR_RootConstrainSelectedInstOperands, |
| 37343 | // GIR_Coverage, 808, |
| 37344 | GIR_Done, |
| 37345 | // Label 2632: @96528 |
| 37346 | GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(96569), // Rule ID 809 // |
| 37347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 37348 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37349 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37351 | // MIs[0] rs1 |
| 37352 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37353 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37354 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37355 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37356 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37357 | GIR_RootConstrainSelectedInstOperands, |
| 37358 | // GIR_Coverage, 809, |
| 37359 | GIR_Done, |
| 37360 | // Label 2633: @96569 |
| 37361 | GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(96610), // Rule ID 1023 // |
| 37362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37363 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37364 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37366 | // MIs[0] rs1 |
| 37367 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37368 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37369 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37370 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>> => (AMOMAX_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37371 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37372 | GIR_RootConstrainSelectedInstOperands, |
| 37373 | // GIR_Coverage, 1023, |
| 37374 | GIR_Done, |
| 37375 | // Label 2634: @96610 |
| 37376 | GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(96651), // Rule ID 1025 // |
| 37377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37378 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37379 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37381 | // MIs[0] rs1 |
| 37382 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37383 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37384 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37385 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>> => (AMOMAX_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37386 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_AQ), |
| 37387 | GIR_RootConstrainSelectedInstOperands, |
| 37388 | // GIR_Coverage, 1025, |
| 37389 | GIR_Done, |
| 37390 | // Label 2635: @96651 |
| 37391 | GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(96692), // Rule ID 1027 // |
| 37392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37393 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37394 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37396 | // MIs[0] rs1 |
| 37397 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37398 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37399 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37400 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>> => (AMOMAX_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37401 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_RL), |
| 37402 | GIR_RootConstrainSelectedInstOperands, |
| 37403 | // GIR_Coverage, 1027, |
| 37404 | GIR_Done, |
| 37405 | // Label 2636: @96692 |
| 37406 | GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(96733), // Rule ID 1029 // |
| 37407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37408 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37409 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37411 | // MIs[0] rs1 |
| 37412 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37413 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37414 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37415 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>> => (AMOMAX_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37416 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_AQ_RL), |
| 37417 | GIR_RootConstrainSelectedInstOperands, |
| 37418 | // GIR_Coverage, 1029, |
| 37419 | GIR_Done, |
| 37420 | // Label 2637: @96733 |
| 37421 | GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(96774), // Rule ID 1031 // |
| 37422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37423 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37424 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37426 | // MIs[0] rs1 |
| 37427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37430 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>> => (AMOMAX_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37431 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_AQ_RL), |
| 37432 | GIR_RootConstrainSelectedInstOperands, |
| 37433 | // GIR_Coverage, 1031, |
| 37434 | GIR_Done, |
| 37435 | // Label 2638: @96774 |
| 37436 | GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(96815), // Rule ID 1033 // |
| 37437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37438 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37439 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37441 | // MIs[0] rs1 |
| 37442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37443 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37444 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37445 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>> => (AMOMAX_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37446 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37447 | GIR_RootConstrainSelectedInstOperands, |
| 37448 | // GIR_Coverage, 1033, |
| 37449 | GIR_Done, |
| 37450 | // Label 2639: @96815 |
| 37451 | GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(96856), // Rule ID 1035 // |
| 37452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37453 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37454 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37456 | // MIs[0] rs1 |
| 37457 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37458 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37459 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37460 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>> => (AMOMAX_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37461 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37462 | GIR_RootConstrainSelectedInstOperands, |
| 37463 | // GIR_Coverage, 1035, |
| 37464 | GIR_Done, |
| 37465 | // Label 2640: @96856 |
| 37466 | GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(96897), // Rule ID 1037 // |
| 37467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37468 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37469 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37471 | // MIs[0] rs1 |
| 37472 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37474 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37475 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>> => (AMOMAX_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37476 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37477 | GIR_RootConstrainSelectedInstOperands, |
| 37478 | // GIR_Coverage, 1037, |
| 37479 | GIR_Done, |
| 37480 | // Label 2641: @96897 |
| 37481 | GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(96938), // Rule ID 1039 // |
| 37482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37483 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37484 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37486 | // MIs[0] rs1 |
| 37487 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37490 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>> => (AMOMAX_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37491 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37492 | GIR_RootConstrainSelectedInstOperands, |
| 37493 | // GIR_Coverage, 1039, |
| 37494 | GIR_Done, |
| 37495 | // Label 2642: @96938 |
| 37496 | GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(96979), // Rule ID 1041 // |
| 37497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37498 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37499 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37501 | // MIs[0] rs1 |
| 37502 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37504 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37505 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>> => (AMOMAX_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37506 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37507 | GIR_RootConstrainSelectedInstOperands, |
| 37508 | // GIR_Coverage, 1041, |
| 37509 | GIR_Done, |
| 37510 | // Label 2643: @96979 |
| 37511 | GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(97020), // Rule ID 1203 // |
| 37512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37513 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37514 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37516 | // MIs[0] rs1 |
| 37517 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37518 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37519 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37520 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>> => (AMOMAX_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37521 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 37522 | GIR_RootConstrainSelectedInstOperands, |
| 37523 | // GIR_Coverage, 1203, |
| 37524 | GIR_Done, |
| 37525 | // Label 2644: @97020 |
| 37526 | GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(97061), // Rule ID 1205 // |
| 37527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37528 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37529 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37531 | // MIs[0] rs1 |
| 37532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37534 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37535 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>> => (AMOMAX_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37536 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_AQ), |
| 37537 | GIR_RootConstrainSelectedInstOperands, |
| 37538 | // GIR_Coverage, 1205, |
| 37539 | GIR_Done, |
| 37540 | // Label 2645: @97061 |
| 37541 | GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(97102), // Rule ID 1207 // |
| 37542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37543 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37544 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37545 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37546 | // MIs[0] rs1 |
| 37547 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37548 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37549 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37550 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>> => (AMOMAX_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37551 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_RL), |
| 37552 | GIR_RootConstrainSelectedInstOperands, |
| 37553 | // GIR_Coverage, 1207, |
| 37554 | GIR_Done, |
| 37555 | // Label 2646: @97102 |
| 37556 | GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(97143), // Rule ID 1209 // |
| 37557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37558 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37559 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37561 | // MIs[0] rs1 |
| 37562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37563 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37564 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37565 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>> => (AMOMAX_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37566 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_AQ_RL), |
| 37567 | GIR_RootConstrainSelectedInstOperands, |
| 37568 | // GIR_Coverage, 1209, |
| 37569 | GIR_Done, |
| 37570 | // Label 2647: @97143 |
| 37571 | GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(97184), // Rule ID 1211 // |
| 37572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 37573 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37574 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37576 | // MIs[0] rs1 |
| 37577 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37580 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>> => (AMOMAX_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37581 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_AQ_RL), |
| 37582 | GIR_RootConstrainSelectedInstOperands, |
| 37583 | // GIR_Coverage, 1211, |
| 37584 | GIR_Done, |
| 37585 | // Label 2648: @97184 |
| 37586 | GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(97225), // Rule ID 1213 // |
| 37587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37588 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37589 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37591 | // MIs[0] rs1 |
| 37592 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37593 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37594 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37595 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>> => (AMOMAX_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37596 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 37597 | GIR_RootConstrainSelectedInstOperands, |
| 37598 | // GIR_Coverage, 1213, |
| 37599 | GIR_Done, |
| 37600 | // Label 2649: @97225 |
| 37601 | GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(97266), // Rule ID 1215 // |
| 37602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37603 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37606 | // MIs[0] rs1 |
| 37607 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37608 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37609 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37610 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>> => (AMOMAX_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37611 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 37612 | GIR_RootConstrainSelectedInstOperands, |
| 37613 | // GIR_Coverage, 1215, |
| 37614 | GIR_Done, |
| 37615 | // Label 2650: @97266 |
| 37616 | GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(97307), // Rule ID 1217 // |
| 37617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37618 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37619 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37621 | // MIs[0] rs1 |
| 37622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37624 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37625 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>> => (AMOMAX_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37626 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 37627 | GIR_RootConstrainSelectedInstOperands, |
| 37628 | // GIR_Coverage, 1217, |
| 37629 | GIR_Done, |
| 37630 | // Label 2651: @97307 |
| 37631 | GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(97348), // Rule ID 1219 // |
| 37632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37633 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37634 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37636 | // MIs[0] rs1 |
| 37637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37638 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37639 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37640 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>> => (AMOMAX_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37641 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 37642 | GIR_RootConstrainSelectedInstOperands, |
| 37643 | // GIR_Coverage, 1219, |
| 37644 | GIR_Done, |
| 37645 | // Label 2652: @97348 |
| 37646 | GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(97389), // Rule ID 1221 // |
| 37647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 37648 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 37649 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37651 | // MIs[0] rs1 |
| 37652 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 37653 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37654 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37655 | // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>> => (AMOMAX_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 37656 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 37657 | GIR_RootConstrainSelectedInstOperands, |
| 37658 | // GIR_Coverage, 1221, |
| 37659 | GIR_Done, |
| 37660 | // Label 2653: @97389 |
| 37661 | GIM_Reject, |
| 37662 | // Label 2603: @97390 |
| 37663 | GIM_Reject, |
| 37664 | // Label 2601: @97391 |
| 37665 | GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(99040), |
| 37666 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37667 | GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(97440), // Rule ID 472 // |
| 37668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37669 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37670 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37672 | // MIs[0] rs1 |
| 37673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37674 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37675 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37676 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37677 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37678 | GIR_RootConstrainSelectedInstOperands, |
| 37679 | // GIR_Coverage, 472, |
| 37680 | GIR_Done, |
| 37681 | // Label 2655: @97440 |
| 37682 | GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(97481), // Rule ID 474 // |
| 37683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37684 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37685 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37687 | // MIs[0] rs1 |
| 37688 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37689 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37690 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37691 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37692 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ), |
| 37693 | GIR_RootConstrainSelectedInstOperands, |
| 37694 | // GIR_Coverage, 474, |
| 37695 | GIR_Done, |
| 37696 | // Label 2656: @97481 |
| 37697 | GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(97522), // Rule ID 476 // |
| 37698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37699 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37700 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37702 | // MIs[0] rs1 |
| 37703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37705 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37706 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37707 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_RL), |
| 37708 | GIR_RootConstrainSelectedInstOperands, |
| 37709 | // GIR_Coverage, 476, |
| 37710 | GIR_Done, |
| 37711 | // Label 2657: @97522 |
| 37712 | GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(97563), // Rule ID 478 // |
| 37713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37714 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37717 | // MIs[0] rs1 |
| 37718 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37719 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37720 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37721 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37722 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 37723 | GIR_RootConstrainSelectedInstOperands, |
| 37724 | // GIR_Coverage, 478, |
| 37725 | GIR_Done, |
| 37726 | // Label 2658: @97563 |
| 37727 | GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(97604), // Rule ID 480 // |
| 37728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 37729 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37730 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37732 | // MIs[0] rs1 |
| 37733 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37735 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37736 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37737 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W_AQ_RL), |
| 37738 | GIR_RootConstrainSelectedInstOperands, |
| 37739 | // GIR_Coverage, 480, |
| 37740 | GIR_Done, |
| 37741 | // Label 2659: @97604 |
| 37742 | GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(97645), // Rule ID 482 // |
| 37743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37744 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37745 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37747 | // MIs[0] rs1 |
| 37748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37750 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37751 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37752 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37753 | GIR_RootConstrainSelectedInstOperands, |
| 37754 | // GIR_Coverage, 482, |
| 37755 | GIR_Done, |
| 37756 | // Label 2660: @97645 |
| 37757 | GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(97686), // Rule ID 484 // |
| 37758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37759 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37760 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37762 | // MIs[0] rs1 |
| 37763 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37764 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37765 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37766 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37767 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37768 | GIR_RootConstrainSelectedInstOperands, |
| 37769 | // GIR_Coverage, 484, |
| 37770 | GIR_Done, |
| 37771 | // Label 2661: @97686 |
| 37772 | GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(97727), // Rule ID 486 // |
| 37773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37774 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37775 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37777 | // MIs[0] rs1 |
| 37778 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37779 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37780 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37781 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37782 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37783 | GIR_RootConstrainSelectedInstOperands, |
| 37784 | // GIR_Coverage, 486, |
| 37785 | GIR_Done, |
| 37786 | // Label 2662: @97727 |
| 37787 | GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(97768), // Rule ID 488 // |
| 37788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37789 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37792 | // MIs[0] rs1 |
| 37793 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37794 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37795 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37796 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37797 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37798 | GIR_RootConstrainSelectedInstOperands, |
| 37799 | // GIR_Coverage, 488, |
| 37800 | GIR_Done, |
| 37801 | // Label 2663: @97768 |
| 37802 | GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(97809), // Rule ID 490 // |
| 37803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 37804 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 37805 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37807 | // MIs[0] rs1 |
| 37808 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37809 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37810 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37811 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37812 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_W), |
| 37813 | GIR_RootConstrainSelectedInstOperands, |
| 37814 | // GIR_Coverage, 490, |
| 37815 | GIR_Done, |
| 37816 | // Label 2664: @97809 |
| 37817 | GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(97850), // Rule ID 602 // |
| 37818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 37819 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37820 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37822 | // MIs[0] rs1 |
| 37823 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37826 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_monotonic>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37827 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D), |
| 37828 | GIR_RootConstrainSelectedInstOperands, |
| 37829 | // GIR_Coverage, 602, |
| 37830 | GIR_Done, |
| 37831 | // Label 2665: @97850 |
| 37832 | GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(97891), // Rule ID 603 // |
| 37833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 37834 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37835 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37837 | // MIs[0] rs1 |
| 37838 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37839 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37840 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37841 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acquire>> => (AMOMAX_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37842 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D_AQ), |
| 37843 | GIR_RootConstrainSelectedInstOperands, |
| 37844 | // GIR_Coverage, 603, |
| 37845 | GIR_Done, |
| 37846 | // Label 2666: @97891 |
| 37847 | GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(97932), // Rule ID 604 // |
| 37848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 37849 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37850 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37852 | // MIs[0] rs1 |
| 37853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37854 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37855 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37856 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_release>> => (AMOMAX_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37857 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D_RL), |
| 37858 | GIR_RootConstrainSelectedInstOperands, |
| 37859 | // GIR_Coverage, 604, |
| 37860 | GIR_Done, |
| 37861 | // Label 2667: @97932 |
| 37862 | GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(97973), // Rule ID 605 // |
| 37863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 37864 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37865 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37867 | // MIs[0] rs1 |
| 37868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37870 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37871 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37872 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D_AQ_RL), |
| 37873 | GIR_RootConstrainSelectedInstOperands, |
| 37874 | // GIR_Coverage, 605, |
| 37875 | GIR_Done, |
| 37876 | // Label 2668: @97973 |
| 37877 | GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(98014), // Rule ID 606 // |
| 37878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 37879 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37880 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37882 | // MIs[0] rs1 |
| 37883 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37885 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37886 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37887 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D_AQ_RL), |
| 37888 | GIR_RootConstrainSelectedInstOperands, |
| 37889 | // GIR_Coverage, 606, |
| 37890 | GIR_Done, |
| 37891 | // Label 2669: @98014 |
| 37892 | GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(98055), // Rule ID 607 // |
| 37893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 37894 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37895 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37897 | // MIs[0] rs1 |
| 37898 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37899 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37900 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37901 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_monotonic>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37902 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D), |
| 37903 | GIR_RootConstrainSelectedInstOperands, |
| 37904 | // GIR_Coverage, 607, |
| 37905 | GIR_Done, |
| 37906 | // Label 2670: @98055 |
| 37907 | GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(98096), // Rule ID 608 // |
| 37908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 37909 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37910 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37912 | // MIs[0] rs1 |
| 37913 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37914 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37916 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acquire>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37917 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D), |
| 37918 | GIR_RootConstrainSelectedInstOperands, |
| 37919 | // GIR_Coverage, 608, |
| 37920 | GIR_Done, |
| 37921 | // Label 2671: @98096 |
| 37922 | GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(98137), // Rule ID 609 // |
| 37923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 37924 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37925 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 37926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37927 | // MIs[0] rs1 |
| 37928 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37929 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37930 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37931 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_release>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37932 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D), |
| 37933 | GIR_RootConstrainSelectedInstOperands, |
| 37934 | // GIR_Coverage, 609, |
| 37935 | GIR_Done, |
| 37936 | // Label 2672: @98137 |
| 37937 | GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(98178), // Rule ID 610 // |
| 37938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 37939 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37940 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 37941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37942 | // MIs[0] rs1 |
| 37943 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37944 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37945 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37946 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acq_rel>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37947 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D), |
| 37948 | GIR_RootConstrainSelectedInstOperands, |
| 37949 | // GIR_Coverage, 610, |
| 37950 | GIR_Done, |
| 37951 | // Label 2673: @98178 |
| 37952 | GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(98219), // Rule ID 611 // |
| 37953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 37954 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 37955 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 37956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37957 | // MIs[0] rs1 |
| 37958 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37960 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37961 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_seq_cst>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37962 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_D), |
| 37963 | GIR_RootConstrainSelectedInstOperands, |
| 37964 | // GIR_Coverage, 611, |
| 37965 | GIR_Done, |
| 37966 | // Label 2674: @98219 |
| 37967 | GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(98260), // Rule ID 1022 // |
| 37968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 37969 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37970 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 37971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37972 | // MIs[0] rs1 |
| 37973 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37974 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37975 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37976 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>> => (AMOMAX_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37977 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 37978 | GIR_RootConstrainSelectedInstOperands, |
| 37979 | // GIR_Coverage, 1022, |
| 37980 | GIR_Done, |
| 37981 | // Label 2675: @98260 |
| 37982 | GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(98301), // Rule ID 1024 // |
| 37983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 37984 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 37985 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 37986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37987 | // MIs[0] rs1 |
| 37988 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37990 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 37991 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>> => (AMOMAX_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 37992 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_AQ), |
| 37993 | GIR_RootConstrainSelectedInstOperands, |
| 37994 | // GIR_Coverage, 1024, |
| 37995 | GIR_Done, |
| 37996 | // Label 2676: @98301 |
| 37997 | GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(98342), // Rule ID 1026 // |
| 37998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 37999 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38000 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38002 | // MIs[0] rs1 |
| 38003 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38004 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38006 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>> => (AMOMAX_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38007 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_RL), |
| 38008 | GIR_RootConstrainSelectedInstOperands, |
| 38009 | // GIR_Coverage, 1026, |
| 38010 | GIR_Done, |
| 38011 | // Label 2677: @98342 |
| 38012 | GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(98383), // Rule ID 1028 // |
| 38013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38014 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38015 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38017 | // MIs[0] rs1 |
| 38018 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38019 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38020 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38021 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>> => (AMOMAX_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38022 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_AQ_RL), |
| 38023 | GIR_RootConstrainSelectedInstOperands, |
| 38024 | // GIR_Coverage, 1028, |
| 38025 | GIR_Done, |
| 38026 | // Label 2678: @98383 |
| 38027 | GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(98424), // Rule ID 1030 // |
| 38028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38029 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38030 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38032 | // MIs[0] rs1 |
| 38033 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38034 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38035 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38036 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>> => (AMOMAX_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38037 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B_AQ_RL), |
| 38038 | GIR_RootConstrainSelectedInstOperands, |
| 38039 | // GIR_Coverage, 1030, |
| 38040 | GIR_Done, |
| 38041 | // Label 2679: @98424 |
| 38042 | GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(98465), // Rule ID 1032 // |
| 38043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38044 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38045 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38047 | // MIs[0] rs1 |
| 38048 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38049 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38050 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38051 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>> => (AMOMAX_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38052 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 38053 | GIR_RootConstrainSelectedInstOperands, |
| 38054 | // GIR_Coverage, 1032, |
| 38055 | GIR_Done, |
| 38056 | // Label 2680: @98465 |
| 38057 | GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(98506), // Rule ID 1034 // |
| 38058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38059 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38060 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38062 | // MIs[0] rs1 |
| 38063 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38064 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38066 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>> => (AMOMAX_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38067 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 38068 | GIR_RootConstrainSelectedInstOperands, |
| 38069 | // GIR_Coverage, 1034, |
| 38070 | GIR_Done, |
| 38071 | // Label 2681: @98506 |
| 38072 | GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(98547), // Rule ID 1036 // |
| 38073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38074 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38075 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38077 | // MIs[0] rs1 |
| 38078 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38080 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38081 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>> => (AMOMAX_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38082 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 38083 | GIR_RootConstrainSelectedInstOperands, |
| 38084 | // GIR_Coverage, 1036, |
| 38085 | GIR_Done, |
| 38086 | // Label 2682: @98547 |
| 38087 | GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(98588), // Rule ID 1038 // |
| 38088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38089 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38090 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38092 | // MIs[0] rs1 |
| 38093 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38094 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38096 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>> => (AMOMAX_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38097 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 38098 | GIR_RootConstrainSelectedInstOperands, |
| 38099 | // GIR_Coverage, 1038, |
| 38100 | GIR_Done, |
| 38101 | // Label 2683: @98588 |
| 38102 | GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(98629), // Rule ID 1040 // |
| 38103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38104 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38105 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38107 | // MIs[0] rs1 |
| 38108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38110 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38111 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>> => (AMOMAX_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38112 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_B), |
| 38113 | GIR_RootConstrainSelectedInstOperands, |
| 38114 | // GIR_Coverage, 1040, |
| 38115 | GIR_Done, |
| 38116 | // Label 2684: @98629 |
| 38117 | GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(98670), // Rule ID 1202 // |
| 38118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38119 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38120 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38122 | // MIs[0] rs1 |
| 38123 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38124 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38125 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38126 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>> => (AMOMAX_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38127 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 38128 | GIR_RootConstrainSelectedInstOperands, |
| 38129 | // GIR_Coverage, 1202, |
| 38130 | GIR_Done, |
| 38131 | // Label 2685: @98670 |
| 38132 | GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(98711), // Rule ID 1204 // |
| 38133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38134 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38135 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38137 | // MIs[0] rs1 |
| 38138 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38140 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38141 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>> => (AMOMAX_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38142 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_AQ), |
| 38143 | GIR_RootConstrainSelectedInstOperands, |
| 38144 | // GIR_Coverage, 1204, |
| 38145 | GIR_Done, |
| 38146 | // Label 2686: @98711 |
| 38147 | GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(98752), // Rule ID 1206 // |
| 38148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38149 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38150 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38152 | // MIs[0] rs1 |
| 38153 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38154 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38155 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38156 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>> => (AMOMAX_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38157 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_RL), |
| 38158 | GIR_RootConstrainSelectedInstOperands, |
| 38159 | // GIR_Coverage, 1206, |
| 38160 | GIR_Done, |
| 38161 | // Label 2687: @98752 |
| 38162 | GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(98793), // Rule ID 1208 // |
| 38163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38164 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38165 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38167 | // MIs[0] rs1 |
| 38168 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38169 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38170 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38171 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>> => (AMOMAX_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38172 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_AQ_RL), |
| 38173 | GIR_RootConstrainSelectedInstOperands, |
| 38174 | // GIR_Coverage, 1208, |
| 38175 | GIR_Done, |
| 38176 | // Label 2688: @98793 |
| 38177 | GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(98834), // Rule ID 1210 // |
| 38178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 38179 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38180 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38182 | // MIs[0] rs1 |
| 38183 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38185 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38186 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>> => (AMOMAX_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38187 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H_AQ_RL), |
| 38188 | GIR_RootConstrainSelectedInstOperands, |
| 38189 | // GIR_Coverage, 1210, |
| 38190 | GIR_Done, |
| 38191 | // Label 2689: @98834 |
| 38192 | GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(98875), // Rule ID 1212 // |
| 38193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38194 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38195 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38197 | // MIs[0] rs1 |
| 38198 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38199 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38200 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38201 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>> => (AMOMAX_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38202 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 38203 | GIR_RootConstrainSelectedInstOperands, |
| 38204 | // GIR_Coverage, 1212, |
| 38205 | GIR_Done, |
| 38206 | // Label 2690: @98875 |
| 38207 | GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(98916), // Rule ID 1214 // |
| 38208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38209 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38210 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38212 | // MIs[0] rs1 |
| 38213 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38215 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38216 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>> => (AMOMAX_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38217 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 38218 | GIR_RootConstrainSelectedInstOperands, |
| 38219 | // GIR_Coverage, 1214, |
| 38220 | GIR_Done, |
| 38221 | // Label 2691: @98916 |
| 38222 | GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(98957), // Rule ID 1216 // |
| 38223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38224 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38225 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38227 | // MIs[0] rs1 |
| 38228 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38229 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38230 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38231 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>> => (AMOMAX_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38232 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 38233 | GIR_RootConstrainSelectedInstOperands, |
| 38234 | // GIR_Coverage, 1216, |
| 38235 | GIR_Done, |
| 38236 | // Label 2692: @98957 |
| 38237 | GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(98998), // Rule ID 1218 // |
| 38238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38239 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38240 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38242 | // MIs[0] rs1 |
| 38243 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38244 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38245 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38246 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>> => (AMOMAX_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38247 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 38248 | GIR_RootConstrainSelectedInstOperands, |
| 38249 | // GIR_Coverage, 1218, |
| 38250 | GIR_Done, |
| 38251 | // Label 2693: @98998 |
| 38252 | GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(99039), // Rule ID 1220 // |
| 38253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 38254 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38255 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38257 | // MIs[0] rs1 |
| 38258 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38261 | // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>> => (AMOMAX_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 38262 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAX_H), |
| 38263 | GIR_RootConstrainSelectedInstOperands, |
| 38264 | // GIR_Coverage, 1220, |
| 38265 | GIR_Done, |
| 38266 | // Label 2694: @99039 |
| 38267 | GIM_Reject, |
| 38268 | // Label 2654: @99040 |
| 38269 | GIM_Reject, |
| 38270 | // Label 2602: @99041 |
| 38271 | GIM_Reject, |
| 38272 | // Label 30: @99042 |
| 38273 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2697*/ GIMT_Encode4(102771), |
| 38274 | /*GILLT_s32*//*Label 2695*/ GIMT_Encode4(99061), |
| 38275 | /*GILLT_s64*//*Label 2696*/ GIMT_Encode4(101121), |
| 38276 | // Label 2695: @99061 |
| 38277 | GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(101120), |
| 38278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38279 | GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(99110), // Rule ID 493 // |
| 38280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38281 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38282 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38284 | // MIs[0] rs1 |
| 38285 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38288 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38289 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38290 | GIR_RootConstrainSelectedInstOperands, |
| 38291 | // GIR_Coverage, 493, |
| 38292 | GIR_Done, |
| 38293 | // Label 2699: @99110 |
| 38294 | GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(99151), // Rule ID 495 // |
| 38295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38296 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38297 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38299 | // MIs[0] rs1 |
| 38300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38301 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38302 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38303 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38304 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ), |
| 38305 | GIR_RootConstrainSelectedInstOperands, |
| 38306 | // GIR_Coverage, 495, |
| 38307 | GIR_Done, |
| 38308 | // Label 2700: @99151 |
| 38309 | GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(99192), // Rule ID 497 // |
| 38310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38311 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38312 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38314 | // MIs[0] rs1 |
| 38315 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38316 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38318 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38319 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_RL), |
| 38320 | GIR_RootConstrainSelectedInstOperands, |
| 38321 | // GIR_Coverage, 497, |
| 38322 | GIR_Done, |
| 38323 | // Label 2701: @99192 |
| 38324 | GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(99233), // Rule ID 499 // |
| 38325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38326 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38327 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38329 | // MIs[0] rs1 |
| 38330 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38332 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38333 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38334 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 38335 | GIR_RootConstrainSelectedInstOperands, |
| 38336 | // GIR_Coverage, 499, |
| 38337 | GIR_Done, |
| 38338 | // Label 2702: @99233 |
| 38339 | GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(99274), // Rule ID 501 // |
| 38340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38341 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38344 | // MIs[0] rs1 |
| 38345 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38346 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38348 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38349 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 38350 | GIR_RootConstrainSelectedInstOperands, |
| 38351 | // GIR_Coverage, 501, |
| 38352 | GIR_Done, |
| 38353 | // Label 2703: @99274 |
| 38354 | GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(99315), // Rule ID 503 // |
| 38355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38356 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38357 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38359 | // MIs[0] rs1 |
| 38360 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38361 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38362 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38363 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38364 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38365 | GIR_RootConstrainSelectedInstOperands, |
| 38366 | // GIR_Coverage, 503, |
| 38367 | GIR_Done, |
| 38368 | // Label 2704: @99315 |
| 38369 | GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(99356), // Rule ID 505 // |
| 38370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38371 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38372 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38374 | // MIs[0] rs1 |
| 38375 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38378 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38380 | GIR_RootConstrainSelectedInstOperands, |
| 38381 | // GIR_Coverage, 505, |
| 38382 | GIR_Done, |
| 38383 | // Label 2705: @99356 |
| 38384 | GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(99397), // Rule ID 507 // |
| 38385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38386 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38387 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38389 | // MIs[0] rs1 |
| 38390 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38391 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38392 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38393 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38394 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38395 | GIR_RootConstrainSelectedInstOperands, |
| 38396 | // GIR_Coverage, 507, |
| 38397 | GIR_Done, |
| 38398 | // Label 2706: @99397 |
| 38399 | GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(99438), // Rule ID 509 // |
| 38400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38401 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38402 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38404 | // MIs[0] rs1 |
| 38405 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38408 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38409 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38410 | GIR_RootConstrainSelectedInstOperands, |
| 38411 | // GIR_Coverage, 509, |
| 38412 | GIR_Done, |
| 38413 | // Label 2707: @99438 |
| 38414 | GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(99479), // Rule ID 511 // |
| 38415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38416 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38419 | // MIs[0] rs1 |
| 38420 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38422 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38423 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38424 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38425 | GIR_RootConstrainSelectedInstOperands, |
| 38426 | // GIR_Coverage, 511, |
| 38427 | GIR_Done, |
| 38428 | // Label 2708: @99479 |
| 38429 | GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(99520), // Rule ID 810 // |
| 38430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 38431 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38432 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38434 | // MIs[0] rs1 |
| 38435 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38436 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38437 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38438 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38439 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38440 | GIR_RootConstrainSelectedInstOperands, |
| 38441 | // GIR_Coverage, 810, |
| 38442 | GIR_Done, |
| 38443 | // Label 2709: @99520 |
| 38444 | GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(99561), // Rule ID 811 // |
| 38445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38446 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38447 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38449 | // MIs[0] rs1 |
| 38450 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38451 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38452 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38453 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38454 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38455 | GIR_RootConstrainSelectedInstOperands, |
| 38456 | // GIR_Coverage, 811, |
| 38457 | GIR_Done, |
| 38458 | // Label 2710: @99561 |
| 38459 | GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(99602), // Rule ID 812 // |
| 38460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 38461 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38462 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38464 | // MIs[0] rs1 |
| 38465 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38466 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38467 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38468 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38469 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ), |
| 38470 | GIR_RootConstrainSelectedInstOperands, |
| 38471 | // GIR_Coverage, 812, |
| 38472 | GIR_Done, |
| 38473 | // Label 2711: @99602 |
| 38474 | GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(99643), // Rule ID 813 // |
| 38475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38476 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38477 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38479 | // MIs[0] rs1 |
| 38480 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38481 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38482 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38483 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38484 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ), |
| 38485 | GIR_RootConstrainSelectedInstOperands, |
| 38486 | // GIR_Coverage, 813, |
| 38487 | GIR_Done, |
| 38488 | // Label 2712: @99643 |
| 38489 | GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(99684), // Rule ID 814 // |
| 38490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 38491 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38492 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38494 | // MIs[0] rs1 |
| 38495 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38496 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38497 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38498 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38499 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_RL), |
| 38500 | GIR_RootConstrainSelectedInstOperands, |
| 38501 | // GIR_Coverage, 814, |
| 38502 | GIR_Done, |
| 38503 | // Label 2713: @99684 |
| 38504 | GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(99725), // Rule ID 815 // |
| 38505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38506 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38507 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38509 | // MIs[0] rs1 |
| 38510 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38511 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38512 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38513 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38514 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_RL), |
| 38515 | GIR_RootConstrainSelectedInstOperands, |
| 38516 | // GIR_Coverage, 815, |
| 38517 | GIR_Done, |
| 38518 | // Label 2714: @99725 |
| 38519 | GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(99766), // Rule ID 816 // |
| 38520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 38521 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38522 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38524 | // MIs[0] rs1 |
| 38525 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38526 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38527 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38528 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38529 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 38530 | GIR_RootConstrainSelectedInstOperands, |
| 38531 | // GIR_Coverage, 816, |
| 38532 | GIR_Done, |
| 38533 | // Label 2715: @99766 |
| 38534 | GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(99807), // Rule ID 817 // |
| 38535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38536 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38537 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38539 | // MIs[0] rs1 |
| 38540 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38541 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38542 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38543 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38544 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 38545 | GIR_RootConstrainSelectedInstOperands, |
| 38546 | // GIR_Coverage, 817, |
| 38547 | GIR_Done, |
| 38548 | // Label 2716: @99807 |
| 38549 | GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(99848), // Rule ID 818 // |
| 38550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 38551 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38552 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38554 | // MIs[0] rs1 |
| 38555 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38556 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38557 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38558 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38559 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 38560 | GIR_RootConstrainSelectedInstOperands, |
| 38561 | // GIR_Coverage, 818, |
| 38562 | GIR_Done, |
| 38563 | // Label 2717: @99848 |
| 38564 | GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(99889), // Rule ID 819 // |
| 38565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 38566 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38567 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38568 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38569 | // MIs[0] rs1 |
| 38570 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38571 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38572 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38573 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38574 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 38575 | GIR_RootConstrainSelectedInstOperands, |
| 38576 | // GIR_Coverage, 819, |
| 38577 | GIR_Done, |
| 38578 | // Label 2718: @99889 |
| 38579 | GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(99930), // Rule ID 820 // |
| 38580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 38581 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38582 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38584 | // MIs[0] rs1 |
| 38585 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38586 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38588 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38589 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38590 | GIR_RootConstrainSelectedInstOperands, |
| 38591 | // GIR_Coverage, 820, |
| 38592 | GIR_Done, |
| 38593 | // Label 2719: @99930 |
| 38594 | GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(99971), // Rule ID 821 // |
| 38595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38596 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38599 | // MIs[0] rs1 |
| 38600 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38601 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38602 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38603 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38604 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38605 | GIR_RootConstrainSelectedInstOperands, |
| 38606 | // GIR_Coverage, 821, |
| 38607 | GIR_Done, |
| 38608 | // Label 2720: @99971 |
| 38609 | GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(100012), // Rule ID 822 // |
| 38610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 38611 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38614 | // MIs[0] rs1 |
| 38615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38616 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38618 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38619 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38620 | GIR_RootConstrainSelectedInstOperands, |
| 38621 | // GIR_Coverage, 822, |
| 38622 | GIR_Done, |
| 38623 | // Label 2721: @100012 |
| 38624 | GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(100053), // Rule ID 823 // |
| 38625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38626 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38627 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38629 | // MIs[0] rs1 |
| 38630 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38631 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38632 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38633 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38634 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38635 | GIR_RootConstrainSelectedInstOperands, |
| 38636 | // GIR_Coverage, 823, |
| 38637 | GIR_Done, |
| 38638 | // Label 2722: @100053 |
| 38639 | GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(100094), // Rule ID 824 // |
| 38640 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 38641 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38642 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38644 | // MIs[0] rs1 |
| 38645 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38646 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38648 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38649 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38650 | GIR_RootConstrainSelectedInstOperands, |
| 38651 | // GIR_Coverage, 824, |
| 38652 | GIR_Done, |
| 38653 | // Label 2723: @100094 |
| 38654 | GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(100135), // Rule ID 825 // |
| 38655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38656 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38657 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38659 | // MIs[0] rs1 |
| 38660 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38661 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38662 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38663 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38664 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38665 | GIR_RootConstrainSelectedInstOperands, |
| 38666 | // GIR_Coverage, 825, |
| 38667 | GIR_Done, |
| 38668 | // Label 2724: @100135 |
| 38669 | GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(100176), // Rule ID 826 // |
| 38670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 38671 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38672 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38674 | // MIs[0] rs1 |
| 38675 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38676 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38677 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38678 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38679 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38680 | GIR_RootConstrainSelectedInstOperands, |
| 38681 | // GIR_Coverage, 826, |
| 38682 | GIR_Done, |
| 38683 | // Label 2725: @100176 |
| 38684 | GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(100217), // Rule ID 827 // |
| 38685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38686 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38687 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38689 | // MIs[0] rs1 |
| 38690 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38691 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38692 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38693 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38694 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38695 | GIR_RootConstrainSelectedInstOperands, |
| 38696 | // GIR_Coverage, 827, |
| 38697 | GIR_Done, |
| 38698 | // Label 2726: @100217 |
| 38699 | GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(100258), // Rule ID 828 // |
| 38700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 38701 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38702 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38704 | // MIs[0] rs1 |
| 38705 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38708 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38709 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38710 | GIR_RootConstrainSelectedInstOperands, |
| 38711 | // GIR_Coverage, 828, |
| 38712 | GIR_Done, |
| 38713 | // Label 2727: @100258 |
| 38714 | GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(100299), // Rule ID 829 // |
| 38715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 38716 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 38717 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38719 | // MIs[0] rs1 |
| 38720 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38721 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38722 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38723 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38724 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 38725 | GIR_RootConstrainSelectedInstOperands, |
| 38726 | // GIR_Coverage, 829, |
| 38727 | GIR_Done, |
| 38728 | // Label 2728: @100299 |
| 38729 | GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(100340), // Rule ID 1043 // |
| 38730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38731 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38734 | // MIs[0] rs1 |
| 38735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38738 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>> => (AMOMIN_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38739 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 38740 | GIR_RootConstrainSelectedInstOperands, |
| 38741 | // GIR_Coverage, 1043, |
| 38742 | GIR_Done, |
| 38743 | // Label 2729: @100340 |
| 38744 | GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(100381), // Rule ID 1045 // |
| 38745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38746 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38749 | // MIs[0] rs1 |
| 38750 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38752 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38753 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>> => (AMOMIN_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38754 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_AQ), |
| 38755 | GIR_RootConstrainSelectedInstOperands, |
| 38756 | // GIR_Coverage, 1045, |
| 38757 | GIR_Done, |
| 38758 | // Label 2730: @100381 |
| 38759 | GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(100422), // Rule ID 1047 // |
| 38760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38761 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38762 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38764 | // MIs[0] rs1 |
| 38765 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38768 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>> => (AMOMIN_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38769 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_RL), |
| 38770 | GIR_RootConstrainSelectedInstOperands, |
| 38771 | // GIR_Coverage, 1047, |
| 38772 | GIR_Done, |
| 38773 | // Label 2731: @100422 |
| 38774 | GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(100463), // Rule ID 1049 // |
| 38775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38776 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38777 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38779 | // MIs[0] rs1 |
| 38780 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38782 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38783 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>> => (AMOMIN_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38784 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_AQ_RL), |
| 38785 | GIR_RootConstrainSelectedInstOperands, |
| 38786 | // GIR_Coverage, 1049, |
| 38787 | GIR_Done, |
| 38788 | // Label 2732: @100463 |
| 38789 | GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(100504), // Rule ID 1051 // |
| 38790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38791 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38792 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38794 | // MIs[0] rs1 |
| 38795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38798 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>> => (AMOMIN_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38799 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_AQ_RL), |
| 38800 | GIR_RootConstrainSelectedInstOperands, |
| 38801 | // GIR_Coverage, 1051, |
| 38802 | GIR_Done, |
| 38803 | // Label 2733: @100504 |
| 38804 | GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(100545), // Rule ID 1053 // |
| 38805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38806 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38807 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38809 | // MIs[0] rs1 |
| 38810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38812 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38813 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>> => (AMOMIN_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38814 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 38815 | GIR_RootConstrainSelectedInstOperands, |
| 38816 | // GIR_Coverage, 1053, |
| 38817 | GIR_Done, |
| 38818 | // Label 2734: @100545 |
| 38819 | GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(100586), // Rule ID 1055 // |
| 38820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38821 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38824 | // MIs[0] rs1 |
| 38825 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38828 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>> => (AMOMIN_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38829 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 38830 | GIR_RootConstrainSelectedInstOperands, |
| 38831 | // GIR_Coverage, 1055, |
| 38832 | GIR_Done, |
| 38833 | // Label 2735: @100586 |
| 38834 | GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(100627), // Rule ID 1057 // |
| 38835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38836 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38837 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38839 | // MIs[0] rs1 |
| 38840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38843 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>> => (AMOMIN_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38844 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 38845 | GIR_RootConstrainSelectedInstOperands, |
| 38846 | // GIR_Coverage, 1057, |
| 38847 | GIR_Done, |
| 38848 | // Label 2736: @100627 |
| 38849 | GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(100668), // Rule ID 1059 // |
| 38850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38851 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38852 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38854 | // MIs[0] rs1 |
| 38855 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38857 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38858 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>> => (AMOMIN_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38859 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 38860 | GIR_RootConstrainSelectedInstOperands, |
| 38861 | // GIR_Coverage, 1059, |
| 38862 | GIR_Done, |
| 38863 | // Label 2737: @100668 |
| 38864 | GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(100709), // Rule ID 1061 // |
| 38865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38866 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 38867 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38869 | // MIs[0] rs1 |
| 38870 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38872 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38873 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>> => (AMOMIN_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38874 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 38875 | GIR_RootConstrainSelectedInstOperands, |
| 38876 | // GIR_Coverage, 1061, |
| 38877 | GIR_Done, |
| 38878 | // Label 2738: @100709 |
| 38879 | GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(100750), // Rule ID 1223 // |
| 38880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38881 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38882 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38884 | // MIs[0] rs1 |
| 38885 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38888 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>> => (AMOMIN_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38889 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 38890 | GIR_RootConstrainSelectedInstOperands, |
| 38891 | // GIR_Coverage, 1223, |
| 38892 | GIR_Done, |
| 38893 | // Label 2739: @100750 |
| 38894 | GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(100791), // Rule ID 1225 // |
| 38895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38896 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38897 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38899 | // MIs[0] rs1 |
| 38900 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38901 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38902 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38903 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>> => (AMOMIN_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38904 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_AQ), |
| 38905 | GIR_RootConstrainSelectedInstOperands, |
| 38906 | // GIR_Coverage, 1225, |
| 38907 | GIR_Done, |
| 38908 | // Label 2740: @100791 |
| 38909 | GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(100832), // Rule ID 1227 // |
| 38910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38911 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38912 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38914 | // MIs[0] rs1 |
| 38915 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38916 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38917 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38918 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>> => (AMOMIN_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38919 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_RL), |
| 38920 | GIR_RootConstrainSelectedInstOperands, |
| 38921 | // GIR_Coverage, 1227, |
| 38922 | GIR_Done, |
| 38923 | // Label 2741: @100832 |
| 38924 | GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(100873), // Rule ID 1229 // |
| 38925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38926 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38927 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 38928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38929 | // MIs[0] rs1 |
| 38930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38931 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38932 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38933 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>> => (AMOMIN_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38934 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_AQ_RL), |
| 38935 | GIR_RootConstrainSelectedInstOperands, |
| 38936 | // GIR_Coverage, 1229, |
| 38937 | GIR_Done, |
| 38938 | // Label 2742: @100873 |
| 38939 | GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(100914), // Rule ID 1231 // |
| 38940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 38941 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38942 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 38943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38944 | // MIs[0] rs1 |
| 38945 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38948 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>> => (AMOMIN_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38949 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_AQ_RL), |
| 38950 | GIR_RootConstrainSelectedInstOperands, |
| 38951 | // GIR_Coverage, 1231, |
| 38952 | GIR_Done, |
| 38953 | // Label 2743: @100914 |
| 38954 | GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(100955), // Rule ID 1233 // |
| 38955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38956 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38957 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 38958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38959 | // MIs[0] rs1 |
| 38960 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38961 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38962 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38963 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>> => (AMOMIN_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38964 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 38965 | GIR_RootConstrainSelectedInstOperands, |
| 38966 | // GIR_Coverage, 1233, |
| 38967 | GIR_Done, |
| 38968 | // Label 2744: @100955 |
| 38969 | GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(100996), // Rule ID 1235 // |
| 38970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38971 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38972 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 38973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38974 | // MIs[0] rs1 |
| 38975 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38976 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38977 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38978 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>> => (AMOMIN_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38979 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 38980 | GIR_RootConstrainSelectedInstOperands, |
| 38981 | // GIR_Coverage, 1235, |
| 38982 | GIR_Done, |
| 38983 | // Label 2745: @100996 |
| 38984 | GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(101037), // Rule ID 1237 // |
| 38985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 38986 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 38987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 38988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38989 | // MIs[0] rs1 |
| 38990 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 38991 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38992 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 38993 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>> => (AMOMIN_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 38994 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 38995 | GIR_RootConstrainSelectedInstOperands, |
| 38996 | // GIR_Coverage, 1237, |
| 38997 | GIR_Done, |
| 38998 | // Label 2746: @101037 |
| 38999 | GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(101078), // Rule ID 1239 // |
| 39000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 39001 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39002 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39004 | // MIs[0] rs1 |
| 39005 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39008 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>> => (AMOMIN_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39009 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39010 | GIR_RootConstrainSelectedInstOperands, |
| 39011 | // GIR_Coverage, 1239, |
| 39012 | GIR_Done, |
| 39013 | // Label 2747: @101078 |
| 39014 | GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(101119), // Rule ID 1241 // |
| 39015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 39016 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39017 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39019 | // MIs[0] rs1 |
| 39020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39021 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39022 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39023 | // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>> => (AMOMIN_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39024 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39025 | GIR_RootConstrainSelectedInstOperands, |
| 39026 | // GIR_Coverage, 1241, |
| 39027 | GIR_Done, |
| 39028 | // Label 2748: @101119 |
| 39029 | GIM_Reject, |
| 39030 | // Label 2698: @101120 |
| 39031 | GIM_Reject, |
| 39032 | // Label 2696: @101121 |
| 39033 | GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(102770), |
| 39034 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39035 | GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(101170), // Rule ID 492 // |
| 39036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39037 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39038 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39040 | // MIs[0] rs1 |
| 39041 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39042 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39044 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39045 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 39046 | GIR_RootConstrainSelectedInstOperands, |
| 39047 | // GIR_Coverage, 492, |
| 39048 | GIR_Done, |
| 39049 | // Label 2750: @101170 |
| 39050 | GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(101211), // Rule ID 494 // |
| 39051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39052 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39053 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39054 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39055 | // MIs[0] rs1 |
| 39056 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39057 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39058 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39059 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39060 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ), |
| 39061 | GIR_RootConstrainSelectedInstOperands, |
| 39062 | // GIR_Coverage, 494, |
| 39063 | GIR_Done, |
| 39064 | // Label 2751: @101211 |
| 39065 | GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(101252), // Rule ID 496 // |
| 39066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39067 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39068 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39070 | // MIs[0] rs1 |
| 39071 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39072 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39073 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39074 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39075 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_RL), |
| 39076 | GIR_RootConstrainSelectedInstOperands, |
| 39077 | // GIR_Coverage, 496, |
| 39078 | GIR_Done, |
| 39079 | // Label 2752: @101252 |
| 39080 | GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(101293), // Rule ID 498 // |
| 39081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39082 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39083 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39085 | // MIs[0] rs1 |
| 39086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39087 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39088 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39089 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39090 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 39091 | GIR_RootConstrainSelectedInstOperands, |
| 39092 | // GIR_Coverage, 498, |
| 39093 | GIR_Done, |
| 39094 | // Label 2753: @101293 |
| 39095 | GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(101334), // Rule ID 500 // |
| 39096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39097 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39098 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39100 | // MIs[0] rs1 |
| 39101 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39102 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39104 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39105 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W_AQ_RL), |
| 39106 | GIR_RootConstrainSelectedInstOperands, |
| 39107 | // GIR_Coverage, 500, |
| 39108 | GIR_Done, |
| 39109 | // Label 2754: @101334 |
| 39110 | GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(101375), // Rule ID 502 // |
| 39111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39112 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39113 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39115 | // MIs[0] rs1 |
| 39116 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39117 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39118 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39119 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39120 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 39121 | GIR_RootConstrainSelectedInstOperands, |
| 39122 | // GIR_Coverage, 502, |
| 39123 | GIR_Done, |
| 39124 | // Label 2755: @101375 |
| 39125 | GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(101416), // Rule ID 504 // |
| 39126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39127 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39128 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39130 | // MIs[0] rs1 |
| 39131 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39132 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39134 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39135 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 39136 | GIR_RootConstrainSelectedInstOperands, |
| 39137 | // GIR_Coverage, 504, |
| 39138 | GIR_Done, |
| 39139 | // Label 2756: @101416 |
| 39140 | GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(101457), // Rule ID 506 // |
| 39141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39142 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39143 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39145 | // MIs[0] rs1 |
| 39146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39147 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39148 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39149 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39150 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 39151 | GIR_RootConstrainSelectedInstOperands, |
| 39152 | // GIR_Coverage, 506, |
| 39153 | GIR_Done, |
| 39154 | // Label 2757: @101457 |
| 39155 | GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(101498), // Rule ID 508 // |
| 39156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39157 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39158 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39160 | // MIs[0] rs1 |
| 39161 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39162 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39164 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39165 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 39166 | GIR_RootConstrainSelectedInstOperands, |
| 39167 | // GIR_Coverage, 508, |
| 39168 | GIR_Done, |
| 39169 | // Label 2758: @101498 |
| 39170 | GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(101539), // Rule ID 510 // |
| 39171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39172 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39173 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39175 | // MIs[0] rs1 |
| 39176 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39177 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39178 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39179 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39180 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_W), |
| 39181 | GIR_RootConstrainSelectedInstOperands, |
| 39182 | // GIR_Coverage, 510, |
| 39183 | GIR_Done, |
| 39184 | // Label 2759: @101539 |
| 39185 | GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(101580), // Rule ID 612 // |
| 39186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 39187 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39188 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39190 | // MIs[0] rs1 |
| 39191 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39192 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39193 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39194 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_monotonic>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39195 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D), |
| 39196 | GIR_RootConstrainSelectedInstOperands, |
| 39197 | // GIR_Coverage, 612, |
| 39198 | GIR_Done, |
| 39199 | // Label 2760: @101580 |
| 39200 | GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(101621), // Rule ID 613 // |
| 39201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 39202 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39203 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39205 | // MIs[0] rs1 |
| 39206 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39207 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39208 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39209 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acquire>> => (AMOMIN_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39210 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D_AQ), |
| 39211 | GIR_RootConstrainSelectedInstOperands, |
| 39212 | // GIR_Coverage, 613, |
| 39213 | GIR_Done, |
| 39214 | // Label 2761: @101621 |
| 39215 | GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(101662), // Rule ID 614 // |
| 39216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 39217 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39218 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39220 | // MIs[0] rs1 |
| 39221 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39222 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39223 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39224 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_release>> => (AMOMIN_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39225 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D_RL), |
| 39226 | GIR_RootConstrainSelectedInstOperands, |
| 39227 | // GIR_Coverage, 614, |
| 39228 | GIR_Done, |
| 39229 | // Label 2762: @101662 |
| 39230 | GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(101703), // Rule ID 615 // |
| 39231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 39232 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39233 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39235 | // MIs[0] rs1 |
| 39236 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39237 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39238 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39239 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39240 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D_AQ_RL), |
| 39241 | GIR_RootConstrainSelectedInstOperands, |
| 39242 | // GIR_Coverage, 615, |
| 39243 | GIR_Done, |
| 39244 | // Label 2763: @101703 |
| 39245 | GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(101744), // Rule ID 616 // |
| 39246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 39247 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39248 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39250 | // MIs[0] rs1 |
| 39251 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39252 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39253 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39254 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39255 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D_AQ_RL), |
| 39256 | GIR_RootConstrainSelectedInstOperands, |
| 39257 | // GIR_Coverage, 616, |
| 39258 | GIR_Done, |
| 39259 | // Label 2764: @101744 |
| 39260 | GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(101785), // Rule ID 617 // |
| 39261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 39262 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39263 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39265 | // MIs[0] rs1 |
| 39266 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39267 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39268 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39269 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_monotonic>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39270 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D), |
| 39271 | GIR_RootConstrainSelectedInstOperands, |
| 39272 | // GIR_Coverage, 617, |
| 39273 | GIR_Done, |
| 39274 | // Label 2765: @101785 |
| 39275 | GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(101826), // Rule ID 618 // |
| 39276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 39277 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39278 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39280 | // MIs[0] rs1 |
| 39281 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39282 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39283 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39284 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acquire>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39285 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D), |
| 39286 | GIR_RootConstrainSelectedInstOperands, |
| 39287 | // GIR_Coverage, 618, |
| 39288 | GIR_Done, |
| 39289 | // Label 2766: @101826 |
| 39290 | GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(101867), // Rule ID 619 // |
| 39291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 39292 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39293 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39295 | // MIs[0] rs1 |
| 39296 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39297 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39298 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39299 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_release>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39300 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D), |
| 39301 | GIR_RootConstrainSelectedInstOperands, |
| 39302 | // GIR_Coverage, 619, |
| 39303 | GIR_Done, |
| 39304 | // Label 2767: @101867 |
| 39305 | GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(101908), // Rule ID 620 // |
| 39306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 39307 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39308 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39310 | // MIs[0] rs1 |
| 39311 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39312 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39313 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39314 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acq_rel>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39315 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D), |
| 39316 | GIR_RootConstrainSelectedInstOperands, |
| 39317 | // GIR_Coverage, 620, |
| 39318 | GIR_Done, |
| 39319 | // Label 2768: @101908 |
| 39320 | GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(101949), // Rule ID 621 // |
| 39321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 39322 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 39323 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39325 | // MIs[0] rs1 |
| 39326 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39327 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39328 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39329 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_seq_cst>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39330 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_D), |
| 39331 | GIR_RootConstrainSelectedInstOperands, |
| 39332 | // GIR_Coverage, 621, |
| 39333 | GIR_Done, |
| 39334 | // Label 2769: @101949 |
| 39335 | GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(101990), // Rule ID 1042 // |
| 39336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39337 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39338 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39340 | // MIs[0] rs1 |
| 39341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39342 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39343 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39344 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>> => (AMOMIN_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39345 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 39346 | GIR_RootConstrainSelectedInstOperands, |
| 39347 | // GIR_Coverage, 1042, |
| 39348 | GIR_Done, |
| 39349 | // Label 2770: @101990 |
| 39350 | GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(102031), // Rule ID 1044 // |
| 39351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39352 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39353 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39355 | // MIs[0] rs1 |
| 39356 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39357 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39358 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39359 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>> => (AMOMIN_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39360 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_AQ), |
| 39361 | GIR_RootConstrainSelectedInstOperands, |
| 39362 | // GIR_Coverage, 1044, |
| 39363 | GIR_Done, |
| 39364 | // Label 2771: @102031 |
| 39365 | GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(102072), // Rule ID 1046 // |
| 39366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39367 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39368 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39370 | // MIs[0] rs1 |
| 39371 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39374 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>> => (AMOMIN_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39375 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_RL), |
| 39376 | GIR_RootConstrainSelectedInstOperands, |
| 39377 | // GIR_Coverage, 1046, |
| 39378 | GIR_Done, |
| 39379 | // Label 2772: @102072 |
| 39380 | GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(102113), // Rule ID 1048 // |
| 39381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39382 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39385 | // MIs[0] rs1 |
| 39386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39387 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39388 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39389 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>> => (AMOMIN_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39390 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_AQ_RL), |
| 39391 | GIR_RootConstrainSelectedInstOperands, |
| 39392 | // GIR_Coverage, 1048, |
| 39393 | GIR_Done, |
| 39394 | // Label 2773: @102113 |
| 39395 | GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(102154), // Rule ID 1050 // |
| 39396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39397 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39398 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39400 | // MIs[0] rs1 |
| 39401 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39402 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39403 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39404 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>> => (AMOMIN_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39405 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B_AQ_RL), |
| 39406 | GIR_RootConstrainSelectedInstOperands, |
| 39407 | // GIR_Coverage, 1050, |
| 39408 | GIR_Done, |
| 39409 | // Label 2774: @102154 |
| 39410 | GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(102195), // Rule ID 1052 // |
| 39411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39412 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39413 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39415 | // MIs[0] rs1 |
| 39416 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39417 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39418 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39419 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>> => (AMOMIN_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39420 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 39421 | GIR_RootConstrainSelectedInstOperands, |
| 39422 | // GIR_Coverage, 1052, |
| 39423 | GIR_Done, |
| 39424 | // Label 2775: @102195 |
| 39425 | GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(102236), // Rule ID 1054 // |
| 39426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39427 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39428 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39430 | // MIs[0] rs1 |
| 39431 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39432 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39434 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>> => (AMOMIN_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39435 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 39436 | GIR_RootConstrainSelectedInstOperands, |
| 39437 | // GIR_Coverage, 1054, |
| 39438 | GIR_Done, |
| 39439 | // Label 2776: @102236 |
| 39440 | GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(102277), // Rule ID 1056 // |
| 39441 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39442 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39443 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39445 | // MIs[0] rs1 |
| 39446 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39447 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39448 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39449 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>> => (AMOMIN_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39450 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 39451 | GIR_RootConstrainSelectedInstOperands, |
| 39452 | // GIR_Coverage, 1056, |
| 39453 | GIR_Done, |
| 39454 | // Label 2777: @102277 |
| 39455 | GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(102318), // Rule ID 1058 // |
| 39456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39457 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39458 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39460 | // MIs[0] rs1 |
| 39461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39464 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>> => (AMOMIN_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39465 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 39466 | GIR_RootConstrainSelectedInstOperands, |
| 39467 | // GIR_Coverage, 1058, |
| 39468 | GIR_Done, |
| 39469 | // Label 2778: @102318 |
| 39470 | GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(102359), // Rule ID 1060 // |
| 39471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39472 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39475 | // MIs[0] rs1 |
| 39476 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39477 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39478 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39479 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>> => (AMOMIN_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39480 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_B), |
| 39481 | GIR_RootConstrainSelectedInstOperands, |
| 39482 | // GIR_Coverage, 1060, |
| 39483 | GIR_Done, |
| 39484 | // Label 2779: @102359 |
| 39485 | GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(102400), // Rule ID 1222 // |
| 39486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39487 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39488 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39490 | // MIs[0] rs1 |
| 39491 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39493 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39494 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>> => (AMOMIN_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39495 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39496 | GIR_RootConstrainSelectedInstOperands, |
| 39497 | // GIR_Coverage, 1222, |
| 39498 | GIR_Done, |
| 39499 | // Label 2780: @102400 |
| 39500 | GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(102441), // Rule ID 1224 // |
| 39501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39502 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39503 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39505 | // MIs[0] rs1 |
| 39506 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39507 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39508 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39509 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>> => (AMOMIN_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39510 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_AQ), |
| 39511 | GIR_RootConstrainSelectedInstOperands, |
| 39512 | // GIR_Coverage, 1224, |
| 39513 | GIR_Done, |
| 39514 | // Label 2781: @102441 |
| 39515 | GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(102482), // Rule ID 1226 // |
| 39516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39517 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39518 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39520 | // MIs[0] rs1 |
| 39521 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39524 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>> => (AMOMIN_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39525 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_RL), |
| 39526 | GIR_RootConstrainSelectedInstOperands, |
| 39527 | // GIR_Coverage, 1226, |
| 39528 | GIR_Done, |
| 39529 | // Label 2782: @102482 |
| 39530 | GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(102523), // Rule ID 1228 // |
| 39531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39532 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39533 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39535 | // MIs[0] rs1 |
| 39536 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39537 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39538 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39539 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>> => (AMOMIN_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39540 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_AQ_RL), |
| 39541 | GIR_RootConstrainSelectedInstOperands, |
| 39542 | // GIR_Coverage, 1228, |
| 39543 | GIR_Done, |
| 39544 | // Label 2783: @102523 |
| 39545 | GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(102564), // Rule ID 1230 // |
| 39546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 39547 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39548 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39550 | // MIs[0] rs1 |
| 39551 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39554 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>> => (AMOMIN_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39555 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H_AQ_RL), |
| 39556 | GIR_RootConstrainSelectedInstOperands, |
| 39557 | // GIR_Coverage, 1230, |
| 39558 | GIR_Done, |
| 39559 | // Label 2784: @102564 |
| 39560 | GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(102605), // Rule ID 1232 // |
| 39561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39562 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39563 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39565 | // MIs[0] rs1 |
| 39566 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39567 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39568 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39569 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>> => (AMOMIN_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39570 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39571 | GIR_RootConstrainSelectedInstOperands, |
| 39572 | // GIR_Coverage, 1232, |
| 39573 | GIR_Done, |
| 39574 | // Label 2785: @102605 |
| 39575 | GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(102646), // Rule ID 1234 // |
| 39576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39577 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39580 | // MIs[0] rs1 |
| 39581 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39582 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39583 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39584 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>> => (AMOMIN_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39585 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39586 | GIR_RootConstrainSelectedInstOperands, |
| 39587 | // GIR_Coverage, 1234, |
| 39588 | GIR_Done, |
| 39589 | // Label 2786: @102646 |
| 39590 | GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(102687), // Rule ID 1236 // |
| 39591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39592 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39593 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39595 | // MIs[0] rs1 |
| 39596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39597 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39598 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39599 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>> => (AMOMIN_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39600 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39601 | GIR_RootConstrainSelectedInstOperands, |
| 39602 | // GIR_Coverage, 1236, |
| 39603 | GIR_Done, |
| 39604 | // Label 2787: @102687 |
| 39605 | GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(102728), // Rule ID 1238 // |
| 39606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39607 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39608 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39610 | // MIs[0] rs1 |
| 39611 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39612 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39614 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>> => (AMOMIN_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39615 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39616 | GIR_RootConstrainSelectedInstOperands, |
| 39617 | // GIR_Coverage, 1238, |
| 39618 | GIR_Done, |
| 39619 | // Label 2788: @102728 |
| 39620 | GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(102769), // Rule ID 1240 // |
| 39621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 39622 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39623 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39625 | // MIs[0] rs1 |
| 39626 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39627 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39628 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39629 | // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>> => (AMOMIN_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 39630 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMIN_H), |
| 39631 | GIR_RootConstrainSelectedInstOperands, |
| 39632 | // GIR_Coverage, 1240, |
| 39633 | GIR_Done, |
| 39634 | // Label 2789: @102769 |
| 39635 | GIM_Reject, |
| 39636 | // Label 2749: @102770 |
| 39637 | GIM_Reject, |
| 39638 | // Label 2697: @102771 |
| 39639 | GIM_Reject, |
| 39640 | // Label 31: @102772 |
| 39641 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2792*/ GIMT_Encode4(106501), |
| 39642 | /*GILLT_s32*//*Label 2790*/ GIMT_Encode4(102791), |
| 39643 | /*GILLT_s64*//*Label 2791*/ GIMT_Encode4(104851), |
| 39644 | // Label 2790: @102791 |
| 39645 | GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(104850), |
| 39646 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39647 | GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(102840), // Rule ID 513 // |
| 39648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39649 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39650 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39651 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39652 | // MIs[0] rs1 |
| 39653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39654 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39656 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39657 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39658 | GIR_RootConstrainSelectedInstOperands, |
| 39659 | // GIR_Coverage, 513, |
| 39660 | GIR_Done, |
| 39661 | // Label 2794: @102840 |
| 39662 | GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(102881), // Rule ID 515 // |
| 39663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39664 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39665 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39667 | // MIs[0] rs1 |
| 39668 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39669 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39670 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39671 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39672 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ), |
| 39673 | GIR_RootConstrainSelectedInstOperands, |
| 39674 | // GIR_Coverage, 515, |
| 39675 | GIR_Done, |
| 39676 | // Label 2795: @102881 |
| 39677 | GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(102922), // Rule ID 517 // |
| 39678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39679 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39680 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39681 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39682 | // MIs[0] rs1 |
| 39683 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39684 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39685 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39686 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39687 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_RL), |
| 39688 | GIR_RootConstrainSelectedInstOperands, |
| 39689 | // GIR_Coverage, 517, |
| 39690 | GIR_Done, |
| 39691 | // Label 2796: @102922 |
| 39692 | GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(102963), // Rule ID 519 // |
| 39693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39694 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39697 | // MIs[0] rs1 |
| 39698 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39699 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39700 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39701 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39702 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 39703 | GIR_RootConstrainSelectedInstOperands, |
| 39704 | // GIR_Coverage, 519, |
| 39705 | GIR_Done, |
| 39706 | // Label 2797: @102963 |
| 39707 | GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(103004), // Rule ID 521 // |
| 39708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39709 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39710 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39712 | // MIs[0] rs1 |
| 39713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39715 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39716 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39717 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 39718 | GIR_RootConstrainSelectedInstOperands, |
| 39719 | // GIR_Coverage, 521, |
| 39720 | GIR_Done, |
| 39721 | // Label 2798: @103004 |
| 39722 | GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(103045), // Rule ID 523 // |
| 39723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39724 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39725 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39727 | // MIs[0] rs1 |
| 39728 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39729 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39730 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39731 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39732 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39733 | GIR_RootConstrainSelectedInstOperands, |
| 39734 | // GIR_Coverage, 523, |
| 39735 | GIR_Done, |
| 39736 | // Label 2799: @103045 |
| 39737 | GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(103086), // Rule ID 525 // |
| 39738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39739 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39740 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39742 | // MIs[0] rs1 |
| 39743 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39744 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39746 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39747 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39748 | GIR_RootConstrainSelectedInstOperands, |
| 39749 | // GIR_Coverage, 525, |
| 39750 | GIR_Done, |
| 39751 | // Label 2800: @103086 |
| 39752 | GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(103127), // Rule ID 527 // |
| 39753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39754 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39755 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39757 | // MIs[0] rs1 |
| 39758 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39761 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39762 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39763 | GIR_RootConstrainSelectedInstOperands, |
| 39764 | // GIR_Coverage, 527, |
| 39765 | GIR_Done, |
| 39766 | // Label 2801: @103127 |
| 39767 | GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(103168), // Rule ID 529 // |
| 39768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39769 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39770 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39772 | // MIs[0] rs1 |
| 39773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39774 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39776 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39777 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39778 | GIR_RootConstrainSelectedInstOperands, |
| 39779 | // GIR_Coverage, 529, |
| 39780 | GIR_Done, |
| 39781 | // Label 2802: @103168 |
| 39782 | GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(103209), // Rule ID 531 // |
| 39783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39784 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39785 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39787 | // MIs[0] rs1 |
| 39788 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39789 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39790 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39791 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39792 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39793 | GIR_RootConstrainSelectedInstOperands, |
| 39794 | // GIR_Coverage, 531, |
| 39795 | GIR_Done, |
| 39796 | // Label 2803: @103209 |
| 39797 | GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(103250), // Rule ID 830 // |
| 39798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39799 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39800 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39802 | // MIs[0] rs1 |
| 39803 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39804 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39806 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39807 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39808 | GIR_RootConstrainSelectedInstOperands, |
| 39809 | // GIR_Coverage, 830, |
| 39810 | GIR_Done, |
| 39811 | // Label 2804: @103250 |
| 39812 | GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(103291), // Rule ID 831 // |
| 39813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39814 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39815 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39817 | // MIs[0] rs1 |
| 39818 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39820 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39821 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39822 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39823 | GIR_RootConstrainSelectedInstOperands, |
| 39824 | // GIR_Coverage, 831, |
| 39825 | GIR_Done, |
| 39826 | // Label 2805: @103291 |
| 39827 | GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(103332), // Rule ID 832 // |
| 39828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39829 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39830 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39832 | // MIs[0] rs1 |
| 39833 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39834 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39835 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39836 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39837 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ), |
| 39838 | GIR_RootConstrainSelectedInstOperands, |
| 39839 | // GIR_Coverage, 832, |
| 39840 | GIR_Done, |
| 39841 | // Label 2806: @103332 |
| 39842 | GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(103373), // Rule ID 833 // |
| 39843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39844 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39845 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39847 | // MIs[0] rs1 |
| 39848 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39849 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39850 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39851 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39852 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ), |
| 39853 | GIR_RootConstrainSelectedInstOperands, |
| 39854 | // GIR_Coverage, 833, |
| 39855 | GIR_Done, |
| 39856 | // Label 2807: @103373 |
| 39857 | GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(103414), // Rule ID 834 // |
| 39858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39859 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39860 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39862 | // MIs[0] rs1 |
| 39863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39864 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39866 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39867 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_RL), |
| 39868 | GIR_RootConstrainSelectedInstOperands, |
| 39869 | // GIR_Coverage, 834, |
| 39870 | GIR_Done, |
| 39871 | // Label 2808: @103414 |
| 39872 | GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(103455), // Rule ID 835 // |
| 39873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39874 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39875 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 39876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39877 | // MIs[0] rs1 |
| 39878 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39879 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39880 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39881 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39882 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_RL), |
| 39883 | GIR_RootConstrainSelectedInstOperands, |
| 39884 | // GIR_Coverage, 835, |
| 39885 | GIR_Done, |
| 39886 | // Label 2809: @103455 |
| 39887 | GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(103496), // Rule ID 836 // |
| 39888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39889 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39890 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39892 | // MIs[0] rs1 |
| 39893 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39894 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39895 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39896 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39897 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 39898 | GIR_RootConstrainSelectedInstOperands, |
| 39899 | // GIR_Coverage, 836, |
| 39900 | GIR_Done, |
| 39901 | // Label 2810: @103496 |
| 39902 | GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(103537), // Rule ID 837 // |
| 39903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39904 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39905 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 39906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39907 | // MIs[0] rs1 |
| 39908 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39911 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39912 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 39913 | GIR_RootConstrainSelectedInstOperands, |
| 39914 | // GIR_Coverage, 837, |
| 39915 | GIR_Done, |
| 39916 | // Label 2811: @103537 |
| 39917 | GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(103578), // Rule ID 838 // |
| 39918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 39919 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39920 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39922 | // MIs[0] rs1 |
| 39923 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39924 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39926 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39927 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 39928 | GIR_RootConstrainSelectedInstOperands, |
| 39929 | // GIR_Coverage, 838, |
| 39930 | GIR_Done, |
| 39931 | // Label 2812: @103578 |
| 39932 | GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(103619), // Rule ID 839 // |
| 39933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 39934 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39935 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 39936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39937 | // MIs[0] rs1 |
| 39938 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39939 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39940 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39941 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39942 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 39943 | GIR_RootConstrainSelectedInstOperands, |
| 39944 | // GIR_Coverage, 839, |
| 39945 | GIR_Done, |
| 39946 | // Label 2813: @103619 |
| 39947 | GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(103660), // Rule ID 840 // |
| 39948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39949 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39950 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39952 | // MIs[0] rs1 |
| 39953 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39954 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39955 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39956 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39957 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39958 | GIR_RootConstrainSelectedInstOperands, |
| 39959 | // GIR_Coverage, 840, |
| 39960 | GIR_Done, |
| 39961 | // Label 2814: @103660 |
| 39962 | GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(103701), // Rule ID 841 // |
| 39963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39964 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39965 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 39966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39967 | // MIs[0] rs1 |
| 39968 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39970 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39971 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39972 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39973 | GIR_RootConstrainSelectedInstOperands, |
| 39974 | // GIR_Coverage, 841, |
| 39975 | GIR_Done, |
| 39976 | // Label 2815: @103701 |
| 39977 | GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(103742), // Rule ID 842 // |
| 39978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 39979 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39980 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39982 | // MIs[0] rs1 |
| 39983 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39984 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39985 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39986 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 39987 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 39988 | GIR_RootConstrainSelectedInstOperands, |
| 39989 | // GIR_Coverage, 842, |
| 39990 | GIR_Done, |
| 39991 | // Label 2816: @103742 |
| 39992 | GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(103783), // Rule ID 843 // |
| 39993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 39994 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 39995 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 39996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 39997 | // MIs[0] rs1 |
| 39998 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 39999 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40000 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40001 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40002 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40003 | GIR_RootConstrainSelectedInstOperands, |
| 40004 | // GIR_Coverage, 843, |
| 40005 | GIR_Done, |
| 40006 | // Label 2817: @103783 |
| 40007 | GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(103824), // Rule ID 844 // |
| 40008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40009 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40010 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40012 | // MIs[0] rs1 |
| 40013 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40014 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40015 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40016 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40017 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40018 | GIR_RootConstrainSelectedInstOperands, |
| 40019 | // GIR_Coverage, 844, |
| 40020 | GIR_Done, |
| 40021 | // Label 2818: @103824 |
| 40022 | GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(103865), // Rule ID 845 // |
| 40023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 40024 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40025 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40027 | // MIs[0] rs1 |
| 40028 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40030 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40031 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40032 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40033 | GIR_RootConstrainSelectedInstOperands, |
| 40034 | // GIR_Coverage, 845, |
| 40035 | GIR_Done, |
| 40036 | // Label 2819: @103865 |
| 40037 | GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(103906), // Rule ID 846 // |
| 40038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40039 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40040 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40042 | // MIs[0] rs1 |
| 40043 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40044 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40045 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40046 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40047 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40048 | GIR_RootConstrainSelectedInstOperands, |
| 40049 | // GIR_Coverage, 846, |
| 40050 | GIR_Done, |
| 40051 | // Label 2820: @103906 |
| 40052 | GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(103947), // Rule ID 847 // |
| 40053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 40054 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40055 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40057 | // MIs[0] rs1 |
| 40058 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40059 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40060 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40061 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40062 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40063 | GIR_RootConstrainSelectedInstOperands, |
| 40064 | // GIR_Coverage, 847, |
| 40065 | GIR_Done, |
| 40066 | // Label 2821: @103947 |
| 40067 | GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(103988), // Rule ID 848 // |
| 40068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40069 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40070 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40072 | // MIs[0] rs1 |
| 40073 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40074 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40075 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40076 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40077 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40078 | GIR_RootConstrainSelectedInstOperands, |
| 40079 | // GIR_Coverage, 848, |
| 40080 | GIR_Done, |
| 40081 | // Label 2822: @103988 |
| 40082 | GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(104029), // Rule ID 849 // |
| 40083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 40084 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40085 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40087 | // MIs[0] rs1 |
| 40088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40089 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40090 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40091 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40092 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40093 | GIR_RootConstrainSelectedInstOperands, |
| 40094 | // GIR_Coverage, 849, |
| 40095 | GIR_Done, |
| 40096 | // Label 2823: @104029 |
| 40097 | GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(104070), // Rule ID 1063 // |
| 40098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40099 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40100 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40102 | // MIs[0] rs1 |
| 40103 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40106 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>> => (AMOMAXU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40107 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40108 | GIR_RootConstrainSelectedInstOperands, |
| 40109 | // GIR_Coverage, 1063, |
| 40110 | GIR_Done, |
| 40111 | // Label 2824: @104070 |
| 40112 | GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(104111), // Rule ID 1065 // |
| 40113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40114 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40115 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40117 | // MIs[0] rs1 |
| 40118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40119 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40120 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40121 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>> => (AMOMAXU_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40122 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_AQ), |
| 40123 | GIR_RootConstrainSelectedInstOperands, |
| 40124 | // GIR_Coverage, 1065, |
| 40125 | GIR_Done, |
| 40126 | // Label 2825: @104111 |
| 40127 | GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(104152), // Rule ID 1067 // |
| 40128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40129 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40130 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40132 | // MIs[0] rs1 |
| 40133 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40134 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40135 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40136 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>> => (AMOMAXU_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40137 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_RL), |
| 40138 | GIR_RootConstrainSelectedInstOperands, |
| 40139 | // GIR_Coverage, 1067, |
| 40140 | GIR_Done, |
| 40141 | // Label 2826: @104152 |
| 40142 | GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(104193), // Rule ID 1069 // |
| 40143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40144 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40147 | // MIs[0] rs1 |
| 40148 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40150 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40151 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>> => (AMOMAXU_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40152 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_AQ_RL), |
| 40153 | GIR_RootConstrainSelectedInstOperands, |
| 40154 | // GIR_Coverage, 1069, |
| 40155 | GIR_Done, |
| 40156 | // Label 2827: @104193 |
| 40157 | GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(104234), // Rule ID 1071 // |
| 40158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40159 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40160 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40162 | // MIs[0] rs1 |
| 40163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40164 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40165 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40166 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>> => (AMOMAXU_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40167 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_AQ_RL), |
| 40168 | GIR_RootConstrainSelectedInstOperands, |
| 40169 | // GIR_Coverage, 1071, |
| 40170 | GIR_Done, |
| 40171 | // Label 2828: @104234 |
| 40172 | GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(104275), // Rule ID 1073 // |
| 40173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40174 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40175 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40177 | // MIs[0] rs1 |
| 40178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40179 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40180 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40181 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>> => (AMOMAXU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40182 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40183 | GIR_RootConstrainSelectedInstOperands, |
| 40184 | // GIR_Coverage, 1073, |
| 40185 | GIR_Done, |
| 40186 | // Label 2829: @104275 |
| 40187 | GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(104316), // Rule ID 1075 // |
| 40188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40189 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40190 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40191 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40192 | // MIs[0] rs1 |
| 40193 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40194 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40195 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40196 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>> => (AMOMAXU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40197 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40198 | GIR_RootConstrainSelectedInstOperands, |
| 40199 | // GIR_Coverage, 1075, |
| 40200 | GIR_Done, |
| 40201 | // Label 2830: @104316 |
| 40202 | GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(104357), // Rule ID 1077 // |
| 40203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40204 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40205 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40207 | // MIs[0] rs1 |
| 40208 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40211 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>> => (AMOMAXU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40212 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40213 | GIR_RootConstrainSelectedInstOperands, |
| 40214 | // GIR_Coverage, 1077, |
| 40215 | GIR_Done, |
| 40216 | // Label 2831: @104357 |
| 40217 | GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(104398), // Rule ID 1079 // |
| 40218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40219 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40220 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40222 | // MIs[0] rs1 |
| 40223 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40224 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40225 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40226 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>> => (AMOMAXU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40227 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40228 | GIR_RootConstrainSelectedInstOperands, |
| 40229 | // GIR_Coverage, 1079, |
| 40230 | GIR_Done, |
| 40231 | // Label 2832: @104398 |
| 40232 | GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(104439), // Rule ID 1081 // |
| 40233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40234 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40237 | // MIs[0] rs1 |
| 40238 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40241 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>> => (AMOMAXU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40242 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40243 | GIR_RootConstrainSelectedInstOperands, |
| 40244 | // GIR_Coverage, 1081, |
| 40245 | GIR_Done, |
| 40246 | // Label 2833: @104439 |
| 40247 | GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(104480), // Rule ID 1243 // |
| 40248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40249 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40250 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40252 | // MIs[0] rs1 |
| 40253 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40256 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>> => (AMOMAXU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40257 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40258 | GIR_RootConstrainSelectedInstOperands, |
| 40259 | // GIR_Coverage, 1243, |
| 40260 | GIR_Done, |
| 40261 | // Label 2834: @104480 |
| 40262 | GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(104521), // Rule ID 1245 // |
| 40263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40264 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40265 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40267 | // MIs[0] rs1 |
| 40268 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40269 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40270 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40271 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>> => (AMOMAXU_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40272 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_AQ), |
| 40273 | GIR_RootConstrainSelectedInstOperands, |
| 40274 | // GIR_Coverage, 1245, |
| 40275 | GIR_Done, |
| 40276 | // Label 2835: @104521 |
| 40277 | GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(104562), // Rule ID 1247 // |
| 40278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40279 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40280 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40282 | // MIs[0] rs1 |
| 40283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40284 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40286 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>> => (AMOMAXU_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40287 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_RL), |
| 40288 | GIR_RootConstrainSelectedInstOperands, |
| 40289 | // GIR_Coverage, 1247, |
| 40290 | GIR_Done, |
| 40291 | // Label 2836: @104562 |
| 40292 | GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(104603), // Rule ID 1249 // |
| 40293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40294 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40295 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40297 | // MIs[0] rs1 |
| 40298 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40299 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40300 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40301 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>> => (AMOMAXU_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40302 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_AQ_RL), |
| 40303 | GIR_RootConstrainSelectedInstOperands, |
| 40304 | // GIR_Coverage, 1249, |
| 40305 | GIR_Done, |
| 40306 | // Label 2837: @104603 |
| 40307 | GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(104644), // Rule ID 1251 // |
| 40308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 40309 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40310 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40312 | // MIs[0] rs1 |
| 40313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40315 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40316 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>> => (AMOMAXU_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40317 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_AQ_RL), |
| 40318 | GIR_RootConstrainSelectedInstOperands, |
| 40319 | // GIR_Coverage, 1251, |
| 40320 | GIR_Done, |
| 40321 | // Label 2838: @104644 |
| 40322 | GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(104685), // Rule ID 1253 // |
| 40323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40324 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40325 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40327 | // MIs[0] rs1 |
| 40328 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40329 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40330 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40331 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>> => (AMOMAXU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40332 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40333 | GIR_RootConstrainSelectedInstOperands, |
| 40334 | // GIR_Coverage, 1253, |
| 40335 | GIR_Done, |
| 40336 | // Label 2839: @104685 |
| 40337 | GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(104726), // Rule ID 1255 // |
| 40338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40339 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40340 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40342 | // MIs[0] rs1 |
| 40343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40344 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40346 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>> => (AMOMAXU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40347 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40348 | GIR_RootConstrainSelectedInstOperands, |
| 40349 | // GIR_Coverage, 1255, |
| 40350 | GIR_Done, |
| 40351 | // Label 2840: @104726 |
| 40352 | GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(104767), // Rule ID 1257 // |
| 40353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40354 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40355 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40357 | // MIs[0] rs1 |
| 40358 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40361 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>> => (AMOMAXU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40362 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40363 | GIR_RootConstrainSelectedInstOperands, |
| 40364 | // GIR_Coverage, 1257, |
| 40365 | GIR_Done, |
| 40366 | // Label 2841: @104767 |
| 40367 | GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(104808), // Rule ID 1259 // |
| 40368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40369 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40370 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40372 | // MIs[0] rs1 |
| 40373 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40376 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>> => (AMOMAXU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40377 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40378 | GIR_RootConstrainSelectedInstOperands, |
| 40379 | // GIR_Coverage, 1259, |
| 40380 | GIR_Done, |
| 40381 | // Label 2842: @104808 |
| 40382 | GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(104849), // Rule ID 1261 // |
| 40383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 40384 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40385 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40387 | // MIs[0] rs1 |
| 40388 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 40389 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40390 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40391 | // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>> => (AMOMAXU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 40392 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40393 | GIR_RootConstrainSelectedInstOperands, |
| 40394 | // GIR_Coverage, 1261, |
| 40395 | GIR_Done, |
| 40396 | // Label 2843: @104849 |
| 40397 | GIM_Reject, |
| 40398 | // Label 2793: @104850 |
| 40399 | GIM_Reject, |
| 40400 | // Label 2791: @104851 |
| 40401 | GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(106500), |
| 40402 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 40403 | GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(104900), // Rule ID 512 // |
| 40404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 40405 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40406 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40408 | // MIs[0] rs1 |
| 40409 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40410 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40411 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40412 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40413 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40414 | GIR_RootConstrainSelectedInstOperands, |
| 40415 | // GIR_Coverage, 512, |
| 40416 | GIR_Done, |
| 40417 | // Label 2845: @104900 |
| 40418 | GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(104941), // Rule ID 514 // |
| 40419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 40420 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40421 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40423 | // MIs[0] rs1 |
| 40424 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40425 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40426 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40427 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40428 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ), |
| 40429 | GIR_RootConstrainSelectedInstOperands, |
| 40430 | // GIR_Coverage, 514, |
| 40431 | GIR_Done, |
| 40432 | // Label 2846: @104941 |
| 40433 | GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(104982), // Rule ID 516 // |
| 40434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 40435 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40436 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40438 | // MIs[0] rs1 |
| 40439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40440 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40442 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40443 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_RL), |
| 40444 | GIR_RootConstrainSelectedInstOperands, |
| 40445 | // GIR_Coverage, 516, |
| 40446 | GIR_Done, |
| 40447 | // Label 2847: @104982 |
| 40448 | GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(105023), // Rule ID 518 // |
| 40449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 40450 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40451 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40453 | // MIs[0] rs1 |
| 40454 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40455 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40456 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40457 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40458 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 40459 | GIR_RootConstrainSelectedInstOperands, |
| 40460 | // GIR_Coverage, 518, |
| 40461 | GIR_Done, |
| 40462 | // Label 2848: @105023 |
| 40463 | GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(105064), // Rule ID 520 // |
| 40464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 40465 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40466 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40468 | // MIs[0] rs1 |
| 40469 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40471 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40472 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40473 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W_AQ_RL), |
| 40474 | GIR_RootConstrainSelectedInstOperands, |
| 40475 | // GIR_Coverage, 520, |
| 40476 | GIR_Done, |
| 40477 | // Label 2849: @105064 |
| 40478 | GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(105105), // Rule ID 522 // |
| 40479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40480 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40481 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40483 | // MIs[0] rs1 |
| 40484 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40486 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40487 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40488 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40489 | GIR_RootConstrainSelectedInstOperands, |
| 40490 | // GIR_Coverage, 522, |
| 40491 | GIR_Done, |
| 40492 | // Label 2850: @105105 |
| 40493 | GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(105146), // Rule ID 524 // |
| 40494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40495 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40496 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40498 | // MIs[0] rs1 |
| 40499 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40500 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40502 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40503 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40504 | GIR_RootConstrainSelectedInstOperands, |
| 40505 | // GIR_Coverage, 524, |
| 40506 | GIR_Done, |
| 40507 | // Label 2851: @105146 |
| 40508 | GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(105187), // Rule ID 526 // |
| 40509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40510 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40511 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40513 | // MIs[0] rs1 |
| 40514 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40515 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40516 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40517 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40518 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40519 | GIR_RootConstrainSelectedInstOperands, |
| 40520 | // GIR_Coverage, 526, |
| 40521 | GIR_Done, |
| 40522 | // Label 2852: @105187 |
| 40523 | GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(105228), // Rule ID 528 // |
| 40524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40525 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40526 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40528 | // MIs[0] rs1 |
| 40529 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40530 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40531 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40532 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40533 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40534 | GIR_RootConstrainSelectedInstOperands, |
| 40535 | // GIR_Coverage, 528, |
| 40536 | GIR_Done, |
| 40537 | // Label 2853: @105228 |
| 40538 | GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(105269), // Rule ID 530 // |
| 40539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 40540 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 40541 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40543 | // MIs[0] rs1 |
| 40544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40546 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40547 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40548 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_W), |
| 40549 | GIR_RootConstrainSelectedInstOperands, |
| 40550 | // GIR_Coverage, 530, |
| 40551 | GIR_Done, |
| 40552 | // Label 2854: @105269 |
| 40553 | GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(105310), // Rule ID 622 // |
| 40554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 40555 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40556 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40558 | // MIs[0] rs1 |
| 40559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40560 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40562 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_monotonic>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40563 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D), |
| 40564 | GIR_RootConstrainSelectedInstOperands, |
| 40565 | // GIR_Coverage, 622, |
| 40566 | GIR_Done, |
| 40567 | // Label 2855: @105310 |
| 40568 | GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(105351), // Rule ID 623 // |
| 40569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 40570 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40571 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40573 | // MIs[0] rs1 |
| 40574 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40575 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40576 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40577 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acquire>> => (AMOMAXU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40578 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D_AQ), |
| 40579 | GIR_RootConstrainSelectedInstOperands, |
| 40580 | // GIR_Coverage, 623, |
| 40581 | GIR_Done, |
| 40582 | // Label 2856: @105351 |
| 40583 | GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(105392), // Rule ID 624 // |
| 40584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 40585 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40586 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40588 | // MIs[0] rs1 |
| 40589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40590 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40591 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40592 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_release>> => (AMOMAXU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40593 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D_RL), |
| 40594 | GIR_RootConstrainSelectedInstOperands, |
| 40595 | // GIR_Coverage, 624, |
| 40596 | GIR_Done, |
| 40597 | // Label 2857: @105392 |
| 40598 | GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(105433), // Rule ID 625 // |
| 40599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 40600 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40601 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40603 | // MIs[0] rs1 |
| 40604 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40605 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40607 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40608 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D_AQ_RL), |
| 40609 | GIR_RootConstrainSelectedInstOperands, |
| 40610 | // GIR_Coverage, 625, |
| 40611 | GIR_Done, |
| 40612 | // Label 2858: @105433 |
| 40613 | GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(105474), // Rule ID 626 // |
| 40614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 40615 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40616 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40618 | // MIs[0] rs1 |
| 40619 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40620 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40621 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40622 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40623 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D_AQ_RL), |
| 40624 | GIR_RootConstrainSelectedInstOperands, |
| 40625 | // GIR_Coverage, 626, |
| 40626 | GIR_Done, |
| 40627 | // Label 2859: @105474 |
| 40628 | GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(105515), // Rule ID 627 // |
| 40629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 40630 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40631 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40633 | // MIs[0] rs1 |
| 40634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40635 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40636 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40637 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_monotonic>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40638 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D), |
| 40639 | GIR_RootConstrainSelectedInstOperands, |
| 40640 | // GIR_Coverage, 627, |
| 40641 | GIR_Done, |
| 40642 | // Label 2860: @105515 |
| 40643 | GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(105556), // Rule ID 628 // |
| 40644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 40645 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40646 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40648 | // MIs[0] rs1 |
| 40649 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40650 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40651 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40652 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acquire>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40653 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D), |
| 40654 | GIR_RootConstrainSelectedInstOperands, |
| 40655 | // GIR_Coverage, 628, |
| 40656 | GIR_Done, |
| 40657 | // Label 2861: @105556 |
| 40658 | GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(105597), // Rule ID 629 // |
| 40659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 40660 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40661 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40663 | // MIs[0] rs1 |
| 40664 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40665 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40666 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40667 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_release>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40668 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D), |
| 40669 | GIR_RootConstrainSelectedInstOperands, |
| 40670 | // GIR_Coverage, 629, |
| 40671 | GIR_Done, |
| 40672 | // Label 2862: @105597 |
| 40673 | GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(105638), // Rule ID 630 // |
| 40674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 40675 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40676 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40678 | // MIs[0] rs1 |
| 40679 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40682 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acq_rel>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40683 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D), |
| 40684 | GIR_RootConstrainSelectedInstOperands, |
| 40685 | // GIR_Coverage, 630, |
| 40686 | GIR_Done, |
| 40687 | // Label 2863: @105638 |
| 40688 | GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(105679), // Rule ID 631 // |
| 40689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 40690 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 40691 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40693 | // MIs[0] rs1 |
| 40694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40695 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40696 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40697 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_seq_cst>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40698 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_D), |
| 40699 | GIR_RootConstrainSelectedInstOperands, |
| 40700 | // GIR_Coverage, 631, |
| 40701 | GIR_Done, |
| 40702 | // Label 2864: @105679 |
| 40703 | GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(105720), // Rule ID 1062 // |
| 40704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40705 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40706 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40708 | // MIs[0] rs1 |
| 40709 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40710 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40711 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40712 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>> => (AMOMAXU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40713 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40714 | GIR_RootConstrainSelectedInstOperands, |
| 40715 | // GIR_Coverage, 1062, |
| 40716 | GIR_Done, |
| 40717 | // Label 2865: @105720 |
| 40718 | GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(105761), // Rule ID 1064 // |
| 40719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40720 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40721 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40723 | // MIs[0] rs1 |
| 40724 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40725 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40726 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40727 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>> => (AMOMAXU_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40728 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_AQ), |
| 40729 | GIR_RootConstrainSelectedInstOperands, |
| 40730 | // GIR_Coverage, 1064, |
| 40731 | GIR_Done, |
| 40732 | // Label 2866: @105761 |
| 40733 | GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(105802), // Rule ID 1066 // |
| 40734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40735 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40736 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40738 | // MIs[0] rs1 |
| 40739 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40741 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40742 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>> => (AMOMAXU_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40743 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_RL), |
| 40744 | GIR_RootConstrainSelectedInstOperands, |
| 40745 | // GIR_Coverage, 1066, |
| 40746 | GIR_Done, |
| 40747 | // Label 2867: @105802 |
| 40748 | GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(105843), // Rule ID 1068 // |
| 40749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40750 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40751 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40753 | // MIs[0] rs1 |
| 40754 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40755 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40756 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40757 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>> => (AMOMAXU_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40758 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_AQ_RL), |
| 40759 | GIR_RootConstrainSelectedInstOperands, |
| 40760 | // GIR_Coverage, 1068, |
| 40761 | GIR_Done, |
| 40762 | // Label 2868: @105843 |
| 40763 | GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(105884), // Rule ID 1070 // |
| 40764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40765 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40766 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40768 | // MIs[0] rs1 |
| 40769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40771 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40772 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>> => (AMOMAXU_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40773 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B_AQ_RL), |
| 40774 | GIR_RootConstrainSelectedInstOperands, |
| 40775 | // GIR_Coverage, 1070, |
| 40776 | GIR_Done, |
| 40777 | // Label 2869: @105884 |
| 40778 | GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(105925), // Rule ID 1072 // |
| 40779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40780 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40781 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40783 | // MIs[0] rs1 |
| 40784 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40785 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40786 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40787 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>> => (AMOMAXU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40788 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40789 | GIR_RootConstrainSelectedInstOperands, |
| 40790 | // GIR_Coverage, 1072, |
| 40791 | GIR_Done, |
| 40792 | // Label 2870: @105925 |
| 40793 | GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(105966), // Rule ID 1074 // |
| 40794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40795 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40796 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40798 | // MIs[0] rs1 |
| 40799 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40800 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40801 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40802 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>> => (AMOMAXU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40803 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40804 | GIR_RootConstrainSelectedInstOperands, |
| 40805 | // GIR_Coverage, 1074, |
| 40806 | GIR_Done, |
| 40807 | // Label 2871: @105966 |
| 40808 | GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(106007), // Rule ID 1076 // |
| 40809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40810 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40811 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40813 | // MIs[0] rs1 |
| 40814 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40816 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40817 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>> => (AMOMAXU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40818 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40819 | GIR_RootConstrainSelectedInstOperands, |
| 40820 | // GIR_Coverage, 1076, |
| 40821 | GIR_Done, |
| 40822 | // Label 2872: @106007 |
| 40823 | GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(106048), // Rule ID 1078 // |
| 40824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40825 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40826 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40828 | // MIs[0] rs1 |
| 40829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40830 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40831 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40832 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>> => (AMOMAXU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40833 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40834 | GIR_RootConstrainSelectedInstOperands, |
| 40835 | // GIR_Coverage, 1078, |
| 40836 | GIR_Done, |
| 40837 | // Label 2873: @106048 |
| 40838 | GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(106089), // Rule ID 1080 // |
| 40839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40840 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40841 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40843 | // MIs[0] rs1 |
| 40844 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40845 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40846 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40847 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>> => (AMOMAXU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40848 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_B), |
| 40849 | GIR_RootConstrainSelectedInstOperands, |
| 40850 | // GIR_Coverage, 1080, |
| 40851 | GIR_Done, |
| 40852 | // Label 2874: @106089 |
| 40853 | GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(106130), // Rule ID 1242 // |
| 40854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40855 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40856 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40858 | // MIs[0] rs1 |
| 40859 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40860 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40862 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>> => (AMOMAXU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40863 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40864 | GIR_RootConstrainSelectedInstOperands, |
| 40865 | // GIR_Coverage, 1242, |
| 40866 | GIR_Done, |
| 40867 | // Label 2875: @106130 |
| 40868 | GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(106171), // Rule ID 1244 // |
| 40869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40870 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40871 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40873 | // MIs[0] rs1 |
| 40874 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40875 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40876 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40877 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>> => (AMOMAXU_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40878 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_AQ), |
| 40879 | GIR_RootConstrainSelectedInstOperands, |
| 40880 | // GIR_Coverage, 1244, |
| 40881 | GIR_Done, |
| 40882 | // Label 2876: @106171 |
| 40883 | GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(106212), // Rule ID 1246 // |
| 40884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40885 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40886 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40888 | // MIs[0] rs1 |
| 40889 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40890 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40891 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40892 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>> => (AMOMAXU_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40893 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_RL), |
| 40894 | GIR_RootConstrainSelectedInstOperands, |
| 40895 | // GIR_Coverage, 1246, |
| 40896 | GIR_Done, |
| 40897 | // Label 2877: @106212 |
| 40898 | GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(106253), // Rule ID 1248 // |
| 40899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40900 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40901 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40903 | // MIs[0] rs1 |
| 40904 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40905 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40906 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40907 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>> => (AMOMAXU_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40908 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_AQ_RL), |
| 40909 | GIR_RootConstrainSelectedInstOperands, |
| 40910 | // GIR_Coverage, 1248, |
| 40911 | GIR_Done, |
| 40912 | // Label 2878: @106253 |
| 40913 | GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(106294), // Rule ID 1250 // |
| 40914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 40915 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40916 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40918 | // MIs[0] rs1 |
| 40919 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40920 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40921 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40922 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>> => (AMOMAXU_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40923 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H_AQ_RL), |
| 40924 | GIR_RootConstrainSelectedInstOperands, |
| 40925 | // GIR_Coverage, 1250, |
| 40926 | GIR_Done, |
| 40927 | // Label 2879: @106294 |
| 40928 | GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(106335), // Rule ID 1252 // |
| 40929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40930 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40931 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 40932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40933 | // MIs[0] rs1 |
| 40934 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40935 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40936 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40937 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>> => (AMOMAXU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40938 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40939 | GIR_RootConstrainSelectedInstOperands, |
| 40940 | // GIR_Coverage, 1252, |
| 40941 | GIR_Done, |
| 40942 | // Label 2880: @106335 |
| 40943 | GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(106376), // Rule ID 1254 // |
| 40944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40945 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40946 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 40947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40948 | // MIs[0] rs1 |
| 40949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40950 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40951 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40952 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>> => (AMOMAXU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40953 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40954 | GIR_RootConstrainSelectedInstOperands, |
| 40955 | // GIR_Coverage, 1254, |
| 40956 | GIR_Done, |
| 40957 | // Label 2881: @106376 |
| 40958 | GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(106417), // Rule ID 1256 // |
| 40959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40960 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40961 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 40962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40963 | // MIs[0] rs1 |
| 40964 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40965 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40966 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40967 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>> => (AMOMAXU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40968 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40969 | GIR_RootConstrainSelectedInstOperands, |
| 40970 | // GIR_Coverage, 1256, |
| 40971 | GIR_Done, |
| 40972 | // Label 2882: @106417 |
| 40973 | GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(106458), // Rule ID 1258 // |
| 40974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40975 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 40977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40978 | // MIs[0] rs1 |
| 40979 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40980 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40982 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>> => (AMOMAXU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40983 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40984 | GIR_RootConstrainSelectedInstOperands, |
| 40985 | // GIR_Coverage, 1258, |
| 40986 | GIR_Done, |
| 40987 | // Label 2883: @106458 |
| 40988 | GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(106499), // Rule ID 1260 // |
| 40989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 40990 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40991 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 40992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40993 | // MIs[0] rs1 |
| 40994 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40996 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 40997 | // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>> => (AMOMAXU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 40998 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMAXU_H), |
| 40999 | GIR_RootConstrainSelectedInstOperands, |
| 41000 | // GIR_Coverage, 1260, |
| 41001 | GIR_Done, |
| 41002 | // Label 2884: @106499 |
| 41003 | GIM_Reject, |
| 41004 | // Label 2844: @106500 |
| 41005 | GIM_Reject, |
| 41006 | // Label 2792: @106501 |
| 41007 | GIM_Reject, |
| 41008 | // Label 32: @106502 |
| 41009 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2887*/ GIMT_Encode4(110231), |
| 41010 | /*GILLT_s32*//*Label 2885*/ GIMT_Encode4(106521), |
| 41011 | /*GILLT_s64*//*Label 2886*/ GIMT_Encode4(108581), |
| 41012 | // Label 2885: @106521 |
| 41013 | GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(108580), |
| 41014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 41015 | GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(106570), // Rule ID 533 // |
| 41016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41017 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41018 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41020 | // MIs[0] rs1 |
| 41021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41024 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41025 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41026 | GIR_RootConstrainSelectedInstOperands, |
| 41027 | // GIR_Coverage, 533, |
| 41028 | GIR_Done, |
| 41029 | // Label 2889: @106570 |
| 41030 | GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(106611), // Rule ID 535 // |
| 41031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41032 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41033 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41035 | // MIs[0] rs1 |
| 41036 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41037 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41038 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41039 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41040 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ), |
| 41041 | GIR_RootConstrainSelectedInstOperands, |
| 41042 | // GIR_Coverage, 535, |
| 41043 | GIR_Done, |
| 41044 | // Label 2890: @106611 |
| 41045 | GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(106652), // Rule ID 537 // |
| 41046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41047 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41048 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41050 | // MIs[0] rs1 |
| 41051 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41052 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41053 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41054 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41055 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_RL), |
| 41056 | GIR_RootConstrainSelectedInstOperands, |
| 41057 | // GIR_Coverage, 537, |
| 41058 | GIR_Done, |
| 41059 | // Label 2891: @106652 |
| 41060 | GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(106693), // Rule ID 539 // |
| 41061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41062 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41063 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41065 | // MIs[0] rs1 |
| 41066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41067 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41068 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41069 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41070 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41071 | GIR_RootConstrainSelectedInstOperands, |
| 41072 | // GIR_Coverage, 539, |
| 41073 | GIR_Done, |
| 41074 | // Label 2892: @106693 |
| 41075 | GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(106734), // Rule ID 541 // |
| 41076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41077 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41078 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41080 | // MIs[0] rs1 |
| 41081 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41082 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41083 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41084 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41085 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41086 | GIR_RootConstrainSelectedInstOperands, |
| 41087 | // GIR_Coverage, 541, |
| 41088 | GIR_Done, |
| 41089 | // Label 2893: @106734 |
| 41090 | GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(106775), // Rule ID 543 // |
| 41091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41092 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41093 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41095 | // MIs[0] rs1 |
| 41096 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41097 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41098 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41099 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41100 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41101 | GIR_RootConstrainSelectedInstOperands, |
| 41102 | // GIR_Coverage, 543, |
| 41103 | GIR_Done, |
| 41104 | // Label 2894: @106775 |
| 41105 | GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(106816), // Rule ID 545 // |
| 41106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41107 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41108 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41110 | // MIs[0] rs1 |
| 41111 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41112 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41114 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41115 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41116 | GIR_RootConstrainSelectedInstOperands, |
| 41117 | // GIR_Coverage, 545, |
| 41118 | GIR_Done, |
| 41119 | // Label 2895: @106816 |
| 41120 | GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(106857), // Rule ID 547 // |
| 41121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41122 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41123 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41125 | // MIs[0] rs1 |
| 41126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41128 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41129 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41130 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41131 | GIR_RootConstrainSelectedInstOperands, |
| 41132 | // GIR_Coverage, 547, |
| 41133 | GIR_Done, |
| 41134 | // Label 2896: @106857 |
| 41135 | GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(106898), // Rule ID 549 // |
| 41136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41137 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41138 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41140 | // MIs[0] rs1 |
| 41141 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41143 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41144 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41145 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41146 | GIR_RootConstrainSelectedInstOperands, |
| 41147 | // GIR_Coverage, 549, |
| 41148 | GIR_Done, |
| 41149 | // Label 2897: @106898 |
| 41150 | GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(106939), // Rule ID 551 // |
| 41151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41152 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41153 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41154 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41155 | // MIs[0] rs1 |
| 41156 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41157 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41158 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41159 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41160 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41161 | GIR_RootConstrainSelectedInstOperands, |
| 41162 | // GIR_Coverage, 551, |
| 41163 | GIR_Done, |
| 41164 | // Label 2898: @106939 |
| 41165 | GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(106980), // Rule ID 850 // |
| 41166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41167 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41168 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41169 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41170 | // MIs[0] rs1 |
| 41171 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41172 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41173 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41174 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41175 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41176 | GIR_RootConstrainSelectedInstOperands, |
| 41177 | // GIR_Coverage, 850, |
| 41178 | GIR_Done, |
| 41179 | // Label 2899: @106980 |
| 41180 | GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(107021), // Rule ID 851 // |
| 41181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41182 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41183 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41185 | // MIs[0] rs1 |
| 41186 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41187 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41188 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41189 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41190 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41191 | GIR_RootConstrainSelectedInstOperands, |
| 41192 | // GIR_Coverage, 851, |
| 41193 | GIR_Done, |
| 41194 | // Label 2900: @107021 |
| 41195 | GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(107062), // Rule ID 852 // |
| 41196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41197 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41198 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41200 | // MIs[0] rs1 |
| 41201 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41202 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41203 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41204 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41205 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ), |
| 41206 | GIR_RootConstrainSelectedInstOperands, |
| 41207 | // GIR_Coverage, 852, |
| 41208 | GIR_Done, |
| 41209 | // Label 2901: @107062 |
| 41210 | GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(107103), // Rule ID 853 // |
| 41211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41212 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41213 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41214 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41215 | // MIs[0] rs1 |
| 41216 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41217 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41218 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41219 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41220 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ), |
| 41221 | GIR_RootConstrainSelectedInstOperands, |
| 41222 | // GIR_Coverage, 853, |
| 41223 | GIR_Done, |
| 41224 | // Label 2902: @107103 |
| 41225 | GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(107144), // Rule ID 854 // |
| 41226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41227 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41228 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41230 | // MIs[0] rs1 |
| 41231 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41232 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41234 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41235 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_RL), |
| 41236 | GIR_RootConstrainSelectedInstOperands, |
| 41237 | // GIR_Coverage, 854, |
| 41238 | GIR_Done, |
| 41239 | // Label 2903: @107144 |
| 41240 | GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(107185), // Rule ID 855 // |
| 41241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41242 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41243 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41245 | // MIs[0] rs1 |
| 41246 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41247 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41248 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41249 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41250 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_RL), |
| 41251 | GIR_RootConstrainSelectedInstOperands, |
| 41252 | // GIR_Coverage, 855, |
| 41253 | GIR_Done, |
| 41254 | // Label 2904: @107185 |
| 41255 | GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(107226), // Rule ID 856 // |
| 41256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41257 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41258 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41260 | // MIs[0] rs1 |
| 41261 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41262 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41263 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41264 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41265 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41266 | GIR_RootConstrainSelectedInstOperands, |
| 41267 | // GIR_Coverage, 856, |
| 41268 | GIR_Done, |
| 41269 | // Label 2905: @107226 |
| 41270 | GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(107267), // Rule ID 857 // |
| 41271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41272 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41273 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41275 | // MIs[0] rs1 |
| 41276 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41277 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41278 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41279 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41280 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41281 | GIR_RootConstrainSelectedInstOperands, |
| 41282 | // GIR_Coverage, 857, |
| 41283 | GIR_Done, |
| 41284 | // Label 2906: @107267 |
| 41285 | GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(107308), // Rule ID 858 // |
| 41286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41287 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41288 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41289 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41290 | // MIs[0] rs1 |
| 41291 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41292 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41293 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41294 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41295 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41296 | GIR_RootConstrainSelectedInstOperands, |
| 41297 | // GIR_Coverage, 858, |
| 41298 | GIR_Done, |
| 41299 | // Label 2907: @107308 |
| 41300 | GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(107349), // Rule ID 859 // |
| 41301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1), |
| 41302 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41305 | // MIs[0] rs1 |
| 41306 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41307 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41308 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41309 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41310 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41311 | GIR_RootConstrainSelectedInstOperands, |
| 41312 | // GIR_Coverage, 859, |
| 41313 | GIR_Done, |
| 41314 | // Label 2908: @107349 |
| 41315 | GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(107390), // Rule ID 860 // |
| 41316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41317 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41318 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41320 | // MIs[0] rs1 |
| 41321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41324 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41325 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41326 | GIR_RootConstrainSelectedInstOperands, |
| 41327 | // GIR_Coverage, 860, |
| 41328 | GIR_Done, |
| 41329 | // Label 2909: @107390 |
| 41330 | GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(107431), // Rule ID 861 // |
| 41331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41332 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41333 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41335 | // MIs[0] rs1 |
| 41336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41338 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41339 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41340 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41341 | GIR_RootConstrainSelectedInstOperands, |
| 41342 | // GIR_Coverage, 861, |
| 41343 | GIR_Done, |
| 41344 | // Label 2910: @107431 |
| 41345 | GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(107472), // Rule ID 862 // |
| 41346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41347 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41348 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41350 | // MIs[0] rs1 |
| 41351 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41352 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41354 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41355 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41356 | GIR_RootConstrainSelectedInstOperands, |
| 41357 | // GIR_Coverage, 862, |
| 41358 | GIR_Done, |
| 41359 | // Label 2911: @107472 |
| 41360 | GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(107513), // Rule ID 863 // |
| 41361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41362 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41363 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41365 | // MIs[0] rs1 |
| 41366 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41367 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41368 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41369 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41370 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41371 | GIR_RootConstrainSelectedInstOperands, |
| 41372 | // GIR_Coverage, 863, |
| 41373 | GIR_Done, |
| 41374 | // Label 2912: @107513 |
| 41375 | GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(107554), // Rule ID 864 // |
| 41376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41377 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41378 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41380 | // MIs[0] rs1 |
| 41381 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41382 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41383 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41384 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41385 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41386 | GIR_RootConstrainSelectedInstOperands, |
| 41387 | // GIR_Coverage, 864, |
| 41388 | GIR_Done, |
| 41389 | // Label 2913: @107554 |
| 41390 | GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(107595), // Rule ID 865 // |
| 41391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41392 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41393 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41395 | // MIs[0] rs1 |
| 41396 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41397 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41398 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41399 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41400 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41401 | GIR_RootConstrainSelectedInstOperands, |
| 41402 | // GIR_Coverage, 865, |
| 41403 | GIR_Done, |
| 41404 | // Label 2914: @107595 |
| 41405 | GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(107636), // Rule ID 866 // |
| 41406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41407 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41408 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41410 | // MIs[0] rs1 |
| 41411 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41412 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41414 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41415 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41416 | GIR_RootConstrainSelectedInstOperands, |
| 41417 | // GIR_Coverage, 866, |
| 41418 | GIR_Done, |
| 41419 | // Label 2915: @107636 |
| 41420 | GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(107677), // Rule ID 867 // |
| 41421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41422 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41423 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41425 | // MIs[0] rs1 |
| 41426 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41427 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41428 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41429 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41430 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41431 | GIR_RootConstrainSelectedInstOperands, |
| 41432 | // GIR_Coverage, 867, |
| 41433 | GIR_Done, |
| 41434 | // Label 2916: @107677 |
| 41435 | GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(107718), // Rule ID 868 // |
| 41436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41437 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41438 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41440 | // MIs[0] rs1 |
| 41441 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41442 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41444 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41445 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41446 | GIR_RootConstrainSelectedInstOperands, |
| 41447 | // GIR_Coverage, 868, |
| 41448 | GIR_Done, |
| 41449 | // Label 2917: @107718 |
| 41450 | GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(107759), // Rule ID 869 // |
| 41451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode1), |
| 41452 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41453 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41455 | // MIs[0] rs1 |
| 41456 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41458 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41459 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41460 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41461 | GIR_RootConstrainSelectedInstOperands, |
| 41462 | // GIR_Coverage, 869, |
| 41463 | GIR_Done, |
| 41464 | // Label 2918: @107759 |
| 41465 | GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(107800), // Rule ID 1083 // |
| 41466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41467 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41468 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41470 | // MIs[0] rs1 |
| 41471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41472 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41474 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>> => (AMOMINU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41475 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 41476 | GIR_RootConstrainSelectedInstOperands, |
| 41477 | // GIR_Coverage, 1083, |
| 41478 | GIR_Done, |
| 41479 | // Label 2919: @107800 |
| 41480 | GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(107841), // Rule ID 1085 // |
| 41481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41482 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41483 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41485 | // MIs[0] rs1 |
| 41486 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41487 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41488 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41489 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>> => (AMOMINU_B_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41490 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_AQ), |
| 41491 | GIR_RootConstrainSelectedInstOperands, |
| 41492 | // GIR_Coverage, 1085, |
| 41493 | GIR_Done, |
| 41494 | // Label 2920: @107841 |
| 41495 | GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(107882), // Rule ID 1087 // |
| 41496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41497 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41498 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41500 | // MIs[0] rs1 |
| 41501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41504 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>> => (AMOMINU_B_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41505 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_RL), |
| 41506 | GIR_RootConstrainSelectedInstOperands, |
| 41507 | // GIR_Coverage, 1087, |
| 41508 | GIR_Done, |
| 41509 | // Label 2921: @107882 |
| 41510 | GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(107923), // Rule ID 1089 // |
| 41511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41512 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41513 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41515 | // MIs[0] rs1 |
| 41516 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41517 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41518 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41519 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>> => (AMOMINU_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41520 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_AQ_RL), |
| 41521 | GIR_RootConstrainSelectedInstOperands, |
| 41522 | // GIR_Coverage, 1089, |
| 41523 | GIR_Done, |
| 41524 | // Label 2922: @107923 |
| 41525 | GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(107964), // Rule ID 1091 // |
| 41526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41527 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41530 | // MIs[0] rs1 |
| 41531 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41532 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41533 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41534 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>> => (AMOMINU_B_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41535 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_AQ_RL), |
| 41536 | GIR_RootConstrainSelectedInstOperands, |
| 41537 | // GIR_Coverage, 1091, |
| 41538 | GIR_Done, |
| 41539 | // Label 2923: @107964 |
| 41540 | GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(108005), // Rule ID 1093 // |
| 41541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41542 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41543 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41545 | // MIs[0] rs1 |
| 41546 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41547 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41548 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41549 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>> => (AMOMINU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41550 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 41551 | GIR_RootConstrainSelectedInstOperands, |
| 41552 | // GIR_Coverage, 1093, |
| 41553 | GIR_Done, |
| 41554 | // Label 2924: @108005 |
| 41555 | GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(108046), // Rule ID 1095 // |
| 41556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41557 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41558 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41560 | // MIs[0] rs1 |
| 41561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41562 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41563 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41564 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>> => (AMOMINU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41565 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 41566 | GIR_RootConstrainSelectedInstOperands, |
| 41567 | // GIR_Coverage, 1095, |
| 41568 | GIR_Done, |
| 41569 | // Label 2925: @108046 |
| 41570 | GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(108087), // Rule ID 1097 // |
| 41571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41572 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41573 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41575 | // MIs[0] rs1 |
| 41576 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41577 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41578 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41579 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>> => (AMOMINU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41580 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 41581 | GIR_RootConstrainSelectedInstOperands, |
| 41582 | // GIR_Coverage, 1097, |
| 41583 | GIR_Done, |
| 41584 | // Label 2926: @108087 |
| 41585 | GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(108128), // Rule ID 1099 // |
| 41586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41587 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41588 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41590 | // MIs[0] rs1 |
| 41591 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41592 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41594 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>> => (AMOMINU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41595 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 41596 | GIR_RootConstrainSelectedInstOperands, |
| 41597 | // GIR_Coverage, 1099, |
| 41598 | GIR_Done, |
| 41599 | // Label 2927: @108128 |
| 41600 | GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(108169), // Rule ID 1101 // |
| 41601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41602 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41603 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41605 | // MIs[0] rs1 |
| 41606 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41607 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41608 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41609 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>> => (AMOMINU_B:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41610 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 41611 | GIR_RootConstrainSelectedInstOperands, |
| 41612 | // GIR_Coverage, 1101, |
| 41613 | GIR_Done, |
| 41614 | // Label 2928: @108169 |
| 41615 | GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(108210), // Rule ID 1263 // |
| 41616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41617 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41618 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41620 | // MIs[0] rs1 |
| 41621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41622 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41623 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41624 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>> => (AMOMINU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41625 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 41626 | GIR_RootConstrainSelectedInstOperands, |
| 41627 | // GIR_Coverage, 1263, |
| 41628 | GIR_Done, |
| 41629 | // Label 2929: @108210 |
| 41630 | GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(108251), // Rule ID 1265 // |
| 41631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41632 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41633 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41635 | // MIs[0] rs1 |
| 41636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41637 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41638 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41639 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>> => (AMOMINU_H_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41640 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_AQ), |
| 41641 | GIR_RootConstrainSelectedInstOperands, |
| 41642 | // GIR_Coverage, 1265, |
| 41643 | GIR_Done, |
| 41644 | // Label 2930: @108251 |
| 41645 | GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(108292), // Rule ID 1267 // |
| 41646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41647 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41648 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41650 | // MIs[0] rs1 |
| 41651 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41652 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41653 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41654 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>> => (AMOMINU_H_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41655 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_RL), |
| 41656 | GIR_RootConstrainSelectedInstOperands, |
| 41657 | // GIR_Coverage, 1267, |
| 41658 | GIR_Done, |
| 41659 | // Label 2931: @108292 |
| 41660 | GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(108333), // Rule ID 1269 // |
| 41661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41662 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41663 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41665 | // MIs[0] rs1 |
| 41666 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41667 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41668 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41669 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>> => (AMOMINU_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41670 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_AQ_RL), |
| 41671 | GIR_RootConstrainSelectedInstOperands, |
| 41672 | // GIR_Coverage, 1269, |
| 41673 | GIR_Done, |
| 41674 | // Label 2932: @108333 |
| 41675 | GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(108374), // Rule ID 1271 // |
| 41676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1), |
| 41677 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41678 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41680 | // MIs[0] rs1 |
| 41681 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41682 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41684 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>> => (AMOMINU_H_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41685 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_AQ_RL), |
| 41686 | GIR_RootConstrainSelectedInstOperands, |
| 41687 | // GIR_Coverage, 1271, |
| 41688 | GIR_Done, |
| 41689 | // Label 2933: @108374 |
| 41690 | GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(108415), // Rule ID 1273 // |
| 41691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41692 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41693 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41695 | // MIs[0] rs1 |
| 41696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41697 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41698 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41699 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>> => (AMOMINU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41700 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 41701 | GIR_RootConstrainSelectedInstOperands, |
| 41702 | // GIR_Coverage, 1273, |
| 41703 | GIR_Done, |
| 41704 | // Label 2934: @108415 |
| 41705 | GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(108456), // Rule ID 1275 // |
| 41706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41707 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41708 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41710 | // MIs[0] rs1 |
| 41711 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41714 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>> => (AMOMINU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41715 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 41716 | GIR_RootConstrainSelectedInstOperands, |
| 41717 | // GIR_Coverage, 1275, |
| 41718 | GIR_Done, |
| 41719 | // Label 2935: @108456 |
| 41720 | GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(108497), // Rule ID 1277 // |
| 41721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41722 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41723 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41725 | // MIs[0] rs1 |
| 41726 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41727 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41728 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41729 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>> => (AMOMINU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41730 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 41731 | GIR_RootConstrainSelectedInstOperands, |
| 41732 | // GIR_Coverage, 1277, |
| 41733 | GIR_Done, |
| 41734 | // Label 2936: @108497 |
| 41735 | GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(108538), // Rule ID 1279 // |
| 41736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41737 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41738 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41740 | // MIs[0] rs1 |
| 41741 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41742 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41743 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41744 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>> => (AMOMINU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41745 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 41746 | GIR_RootConstrainSelectedInstOperands, |
| 41747 | // GIR_Coverage, 1279, |
| 41748 | GIR_Done, |
| 41749 | // Label 2937: @108538 |
| 41750 | GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(108579), // Rule ID 1281 // |
| 41751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1), |
| 41752 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41753 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41755 | // MIs[0] rs1 |
| 41756 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 41757 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41758 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41759 | // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>> => (AMOMINU_H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 41760 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 41761 | GIR_RootConstrainSelectedInstOperands, |
| 41762 | // GIR_Coverage, 1281, |
| 41763 | GIR_Done, |
| 41764 | // Label 2938: @108579 |
| 41765 | GIM_Reject, |
| 41766 | // Label 2888: @108580 |
| 41767 | GIM_Reject, |
| 41768 | // Label 2886: @108581 |
| 41769 | GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(110230), |
| 41770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 41771 | GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(108630), // Rule ID 532 // |
| 41772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41773 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41774 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41776 | // MIs[0] rs1 |
| 41777 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41778 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41780 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41781 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41782 | GIR_RootConstrainSelectedInstOperands, |
| 41783 | // GIR_Coverage, 532, |
| 41784 | GIR_Done, |
| 41785 | // Label 2940: @108630 |
| 41786 | GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(108671), // Rule ID 534 // |
| 41787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41788 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41789 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41791 | // MIs[0] rs1 |
| 41792 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41794 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41795 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41796 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ), |
| 41797 | GIR_RootConstrainSelectedInstOperands, |
| 41798 | // GIR_Coverage, 534, |
| 41799 | GIR_Done, |
| 41800 | // Label 2941: @108671 |
| 41801 | GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(108712), // Rule ID 536 // |
| 41802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41803 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41804 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41805 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41806 | // MIs[0] rs1 |
| 41807 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41808 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41809 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41810 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41811 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_RL), |
| 41812 | GIR_RootConstrainSelectedInstOperands, |
| 41813 | // GIR_Coverage, 536, |
| 41814 | GIR_Done, |
| 41815 | // Label 2942: @108712 |
| 41816 | GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(108753), // Rule ID 538 // |
| 41817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41818 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41819 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41821 | // MIs[0] rs1 |
| 41822 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41823 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41824 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41825 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41826 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41827 | GIR_RootConstrainSelectedInstOperands, |
| 41828 | // GIR_Coverage, 538, |
| 41829 | GIR_Done, |
| 41830 | // Label 2943: @108753 |
| 41831 | GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(108794), // Rule ID 540 // |
| 41832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0), |
| 41833 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41834 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41836 | // MIs[0] rs1 |
| 41837 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41838 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41839 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41840 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41841 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W_AQ_RL), |
| 41842 | GIR_RootConstrainSelectedInstOperands, |
| 41843 | // GIR_Coverage, 540, |
| 41844 | GIR_Done, |
| 41845 | // Label 2944: @108794 |
| 41846 | GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(108835), // Rule ID 542 // |
| 41847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41848 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41849 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41851 | // MIs[0] rs1 |
| 41852 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41853 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41854 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41855 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41856 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41857 | GIR_RootConstrainSelectedInstOperands, |
| 41858 | // GIR_Coverage, 542, |
| 41859 | GIR_Done, |
| 41860 | // Label 2945: @108835 |
| 41861 | GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(108876), // Rule ID 544 // |
| 41862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41863 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41864 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41866 | // MIs[0] rs1 |
| 41867 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41868 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41869 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41870 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41871 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41872 | GIR_RootConstrainSelectedInstOperands, |
| 41873 | // GIR_Coverage, 544, |
| 41874 | GIR_Done, |
| 41875 | // Label 2946: @108876 |
| 41876 | GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(108917), // Rule ID 546 // |
| 41877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41878 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41879 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41881 | // MIs[0] rs1 |
| 41882 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41883 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41884 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41885 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41886 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41887 | GIR_RootConstrainSelectedInstOperands, |
| 41888 | // GIR_Coverage, 546, |
| 41889 | GIR_Done, |
| 41890 | // Label 2947: @108917 |
| 41891 | GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(108958), // Rule ID 548 // |
| 41892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41893 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41894 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41895 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41896 | // MIs[0] rs1 |
| 41897 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41898 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41899 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41900 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41901 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41902 | GIR_RootConstrainSelectedInstOperands, |
| 41903 | // GIR_Coverage, 548, |
| 41904 | GIR_Done, |
| 41905 | // Label 2948: @108958 |
| 41906 | GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(108999), // Rule ID 550 // |
| 41907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_HwMode0), |
| 41908 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 41909 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41911 | // MIs[0] rs1 |
| 41912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41913 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41914 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41915 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41916 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_W), |
| 41917 | GIR_RootConstrainSelectedInstOperands, |
| 41918 | // GIR_Coverage, 550, |
| 41919 | GIR_Done, |
| 41920 | // Label 2949: @108999 |
| 41921 | GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(109040), // Rule ID 632 // |
| 41922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 41923 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 41924 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 41925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41926 | // MIs[0] rs1 |
| 41927 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41928 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41930 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_monotonic>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41931 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D), |
| 41932 | GIR_RootConstrainSelectedInstOperands, |
| 41933 | // GIR_Coverage, 632, |
| 41934 | GIR_Done, |
| 41935 | // Label 2950: @109040 |
| 41936 | GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(109081), // Rule ID 633 // |
| 41937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 41938 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 41939 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 41940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41941 | // MIs[0] rs1 |
| 41942 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41943 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41944 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41945 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acquire>> => (AMOMINU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41946 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D_AQ), |
| 41947 | GIR_RootConstrainSelectedInstOperands, |
| 41948 | // GIR_Coverage, 633, |
| 41949 | GIR_Done, |
| 41950 | // Label 2951: @109081 |
| 41951 | GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(109122), // Rule ID 634 // |
| 41952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 41953 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 41954 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 41955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41956 | // MIs[0] rs1 |
| 41957 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41960 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_release>> => (AMOMINU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41961 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D_RL), |
| 41962 | GIR_RootConstrainSelectedInstOperands, |
| 41963 | // GIR_Coverage, 634, |
| 41964 | GIR_Done, |
| 41965 | // Label 2952: @109122 |
| 41966 | GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(109163), // Rule ID 635 // |
| 41967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 41968 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 41969 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 41970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41971 | // MIs[0] rs1 |
| 41972 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41973 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41974 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41975 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41976 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D_AQ_RL), |
| 41977 | GIR_RootConstrainSelectedInstOperands, |
| 41978 | // GIR_Coverage, 635, |
| 41979 | GIR_Done, |
| 41980 | // Label 2953: @109163 |
| 41981 | GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(109204), // Rule ID 636 // |
| 41982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0), |
| 41983 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 41984 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 41985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41986 | // MIs[0] rs1 |
| 41987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 41988 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41989 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 41990 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 41991 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D_AQ_RL), |
| 41992 | GIR_RootConstrainSelectedInstOperands, |
| 41993 | // GIR_Coverage, 636, |
| 41994 | GIR_Done, |
| 41995 | // Label 2954: @109204 |
| 41996 | GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(109245), // Rule ID 637 // |
| 41997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 41998 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 41999 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 42000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42001 | // MIs[0] rs1 |
| 42002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42004 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42005 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_monotonic>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42006 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D), |
| 42007 | GIR_RootConstrainSelectedInstOperands, |
| 42008 | // GIR_Coverage, 637, |
| 42009 | GIR_Done, |
| 42010 | // Label 2955: @109245 |
| 42011 | GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(109286), // Rule ID 638 // |
| 42012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 42013 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 42014 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 42015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42016 | // MIs[0] rs1 |
| 42017 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42020 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acquire>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42021 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D), |
| 42022 | GIR_RootConstrainSelectedInstOperands, |
| 42023 | // GIR_Coverage, 638, |
| 42024 | GIR_Done, |
| 42025 | // Label 2956: @109286 |
| 42026 | GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(109327), // Rule ID 639 // |
| 42027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 42028 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 42029 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 42030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42031 | // MIs[0] rs1 |
| 42032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42033 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42034 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42035 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_release>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42036 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D), |
| 42037 | GIR_RootConstrainSelectedInstOperands, |
| 42038 | // GIR_Coverage, 639, |
| 42039 | GIR_Done, |
| 42040 | // Label 2957: @109327 |
| 42041 | GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(109368), // Rule ID 640 // |
| 42042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 42043 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 42044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 42045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42046 | // MIs[0] rs1 |
| 42047 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42048 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42049 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42050 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acq_rel>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42051 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D), |
| 42052 | GIR_RootConstrainSelectedInstOperands, |
| 42053 | // GIR_Coverage, 640, |
| 42054 | GIR_Done, |
| 42055 | // Label 2958: @109368 |
| 42056 | GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(109409), // Rule ID 641 // |
| 42057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0), |
| 42058 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 42059 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 42060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42061 | // MIs[0] rs1 |
| 42062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42064 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42065 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_seq_cst>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42066 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_D), |
| 42067 | GIR_RootConstrainSelectedInstOperands, |
| 42068 | // GIR_Coverage, 641, |
| 42069 | GIR_Done, |
| 42070 | // Label 2959: @109409 |
| 42071 | GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(109450), // Rule ID 1082 // |
| 42072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42073 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42074 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 42075 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42076 | // MIs[0] rs1 |
| 42077 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42078 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42079 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42080 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>> => (AMOMINU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42081 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 42082 | GIR_RootConstrainSelectedInstOperands, |
| 42083 | // GIR_Coverage, 1082, |
| 42084 | GIR_Done, |
| 42085 | // Label 2960: @109450 |
| 42086 | GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(109491), // Rule ID 1084 // |
| 42087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42088 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42089 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 42090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42091 | // MIs[0] rs1 |
| 42092 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42093 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42094 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42095 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>> => (AMOMINU_B_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42096 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_AQ), |
| 42097 | GIR_RootConstrainSelectedInstOperands, |
| 42098 | // GIR_Coverage, 1084, |
| 42099 | GIR_Done, |
| 42100 | // Label 2961: @109491 |
| 42101 | GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(109532), // Rule ID 1086 // |
| 42102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42103 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 42105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42106 | // MIs[0] rs1 |
| 42107 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42110 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>> => (AMOMINU_B_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42111 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_RL), |
| 42112 | GIR_RootConstrainSelectedInstOperands, |
| 42113 | // GIR_Coverage, 1086, |
| 42114 | GIR_Done, |
| 42115 | // Label 2962: @109532 |
| 42116 | GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(109573), // Rule ID 1088 // |
| 42117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42118 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42119 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 42120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42121 | // MIs[0] rs1 |
| 42122 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42124 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42125 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>> => (AMOMINU_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42126 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_AQ_RL), |
| 42127 | GIR_RootConstrainSelectedInstOperands, |
| 42128 | // GIR_Coverage, 1088, |
| 42129 | GIR_Done, |
| 42130 | // Label 2963: @109573 |
| 42131 | GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(109614), // Rule ID 1090 // |
| 42132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42133 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42134 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 42135 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42136 | // MIs[0] rs1 |
| 42137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42138 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42139 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42140 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>> => (AMOMINU_B_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42141 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B_AQ_RL), |
| 42142 | GIR_RootConstrainSelectedInstOperands, |
| 42143 | // GIR_Coverage, 1090, |
| 42144 | GIR_Done, |
| 42145 | // Label 2964: @109614 |
| 42146 | GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(109655), // Rule ID 1092 // |
| 42147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42148 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42149 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 42150 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42151 | // MIs[0] rs1 |
| 42152 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42153 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42154 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42155 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>> => (AMOMINU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42156 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 42157 | GIR_RootConstrainSelectedInstOperands, |
| 42158 | // GIR_Coverage, 1092, |
| 42159 | GIR_Done, |
| 42160 | // Label 2965: @109655 |
| 42161 | GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(109696), // Rule ID 1094 // |
| 42162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42163 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 42165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42166 | // MIs[0] rs1 |
| 42167 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42168 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42169 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42170 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>> => (AMOMINU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42171 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 42172 | GIR_RootConstrainSelectedInstOperands, |
| 42173 | // GIR_Coverage, 1094, |
| 42174 | GIR_Done, |
| 42175 | // Label 2966: @109696 |
| 42176 | GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(109737), // Rule ID 1096 // |
| 42177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42178 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42179 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 42180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42181 | // MIs[0] rs1 |
| 42182 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42183 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42184 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42185 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>> => (AMOMINU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42186 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 42187 | GIR_RootConstrainSelectedInstOperands, |
| 42188 | // GIR_Coverage, 1096, |
| 42189 | GIR_Done, |
| 42190 | // Label 2967: @109737 |
| 42191 | GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(109778), // Rule ID 1098 // |
| 42192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42193 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42194 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 42195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42196 | // MIs[0] rs1 |
| 42197 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42198 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42200 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>> => (AMOMINU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42201 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 42202 | GIR_RootConstrainSelectedInstOperands, |
| 42203 | // GIR_Coverage, 1098, |
| 42204 | GIR_Done, |
| 42205 | // Label 2968: @109778 |
| 42206 | GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(109819), // Rule ID 1100 // |
| 42207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42208 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 42209 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 42210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42211 | // MIs[0] rs1 |
| 42212 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42213 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42215 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>> => (AMOMINU_B:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42216 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_B), |
| 42217 | GIR_RootConstrainSelectedInstOperands, |
| 42218 | // GIR_Coverage, 1100, |
| 42219 | GIR_Done, |
| 42220 | // Label 2969: @109819 |
| 42221 | GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(109860), // Rule ID 1262 // |
| 42222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42223 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42224 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 42225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42226 | // MIs[0] rs1 |
| 42227 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42228 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42229 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42230 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>> => (AMOMINU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42231 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 42232 | GIR_RootConstrainSelectedInstOperands, |
| 42233 | // GIR_Coverage, 1262, |
| 42234 | GIR_Done, |
| 42235 | // Label 2970: @109860 |
| 42236 | GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(109901), // Rule ID 1264 // |
| 42237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42238 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42239 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 42240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42241 | // MIs[0] rs1 |
| 42242 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42243 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42244 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42245 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>> => (AMOMINU_H_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42246 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_AQ), |
| 42247 | GIR_RootConstrainSelectedInstOperands, |
| 42248 | // GIR_Coverage, 1264, |
| 42249 | GIR_Done, |
| 42250 | // Label 2971: @109901 |
| 42251 | GIM_Try, /*On fail goto*//*Label 2972*/ GIMT_Encode4(109942), // Rule ID 1266 // |
| 42252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42253 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42254 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 42255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42256 | // MIs[0] rs1 |
| 42257 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42258 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42259 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42260 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>> => (AMOMINU_H_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42261 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_RL), |
| 42262 | GIR_RootConstrainSelectedInstOperands, |
| 42263 | // GIR_Coverage, 1266, |
| 42264 | GIR_Done, |
| 42265 | // Label 2972: @109942 |
| 42266 | GIM_Try, /*On fail goto*//*Label 2973*/ GIMT_Encode4(109983), // Rule ID 1268 // |
| 42267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42268 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42269 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 42270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42271 | // MIs[0] rs1 |
| 42272 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42274 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42275 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>> => (AMOMINU_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42276 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_AQ_RL), |
| 42277 | GIR_RootConstrainSelectedInstOperands, |
| 42278 | // GIR_Coverage, 1268, |
| 42279 | GIR_Done, |
| 42280 | // Label 2973: @109983 |
| 42281 | GIM_Try, /*On fail goto*//*Label 2974*/ GIMT_Encode4(110024), // Rule ID 1270 // |
| 42282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0), |
| 42283 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42284 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 42285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42286 | // MIs[0] rs1 |
| 42287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42289 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42290 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>> => (AMOMINU_H_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42291 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H_AQ_RL), |
| 42292 | GIR_RootConstrainSelectedInstOperands, |
| 42293 | // GIR_Coverage, 1270, |
| 42294 | GIR_Done, |
| 42295 | // Label 2974: @110024 |
| 42296 | GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(110065), // Rule ID 1272 // |
| 42297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42298 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42299 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic, |
| 42300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42301 | // MIs[0] rs1 |
| 42302 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42303 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42304 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42305 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>> => (AMOMINU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42306 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 42307 | GIR_RootConstrainSelectedInstOperands, |
| 42308 | // GIR_Coverage, 1272, |
| 42309 | GIR_Done, |
| 42310 | // Label 2975: @110065 |
| 42311 | GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(110106), // Rule ID 1274 // |
| 42312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42313 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42314 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire, |
| 42315 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42316 | // MIs[0] rs1 |
| 42317 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42318 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42319 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42320 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>> => (AMOMINU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42321 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 42322 | GIR_RootConstrainSelectedInstOperands, |
| 42323 | // GIR_Coverage, 1274, |
| 42324 | GIR_Done, |
| 42325 | // Label 2976: @110106 |
| 42326 | GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(110147), // Rule ID 1276 // |
| 42327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42328 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42329 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release, |
| 42330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42331 | // MIs[0] rs1 |
| 42332 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42333 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42334 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42335 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>> => (AMOMINU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42336 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 42337 | GIR_RootConstrainSelectedInstOperands, |
| 42338 | // GIR_Coverage, 1276, |
| 42339 | GIR_Done, |
| 42340 | // Label 2977: @110147 |
| 42341 | GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(110188), // Rule ID 1278 // |
| 42342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42343 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42344 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease, |
| 42345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42346 | // MIs[0] rs1 |
| 42347 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42348 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42349 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42350 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>> => (AMOMINU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42351 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 42352 | GIR_RootConstrainSelectedInstOperands, |
| 42353 | // GIR_Coverage, 1278, |
| 42354 | GIR_Done, |
| 42355 | // Label 2978: @110188 |
| 42356 | GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(110229), // Rule ID 1280 // |
| 42357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0), |
| 42358 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 42359 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent, |
| 42360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42361 | // MIs[0] rs1 |
| 42362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 42363 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42364 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42365 | // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>> => (AMOMINU_H:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42366 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AMOMINU_H), |
| 42367 | GIR_RootConstrainSelectedInstOperands, |
| 42368 | // GIR_Coverage, 1280, |
| 42369 | GIR_Done, |
| 42370 | // Label 2979: @110229 |
| 42371 | GIM_Reject, |
| 42372 | // Label 2939: @110230 |
| 42373 | GIM_Reject, |
| 42374 | // Label 2887: @110231 |
| 42375 | GIM_Reject, |
| 42376 | // Label 33: @110232 |
| 42377 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 2982*/ GIMT_Encode4(110449), |
| 42378 | /*GILLT_s32*//*Label 2980*/ GIMT_Encode4(110251), |
| 42379 | /*GILLT_s64*//*Label 2981*/ GIMT_Encode4(110350), |
| 42380 | // Label 2980: @110251 |
| 42381 | GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(110277), // Rule ID 236 // |
| 42382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 42383 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 4, |
| 42384 | // MIs[0] Operand 1 |
| 42385 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42386 | // (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 2:{ *:[i32] }, 3:{ *:[i32] }) |
| 42387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE), |
| 42388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 42389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42390 | GIR_RootConstrainSelectedInstOperands, |
| 42391 | // GIR_Coverage, 236, |
| 42392 | GIR_EraseRootFromParent_Done, |
| 42393 | // Label 2983: @110277 |
| 42394 | GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(110303), // Rule ID 238 // |
| 42395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 42396 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 5, |
| 42397 | // MIs[0] Operand 1 |
| 42398 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42399 | // (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 1:{ *:[i32] }) |
| 42400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE), |
| 42401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 42403 | GIR_RootConstrainSelectedInstOperands, |
| 42404 | // GIR_Coverage, 238, |
| 42405 | GIR_EraseRootFromParent_Done, |
| 42406 | // Label 2984: @110303 |
| 42407 | GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(110323), // Rule ID 240 // |
| 42408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 42409 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 6, |
| 42410 | // MIs[0] Operand 1 |
| 42411 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42412 | // (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE_TSO) |
| 42413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE_TSO), |
| 42414 | GIR_RootConstrainSelectedInstOperands, |
| 42415 | // GIR_Coverage, 240, |
| 42416 | GIR_EraseRootFromParent_Done, |
| 42417 | // Label 2985: @110323 |
| 42418 | GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(110349), // Rule ID 242 // |
| 42419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 42420 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7, |
| 42421 | // MIs[0] Operand 1 |
| 42422 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42423 | // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 42424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE), |
| 42425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42427 | GIR_RootConstrainSelectedInstOperands, |
| 42428 | // GIR_Coverage, 242, |
| 42429 | GIR_EraseRootFromParent_Done, |
| 42430 | // Label 2986: @110349 |
| 42431 | GIM_Reject, |
| 42432 | // Label 2981: @110350 |
| 42433 | GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(110376), // Rule ID 235 // |
| 42434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 42435 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 4, |
| 42436 | // MIs[0] Operand 1 |
| 42437 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42438 | // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 2:{ *:[i64] }, 3:{ *:[i64] }) |
| 42439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE), |
| 42440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 42441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42442 | GIR_RootConstrainSelectedInstOperands, |
| 42443 | // GIR_Coverage, 235, |
| 42444 | GIR_EraseRootFromParent_Done, |
| 42445 | // Label 2987: @110376 |
| 42446 | GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(110402), // Rule ID 237 // |
| 42447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 42448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 5, |
| 42449 | // MIs[0] Operand 1 |
| 42450 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42451 | // (atomic_fence 5:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 3:{ *:[i64] }, 1:{ *:[i64] }) |
| 42452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE), |
| 42453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 42455 | GIR_RootConstrainSelectedInstOperands, |
| 42456 | // GIR_Coverage, 237, |
| 42457 | GIR_EraseRootFromParent_Done, |
| 42458 | // Label 2988: @110402 |
| 42459 | GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(110422), // Rule ID 239 // |
| 42460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 42461 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 6, |
| 42462 | // MIs[0] Operand 1 |
| 42463 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42464 | // (atomic_fence 6:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE_TSO) |
| 42465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE_TSO), |
| 42466 | GIR_RootConstrainSelectedInstOperands, |
| 42467 | // GIR_Coverage, 239, |
| 42468 | GIR_EraseRootFromParent_Done, |
| 42469 | // Label 2989: @110422 |
| 42470 | GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(110448), // Rule ID 241 // |
| 42471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 42472 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7, |
| 42473 | // MIs[0] Operand 1 |
| 42474 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 42475 | // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 42476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FENCE), |
| 42477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 42479 | GIR_RootConstrainSelectedInstOperands, |
| 42480 | // GIR_Coverage, 241, |
| 42481 | GIR_EraseRootFromParent_Done, |
| 42482 | // Label 2990: @110448 |
| 42483 | GIM_Reject, |
| 42484 | // Label 2982: @110449 |
| 42485 | GIM_Reject, |
| 42486 | // Label 34: @110450 |
| 42487 | GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(110675), |
| 42488 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 42489 | GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(110494), // Rule ID 2865 // |
| 42490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknd_IsRV64_HwMode0), |
| 42491 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64im), |
| 42492 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42493 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42495 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42496 | // (intrinsic_wo_chain:{ *:[i64] } 10181:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1) => (AES64IM:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 42497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64IM), |
| 42498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42499 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42500 | GIR_RootConstrainSelectedInstOperands, |
| 42501 | // GIR_Coverage, 2865, |
| 42502 | GIR_EraseRootFromParent_Done, |
| 42503 | // Label 2992: @110494 |
| 42504 | GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(110530), // Rule ID 2886 // |
| 42505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV64_HwMode0), |
| 42506 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sig0), |
| 42507 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42508 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42510 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42511 | // (intrinsic_wo_chain:{ *:[i64] } 10319:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1) => (SHA512SIG0:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 42512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SIG0), |
| 42513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42515 | GIR_RootConstrainSelectedInstOperands, |
| 42516 | // GIR_Coverage, 2886, |
| 42517 | GIR_EraseRootFromParent_Done, |
| 42518 | // Label 2993: @110530 |
| 42519 | GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(110566), // Rule ID 2887 // |
| 42520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV64_HwMode0), |
| 42521 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sig1), |
| 42522 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42525 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42526 | // (intrinsic_wo_chain:{ *:[i64] } 10322:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1) => (SHA512SIG1:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 42527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SIG1), |
| 42528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42529 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42530 | GIR_RootConstrainSelectedInstOperands, |
| 42531 | // GIR_Coverage, 2887, |
| 42532 | GIR_EraseRootFromParent_Done, |
| 42533 | // Label 2994: @110566 |
| 42534 | GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(110602), // Rule ID 2888 // |
| 42535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV64_HwMode0), |
| 42536 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sum0), |
| 42537 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42538 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42539 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42540 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42541 | // (intrinsic_wo_chain:{ *:[i64] } 10325:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1) => (SHA512SUM0:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 42542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SUM0), |
| 42543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42544 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42545 | GIR_RootConstrainSelectedInstOperands, |
| 42546 | // GIR_Coverage, 2888, |
| 42547 | GIR_EraseRootFromParent_Done, |
| 42548 | // Label 2995: @110602 |
| 42549 | GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(110638), // Rule ID 2889 // |
| 42550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV64_HwMode0), |
| 42551 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sum1), |
| 42552 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42553 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42555 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42556 | // (intrinsic_wo_chain:{ *:[i64] } 10327:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1) => (SHA512SUM1:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 42557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SUM1), |
| 42558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42559 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42560 | GIR_RootConstrainSelectedInstOperands, |
| 42561 | // GIR_Coverage, 2889, |
| 42562 | GIR_EraseRootFromParent_Done, |
| 42563 | // Label 2996: @110638 |
| 42564 | GIM_Try, /*On fail goto*//*Label 2997*/ GIMT_Encode4(110674), // Rule ID 64960 // |
| 42565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 42566 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_clb), |
| 42567 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42570 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42571 | // (intrinsic_wo_chain:{ *:[i32] } 10201:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1) => (CV_CLB:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 42572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_CLB), |
| 42573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42574 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42575 | GIR_RootConstrainSelectedInstOperands, |
| 42576 | // GIR_Coverage, 64960, |
| 42577 | GIR_EraseRootFromParent_Done, |
| 42578 | // Label 2997: @110674 |
| 42579 | GIM_Reject, |
| 42580 | // Label 2991: @110675 |
| 42581 | GIM_Try, /*On fail goto*//*Label 2998*/ GIMT_Encode4(111675), |
| 42582 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 42583 | GIM_Try, /*On fail goto*//*Label 2999*/ GIMT_Encode4(110729), // Rule ID 2867 // |
| 42584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZkndOrZkne_IsRV64_HwMode0), |
| 42585 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64ks1i), |
| 42586 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42587 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42589 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42590 | // MIs[0] rnum |
| 42591 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 42592 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_rnum), |
| 42593 | // (intrinsic_wo_chain:{ *:[i64] } 10182:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, (timm:{ *:[i32] })<<P:Predicate_rnum>>:$rnum) => (AES64KS1I:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (timm:{ *:[i32] })<<P:Predicate_rnum>>:$rnum) |
| 42594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64KS1I), |
| 42595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42596 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42597 | GIR_RootToRootCopy, /*OpIdx*/3, // rnum |
| 42598 | GIR_RootConstrainSelectedInstOperands, |
| 42599 | // GIR_Coverage, 2867, |
| 42600 | GIR_EraseRootFromParent_Done, |
| 42601 | // Label 2999: @110729 |
| 42602 | GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(110774), // Rule ID 64968 // |
| 42603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 42604 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_clip), |
| 42605 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42606 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42607 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42609 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42610 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42611 | // (intrinsic_wo_chain:{ *:[i32] } 10192:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_CLIPR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_CLIPR), |
| 42613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42614 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42615 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42616 | GIR_RootConstrainSelectedInstOperands, |
| 42617 | // GIR_Coverage, 64968, |
| 42618 | GIR_EraseRootFromParent_Done, |
| 42619 | // Label 3000: @110774 |
| 42620 | GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(110819), // Rule ID 64993 // |
| 42621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 42622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_clipu), |
| 42623 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42627 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42628 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42629 | // (intrinsic_wo_chain:{ *:[i32] } 10193:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_CLIPUR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_CLIPUR), |
| 42631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42632 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42633 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42634 | GIR_RootConstrainSelectedInstOperands, |
| 42635 | // GIR_Coverage, 64993, |
| 42636 | GIR_EraseRootFromParent_Done, |
| 42637 | // Label 3001: @110819 |
| 42638 | GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(110864), // Rule ID 2789 // |
| 42639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkx_HwMode0), |
| 42640 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_xperm4), |
| 42641 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42642 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42643 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42646 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42647 | // (intrinsic_wo_chain:{ *:[i64] } 10883:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (XPERM4:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XPERM4), |
| 42649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42650 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42651 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42652 | GIR_RootConstrainSelectedInstOperands, |
| 42653 | // GIR_Coverage, 2789, |
| 42654 | GIR_EraseRootFromParent_Done, |
| 42655 | // Label 3002: @110864 |
| 42656 | GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(110909), // Rule ID 2790 // |
| 42657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkx_HwMode1), |
| 42658 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_xperm4), |
| 42659 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42663 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42664 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42665 | // (intrinsic_wo_chain:{ *:[i32] } 10883:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XPERM4:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XPERM4), |
| 42667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42668 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42669 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42670 | GIR_RootConstrainSelectedInstOperands, |
| 42671 | // GIR_Coverage, 2790, |
| 42672 | GIR_EraseRootFromParent_Done, |
| 42673 | // Label 3003: @110909 |
| 42674 | GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(110954), // Rule ID 2791 // |
| 42675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkx_HwMode0), |
| 42676 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_xperm8), |
| 42677 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42678 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42679 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42682 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42683 | // (intrinsic_wo_chain:{ *:[i64] } 10884:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (XPERM8:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XPERM8), |
| 42685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42687 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42688 | GIR_RootConstrainSelectedInstOperands, |
| 42689 | // GIR_Coverage, 2791, |
| 42690 | GIR_EraseRootFromParent_Done, |
| 42691 | // Label 3004: @110954 |
| 42692 | GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(110999), // Rule ID 2792 // |
| 42693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkx_HwMode1), |
| 42694 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_xperm8), |
| 42695 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42697 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42699 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42700 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42701 | // (intrinsic_wo_chain:{ *:[i32] } 10884:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XPERM8:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XPERM8), |
| 42703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42704 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42705 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42706 | GIR_RootConstrainSelectedInstOperands, |
| 42707 | // GIR_Coverage, 2792, |
| 42708 | GIR_EraseRootFromParent_Done, |
| 42709 | // Label 3005: @110999 |
| 42710 | GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(111044), // Rule ID 2863 // |
| 42711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknd_IsRV64_HwMode0), |
| 42712 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64ds), |
| 42713 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42714 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42715 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42717 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42718 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42719 | // (intrinsic_wo_chain:{ *:[i64] } 10177:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AES64DS:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64DS), |
| 42721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42722 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42723 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42724 | GIR_RootConstrainSelectedInstOperands, |
| 42725 | // GIR_Coverage, 2863, |
| 42726 | GIR_EraseRootFromParent_Done, |
| 42727 | // Label 3006: @111044 |
| 42728 | GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(111089), // Rule ID 2864 // |
| 42729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknd_IsRV64_HwMode0), |
| 42730 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64dsm), |
| 42731 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42732 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42733 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42735 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42736 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42737 | // (intrinsic_wo_chain:{ *:[i64] } 10178:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AES64DSM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64DSM), |
| 42739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42740 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42741 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42742 | GIR_RootConstrainSelectedInstOperands, |
| 42743 | // GIR_Coverage, 2864, |
| 42744 | GIR_EraseRootFromParent_Done, |
| 42745 | // Label 3007: @111089 |
| 42746 | GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(111134), // Rule ID 2866 // |
| 42747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZkndOrZkne_IsRV64_HwMode0), |
| 42748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64ks2), |
| 42749 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42751 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42754 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42755 | // (intrinsic_wo_chain:{ *:[i64] } 10183:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AES64KS2:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64KS2), |
| 42757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42758 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42759 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42760 | GIR_RootConstrainSelectedInstOperands, |
| 42761 | // GIR_Coverage, 2866, |
| 42762 | GIR_EraseRootFromParent_Done, |
| 42763 | // Label 3008: @111134 |
| 42764 | GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(111179), // Rule ID 2870 // |
| 42765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZkne_IsRV64_HwMode0), |
| 42766 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64es), |
| 42767 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42768 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42769 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42771 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42772 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42773 | // (intrinsic_wo_chain:{ *:[i64] } 10179:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AES64ES:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64ES), |
| 42775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42776 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42777 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42778 | GIR_RootConstrainSelectedInstOperands, |
| 42779 | // GIR_Coverage, 2870, |
| 42780 | GIR_EraseRootFromParent_Done, |
| 42781 | // Label 3009: @111179 |
| 42782 | GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(111224), // Rule ID 2871 // |
| 42783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZkne_IsRV64_HwMode0), |
| 42784 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes64esm), |
| 42785 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 42786 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42787 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 42788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42789 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42790 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42791 | // (intrinsic_wo_chain:{ *:[i64] } 10180:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AES64ESM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 42792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES64ESM), |
| 42793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42794 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42795 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42796 | GIR_RootConstrainSelectedInstOperands, |
| 42797 | // GIR_Coverage, 2871, |
| 42798 | GIR_EraseRootFromParent_Done, |
| 42799 | // Label 3010: @111224 |
| 42800 | GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(111269), // Rule ID 2880 // |
| 42801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV32_HwMode1), |
| 42802 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sig0l), |
| 42803 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42804 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42805 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42807 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42808 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42809 | // (intrinsic_wo_chain:{ *:[i32] } 10321:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SHA512SIG0L:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SIG0L), |
| 42811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42812 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42813 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42814 | GIR_RootConstrainSelectedInstOperands, |
| 42815 | // GIR_Coverage, 2880, |
| 42816 | GIR_EraseRootFromParent_Done, |
| 42817 | // Label 3011: @111269 |
| 42818 | GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(111314), // Rule ID 2881 // |
| 42819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV32_HwMode1), |
| 42820 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sig0h), |
| 42821 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42822 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42823 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42826 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42827 | // (intrinsic_wo_chain:{ *:[i32] } 10320:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SHA512SIG0H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SIG0H), |
| 42829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42830 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42831 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42832 | GIR_RootConstrainSelectedInstOperands, |
| 42833 | // GIR_Coverage, 2881, |
| 42834 | GIR_EraseRootFromParent_Done, |
| 42835 | // Label 3012: @111314 |
| 42836 | GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(111359), // Rule ID 2882 // |
| 42837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV32_HwMode1), |
| 42838 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sig1l), |
| 42839 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42840 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42841 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42844 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42845 | // (intrinsic_wo_chain:{ *:[i32] } 10324:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SHA512SIG1L:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SIG1L), |
| 42847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42848 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42849 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42850 | GIR_RootConstrainSelectedInstOperands, |
| 42851 | // GIR_Coverage, 2882, |
| 42852 | GIR_EraseRootFromParent_Done, |
| 42853 | // Label 3013: @111359 |
| 42854 | GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(111404), // Rule ID 2883 // |
| 42855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV32_HwMode1), |
| 42856 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sig1h), |
| 42857 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42859 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42862 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42863 | // (intrinsic_wo_chain:{ *:[i32] } 10323:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SHA512SIG1H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SIG1H), |
| 42865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42866 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42867 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42868 | GIR_RootConstrainSelectedInstOperands, |
| 42869 | // GIR_Coverage, 2883, |
| 42870 | GIR_EraseRootFromParent_Done, |
| 42871 | // Label 3014: @111404 |
| 42872 | GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(111449), // Rule ID 2884 // |
| 42873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV32_HwMode1), |
| 42874 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sum0r), |
| 42875 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42876 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42877 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42880 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42881 | // (intrinsic_wo_chain:{ *:[i32] } 10326:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SHA512SUM0R:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SUM0R), |
| 42883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42885 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42886 | GIR_RootConstrainSelectedInstOperands, |
| 42887 | // GIR_Coverage, 2884, |
| 42888 | GIR_EraseRootFromParent_Done, |
| 42889 | // Label 3015: @111449 |
| 42890 | GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(111494), // Rule ID 2885 // |
| 42891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknh_IsRV32_HwMode1), |
| 42892 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_sha512sum1r), |
| 42893 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42894 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42895 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42897 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42898 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42899 | // (intrinsic_wo_chain:{ *:[i32] } 10328:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SHA512SUM1R:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SHA512SUM1R), |
| 42901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42902 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42903 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42904 | GIR_RootConstrainSelectedInstOperands, |
| 42905 | // GIR_Coverage, 2885, |
| 42906 | GIR_EraseRootFromParent_Done, |
| 42907 | // Label 3016: @111494 |
| 42908 | GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(111539), // Rule ID 64945 // |
| 42909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 42910 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_extract), |
| 42911 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42913 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42916 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42917 | // (intrinsic_wo_chain:{ *:[i32] } 10202:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_EXTRACTR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_EXTRACTR), |
| 42919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42920 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42921 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42922 | GIR_RootConstrainSelectedInstOperands, |
| 42923 | // GIR_Coverage, 64945, |
| 42924 | GIR_EraseRootFromParent_Done, |
| 42925 | // Label 3017: @111539 |
| 42926 | GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(111584), // Rule ID 64947 // |
| 42927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 42928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_extractu), |
| 42929 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42930 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42931 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42933 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42934 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42935 | // (intrinsic_wo_chain:{ *:[i32] } 10203:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_EXTRACTUR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_EXTRACTUR), |
| 42937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42938 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42939 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42940 | GIR_RootConstrainSelectedInstOperands, |
| 42941 | // GIR_Coverage, 64947, |
| 42942 | GIR_EraseRootFromParent_Done, |
| 42943 | // Label 3018: @111584 |
| 42944 | GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(111629), // Rule ID 64949 // |
| 42945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 42946 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_bclr), |
| 42947 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42948 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42949 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42951 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42952 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42953 | // (intrinsic_wo_chain:{ *:[i32] } 10198:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_BCLRR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_BCLRR), |
| 42955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42956 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42957 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42958 | GIR_RootConstrainSelectedInstOperands, |
| 42959 | // GIR_Coverage, 64949, |
| 42960 | GIR_EraseRootFromParent_Done, |
| 42961 | // Label 3019: @111629 |
| 42962 | GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(111674), // Rule ID 64951 // |
| 42963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 42964 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_bset), |
| 42965 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42966 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42967 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 42968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42970 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42971 | // (intrinsic_wo_chain:{ *:[i32] } 10200:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_BSETR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 42972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_BSETR), |
| 42973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 42974 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 42975 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 42976 | GIR_RootConstrainSelectedInstOperands, |
| 42977 | // GIR_Coverage, 64951, |
| 42978 | GIR_EraseRootFromParent_Done, |
| 42979 | // Label 3020: @111674 |
| 42980 | GIM_Reject, |
| 42981 | // Label 2998: @111675 |
| 42982 | GIM_Try, /*On fail goto*//*Label 3021*/ GIMT_Encode4(114108), |
| 42983 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 42984 | GIM_Try, /*On fail goto*//*Label 3022*/ GIMT_Encode4(111739), // Rule ID 64965 // |
| 42985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 42986 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_bitrev), |
| 42987 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42988 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42990 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 42991 | // MIs[0] pts |
| 42992 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 42993 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 42994 | // MIs[0] radix |
| 42995 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 42996 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm2), |
| 42997 | // (intrinsic_wo_chain:{ *:[i32] } 10199:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$pts, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm2>>:$radix) => (CV_BITREV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm2>>:$radix, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$pts) |
| 42998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_BITREV), |
| 42999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43000 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43001 | GIR_RootToRootCopy, /*OpIdx*/4, // radix |
| 43002 | GIR_RootToRootCopy, /*OpIdx*/3, // pts |
| 43003 | GIR_RootConstrainSelectedInstOperands, |
| 43004 | // GIR_Coverage, 64965, |
| 43005 | GIR_EraseRootFromParent_Done, |
| 43006 | // Label 3022: @111739 |
| 43007 | GIM_Try, /*On fail goto*//*Label 3023*/ GIMT_Encode4(111804), // Rule ID 64972 // |
| 43008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43009 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addn), |
| 43010 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43011 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43012 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43013 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43015 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43016 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43017 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43018 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43019 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43020 | // MIs[1] Operand 1 |
| 43021 | // No operand predicates |
| 43022 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43023 | // (intrinsic_wo_chain:{ *:[i32] } 10188:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_ADDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDN), |
| 43025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43026 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43027 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43028 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43029 | GIR_RootConstrainSelectedInstOperands, |
| 43030 | // GIR_Coverage, 64972, |
| 43031 | GIR_EraseRootFromParent_Done, |
| 43032 | // Label 3023: @111804 |
| 43033 | GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(111869), // Rule ID 64997 // |
| 43034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43035 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addun), |
| 43036 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43037 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43038 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43039 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43041 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43042 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43043 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43044 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43045 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43046 | // MIs[1] Operand 1 |
| 43047 | // No operand predicates |
| 43048 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43049 | // (intrinsic_wo_chain:{ *:[i32] } 10190:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_ADDUN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDUN), |
| 43051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43052 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43053 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43054 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43055 | GIR_RootConstrainSelectedInstOperands, |
| 43056 | // GIR_Coverage, 64997, |
| 43057 | GIR_EraseRootFromParent_Done, |
| 43058 | // Label 3024: @111869 |
| 43059 | GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(111934), // Rule ID 65000 // |
| 43060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43061 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addrn), |
| 43062 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43063 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43064 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43065 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43067 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43068 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43069 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43070 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43071 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43072 | // MIs[1] Operand 1 |
| 43073 | // No operand predicates |
| 43074 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43075 | // (intrinsic_wo_chain:{ *:[i32] } 10189:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_ADDRN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDRN), |
| 43077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43078 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43079 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43080 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43081 | GIR_RootConstrainSelectedInstOperands, |
| 43082 | // GIR_Coverage, 65000, |
| 43083 | GIR_EraseRootFromParent_Done, |
| 43084 | // Label 3025: @111934 |
| 43085 | GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(111999), // Rule ID 65003 // |
| 43086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addurn), |
| 43088 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43089 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43090 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43091 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43093 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43094 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43096 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43097 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43098 | // MIs[1] Operand 1 |
| 43099 | // No operand predicates |
| 43100 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43101 | // (intrinsic_wo_chain:{ *:[i32] } 10191:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_ADDURN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDURN), |
| 43103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43104 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43105 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43106 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43107 | GIR_RootConstrainSelectedInstOperands, |
| 43108 | // GIR_Coverage, 65003, |
| 43109 | GIR_EraseRootFromParent_Done, |
| 43110 | // Label 3026: @111999 |
| 43111 | GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(112064), // Rule ID 65006 // |
| 43112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43113 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subn), |
| 43114 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43115 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43116 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43117 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43120 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43121 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43122 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43123 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43124 | // MIs[1] Operand 1 |
| 43125 | // No operand predicates |
| 43126 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43127 | // (intrinsic_wo_chain:{ *:[i32] } 10194:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_SUBN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBN), |
| 43129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43130 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43131 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43132 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43133 | GIR_RootConstrainSelectedInstOperands, |
| 43134 | // GIR_Coverage, 65006, |
| 43135 | GIR_EraseRootFromParent_Done, |
| 43136 | // Label 3027: @112064 |
| 43137 | GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(112129), // Rule ID 65009 // |
| 43138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43139 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subun), |
| 43140 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43142 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43143 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43146 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43148 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43149 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43150 | // MIs[1] Operand 1 |
| 43151 | // No operand predicates |
| 43152 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43153 | // (intrinsic_wo_chain:{ *:[i32] } 10196:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_SUBUN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBUN), |
| 43155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43156 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43157 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43158 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43159 | GIR_RootConstrainSelectedInstOperands, |
| 43160 | // GIR_Coverage, 65009, |
| 43161 | GIR_EraseRootFromParent_Done, |
| 43162 | // Label 3028: @112129 |
| 43163 | GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(112194), // Rule ID 65012 // |
| 43164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43165 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subrn), |
| 43166 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43167 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43168 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43169 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43171 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43172 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43173 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43174 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43175 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43176 | // MIs[1] Operand 1 |
| 43177 | // No operand predicates |
| 43178 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43179 | // (intrinsic_wo_chain:{ *:[i32] } 10195:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_SUBRN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBRN), |
| 43181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43182 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43183 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43184 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43185 | GIR_RootConstrainSelectedInstOperands, |
| 43186 | // GIR_Coverage, 65012, |
| 43187 | GIR_EraseRootFromParent_Done, |
| 43188 | // Label 3029: @112194 |
| 43189 | GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(112259), // Rule ID 65015 // |
| 43190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43191 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_suburn), |
| 43192 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43193 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43194 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43195 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43197 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43198 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 43200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 43201 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 43202 | // MIs[1] Operand 1 |
| 43203 | // No operand predicates |
| 43204 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43205 | // (intrinsic_wo_chain:{ *:[i32] } 10197:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (CV_SUBURN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 43206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBURN), |
| 43207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43208 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43209 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43210 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 43211 | GIR_RootConstrainSelectedInstOperands, |
| 43212 | // GIR_Coverage, 65015, |
| 43213 | GIR_EraseRootFromParent_Done, |
| 43214 | // Label 3030: @112259 |
| 43215 | GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(112314), // Rule ID 2861 // |
| 43216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknd_IsRV32_HwMode1), |
| 43217 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes32dsi), |
| 43218 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43219 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43220 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43222 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43223 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43224 | // MIs[0] imm |
| 43225 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43226 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_byteselect), |
| 43227 | // (intrinsic_wo_chain:{ *:[i32] } 10173:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) => (AES32DSI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) |
| 43228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES32DSI), |
| 43229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43230 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43231 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43232 | GIR_RootToRootCopy, /*OpIdx*/4, // imm |
| 43233 | GIR_RootConstrainSelectedInstOperands, |
| 43234 | // GIR_Coverage, 2861, |
| 43235 | GIR_EraseRootFromParent_Done, |
| 43236 | // Label 3031: @112314 |
| 43237 | GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(112369), // Rule ID 2862 // |
| 43238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZknd_IsRV32_HwMode1), |
| 43239 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes32dsmi), |
| 43240 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43241 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43242 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43244 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43245 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43246 | // MIs[0] imm |
| 43247 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43248 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_byteselect), |
| 43249 | // (intrinsic_wo_chain:{ *:[i32] } 10174:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) => (AES32DSMI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) |
| 43250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES32DSMI), |
| 43251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43252 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43253 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43254 | GIR_RootToRootCopy, /*OpIdx*/4, // imm |
| 43255 | GIR_RootConstrainSelectedInstOperands, |
| 43256 | // GIR_Coverage, 2862, |
| 43257 | GIR_EraseRootFromParent_Done, |
| 43258 | // Label 3032: @112369 |
| 43259 | GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(112424), // Rule ID 2868 // |
| 43260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZkne_IsRV32_HwMode1), |
| 43261 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes32esi), |
| 43262 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43263 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43264 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43266 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43267 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43268 | // MIs[0] imm |
| 43269 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43270 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_byteselect), |
| 43271 | // (intrinsic_wo_chain:{ *:[i32] } 10175:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) => (AES32ESI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) |
| 43272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES32ESI), |
| 43273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43274 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43275 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43276 | GIR_RootToRootCopy, /*OpIdx*/4, // imm |
| 43277 | GIR_RootConstrainSelectedInstOperands, |
| 43278 | // GIR_Coverage, 2868, |
| 43279 | GIR_EraseRootFromParent_Done, |
| 43280 | // Label 3033: @112424 |
| 43281 | GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(112479), // Rule ID 2869 // |
| 43282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZkne_IsRV32_HwMode1), |
| 43283 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_aes32esmi), |
| 43284 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43285 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43286 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43288 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43289 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43290 | // MIs[0] imm |
| 43291 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43292 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_byteselect), |
| 43293 | // (intrinsic_wo_chain:{ *:[i32] } 10176:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) => (AES32ESMI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_byteselect>>:$imm) |
| 43294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::AES32ESMI), |
| 43295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43297 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43298 | GIR_RootToRootCopy, /*OpIdx*/4, // imm |
| 43299 | GIR_RootConstrainSelectedInstOperands, |
| 43300 | // GIR_Coverage, 2869, |
| 43301 | GIR_EraseRootFromParent_Done, |
| 43302 | // Label 3034: @112479 |
| 43303 | GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(112534), // Rule ID 65026 // |
| 43304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43305 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_muluN), |
| 43306 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43307 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43308 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43311 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43312 | // MIs[0] imm5 |
| 43313 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43314 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43315 | // (intrinsic_wo_chain:{ *:[i32] } 10221:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULUN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULUN), |
| 43317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43318 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43319 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43320 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43321 | GIR_RootConstrainSelectedInstOperands, |
| 43322 | // GIR_Coverage, 65026, |
| 43323 | GIR_EraseRootFromParent_Done, |
| 43324 | // Label 3035: @112534 |
| 43325 | GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(112589), // Rule ID 65027 // |
| 43326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43327 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mulhhuN), |
| 43328 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43329 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43330 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43332 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43333 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43334 | // MIs[0] imm5 |
| 43335 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43336 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43337 | // (intrinsic_wo_chain:{ *:[i32] } 10217:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULHHUN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULHHUN), |
| 43339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43340 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43341 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43342 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43343 | GIR_RootConstrainSelectedInstOperands, |
| 43344 | // GIR_Coverage, 65027, |
| 43345 | GIR_EraseRootFromParent_Done, |
| 43346 | // Label 3036: @112589 |
| 43347 | GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(112644), // Rule ID 65028 // |
| 43348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43349 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mulsN), |
| 43350 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43351 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43352 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43354 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43355 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43356 | // MIs[0] imm5 |
| 43357 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43358 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43359 | // (intrinsic_wo_chain:{ *:[i32] } 10219:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULSN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULSN), |
| 43361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43362 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43363 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43364 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43365 | GIR_RootConstrainSelectedInstOperands, |
| 43366 | // GIR_Coverage, 65028, |
| 43367 | GIR_EraseRootFromParent_Done, |
| 43368 | // Label 3037: @112644 |
| 43369 | GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(112699), // Rule ID 65029 // |
| 43370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43371 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mulhhsN), |
| 43372 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43373 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43374 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43377 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43378 | // MIs[0] imm5 |
| 43379 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43380 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43381 | // (intrinsic_wo_chain:{ *:[i32] } 10215:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULHHSN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULHHSN), |
| 43383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43384 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43385 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43386 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43387 | GIR_RootConstrainSelectedInstOperands, |
| 43388 | // GIR_Coverage, 65029, |
| 43389 | GIR_EraseRootFromParent_Done, |
| 43390 | // Label 3038: @112699 |
| 43391 | GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(112754), // Rule ID 65030 // |
| 43392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43393 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_muluRN), |
| 43394 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43396 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43398 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43399 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43400 | // MIs[0] imm5 |
| 43401 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43402 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43403 | // (intrinsic_wo_chain:{ *:[i32] } 10222:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULURN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULURN), |
| 43405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43407 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43408 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43409 | GIR_RootConstrainSelectedInstOperands, |
| 43410 | // GIR_Coverage, 65030, |
| 43411 | GIR_EraseRootFromParent_Done, |
| 43412 | // Label 3039: @112754 |
| 43413 | GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(112809), // Rule ID 65031 // |
| 43414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43415 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mulhhuRN), |
| 43416 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43417 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43418 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43420 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43421 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43422 | // MIs[0] imm5 |
| 43423 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43424 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43425 | // (intrinsic_wo_chain:{ *:[i32] } 10218:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULHHURN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULHHURN), |
| 43427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43428 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43429 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43430 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43431 | GIR_RootConstrainSelectedInstOperands, |
| 43432 | // GIR_Coverage, 65031, |
| 43433 | GIR_EraseRootFromParent_Done, |
| 43434 | // Label 3040: @112809 |
| 43435 | GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(112864), // Rule ID 65032 // |
| 43436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43437 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mulsRN), |
| 43438 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43439 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43440 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43442 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43443 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43444 | // MIs[0] imm5 |
| 43445 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43446 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43447 | // (intrinsic_wo_chain:{ *:[i32] } 10220:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULSRN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULSRN), |
| 43449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43450 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43451 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43452 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43453 | GIR_RootConstrainSelectedInstOperands, |
| 43454 | // GIR_Coverage, 65032, |
| 43455 | GIR_EraseRootFromParent_Done, |
| 43456 | // Label 3041: @112864 |
| 43457 | GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(112919), // Rule ID 65033 // |
| 43458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43459 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mulhhsRN), |
| 43460 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43461 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43462 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43464 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43465 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43466 | // MIs[0] imm5 |
| 43467 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 43468 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43469 | // (intrinsic_wo_chain:{ *:[i32] } 10216:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MULHHSRN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MULHHSRN), |
| 43471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 43472 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43473 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43474 | GIR_RootToRootCopy, /*OpIdx*/4, // imm5 |
| 43475 | GIR_RootConstrainSelectedInstOperands, |
| 43476 | // GIR_Coverage, 65033, |
| 43477 | GIR_EraseRootFromParent_Done, |
| 43478 | // Label 3042: @112919 |
| 43479 | GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(112973), // Rule ID 64970 // |
| 43480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43481 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addn), |
| 43482 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43483 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43484 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43485 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43486 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43487 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43488 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43489 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43490 | // (intrinsic_wo_chain:{ *:[i32] } 10188:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDNR), |
| 43492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43493 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43494 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43495 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43496 | GIR_RootConstrainSelectedInstOperands, |
| 43497 | // GIR_Coverage, 64970, |
| 43498 | GIR_EraseRootFromParent_Done, |
| 43499 | // Label 3043: @112973 |
| 43500 | GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(113027), // Rule ID 64971 // |
| 43501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addn), |
| 43503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43506 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43508 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43509 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43510 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43511 | // (intrinsic_wo_chain:{ *:[i32] } 10188:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDNR), |
| 43513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43515 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43516 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43517 | GIR_RootConstrainSelectedInstOperands, |
| 43518 | // GIR_Coverage, 64971, |
| 43519 | GIR_EraseRootFromParent_Done, |
| 43520 | // Label 3044: @113027 |
| 43521 | GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(113081), // Rule ID 64995 // |
| 43522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43523 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addun), |
| 43524 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43525 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43526 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43527 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43530 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43531 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43532 | // (intrinsic_wo_chain:{ *:[i32] } 10190:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDUNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDUNR), |
| 43534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43535 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43536 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43537 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43538 | GIR_RootConstrainSelectedInstOperands, |
| 43539 | // GIR_Coverage, 64995, |
| 43540 | GIR_EraseRootFromParent_Done, |
| 43541 | // Label 3045: @113081 |
| 43542 | GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(113135), // Rule ID 64996 // |
| 43543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43544 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addun), |
| 43545 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43546 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43547 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43548 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43550 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43551 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43552 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43553 | // (intrinsic_wo_chain:{ *:[i32] } 10190:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDUNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDUNR), |
| 43555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43556 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43557 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43558 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43559 | GIR_RootConstrainSelectedInstOperands, |
| 43560 | // GIR_Coverage, 64996, |
| 43561 | GIR_EraseRootFromParent_Done, |
| 43562 | // Label 3046: @113135 |
| 43563 | GIM_Try, /*On fail goto*//*Label 3047*/ GIMT_Encode4(113189), // Rule ID 64998 // |
| 43564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43565 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addrn), |
| 43566 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43567 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43568 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43569 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43571 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43572 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43573 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43574 | // (intrinsic_wo_chain:{ *:[i32] } 10189:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDRNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDRNR), |
| 43576 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43577 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43578 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43579 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43580 | GIR_RootConstrainSelectedInstOperands, |
| 43581 | // GIR_Coverage, 64998, |
| 43582 | GIR_EraseRootFromParent_Done, |
| 43583 | // Label 3047: @113189 |
| 43584 | GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(113243), // Rule ID 64999 // |
| 43585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addrn), |
| 43587 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43589 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43590 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43592 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43593 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43594 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43595 | // (intrinsic_wo_chain:{ *:[i32] } 10189:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDRNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDRNR), |
| 43597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43598 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43599 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43600 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43601 | GIR_RootConstrainSelectedInstOperands, |
| 43602 | // GIR_Coverage, 64999, |
| 43603 | GIR_EraseRootFromParent_Done, |
| 43604 | // Label 3048: @113243 |
| 43605 | GIM_Try, /*On fail goto*//*Label 3049*/ GIMT_Encode4(113297), // Rule ID 65001 // |
| 43606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43607 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addurn), |
| 43608 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43609 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43610 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43611 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43614 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43615 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43616 | // (intrinsic_wo_chain:{ *:[i32] } 10191:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDURNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDURNR), |
| 43618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43619 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43620 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43621 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43622 | GIR_RootConstrainSelectedInstOperands, |
| 43623 | // GIR_Coverage, 65001, |
| 43624 | GIR_EraseRootFromParent_Done, |
| 43625 | // Label 3049: @113297 |
| 43626 | GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(113351), // Rule ID 65002 // |
| 43627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_addurn), |
| 43629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43631 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43632 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43635 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43636 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43637 | // (intrinsic_wo_chain:{ *:[i32] } 10191:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_ADDURNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_ADDURNR), |
| 43639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43640 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43641 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43642 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43643 | GIR_RootConstrainSelectedInstOperands, |
| 43644 | // GIR_Coverage, 65002, |
| 43645 | GIR_EraseRootFromParent_Done, |
| 43646 | // Label 3050: @113351 |
| 43647 | GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(113405), // Rule ID 65004 // |
| 43648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43649 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subn), |
| 43650 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43651 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43652 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43653 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43656 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43657 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43658 | // (intrinsic_wo_chain:{ *:[i32] } 10194:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBNR), |
| 43660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43662 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43663 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43664 | GIR_RootConstrainSelectedInstOperands, |
| 43665 | // GIR_Coverage, 65004, |
| 43666 | GIR_EraseRootFromParent_Done, |
| 43667 | // Label 3051: @113405 |
| 43668 | GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(113459), // Rule ID 65005 // |
| 43669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43670 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subn), |
| 43671 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43673 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43674 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43676 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43677 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43678 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43679 | // (intrinsic_wo_chain:{ *:[i32] } 10194:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBNR), |
| 43681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43682 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43683 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43684 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43685 | GIR_RootConstrainSelectedInstOperands, |
| 43686 | // GIR_Coverage, 65005, |
| 43687 | GIR_EraseRootFromParent_Done, |
| 43688 | // Label 3052: @113459 |
| 43689 | GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(113513), // Rule ID 65007 // |
| 43690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43691 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subun), |
| 43692 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43693 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43694 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43695 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43698 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43699 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43700 | // (intrinsic_wo_chain:{ *:[i32] } 10196:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBUNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBUNR), |
| 43702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43703 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43704 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43705 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43706 | GIR_RootConstrainSelectedInstOperands, |
| 43707 | // GIR_Coverage, 65007, |
| 43708 | GIR_EraseRootFromParent_Done, |
| 43709 | // Label 3053: @113513 |
| 43710 | GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(113567), // Rule ID 65008 // |
| 43711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43712 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subun), |
| 43713 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43714 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43715 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43716 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43717 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43718 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43719 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43720 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43721 | // (intrinsic_wo_chain:{ *:[i32] } 10196:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBUNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBUNR), |
| 43723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43724 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43725 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43726 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43727 | GIR_RootConstrainSelectedInstOperands, |
| 43728 | // GIR_Coverage, 65008, |
| 43729 | GIR_EraseRootFromParent_Done, |
| 43730 | // Label 3054: @113567 |
| 43731 | GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(113621), // Rule ID 65010 // |
| 43732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43733 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subrn), |
| 43734 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43735 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43736 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43737 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43739 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43740 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43741 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43742 | // (intrinsic_wo_chain:{ *:[i32] } 10195:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBRNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBRNR), |
| 43744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43745 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43746 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43747 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43748 | GIR_RootConstrainSelectedInstOperands, |
| 43749 | // GIR_Coverage, 65010, |
| 43750 | GIR_EraseRootFromParent_Done, |
| 43751 | // Label 3055: @113621 |
| 43752 | GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(113675), // Rule ID 65011 // |
| 43753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43754 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_subrn), |
| 43755 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43756 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43757 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43758 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43761 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43762 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43763 | // (intrinsic_wo_chain:{ *:[i32] } 10195:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBRNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBRNR), |
| 43765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43766 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43767 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43768 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43769 | GIR_RootConstrainSelectedInstOperands, |
| 43770 | // GIR_Coverage, 65011, |
| 43771 | GIR_EraseRootFromParent_Done, |
| 43772 | // Label 3056: @113675 |
| 43773 | GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(113729), // Rule ID 65013 // |
| 43774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 43775 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_suburn), |
| 43776 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43777 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43778 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43779 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43781 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43782 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43783 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43784 | // (intrinsic_wo_chain:{ *:[i32] } 10197:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBURNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBURNR), |
| 43786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43787 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43788 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43789 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43790 | GIR_RootConstrainSelectedInstOperands, |
| 43791 | // GIR_Coverage, 65013, |
| 43792 | GIR_EraseRootFromParent_Done, |
| 43793 | // Label 3057: @113729 |
| 43794 | GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(113783), // Rule ID 65014 // |
| 43795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 43796 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_alu_suburn), |
| 43797 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43798 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43799 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43800 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43802 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43803 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43804 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43805 | // (intrinsic_wo_chain:{ *:[i32] } 10197:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) => (CV_SUBURNR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs3) |
| 43806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SUBURNR), |
| 43807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43808 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43809 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43810 | GIR_RootToRootCopy, /*OpIdx*/4, // rs3 |
| 43811 | GIR_RootConstrainSelectedInstOperands, |
| 43812 | // GIR_Coverage, 65014, |
| 43813 | GIR_EraseRootFromParent_Done, |
| 43814 | // Label 3058: @113783 |
| 43815 | GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(113837), // Rule ID 64953 // |
| 43816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0), |
| 43817 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_insert), |
| 43818 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43819 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43820 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43821 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43823 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43824 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43825 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43826 | // (intrinsic_wo_chain:{ *:[i32] } 10204:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd) => (CV_INSERTR:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 43827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_INSERTR), |
| 43828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43829 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43830 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43831 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43832 | GIR_RootConstrainSelectedInstOperands, |
| 43833 | // GIR_Coverage, 64953, |
| 43834 | GIR_EraseRootFromParent_Done, |
| 43835 | // Label 3059: @113837 |
| 43836 | GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(113891), // Rule ID 64954 // |
| 43837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 43838 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_bitmanip_insert), |
| 43839 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43840 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43841 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43842 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43844 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43845 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43846 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43847 | // (intrinsic_wo_chain:{ *:[i32] } 10204:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd) => (CV_INSERTR:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 43848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_INSERTR), |
| 43849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43850 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43851 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43852 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43853 | GIR_RootConstrainSelectedInstOperands, |
| 43854 | // GIR_Coverage, 64954, |
| 43855 | GIR_EraseRootFromParent_Done, |
| 43856 | // Label 3060: @113891 |
| 43857 | GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(113945), // Rule ID 65022 // |
| 43858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode0), |
| 43859 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mac), |
| 43860 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43861 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43862 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43863 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43866 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43867 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43868 | // (intrinsic_wo_chain:{ *:[i32] } 10205:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd) => (CV_MAC:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 43869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MAC), |
| 43870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43871 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43873 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43874 | GIR_RootConstrainSelectedInstOperands, |
| 43875 | // GIR_Coverage, 65022, |
| 43876 | GIR_EraseRootFromParent_Done, |
| 43877 | // Label 3061: @113945 |
| 43878 | GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(113999), // Rule ID 65023 // |
| 43879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43880 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_mac), |
| 43881 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43882 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43883 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43884 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43886 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43887 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43888 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43889 | // (intrinsic_wo_chain:{ *:[i32] } 10205:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd) => (CV_MAC:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 43890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MAC), |
| 43891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43892 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43893 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43894 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43895 | GIR_RootConstrainSelectedInstOperands, |
| 43896 | // GIR_Coverage, 65023, |
| 43897 | GIR_EraseRootFromParent_Done, |
| 43898 | // Label 3062: @113999 |
| 43899 | GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(114053), // Rule ID 65024 // |
| 43900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode0), |
| 43901 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_msu), |
| 43902 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43903 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43904 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43905 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43907 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43908 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43909 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43910 | // (intrinsic_wo_chain:{ *:[i32] } 10214:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd) => (CV_MSU:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 43911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MSU), |
| 43912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43913 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43914 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43915 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43916 | GIR_RootConstrainSelectedInstOperands, |
| 43917 | // GIR_Coverage, 65024, |
| 43918 | GIR_EraseRootFromParent_Done, |
| 43919 | // Label 3063: @114053 |
| 43920 | GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(114107), // Rule ID 65025 // |
| 43921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43922 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_msu), |
| 43923 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43925 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43926 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43928 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43929 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43930 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43931 | // (intrinsic_wo_chain:{ *:[i32] } 10214:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd) => (CV_MSU:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 43932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MSU), |
| 43933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43934 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43935 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43936 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43937 | GIR_RootConstrainSelectedInstOperands, |
| 43938 | // GIR_Coverage, 65025, |
| 43939 | GIR_EraseRootFromParent_Done, |
| 43940 | // Label 3064: @114107 |
| 43941 | GIM_Reject, |
| 43942 | // Label 3021: @114108 |
| 43943 | GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(114629), |
| 43944 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 43945 | GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(114180), // Rule ID 65034 // |
| 43946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43947 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_macuN), |
| 43948 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43949 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43950 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43951 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43953 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43954 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43955 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43956 | // MIs[0] imm5 |
| 43957 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 43958 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43959 | // (intrinsic_wo_chain:{ *:[i32] } 10212:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACUN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACUN), |
| 43961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43962 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43963 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43964 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43965 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 43966 | GIR_RootConstrainSelectedInstOperands, |
| 43967 | // GIR_Coverage, 65034, |
| 43968 | GIR_EraseRootFromParent_Done, |
| 43969 | // Label 3066: @114180 |
| 43970 | GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(114244), // Rule ID 65035 // |
| 43971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43972 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_machhuN), |
| 43973 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43975 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 43976 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 43977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43978 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43979 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43980 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 43981 | // MIs[0] imm5 |
| 43982 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 43983 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 43984 | // (intrinsic_wo_chain:{ *:[i32] } 10208:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACHHUN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 43985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACHHUN), |
| 43986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 43987 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 43988 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 43989 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 43990 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 43991 | GIR_RootConstrainSelectedInstOperands, |
| 43992 | // GIR_Coverage, 65035, |
| 43993 | GIR_EraseRootFromParent_Done, |
| 43994 | // Label 3067: @114244 |
| 43995 | GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(114308), // Rule ID 65036 // |
| 43996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 43997 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_macsN), |
| 43998 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43999 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44000 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44001 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44003 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44004 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44005 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44006 | // MIs[0] imm5 |
| 44007 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44008 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 44009 | // (intrinsic_wo_chain:{ *:[i32] } 10210:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACSN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 44010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACSN), |
| 44011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 44012 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 44013 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 44014 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 44015 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 44016 | GIR_RootConstrainSelectedInstOperands, |
| 44017 | // GIR_Coverage, 65036, |
| 44018 | GIR_EraseRootFromParent_Done, |
| 44019 | // Label 3068: @114308 |
| 44020 | GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(114372), // Rule ID 65037 // |
| 44021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 44022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_machhsN), |
| 44023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44026 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44028 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44029 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44030 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44031 | // MIs[0] imm5 |
| 44032 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44033 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 44034 | // (intrinsic_wo_chain:{ *:[i32] } 10206:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACHHSN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 44035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACHHSN), |
| 44036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 44037 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 44038 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 44039 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 44040 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 44041 | GIR_RootConstrainSelectedInstOperands, |
| 44042 | // GIR_Coverage, 65037, |
| 44043 | GIR_EraseRootFromParent_Done, |
| 44044 | // Label 3069: @114372 |
| 44045 | GIM_Try, /*On fail goto*//*Label 3070*/ GIMT_Encode4(114436), // Rule ID 65038 // |
| 44046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 44047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_macuRN), |
| 44048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44050 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44051 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44053 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44054 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44055 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44056 | // MIs[0] imm5 |
| 44057 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44058 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 44059 | // (intrinsic_wo_chain:{ *:[i32] } 10213:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACURN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 44060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACURN), |
| 44061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 44062 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 44063 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 44064 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 44065 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 44066 | GIR_RootConstrainSelectedInstOperands, |
| 44067 | // GIR_Coverage, 65038, |
| 44068 | GIR_EraseRootFromParent_Done, |
| 44069 | // Label 3070: @114436 |
| 44070 | GIM_Try, /*On fail goto*//*Label 3071*/ GIMT_Encode4(114500), // Rule ID 65039 // |
| 44071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 44072 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_machhuRN), |
| 44073 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44074 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44075 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44076 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44078 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44079 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44080 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44081 | // MIs[0] imm5 |
| 44082 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44083 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 44084 | // (intrinsic_wo_chain:{ *:[i32] } 10209:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACHHURN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 44085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACHHURN), |
| 44086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 44087 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 44088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 44089 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 44090 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 44091 | GIR_RootConstrainSelectedInstOperands, |
| 44092 | // GIR_Coverage, 65039, |
| 44093 | GIR_EraseRootFromParent_Done, |
| 44094 | // Label 3071: @114500 |
| 44095 | GIM_Try, /*On fail goto*//*Label 3072*/ GIMT_Encode4(114564), // Rule ID 65040 // |
| 44096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 44097 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_macsRN), |
| 44098 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44099 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44100 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44101 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44104 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44105 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44106 | // MIs[0] imm5 |
| 44107 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44108 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 44109 | // (intrinsic_wo_chain:{ *:[i32] } 10211:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACSRN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 44110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACSRN), |
| 44111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 44112 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 44113 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 44114 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 44115 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 44116 | GIR_RootConstrainSelectedInstOperands, |
| 44117 | // GIR_Coverage, 65040, |
| 44118 | GIR_EraseRootFromParent_Done, |
| 44119 | // Label 3072: @114564 |
| 44120 | GIM_Try, /*On fail goto*//*Label 3073*/ GIMT_Encode4(114628), // Rule ID 65041 // |
| 44121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVmac_HwMode1), |
| 44122 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_cv_mac_machhsRN), |
| 44123 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44125 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44126 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44128 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44129 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44130 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44131 | // MIs[0] imm5 |
| 44132 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44133 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cv_tuimm5), |
| 44134 | // (intrinsic_wo_chain:{ *:[i32] } 10207:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rd, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) => (CV_MACHHSRN:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i32] })<<P:Predicate_cv_tuimm5>>:$imm5) |
| 44135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_MACHHSRN), |
| 44136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 44137 | GIR_RootToRootCopy, /*OpIdx*/4, // rd |
| 44138 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 44139 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 44140 | GIR_RootToRootCopy, /*OpIdx*/5, // imm5 |
| 44141 | GIR_RootConstrainSelectedInstOperands, |
| 44142 | // GIR_Coverage, 65041, |
| 44143 | GIR_EraseRootFromParent_Done, |
| 44144 | // Label 3073: @114628 |
| 44145 | GIM_Reject, |
| 44146 | // Label 3065: @114629 |
| 44147 | GIM_Reject, |
| 44148 | // Label 35: @114630 |
| 44149 | GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(115087), |
| 44150 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 44151 | GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(114710), // Rule ID 652 // |
| 44152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44153 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_xchg_i32), |
| 44154 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44155 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44156 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44158 | // MIs[0] addr |
| 44159 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44160 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44161 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44162 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44163 | // MIs[0] ordering |
| 44164 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44165 | // (intrinsic_w_chain:{ *:[i32] } 10237:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicSwap32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44166 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicSwap32), |
| 44168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44169 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44170 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44171 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44172 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44173 | GIR_RootToRootCopy, /*OpIdx*/5, // ordering |
| 44174 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44175 | GIR_RootConstrainSelectedInstOperands, |
| 44176 | // GIR_Coverage, 652, |
| 44177 | GIR_EraseRootFromParent_Done, |
| 44178 | // Label 3075: @114710 |
| 44179 | GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(114782), // Rule ID 653 // |
| 44180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44181 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_add_i32), |
| 44182 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44183 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44184 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44186 | // MIs[0] addr |
| 44187 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44188 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44189 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44190 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44191 | // MIs[0] ordering |
| 44192 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44193 | // (intrinsic_w_chain:{ *:[i32] } 10223:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadAdd32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44194 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadAdd32), |
| 44196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44197 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44198 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44199 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44200 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44201 | GIR_RootToRootCopy, /*OpIdx*/5, // ordering |
| 44202 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44203 | GIR_RootConstrainSelectedInstOperands, |
| 44204 | // GIR_Coverage, 653, |
| 44205 | GIR_EraseRootFromParent_Done, |
| 44206 | // Label 3076: @114782 |
| 44207 | GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(114854), // Rule ID 654 // |
| 44208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44209 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_sub_i32), |
| 44210 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44212 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44214 | // MIs[0] addr |
| 44215 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44216 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44217 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44218 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44219 | // MIs[0] ordering |
| 44220 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44221 | // (intrinsic_w_chain:{ *:[i32] } 10231:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadSub32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44222 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadSub32), |
| 44224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44225 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44226 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44227 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44228 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44229 | GIR_RootToRootCopy, /*OpIdx*/5, // ordering |
| 44230 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44231 | GIR_RootConstrainSelectedInstOperands, |
| 44232 | // GIR_Coverage, 654, |
| 44233 | GIR_EraseRootFromParent_Done, |
| 44234 | // Label 3077: @114854 |
| 44235 | GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(114926), // Rule ID 655 // |
| 44236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44237 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_nand_i32), |
| 44238 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44240 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44242 | // MIs[0] addr |
| 44243 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44244 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44245 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44246 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44247 | // MIs[0] ordering |
| 44248 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44249 | // (intrinsic_w_chain:{ *:[i32] } 10229:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44250 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadNand32), |
| 44252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44253 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44254 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44255 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44256 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44257 | GIR_RootToRootCopy, /*OpIdx*/5, // ordering |
| 44258 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44259 | GIR_RootConstrainSelectedInstOperands, |
| 44260 | // GIR_Coverage, 655, |
| 44261 | GIR_EraseRootFromParent_Done, |
| 44262 | // Label 3078: @114926 |
| 44263 | GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(115006), // Rule ID 658 // |
| 44264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44265 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_umax_i32), |
| 44266 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44267 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44268 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44269 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44270 | // MIs[0] addr |
| 44271 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44272 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44273 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44274 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44275 | // MIs[0] ordering |
| 44276 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44277 | // (intrinsic_w_chain:{ *:[i32] } 10233:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadUMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44278 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 44279 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadUMax32), |
| 44281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44282 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44283 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44284 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44285 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44286 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44287 | GIR_RootToRootCopy, /*OpIdx*/5, // ordering |
| 44288 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44289 | GIR_RootConstrainSelectedInstOperands, |
| 44290 | // GIR_Coverage, 658, |
| 44291 | GIR_EraseRootFromParent_Done, |
| 44292 | // Label 3079: @115006 |
| 44293 | GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(115086), // Rule ID 659 // |
| 44294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44295 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_umin_i32), |
| 44296 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44297 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44298 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44300 | // MIs[0] addr |
| 44301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44302 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44303 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44304 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44305 | // MIs[0] ordering |
| 44306 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 44307 | // (intrinsic_w_chain:{ *:[i32] } 10235:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadUMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44308 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 44309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadUMin32), |
| 44311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44312 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44313 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44314 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44315 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44316 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44317 | GIR_RootToRootCopy, /*OpIdx*/5, // ordering |
| 44318 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44319 | GIR_RootConstrainSelectedInstOperands, |
| 44320 | // GIR_Coverage, 659, |
| 44321 | GIR_EraseRootFromParent_Done, |
| 44322 | // Label 3080: @115086 |
| 44323 | GIM_Reject, |
| 44324 | // Label 3074: @115087 |
| 44325 | GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(115355), |
| 44326 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 44327 | GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(115184), // Rule ID 656 // |
| 44328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44329 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_max_i32), |
| 44330 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44331 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44332 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44333 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 44334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44335 | // MIs[0] addr |
| 44336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44338 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44339 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44340 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44341 | // MIs[0] ordering |
| 44342 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 44343 | // (intrinsic_w_chain:{ *:[i32] } 10225:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) |
| 44344 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 44345 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadMax32), |
| 44347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44348 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44349 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44350 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44351 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44352 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44353 | GIR_RootToRootCopy, /*OpIdx*/5, // shiftamt |
| 44354 | GIR_RootToRootCopy, /*OpIdx*/6, // ordering |
| 44355 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44356 | GIR_RootConstrainSelectedInstOperands, |
| 44357 | // GIR_Coverage, 656, |
| 44358 | GIR_EraseRootFromParent_Done, |
| 44359 | // Label 3082: @115184 |
| 44360 | GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(115273), // Rule ID 657 // |
| 44361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44362 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_atomicrmw_min_i32), |
| 44363 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44364 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44365 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44366 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 44367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44368 | // MIs[0] addr |
| 44369 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44370 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44371 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44372 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44373 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44374 | // MIs[0] ordering |
| 44375 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 44376 | // (intrinsic_w_chain:{ *:[i32] } 10227:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedAtomicLoadMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) |
| 44377 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 44378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedAtomicLoadMin32), |
| 44380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44381 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44382 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44383 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44384 | GIR_RootToRootCopy, /*OpIdx*/3, // incr |
| 44385 | GIR_RootToRootCopy, /*OpIdx*/4, // mask |
| 44386 | GIR_RootToRootCopy, /*OpIdx*/5, // shiftamt |
| 44387 | GIR_RootToRootCopy, /*OpIdx*/6, // ordering |
| 44388 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44389 | GIR_RootConstrainSelectedInstOperands, |
| 44390 | // GIR_Coverage, 657, |
| 44391 | GIR_EraseRootFromParent_Done, |
| 44392 | // Label 3083: @115273 |
| 44393 | GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(115354), // Rule ID 688 // |
| 44394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtA_HwMode1), |
| 44395 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::riscv_masked_cmpxchg_i32), |
| 44396 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 44397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44398 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 44399 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 44400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44401 | // MIs[0] addr |
| 44402 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 44403 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44404 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44405 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44406 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 44407 | // MIs[0] ordering |
| 44408 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 44409 | // (intrinsic_w_chain:{ *:[i32] } 10239:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) => (PseudoMaskedCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) |
| 44410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoMaskedCmpXchg32), |
| 44412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[res] |
| 44413 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 44414 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 44415 | GIR_RootToRootCopy, /*OpIdx*/3, // cmpval |
| 44416 | GIR_RootToRootCopy, /*OpIdx*/4, // newval |
| 44417 | GIR_RootToRootCopy, /*OpIdx*/5, // mask |
| 44418 | GIR_RootToRootCopy, /*OpIdx*/6, // ordering |
| 44419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44420 | GIR_RootConstrainSelectedInstOperands, |
| 44421 | // GIR_Coverage, 688, |
| 44422 | GIR_EraseRootFromParent_Done, |
| 44423 | // Label 3084: @115354 |
| 44424 | GIM_Reject, |
| 44425 | // Label 3081: @115355 |
| 44426 | GIM_Reject, |
| 44427 | // Label 36: @115356 |
| 44428 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(32), /*)*//*default:*//*Label 3100*/ GIMT_Encode4(118476), |
| 44429 | /*GILLT_nxv1s16*//*Label 3085*/ GIMT_Encode4(115467), |
| 44430 | /*GILLT_nxv1s32*//*Label 3086*/ GIMT_Encode4(115571), |
| 44431 | /*GILLT_nxv1s64*//*Label 3087*/ GIMT_Encode4(115788), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44432 | /*GILLT_nxv2s16*//*Label 3088*/ GIMT_Encode4(116113), |
| 44433 | /*GILLT_nxv2s32*//*Label 3089*/ GIMT_Encode4(116217), |
| 44434 | /*GILLT_nxv2s64*//*Label 3090*/ GIMT_Encode4(116434), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44435 | /*GILLT_nxv4s16*//*Label 3091*/ GIMT_Encode4(116759), |
| 44436 | /*GILLT_nxv4s32*//*Label 3092*/ GIMT_Encode4(116863), |
| 44437 | /*GILLT_nxv4s64*//*Label 3093*/ GIMT_Encode4(117080), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44438 | /*GILLT_nxv8s16*//*Label 3094*/ GIMT_Encode4(117405), |
| 44439 | /*GILLT_nxv8s32*//*Label 3095*/ GIMT_Encode4(117509), |
| 44440 | /*GILLT_nxv8s64*//*Label 3096*/ GIMT_Encode4(117726), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44441 | /*GILLT_nxv16s16*//*Label 3097*/ GIMT_Encode4(118051), |
| 44442 | /*GILLT_nxv16s32*//*Label 3098*/ GIMT_Encode4(118155), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44443 | /*GILLT_nxv32s16*//*Label 3099*/ GIMT_Encode4(118372), |
| 44444 | // Label 3085: @115467 |
| 44445 | GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(115570), |
| 44446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 44447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44449 | GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(115526), // Rule ID 48114 // |
| 44450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44451 | // (anyext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 44452 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 44453 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44454 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF4), |
| 44457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44458 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44459 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 44462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44463 | GIR_RootConstrainSelectedInstOperands, |
| 44464 | // GIR_Coverage, 48114, |
| 44465 | GIR_EraseRootFromParent_Done, |
| 44466 | // Label 3102: @115526 |
| 44467 | GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(115569), // Rule ID 48115 // |
| 44468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44469 | // (anyext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 44470 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 44471 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44472 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44473 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF4), |
| 44475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44476 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44477 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 44480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44481 | GIR_RootConstrainSelectedInstOperands, |
| 44482 | // GIR_Coverage, 48115, |
| 44483 | GIR_EraseRootFromParent_Done, |
| 44484 | // Label 3103: @115569 |
| 44485 | GIM_Reject, |
| 44486 | // Label 3101: @115570 |
| 44487 | GIM_Reject, |
| 44488 | // Label 3086: @115571 |
| 44489 | GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(115625), // Rule ID 48138 // |
| 44490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44491 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 44492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44494 | // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 44495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 44496 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44497 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44498 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 44500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44501 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44502 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44506 | GIR_RootConstrainSelectedInstOperands, |
| 44507 | // GIR_Coverage, 48138, |
| 44508 | GIR_EraseRootFromParent_Done, |
| 44509 | // Label 3104: @115625 |
| 44510 | GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(115679), // Rule ID 48139 // |
| 44511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44512 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 44513 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44514 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44515 | // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 44516 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 44517 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44518 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 44521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44522 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44523 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44527 | GIR_RootConstrainSelectedInstOperands, |
| 44528 | // GIR_Coverage, 48139, |
| 44529 | GIR_EraseRootFromParent_Done, |
| 44530 | // Label 3105: @115679 |
| 44531 | GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(115733), // Rule ID 48204 // |
| 44532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44533 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 44534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44535 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44536 | // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 44537 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 44538 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44539 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_MF2), |
| 44542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44543 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44544 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44548 | GIR_RootConstrainSelectedInstOperands, |
| 44549 | // GIR_Coverage, 48204, |
| 44550 | GIR_EraseRootFromParent_Done, |
| 44551 | // Label 3106: @115733 |
| 44552 | GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(115787), // Rule ID 48205 // |
| 44553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44554 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 44555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44556 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44557 | // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 44558 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 44559 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44560 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_MF2), |
| 44563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44564 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44565 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44569 | GIR_RootConstrainSelectedInstOperands, |
| 44570 | // GIR_Coverage, 48205, |
| 44571 | GIR_EraseRootFromParent_Done, |
| 44572 | // Label 3107: @115787 |
| 44573 | GIM_Reject, |
| 44574 | // Label 3087: @115788 |
| 44575 | GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(115842), // Rule ID 48158 // |
| 44576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 44577 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 44578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44579 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44580 | // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 44581 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 44582 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44583 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 44586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44587 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44588 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44592 | GIR_RootConstrainSelectedInstOperands, |
| 44593 | // GIR_Coverage, 48158, |
| 44594 | GIR_EraseRootFromParent_Done, |
| 44595 | // Label 3108: @115842 |
| 44596 | GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(115896), // Rule ID 48159 // |
| 44597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 44598 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 44599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44600 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44601 | // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 44602 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 44603 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44604 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 44607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44608 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44609 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44613 | GIR_RootConstrainSelectedInstOperands, |
| 44614 | // GIR_Coverage, 48159, |
| 44615 | GIR_EraseRootFromParent_Done, |
| 44616 | // Label 3109: @115896 |
| 44617 | GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(115950), // Rule ID 48224 // |
| 44618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 44619 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 44620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44621 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44622 | // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 44623 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 44624 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44625 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 44628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44629 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44630 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44634 | GIR_RootConstrainSelectedInstOperands, |
| 44635 | // GIR_Coverage, 48224, |
| 44636 | GIR_EraseRootFromParent_Done, |
| 44637 | // Label 3110: @115950 |
| 44638 | GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(116004), // Rule ID 48225 // |
| 44639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 44640 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 44641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44642 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44643 | // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 44644 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 44645 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44646 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44647 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 44649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44650 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44651 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44655 | GIR_RootConstrainSelectedInstOperands, |
| 44656 | // GIR_Coverage, 48225, |
| 44657 | GIR_EraseRootFromParent_Done, |
| 44658 | // Label 3111: @116004 |
| 44659 | GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(116058), // Rule ID 48258 // |
| 44660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 44661 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 44662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44664 | // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 44665 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 44666 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44667 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44668 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M1), |
| 44670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44671 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44672 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44676 | GIR_RootConstrainSelectedInstOperands, |
| 44677 | // GIR_Coverage, 48258, |
| 44678 | GIR_EraseRootFromParent_Done, |
| 44679 | // Label 3112: @116058 |
| 44680 | GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(116112), // Rule ID 48259 // |
| 44681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 44682 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 44683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44684 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44685 | // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 44686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 44687 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M1), |
| 44691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44692 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44693 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44697 | GIR_RootConstrainSelectedInstOperands, |
| 44698 | // GIR_Coverage, 48259, |
| 44699 | GIR_EraseRootFromParent_Done, |
| 44700 | // Label 3113: @116112 |
| 44701 | GIM_Reject, |
| 44702 | // Label 3088: @116113 |
| 44703 | GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(116216), |
| 44704 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 44705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44707 | GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(116172), // Rule ID 48118 // |
| 44708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44709 | // (anyext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 44710 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 44711 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 44715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44716 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44717 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 44720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44721 | GIR_RootConstrainSelectedInstOperands, |
| 44722 | // GIR_Coverage, 48118, |
| 44723 | GIR_EraseRootFromParent_Done, |
| 44724 | // Label 3115: @116172 |
| 44725 | GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(116215), // Rule ID 48119 // |
| 44726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44727 | // (anyext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 44728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 44729 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44730 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 44733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44734 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44735 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 44738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44739 | GIR_RootConstrainSelectedInstOperands, |
| 44740 | // GIR_Coverage, 48119, |
| 44741 | GIR_EraseRootFromParent_Done, |
| 44742 | // Label 3116: @116215 |
| 44743 | GIM_Reject, |
| 44744 | // Label 3114: @116216 |
| 44745 | GIM_Reject, |
| 44746 | // Label 3089: @116217 |
| 44747 | GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(116271), // Rule ID 48142 // |
| 44748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44749 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 44750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44752 | // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 44753 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 44754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44755 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 44758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44759 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44760 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44764 | GIR_RootConstrainSelectedInstOperands, |
| 44765 | // GIR_Coverage, 48142, |
| 44766 | GIR_EraseRootFromParent_Done, |
| 44767 | // Label 3117: @116271 |
| 44768 | GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(116325), // Rule ID 48143 // |
| 44769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44770 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 44771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44772 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44773 | // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 44774 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 44775 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44776 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 44779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44780 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44781 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44785 | GIR_RootConstrainSelectedInstOperands, |
| 44786 | // GIR_Coverage, 48143, |
| 44787 | GIR_EraseRootFromParent_Done, |
| 44788 | // Label 3118: @116325 |
| 44789 | GIM_Try, /*On fail goto*//*Label 3119*/ GIMT_Encode4(116379), // Rule ID 48208 // |
| 44790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44791 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 44792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44794 | // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 44795 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 44796 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44797 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 44800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44801 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44802 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44806 | GIR_RootConstrainSelectedInstOperands, |
| 44807 | // GIR_Coverage, 48208, |
| 44808 | GIR_EraseRootFromParent_Done, |
| 44809 | // Label 3119: @116379 |
| 44810 | GIM_Try, /*On fail goto*//*Label 3120*/ GIMT_Encode4(116433), // Rule ID 48209 // |
| 44811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 44813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44814 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44815 | // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 44816 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 44817 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44818 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44819 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 44821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44822 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44823 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 44826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44827 | GIR_RootConstrainSelectedInstOperands, |
| 44828 | // GIR_Coverage, 48209, |
| 44829 | GIR_EraseRootFromParent_Done, |
| 44830 | // Label 3120: @116433 |
| 44831 | GIM_Reject, |
| 44832 | // Label 3090: @116434 |
| 44833 | GIM_Try, /*On fail goto*//*Label 3121*/ GIMT_Encode4(116488), // Rule ID 48162 // |
| 44834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 44835 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 44836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 44837 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44838 | // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 44839 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 44840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 44844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44845 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44846 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44850 | GIR_RootConstrainSelectedInstOperands, |
| 44851 | // GIR_Coverage, 48162, |
| 44852 | GIR_EraseRootFromParent_Done, |
| 44853 | // Label 3121: @116488 |
| 44854 | GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(116542), // Rule ID 48163 // |
| 44855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 44856 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 44857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 44858 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44859 | // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 44860 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 44861 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44862 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 44865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44866 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44867 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44871 | GIR_RootConstrainSelectedInstOperands, |
| 44872 | // GIR_Coverage, 48163, |
| 44873 | GIR_EraseRootFromParent_Done, |
| 44874 | // Label 3122: @116542 |
| 44875 | GIM_Try, /*On fail goto*//*Label 3123*/ GIMT_Encode4(116596), // Rule ID 48228 // |
| 44876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 44877 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 44878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 44879 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44880 | // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 44881 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 44882 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44883 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 44886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44887 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44888 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44892 | GIR_RootConstrainSelectedInstOperands, |
| 44893 | // GIR_Coverage, 48228, |
| 44894 | GIR_EraseRootFromParent_Done, |
| 44895 | // Label 3123: @116596 |
| 44896 | GIM_Try, /*On fail goto*//*Label 3124*/ GIMT_Encode4(116650), // Rule ID 48229 // |
| 44897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 44898 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 44899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 44900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44901 | // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 44902 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 44903 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44904 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 44907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44909 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44913 | GIR_RootConstrainSelectedInstOperands, |
| 44914 | // GIR_Coverage, 48229, |
| 44915 | GIR_EraseRootFromParent_Done, |
| 44916 | // Label 3124: @116650 |
| 44917 | GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(116704), // Rule ID 48262 // |
| 44918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 44919 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 44920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 44921 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44922 | // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 44923 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 44924 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44925 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M2), |
| 44928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44929 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44930 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44934 | GIR_RootConstrainSelectedInstOperands, |
| 44935 | // GIR_Coverage, 48262, |
| 44936 | GIR_EraseRootFromParent_Done, |
| 44937 | // Label 3125: @116704 |
| 44938 | GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(116758), // Rule ID 48263 // |
| 44939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 44940 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 44941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 44942 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44943 | // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 44944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 44945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M2), |
| 44949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44950 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44951 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 44954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44955 | GIR_RootConstrainSelectedInstOperands, |
| 44956 | // GIR_Coverage, 48263, |
| 44957 | GIR_EraseRootFromParent_Done, |
| 44958 | // Label 3126: @116758 |
| 44959 | GIM_Reject, |
| 44960 | // Label 3091: @116759 |
| 44961 | GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(116862), |
| 44962 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 44963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44964 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 44965 | GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(116818), // Rule ID 48122 // |
| 44966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 44967 | // (anyext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 44968 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 44969 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44970 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 44973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44974 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44975 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 44978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44979 | GIR_RootConstrainSelectedInstOperands, |
| 44980 | // GIR_Coverage, 48122, |
| 44981 | GIR_EraseRootFromParent_Done, |
| 44982 | // Label 3128: @116818 |
| 44983 | GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(116861), // Rule ID 48123 // |
| 44984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 44985 | // (anyext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 44986 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 44987 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44988 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 44991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 44992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44993 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 44994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 44995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 44996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 44997 | GIR_RootConstrainSelectedInstOperands, |
| 44998 | // GIR_Coverage, 48123, |
| 44999 | GIR_EraseRootFromParent_Done, |
| 45000 | // Label 3129: @116861 |
| 45001 | GIM_Reject, |
| 45002 | // Label 3127: @116862 |
| 45003 | GIM_Reject, |
| 45004 | // Label 3092: @116863 |
| 45005 | GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(116917), // Rule ID 48146 // |
| 45006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 45008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45010 | // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45011 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 45012 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45013 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45014 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 45016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45017 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45018 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45022 | GIR_RootConstrainSelectedInstOperands, |
| 45023 | // GIR_Coverage, 48146, |
| 45024 | GIR_EraseRootFromParent_Done, |
| 45025 | // Label 3130: @116917 |
| 45026 | GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(116971), // Rule ID 48147 // |
| 45027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 45029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45031 | // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 45033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 45037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45038 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45039 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45043 | GIR_RootConstrainSelectedInstOperands, |
| 45044 | // GIR_Coverage, 48147, |
| 45045 | GIR_EraseRootFromParent_Done, |
| 45046 | // Label 3131: @116971 |
| 45047 | GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(117025), // Rule ID 48212 // |
| 45048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45049 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 45050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45051 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45052 | // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45053 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 45054 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45055 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 45058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45060 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45064 | GIR_RootConstrainSelectedInstOperands, |
| 45065 | // GIR_Coverage, 48212, |
| 45066 | GIR_EraseRootFromParent_Done, |
| 45067 | // Label 3132: @117025 |
| 45068 | GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(117079), // Rule ID 48213 // |
| 45069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45070 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 45071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45072 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45073 | // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45074 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 45075 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45076 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 45079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45080 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45081 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45085 | GIR_RootConstrainSelectedInstOperands, |
| 45086 | // GIR_Coverage, 48213, |
| 45087 | GIR_EraseRootFromParent_Done, |
| 45088 | // Label 3133: @117079 |
| 45089 | GIM_Reject, |
| 45090 | // Label 3093: @117080 |
| 45091 | GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(117134), // Rule ID 48166 // |
| 45092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45093 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 45094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45095 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45096 | // (anyext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45097 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 45098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45099 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 45102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45104 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45108 | GIR_RootConstrainSelectedInstOperands, |
| 45109 | // GIR_Coverage, 48166, |
| 45110 | GIR_EraseRootFromParent_Done, |
| 45111 | // Label 3134: @117134 |
| 45112 | GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(117188), // Rule ID 48167 // |
| 45113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45114 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 45115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45117 | // (anyext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45118 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 45119 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45120 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 45123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45124 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45125 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45129 | GIR_RootConstrainSelectedInstOperands, |
| 45130 | // GIR_Coverage, 48167, |
| 45131 | GIR_EraseRootFromParent_Done, |
| 45132 | // Label 3135: @117188 |
| 45133 | GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(117242), // Rule ID 48232 // |
| 45134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45135 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 45136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45138 | // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45139 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 45140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 45144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45145 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45146 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45150 | GIR_RootConstrainSelectedInstOperands, |
| 45151 | // GIR_Coverage, 48232, |
| 45152 | GIR_EraseRootFromParent_Done, |
| 45153 | // Label 3136: @117242 |
| 45154 | GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(117296), // Rule ID 48233 // |
| 45155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 45157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45159 | // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45160 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 45161 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45162 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 45165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45166 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45167 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45171 | GIR_RootConstrainSelectedInstOperands, |
| 45172 | // GIR_Coverage, 48233, |
| 45173 | GIR_EraseRootFromParent_Done, |
| 45174 | // Label 3137: @117296 |
| 45175 | GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(117350), // Rule ID 48266 // |
| 45176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45177 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 45178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45179 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45180 | // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45181 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 45182 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45183 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M4), |
| 45186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45187 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45188 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45192 | GIR_RootConstrainSelectedInstOperands, |
| 45193 | // GIR_Coverage, 48266, |
| 45194 | GIR_EraseRootFromParent_Done, |
| 45195 | // Label 3138: @117350 |
| 45196 | GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(117404), // Rule ID 48267 // |
| 45197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45198 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 45199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45201 | // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 45203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M4), |
| 45207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45208 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45209 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45213 | GIR_RootConstrainSelectedInstOperands, |
| 45214 | // GIR_Coverage, 48267, |
| 45215 | GIR_EraseRootFromParent_Done, |
| 45216 | // Label 3139: @117404 |
| 45217 | GIM_Reject, |
| 45218 | // Label 3094: @117405 |
| 45219 | GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(117508), |
| 45220 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 45221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45222 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45223 | GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(117464), // Rule ID 48126 // |
| 45224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45225 | // (anyext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 45226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 45227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 45231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45232 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45233 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45237 | GIR_RootConstrainSelectedInstOperands, |
| 45238 | // GIR_Coverage, 48126, |
| 45239 | GIR_EraseRootFromParent_Done, |
| 45240 | // Label 3141: @117464 |
| 45241 | GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(117507), // Rule ID 48127 // |
| 45242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45243 | // (anyext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 45244 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 45245 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45246 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 45249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45250 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45251 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45255 | GIR_RootConstrainSelectedInstOperands, |
| 45256 | // GIR_Coverage, 48127, |
| 45257 | GIR_EraseRootFromParent_Done, |
| 45258 | // Label 3142: @117507 |
| 45259 | GIM_Reject, |
| 45260 | // Label 3140: @117508 |
| 45261 | GIM_Reject, |
| 45262 | // Label 3095: @117509 |
| 45263 | GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(117563), // Rule ID 48150 // |
| 45264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45265 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 45266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45267 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45268 | // (anyext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 45270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 45274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45276 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45280 | GIR_RootConstrainSelectedInstOperands, |
| 45281 | // GIR_Coverage, 48150, |
| 45282 | GIR_EraseRootFromParent_Done, |
| 45283 | // Label 3143: @117563 |
| 45284 | GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(117617), // Rule ID 48151 // |
| 45285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45286 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 45287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45289 | // (anyext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45290 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 45291 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45292 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 45295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45296 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45297 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45301 | GIR_RootConstrainSelectedInstOperands, |
| 45302 | // GIR_Coverage, 48151, |
| 45303 | GIR_EraseRootFromParent_Done, |
| 45304 | // Label 3144: @117617 |
| 45305 | GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(117671), // Rule ID 48216 // |
| 45306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45307 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 45308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45309 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45310 | // (anyext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45311 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 45312 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45313 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 45316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45317 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45318 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45322 | GIR_RootConstrainSelectedInstOperands, |
| 45323 | // GIR_Coverage, 48216, |
| 45324 | GIR_EraseRootFromParent_Done, |
| 45325 | // Label 3145: @117671 |
| 45326 | GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(117725), // Rule ID 48217 // |
| 45327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45328 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 45329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45330 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45331 | // (anyext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 45333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 45337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45339 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45343 | GIR_RootConstrainSelectedInstOperands, |
| 45344 | // GIR_Coverage, 48217, |
| 45345 | GIR_EraseRootFromParent_Done, |
| 45346 | // Label 3146: @117725 |
| 45347 | GIM_Reject, |
| 45348 | // Label 3096: @117726 |
| 45349 | GIM_Try, /*On fail goto*//*Label 3147*/ GIMT_Encode4(117780), // Rule ID 48170 // |
| 45350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45351 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 45352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45353 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45354 | // (anyext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45355 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 45356 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45357 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 45360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45361 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45362 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45366 | GIR_RootConstrainSelectedInstOperands, |
| 45367 | // GIR_Coverage, 48170, |
| 45368 | GIR_EraseRootFromParent_Done, |
| 45369 | // Label 3147: @117780 |
| 45370 | GIM_Try, /*On fail goto*//*Label 3148*/ GIMT_Encode4(117834), // Rule ID 48171 // |
| 45371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45372 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 45373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45375 | // (anyext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45376 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 45377 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45378 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 45381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45382 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45383 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45387 | GIR_RootConstrainSelectedInstOperands, |
| 45388 | // GIR_Coverage, 48171, |
| 45389 | GIR_EraseRootFromParent_Done, |
| 45390 | // Label 3148: @117834 |
| 45391 | GIM_Try, /*On fail goto*//*Label 3149*/ GIMT_Encode4(117888), // Rule ID 48236 // |
| 45392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45393 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 45394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45395 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45396 | // (anyext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45397 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 45398 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45399 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 45402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45404 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45408 | GIR_RootConstrainSelectedInstOperands, |
| 45409 | // GIR_Coverage, 48236, |
| 45410 | GIR_EraseRootFromParent_Done, |
| 45411 | // Label 3149: @117888 |
| 45412 | GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(117942), // Rule ID 48237 // |
| 45413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45414 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 45415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45416 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45417 | // (anyext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45418 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 45419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 45423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45424 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45425 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45429 | GIR_RootConstrainSelectedInstOperands, |
| 45430 | // GIR_Coverage, 48237, |
| 45431 | GIR_EraseRootFromParent_Done, |
| 45432 | // Label 3150: @117942 |
| 45433 | GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(117996), // Rule ID 48270 // |
| 45434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45435 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 45436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45437 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45438 | // (anyext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45439 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 45440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45441 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M8), |
| 45444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45445 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45446 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45450 | GIR_RootConstrainSelectedInstOperands, |
| 45451 | // GIR_Coverage, 48270, |
| 45452 | GIR_EraseRootFromParent_Done, |
| 45453 | // Label 3151: @117996 |
| 45454 | GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(118050), // Rule ID 48271 // |
| 45455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45456 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 45457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45458 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45459 | // (anyext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45460 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 45461 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45462 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M8), |
| 45465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45466 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45467 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45471 | GIR_RootConstrainSelectedInstOperands, |
| 45472 | // GIR_Coverage, 48271, |
| 45473 | GIR_EraseRootFromParent_Done, |
| 45474 | // Label 3152: @118050 |
| 45475 | GIM_Reject, |
| 45476 | // Label 3097: @118051 |
| 45477 | GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(118154), |
| 45478 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 45479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45480 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45481 | GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(118110), // Rule ID 48130 // |
| 45482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45483 | // (anyext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 45484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 45485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 45489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45490 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45491 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45495 | GIR_RootConstrainSelectedInstOperands, |
| 45496 | // GIR_Coverage, 48130, |
| 45497 | GIR_EraseRootFromParent_Done, |
| 45498 | // Label 3154: @118110 |
| 45499 | GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(118153), // Rule ID 48131 // |
| 45500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45501 | // (anyext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 45502 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 45503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45504 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 45507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45508 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45509 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45513 | GIR_RootConstrainSelectedInstOperands, |
| 45514 | // GIR_Coverage, 48131, |
| 45515 | GIR_EraseRootFromParent_Done, |
| 45516 | // Label 3155: @118153 |
| 45517 | GIM_Reject, |
| 45518 | // Label 3153: @118154 |
| 45519 | GIM_Reject, |
| 45520 | // Label 3098: @118155 |
| 45521 | GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(118209), // Rule ID 48154 // |
| 45522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45523 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 45524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45525 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45526 | // (anyext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45527 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 45528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45529 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 45532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45534 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45538 | GIR_RootConstrainSelectedInstOperands, |
| 45539 | // GIR_Coverage, 48154, |
| 45540 | GIR_EraseRootFromParent_Done, |
| 45541 | // Label 3156: @118209 |
| 45542 | GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(118263), // Rule ID 48155 // |
| 45543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45544 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 45545 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45546 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45547 | // (anyext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45548 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 45549 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45550 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 45553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45555 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45559 | GIR_RootConstrainSelectedInstOperands, |
| 45560 | // GIR_Coverage, 48155, |
| 45561 | GIR_EraseRootFromParent_Done, |
| 45562 | // Label 3157: @118263 |
| 45563 | GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(118317), // Rule ID 48220 // |
| 45564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45565 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 45566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45567 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45568 | // (anyext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 45570 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45571 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 45574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45575 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45576 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45580 | GIR_RootConstrainSelectedInstOperands, |
| 45581 | // GIR_Coverage, 48220, |
| 45582 | GIR_EraseRootFromParent_Done, |
| 45583 | // Label 3158: @118317 |
| 45584 | GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(118371), // Rule ID 48221 // |
| 45585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45586 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 45587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 45589 | // (anyext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 45591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 45595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45597 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45601 | GIR_RootConstrainSelectedInstOperands, |
| 45602 | // GIR_Coverage, 48221, |
| 45603 | GIR_EraseRootFromParent_Done, |
| 45604 | // Label 3159: @118371 |
| 45605 | GIM_Reject, |
| 45606 | // Label 3099: @118372 |
| 45607 | GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(118475), |
| 45608 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 45609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 45610 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 45611 | GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(118431), // Rule ID 48134 // |
| 45612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45613 | // (anyext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 45614 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 45615 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45616 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 45619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45621 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45625 | GIR_RootConstrainSelectedInstOperands, |
| 45626 | // GIR_Coverage, 48134, |
| 45627 | GIR_EraseRootFromParent_Done, |
| 45628 | // Label 3161: @118431 |
| 45629 | GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(118474), // Rule ID 48135 // |
| 45630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45631 | // (anyext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 45632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 45633 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45634 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 45637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45638 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45639 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45643 | GIR_RootConstrainSelectedInstOperands, |
| 45644 | // GIR_Coverage, 48135, |
| 45645 | GIR_EraseRootFromParent_Done, |
| 45646 | // Label 3162: @118474 |
| 45647 | GIM_Reject, |
| 45648 | // Label 3160: @118475 |
| 45649 | GIM_Reject, |
| 45650 | // Label 3100: @118476 |
| 45651 | GIM_Reject, |
| 45652 | // Label 37: @118477 |
| 45653 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(32), /*)*//*default:*//*Label 3179*/ GIMT_Encode4(121641), |
| 45654 | /*GILLT_s64*//*Label 3163*/ GIMT_Encode4(118600), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45655 | /*GILLT_nxv1s16*//*Label 3164*/ GIMT_Encode4(118632), |
| 45656 | /*GILLT_nxv1s32*//*Label 3165*/ GIMT_Encode4(118736), |
| 45657 | /*GILLT_nxv1s64*//*Label 3166*/ GIMT_Encode4(118953), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45658 | /*GILLT_nxv2s16*//*Label 3167*/ GIMT_Encode4(119278), |
| 45659 | /*GILLT_nxv2s32*//*Label 3168*/ GIMT_Encode4(119382), |
| 45660 | /*GILLT_nxv2s64*//*Label 3169*/ GIMT_Encode4(119599), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45661 | /*GILLT_nxv4s16*//*Label 3170*/ GIMT_Encode4(119924), |
| 45662 | /*GILLT_nxv4s32*//*Label 3171*/ GIMT_Encode4(120028), |
| 45663 | /*GILLT_nxv4s64*//*Label 3172*/ GIMT_Encode4(120245), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45664 | /*GILLT_nxv8s16*//*Label 3173*/ GIMT_Encode4(120570), |
| 45665 | /*GILLT_nxv8s32*//*Label 3174*/ GIMT_Encode4(120674), |
| 45666 | /*GILLT_nxv8s64*//*Label 3175*/ GIMT_Encode4(120891), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45667 | /*GILLT_nxv16s16*//*Label 3176*/ GIMT_Encode4(121216), |
| 45668 | /*GILLT_nxv16s32*//*Label 3177*/ GIMT_Encode4(121320), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45669 | /*GILLT_nxv32s16*//*Label 3178*/ GIMT_Encode4(121537), |
| 45670 | // Label 3163: @118600 |
| 45671 | GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(118631), // Rule ID 295 // |
| 45672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 45673 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 45675 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 45676 | // (sext:{ *:[i64] } GPR:{ *:[i32] }:$src) => (ADDIW:{ *:[i64] } GPR:{ *:[i32] }:$src, 0:{ *:[i64] }) |
| 45677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDIW), |
| 45678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45679 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45681 | GIR_RootConstrainSelectedInstOperands, |
| 45682 | // GIR_Coverage, 295, |
| 45683 | GIR_EraseRootFromParent_Done, |
| 45684 | // Label 3180: @118631 |
| 45685 | GIM_Reject, |
| 45686 | // Label 3164: @118632 |
| 45687 | GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(118735), |
| 45688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 45689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45690 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45691 | GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(118691), // Rule ID 48172 // |
| 45692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45693 | // (sext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSEXT_VF2_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 45694 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 45695 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45696 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45697 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_MF4), |
| 45699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45700 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45701 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45705 | GIR_RootConstrainSelectedInstOperands, |
| 45706 | // GIR_Coverage, 48172, |
| 45707 | GIR_EraseRootFromParent_Done, |
| 45708 | // Label 3182: @118691 |
| 45709 | GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(118734), // Rule ID 48173 // |
| 45710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45711 | // (sext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSEXT_VF2_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 45712 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 45713 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45714 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_MF4), |
| 45717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45718 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45719 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45723 | GIR_RootConstrainSelectedInstOperands, |
| 45724 | // GIR_Coverage, 48173, |
| 45725 | GIR_EraseRootFromParent_Done, |
| 45726 | // Label 3183: @118734 |
| 45727 | GIM_Reject, |
| 45728 | // Label 3181: @118735 |
| 45729 | GIM_Reject, |
| 45730 | // Label 3165: @118736 |
| 45731 | GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(118790), // Rule ID 48184 // |
| 45732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45733 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 45734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45735 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45736 | // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSEXT_VF2_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45737 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 45738 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45739 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45740 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_MF2), |
| 45742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45743 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45744 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45748 | GIR_RootConstrainSelectedInstOperands, |
| 45749 | // GIR_Coverage, 48184, |
| 45750 | GIR_EraseRootFromParent_Done, |
| 45751 | // Label 3184: @118790 |
| 45752 | GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(118844), // Rule ID 48185 // |
| 45753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45754 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 45755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45757 | // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSEXT_VF2_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45758 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 45759 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45760 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_MF2), |
| 45763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45764 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45765 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45769 | GIR_RootConstrainSelectedInstOperands, |
| 45770 | // GIR_Coverage, 48185, |
| 45771 | GIR_EraseRootFromParent_Done, |
| 45772 | // Label 3185: @118844 |
| 45773 | GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(118898), // Rule ID 48238 // |
| 45774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45775 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 45776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45777 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45778 | // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSEXT_VF4_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45779 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 45780 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45781 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45782 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_MF2), |
| 45784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45785 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45786 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45790 | GIR_RootConstrainSelectedInstOperands, |
| 45791 | // GIR_Coverage, 48238, |
| 45792 | GIR_EraseRootFromParent_Done, |
| 45793 | // Label 3186: @118898 |
| 45794 | GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(118952), // Rule ID 48239 // |
| 45795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45796 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 45797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45799 | // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSEXT_VF4_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 45800 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 45801 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45802 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_MF2), |
| 45805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45806 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45807 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 45810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45811 | GIR_RootConstrainSelectedInstOperands, |
| 45812 | // GIR_Coverage, 48239, |
| 45813 | GIR_EraseRootFromParent_Done, |
| 45814 | // Label 3187: @118952 |
| 45815 | GIM_Reject, |
| 45816 | // Label 3166: @118953 |
| 45817 | GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(119007), // Rule ID 48194 // |
| 45818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45819 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 45820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45821 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45822 | // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSEXT_VF2_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 45824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45826 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M1), |
| 45828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45829 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45830 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45834 | GIR_RootConstrainSelectedInstOperands, |
| 45835 | // GIR_Coverage, 48194, |
| 45836 | GIR_EraseRootFromParent_Done, |
| 45837 | // Label 3188: @119007 |
| 45838 | GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(119061), // Rule ID 48195 // |
| 45839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45840 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 45841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45842 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45843 | // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSEXT_VF2_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45844 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 45845 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45846 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M1), |
| 45849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45850 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45851 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45855 | GIR_RootConstrainSelectedInstOperands, |
| 45856 | // GIR_Coverage, 48195, |
| 45857 | GIR_EraseRootFromParent_Done, |
| 45858 | // Label 3189: @119061 |
| 45859 | GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(119115), // Rule ID 48248 // |
| 45860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 45862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45863 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45864 | // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSEXT_VF4_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45865 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 45866 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45867 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45868 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M1), |
| 45870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45871 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45872 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45876 | GIR_RootConstrainSelectedInstOperands, |
| 45877 | // GIR_Coverage, 48248, |
| 45878 | GIR_EraseRootFromParent_Done, |
| 45879 | // Label 3190: @119115 |
| 45880 | GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(119169), // Rule ID 48249 // |
| 45881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45882 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 45883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45885 | // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSEXT_VF4_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45886 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 45887 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45888 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M1), |
| 45891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45892 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45893 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45897 | GIR_RootConstrainSelectedInstOperands, |
| 45898 | // GIR_Coverage, 48249, |
| 45899 | GIR_EraseRootFromParent_Done, |
| 45900 | // Label 3191: @119169 |
| 45901 | GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(119223), // Rule ID 48272 // |
| 45902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 45903 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 45904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45905 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45906 | // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSEXT_VF8_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 45907 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 45908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45909 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45910 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M1), |
| 45912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45913 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45918 | GIR_RootConstrainSelectedInstOperands, |
| 45919 | // GIR_Coverage, 48272, |
| 45920 | GIR_EraseRootFromParent_Done, |
| 45921 | // Label 3192: @119223 |
| 45922 | GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(119277), // Rule ID 48273 // |
| 45923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 45924 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 45925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45926 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45927 | // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSEXT_VF8_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 45928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 45929 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45930 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M1), |
| 45933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45934 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45935 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 45938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45939 | GIR_RootConstrainSelectedInstOperands, |
| 45940 | // GIR_Coverage, 48273, |
| 45941 | GIR_EraseRootFromParent_Done, |
| 45942 | // Label 3193: @119277 |
| 45943 | GIM_Reject, |
| 45944 | // Label 3167: @119278 |
| 45945 | GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(119381), |
| 45946 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 45947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45949 | GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(119337), // Rule ID 48174 // |
| 45950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45951 | // (sext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSEXT_VF2_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 45952 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 45953 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45954 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45955 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_MF2), |
| 45957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45958 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45959 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45963 | GIR_RootConstrainSelectedInstOperands, |
| 45964 | // GIR_Coverage, 48174, |
| 45965 | GIR_EraseRootFromParent_Done, |
| 45966 | // Label 3195: @119337 |
| 45967 | GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(119380), // Rule ID 48175 // |
| 45968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 45969 | // (sext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSEXT_VF2_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 45970 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 45971 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45972 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45973 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_MF2), |
| 45975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 45976 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45977 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 45978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 45979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 45980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 45981 | GIR_RootConstrainSelectedInstOperands, |
| 45982 | // GIR_Coverage, 48175, |
| 45983 | GIR_EraseRootFromParent_Done, |
| 45984 | // Label 3196: @119380 |
| 45985 | GIM_Reject, |
| 45986 | // Label 3194: @119381 |
| 45987 | GIM_Reject, |
| 45988 | // Label 3168: @119382 |
| 45989 | GIM_Try, /*On fail goto*//*Label 3197*/ GIMT_Encode4(119436), // Rule ID 48186 // |
| 45990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 45991 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 45992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45993 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 45994 | // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSEXT_VF2_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 45995 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 45996 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45997 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45998 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45999 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M1), |
| 46000 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46001 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46002 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46006 | GIR_RootConstrainSelectedInstOperands, |
| 46007 | // GIR_Coverage, 48186, |
| 46008 | GIR_EraseRootFromParent_Done, |
| 46009 | // Label 3197: @119436 |
| 46010 | GIM_Try, /*On fail goto*//*Label 3198*/ GIMT_Encode4(119490), // Rule ID 48187 // |
| 46011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46012 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 46013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46014 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46015 | // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSEXT_VF2_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46016 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 46017 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46018 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M1), |
| 46021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46022 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46023 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46027 | GIR_RootConstrainSelectedInstOperands, |
| 46028 | // GIR_Coverage, 48187, |
| 46029 | GIR_EraseRootFromParent_Done, |
| 46030 | // Label 3198: @119490 |
| 46031 | GIM_Try, /*On fail goto*//*Label 3199*/ GIMT_Encode4(119544), // Rule ID 48240 // |
| 46032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46033 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 46034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46036 | // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSEXT_VF4_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46037 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 46038 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46039 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M1), |
| 46042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46043 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46044 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46048 | GIR_RootConstrainSelectedInstOperands, |
| 46049 | // GIR_Coverage, 48240, |
| 46050 | GIR_EraseRootFromParent_Done, |
| 46051 | // Label 3199: @119544 |
| 46052 | GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(119598), // Rule ID 48241 // |
| 46053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46054 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 46055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46056 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46057 | // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSEXT_VF4_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46058 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 46059 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46060 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M1), |
| 46063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46064 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46065 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46069 | GIR_RootConstrainSelectedInstOperands, |
| 46070 | // GIR_Coverage, 48241, |
| 46071 | GIR_EraseRootFromParent_Done, |
| 46072 | // Label 3200: @119598 |
| 46073 | GIM_Reject, |
| 46074 | // Label 3169: @119599 |
| 46075 | GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(119653), // Rule ID 48196 // |
| 46076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46077 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 46078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46080 | // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSEXT_VF2_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 46082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M2), |
| 46086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46087 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46088 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46092 | GIR_RootConstrainSelectedInstOperands, |
| 46093 | // GIR_Coverage, 48196, |
| 46094 | GIR_EraseRootFromParent_Done, |
| 46095 | // Label 3201: @119653 |
| 46096 | GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(119707), // Rule ID 48197 // |
| 46097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46098 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 46099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46101 | // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSEXT_VF2_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46102 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 46103 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46104 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M2), |
| 46107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46108 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46109 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46113 | GIR_RootConstrainSelectedInstOperands, |
| 46114 | // GIR_Coverage, 48197, |
| 46115 | GIR_EraseRootFromParent_Done, |
| 46116 | // Label 3202: @119707 |
| 46117 | GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(119761), // Rule ID 48250 // |
| 46118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46119 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 46120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46122 | // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSEXT_VF4_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46123 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 46124 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46125 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M2), |
| 46128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46129 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46130 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46134 | GIR_RootConstrainSelectedInstOperands, |
| 46135 | // GIR_Coverage, 48250, |
| 46136 | GIR_EraseRootFromParent_Done, |
| 46137 | // Label 3203: @119761 |
| 46138 | GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(119815), // Rule ID 48251 // |
| 46139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 46141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46143 | // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSEXT_VF4_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 46145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46147 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M2), |
| 46149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46150 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46151 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46155 | GIR_RootConstrainSelectedInstOperands, |
| 46156 | // GIR_Coverage, 48251, |
| 46157 | GIR_EraseRootFromParent_Done, |
| 46158 | // Label 3204: @119815 |
| 46159 | GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(119869), // Rule ID 48274 // |
| 46160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46161 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 46162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46164 | // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSEXT_VF8_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 46166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M2), |
| 46170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46171 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46172 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46176 | GIR_RootConstrainSelectedInstOperands, |
| 46177 | // GIR_Coverage, 48274, |
| 46178 | GIR_EraseRootFromParent_Done, |
| 46179 | // Label 3205: @119869 |
| 46180 | GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(119923), // Rule ID 48275 // |
| 46181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 46183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46185 | // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSEXT_VF8_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46186 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 46187 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46188 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46189 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M2), |
| 46191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46192 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46193 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46197 | GIR_RootConstrainSelectedInstOperands, |
| 46198 | // GIR_Coverage, 48275, |
| 46199 | GIR_EraseRootFromParent_Done, |
| 46200 | // Label 3206: @119923 |
| 46201 | GIM_Reject, |
| 46202 | // Label 3170: @119924 |
| 46203 | GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(120027), |
| 46204 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 46205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46206 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46207 | GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(119983), // Rule ID 48176 // |
| 46208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46209 | // (sext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSEXT_VF2_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 46210 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 46211 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46212 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M1), |
| 46215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46216 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46217 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46221 | GIR_RootConstrainSelectedInstOperands, |
| 46222 | // GIR_Coverage, 48176, |
| 46223 | GIR_EraseRootFromParent_Done, |
| 46224 | // Label 3208: @119983 |
| 46225 | GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(120026), // Rule ID 48177 // |
| 46226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46227 | // (sext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSEXT_VF2_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 46228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 46229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46230 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M1), |
| 46233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46234 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46235 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46239 | GIR_RootConstrainSelectedInstOperands, |
| 46240 | // GIR_Coverage, 48177, |
| 46241 | GIR_EraseRootFromParent_Done, |
| 46242 | // Label 3209: @120026 |
| 46243 | GIM_Reject, |
| 46244 | // Label 3207: @120027 |
| 46245 | GIM_Reject, |
| 46246 | // Label 3171: @120028 |
| 46247 | GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(120082), // Rule ID 48188 // |
| 46248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46249 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 46250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46251 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46252 | // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSEXT_VF2_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46253 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 46254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46255 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M2), |
| 46258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46260 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46264 | GIR_RootConstrainSelectedInstOperands, |
| 46265 | // GIR_Coverage, 48188, |
| 46266 | GIR_EraseRootFromParent_Done, |
| 46267 | // Label 3210: @120082 |
| 46268 | GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(120136), // Rule ID 48189 // |
| 46269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46270 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 46271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46273 | // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSEXT_VF2_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46274 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 46275 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46276 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M2), |
| 46279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46280 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46281 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46285 | GIR_RootConstrainSelectedInstOperands, |
| 46286 | // GIR_Coverage, 48189, |
| 46287 | GIR_EraseRootFromParent_Done, |
| 46288 | // Label 3211: @120136 |
| 46289 | GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(120190), // Rule ID 48242 // |
| 46290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46291 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 46292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46293 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46294 | // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSEXT_VF4_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46295 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 46296 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46297 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M2), |
| 46300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46302 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46306 | GIR_RootConstrainSelectedInstOperands, |
| 46307 | // GIR_Coverage, 48242, |
| 46308 | GIR_EraseRootFromParent_Done, |
| 46309 | // Label 3212: @120190 |
| 46310 | GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(120244), // Rule ID 48243 // |
| 46311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46312 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 46313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46315 | // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSEXT_VF4_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46316 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 46317 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46318 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M2), |
| 46321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46322 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46323 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46327 | GIR_RootConstrainSelectedInstOperands, |
| 46328 | // GIR_Coverage, 48243, |
| 46329 | GIR_EraseRootFromParent_Done, |
| 46330 | // Label 3213: @120244 |
| 46331 | GIM_Reject, |
| 46332 | // Label 3172: @120245 |
| 46333 | GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(120299), // Rule ID 48198 // |
| 46334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46335 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 46336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46338 | // (sext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSEXT_VF2_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46339 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 46340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46341 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M4), |
| 46344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46345 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46346 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46350 | GIR_RootConstrainSelectedInstOperands, |
| 46351 | // GIR_Coverage, 48198, |
| 46352 | GIR_EraseRootFromParent_Done, |
| 46353 | // Label 3214: @120299 |
| 46354 | GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(120353), // Rule ID 48199 // |
| 46355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 46357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46358 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46359 | // (sext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSEXT_VF2_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46360 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 46361 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46362 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46363 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M4), |
| 46365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46366 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46367 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46371 | GIR_RootConstrainSelectedInstOperands, |
| 46372 | // GIR_Coverage, 48199, |
| 46373 | GIR_EraseRootFromParent_Done, |
| 46374 | // Label 3215: @120353 |
| 46375 | GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(120407), // Rule ID 48252 // |
| 46376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46377 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 46378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46379 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46380 | // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSEXT_VF4_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46381 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 46382 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M4), |
| 46386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46387 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46388 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46392 | GIR_RootConstrainSelectedInstOperands, |
| 46393 | // GIR_Coverage, 48252, |
| 46394 | GIR_EraseRootFromParent_Done, |
| 46395 | // Label 3216: @120407 |
| 46396 | GIM_Try, /*On fail goto*//*Label 3217*/ GIMT_Encode4(120461), // Rule ID 48253 // |
| 46397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46398 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 46399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46400 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46401 | // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSEXT_VF4_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46402 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 46403 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46404 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M4), |
| 46407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46408 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46409 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46413 | GIR_RootConstrainSelectedInstOperands, |
| 46414 | // GIR_Coverage, 48253, |
| 46415 | GIR_EraseRootFromParent_Done, |
| 46416 | // Label 3217: @120461 |
| 46417 | GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(120515), // Rule ID 48276 // |
| 46418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46419 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 46420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46422 | // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSEXT_VF8_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46423 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 46424 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46425 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M4), |
| 46428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46429 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46430 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46434 | GIR_RootConstrainSelectedInstOperands, |
| 46435 | // GIR_Coverage, 48276, |
| 46436 | GIR_EraseRootFromParent_Done, |
| 46437 | // Label 3218: @120515 |
| 46438 | GIM_Try, /*On fail goto*//*Label 3219*/ GIMT_Encode4(120569), // Rule ID 48277 // |
| 46439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46440 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 46441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46442 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46443 | // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSEXT_VF8_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46444 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 46445 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46446 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M4), |
| 46449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46450 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46451 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46455 | GIR_RootConstrainSelectedInstOperands, |
| 46456 | // GIR_Coverage, 48277, |
| 46457 | GIR_EraseRootFromParent_Done, |
| 46458 | // Label 3219: @120569 |
| 46459 | GIM_Reject, |
| 46460 | // Label 3173: @120570 |
| 46461 | GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(120673), |
| 46462 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 46463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46464 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46465 | GIM_Try, /*On fail goto*//*Label 3221*/ GIMT_Encode4(120629), // Rule ID 48178 // |
| 46466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46467 | // (sext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSEXT_VF2_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 46468 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 46469 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46470 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M2), |
| 46473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46474 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46475 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46479 | GIR_RootConstrainSelectedInstOperands, |
| 46480 | // GIR_Coverage, 48178, |
| 46481 | GIR_EraseRootFromParent_Done, |
| 46482 | // Label 3221: @120629 |
| 46483 | GIM_Try, /*On fail goto*//*Label 3222*/ GIMT_Encode4(120672), // Rule ID 48179 // |
| 46484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46485 | // (sext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSEXT_VF2_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 46486 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 46487 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46488 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M2), |
| 46491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46492 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46493 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46497 | GIR_RootConstrainSelectedInstOperands, |
| 46498 | // GIR_Coverage, 48179, |
| 46499 | GIR_EraseRootFromParent_Done, |
| 46500 | // Label 3222: @120672 |
| 46501 | GIM_Reject, |
| 46502 | // Label 3220: @120673 |
| 46503 | GIM_Reject, |
| 46504 | // Label 3174: @120674 |
| 46505 | GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(120728), // Rule ID 48190 // |
| 46506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46507 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 46508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46509 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46510 | // (sext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSEXT_VF2_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46511 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 46512 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46513 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M4), |
| 46516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46517 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46518 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46522 | GIR_RootConstrainSelectedInstOperands, |
| 46523 | // GIR_Coverage, 48190, |
| 46524 | GIR_EraseRootFromParent_Done, |
| 46525 | // Label 3223: @120728 |
| 46526 | GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(120782), // Rule ID 48191 // |
| 46527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46528 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 46529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46530 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46531 | // (sext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSEXT_VF2_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46532 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 46533 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46534 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M4), |
| 46537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46539 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46543 | GIR_RootConstrainSelectedInstOperands, |
| 46544 | // GIR_Coverage, 48191, |
| 46545 | GIR_EraseRootFromParent_Done, |
| 46546 | // Label 3224: @120782 |
| 46547 | GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(120836), // Rule ID 48244 // |
| 46548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 46550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46551 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46552 | // (sext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSEXT_VF4_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46553 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 46554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46555 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M4), |
| 46558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46559 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46564 | GIR_RootConstrainSelectedInstOperands, |
| 46565 | // GIR_Coverage, 48244, |
| 46566 | GIR_EraseRootFromParent_Done, |
| 46567 | // Label 3225: @120836 |
| 46568 | GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(120890), // Rule ID 48245 // |
| 46569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46570 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 46571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46572 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46573 | // (sext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSEXT_VF4_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46574 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 46575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M4), |
| 46579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46580 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46581 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46585 | GIR_RootConstrainSelectedInstOperands, |
| 46586 | // GIR_Coverage, 48245, |
| 46587 | GIR_EraseRootFromParent_Done, |
| 46588 | // Label 3226: @120890 |
| 46589 | GIM_Reject, |
| 46590 | // Label 3175: @120891 |
| 46591 | GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(120945), // Rule ID 48200 // |
| 46592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46593 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 46594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46596 | // (sext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSEXT_VF2_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 46598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46600 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M8), |
| 46602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46604 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46608 | GIR_RootConstrainSelectedInstOperands, |
| 46609 | // GIR_Coverage, 48200, |
| 46610 | GIR_EraseRootFromParent_Done, |
| 46611 | // Label 3227: @120945 |
| 46612 | GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(120999), // Rule ID 48201 // |
| 46613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46614 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 46615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46616 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46617 | // (sext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSEXT_VF2_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46618 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 46619 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46620 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M8), |
| 46623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46624 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46625 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46629 | GIR_RootConstrainSelectedInstOperands, |
| 46630 | // GIR_Coverage, 48201, |
| 46631 | GIR_EraseRootFromParent_Done, |
| 46632 | // Label 3228: @120999 |
| 46633 | GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(121053), // Rule ID 48254 // |
| 46634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46635 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 46636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46637 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46638 | // (sext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSEXT_VF4_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46639 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 46640 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46641 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M8), |
| 46644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46646 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46650 | GIR_RootConstrainSelectedInstOperands, |
| 46651 | // GIR_Coverage, 48254, |
| 46652 | GIR_EraseRootFromParent_Done, |
| 46653 | // Label 3229: @121053 |
| 46654 | GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(121107), // Rule ID 48255 // |
| 46655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46656 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 46657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46658 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46659 | // (sext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSEXT_VF4_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46660 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 46661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M8), |
| 46665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46666 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46667 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46671 | GIR_RootConstrainSelectedInstOperands, |
| 46672 | // GIR_Coverage, 48255, |
| 46673 | GIR_EraseRootFromParent_Done, |
| 46674 | // Label 3230: @121107 |
| 46675 | GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(121161), // Rule ID 48278 // |
| 46676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 46677 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 46678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46679 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46680 | // (sext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSEXT_VF8_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 46681 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 46682 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46683 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M8), |
| 46686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46687 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46688 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46692 | GIR_RootConstrainSelectedInstOperands, |
| 46693 | // GIR_Coverage, 48278, |
| 46694 | GIR_EraseRootFromParent_Done, |
| 46695 | // Label 3231: @121161 |
| 46696 | GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(121215), // Rule ID 48279 // |
| 46697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 46698 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 46699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46700 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46701 | // (sext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSEXT_VF8_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 46702 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 46703 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46704 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46705 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF8_M8), |
| 46707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46708 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46709 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 46712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46713 | GIR_RootConstrainSelectedInstOperands, |
| 46714 | // GIR_Coverage, 48279, |
| 46715 | GIR_EraseRootFromParent_Done, |
| 46716 | // Label 3232: @121215 |
| 46717 | GIM_Reject, |
| 46718 | // Label 3176: @121216 |
| 46719 | GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(121319), |
| 46720 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 46721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46722 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46723 | GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(121275), // Rule ID 48180 // |
| 46724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46725 | // (sext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSEXT_VF2_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 46726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 46727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M4), |
| 46731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46732 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46733 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46737 | GIR_RootConstrainSelectedInstOperands, |
| 46738 | // GIR_Coverage, 48180, |
| 46739 | GIR_EraseRootFromParent_Done, |
| 46740 | // Label 3234: @121275 |
| 46741 | GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(121318), // Rule ID 48181 // |
| 46742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46743 | // (sext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSEXT_VF2_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 46744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 46745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46747 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M4), |
| 46749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46750 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46755 | GIR_RootConstrainSelectedInstOperands, |
| 46756 | // GIR_Coverage, 48181, |
| 46757 | GIR_EraseRootFromParent_Done, |
| 46758 | // Label 3235: @121318 |
| 46759 | GIM_Reject, |
| 46760 | // Label 3233: @121319 |
| 46761 | GIM_Reject, |
| 46762 | // Label 3177: @121320 |
| 46763 | GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(121374), // Rule ID 48192 // |
| 46764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46765 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 46766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46767 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46768 | // (sext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSEXT_VF2_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46769 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 46770 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46771 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46772 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M8), |
| 46774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46775 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46776 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46780 | GIR_RootConstrainSelectedInstOperands, |
| 46781 | // GIR_Coverage, 48192, |
| 46782 | GIR_EraseRootFromParent_Done, |
| 46783 | // Label 3236: @121374 |
| 46784 | GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(121428), // Rule ID 48193 // |
| 46785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46786 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 46787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46788 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46789 | // (sext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSEXT_VF2_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46790 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 46791 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46792 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M8), |
| 46795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46796 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46797 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46801 | GIR_RootConstrainSelectedInstOperands, |
| 46802 | // GIR_Coverage, 48193, |
| 46803 | GIR_EraseRootFromParent_Done, |
| 46804 | // Label 3237: @121428 |
| 46805 | GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(121482), // Rule ID 48246 // |
| 46806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46807 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 46808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46809 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46810 | // (sext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSEXT_VF4_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46811 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 46812 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46813 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46814 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M8), |
| 46816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46817 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46818 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46822 | GIR_RootConstrainSelectedInstOperands, |
| 46823 | // GIR_Coverage, 48246, |
| 46824 | GIR_EraseRootFromParent_Done, |
| 46825 | // Label 3238: @121482 |
| 46826 | GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(121536), // Rule ID 48247 // |
| 46827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 46829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46830 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 46831 | // (sext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSEXT_VF4_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 46832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 46833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46834 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46835 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF4_M8), |
| 46837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46838 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46839 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 46842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46843 | GIR_RootConstrainSelectedInstOperands, |
| 46844 | // GIR_Coverage, 48247, |
| 46845 | GIR_EraseRootFromParent_Done, |
| 46846 | // Label 3239: @121536 |
| 46847 | GIM_Reject, |
| 46848 | // Label 3178: @121537 |
| 46849 | GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(121640), |
| 46850 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 46851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 46852 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 46853 | GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(121596), // Rule ID 48182 // |
| 46854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46855 | // (sext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSEXT_VF2_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 46856 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 46857 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46858 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46859 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M8), |
| 46861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46862 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46863 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46867 | GIR_RootConstrainSelectedInstOperands, |
| 46868 | // GIR_Coverage, 48182, |
| 46869 | GIR_EraseRootFromParent_Done, |
| 46870 | // Label 3241: @121596 |
| 46871 | GIM_Try, /*On fail goto*//*Label 3242*/ GIMT_Encode4(121639), // Rule ID 48183 // |
| 46872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46873 | // (sext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSEXT_VF2_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 46874 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 46875 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46876 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSEXT_VF2_M8), |
| 46879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46881 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46885 | GIR_RootConstrainSelectedInstOperands, |
| 46886 | // GIR_Coverage, 48183, |
| 46887 | GIR_EraseRootFromParent_Done, |
| 46888 | // Label 3242: @121639 |
| 46889 | GIM_Reject, |
| 46890 | // Label 3240: @121640 |
| 46891 | GIM_Reject, |
| 46892 | // Label 3179: @121641 |
| 46893 | GIM_Reject, |
| 46894 | // Label 38: @121642 |
| 46895 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(32), /*)*//*default:*//*Label 3259*/ GIMT_Encode4(124857), |
| 46896 | /*GILLT_s64*//*Label 3243*/ GIMT_Encode4(121765), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46897 | /*GILLT_nxv1s16*//*Label 3244*/ GIMT_Encode4(121848), |
| 46898 | /*GILLT_nxv1s32*//*Label 3245*/ GIMT_Encode4(121952), |
| 46899 | /*GILLT_nxv1s64*//*Label 3246*/ GIMT_Encode4(122169), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46900 | /*GILLT_nxv2s16*//*Label 3247*/ GIMT_Encode4(122494), |
| 46901 | /*GILLT_nxv2s32*//*Label 3248*/ GIMT_Encode4(122598), |
| 46902 | /*GILLT_nxv2s64*//*Label 3249*/ GIMT_Encode4(122815), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46903 | /*GILLT_nxv4s16*//*Label 3250*/ GIMT_Encode4(123140), |
| 46904 | /*GILLT_nxv4s32*//*Label 3251*/ GIMT_Encode4(123244), |
| 46905 | /*GILLT_nxv4s64*//*Label 3252*/ GIMT_Encode4(123461), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46906 | /*GILLT_nxv8s16*//*Label 3253*/ GIMT_Encode4(123786), |
| 46907 | /*GILLT_nxv8s32*//*Label 3254*/ GIMT_Encode4(123890), |
| 46908 | /*GILLT_nxv8s64*//*Label 3255*/ GIMT_Encode4(124107), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46909 | /*GILLT_nxv16s16*//*Label 3256*/ GIMT_Encode4(124432), |
| 46910 | /*GILLT_nxv16s32*//*Label 3257*/ GIMT_Encode4(124536), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46911 | /*GILLT_nxv32s16*//*Label 3258*/ GIMT_Encode4(124753), |
| 46912 | // Label 3243: @121765 |
| 46913 | GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(121847), |
| 46914 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 46916 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 46917 | GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(121823), // Rule ID 322 // |
| 46918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_NotHasStdExtZba_HwMode0), |
| 46919 | // (zext:{ *:[i64] } GPR:{ *:[i32] }:$src) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i32] }:$src, 32:{ *:[i64] }), 32:{ *:[i64] }) |
| 46920 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 46921 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 46922 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46923 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 46924 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 46925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 46927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46928 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/32, |
| 46930 | GIR_RootConstrainSelectedInstOperands, |
| 46931 | // GIR_Coverage, 322, |
| 46932 | GIR_EraseRootFromParent_Done, |
| 46933 | // Label 3261: @121823 |
| 46934 | GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(121846), // Rule ID 2829 // |
| 46935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 46936 | // (zext:{ *:[i64] } GPR:{ *:[i32] }:$src) => (ADD_UW:{ *:[i64] } GPR:{ *:[i32] }:$src, X0:{ *:[i64] }) |
| 46937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), |
| 46938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46939 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46940 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46941 | GIR_RootConstrainSelectedInstOperands, |
| 46942 | // GIR_Coverage, 2829, |
| 46943 | GIR_EraseRootFromParent_Done, |
| 46944 | // Label 3262: @121846 |
| 46945 | GIM_Reject, |
| 46946 | // Label 3260: @121847 |
| 46947 | GIM_Reject, |
| 46948 | // Label 3244: @121848 |
| 46949 | GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(121951), |
| 46950 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 46951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46952 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46953 | GIM_Try, /*On fail goto*//*Label 3264*/ GIMT_Encode4(121907), // Rule ID 46632 // |
| 46954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46955 | // (zext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 46956 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 46957 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46958 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46959 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF4), |
| 46961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46962 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46963 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46967 | GIR_RootConstrainSelectedInstOperands, |
| 46968 | // GIR_Coverage, 46632, |
| 46969 | GIR_EraseRootFromParent_Done, |
| 46970 | // Label 3264: @121907 |
| 46971 | GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(121950), // Rule ID 46633 // |
| 46972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 46973 | // (zext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 46974 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 46975 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46976 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46977 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF4), |
| 46979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 46980 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46981 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 46982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 46983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 46984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 46985 | GIR_RootConstrainSelectedInstOperands, |
| 46986 | // GIR_Coverage, 46633, |
| 46987 | GIR_EraseRootFromParent_Done, |
| 46988 | // Label 3265: @121950 |
| 46989 | GIM_Reject, |
| 46990 | // Label 3263: @121951 |
| 46991 | GIM_Reject, |
| 46992 | // Label 3245: @121952 |
| 46993 | GIM_Try, /*On fail goto*//*Label 3266*/ GIMT_Encode4(122006), // Rule ID 48136 // |
| 46994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 46995 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 46996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46997 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 46998 | // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 46999 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 47000 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 47004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47006 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47010 | GIR_RootConstrainSelectedInstOperands, |
| 47011 | // GIR_Coverage, 48136, |
| 47012 | GIR_EraseRootFromParent_Done, |
| 47013 | // Label 3266: @122006 |
| 47014 | GIM_Try, /*On fail goto*//*Label 3267*/ GIMT_Encode4(122060), // Rule ID 48137 // |
| 47015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47016 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 47017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47019 | // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47020 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 47021 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47022 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47023 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 47025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47026 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47027 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47031 | GIR_RootConstrainSelectedInstOperands, |
| 47032 | // GIR_Coverage, 48137, |
| 47033 | GIR_EraseRootFromParent_Done, |
| 47034 | // Label 3267: @122060 |
| 47035 | GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(122114), // Rule ID 48202 // |
| 47036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47037 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 47038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47040 | // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47041 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 47042 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47043 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47044 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_MF2), |
| 47046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47048 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47052 | GIR_RootConstrainSelectedInstOperands, |
| 47053 | // GIR_Coverage, 48202, |
| 47054 | GIR_EraseRootFromParent_Done, |
| 47055 | // Label 3268: @122114 |
| 47056 | GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(122168), // Rule ID 48203 // |
| 47057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47058 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 47059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47060 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47061 | // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47062 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 47063 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47064 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_MF2), |
| 47067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47068 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47069 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47073 | GIR_RootConstrainSelectedInstOperands, |
| 47074 | // GIR_Coverage, 48203, |
| 47075 | GIR_EraseRootFromParent_Done, |
| 47076 | // Label 3269: @122168 |
| 47077 | GIM_Reject, |
| 47078 | // Label 3246: @122169 |
| 47079 | GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(122223), // Rule ID 48156 // |
| 47080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 47082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47084 | // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47085 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 47086 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47087 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 47090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47091 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47092 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47096 | GIR_RootConstrainSelectedInstOperands, |
| 47097 | // GIR_Coverage, 48156, |
| 47098 | GIR_EraseRootFromParent_Done, |
| 47099 | // Label 3270: @122223 |
| 47100 | GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(122277), // Rule ID 48157 // |
| 47101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47102 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 47103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47105 | // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47106 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 47107 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47108 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 47111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47112 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47113 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47117 | GIR_RootConstrainSelectedInstOperands, |
| 47118 | // GIR_Coverage, 48157, |
| 47119 | GIR_EraseRootFromParent_Done, |
| 47120 | // Label 3271: @122277 |
| 47121 | GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(122331), // Rule ID 48222 // |
| 47122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47123 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 47124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47125 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47126 | // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47127 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 47128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 47132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47133 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47134 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47138 | GIR_RootConstrainSelectedInstOperands, |
| 47139 | // GIR_Coverage, 48222, |
| 47140 | GIR_EraseRootFromParent_Done, |
| 47141 | // Label 3272: @122331 |
| 47142 | GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(122385), // Rule ID 48223 // |
| 47143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47144 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 47145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47146 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47147 | // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47148 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 47149 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47150 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 47153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47154 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47159 | GIR_RootConstrainSelectedInstOperands, |
| 47160 | // GIR_Coverage, 48223, |
| 47161 | GIR_EraseRootFromParent_Done, |
| 47162 | // Label 3273: @122385 |
| 47163 | GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(122439), // Rule ID 48256 // |
| 47164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 47166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47168 | // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47169 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 47170 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47171 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M1), |
| 47174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47175 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47176 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47180 | GIR_RootConstrainSelectedInstOperands, |
| 47181 | // GIR_Coverage, 48256, |
| 47182 | GIR_EraseRootFromParent_Done, |
| 47183 | // Label 3274: @122439 |
| 47184 | GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(122493), // Rule ID 48257 // |
| 47185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47186 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 47187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47189 | // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2) => (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47190 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 47191 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47192 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M1), |
| 47195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47196 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47197 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47201 | GIR_RootConstrainSelectedInstOperands, |
| 47202 | // GIR_Coverage, 48257, |
| 47203 | GIR_EraseRootFromParent_Done, |
| 47204 | // Label 3275: @122493 |
| 47205 | GIM_Reject, |
| 47206 | // Label 3247: @122494 |
| 47207 | GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(122597), |
| 47208 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 47209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47210 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47211 | GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(122553), // Rule ID 48116 // |
| 47212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47213 | // (zext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 47214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 47215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 47219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47220 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47221 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47225 | GIR_RootConstrainSelectedInstOperands, |
| 47226 | // GIR_Coverage, 48116, |
| 47227 | GIR_EraseRootFromParent_Done, |
| 47228 | // Label 3277: @122553 |
| 47229 | GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(122596), // Rule ID 48117 // |
| 47230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47231 | // (zext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 47232 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 47233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_MF2), |
| 47237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47239 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47243 | GIR_RootConstrainSelectedInstOperands, |
| 47244 | // GIR_Coverage, 48117, |
| 47245 | GIR_EraseRootFromParent_Done, |
| 47246 | // Label 3278: @122596 |
| 47247 | GIM_Reject, |
| 47248 | // Label 3276: @122597 |
| 47249 | GIM_Reject, |
| 47250 | // Label 3248: @122598 |
| 47251 | GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(122652), // Rule ID 48140 // |
| 47252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47253 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 47254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47255 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47256 | // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47257 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 47258 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47259 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 47262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47263 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47264 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47268 | GIR_RootConstrainSelectedInstOperands, |
| 47269 | // GIR_Coverage, 48140, |
| 47270 | GIR_EraseRootFromParent_Done, |
| 47271 | // Label 3279: @122652 |
| 47272 | GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(122706), // Rule ID 48141 // |
| 47273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47274 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 47275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47277 | // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 47279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 47283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47289 | GIR_RootConstrainSelectedInstOperands, |
| 47290 | // GIR_Coverage, 48141, |
| 47291 | GIR_EraseRootFromParent_Done, |
| 47292 | // Label 3280: @122706 |
| 47293 | GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(122760), // Rule ID 48206 // |
| 47294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47295 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 47296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47297 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47298 | // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47299 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 47300 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47301 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 47304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47305 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47306 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47310 | GIR_RootConstrainSelectedInstOperands, |
| 47311 | // GIR_Coverage, 48206, |
| 47312 | GIR_EraseRootFromParent_Done, |
| 47313 | // Label 3281: @122760 |
| 47314 | GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(122814), // Rule ID 48207 // |
| 47315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47316 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 47317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47318 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47319 | // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 47321 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47322 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M1), |
| 47325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47326 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47327 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47331 | GIR_RootConstrainSelectedInstOperands, |
| 47332 | // GIR_Coverage, 48207, |
| 47333 | GIR_EraseRootFromParent_Done, |
| 47334 | // Label 3282: @122814 |
| 47335 | GIM_Reject, |
| 47336 | // Label 3249: @122815 |
| 47337 | GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(122869), // Rule ID 48160 // |
| 47338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47339 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 47340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47341 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47342 | // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47343 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 47344 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47345 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47346 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 47348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47350 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47354 | GIR_RootConstrainSelectedInstOperands, |
| 47355 | // GIR_Coverage, 48160, |
| 47356 | GIR_EraseRootFromParent_Done, |
| 47357 | // Label 3283: @122869 |
| 47358 | GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(122923), // Rule ID 48161 // |
| 47359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47360 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 47361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47362 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47363 | // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 47365 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47366 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 47369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47371 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47375 | GIR_RootConstrainSelectedInstOperands, |
| 47376 | // GIR_Coverage, 48161, |
| 47377 | GIR_EraseRootFromParent_Done, |
| 47378 | // Label 3284: @122923 |
| 47379 | GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(122977), // Rule ID 48226 // |
| 47380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47381 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 47382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47383 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47384 | // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47385 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 47386 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 47390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47391 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47392 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47396 | GIR_RootConstrainSelectedInstOperands, |
| 47397 | // GIR_Coverage, 48226, |
| 47398 | GIR_EraseRootFromParent_Done, |
| 47399 | // Label 3285: @122977 |
| 47400 | GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(123031), // Rule ID 48227 // |
| 47401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47402 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 47403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47404 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47405 | // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 47407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47408 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 47411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47413 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47417 | GIR_RootConstrainSelectedInstOperands, |
| 47418 | // GIR_Coverage, 48227, |
| 47419 | GIR_EraseRootFromParent_Done, |
| 47420 | // Label 3286: @123031 |
| 47421 | GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(123085), // Rule ID 48260 // |
| 47422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47423 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 47424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47425 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47426 | // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47427 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 47428 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47429 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47430 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M2), |
| 47432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47433 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47434 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47438 | GIR_RootConstrainSelectedInstOperands, |
| 47439 | // GIR_Coverage, 48260, |
| 47440 | GIR_EraseRootFromParent_Done, |
| 47441 | // Label 3287: @123085 |
| 47442 | GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(123139), // Rule ID 48261 // |
| 47443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47444 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 47445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47446 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47447 | // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2) => (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47448 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 47449 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47450 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M2), |
| 47453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47454 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47455 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47459 | GIR_RootConstrainSelectedInstOperands, |
| 47460 | // GIR_Coverage, 48261, |
| 47461 | GIR_EraseRootFromParent_Done, |
| 47462 | // Label 3288: @123139 |
| 47463 | GIM_Reject, |
| 47464 | // Label 3250: @123140 |
| 47465 | GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(123243), |
| 47466 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 47467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47468 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47469 | GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(123199), // Rule ID 48120 // |
| 47470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47471 | // (zext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 47472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 47473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 47477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47479 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47483 | GIR_RootConstrainSelectedInstOperands, |
| 47484 | // GIR_Coverage, 48120, |
| 47485 | GIR_EraseRootFromParent_Done, |
| 47486 | // Label 3290: @123199 |
| 47487 | GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(123242), // Rule ID 48121 // |
| 47488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47489 | // (zext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 47490 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 47491 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47492 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47493 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M1), |
| 47495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47496 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47497 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47501 | GIR_RootConstrainSelectedInstOperands, |
| 47502 | // GIR_Coverage, 48121, |
| 47503 | GIR_EraseRootFromParent_Done, |
| 47504 | // Label 3291: @123242 |
| 47505 | GIM_Reject, |
| 47506 | // Label 3289: @123243 |
| 47507 | GIM_Reject, |
| 47508 | // Label 3251: @123244 |
| 47509 | GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(123298), // Rule ID 48144 // |
| 47510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47511 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 47512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47513 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47514 | // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 47516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 47520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47521 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47522 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47526 | GIR_RootConstrainSelectedInstOperands, |
| 47527 | // GIR_Coverage, 48144, |
| 47528 | GIR_EraseRootFromParent_Done, |
| 47529 | // Label 3292: @123298 |
| 47530 | GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(123352), // Rule ID 48145 // |
| 47531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47532 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 47533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47534 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47535 | // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47536 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 47537 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47538 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47539 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 47541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47542 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47543 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47547 | GIR_RootConstrainSelectedInstOperands, |
| 47548 | // GIR_Coverage, 48145, |
| 47549 | GIR_EraseRootFromParent_Done, |
| 47550 | // Label 3293: @123352 |
| 47551 | GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(123406), // Rule ID 48210 // |
| 47552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47553 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 47554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47555 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47556 | // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 47558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 47562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47564 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47568 | GIR_RootConstrainSelectedInstOperands, |
| 47569 | // GIR_Coverage, 48210, |
| 47570 | GIR_EraseRootFromParent_Done, |
| 47571 | // Label 3294: @123406 |
| 47572 | GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(123460), // Rule ID 48211 // |
| 47573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47574 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 47575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47577 | // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47578 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 47579 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47580 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M2), |
| 47583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47585 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47589 | GIR_RootConstrainSelectedInstOperands, |
| 47590 | // GIR_Coverage, 48211, |
| 47591 | GIR_EraseRootFromParent_Done, |
| 47592 | // Label 3295: @123460 |
| 47593 | GIM_Reject, |
| 47594 | // Label 3252: @123461 |
| 47595 | GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(123515), // Rule ID 48164 // |
| 47596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47597 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 47598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47599 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47600 | // (zext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47601 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 47602 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47603 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 47606 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47607 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47608 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47612 | GIR_RootConstrainSelectedInstOperands, |
| 47613 | // GIR_Coverage, 48164, |
| 47614 | GIR_EraseRootFromParent_Done, |
| 47615 | // Label 3296: @123515 |
| 47616 | GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(123569), // Rule ID 48165 // |
| 47617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 47619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47620 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47621 | // (zext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47622 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 47623 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47624 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 47627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47629 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47633 | GIR_RootConstrainSelectedInstOperands, |
| 47634 | // GIR_Coverage, 48165, |
| 47635 | GIR_EraseRootFromParent_Done, |
| 47636 | // Label 3297: @123569 |
| 47637 | GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(123623), // Rule ID 48230 // |
| 47638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47639 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 47640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47641 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47642 | // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47643 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 47644 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47645 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 47648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47649 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47650 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47654 | GIR_RootConstrainSelectedInstOperands, |
| 47655 | // GIR_Coverage, 48230, |
| 47656 | GIR_EraseRootFromParent_Done, |
| 47657 | // Label 3298: @123623 |
| 47658 | GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(123677), // Rule ID 48231 // |
| 47659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47660 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 47661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47662 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47663 | // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47664 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 47665 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47666 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47667 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 47669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47671 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47675 | GIR_RootConstrainSelectedInstOperands, |
| 47676 | // GIR_Coverage, 48231, |
| 47677 | GIR_EraseRootFromParent_Done, |
| 47678 | // Label 3299: @123677 |
| 47679 | GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(123731), // Rule ID 48264 // |
| 47680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47681 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 47682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47684 | // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 47686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M4), |
| 47690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47691 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47692 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47696 | GIR_RootConstrainSelectedInstOperands, |
| 47697 | // GIR_Coverage, 48264, |
| 47698 | GIR_EraseRootFromParent_Done, |
| 47699 | // Label 3300: @123731 |
| 47700 | GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(123785), // Rule ID 48265 // |
| 47701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47702 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 47703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47705 | // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2) => (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 47707 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47708 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M4), |
| 47711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47713 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47717 | GIR_RootConstrainSelectedInstOperands, |
| 47718 | // GIR_Coverage, 48265, |
| 47719 | GIR_EraseRootFromParent_Done, |
| 47720 | // Label 3301: @123785 |
| 47721 | GIM_Reject, |
| 47722 | // Label 3253: @123786 |
| 47723 | GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(123889), |
| 47724 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 47725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47727 | GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(123845), // Rule ID 48124 // |
| 47728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47729 | // (zext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 47730 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 47731 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47732 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 47735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47736 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47737 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47741 | GIR_RootConstrainSelectedInstOperands, |
| 47742 | // GIR_Coverage, 48124, |
| 47743 | GIR_EraseRootFromParent_Done, |
| 47744 | // Label 3303: @123845 |
| 47745 | GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(123888), // Rule ID 48125 // |
| 47746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47747 | // (zext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 47748 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 47749 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47750 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M2), |
| 47753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47754 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47755 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47759 | GIR_RootConstrainSelectedInstOperands, |
| 47760 | // GIR_Coverage, 48125, |
| 47761 | GIR_EraseRootFromParent_Done, |
| 47762 | // Label 3304: @123888 |
| 47763 | GIM_Reject, |
| 47764 | // Label 3302: @123889 |
| 47765 | GIM_Reject, |
| 47766 | // Label 3254: @123890 |
| 47767 | GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(123944), // Rule ID 48148 // |
| 47768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47769 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 47770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47772 | // (zext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 47774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 47778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47784 | GIR_RootConstrainSelectedInstOperands, |
| 47785 | // GIR_Coverage, 48148, |
| 47786 | GIR_EraseRootFromParent_Done, |
| 47787 | // Label 3305: @123944 |
| 47788 | GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(123998), // Rule ID 48149 // |
| 47789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47790 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 47791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47792 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47793 | // (zext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47794 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 47795 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47796 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47797 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 47799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47800 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47801 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47805 | GIR_RootConstrainSelectedInstOperands, |
| 47806 | // GIR_Coverage, 48149, |
| 47807 | GIR_EraseRootFromParent_Done, |
| 47808 | // Label 3306: @123998 |
| 47809 | GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(124052), // Rule ID 48214 // |
| 47810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47811 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 47812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47813 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47814 | // (zext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 47815 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 47816 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47817 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 47820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47821 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47822 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47826 | GIR_RootConstrainSelectedInstOperands, |
| 47827 | // GIR_Coverage, 48214, |
| 47828 | GIR_EraseRootFromParent_Done, |
| 47829 | // Label 3307: @124052 |
| 47830 | GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(124106), // Rule ID 48215 // |
| 47831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 47832 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 47833 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47834 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47835 | // (zext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 47836 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 47837 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47838 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M4), |
| 47841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47843 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 47846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47847 | GIR_RootConstrainSelectedInstOperands, |
| 47848 | // GIR_Coverage, 48215, |
| 47849 | GIR_EraseRootFromParent_Done, |
| 47850 | // Label 3308: @124106 |
| 47851 | GIM_Reject, |
| 47852 | // Label 3255: @124107 |
| 47853 | GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(124161), // Rule ID 48168 // |
| 47854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47855 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 47856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 47857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47858 | // (zext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47859 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 47860 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47861 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 47864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47865 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47866 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47870 | GIR_RootConstrainSelectedInstOperands, |
| 47871 | // GIR_Coverage, 48168, |
| 47872 | GIR_EraseRootFromParent_Done, |
| 47873 | // Label 3309: @124161 |
| 47874 | GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(124215), // Rule ID 48169 // |
| 47875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47876 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 47877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 47878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47879 | // (zext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47880 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 47881 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47882 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47883 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 47885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47886 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47887 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47891 | GIR_RootConstrainSelectedInstOperands, |
| 47892 | // GIR_Coverage, 48169, |
| 47893 | GIR_EraseRootFromParent_Done, |
| 47894 | // Label 3310: @124215 |
| 47895 | GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(124269), // Rule ID 48234 // |
| 47896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47897 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 47898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 47899 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47900 | // (zext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47901 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 47902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 47906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47907 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47912 | GIR_RootConstrainSelectedInstOperands, |
| 47913 | // GIR_Coverage, 48234, |
| 47914 | GIR_EraseRootFromParent_Done, |
| 47915 | // Label 3311: @124269 |
| 47916 | GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(124323), // Rule ID 48235 // |
| 47917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47918 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 47919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 47920 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47921 | // (zext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47922 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 47923 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47924 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 47927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47928 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47929 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47933 | GIR_RootConstrainSelectedInstOperands, |
| 47934 | // GIR_Coverage, 48235, |
| 47935 | GIR_EraseRootFromParent_Done, |
| 47936 | // Label 3312: @124323 |
| 47937 | GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(124377), // Rule ID 48268 // |
| 47938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0), |
| 47939 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 47940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 47941 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47942 | // (zext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 47943 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 47944 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47945 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M8), |
| 47948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47949 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47950 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47954 | GIR_RootConstrainSelectedInstOperands, |
| 47955 | // GIR_Coverage, 48268, |
| 47956 | GIR_EraseRootFromParent_Done, |
| 47957 | // Label 3313: @124377 |
| 47958 | GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(124431), // Rule ID 48269 // |
| 47959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1), |
| 47960 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 47961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 47962 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 47963 | // (zext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2) => (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 47964 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 47965 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47966 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF8_M8), |
| 47969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47970 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47971 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 47974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47975 | GIR_RootConstrainSelectedInstOperands, |
| 47976 | // GIR_Coverage, 48269, |
| 47977 | GIR_EraseRootFromParent_Done, |
| 47978 | // Label 3314: @124431 |
| 47979 | GIM_Reject, |
| 47980 | // Label 3256: @124432 |
| 47981 | GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(124535), |
| 47982 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 47983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 47984 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 47985 | GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(124491), // Rule ID 48128 // |
| 47986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 47987 | // (zext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 47988 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 47989 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 47990 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 47993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 47994 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47995 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 47996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 47997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 47998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 47999 | GIR_RootConstrainSelectedInstOperands, |
| 48000 | // GIR_Coverage, 48128, |
| 48001 | GIR_EraseRootFromParent_Done, |
| 48002 | // Label 3316: @124491 |
| 48003 | GIM_Try, /*On fail goto*//*Label 3317*/ GIMT_Encode4(124534), // Rule ID 48129 // |
| 48004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48005 | // (zext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 48006 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 48007 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48008 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48009 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M4), |
| 48011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48012 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48013 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48017 | GIR_RootConstrainSelectedInstOperands, |
| 48018 | // GIR_Coverage, 48129, |
| 48019 | GIR_EraseRootFromParent_Done, |
| 48020 | // Label 3317: @124534 |
| 48021 | GIM_Reject, |
| 48022 | // Label 3315: @124535 |
| 48023 | GIM_Reject, |
| 48024 | // Label 3257: @124536 |
| 48025 | GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(124590), // Rule ID 48152 // |
| 48026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48027 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 48028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 48029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 48030 | // (zext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 48031 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 48032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48033 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48034 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 48036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48037 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48038 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48042 | GIR_RootConstrainSelectedInstOperands, |
| 48043 | // GIR_Coverage, 48152, |
| 48044 | GIR_EraseRootFromParent_Done, |
| 48045 | // Label 3318: @124590 |
| 48046 | GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(124644), // Rule ID 48153 // |
| 48047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48048 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 48049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 48050 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 48051 | // (zext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 48052 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 48053 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48054 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 48057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48058 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48059 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48063 | GIR_RootConstrainSelectedInstOperands, |
| 48064 | // GIR_Coverage, 48153, |
| 48065 | GIR_EraseRootFromParent_Done, |
| 48066 | // Label 3319: @124644 |
| 48067 | GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(124698), // Rule ID 48218 // |
| 48068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48069 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 48070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 48071 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48072 | // (zext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 48073 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 48074 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48075 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48076 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 48078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48079 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48080 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48084 | GIR_RootConstrainSelectedInstOperands, |
| 48085 | // GIR_Coverage, 48218, |
| 48086 | GIR_EraseRootFromParent_Done, |
| 48087 | // Label 3320: @124698 |
| 48088 | GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(124752), // Rule ID 48219 // |
| 48089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48090 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 48091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 48092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48093 | // (zext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 48094 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 48095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF4_M8), |
| 48099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48100 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48101 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48105 | GIR_RootConstrainSelectedInstOperands, |
| 48106 | // GIR_Coverage, 48219, |
| 48107 | GIR_EraseRootFromParent_Done, |
| 48108 | // Label 3321: @124752 |
| 48109 | GIM_Reject, |
| 48110 | // Label 3258: @124753 |
| 48111 | GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(124856), |
| 48112 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 48113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 48114 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 48115 | GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(124812), // Rule ID 48132 // |
| 48116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48117 | // (zext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 48118 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 48119 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48120 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 48123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48124 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48125 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48129 | GIR_RootConstrainSelectedInstOperands, |
| 48130 | // GIR_Coverage, 48132, |
| 48131 | GIR_EraseRootFromParent_Done, |
| 48132 | // Label 3323: @124812 |
| 48133 | GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(124855), // Rule ID 48133 // |
| 48134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48135 | // (zext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 48136 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 48137 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48138 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVZEXT_VF2_M8), |
| 48141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48143 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 48144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48147 | GIR_RootConstrainSelectedInstOperands, |
| 48148 | // GIR_Coverage, 48133, |
| 48149 | GIR_EraseRootFromParent_Done, |
| 48150 | // Label 3324: @124855 |
| 48151 | GIM_Reject, |
| 48152 | // Label 3322: @124856 |
| 48153 | GIM_Reject, |
| 48154 | // Label 3259: @124857 |
| 48155 | GIM_Reject, |
| 48156 | // Label 39: @124858 |
| 48157 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 3349*/ GIMT_Encode4(128302), |
| 48158 | /*GILLT_s32*//*Label 3325*/ GIMT_Encode4(124993), |
| 48159 | /*GILLT_s64*//*Label 3326*/ GIMT_Encode4(125366), GIMT_Encode4(0), |
| 48160 | /*GILLT_nxv1s8*//*Label 3327*/ GIMT_Encode4(125772), |
| 48161 | /*GILLT_nxv1s16*//*Label 3328*/ GIMT_Encode4(125887), |
| 48162 | /*GILLT_nxv1s32*//*Label 3329*/ GIMT_Encode4(126002), |
| 48163 | /*GILLT_nxv1s64*//*Label 3330*/ GIMT_Encode4(126117), GIMT_Encode4(0), |
| 48164 | /*GILLT_nxv2s8*//*Label 3331*/ GIMT_Encode4(126232), |
| 48165 | /*GILLT_nxv2s16*//*Label 3332*/ GIMT_Encode4(126347), |
| 48166 | /*GILLT_nxv2s32*//*Label 3333*/ GIMT_Encode4(126462), |
| 48167 | /*GILLT_nxv2s64*//*Label 3334*/ GIMT_Encode4(126577), GIMT_Encode4(0), |
| 48168 | /*GILLT_nxv4s8*//*Label 3335*/ GIMT_Encode4(126692), |
| 48169 | /*GILLT_nxv4s16*//*Label 3336*/ GIMT_Encode4(126807), |
| 48170 | /*GILLT_nxv4s32*//*Label 3337*/ GIMT_Encode4(126922), |
| 48171 | /*GILLT_nxv4s64*//*Label 3338*/ GIMT_Encode4(127037), GIMT_Encode4(0), |
| 48172 | /*GILLT_nxv8s8*//*Label 3339*/ GIMT_Encode4(127152), |
| 48173 | /*GILLT_nxv8s16*//*Label 3340*/ GIMT_Encode4(127267), |
| 48174 | /*GILLT_nxv8s32*//*Label 3341*/ GIMT_Encode4(127382), |
| 48175 | /*GILLT_nxv8s64*//*Label 3342*/ GIMT_Encode4(127497), GIMT_Encode4(0), |
| 48176 | /*GILLT_nxv16s8*//*Label 3343*/ GIMT_Encode4(127612), |
| 48177 | /*GILLT_nxv16s16*//*Label 3344*/ GIMT_Encode4(127727), |
| 48178 | /*GILLT_nxv16s32*//*Label 3345*/ GIMT_Encode4(127842), GIMT_Encode4(0), |
| 48179 | /*GILLT_nxv32s8*//*Label 3346*/ GIMT_Encode4(127957), |
| 48180 | /*GILLT_nxv32s16*//*Label 3347*/ GIMT_Encode4(128072), GIMT_Encode4(0), |
| 48181 | /*GILLT_nxv64s8*//*Label 3348*/ GIMT_Encode4(128187), |
| 48182 | // Label 3325: @124993 |
| 48183 | GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(125365), |
| 48184 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 48185 | GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(125045), // Rule ID 2631 // |
| 48186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), |
| 48187 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48189 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 1, |
| 48190 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 48191 | // (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)) => (BSET:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs2) |
| 48192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 48193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48194 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 48196 | GIR_RootConstrainSelectedInstOperands, |
| 48197 | // GIR_Coverage, 2631, |
| 48198 | GIR_EraseRootFromParent_Done, |
| 48199 | // Label 3351: @125045 |
| 48200 | GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(125089), // Rule ID 2854 // |
| 48201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), |
| 48202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 48203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48204 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 1, |
| 48205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 48206 | // (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (BSET:{ *:[i32] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs2) |
| 48207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 48208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48209 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 48211 | GIR_RootConstrainSelectedInstOperands, |
| 48212 | // GIR_Coverage, 2854, |
| 48213 | GIR_EraseRootFromParent_Done, |
| 48214 | // Label 3352: @125089 |
| 48215 | GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(125134), // Rule ID 85 // |
| 48216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 48217 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48219 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48220 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 48221 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48222 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 48223 | // MIs[1] Operand 1 |
| 48224 | // No operand predicates |
| 48225 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48226 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 48227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 48228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48229 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48230 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 48231 | GIR_RootConstrainSelectedInstOperands, |
| 48232 | // GIR_Coverage, 85, |
| 48233 | GIR_EraseRootFromParent_Done, |
| 48234 | // Label 3353: @125134 |
| 48235 | GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(125179), // Rule ID 314 // |
| 48236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 48237 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 48238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48240 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 48241 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48242 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 48243 | // MIs[1] Operand 1 |
| 48244 | // No operand predicates |
| 48245 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48246 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) => (SLLIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) |
| 48247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLIW), |
| 48248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48249 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48250 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 48251 | GIR_RootConstrainSelectedInstOperands, |
| 48252 | // GIR_Coverage, 314, |
| 48253 | GIR_EraseRootFromParent_Done, |
| 48254 | // Label 3354: @125179 |
| 48255 | GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(125224), // Rule ID 315 // |
| 48256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 48257 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48260 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 48261 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48262 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 48263 | // MIs[1] Operand 1 |
| 48264 | // No operand predicates |
| 48265 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48266 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (SLLIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 48267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLIW), |
| 48268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48270 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 48271 | GIR_RootConstrainSelectedInstOperands, |
| 48272 | // GIR_Coverage, 315, |
| 48273 | GIR_EraseRootFromParent_Done, |
| 48274 | // Label 3355: @125224 |
| 48275 | GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(125264), // Rule ID 98 // |
| 48276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 48277 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48279 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48280 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 48281 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 48282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLL), |
| 48283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48284 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 48286 | GIR_RootConstrainSelectedInstOperands, |
| 48287 | // GIR_Coverage, 98, |
| 48288 | GIR_EraseRootFromParent_Done, |
| 48289 | // Label 3356: @125264 |
| 48290 | GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(125304), // Rule ID 307 // |
| 48291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 48292 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 48293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48294 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMask32), |
| 48296 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMask32:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (SLLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 48297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLW), |
| 48298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48299 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 48301 | GIR_RootConstrainSelectedInstOperands, |
| 48302 | // GIR_Coverage, 307, |
| 48303 | GIR_EraseRootFromParent_Done, |
| 48304 | // Label 3357: @125304 |
| 48305 | GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(125334), // Rule ID 65045 // |
| 48306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 48307 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48309 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48311 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SLLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 48312 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SLLW), |
| 48313 | GIR_RootConstrainSelectedInstOperands, |
| 48314 | // GIR_Coverage, 65045, |
| 48315 | GIR_Done, |
| 48316 | // Label 3358: @125334 |
| 48317 | GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(125364), // Rule ID 65046 // |
| 48318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 48319 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 48320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48321 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48322 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48323 | // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SLLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 48324 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SLLW), |
| 48325 | GIR_RootConstrainSelectedInstOperands, |
| 48326 | // GIR_Coverage, 65046, |
| 48327 | GIR_Done, |
| 48328 | // Label 3359: @125364 |
| 48329 | GIM_Reject, |
| 48330 | // Label 3350: @125365 |
| 48331 | GIM_Reject, |
| 48332 | // Label 3326: @125366 |
| 48333 | GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(125771), |
| 48334 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 48335 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 48336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48337 | GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(125471), // Rule ID 244 // |
| 48338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_NotHasStdExtZba_HwMode0), |
| 48339 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 48340 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 48341 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 48342 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48343 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48344 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), |
| 48345 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 48346 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48347 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 48348 | // MIs[2] Operand 1 |
| 48349 | // No operand predicates |
| 48350 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 48351 | // (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), (ImmSubFrom32:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)) |
| 48352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 48353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 48354 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48355 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 48356 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 48357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 48359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48360 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48361 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFrom32), // shamt |
| 48362 | GIR_RootConstrainSelectedInstOperands, |
| 48363 | // GIR_Coverage, 244, |
| 48364 | GIR_EraseRootFromParent_Done, |
| 48365 | // Label 3361: @125471 |
| 48366 | GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(125539), // Rule ID 2745 // |
| 48367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 48368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 48369 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 48370 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 48371 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48372 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48373 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), |
| 48374 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 48375 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48376 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 48377 | // MIs[2] Operand 1 |
| 48378 | // No operand predicates |
| 48379 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 48380 | // (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) => (SLLI_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) |
| 48381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLI_UW), |
| 48382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 48384 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 48385 | GIR_RootConstrainSelectedInstOperands, |
| 48386 | // GIR_Coverage, 2745, |
| 48387 | GIR_EraseRootFromParent_Done, |
| 48388 | // Label 3362: @125539 |
| 48389 | GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(125576), // Rule ID 2630 // |
| 48390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), |
| 48391 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 1, |
| 48392 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 48393 | // (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (BSET:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs2) |
| 48394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BSET), |
| 48395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48396 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 48397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 48398 | GIR_RootConstrainSelectedInstOperands, |
| 48399 | // GIR_Coverage, 2630, |
| 48400 | GIR_EraseRootFromParent_Done, |
| 48401 | // Label 3363: @125576 |
| 48402 | GIM_Try, /*On fail goto*//*Label 3364*/ GIMT_Encode4(125651), // Rule ID 323 // |
| 48403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_NotHasStdExtZba_HwMode0), |
| 48404 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 48405 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 48406 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 48407 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48408 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 48409 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48410 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 48411 | // MIs[2] Operand 1 |
| 48412 | // No operand predicates |
| 48413 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 48414 | // (shl:{ *:[i64] } (zext:{ *:[i64] } GPR:{ *:[i32] }:$rs), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i32] }:$rs, 32:{ *:[i64] }), (ImmSubFrom32:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)) |
| 48415 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 48416 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 48417 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48418 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 48419 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 48420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 48422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48423 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48424 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFrom32), // shamt |
| 48425 | GIR_RootConstrainSelectedInstOperands, |
| 48426 | // GIR_Coverage, 323, |
| 48427 | GIR_EraseRootFromParent_Done, |
| 48428 | // Label 3364: @125651 |
| 48429 | GIM_Try, /*On fail goto*//*Label 3365*/ GIMT_Encode4(125699), // Rule ID 2826 // |
| 48430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), |
| 48431 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 48432 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 48433 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 48434 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 48435 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48436 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 48437 | // MIs[2] Operand 1 |
| 48438 | // No operand predicates |
| 48439 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 48440 | // (shl:{ *:[i64] } (zext:{ *:[i64] } i32:{ *:[i32] }:$rs1), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) => (SLLI_UW:{ *:[i64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) |
| 48441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLI_UW), |
| 48442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 48444 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 48445 | GIR_RootConstrainSelectedInstOperands, |
| 48446 | // GIR_Coverage, 2826, |
| 48447 | GIR_EraseRootFromParent_Done, |
| 48448 | // Label 3365: @125699 |
| 48449 | GIM_Try, /*On fail goto*//*Label 3366*/ GIMT_Encode4(125737), // Rule ID 84 // |
| 48450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 48451 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48452 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 48453 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 48454 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 48455 | // MIs[1] Operand 1 |
| 48456 | // No operand predicates |
| 48457 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 48458 | // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) => (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 48459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLI), |
| 48460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48461 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48462 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 48463 | GIR_RootConstrainSelectedInstOperands, |
| 48464 | // GIR_Coverage, 84, |
| 48465 | GIR_EraseRootFromParent_Done, |
| 48466 | // Label 3366: @125737 |
| 48467 | GIM_Try, /*On fail goto*//*Label 3367*/ GIMT_Encode4(125770), // Rule ID 97 // |
| 48468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 48469 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 48470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 48471 | // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 48472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLL), |
| 48473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48474 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 48476 | GIR_RootConstrainSelectedInstOperands, |
| 48477 | // GIR_Coverage, 97, |
| 48478 | GIR_EraseRootFromParent_Done, |
| 48479 | // Label 3367: @125770 |
| 48480 | GIM_Reject, |
| 48481 | // Label 3360: @125771 |
| 48482 | GIM_Reject, |
| 48483 | // Label 3327: @125772 |
| 48484 | GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(125886), |
| 48485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 48486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 48487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48490 | GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(125840), // Rule ID 48676 // |
| 48491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48492 | // (shl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSLL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 48493 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 48494 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48495 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF8), |
| 48498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48501 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48505 | GIR_RootConstrainSelectedInstOperands, |
| 48506 | // GIR_Coverage, 48676, |
| 48507 | GIR_EraseRootFromParent_Done, |
| 48508 | // Label 3369: @125840 |
| 48509 | GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(125885), // Rule ID 48677 // |
| 48510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48511 | // (shl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSLL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 48512 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 48513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF8), |
| 48517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48518 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48520 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48524 | GIR_RootConstrainSelectedInstOperands, |
| 48525 | // GIR_Coverage, 48677, |
| 48526 | GIR_EraseRootFromParent_Done, |
| 48527 | // Label 3370: @125885 |
| 48528 | GIM_Reject, |
| 48529 | // Label 3368: @125886 |
| 48530 | GIM_Reject, |
| 48531 | // Label 3328: @125887 |
| 48532 | GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(126001), |
| 48533 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 48534 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 48535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48538 | GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(125955), // Rule ID 48688 // |
| 48539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48540 | // (shl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSLL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 48541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 48542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF4), |
| 48546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48548 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48549 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48553 | GIR_RootConstrainSelectedInstOperands, |
| 48554 | // GIR_Coverage, 48688, |
| 48555 | GIR_EraseRootFromParent_Done, |
| 48556 | // Label 3372: @125955 |
| 48557 | GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(126000), // Rule ID 48689 // |
| 48558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48559 | // (shl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSLL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 48560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 48561 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48562 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF4), |
| 48565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48566 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48567 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48568 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48572 | GIR_RootConstrainSelectedInstOperands, |
| 48573 | // GIR_Coverage, 48689, |
| 48574 | GIR_EraseRootFromParent_Done, |
| 48575 | // Label 3373: @126000 |
| 48576 | GIM_Reject, |
| 48577 | // Label 3371: @126001 |
| 48578 | GIM_Reject, |
| 48579 | // Label 3329: @126002 |
| 48580 | GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(126116), |
| 48581 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 48582 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 48583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48586 | GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(126070), // Rule ID 48696 // |
| 48587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48588 | // (shl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSLL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 48589 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 48590 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48591 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF2), |
| 48594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48595 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48596 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48597 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48601 | GIR_RootConstrainSelectedInstOperands, |
| 48602 | // GIR_Coverage, 48696, |
| 48603 | GIR_EraseRootFromParent_Done, |
| 48604 | // Label 3375: @126070 |
| 48605 | GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(126115), // Rule ID 48697 // |
| 48606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48607 | // (shl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSLL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 48608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 48609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF2), |
| 48613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48616 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48620 | GIR_RootConstrainSelectedInstOperands, |
| 48621 | // GIR_Coverage, 48697, |
| 48622 | GIR_EraseRootFromParent_Done, |
| 48623 | // Label 3376: @126115 |
| 48624 | GIM_Reject, |
| 48625 | // Label 3374: @126116 |
| 48626 | GIM_Reject, |
| 48627 | // Label 3330: @126117 |
| 48628 | GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(126231), |
| 48629 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 48630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 48631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48632 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48634 | GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(126185), // Rule ID 48712 // |
| 48635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 48636 | // (shl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 48637 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 48638 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48639 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 48642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48643 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48644 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48645 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 48648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48649 | GIR_RootConstrainSelectedInstOperands, |
| 48650 | // GIR_Coverage, 48712, |
| 48651 | GIR_EraseRootFromParent_Done, |
| 48652 | // Label 3378: @126185 |
| 48653 | GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(126230), // Rule ID 48713 // |
| 48654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 48655 | // (shl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 48656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 48657 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48658 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 48661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48663 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48664 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 48667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48668 | GIR_RootConstrainSelectedInstOperands, |
| 48669 | // GIR_Coverage, 48713, |
| 48670 | GIR_EraseRootFromParent_Done, |
| 48671 | // Label 3379: @126230 |
| 48672 | GIM_Reject, |
| 48673 | // Label 3377: @126231 |
| 48674 | GIM_Reject, |
| 48675 | // Label 3331: @126232 |
| 48676 | GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(126346), |
| 48677 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 48678 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 48679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48682 | GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(126300), // Rule ID 48680 // |
| 48683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48684 | // (shl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSLL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 48685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 48686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF4), |
| 48690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48691 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48692 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48693 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48697 | GIR_RootConstrainSelectedInstOperands, |
| 48698 | // GIR_Coverage, 48680, |
| 48699 | GIR_EraseRootFromParent_Done, |
| 48700 | // Label 3381: @126300 |
| 48701 | GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(126345), // Rule ID 48681 // |
| 48702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48703 | // (shl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSLL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 48704 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 48705 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48706 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF4), |
| 48709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48710 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48711 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48712 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48716 | GIR_RootConstrainSelectedInstOperands, |
| 48717 | // GIR_Coverage, 48681, |
| 48718 | GIR_EraseRootFromParent_Done, |
| 48719 | // Label 3382: @126345 |
| 48720 | GIM_Reject, |
| 48721 | // Label 3380: @126346 |
| 48722 | GIM_Reject, |
| 48723 | // Label 3332: @126347 |
| 48724 | GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(126461), |
| 48725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 48726 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 48727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48730 | GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(126415), // Rule ID 48692 // |
| 48731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48732 | // (shl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSLL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 48733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 48734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF2), |
| 48738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48739 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48740 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48741 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48745 | GIR_RootConstrainSelectedInstOperands, |
| 48746 | // GIR_Coverage, 48692, |
| 48747 | GIR_EraseRootFromParent_Done, |
| 48748 | // Label 3384: @126415 |
| 48749 | GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(126460), // Rule ID 48693 // |
| 48750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48751 | // (shl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSLL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 48752 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 48753 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48754 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF2), |
| 48757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48758 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48759 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48760 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48764 | GIR_RootConstrainSelectedInstOperands, |
| 48765 | // GIR_Coverage, 48693, |
| 48766 | GIR_EraseRootFromParent_Done, |
| 48767 | // Label 3385: @126460 |
| 48768 | GIM_Reject, |
| 48769 | // Label 3383: @126461 |
| 48770 | GIM_Reject, |
| 48771 | // Label 3333: @126462 |
| 48772 | GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(126576), |
| 48773 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 48774 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 48775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48777 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48778 | GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(126530), // Rule ID 48708 // |
| 48779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48780 | // (shl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 48781 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 48782 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48783 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 48786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48787 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48788 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48789 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48793 | GIR_RootConstrainSelectedInstOperands, |
| 48794 | // GIR_Coverage, 48708, |
| 48795 | GIR_EraseRootFromParent_Done, |
| 48796 | // Label 3387: @126530 |
| 48797 | GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(126575), // Rule ID 48709 // |
| 48798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48799 | // (shl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 48800 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 48801 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48802 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 48805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48806 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48807 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48808 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48812 | GIR_RootConstrainSelectedInstOperands, |
| 48813 | // GIR_Coverage, 48709, |
| 48814 | GIR_EraseRootFromParent_Done, |
| 48815 | // Label 3388: @126575 |
| 48816 | GIM_Reject, |
| 48817 | // Label 3386: @126576 |
| 48818 | GIM_Reject, |
| 48819 | // Label 3334: @126577 |
| 48820 | GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(126691), |
| 48821 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 48822 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 48823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48826 | GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(126645), // Rule ID 48752 // |
| 48827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 48828 | // (shl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 48829 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 48830 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48831 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 48834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48835 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48836 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48837 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 48840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48841 | GIR_RootConstrainSelectedInstOperands, |
| 48842 | // GIR_Coverage, 48752, |
| 48843 | GIR_EraseRootFromParent_Done, |
| 48844 | // Label 3390: @126645 |
| 48845 | GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(126690), // Rule ID 48753 // |
| 48846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 48847 | // (shl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 48848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 48849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 48853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48854 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48855 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48856 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 48859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48860 | GIR_RootConstrainSelectedInstOperands, |
| 48861 | // GIR_Coverage, 48753, |
| 48862 | GIR_EraseRootFromParent_Done, |
| 48863 | // Label 3391: @126690 |
| 48864 | GIM_Reject, |
| 48865 | // Label 3389: @126691 |
| 48866 | GIM_Reject, |
| 48867 | // Label 3335: @126692 |
| 48868 | GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(126806), |
| 48869 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 48870 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 48871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48874 | GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(126760), // Rule ID 48684 // |
| 48875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48876 | // (shl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSLL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 48877 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 48878 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48879 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48880 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF2), |
| 48882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48883 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48884 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48885 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48889 | GIR_RootConstrainSelectedInstOperands, |
| 48890 | // GIR_Coverage, 48684, |
| 48891 | GIR_EraseRootFromParent_Done, |
| 48892 | // Label 3393: @126760 |
| 48893 | GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(126805), // Rule ID 48685 // |
| 48894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48895 | // (shl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSLL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 48896 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 48897 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48898 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48899 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_MF2), |
| 48901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48902 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48903 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48904 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48908 | GIR_RootConstrainSelectedInstOperands, |
| 48909 | // GIR_Coverage, 48685, |
| 48910 | GIR_EraseRootFromParent_Done, |
| 48911 | // Label 3394: @126805 |
| 48912 | GIM_Reject, |
| 48913 | // Label 3392: @126806 |
| 48914 | GIM_Reject, |
| 48915 | // Label 3336: @126807 |
| 48916 | GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(126921), |
| 48917 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 48918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 48919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48920 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48921 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 48922 | GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(126875), // Rule ID 48704 // |
| 48923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48924 | // (shl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 48925 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 48926 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48927 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48928 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 48930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48931 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48932 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48933 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48937 | GIR_RootConstrainSelectedInstOperands, |
| 48938 | // GIR_Coverage, 48704, |
| 48939 | GIR_EraseRootFromParent_Done, |
| 48940 | // Label 3396: @126875 |
| 48941 | GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(126920), // Rule ID 48705 // |
| 48942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48943 | // (shl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 48944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 48945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 48949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48950 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48951 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48952 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 48955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48956 | GIR_RootConstrainSelectedInstOperands, |
| 48957 | // GIR_Coverage, 48705, |
| 48958 | GIR_EraseRootFromParent_Done, |
| 48959 | // Label 3397: @126920 |
| 48960 | GIM_Reject, |
| 48961 | // Label 3395: @126921 |
| 48962 | GIM_Reject, |
| 48963 | // Label 3337: @126922 |
| 48964 | GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(127036), |
| 48965 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 48966 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 48967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48968 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 48970 | GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(126990), // Rule ID 48740 // |
| 48971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 48972 | // (shl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 48973 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 48974 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48975 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 48978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48979 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48980 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 48981 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 48982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 48983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 48984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 48985 | GIR_RootConstrainSelectedInstOperands, |
| 48986 | // GIR_Coverage, 48740, |
| 48987 | GIR_EraseRootFromParent_Done, |
| 48988 | // Label 3399: @126990 |
| 48989 | GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(127035), // Rule ID 48741 // |
| 48990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 48991 | // (shl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 48992 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 48993 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 48994 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48995 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 48997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 48998 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48999 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49000 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49004 | GIR_RootConstrainSelectedInstOperands, |
| 49005 | // GIR_Coverage, 48741, |
| 49006 | GIR_EraseRootFromParent_Done, |
| 49007 | // Label 3400: @127035 |
| 49008 | GIM_Reject, |
| 49009 | // Label 3398: @127036 |
| 49010 | GIM_Reject, |
| 49011 | // Label 3338: @127037 |
| 49012 | GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(127151), |
| 49013 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 49014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 49015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49017 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49018 | GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(127105), // Rule ID 48756 // |
| 49019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 49020 | // (shl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 49021 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 49022 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49023 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49024 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49027 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49028 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49029 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 49032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49033 | GIR_RootConstrainSelectedInstOperands, |
| 49034 | // GIR_Coverage, 48756, |
| 49035 | GIR_EraseRootFromParent_Done, |
| 49036 | // Label 3402: @127105 |
| 49037 | GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(127150), // Rule ID 48757 // |
| 49038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 49039 | // (shl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 49040 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 49041 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49042 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49046 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49047 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 49051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49052 | GIR_RootConstrainSelectedInstOperands, |
| 49053 | // GIR_Coverage, 48757, |
| 49054 | GIR_EraseRootFromParent_Done, |
| 49055 | // Label 3403: @127150 |
| 49056 | GIM_Reject, |
| 49057 | // Label 3401: @127151 |
| 49058 | GIM_Reject, |
| 49059 | // Label 3339: @127152 |
| 49060 | GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(127266), |
| 49061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 49062 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 49063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49064 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49066 | GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(127220), // Rule ID 48700 // |
| 49067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49068 | // (shl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 49069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 49070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 49074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49076 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49077 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49081 | GIR_RootConstrainSelectedInstOperands, |
| 49082 | // GIR_Coverage, 48700, |
| 49083 | GIR_EraseRootFromParent_Done, |
| 49084 | // Label 3405: @127220 |
| 49085 | GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(127265), // Rule ID 48701 // |
| 49086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49087 | // (shl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSLL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 49088 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 49089 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49090 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M1), |
| 49093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49095 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49096 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49100 | GIR_RootConstrainSelectedInstOperands, |
| 49101 | // GIR_Coverage, 48701, |
| 49102 | GIR_EraseRootFromParent_Done, |
| 49103 | // Label 3406: @127265 |
| 49104 | GIM_Reject, |
| 49105 | // Label 3404: @127266 |
| 49106 | GIM_Reject, |
| 49107 | // Label 3340: @127267 |
| 49108 | GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(127381), |
| 49109 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 49110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 49111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 49112 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 49113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 49114 | GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(127335), // Rule ID 48728 // |
| 49115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49116 | // (shl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 49117 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 49118 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49119 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 49122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49123 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49124 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49125 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49129 | GIR_RootConstrainSelectedInstOperands, |
| 49130 | // GIR_Coverage, 48728, |
| 49131 | GIR_EraseRootFromParent_Done, |
| 49132 | // Label 3408: @127335 |
| 49133 | GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(127380), // Rule ID 48729 // |
| 49134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49135 | // (shl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 49136 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 49137 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49138 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 49141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49143 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49144 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49148 | GIR_RootConstrainSelectedInstOperands, |
| 49149 | // GIR_Coverage, 48729, |
| 49150 | GIR_EraseRootFromParent_Done, |
| 49151 | // Label 3409: @127380 |
| 49152 | GIM_Reject, |
| 49153 | // Label 3407: @127381 |
| 49154 | GIM_Reject, |
| 49155 | // Label 3341: @127382 |
| 49156 | GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(127496), |
| 49157 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 49158 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 49159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49160 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49162 | GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(127450), // Rule ID 48744 // |
| 49163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49164 | // (shl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 49165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 49166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49171 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49172 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49173 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49177 | GIR_RootConstrainSelectedInstOperands, |
| 49178 | // GIR_Coverage, 48744, |
| 49179 | GIR_EraseRootFromParent_Done, |
| 49180 | // Label 3411: @127450 |
| 49181 | GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(127495), // Rule ID 48745 // |
| 49182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49183 | // (shl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 49184 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 49185 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49186 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49190 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49191 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49192 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49196 | GIR_RootConstrainSelectedInstOperands, |
| 49197 | // GIR_Coverage, 48745, |
| 49198 | GIR_EraseRootFromParent_Done, |
| 49199 | // Label 3412: @127495 |
| 49200 | GIM_Reject, |
| 49201 | // Label 3410: @127496 |
| 49202 | GIM_Reject, |
| 49203 | // Label 3342: @127497 |
| 49204 | GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(127611), |
| 49205 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 49206 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 49207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49208 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49209 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49210 | GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(127565), // Rule ID 48760 // |
| 49211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 49212 | // (shl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 49213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 49214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49219 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49220 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49221 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 49224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49225 | GIR_RootConstrainSelectedInstOperands, |
| 49226 | // GIR_Coverage, 48760, |
| 49227 | GIR_EraseRootFromParent_Done, |
| 49228 | // Label 3414: @127565 |
| 49229 | GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(127610), // Rule ID 48761 // |
| 49230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 49231 | // (shl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 49232 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 49233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49239 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49240 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 49243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49244 | GIR_RootConstrainSelectedInstOperands, |
| 49245 | // GIR_Coverage, 48761, |
| 49246 | GIR_EraseRootFromParent_Done, |
| 49247 | // Label 3415: @127610 |
| 49248 | GIM_Reject, |
| 49249 | // Label 3413: @127611 |
| 49250 | GIM_Reject, |
| 49251 | // Label 3343: @127612 |
| 49252 | GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(127726), |
| 49253 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 49254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 49255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 49256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 49257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 49258 | GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(127680), // Rule ID 48716 // |
| 49259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49260 | // (shl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 49261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 49262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 49266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49268 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49269 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49273 | GIR_RootConstrainSelectedInstOperands, |
| 49274 | // GIR_Coverage, 48716, |
| 49275 | GIR_EraseRootFromParent_Done, |
| 49276 | // Label 3417: @127680 |
| 49277 | GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(127725), // Rule ID 48717 // |
| 49278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49279 | // (shl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSLL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 49280 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 49281 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49282 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M2), |
| 49285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49286 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49287 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49288 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49292 | GIR_RootConstrainSelectedInstOperands, |
| 49293 | // GIR_Coverage, 48717, |
| 49294 | GIR_EraseRootFromParent_Done, |
| 49295 | // Label 3418: @127725 |
| 49296 | GIM_Reject, |
| 49297 | // Label 3416: @127726 |
| 49298 | GIM_Reject, |
| 49299 | // Label 3344: @127727 |
| 49300 | GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(127841), |
| 49301 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 49302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 49303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49304 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49305 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49306 | GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(127795), // Rule ID 48732 // |
| 49307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49308 | // (shl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 49309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 49310 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49311 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49315 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49317 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49321 | GIR_RootConstrainSelectedInstOperands, |
| 49322 | // GIR_Coverage, 48732, |
| 49323 | GIR_EraseRootFromParent_Done, |
| 49324 | // Label 3420: @127795 |
| 49325 | GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(127840), // Rule ID 48733 // |
| 49326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49327 | // (shl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 49328 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 49329 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49330 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49334 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49335 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49336 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49340 | GIR_RootConstrainSelectedInstOperands, |
| 49341 | // GIR_Coverage, 48733, |
| 49342 | GIR_EraseRootFromParent_Done, |
| 49343 | // Label 3421: @127840 |
| 49344 | GIM_Reject, |
| 49345 | // Label 3419: @127841 |
| 49346 | GIM_Reject, |
| 49347 | // Label 3345: @127842 |
| 49348 | GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(127956), |
| 49349 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 49350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 49351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49352 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49354 | GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(127910), // Rule ID 48748 // |
| 49355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49356 | // (shl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 49357 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 49358 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49359 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49363 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49364 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49365 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49369 | GIR_RootConstrainSelectedInstOperands, |
| 49370 | // GIR_Coverage, 48748, |
| 49371 | GIR_EraseRootFromParent_Done, |
| 49372 | // Label 3423: @127910 |
| 49373 | GIM_Try, /*On fail goto*//*Label 3424*/ GIMT_Encode4(127955), // Rule ID 48749 // |
| 49374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49375 | // (shl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 49376 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 49377 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49378 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49382 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49383 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49384 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49388 | GIR_RootConstrainSelectedInstOperands, |
| 49389 | // GIR_Coverage, 48749, |
| 49390 | GIR_EraseRootFromParent_Done, |
| 49391 | // Label 3424: @127955 |
| 49392 | GIM_Reject, |
| 49393 | // Label 3422: @127956 |
| 49394 | GIM_Reject, |
| 49395 | // Label 3346: @127957 |
| 49396 | GIM_Try, /*On fail goto*//*Label 3425*/ GIMT_Encode4(128071), |
| 49397 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 49398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 49399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49400 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 49402 | GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(128025), // Rule ID 48720 // |
| 49403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49404 | // (shl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 49405 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 49406 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49407 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49411 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49412 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49413 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49417 | GIR_RootConstrainSelectedInstOperands, |
| 49418 | // GIR_Coverage, 48720, |
| 49419 | GIR_EraseRootFromParent_Done, |
| 49420 | // Label 3426: @128025 |
| 49421 | GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(128070), // Rule ID 48721 // |
| 49422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49423 | // (shl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSLL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 49424 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 49425 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M4), |
| 49429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49431 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49432 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49436 | GIR_RootConstrainSelectedInstOperands, |
| 49437 | // GIR_Coverage, 48721, |
| 49438 | GIR_EraseRootFromParent_Done, |
| 49439 | // Label 3427: @128070 |
| 49440 | GIM_Reject, |
| 49441 | // Label 3425: @128071 |
| 49442 | GIM_Reject, |
| 49443 | // Label 3347: @128072 |
| 49444 | GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(128186), |
| 49445 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 49446 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 49447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49450 | GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(128140), // Rule ID 48736 // |
| 49451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49452 | // (shl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 49453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 49454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49460 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49461 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49465 | GIR_RootConstrainSelectedInstOperands, |
| 49466 | // GIR_Coverage, 48736, |
| 49467 | GIR_EraseRootFromParent_Done, |
| 49468 | // Label 3429: @128140 |
| 49469 | GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(128185), // Rule ID 48737 // |
| 49470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49471 | // (shl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 49472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 49473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49479 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49480 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49484 | GIR_RootConstrainSelectedInstOperands, |
| 49485 | // GIR_Coverage, 48737, |
| 49486 | GIR_EraseRootFromParent_Done, |
| 49487 | // Label 3430: @128185 |
| 49488 | GIM_Reject, |
| 49489 | // Label 3428: @128186 |
| 49490 | GIM_Reject, |
| 49491 | // Label 3348: @128187 |
| 49492 | GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(128301), |
| 49493 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 49494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 49495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49496 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49497 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 49498 | GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(128255), // Rule ID 48724 // |
| 49499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49500 | // (shl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 49501 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 49502 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49503 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49507 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49508 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49509 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49513 | GIR_RootConstrainSelectedInstOperands, |
| 49514 | // GIR_Coverage, 48724, |
| 49515 | GIR_EraseRootFromParent_Done, |
| 49516 | // Label 3432: @128255 |
| 49517 | GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(128300), // Rule ID 48725 // |
| 49518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49519 | // (shl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSLL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 49520 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 49521 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49522 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49523 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSLL_VV_M8), |
| 49525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49526 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49527 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49528 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49532 | GIR_RootConstrainSelectedInstOperands, |
| 49533 | // GIR_Coverage, 48725, |
| 49534 | GIR_EraseRootFromParent_Done, |
| 49535 | // Label 3433: @128300 |
| 49536 | GIM_Reject, |
| 49537 | // Label 3431: @128301 |
| 49538 | GIM_Reject, |
| 49539 | // Label 3349: @128302 |
| 49540 | GIM_Reject, |
| 49541 | // Label 40: @128303 |
| 49542 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 3458*/ GIMT_Encode4(131409), |
| 49543 | /*GILLT_s32*//*Label 3434*/ GIMT_Encode4(128438), |
| 49544 | /*GILLT_s64*//*Label 3435*/ GIMT_Encode4(128723), GIMT_Encode4(0), |
| 49545 | /*GILLT_nxv1s8*//*Label 3436*/ GIMT_Encode4(128879), |
| 49546 | /*GILLT_nxv1s16*//*Label 3437*/ GIMT_Encode4(128994), |
| 49547 | /*GILLT_nxv1s32*//*Label 3438*/ GIMT_Encode4(129109), |
| 49548 | /*GILLT_nxv1s64*//*Label 3439*/ GIMT_Encode4(129224), GIMT_Encode4(0), |
| 49549 | /*GILLT_nxv2s8*//*Label 3440*/ GIMT_Encode4(129339), |
| 49550 | /*GILLT_nxv2s16*//*Label 3441*/ GIMT_Encode4(129454), |
| 49551 | /*GILLT_nxv2s32*//*Label 3442*/ GIMT_Encode4(129569), |
| 49552 | /*GILLT_nxv2s64*//*Label 3443*/ GIMT_Encode4(129684), GIMT_Encode4(0), |
| 49553 | /*GILLT_nxv4s8*//*Label 3444*/ GIMT_Encode4(129799), |
| 49554 | /*GILLT_nxv4s16*//*Label 3445*/ GIMT_Encode4(129914), |
| 49555 | /*GILLT_nxv4s32*//*Label 3446*/ GIMT_Encode4(130029), |
| 49556 | /*GILLT_nxv4s64*//*Label 3447*/ GIMT_Encode4(130144), GIMT_Encode4(0), |
| 49557 | /*GILLT_nxv8s8*//*Label 3448*/ GIMT_Encode4(130259), |
| 49558 | /*GILLT_nxv8s16*//*Label 3449*/ GIMT_Encode4(130374), |
| 49559 | /*GILLT_nxv8s32*//*Label 3450*/ GIMT_Encode4(130489), |
| 49560 | /*GILLT_nxv8s64*//*Label 3451*/ GIMT_Encode4(130604), GIMT_Encode4(0), |
| 49561 | /*GILLT_nxv16s8*//*Label 3452*/ GIMT_Encode4(130719), |
| 49562 | /*GILLT_nxv16s16*//*Label 3453*/ GIMT_Encode4(130834), |
| 49563 | /*GILLT_nxv16s32*//*Label 3454*/ GIMT_Encode4(130949), GIMT_Encode4(0), |
| 49564 | /*GILLT_nxv32s8*//*Label 3455*/ GIMT_Encode4(131064), |
| 49565 | /*GILLT_nxv32s16*//*Label 3456*/ GIMT_Encode4(131179), GIMT_Encode4(0), |
| 49566 | /*GILLT_nxv64s8*//*Label 3457*/ GIMT_Encode4(131294), |
| 49567 | // Label 3434: @128438 |
| 49568 | GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(128722), |
| 49569 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 49570 | GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(128491), // Rule ID 87 // |
| 49571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 49572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49574 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49575 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49576 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 49577 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 49578 | // MIs[1] Operand 1 |
| 49579 | // No operand predicates |
| 49580 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49581 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 49582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 49583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49584 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49585 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 49586 | GIR_RootConstrainSelectedInstOperands, |
| 49587 | // GIR_Coverage, 87, |
| 49588 | GIR_EraseRootFromParent_Done, |
| 49589 | // Label 3460: @128491 |
| 49590 | GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(128536), // Rule ID 316 // |
| 49591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 49592 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49594 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49595 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49596 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 49597 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 49598 | // MIs[1] Operand 1 |
| 49599 | // No operand predicates |
| 49600 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49601 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) => (SRLIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) |
| 49602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 49603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49604 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49605 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 49606 | GIR_RootConstrainSelectedInstOperands, |
| 49607 | // GIR_Coverage, 316, |
| 49608 | GIR_EraseRootFromParent_Done, |
| 49609 | // Label 3461: @128536 |
| 49610 | GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(128581), // Rule ID 317 // |
| 49611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 49612 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49614 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49615 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49616 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 49617 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 49618 | // MIs[1] Operand 1 |
| 49619 | // No operand predicates |
| 49620 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49621 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (SRLIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 49622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 49623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49624 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49625 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 49626 | GIR_RootConstrainSelectedInstOperands, |
| 49627 | // GIR_Coverage, 317, |
| 49628 | GIR_EraseRootFromParent_Done, |
| 49629 | // Label 3462: @128581 |
| 49630 | GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(128621), // Rule ID 100 // |
| 49631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 49632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49634 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 49636 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 49637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRL), |
| 49638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49639 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 49641 | GIR_RootConstrainSelectedInstOperands, |
| 49642 | // GIR_Coverage, 100, |
| 49643 | GIR_EraseRootFromParent_Done, |
| 49644 | // Label 3463: @128621 |
| 49645 | GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(128661), // Rule ID 308 // |
| 49646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 49647 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49649 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMask32), |
| 49651 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMask32:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (SRLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 49652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLW), |
| 49653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49654 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 49656 | GIR_RootConstrainSelectedInstOperands, |
| 49657 | // GIR_Coverage, 308, |
| 49658 | GIR_EraseRootFromParent_Done, |
| 49659 | // Label 3464: @128661 |
| 49660 | GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(128691), // Rule ID 65049 // |
| 49661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 49662 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49664 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49665 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49666 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 49667 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SRLW), |
| 49668 | GIR_RootConstrainSelectedInstOperands, |
| 49669 | // GIR_Coverage, 65049, |
| 49670 | GIR_Done, |
| 49671 | // Label 3465: @128691 |
| 49672 | GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(128721), // Rule ID 65050 // |
| 49673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 49674 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 49675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49676 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49677 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49678 | // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 49679 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SRLW), |
| 49680 | GIR_RootConstrainSelectedInstOperands, |
| 49681 | // GIR_Coverage, 65050, |
| 49682 | GIR_Done, |
| 49683 | // Label 3466: @128721 |
| 49684 | GIM_Reject, |
| 49685 | // Label 3459: @128722 |
| 49686 | GIM_Reject, |
| 49687 | // Label 3435: @128723 |
| 49688 | GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(128878), |
| 49689 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 49690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 49691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49692 | GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(128806), // Rule ID 248 // |
| 49693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 49694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 49695 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 49696 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 49697 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 49698 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49699 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), |
| 49700 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 49701 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 49702 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 49703 | // MIs[2] Operand 1 |
| 49704 | // No operand predicates |
| 49705 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 49706 | // (srl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) => (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) |
| 49707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), |
| 49708 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 49710 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt |
| 49711 | GIR_RootConstrainSelectedInstOperands, |
| 49712 | // GIR_Coverage, 248, |
| 49713 | GIR_EraseRootFromParent_Done, |
| 49714 | // Label 3468: @128806 |
| 49715 | GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(128844), // Rule ID 86 // |
| 49716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 49717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49718 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 49719 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 49720 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 49721 | // MIs[1] Operand 1 |
| 49722 | // No operand predicates |
| 49723 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 49724 | // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) => (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 49725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), |
| 49726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49727 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49728 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 49729 | GIR_RootConstrainSelectedInstOperands, |
| 49730 | // GIR_Coverage, 86, |
| 49731 | GIR_EraseRootFromParent_Done, |
| 49732 | // Label 3469: @128844 |
| 49733 | GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(128877), // Rule ID 99 // |
| 49734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 49735 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 49736 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 49737 | // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 49738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRL), |
| 49739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49740 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 49742 | GIR_RootConstrainSelectedInstOperands, |
| 49743 | // GIR_Coverage, 99, |
| 49744 | GIR_EraseRootFromParent_Done, |
| 49745 | // Label 3470: @128877 |
| 49746 | GIM_Reject, |
| 49747 | // Label 3467: @128878 |
| 49748 | GIM_Reject, |
| 49749 | // Label 3436: @128879 |
| 49750 | GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(128993), |
| 49751 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 49752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 49753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49754 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49755 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49756 | GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(128947), // Rule ID 48808 // |
| 49757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49758 | // (srl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSRL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 49759 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 49760 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49761 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF8), |
| 49764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49765 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49767 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49771 | GIR_RootConstrainSelectedInstOperands, |
| 49772 | // GIR_Coverage, 48808, |
| 49773 | GIR_EraseRootFromParent_Done, |
| 49774 | // Label 3472: @128947 |
| 49775 | GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(128992), // Rule ID 48809 // |
| 49776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49777 | // (srl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSRL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 49778 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 49779 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49780 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49781 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF8), |
| 49783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49784 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49785 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49786 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49790 | GIR_RootConstrainSelectedInstOperands, |
| 49791 | // GIR_Coverage, 48809, |
| 49792 | GIR_EraseRootFromParent_Done, |
| 49793 | // Label 3473: @128992 |
| 49794 | GIM_Reject, |
| 49795 | // Label 3471: @128993 |
| 49796 | GIM_Reject, |
| 49797 | // Label 3437: @128994 |
| 49798 | GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(129108), |
| 49799 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 49800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 49801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49802 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49804 | GIM_Try, /*On fail goto*//*Label 3475*/ GIMT_Encode4(129062), // Rule ID 48820 // |
| 49805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49806 | // (srl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSRL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 49807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 49808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF4), |
| 49812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49815 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49819 | GIR_RootConstrainSelectedInstOperands, |
| 49820 | // GIR_Coverage, 48820, |
| 49821 | GIR_EraseRootFromParent_Done, |
| 49822 | // Label 3475: @129062 |
| 49823 | GIM_Try, /*On fail goto*//*Label 3476*/ GIMT_Encode4(129107), // Rule ID 48821 // |
| 49824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49825 | // (srl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSRL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 49826 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 49827 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49828 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF4), |
| 49831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49832 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49833 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49834 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 49837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49838 | GIR_RootConstrainSelectedInstOperands, |
| 49839 | // GIR_Coverage, 48821, |
| 49840 | GIR_EraseRootFromParent_Done, |
| 49841 | // Label 3476: @129107 |
| 49842 | GIM_Reject, |
| 49843 | // Label 3474: @129108 |
| 49844 | GIM_Reject, |
| 49845 | // Label 3438: @129109 |
| 49846 | GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(129223), |
| 49847 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 49848 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 49849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49851 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49852 | GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(129177), // Rule ID 48828 // |
| 49853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49854 | // (srl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSRL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 49855 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 49856 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49857 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF2), |
| 49860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49861 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49862 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49863 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49867 | GIR_RootConstrainSelectedInstOperands, |
| 49868 | // GIR_Coverage, 48828, |
| 49869 | GIR_EraseRootFromParent_Done, |
| 49870 | // Label 3478: @129177 |
| 49871 | GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(129222), // Rule ID 48829 // |
| 49872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49873 | // (srl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSRL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 49874 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 49875 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49876 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF2), |
| 49879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49881 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49882 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 49885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49886 | GIR_RootConstrainSelectedInstOperands, |
| 49887 | // GIR_Coverage, 48829, |
| 49888 | GIR_EraseRootFromParent_Done, |
| 49889 | // Label 3479: @129222 |
| 49890 | GIM_Reject, |
| 49891 | // Label 3477: @129223 |
| 49892 | GIM_Reject, |
| 49893 | // Label 3439: @129224 |
| 49894 | GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(129338), |
| 49895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 49896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 49897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49898 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49899 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49900 | GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(129292), // Rule ID 48844 // |
| 49901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 49902 | // (srl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 49903 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 49904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 49908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49909 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49910 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49911 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 49914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49915 | GIR_RootConstrainSelectedInstOperands, |
| 49916 | // GIR_Coverage, 48844, |
| 49917 | GIR_EraseRootFromParent_Done, |
| 49918 | // Label 3481: @129292 |
| 49919 | GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(129337), // Rule ID 48845 // |
| 49920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 49921 | // (srl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 49922 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 49923 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49924 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 49927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49928 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49929 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49930 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 49933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49934 | GIR_RootConstrainSelectedInstOperands, |
| 49935 | // GIR_Coverage, 48845, |
| 49936 | GIR_EraseRootFromParent_Done, |
| 49937 | // Label 3482: @129337 |
| 49938 | GIM_Reject, |
| 49939 | // Label 3480: @129338 |
| 49940 | GIM_Reject, |
| 49941 | // Label 3440: @129339 |
| 49942 | GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(129453), |
| 49943 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 49944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 49945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49948 | GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(129407), // Rule ID 48812 // |
| 49949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49950 | // (srl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSRL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 49951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 49952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49953 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF4), |
| 49956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49957 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49958 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49959 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49963 | GIR_RootConstrainSelectedInstOperands, |
| 49964 | // GIR_Coverage, 48812, |
| 49965 | GIR_EraseRootFromParent_Done, |
| 49966 | // Label 3484: @129407 |
| 49967 | GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(129452), // Rule ID 48813 // |
| 49968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 49969 | // (srl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSRL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 49970 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 49971 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 49972 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49973 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 49974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF4), |
| 49975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 49976 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49977 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 49978 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 49979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 49980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 49982 | GIR_RootConstrainSelectedInstOperands, |
| 49983 | // GIR_Coverage, 48813, |
| 49984 | GIR_EraseRootFromParent_Done, |
| 49985 | // Label 3485: @129452 |
| 49986 | GIM_Reject, |
| 49987 | // Label 3483: @129453 |
| 49988 | GIM_Reject, |
| 49989 | // Label 3441: @129454 |
| 49990 | GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(129568), |
| 49991 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 49992 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 49993 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 49996 | GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(129522), // Rule ID 48824 // |
| 49997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 49998 | // (srl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSRL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 49999 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 50000 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF2), |
| 50004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50006 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50007 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50011 | GIR_RootConstrainSelectedInstOperands, |
| 50012 | // GIR_Coverage, 48824, |
| 50013 | GIR_EraseRootFromParent_Done, |
| 50014 | // Label 3487: @129522 |
| 50015 | GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(129567), // Rule ID 48825 // |
| 50016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50017 | // (srl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSRL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 50018 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 50019 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50020 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50021 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF2), |
| 50023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50024 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50025 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50026 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50030 | GIR_RootConstrainSelectedInstOperands, |
| 50031 | // GIR_Coverage, 48825, |
| 50032 | GIR_EraseRootFromParent_Done, |
| 50033 | // Label 3488: @129567 |
| 50034 | GIM_Reject, |
| 50035 | // Label 3486: @129568 |
| 50036 | GIM_Reject, |
| 50037 | // Label 3442: @129569 |
| 50038 | GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(129683), |
| 50039 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 50040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 50041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50042 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50044 | GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(129637), // Rule ID 48840 // |
| 50045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50046 | // (srl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 50047 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 50048 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50049 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 50052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50053 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50054 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50055 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50059 | GIR_RootConstrainSelectedInstOperands, |
| 50060 | // GIR_Coverage, 48840, |
| 50061 | GIR_EraseRootFromParent_Done, |
| 50062 | // Label 3490: @129637 |
| 50063 | GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(129682), // Rule ID 48841 // |
| 50064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50065 | // (srl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 50066 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 50067 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50068 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50069 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 50071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50072 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50073 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50074 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50078 | GIR_RootConstrainSelectedInstOperands, |
| 50079 | // GIR_Coverage, 48841, |
| 50080 | GIR_EraseRootFromParent_Done, |
| 50081 | // Label 3491: @129682 |
| 50082 | GIM_Reject, |
| 50083 | // Label 3489: @129683 |
| 50084 | GIM_Reject, |
| 50085 | // Label 3443: @129684 |
| 50086 | GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(129798), |
| 50087 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 50088 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 50089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50090 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50091 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50092 | GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(129752), // Rule ID 48884 // |
| 50093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 50094 | // (srl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 50095 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 50096 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50097 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50101 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50102 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50103 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 50106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50107 | GIR_RootConstrainSelectedInstOperands, |
| 50108 | // GIR_Coverage, 48884, |
| 50109 | GIR_EraseRootFromParent_Done, |
| 50110 | // Label 3493: @129752 |
| 50111 | GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(129797), // Rule ID 48885 // |
| 50112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 50113 | // (srl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 50114 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 50115 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50116 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50120 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50121 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50122 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 50125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50126 | GIR_RootConstrainSelectedInstOperands, |
| 50127 | // GIR_Coverage, 48885, |
| 50128 | GIR_EraseRootFromParent_Done, |
| 50129 | // Label 3494: @129797 |
| 50130 | GIM_Reject, |
| 50131 | // Label 3492: @129798 |
| 50132 | GIM_Reject, |
| 50133 | // Label 3444: @129799 |
| 50134 | GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(129913), |
| 50135 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 50136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 50137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50138 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50139 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50140 | GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(129867), // Rule ID 48816 // |
| 50141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50142 | // (srl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSRL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 50143 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 50144 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50145 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF2), |
| 50148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50149 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50150 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50151 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50155 | GIR_RootConstrainSelectedInstOperands, |
| 50156 | // GIR_Coverage, 48816, |
| 50157 | GIR_EraseRootFromParent_Done, |
| 50158 | // Label 3496: @129867 |
| 50159 | GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(129912), // Rule ID 48817 // |
| 50160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50161 | // (srl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSRL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 50162 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 50163 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50164 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_MF2), |
| 50167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50168 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50169 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50170 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50174 | GIR_RootConstrainSelectedInstOperands, |
| 50175 | // GIR_Coverage, 48817, |
| 50176 | GIR_EraseRootFromParent_Done, |
| 50177 | // Label 3497: @129912 |
| 50178 | GIM_Reject, |
| 50179 | // Label 3495: @129913 |
| 50180 | GIM_Reject, |
| 50181 | // Label 3445: @129914 |
| 50182 | GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(130028), |
| 50183 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 50184 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 50185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50186 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50187 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50188 | GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(129982), // Rule ID 48836 // |
| 50189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50190 | // (srl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 50191 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 50192 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50193 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 50196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50198 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50199 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50203 | GIR_RootConstrainSelectedInstOperands, |
| 50204 | // GIR_Coverage, 48836, |
| 50205 | GIR_EraseRootFromParent_Done, |
| 50206 | // Label 3499: @129982 |
| 50207 | GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(130027), // Rule ID 48837 // |
| 50208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50209 | // (srl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 50210 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 50211 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50212 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 50215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50216 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50217 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50218 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50222 | GIR_RootConstrainSelectedInstOperands, |
| 50223 | // GIR_Coverage, 48837, |
| 50224 | GIR_EraseRootFromParent_Done, |
| 50225 | // Label 3500: @130027 |
| 50226 | GIM_Reject, |
| 50227 | // Label 3498: @130028 |
| 50228 | GIM_Reject, |
| 50229 | // Label 3446: @130029 |
| 50230 | GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(130143), |
| 50231 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 50232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 50233 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50234 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50235 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50236 | GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(130097), // Rule ID 48872 // |
| 50237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50238 | // (srl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 50239 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 50240 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50241 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50246 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50247 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50251 | GIR_RootConstrainSelectedInstOperands, |
| 50252 | // GIR_Coverage, 48872, |
| 50253 | GIR_EraseRootFromParent_Done, |
| 50254 | // Label 3502: @130097 |
| 50255 | GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(130142), // Rule ID 48873 // |
| 50256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50257 | // (srl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 50258 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 50259 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50260 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50261 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50264 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50265 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50266 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50270 | GIR_RootConstrainSelectedInstOperands, |
| 50271 | // GIR_Coverage, 48873, |
| 50272 | GIR_EraseRootFromParent_Done, |
| 50273 | // Label 3503: @130142 |
| 50274 | GIM_Reject, |
| 50275 | // Label 3501: @130143 |
| 50276 | GIM_Reject, |
| 50277 | // Label 3447: @130144 |
| 50278 | GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(130258), |
| 50279 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 50280 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 50281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50282 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50283 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50284 | GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(130212), // Rule ID 48888 // |
| 50285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 50286 | // (srl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 50287 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 50288 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50289 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50290 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50293 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50294 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50295 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 50298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50299 | GIR_RootConstrainSelectedInstOperands, |
| 50300 | // GIR_Coverage, 48888, |
| 50301 | GIR_EraseRootFromParent_Done, |
| 50302 | // Label 3505: @130212 |
| 50303 | GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(130257), // Rule ID 48889 // |
| 50304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 50305 | // (srl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 50306 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 50307 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50308 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50309 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50312 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50313 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50314 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 50317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50318 | GIR_RootConstrainSelectedInstOperands, |
| 50319 | // GIR_Coverage, 48889, |
| 50320 | GIR_EraseRootFromParent_Done, |
| 50321 | // Label 3506: @130257 |
| 50322 | GIM_Reject, |
| 50323 | // Label 3504: @130258 |
| 50324 | GIM_Reject, |
| 50325 | // Label 3448: @130259 |
| 50326 | GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(130373), |
| 50327 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 50328 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 50329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50330 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50331 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 50332 | GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(130327), // Rule ID 48832 // |
| 50333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50334 | // (srl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 50335 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 50336 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50337 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 50340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50342 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50343 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50347 | GIR_RootConstrainSelectedInstOperands, |
| 50348 | // GIR_Coverage, 48832, |
| 50349 | GIR_EraseRootFromParent_Done, |
| 50350 | // Label 3508: @130327 |
| 50351 | GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(130372), // Rule ID 48833 // |
| 50352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50353 | // (srl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSRL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 50354 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 50355 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50356 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M1), |
| 50359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50360 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50361 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50362 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50366 | GIR_RootConstrainSelectedInstOperands, |
| 50367 | // GIR_Coverage, 48833, |
| 50368 | GIR_EraseRootFromParent_Done, |
| 50369 | // Label 3509: @130372 |
| 50370 | GIM_Reject, |
| 50371 | // Label 3507: @130373 |
| 50372 | GIM_Reject, |
| 50373 | // Label 3449: @130374 |
| 50374 | GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(130488), |
| 50375 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 50376 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 50377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50378 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50379 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50380 | GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(130442), // Rule ID 48860 // |
| 50381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50382 | // (srl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 50383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 50384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50390 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50391 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50395 | GIR_RootConstrainSelectedInstOperands, |
| 50396 | // GIR_Coverage, 48860, |
| 50397 | GIR_EraseRootFromParent_Done, |
| 50398 | // Label 3511: @130442 |
| 50399 | GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(130487), // Rule ID 48861 // |
| 50400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50401 | // (srl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 50402 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 50403 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50404 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50408 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50409 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50410 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50414 | GIR_RootConstrainSelectedInstOperands, |
| 50415 | // GIR_Coverage, 48861, |
| 50416 | GIR_EraseRootFromParent_Done, |
| 50417 | // Label 3512: @130487 |
| 50418 | GIM_Reject, |
| 50419 | // Label 3510: @130488 |
| 50420 | GIM_Reject, |
| 50421 | // Label 3450: @130489 |
| 50422 | GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(130603), |
| 50423 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 50424 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 50425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50426 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50427 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50428 | GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(130557), // Rule ID 48876 // |
| 50429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50430 | // (srl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 50431 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 50432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50433 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50438 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50439 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50443 | GIR_RootConstrainSelectedInstOperands, |
| 50444 | // GIR_Coverage, 48876, |
| 50445 | GIR_EraseRootFromParent_Done, |
| 50446 | // Label 3514: @130557 |
| 50447 | GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(130602), // Rule ID 48877 // |
| 50448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50449 | // (srl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 50450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 50451 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50452 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50456 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50457 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50458 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50462 | GIR_RootConstrainSelectedInstOperands, |
| 50463 | // GIR_Coverage, 48877, |
| 50464 | GIR_EraseRootFromParent_Done, |
| 50465 | // Label 3515: @130602 |
| 50466 | GIM_Reject, |
| 50467 | // Label 3513: @130603 |
| 50468 | GIM_Reject, |
| 50469 | // Label 3451: @130604 |
| 50470 | GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(130718), |
| 50471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 50472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 50473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50474 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50475 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50476 | GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(130672), // Rule ID 48892 // |
| 50477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 50478 | // (srl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 50479 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 50480 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50481 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50485 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50486 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50487 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 50490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50491 | GIR_RootConstrainSelectedInstOperands, |
| 50492 | // GIR_Coverage, 48892, |
| 50493 | GIR_EraseRootFromParent_Done, |
| 50494 | // Label 3517: @130672 |
| 50495 | GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(130717), // Rule ID 48893 // |
| 50496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 50497 | // (srl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 50498 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 50499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50504 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50505 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 50509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50510 | GIR_RootConstrainSelectedInstOperands, |
| 50511 | // GIR_Coverage, 48893, |
| 50512 | GIR_EraseRootFromParent_Done, |
| 50513 | // Label 3518: @130717 |
| 50514 | GIM_Reject, |
| 50515 | // Label 3516: @130718 |
| 50516 | GIM_Reject, |
| 50517 | // Label 3452: @130719 |
| 50518 | GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(130833), |
| 50519 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 50520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 50521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 50524 | GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(130787), // Rule ID 48848 // |
| 50525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50526 | // (srl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 50527 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 50528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50529 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50534 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50535 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50539 | GIR_RootConstrainSelectedInstOperands, |
| 50540 | // GIR_Coverage, 48848, |
| 50541 | GIR_EraseRootFromParent_Done, |
| 50542 | // Label 3520: @130787 |
| 50543 | GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(130832), // Rule ID 48849 // |
| 50544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50545 | // (srl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSRL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 50546 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 50547 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50548 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M2), |
| 50551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50552 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50553 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50554 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50558 | GIR_RootConstrainSelectedInstOperands, |
| 50559 | // GIR_Coverage, 48849, |
| 50560 | GIR_EraseRootFromParent_Done, |
| 50561 | // Label 3521: @130832 |
| 50562 | GIM_Reject, |
| 50563 | // Label 3519: @130833 |
| 50564 | GIM_Reject, |
| 50565 | // Label 3453: @130834 |
| 50566 | GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(130948), |
| 50567 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 50568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 50569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50570 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50571 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50572 | GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(130902), // Rule ID 48864 // |
| 50573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50574 | // (srl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 50575 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 50576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50577 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50581 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50582 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50583 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50587 | GIR_RootConstrainSelectedInstOperands, |
| 50588 | // GIR_Coverage, 48864, |
| 50589 | GIR_EraseRootFromParent_Done, |
| 50590 | // Label 3523: @130902 |
| 50591 | GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(130947), // Rule ID 48865 // |
| 50592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50593 | // (srl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 50594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 50595 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50596 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50600 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50601 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50602 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50606 | GIR_RootConstrainSelectedInstOperands, |
| 50607 | // GIR_Coverage, 48865, |
| 50608 | GIR_EraseRootFromParent_Done, |
| 50609 | // Label 3524: @130947 |
| 50610 | GIM_Reject, |
| 50611 | // Label 3522: @130948 |
| 50612 | GIM_Reject, |
| 50613 | // Label 3454: @130949 |
| 50614 | GIM_Try, /*On fail goto*//*Label 3525*/ GIMT_Encode4(131063), |
| 50615 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 50616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 50617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50619 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50620 | GIM_Try, /*On fail goto*//*Label 3526*/ GIMT_Encode4(131017), // Rule ID 48880 // |
| 50621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50622 | // (srl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 50623 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 50624 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50625 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50629 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50630 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50631 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50635 | GIR_RootConstrainSelectedInstOperands, |
| 50636 | // GIR_Coverage, 48880, |
| 50637 | GIR_EraseRootFromParent_Done, |
| 50638 | // Label 3526: @131017 |
| 50639 | GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(131062), // Rule ID 48881 // |
| 50640 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50641 | // (srl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 50642 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 50643 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50644 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50648 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50649 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50650 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 50653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50654 | GIR_RootConstrainSelectedInstOperands, |
| 50655 | // GIR_Coverage, 48881, |
| 50656 | GIR_EraseRootFromParent_Done, |
| 50657 | // Label 3527: @131062 |
| 50658 | GIM_Reject, |
| 50659 | // Label 3525: @131063 |
| 50660 | GIM_Reject, |
| 50661 | // Label 3455: @131064 |
| 50662 | GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(131178), |
| 50663 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 50664 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 50665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50666 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50667 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 50668 | GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(131132), // Rule ID 48852 // |
| 50669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50670 | // (srl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 50671 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 50672 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50673 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50677 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50678 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50679 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50683 | GIR_RootConstrainSelectedInstOperands, |
| 50684 | // GIR_Coverage, 48852, |
| 50685 | GIR_EraseRootFromParent_Done, |
| 50686 | // Label 3529: @131132 |
| 50687 | GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(131177), // Rule ID 48853 // |
| 50688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50689 | // (srl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSRL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 50690 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 50691 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50692 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50693 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M4), |
| 50695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50696 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50697 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50698 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50702 | GIR_RootConstrainSelectedInstOperands, |
| 50703 | // GIR_Coverage, 48853, |
| 50704 | GIR_EraseRootFromParent_Done, |
| 50705 | // Label 3530: @131177 |
| 50706 | GIM_Reject, |
| 50707 | // Label 3528: @131178 |
| 50708 | GIM_Reject, |
| 50709 | // Label 3456: @131179 |
| 50710 | GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(131293), |
| 50711 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 50712 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 50713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50715 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50716 | GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(131247), // Rule ID 48868 // |
| 50717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50718 | // (srl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 50719 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 50720 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50721 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50722 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50725 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50726 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50727 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50731 | GIR_RootConstrainSelectedInstOperands, |
| 50732 | // GIR_Coverage, 48868, |
| 50733 | GIR_EraseRootFromParent_Done, |
| 50734 | // Label 3532: @131247 |
| 50735 | GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(131292), // Rule ID 48869 // |
| 50736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50737 | // (srl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 50738 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 50739 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50740 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50741 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50744 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50745 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50746 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 50749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50750 | GIR_RootConstrainSelectedInstOperands, |
| 50751 | // GIR_Coverage, 48869, |
| 50752 | GIR_EraseRootFromParent_Done, |
| 50753 | // Label 3533: @131292 |
| 50754 | GIM_Reject, |
| 50755 | // Label 3531: @131293 |
| 50756 | GIM_Reject, |
| 50757 | // Label 3457: @131294 |
| 50758 | GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(131408), |
| 50759 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 50760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 50761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50763 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 50764 | GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(131362), // Rule ID 48856 // |
| 50765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 50766 | // (srl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 50767 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 50768 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50769 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50770 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50773 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50774 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50775 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50779 | GIR_RootConstrainSelectedInstOperands, |
| 50780 | // GIR_Coverage, 48856, |
| 50781 | GIR_EraseRootFromParent_Done, |
| 50782 | // Label 3535: @131362 |
| 50783 | GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(131407), // Rule ID 48857 // |
| 50784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 50785 | // (srl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSRL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 50786 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 50787 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 50788 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRL_VV_M8), |
| 50791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50792 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50793 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50794 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 50795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 50796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 50798 | GIR_RootConstrainSelectedInstOperands, |
| 50799 | // GIR_Coverage, 48857, |
| 50800 | GIR_EraseRootFromParent_Done, |
| 50801 | // Label 3536: @131407 |
| 50802 | GIM_Reject, |
| 50803 | // Label 3534: @131408 |
| 50804 | GIM_Reject, |
| 50805 | // Label 3458: @131409 |
| 50806 | GIM_Reject, |
| 50807 | // Label 41: @131410 |
| 50808 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 3561*/ GIMT_Encode4(134485), |
| 50809 | /*GILLT_s32*//*Label 3537*/ GIMT_Encode4(131545), |
| 50810 | /*GILLT_s64*//*Label 3538*/ GIMT_Encode4(131830), GIMT_Encode4(0), |
| 50811 | /*GILLT_nxv1s8*//*Label 3539*/ GIMT_Encode4(131955), |
| 50812 | /*GILLT_nxv1s16*//*Label 3540*/ GIMT_Encode4(132070), |
| 50813 | /*GILLT_nxv1s32*//*Label 3541*/ GIMT_Encode4(132185), |
| 50814 | /*GILLT_nxv1s64*//*Label 3542*/ GIMT_Encode4(132300), GIMT_Encode4(0), |
| 50815 | /*GILLT_nxv2s8*//*Label 3543*/ GIMT_Encode4(132415), |
| 50816 | /*GILLT_nxv2s16*//*Label 3544*/ GIMT_Encode4(132530), |
| 50817 | /*GILLT_nxv2s32*//*Label 3545*/ GIMT_Encode4(132645), |
| 50818 | /*GILLT_nxv2s64*//*Label 3546*/ GIMT_Encode4(132760), GIMT_Encode4(0), |
| 50819 | /*GILLT_nxv4s8*//*Label 3547*/ GIMT_Encode4(132875), |
| 50820 | /*GILLT_nxv4s16*//*Label 3548*/ GIMT_Encode4(132990), |
| 50821 | /*GILLT_nxv4s32*//*Label 3549*/ GIMT_Encode4(133105), |
| 50822 | /*GILLT_nxv4s64*//*Label 3550*/ GIMT_Encode4(133220), GIMT_Encode4(0), |
| 50823 | /*GILLT_nxv8s8*//*Label 3551*/ GIMT_Encode4(133335), |
| 50824 | /*GILLT_nxv8s16*//*Label 3552*/ GIMT_Encode4(133450), |
| 50825 | /*GILLT_nxv8s32*//*Label 3553*/ GIMT_Encode4(133565), |
| 50826 | /*GILLT_nxv8s64*//*Label 3554*/ GIMT_Encode4(133680), GIMT_Encode4(0), |
| 50827 | /*GILLT_nxv16s8*//*Label 3555*/ GIMT_Encode4(133795), |
| 50828 | /*GILLT_nxv16s16*//*Label 3556*/ GIMT_Encode4(133910), |
| 50829 | /*GILLT_nxv16s32*//*Label 3557*/ GIMT_Encode4(134025), GIMT_Encode4(0), |
| 50830 | /*GILLT_nxv32s8*//*Label 3558*/ GIMT_Encode4(134140), |
| 50831 | /*GILLT_nxv32s16*//*Label 3559*/ GIMT_Encode4(134255), GIMT_Encode4(0), |
| 50832 | /*GILLT_nxv64s8*//*Label 3560*/ GIMT_Encode4(134370), |
| 50833 | // Label 3537: @131545 |
| 50834 | GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(131829), |
| 50835 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 50836 | GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(131598), // Rule ID 89 // |
| 50837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 50838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 50839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50840 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50841 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50842 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 50843 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 50844 | // MIs[1] Operand 1 |
| 50845 | // No operand predicates |
| 50846 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50847 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) => (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 50848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRAI), |
| 50849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50850 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50851 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 50852 | GIR_RootConstrainSelectedInstOperands, |
| 50853 | // GIR_Coverage, 89, |
| 50854 | GIR_EraseRootFromParent_Done, |
| 50855 | // Label 3563: @131598 |
| 50856 | GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(131643), // Rule ID 318 // |
| 50857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 50858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 50859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50860 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50861 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50862 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 50863 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 50864 | // MIs[1] Operand 1 |
| 50865 | // No operand predicates |
| 50866 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50867 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) => (SRAIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) |
| 50868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRAIW), |
| 50869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50870 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50871 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 50872 | GIR_RootConstrainSelectedInstOperands, |
| 50873 | // GIR_Coverage, 318, |
| 50874 | GIR_EraseRootFromParent_Done, |
| 50875 | // Label 3564: @131643 |
| 50876 | GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(131688), // Rule ID 319 // |
| 50877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 50878 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 50879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50880 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50882 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 50883 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 50884 | // MIs[1] Operand 1 |
| 50885 | // No operand predicates |
| 50886 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50887 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (SRAIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 50888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRAIW), |
| 50889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50890 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50891 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 50892 | GIR_RootConstrainSelectedInstOperands, |
| 50893 | // GIR_Coverage, 319, |
| 50894 | GIR_EraseRootFromParent_Done, |
| 50895 | // Label 3565: @131688 |
| 50896 | GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(131728), // Rule ID 102 // |
| 50897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 50898 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 50899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50901 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 50902 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 50903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRA), |
| 50904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50905 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 50907 | GIR_RootConstrainSelectedInstOperands, |
| 50908 | // GIR_Coverage, 102, |
| 50909 | GIR_EraseRootFromParent_Done, |
| 50910 | // Label 3566: @131728 |
| 50911 | GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(131768), // Rule ID 309 // |
| 50912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 50913 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 50914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50915 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50916 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMask32), |
| 50917 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMask32:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (SRAW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 50918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRAW), |
| 50919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50920 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 50922 | GIR_RootConstrainSelectedInstOperands, |
| 50923 | // GIR_Coverage, 309, |
| 50924 | GIR_EraseRootFromParent_Done, |
| 50925 | // Label 3567: @131768 |
| 50926 | GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(131798), // Rule ID 65047 // |
| 50927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), |
| 50928 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 50929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50930 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50931 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50932 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRAW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 50933 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SRAW), |
| 50934 | GIR_RootConstrainSelectedInstOperands, |
| 50935 | // GIR_Coverage, 65047, |
| 50936 | GIR_Done, |
| 50937 | // Label 3568: @131798 |
| 50938 | GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(131828), // Rule ID 65048 // |
| 50939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), |
| 50940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 50941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50942 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50943 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50944 | // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRAW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 50945 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SRAW), |
| 50946 | GIR_RootConstrainSelectedInstOperands, |
| 50947 | // GIR_Coverage, 65048, |
| 50948 | GIR_Done, |
| 50949 | // Label 3569: @131828 |
| 50950 | GIM_Reject, |
| 50951 | // Label 3562: @131829 |
| 50952 | GIM_Reject, |
| 50953 | // Label 3538: @131830 |
| 50954 | GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(131954), |
| 50955 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 50956 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 50957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50958 | GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(131882), // Rule ID 63033 // |
| 50959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_IsRV64_HwMode0), |
| 50960 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50961 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 50962 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50963 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 32, |
| 50964 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50965 | // (sra:{ *:[i64] } (bswap:{ *:[i64] } i64:{ *:[i64] }:$rs1), 32:{ *:[i64] }) => (TH_REVW:{ *:[i64] } i64:{ *:[i64] }:$rs1) |
| 50966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_REVW), |
| 50967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 50969 | GIR_RootConstrainSelectedInstOperands, |
| 50970 | // GIR_Coverage, 63033, |
| 50971 | GIR_EraseRootFromParent_Done, |
| 50972 | // Label 3571: @131882 |
| 50973 | GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(131920), // Rule ID 88 // |
| 50974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 50975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 50978 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 50979 | // MIs[1] Operand 1 |
| 50980 | // No operand predicates |
| 50981 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 50982 | // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) => (SRAI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 50983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRAI), |
| 50984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50985 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50986 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 50987 | GIR_RootConstrainSelectedInstOperands, |
| 50988 | // GIR_Coverage, 88, |
| 50989 | GIR_EraseRootFromParent_Done, |
| 50990 | // Label 3572: @131920 |
| 50991 | GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(131953), // Rule ID 101 // |
| 50992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 50993 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 50994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 50995 | // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 50996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRA), |
| 50997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 50998 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 50999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 51000 | GIR_RootConstrainSelectedInstOperands, |
| 51001 | // GIR_Coverage, 101, |
| 51002 | GIR_EraseRootFromParent_Done, |
| 51003 | // Label 3573: @131953 |
| 51004 | GIM_Reject, |
| 51005 | // Label 3570: @131954 |
| 51006 | GIM_Reject, |
| 51007 | // Label 3539: @131955 |
| 51008 | GIM_Try, /*On fail goto*//*Label 3574*/ GIMT_Encode4(132069), |
| 51009 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 51010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 51011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51012 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51014 | GIM_Try, /*On fail goto*//*Label 3575*/ GIMT_Encode4(132023), // Rule ID 48940 // |
| 51015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51016 | // (sra:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSRA_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 51017 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 51018 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51019 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF8), |
| 51022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51023 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51024 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51025 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51029 | GIR_RootConstrainSelectedInstOperands, |
| 51030 | // GIR_Coverage, 48940, |
| 51031 | GIR_EraseRootFromParent_Done, |
| 51032 | // Label 3575: @132023 |
| 51033 | GIM_Try, /*On fail goto*//*Label 3576*/ GIMT_Encode4(132068), // Rule ID 48941 // |
| 51034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51035 | // (sra:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSRA_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 51036 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 51037 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51038 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF8), |
| 51041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51042 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51043 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51044 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51048 | GIR_RootConstrainSelectedInstOperands, |
| 51049 | // GIR_Coverage, 48941, |
| 51050 | GIR_EraseRootFromParent_Done, |
| 51051 | // Label 3576: @132068 |
| 51052 | GIM_Reject, |
| 51053 | // Label 3574: @132069 |
| 51054 | GIM_Reject, |
| 51055 | // Label 3540: @132070 |
| 51056 | GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(132184), |
| 51057 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 51058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 51059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51060 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51061 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51062 | GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(132138), // Rule ID 48952 // |
| 51063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51064 | // (sra:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSRA_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 51065 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 51066 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51067 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51068 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF4), |
| 51070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51071 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51072 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51073 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51077 | GIR_RootConstrainSelectedInstOperands, |
| 51078 | // GIR_Coverage, 48952, |
| 51079 | GIR_EraseRootFromParent_Done, |
| 51080 | // Label 3578: @132138 |
| 51081 | GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(132183), // Rule ID 48953 // |
| 51082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51083 | // (sra:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSRA_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 51084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 51085 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51086 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF4), |
| 51089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51090 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51091 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51092 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51096 | GIR_RootConstrainSelectedInstOperands, |
| 51097 | // GIR_Coverage, 48953, |
| 51098 | GIR_EraseRootFromParent_Done, |
| 51099 | // Label 3579: @132183 |
| 51100 | GIM_Reject, |
| 51101 | // Label 3577: @132184 |
| 51102 | GIM_Reject, |
| 51103 | // Label 3541: @132185 |
| 51104 | GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(132299), |
| 51105 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 51106 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 51107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51110 | GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(132253), // Rule ID 48960 // |
| 51111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51112 | // (sra:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSRA_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 51113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 51114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF2), |
| 51118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51119 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51120 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51121 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51125 | GIR_RootConstrainSelectedInstOperands, |
| 51126 | // GIR_Coverage, 48960, |
| 51127 | GIR_EraseRootFromParent_Done, |
| 51128 | // Label 3581: @132253 |
| 51129 | GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(132298), // Rule ID 48961 // |
| 51130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51131 | // (sra:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSRA_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 51132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 51133 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51134 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF2), |
| 51137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51138 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51139 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51140 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51144 | GIR_RootConstrainSelectedInstOperands, |
| 51145 | // GIR_Coverage, 48961, |
| 51146 | GIR_EraseRootFromParent_Done, |
| 51147 | // Label 3582: @132298 |
| 51148 | GIM_Reject, |
| 51149 | // Label 3580: @132299 |
| 51150 | GIM_Reject, |
| 51151 | // Label 3542: @132300 |
| 51152 | GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(132414), |
| 51153 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 51154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 51155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51157 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51158 | GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(132368), // Rule ID 48976 // |
| 51159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 51160 | // (sra:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 51161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 51162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51167 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51169 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51173 | GIR_RootConstrainSelectedInstOperands, |
| 51174 | // GIR_Coverage, 48976, |
| 51175 | GIR_EraseRootFromParent_Done, |
| 51176 | // Label 3584: @132368 |
| 51177 | GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(132413), // Rule ID 48977 // |
| 51178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 51179 | // (sra:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 51180 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 51181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51187 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51188 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51192 | GIR_RootConstrainSelectedInstOperands, |
| 51193 | // GIR_Coverage, 48977, |
| 51194 | GIR_EraseRootFromParent_Done, |
| 51195 | // Label 3585: @132413 |
| 51196 | GIM_Reject, |
| 51197 | // Label 3583: @132414 |
| 51198 | GIM_Reject, |
| 51199 | // Label 3543: @132415 |
| 51200 | GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(132529), |
| 51201 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 51202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 51203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51204 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51205 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51206 | GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(132483), // Rule ID 48944 // |
| 51207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51208 | // (sra:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSRA_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 51209 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 51210 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51211 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51212 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF4), |
| 51214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51215 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51216 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51217 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51221 | GIR_RootConstrainSelectedInstOperands, |
| 51222 | // GIR_Coverage, 48944, |
| 51223 | GIR_EraseRootFromParent_Done, |
| 51224 | // Label 3587: @132483 |
| 51225 | GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(132528), // Rule ID 48945 // |
| 51226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51227 | // (sra:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSRA_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 51228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 51229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51230 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF4), |
| 51233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51234 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51235 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51236 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51240 | GIR_RootConstrainSelectedInstOperands, |
| 51241 | // GIR_Coverage, 48945, |
| 51242 | GIR_EraseRootFromParent_Done, |
| 51243 | // Label 3588: @132528 |
| 51244 | GIM_Reject, |
| 51245 | // Label 3586: @132529 |
| 51246 | GIM_Reject, |
| 51247 | // Label 3544: @132530 |
| 51248 | GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(132644), |
| 51249 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 51250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 51251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51252 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51253 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51254 | GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(132598), // Rule ID 48956 // |
| 51255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51256 | // (sra:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSRA_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 51257 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 51258 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51259 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF2), |
| 51262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51263 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51264 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51265 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51269 | GIR_RootConstrainSelectedInstOperands, |
| 51270 | // GIR_Coverage, 48956, |
| 51271 | GIR_EraseRootFromParent_Done, |
| 51272 | // Label 3590: @132598 |
| 51273 | GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(132643), // Rule ID 48957 // |
| 51274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51275 | // (sra:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSRA_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 51276 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 51277 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51278 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51279 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF2), |
| 51281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51282 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51283 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51284 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51288 | GIR_RootConstrainSelectedInstOperands, |
| 51289 | // GIR_Coverage, 48957, |
| 51290 | GIR_EraseRootFromParent_Done, |
| 51291 | // Label 3591: @132643 |
| 51292 | GIM_Reject, |
| 51293 | // Label 3589: @132644 |
| 51294 | GIM_Reject, |
| 51295 | // Label 3545: @132645 |
| 51296 | GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(132759), |
| 51297 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 51298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 51299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51300 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51301 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51302 | GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(132713), // Rule ID 48972 // |
| 51303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51304 | // (sra:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 51305 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 51306 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51307 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51311 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51312 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51313 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51317 | GIR_RootConstrainSelectedInstOperands, |
| 51318 | // GIR_Coverage, 48972, |
| 51319 | GIR_EraseRootFromParent_Done, |
| 51320 | // Label 3593: @132713 |
| 51321 | GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(132758), // Rule ID 48973 // |
| 51322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51323 | // (sra:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 51324 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 51325 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51326 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51327 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51330 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51331 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51332 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51336 | GIR_RootConstrainSelectedInstOperands, |
| 51337 | // GIR_Coverage, 48973, |
| 51338 | GIR_EraseRootFromParent_Done, |
| 51339 | // Label 3594: @132758 |
| 51340 | GIM_Reject, |
| 51341 | // Label 3592: @132759 |
| 51342 | GIM_Reject, |
| 51343 | // Label 3546: @132760 |
| 51344 | GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(132874), |
| 51345 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 51346 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 51347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51348 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51349 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51350 | GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(132828), // Rule ID 49016 // |
| 51351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 51352 | // (sra:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 51353 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 51354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51355 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51356 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51359 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51360 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51361 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51365 | GIR_RootConstrainSelectedInstOperands, |
| 51366 | // GIR_Coverage, 49016, |
| 51367 | GIR_EraseRootFromParent_Done, |
| 51368 | // Label 3596: @132828 |
| 51369 | GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(132873), // Rule ID 49017 // |
| 51370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 51371 | // (sra:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 51372 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 51373 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51374 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51378 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51379 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51380 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51384 | GIR_RootConstrainSelectedInstOperands, |
| 51385 | // GIR_Coverage, 49017, |
| 51386 | GIR_EraseRootFromParent_Done, |
| 51387 | // Label 3597: @132873 |
| 51388 | GIM_Reject, |
| 51389 | // Label 3595: @132874 |
| 51390 | GIM_Reject, |
| 51391 | // Label 3547: @132875 |
| 51392 | GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(132989), |
| 51393 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 51394 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 51395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51396 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51397 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51398 | GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(132943), // Rule ID 48948 // |
| 51399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51400 | // (sra:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSRA_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 51401 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 51402 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51403 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51404 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF2), |
| 51406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51407 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51408 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51409 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51413 | GIR_RootConstrainSelectedInstOperands, |
| 51414 | // GIR_Coverage, 48948, |
| 51415 | GIR_EraseRootFromParent_Done, |
| 51416 | // Label 3599: @132943 |
| 51417 | GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(132988), // Rule ID 48949 // |
| 51418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51419 | // (sra:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSRA_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 51420 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 51421 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51422 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51423 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_MF2), |
| 51425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51426 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51427 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51428 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51432 | GIR_RootConstrainSelectedInstOperands, |
| 51433 | // GIR_Coverage, 48949, |
| 51434 | GIR_EraseRootFromParent_Done, |
| 51435 | // Label 3600: @132988 |
| 51436 | GIM_Reject, |
| 51437 | // Label 3598: @132989 |
| 51438 | GIM_Reject, |
| 51439 | // Label 3548: @132990 |
| 51440 | GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(133104), |
| 51441 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 51442 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 51443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51444 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51445 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51446 | GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(133058), // Rule ID 48968 // |
| 51447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51448 | // (sra:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 51449 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 51450 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51451 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51452 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51455 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51456 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51457 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51461 | GIR_RootConstrainSelectedInstOperands, |
| 51462 | // GIR_Coverage, 48968, |
| 51463 | GIR_EraseRootFromParent_Done, |
| 51464 | // Label 3602: @133058 |
| 51465 | GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(133103), // Rule ID 48969 // |
| 51466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51467 | // (sra:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 51468 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 51469 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51470 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51474 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51475 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51476 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51480 | GIR_RootConstrainSelectedInstOperands, |
| 51481 | // GIR_Coverage, 48969, |
| 51482 | GIR_EraseRootFromParent_Done, |
| 51483 | // Label 3603: @133103 |
| 51484 | GIM_Reject, |
| 51485 | // Label 3601: @133104 |
| 51486 | GIM_Reject, |
| 51487 | // Label 3549: @133105 |
| 51488 | GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(133219), |
| 51489 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 51490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 51491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51493 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51494 | GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(133173), // Rule ID 49004 // |
| 51495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51496 | // (sra:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 51497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 51498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51499 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51504 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51505 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51509 | GIR_RootConstrainSelectedInstOperands, |
| 51510 | // GIR_Coverage, 49004, |
| 51511 | GIR_EraseRootFromParent_Done, |
| 51512 | // Label 3605: @133173 |
| 51513 | GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(133218), // Rule ID 49005 // |
| 51514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51515 | // (sra:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 51516 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 51517 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51518 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51522 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51523 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51524 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51528 | GIR_RootConstrainSelectedInstOperands, |
| 51529 | // GIR_Coverage, 49005, |
| 51530 | GIR_EraseRootFromParent_Done, |
| 51531 | // Label 3606: @133218 |
| 51532 | GIM_Reject, |
| 51533 | // Label 3604: @133219 |
| 51534 | GIM_Reject, |
| 51535 | // Label 3550: @133220 |
| 51536 | GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(133334), |
| 51537 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 51538 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 51539 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51540 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51541 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51542 | GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(133288), // Rule ID 49020 // |
| 51543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 51544 | // (sra:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 51545 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 51546 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51547 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51548 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51551 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51552 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51553 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51557 | GIR_RootConstrainSelectedInstOperands, |
| 51558 | // GIR_Coverage, 49020, |
| 51559 | GIR_EraseRootFromParent_Done, |
| 51560 | // Label 3608: @133288 |
| 51561 | GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(133333), // Rule ID 49021 // |
| 51562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 51563 | // (sra:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 51564 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 51565 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51566 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51570 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51571 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51572 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51576 | GIR_RootConstrainSelectedInstOperands, |
| 51577 | // GIR_Coverage, 49021, |
| 51578 | GIR_EraseRootFromParent_Done, |
| 51579 | // Label 3609: @133333 |
| 51580 | GIM_Reject, |
| 51581 | // Label 3607: @133334 |
| 51582 | GIM_Reject, |
| 51583 | // Label 3551: @133335 |
| 51584 | GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(133449), |
| 51585 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 51586 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 51587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51589 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 51590 | GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(133403), // Rule ID 48964 // |
| 51591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51592 | // (sra:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 51593 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 51594 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51595 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51596 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51599 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51600 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51601 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51605 | GIR_RootConstrainSelectedInstOperands, |
| 51606 | // GIR_Coverage, 48964, |
| 51607 | GIR_EraseRootFromParent_Done, |
| 51608 | // Label 3611: @133403 |
| 51609 | GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(133448), // Rule ID 48965 // |
| 51610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51611 | // (sra:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSRA_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 51612 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 51613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M1), |
| 51617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51618 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51619 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51620 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51624 | GIR_RootConstrainSelectedInstOperands, |
| 51625 | // GIR_Coverage, 48965, |
| 51626 | GIR_EraseRootFromParent_Done, |
| 51627 | // Label 3612: @133448 |
| 51628 | GIM_Reject, |
| 51629 | // Label 3610: @133449 |
| 51630 | GIM_Reject, |
| 51631 | // Label 3552: @133450 |
| 51632 | GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(133564), |
| 51633 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 51634 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 51635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51636 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51637 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51638 | GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(133518), // Rule ID 48992 // |
| 51639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51640 | // (sra:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 51641 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 51642 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51643 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51644 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51647 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51648 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51649 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51653 | GIR_RootConstrainSelectedInstOperands, |
| 51654 | // GIR_Coverage, 48992, |
| 51655 | GIR_EraseRootFromParent_Done, |
| 51656 | // Label 3614: @133518 |
| 51657 | GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(133563), // Rule ID 48993 // |
| 51658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51659 | // (sra:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 51660 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 51661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51666 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51667 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51668 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51672 | GIR_RootConstrainSelectedInstOperands, |
| 51673 | // GIR_Coverage, 48993, |
| 51674 | GIR_EraseRootFromParent_Done, |
| 51675 | // Label 3615: @133563 |
| 51676 | GIM_Reject, |
| 51677 | // Label 3613: @133564 |
| 51678 | GIM_Reject, |
| 51679 | // Label 3553: @133565 |
| 51680 | GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(133679), |
| 51681 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 51682 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 51683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51684 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51685 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51686 | GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(133633), // Rule ID 49008 // |
| 51687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51688 | // (sra:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 51689 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 51690 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51691 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51695 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51696 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51697 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51701 | GIR_RootConstrainSelectedInstOperands, |
| 51702 | // GIR_Coverage, 49008, |
| 51703 | GIR_EraseRootFromParent_Done, |
| 51704 | // Label 3617: @133633 |
| 51705 | GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(133678), // Rule ID 49009 // |
| 51706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51707 | // (sra:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 51708 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 51709 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51710 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51714 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51715 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51716 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51720 | GIR_RootConstrainSelectedInstOperands, |
| 51721 | // GIR_Coverage, 49009, |
| 51722 | GIR_EraseRootFromParent_Done, |
| 51723 | // Label 3618: @133678 |
| 51724 | GIM_Reject, |
| 51725 | // Label 3616: @133679 |
| 51726 | GIM_Reject, |
| 51727 | // Label 3554: @133680 |
| 51728 | GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(133794), |
| 51729 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 51730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 51731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51732 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51734 | GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(133748), // Rule ID 49024 // |
| 51735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 51736 | // (sra:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 51737 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 51738 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51739 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51740 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 51742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51743 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51744 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51745 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51749 | GIR_RootConstrainSelectedInstOperands, |
| 51750 | // GIR_Coverage, 49024, |
| 51751 | GIR_EraseRootFromParent_Done, |
| 51752 | // Label 3620: @133748 |
| 51753 | GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(133793), // Rule ID 49025 // |
| 51754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 51755 | // (sra:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 51756 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 51757 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51758 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 51761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51762 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51763 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51764 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 51767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51768 | GIR_RootConstrainSelectedInstOperands, |
| 51769 | // GIR_Coverage, 49025, |
| 51770 | GIR_EraseRootFromParent_Done, |
| 51771 | // Label 3621: @133793 |
| 51772 | GIM_Reject, |
| 51773 | // Label 3619: @133794 |
| 51774 | GIM_Reject, |
| 51775 | // Label 3555: @133795 |
| 51776 | GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(133909), |
| 51777 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 51778 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 51779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51780 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51781 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 51782 | GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(133863), // Rule ID 48980 // |
| 51783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51784 | // (sra:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 51785 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 51786 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51787 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51788 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51791 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51792 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51793 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51797 | GIR_RootConstrainSelectedInstOperands, |
| 51798 | // GIR_Coverage, 48980, |
| 51799 | GIR_EraseRootFromParent_Done, |
| 51800 | // Label 3623: @133863 |
| 51801 | GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(133908), // Rule ID 48981 // |
| 51802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51803 | // (sra:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSRA_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 51804 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 51805 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51806 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M2), |
| 51809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51810 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51811 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51812 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51816 | GIR_RootConstrainSelectedInstOperands, |
| 51817 | // GIR_Coverage, 48981, |
| 51818 | GIR_EraseRootFromParent_Done, |
| 51819 | // Label 3624: @133908 |
| 51820 | GIM_Reject, |
| 51821 | // Label 3622: @133909 |
| 51822 | GIM_Reject, |
| 51823 | // Label 3556: @133910 |
| 51824 | GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(134024), |
| 51825 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 51826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 51827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51828 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51829 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51830 | GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(133978), // Rule ID 48996 // |
| 51831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51832 | // (sra:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 51833 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 51834 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51835 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51839 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51840 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51841 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51845 | GIR_RootConstrainSelectedInstOperands, |
| 51846 | // GIR_Coverage, 48996, |
| 51847 | GIR_EraseRootFromParent_Done, |
| 51848 | // Label 3626: @133978 |
| 51849 | GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(134023), // Rule ID 48997 // |
| 51850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51851 | // (sra:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 51852 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 51853 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51854 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51858 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51859 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51860 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51864 | GIR_RootConstrainSelectedInstOperands, |
| 51865 | // GIR_Coverage, 48997, |
| 51866 | GIR_EraseRootFromParent_Done, |
| 51867 | // Label 3627: @134023 |
| 51868 | GIM_Reject, |
| 51869 | // Label 3625: @134024 |
| 51870 | GIM_Reject, |
| 51871 | // Label 3557: @134025 |
| 51872 | GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(134139), |
| 51873 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 51874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 51875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51877 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51878 | GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(134093), // Rule ID 49012 // |
| 51879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51880 | // (sra:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 51881 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 51882 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51883 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 51886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51887 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51888 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51889 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51893 | GIR_RootConstrainSelectedInstOperands, |
| 51894 | // GIR_Coverage, 49012, |
| 51895 | GIR_EraseRootFromParent_Done, |
| 51896 | // Label 3629: @134093 |
| 51897 | GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(134138), // Rule ID 49013 // |
| 51898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51899 | // (sra:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 51900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 51901 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51902 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 51905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51906 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51907 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51908 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 51911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51912 | GIR_RootConstrainSelectedInstOperands, |
| 51913 | // GIR_Coverage, 49013, |
| 51914 | GIR_EraseRootFromParent_Done, |
| 51915 | // Label 3630: @134138 |
| 51916 | GIM_Reject, |
| 51917 | // Label 3628: @134139 |
| 51918 | GIM_Reject, |
| 51919 | // Label 3558: @134140 |
| 51920 | GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(134254), |
| 51921 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 51922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 51923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51924 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 51926 | GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(134208), // Rule ID 48984 // |
| 51927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51928 | // (sra:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 51929 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 51930 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51931 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51935 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51936 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51937 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51941 | GIR_RootConstrainSelectedInstOperands, |
| 51942 | // GIR_Coverage, 48984, |
| 51943 | GIR_EraseRootFromParent_Done, |
| 51944 | // Label 3632: @134208 |
| 51945 | GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(134253), // Rule ID 48985 // |
| 51946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51947 | // (sra:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSRA_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 51948 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 51949 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51950 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M4), |
| 51953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51954 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51955 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51956 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51960 | GIR_RootConstrainSelectedInstOperands, |
| 51961 | // GIR_Coverage, 48985, |
| 51962 | GIR_EraseRootFromParent_Done, |
| 51963 | // Label 3633: @134253 |
| 51964 | GIM_Reject, |
| 51965 | // Label 3631: @134254 |
| 51966 | GIM_Reject, |
| 51967 | // Label 3559: @134255 |
| 51968 | GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(134369), |
| 51969 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 51970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 51971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51972 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51973 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 51974 | GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(134323), // Rule ID 49000 // |
| 51975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 51976 | // (sra:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 51977 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 51978 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51979 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51980 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 51982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 51983 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51984 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 51985 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 51986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 51987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 51988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 51989 | GIR_RootConstrainSelectedInstOperands, |
| 51990 | // GIR_Coverage, 49000, |
| 51991 | GIR_EraseRootFromParent_Done, |
| 51992 | // Label 3635: @134323 |
| 51993 | GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(134368), // Rule ID 49001 // |
| 51994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 51995 | // (sra:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 51996 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 51997 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 51998 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 52001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52002 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52003 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52004 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52008 | GIR_RootConstrainSelectedInstOperands, |
| 52009 | // GIR_Coverage, 49001, |
| 52010 | GIR_EraseRootFromParent_Done, |
| 52011 | // Label 3636: @134368 |
| 52012 | GIM_Reject, |
| 52013 | // Label 3634: @134369 |
| 52014 | GIM_Reject, |
| 52015 | // Label 3560: @134370 |
| 52016 | GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(134484), |
| 52017 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 52018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 52019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 52020 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 52021 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 52022 | GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(134438), // Rule ID 48988 // |
| 52023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52024 | // (sra:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 52025 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 52026 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52027 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 52030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52031 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52032 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52033 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52037 | GIR_RootConstrainSelectedInstOperands, |
| 52038 | // GIR_Coverage, 48988, |
| 52039 | GIR_EraseRootFromParent_Done, |
| 52040 | // Label 3638: @134438 |
| 52041 | GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(134483), // Rule ID 48989 // |
| 52042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52043 | // (sra:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSRA_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 52044 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 52045 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52046 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSRA_VV_M8), |
| 52049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52050 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52051 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52052 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52056 | GIR_RootConstrainSelectedInstOperands, |
| 52057 | // GIR_Coverage, 48989, |
| 52058 | GIR_EraseRootFromParent_Done, |
| 52059 | // Label 3639: @134483 |
| 52060 | GIM_Reject, |
| 52061 | // Label 3637: @134484 |
| 52062 | GIM_Reject, |
| 52063 | // Label 3561: @134485 |
| 52064 | GIM_Reject, |
| 52065 | // Label 42: @134486 |
| 52066 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 3664*/ GIMT_Encode4(137588), |
| 52067 | /*GILLT_s32*//*Label 3640*/ GIMT_Encode4(134621), |
| 52068 | /*GILLT_s64*//*Label 3641*/ GIMT_Encode4(134921), GIMT_Encode4(0), |
| 52069 | /*GILLT_nxv1s8*//*Label 3642*/ GIMT_Encode4(135058), |
| 52070 | /*GILLT_nxv1s16*//*Label 3643*/ GIMT_Encode4(135173), |
| 52071 | /*GILLT_nxv1s32*//*Label 3644*/ GIMT_Encode4(135288), |
| 52072 | /*GILLT_nxv1s64*//*Label 3645*/ GIMT_Encode4(135403), GIMT_Encode4(0), |
| 52073 | /*GILLT_nxv2s8*//*Label 3646*/ GIMT_Encode4(135518), |
| 52074 | /*GILLT_nxv2s16*//*Label 3647*/ GIMT_Encode4(135633), |
| 52075 | /*GILLT_nxv2s32*//*Label 3648*/ GIMT_Encode4(135748), |
| 52076 | /*GILLT_nxv2s64*//*Label 3649*/ GIMT_Encode4(135863), GIMT_Encode4(0), |
| 52077 | /*GILLT_nxv4s8*//*Label 3650*/ GIMT_Encode4(135978), |
| 52078 | /*GILLT_nxv4s16*//*Label 3651*/ GIMT_Encode4(136093), |
| 52079 | /*GILLT_nxv4s32*//*Label 3652*/ GIMT_Encode4(136208), |
| 52080 | /*GILLT_nxv4s64*//*Label 3653*/ GIMT_Encode4(136323), GIMT_Encode4(0), |
| 52081 | /*GILLT_nxv8s8*//*Label 3654*/ GIMT_Encode4(136438), |
| 52082 | /*GILLT_nxv8s16*//*Label 3655*/ GIMT_Encode4(136553), |
| 52083 | /*GILLT_nxv8s32*//*Label 3656*/ GIMT_Encode4(136668), |
| 52084 | /*GILLT_nxv8s64*//*Label 3657*/ GIMT_Encode4(136783), GIMT_Encode4(0), |
| 52085 | /*GILLT_nxv16s8*//*Label 3658*/ GIMT_Encode4(136898), |
| 52086 | /*GILLT_nxv16s16*//*Label 3659*/ GIMT_Encode4(137013), |
| 52087 | /*GILLT_nxv16s32*//*Label 3660*/ GIMT_Encode4(137128), GIMT_Encode4(0), |
| 52088 | /*GILLT_nxv32s8*//*Label 3661*/ GIMT_Encode4(137243), |
| 52089 | /*GILLT_nxv32s16*//*Label 3662*/ GIMT_Encode4(137358), GIMT_Encode4(0), |
| 52090 | /*GILLT_nxv64s8*//*Label 3663*/ GIMT_Encode4(137473), |
| 52091 | // Label 3640: @134621 |
| 52092 | GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(134920), |
| 52093 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 52094 | GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(134674), // Rule ID 2613 // |
| 52095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 52096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 52097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52098 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52099 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52100 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 52101 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 52102 | // MIs[1] Operand 1 |
| 52103 | // No operand predicates |
| 52104 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 52105 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) => (RORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 52106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORI), |
| 52107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52108 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52109 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52110 | GIR_RootConstrainSelectedInstOperands, |
| 52111 | // GIR_Coverage, 2613, |
| 52112 | GIR_EraseRootFromParent_Done, |
| 52113 | // Label 3666: @134674 |
| 52114 | GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(134719), // Rule ID 2815 // |
| 52115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 52116 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 52117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52118 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52119 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52120 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 52121 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 52122 | // MIs[1] Operand 1 |
| 52123 | // No operand predicates |
| 52124 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 52125 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) => (RORIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$imm) |
| 52126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORIW), |
| 52127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52128 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52129 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52130 | GIR_RootConstrainSelectedInstOperands, |
| 52131 | // GIR_Coverage, 2815, |
| 52132 | GIR_EraseRootFromParent_Done, |
| 52133 | // Label 3667: @134719 |
| 52134 | GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(134764), // Rule ID 2816 // |
| 52135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 52136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 52137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52138 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52140 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 52141 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 52142 | // MIs[1] Operand 1 |
| 52143 | // No operand predicates |
| 52144 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 52145 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) => (RORIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$imm) |
| 52146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORIW), |
| 52147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52148 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52149 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52150 | GIR_RootConstrainSelectedInstOperands, |
| 52151 | // GIR_Coverage, 2816, |
| 52152 | GIR_EraseRootFromParent_Done, |
| 52153 | // Label 3668: @134764 |
| 52154 | GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(134809), // Rule ID 63015 // |
| 52155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode1), |
| 52156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 52157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52159 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52160 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 52161 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 52162 | // MIs[1] Operand 1 |
| 52163 | // No operand predicates |
| 52164 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 52165 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) => (TH_SRRI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 52166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_SRRI), |
| 52167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52169 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52170 | GIR_RootConstrainSelectedInstOperands, |
| 52171 | // GIR_Coverage, 63015, |
| 52172 | GIR_EraseRootFromParent_Done, |
| 52173 | // Label 3669: @134809 |
| 52174 | GIM_Try, /*On fail goto*//*Label 3670*/ GIMT_Encode4(134849), // Rule ID 2611 // |
| 52175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 52176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 52177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 52180 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)) => (ROR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 52181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ROR), |
| 52182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52183 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 52185 | GIR_RootConstrainSelectedInstOperands, |
| 52186 | // GIR_Coverage, 2611, |
| 52187 | GIR_EraseRootFromParent_Done, |
| 52188 | // Label 3670: @134849 |
| 52189 | GIM_Try, /*On fail goto*//*Label 3671*/ GIMT_Encode4(134889), // Rule ID 2814 // |
| 52190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 52191 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 52192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52193 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMask32), |
| 52195 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMask32:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (RORW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 52196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORW), |
| 52197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52198 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 52200 | GIR_RootConstrainSelectedInstOperands, |
| 52201 | // GIR_Coverage, 2814, |
| 52202 | GIR_EraseRootFromParent_Done, |
| 52203 | // Label 3671: @134889 |
| 52204 | GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(134919), // Rule ID 64964 // |
| 52205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 52206 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 52207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52208 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52209 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52210 | // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_ROR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 52211 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_ROR), |
| 52212 | GIR_RootConstrainSelectedInstOperands, |
| 52213 | // GIR_Coverage, 64964, |
| 52214 | GIR_Done, |
| 52215 | // Label 3672: @134919 |
| 52216 | GIM_Reject, |
| 52217 | // Label 3665: @134920 |
| 52218 | GIM_Reject, |
| 52219 | // Label 3641: @134921 |
| 52220 | GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(135057), |
| 52221 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 52222 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 52223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52224 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52225 | GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(134974), // Rule ID 2612 // |
| 52226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 52227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52228 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 52229 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 52230 | // MIs[1] Operand 1 |
| 52231 | // No operand predicates |
| 52232 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 52233 | // (rotr:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) => (RORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 52234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORI), |
| 52235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52236 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52237 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52238 | GIR_RootConstrainSelectedInstOperands, |
| 52239 | // GIR_Coverage, 2612, |
| 52240 | GIR_EraseRootFromParent_Done, |
| 52241 | // Label 3674: @134974 |
| 52242 | GIM_Try, /*On fail goto*//*Label 3675*/ GIMT_Encode4(135008), // Rule ID 63014 // |
| 52243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode0), |
| 52244 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52245 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 52246 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 52247 | // MIs[1] Operand 1 |
| 52248 | // No operand predicates |
| 52249 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 52250 | // (rotr:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) => (TH_SRRI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm) |
| 52251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_SRRI), |
| 52252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52253 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52254 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52255 | GIR_RootConstrainSelectedInstOperands, |
| 52256 | // GIR_Coverage, 63014, |
| 52257 | GIR_EraseRootFromParent_Done, |
| 52258 | // Label 3675: @135008 |
| 52259 | GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(135037), // Rule ID 2610 // |
| 52260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 52261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 52262 | // (rotr:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (ROR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 52263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ROR), |
| 52264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52265 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 52267 | GIR_RootConstrainSelectedInstOperands, |
| 52268 | // GIR_Coverage, 2610, |
| 52269 | GIR_EraseRootFromParent_Done, |
| 52270 | // Label 3676: @135037 |
| 52271 | GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(135056), // Rule ID 64963 // |
| 52272 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0), |
| 52273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 52274 | // (rotr:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (CV_ROR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 52275 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_ROR), |
| 52276 | GIR_RootConstrainSelectedInstOperands, |
| 52277 | // GIR_Coverage, 64963, |
| 52278 | GIR_Done, |
| 52279 | // Label 3677: @135056 |
| 52280 | GIM_Reject, |
| 52281 | // Label 3673: @135057 |
| 52282 | GIM_Reject, |
| 52283 | // Label 3642: @135058 |
| 52284 | GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(135172), |
| 52285 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 52286 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 52287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52289 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52290 | GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(135126), // Rule ID 59892 // |
| 52291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52292 | // (rotr:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVROR_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 52293 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 52294 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52295 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF8), |
| 52298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52299 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52300 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52301 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52305 | GIR_RootConstrainSelectedInstOperands, |
| 52306 | // GIR_Coverage, 59892, |
| 52307 | GIR_EraseRootFromParent_Done, |
| 52308 | // Label 3679: @135126 |
| 52309 | GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(135171), // Rule ID 59893 // |
| 52310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52311 | // (rotr:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVROR_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 52312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 52313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52314 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52315 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF8), |
| 52317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52318 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52319 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52320 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52324 | GIR_RootConstrainSelectedInstOperands, |
| 52325 | // GIR_Coverage, 59893, |
| 52326 | GIR_EraseRootFromParent_Done, |
| 52327 | // Label 3680: @135171 |
| 52328 | GIM_Reject, |
| 52329 | // Label 3678: @135172 |
| 52330 | GIM_Reject, |
| 52331 | // Label 3643: @135173 |
| 52332 | GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(135287), |
| 52333 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 52334 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 52335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52338 | GIM_Try, /*On fail goto*//*Label 3682*/ GIMT_Encode4(135241), // Rule ID 59904 // |
| 52339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52340 | // (rotr:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVROR_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 52341 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 52342 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52343 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF4), |
| 52346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52347 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52348 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52349 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52353 | GIR_RootConstrainSelectedInstOperands, |
| 52354 | // GIR_Coverage, 59904, |
| 52355 | GIR_EraseRootFromParent_Done, |
| 52356 | // Label 3682: @135241 |
| 52357 | GIM_Try, /*On fail goto*//*Label 3683*/ GIMT_Encode4(135286), // Rule ID 59905 // |
| 52358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52359 | // (rotr:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVROR_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 52360 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 52361 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52362 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52363 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF4), |
| 52365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52366 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52367 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52368 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52372 | GIR_RootConstrainSelectedInstOperands, |
| 52373 | // GIR_Coverage, 59905, |
| 52374 | GIR_EraseRootFromParent_Done, |
| 52375 | // Label 3683: @135286 |
| 52376 | GIM_Reject, |
| 52377 | // Label 3681: @135287 |
| 52378 | GIM_Reject, |
| 52379 | // Label 3644: @135288 |
| 52380 | GIM_Try, /*On fail goto*//*Label 3684*/ GIMT_Encode4(135402), |
| 52381 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 52382 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 52383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52384 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52385 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52386 | GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(135356), // Rule ID 59912 // |
| 52387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52388 | // (rotr:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVROR_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 52389 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 52390 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52391 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52392 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF2), |
| 52394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52395 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52396 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52397 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52401 | GIR_RootConstrainSelectedInstOperands, |
| 52402 | // GIR_Coverage, 59912, |
| 52403 | GIR_EraseRootFromParent_Done, |
| 52404 | // Label 3685: @135356 |
| 52405 | GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(135401), // Rule ID 59913 // |
| 52406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52407 | // (rotr:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVROR_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 52408 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 52409 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52410 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52411 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF2), |
| 52413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52414 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52415 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52416 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52420 | GIR_RootConstrainSelectedInstOperands, |
| 52421 | // GIR_Coverage, 59913, |
| 52422 | GIR_EraseRootFromParent_Done, |
| 52423 | // Label 3686: @135401 |
| 52424 | GIM_Reject, |
| 52425 | // Label 3684: @135402 |
| 52426 | GIM_Reject, |
| 52427 | // Label 3645: @135403 |
| 52428 | GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(135517), |
| 52429 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 52430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 52431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52432 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52434 | GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(135471), // Rule ID 59928 // |
| 52435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 52436 | // (rotr:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 52437 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 52438 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52439 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52440 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52443 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52444 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52445 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 52448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52449 | GIR_RootConstrainSelectedInstOperands, |
| 52450 | // GIR_Coverage, 59928, |
| 52451 | GIR_EraseRootFromParent_Done, |
| 52452 | // Label 3688: @135471 |
| 52453 | GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(135516), // Rule ID 59929 // |
| 52454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 52455 | // (rotr:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 52456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 52457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52463 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52464 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 52467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52468 | GIR_RootConstrainSelectedInstOperands, |
| 52469 | // GIR_Coverage, 59929, |
| 52470 | GIR_EraseRootFromParent_Done, |
| 52471 | // Label 3689: @135516 |
| 52472 | GIM_Reject, |
| 52473 | // Label 3687: @135517 |
| 52474 | GIM_Reject, |
| 52475 | // Label 3646: @135518 |
| 52476 | GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(135632), |
| 52477 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 52478 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 52479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52480 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52481 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52482 | GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(135586), // Rule ID 59896 // |
| 52483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52484 | // (rotr:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVROR_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 52485 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 52486 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52487 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52488 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF4), |
| 52490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52491 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52492 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52493 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52497 | GIR_RootConstrainSelectedInstOperands, |
| 52498 | // GIR_Coverage, 59896, |
| 52499 | GIR_EraseRootFromParent_Done, |
| 52500 | // Label 3691: @135586 |
| 52501 | GIM_Try, /*On fail goto*//*Label 3692*/ GIMT_Encode4(135631), // Rule ID 59897 // |
| 52502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52503 | // (rotr:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVROR_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 52504 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 52505 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52506 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF4), |
| 52509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52511 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52512 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52516 | GIR_RootConstrainSelectedInstOperands, |
| 52517 | // GIR_Coverage, 59897, |
| 52518 | GIR_EraseRootFromParent_Done, |
| 52519 | // Label 3692: @135631 |
| 52520 | GIM_Reject, |
| 52521 | // Label 3690: @135632 |
| 52522 | GIM_Reject, |
| 52523 | // Label 3647: @135633 |
| 52524 | GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(135747), |
| 52525 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 52526 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 52527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52528 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52530 | GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(135701), // Rule ID 59908 // |
| 52531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52532 | // (rotr:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVROR_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 52533 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 52534 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52535 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF2), |
| 52538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52539 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52540 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52541 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52545 | GIR_RootConstrainSelectedInstOperands, |
| 52546 | // GIR_Coverage, 59908, |
| 52547 | GIR_EraseRootFromParent_Done, |
| 52548 | // Label 3694: @135701 |
| 52549 | GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(135746), // Rule ID 59909 // |
| 52550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52551 | // (rotr:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVROR_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 52552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 52553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52554 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF2), |
| 52557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52558 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52559 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52560 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52564 | GIR_RootConstrainSelectedInstOperands, |
| 52565 | // GIR_Coverage, 59909, |
| 52566 | GIR_EraseRootFromParent_Done, |
| 52567 | // Label 3695: @135746 |
| 52568 | GIM_Reject, |
| 52569 | // Label 3693: @135747 |
| 52570 | GIM_Reject, |
| 52571 | // Label 3648: @135748 |
| 52572 | GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(135862), |
| 52573 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 52574 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 52575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52578 | GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(135816), // Rule ID 59924 // |
| 52579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52580 | // (rotr:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 52581 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 52582 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52583 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52587 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52588 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52589 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52593 | GIR_RootConstrainSelectedInstOperands, |
| 52594 | // GIR_Coverage, 59924, |
| 52595 | GIR_EraseRootFromParent_Done, |
| 52596 | // Label 3697: @135816 |
| 52597 | GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(135861), // Rule ID 59925 // |
| 52598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52599 | // (rotr:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 52600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 52601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52602 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52606 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52607 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52608 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52612 | GIR_RootConstrainSelectedInstOperands, |
| 52613 | // GIR_Coverage, 59925, |
| 52614 | GIR_EraseRootFromParent_Done, |
| 52615 | // Label 3698: @135861 |
| 52616 | GIM_Reject, |
| 52617 | // Label 3696: @135862 |
| 52618 | GIM_Reject, |
| 52619 | // Label 3649: @135863 |
| 52620 | GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(135977), |
| 52621 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 52622 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 52623 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52624 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52625 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52626 | GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(135931), // Rule ID 59968 // |
| 52627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 52628 | // (rotr:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 52629 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 52630 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52631 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 52634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52635 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52636 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52637 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 52640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52641 | GIR_RootConstrainSelectedInstOperands, |
| 52642 | // GIR_Coverage, 59968, |
| 52643 | GIR_EraseRootFromParent_Done, |
| 52644 | // Label 3700: @135931 |
| 52645 | GIM_Try, /*On fail goto*//*Label 3701*/ GIMT_Encode4(135976), // Rule ID 59969 // |
| 52646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 52647 | // (rotr:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 52648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 52649 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 52653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52654 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52655 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52656 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 52659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52660 | GIR_RootConstrainSelectedInstOperands, |
| 52661 | // GIR_Coverage, 59969, |
| 52662 | GIR_EraseRootFromParent_Done, |
| 52663 | // Label 3701: @135976 |
| 52664 | GIM_Reject, |
| 52665 | // Label 3699: @135977 |
| 52666 | GIM_Reject, |
| 52667 | // Label 3650: @135978 |
| 52668 | GIM_Try, /*On fail goto*//*Label 3702*/ GIMT_Encode4(136092), |
| 52669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 52670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 52671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52674 | GIM_Try, /*On fail goto*//*Label 3703*/ GIMT_Encode4(136046), // Rule ID 59900 // |
| 52675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52676 | // (rotr:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVROR_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 52677 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 52678 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52679 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF2), |
| 52682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52683 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52684 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52685 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52689 | GIR_RootConstrainSelectedInstOperands, |
| 52690 | // GIR_Coverage, 59900, |
| 52691 | GIR_EraseRootFromParent_Done, |
| 52692 | // Label 3703: @136046 |
| 52693 | GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(136091), // Rule ID 59901 // |
| 52694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52695 | // (rotr:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVROR_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 52696 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 52697 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_MF2), |
| 52701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52702 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52704 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52708 | GIR_RootConstrainSelectedInstOperands, |
| 52709 | // GIR_Coverage, 59901, |
| 52710 | GIR_EraseRootFromParent_Done, |
| 52711 | // Label 3704: @136091 |
| 52712 | GIM_Reject, |
| 52713 | // Label 3702: @136092 |
| 52714 | GIM_Reject, |
| 52715 | // Label 3651: @136093 |
| 52716 | GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(136207), |
| 52717 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 52718 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 52719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52720 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52721 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52722 | GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(136161), // Rule ID 59920 // |
| 52723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52724 | // (rotr:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 52725 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 52726 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52727 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52731 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52732 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52733 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52737 | GIR_RootConstrainSelectedInstOperands, |
| 52738 | // GIR_Coverage, 59920, |
| 52739 | GIR_EraseRootFromParent_Done, |
| 52740 | // Label 3706: @136161 |
| 52741 | GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(136206), // Rule ID 59921 // |
| 52742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52743 | // (rotr:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 52744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 52745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52747 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52750 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52752 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52756 | GIR_RootConstrainSelectedInstOperands, |
| 52757 | // GIR_Coverage, 59921, |
| 52758 | GIR_EraseRootFromParent_Done, |
| 52759 | // Label 3707: @136206 |
| 52760 | GIM_Reject, |
| 52761 | // Label 3705: @136207 |
| 52762 | GIM_Reject, |
| 52763 | // Label 3652: @136208 |
| 52764 | GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(136322), |
| 52765 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 52766 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 52767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52768 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52770 | GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(136276), // Rule ID 59956 // |
| 52771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52772 | // (rotr:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 52773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 52774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 52778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52781 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52785 | GIR_RootConstrainSelectedInstOperands, |
| 52786 | // GIR_Coverage, 59956, |
| 52787 | GIR_EraseRootFromParent_Done, |
| 52788 | // Label 3709: @136276 |
| 52789 | GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(136321), // Rule ID 59957 // |
| 52790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52791 | // (rotr:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 52792 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 52793 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52794 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 52797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52798 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52799 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52800 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52804 | GIR_RootConstrainSelectedInstOperands, |
| 52805 | // GIR_Coverage, 59957, |
| 52806 | GIR_EraseRootFromParent_Done, |
| 52807 | // Label 3710: @136321 |
| 52808 | GIM_Reject, |
| 52809 | // Label 3708: @136322 |
| 52810 | GIM_Reject, |
| 52811 | // Label 3653: @136323 |
| 52812 | GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(136437), |
| 52813 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 52814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 52815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 52816 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 52817 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 52818 | GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(136391), // Rule ID 59972 // |
| 52819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 52820 | // (rotr:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 52821 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 52822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 52826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52827 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52828 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52829 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 52832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52833 | GIR_RootConstrainSelectedInstOperands, |
| 52834 | // GIR_Coverage, 59972, |
| 52835 | GIR_EraseRootFromParent_Done, |
| 52836 | // Label 3712: @136391 |
| 52837 | GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(136436), // Rule ID 59973 // |
| 52838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 52839 | // (rotr:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 52840 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 52841 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52842 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 52845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52846 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52847 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52848 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 52851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52852 | GIR_RootConstrainSelectedInstOperands, |
| 52853 | // GIR_Coverage, 59973, |
| 52854 | GIR_EraseRootFromParent_Done, |
| 52855 | // Label 3713: @136436 |
| 52856 | GIM_Reject, |
| 52857 | // Label 3711: @136437 |
| 52858 | GIM_Reject, |
| 52859 | // Label 3654: @136438 |
| 52860 | GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(136552), |
| 52861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 52862 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 52863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52864 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 52866 | GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(136506), // Rule ID 59916 // |
| 52867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52868 | // (rotr:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 52869 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 52870 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52871 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52875 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52876 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52877 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52881 | GIR_RootConstrainSelectedInstOperands, |
| 52882 | // GIR_Coverage, 59916, |
| 52883 | GIR_EraseRootFromParent_Done, |
| 52884 | // Label 3715: @136506 |
| 52885 | GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(136551), // Rule ID 59917 // |
| 52886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52887 | // (rotr:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVROR_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 52888 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 52889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52891 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M1), |
| 52893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52894 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52895 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52896 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52900 | GIR_RootConstrainSelectedInstOperands, |
| 52901 | // GIR_Coverage, 59917, |
| 52902 | GIR_EraseRootFromParent_Done, |
| 52903 | // Label 3716: @136551 |
| 52904 | GIM_Reject, |
| 52905 | // Label 3714: @136552 |
| 52906 | GIM_Reject, |
| 52907 | // Label 3655: @136553 |
| 52908 | GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(136667), |
| 52909 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 52910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 52911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52912 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52913 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 52914 | GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(136621), // Rule ID 59944 // |
| 52915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52916 | // (rotr:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 52917 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 52918 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52919 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 52922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52923 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52924 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52925 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52929 | GIR_RootConstrainSelectedInstOperands, |
| 52930 | // GIR_Coverage, 59944, |
| 52931 | GIR_EraseRootFromParent_Done, |
| 52932 | // Label 3718: @136621 |
| 52933 | GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(136666), // Rule ID 59945 // |
| 52934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52935 | // (rotr:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 52936 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 52937 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52938 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 52941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52942 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52943 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52944 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 52947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52948 | GIR_RootConstrainSelectedInstOperands, |
| 52949 | // GIR_Coverage, 59945, |
| 52950 | GIR_EraseRootFromParent_Done, |
| 52951 | // Label 3719: @136666 |
| 52952 | GIM_Reject, |
| 52953 | // Label 3717: @136667 |
| 52954 | GIM_Reject, |
| 52955 | // Label 3656: @136668 |
| 52956 | GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(136782), |
| 52957 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 52958 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 52959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 52960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 52961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 52962 | GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(136736), // Rule ID 59960 // |
| 52963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 52964 | // (rotr:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 52965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 52966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 52970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52971 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52973 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52977 | GIR_RootConstrainSelectedInstOperands, |
| 52978 | // GIR_Coverage, 59960, |
| 52979 | GIR_EraseRootFromParent_Done, |
| 52980 | // Label 3721: @136736 |
| 52981 | GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(136781), // Rule ID 59961 // |
| 52982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 52983 | // (rotr:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 52984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 52985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 52986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 52989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 52990 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52991 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 52992 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 52993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 52994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 52995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 52996 | GIR_RootConstrainSelectedInstOperands, |
| 52997 | // GIR_Coverage, 59961, |
| 52998 | GIR_EraseRootFromParent_Done, |
| 52999 | // Label 3722: @136781 |
| 53000 | GIM_Reject, |
| 53001 | // Label 3720: @136782 |
| 53002 | GIM_Reject, |
| 53003 | // Label 3657: @136783 |
| 53004 | GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(136897), |
| 53005 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 53006 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 53007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53008 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53009 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53010 | GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(136851), // Rule ID 59976 // |
| 53011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 53012 | // (rotr:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 53013 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 53014 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53015 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53019 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53020 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53021 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 53024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53025 | GIR_RootConstrainSelectedInstOperands, |
| 53026 | // GIR_Coverage, 59976, |
| 53027 | GIR_EraseRootFromParent_Done, |
| 53028 | // Label 3724: @136851 |
| 53029 | GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(136896), // Rule ID 59977 // |
| 53030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 53031 | // (rotr:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 53032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 53033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53038 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53039 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53040 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 53043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53044 | GIR_RootConstrainSelectedInstOperands, |
| 53045 | // GIR_Coverage, 59977, |
| 53046 | GIR_EraseRootFromParent_Done, |
| 53047 | // Label 3725: @136896 |
| 53048 | GIM_Reject, |
| 53049 | // Label 3723: @136897 |
| 53050 | GIM_Reject, |
| 53051 | // Label 3658: @136898 |
| 53052 | GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(137012), |
| 53053 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 53054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 53055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 53056 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 53057 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 53058 | GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(136966), // Rule ID 59932 // |
| 53059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53060 | // (rotr:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 53061 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 53062 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53063 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53064 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 53066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53067 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53069 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53073 | GIR_RootConstrainSelectedInstOperands, |
| 53074 | // GIR_Coverage, 59932, |
| 53075 | GIR_EraseRootFromParent_Done, |
| 53076 | // Label 3727: @136966 |
| 53077 | GIM_Try, /*On fail goto*//*Label 3728*/ GIMT_Encode4(137011), // Rule ID 59933 // |
| 53078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53079 | // (rotr:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVROR_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 53080 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 53081 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53082 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M2), |
| 53085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53086 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53087 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53092 | GIR_RootConstrainSelectedInstOperands, |
| 53093 | // GIR_Coverage, 59933, |
| 53094 | GIR_EraseRootFromParent_Done, |
| 53095 | // Label 3728: @137011 |
| 53096 | GIM_Reject, |
| 53097 | // Label 3726: @137012 |
| 53098 | GIM_Reject, |
| 53099 | // Label 3659: @137013 |
| 53100 | GIM_Try, /*On fail goto*//*Label 3729*/ GIMT_Encode4(137127), |
| 53101 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 53102 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 53103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 53104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 53105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 53106 | GIM_Try, /*On fail goto*//*Label 3730*/ GIMT_Encode4(137081), // Rule ID 59948 // |
| 53107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53108 | // (rotr:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 53109 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 53110 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53111 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 53114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53115 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53116 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53117 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53121 | GIR_RootConstrainSelectedInstOperands, |
| 53122 | // GIR_Coverage, 59948, |
| 53123 | GIR_EraseRootFromParent_Done, |
| 53124 | // Label 3730: @137081 |
| 53125 | GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(137126), // Rule ID 59949 // |
| 53126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53127 | // (rotr:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 53128 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 53129 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53130 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 53133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53134 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53135 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53136 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53140 | GIR_RootConstrainSelectedInstOperands, |
| 53141 | // GIR_Coverage, 59949, |
| 53142 | GIR_EraseRootFromParent_Done, |
| 53143 | // Label 3731: @137126 |
| 53144 | GIM_Reject, |
| 53145 | // Label 3729: @137127 |
| 53146 | GIM_Reject, |
| 53147 | // Label 3660: @137128 |
| 53148 | GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(137242), |
| 53149 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 53150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 53151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53152 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53153 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53154 | GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(137196), // Rule ID 59964 // |
| 53155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53156 | // (rotr:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 53157 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 53158 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53159 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53163 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53164 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53165 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 53168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53169 | GIR_RootConstrainSelectedInstOperands, |
| 53170 | // GIR_Coverage, 59964, |
| 53171 | GIR_EraseRootFromParent_Done, |
| 53172 | // Label 3733: @137196 |
| 53173 | GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(137241), // Rule ID 59965 // |
| 53174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53175 | // (rotr:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 53176 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 53177 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53178 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53182 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53183 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53184 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 53187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53188 | GIR_RootConstrainSelectedInstOperands, |
| 53189 | // GIR_Coverage, 59965, |
| 53190 | GIR_EraseRootFromParent_Done, |
| 53191 | // Label 3734: @137241 |
| 53192 | GIM_Reject, |
| 53193 | // Label 3732: @137242 |
| 53194 | GIM_Reject, |
| 53195 | // Label 3661: @137243 |
| 53196 | GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(137357), |
| 53197 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 53198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 53199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 53200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 53201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 53202 | GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(137311), // Rule ID 59936 // |
| 53203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53204 | // (rotr:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 53205 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 53206 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53207 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 53210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53211 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53212 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53213 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53217 | GIR_RootConstrainSelectedInstOperands, |
| 53218 | // GIR_Coverage, 59936, |
| 53219 | GIR_EraseRootFromParent_Done, |
| 53220 | // Label 3736: @137311 |
| 53221 | GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(137356), // Rule ID 59937 // |
| 53222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53223 | // (rotr:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVROR_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 53224 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 53225 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53226 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53227 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M4), |
| 53229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53230 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53231 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53232 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53236 | GIR_RootConstrainSelectedInstOperands, |
| 53237 | // GIR_Coverage, 59937, |
| 53238 | GIR_EraseRootFromParent_Done, |
| 53239 | // Label 3737: @137356 |
| 53240 | GIM_Reject, |
| 53241 | // Label 3735: @137357 |
| 53242 | GIM_Reject, |
| 53243 | // Label 3662: @137358 |
| 53244 | GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(137472), |
| 53245 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 53246 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 53247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53248 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53249 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53250 | GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(137426), // Rule ID 59952 // |
| 53251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53252 | // (rotr:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 53253 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 53254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53255 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53260 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53261 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53265 | GIR_RootConstrainSelectedInstOperands, |
| 53266 | // GIR_Coverage, 59952, |
| 53267 | GIR_EraseRootFromParent_Done, |
| 53268 | // Label 3739: @137426 |
| 53269 | GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(137471), // Rule ID 59953 // |
| 53270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53271 | // (rotr:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 53272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 53273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53278 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53279 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53280 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53284 | GIR_RootConstrainSelectedInstOperands, |
| 53285 | // GIR_Coverage, 59953, |
| 53286 | GIR_EraseRootFromParent_Done, |
| 53287 | // Label 3740: @137471 |
| 53288 | GIM_Reject, |
| 53289 | // Label 3738: @137472 |
| 53290 | GIM_Reject, |
| 53291 | // Label 3663: @137473 |
| 53292 | GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(137587), |
| 53293 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 53294 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 53295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53296 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53297 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 53298 | GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(137541), // Rule ID 59940 // |
| 53299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53300 | // (rotr:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 53301 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 53302 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53303 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53307 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53308 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53309 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53313 | GIR_RootConstrainSelectedInstOperands, |
| 53314 | // GIR_Coverage, 59940, |
| 53315 | GIR_EraseRootFromParent_Done, |
| 53316 | // Label 3742: @137541 |
| 53317 | GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(137586), // Rule ID 59941 // |
| 53318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53319 | // (rotr:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVROR_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 53320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 53321 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53322 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROR_VV_M8), |
| 53325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53326 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53327 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53332 | GIR_RootConstrainSelectedInstOperands, |
| 53333 | // GIR_Coverage, 59941, |
| 53334 | GIR_EraseRootFromParent_Done, |
| 53335 | // Label 3743: @137586 |
| 53336 | GIM_Reject, |
| 53337 | // Label 3741: @137587 |
| 53338 | GIM_Reject, |
| 53339 | // Label 3664: @137588 |
| 53340 | GIM_Reject, |
| 53341 | // Label 43: @137589 |
| 53342 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 3768*/ GIMT_Encode4(140654), |
| 53343 | /*GILLT_s32*//*Label 3744*/ GIMT_Encode4(137724), |
| 53344 | /*GILLT_s64*//*Label 3745*/ GIMT_Encode4(138002), GIMT_Encode4(0), |
| 53345 | /*GILLT_nxv1s8*//*Label 3746*/ GIMT_Encode4(138124), |
| 53346 | /*GILLT_nxv1s16*//*Label 3747*/ GIMT_Encode4(138239), |
| 53347 | /*GILLT_nxv1s32*//*Label 3748*/ GIMT_Encode4(138354), |
| 53348 | /*GILLT_nxv1s64*//*Label 3749*/ GIMT_Encode4(138469), GIMT_Encode4(0), |
| 53349 | /*GILLT_nxv2s8*//*Label 3750*/ GIMT_Encode4(138584), |
| 53350 | /*GILLT_nxv2s16*//*Label 3751*/ GIMT_Encode4(138699), |
| 53351 | /*GILLT_nxv2s32*//*Label 3752*/ GIMT_Encode4(138814), |
| 53352 | /*GILLT_nxv2s64*//*Label 3753*/ GIMT_Encode4(138929), GIMT_Encode4(0), |
| 53353 | /*GILLT_nxv4s8*//*Label 3754*/ GIMT_Encode4(139044), |
| 53354 | /*GILLT_nxv4s16*//*Label 3755*/ GIMT_Encode4(139159), |
| 53355 | /*GILLT_nxv4s32*//*Label 3756*/ GIMT_Encode4(139274), |
| 53356 | /*GILLT_nxv4s64*//*Label 3757*/ GIMT_Encode4(139389), GIMT_Encode4(0), |
| 53357 | /*GILLT_nxv8s8*//*Label 3758*/ GIMT_Encode4(139504), |
| 53358 | /*GILLT_nxv8s16*//*Label 3759*/ GIMT_Encode4(139619), |
| 53359 | /*GILLT_nxv8s32*//*Label 3760*/ GIMT_Encode4(139734), |
| 53360 | /*GILLT_nxv8s64*//*Label 3761*/ GIMT_Encode4(139849), GIMT_Encode4(0), |
| 53361 | /*GILLT_nxv16s8*//*Label 3762*/ GIMT_Encode4(139964), |
| 53362 | /*GILLT_nxv16s16*//*Label 3763*/ GIMT_Encode4(140079), |
| 53363 | /*GILLT_nxv16s32*//*Label 3764*/ GIMT_Encode4(140194), GIMT_Encode4(0), |
| 53364 | /*GILLT_nxv32s8*//*Label 3765*/ GIMT_Encode4(140309), |
| 53365 | /*GILLT_nxv32s16*//*Label 3766*/ GIMT_Encode4(140424), GIMT_Encode4(0), |
| 53366 | /*GILLT_nxv64s8*//*Label 3767*/ GIMT_Encode4(140539), |
| 53367 | // Label 3744: @137724 |
| 53368 | GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(138001), |
| 53369 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 53370 | GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(137779), // Rule ID 2615 // |
| 53371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 53372 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 53373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53375 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53376 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 53377 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 53378 | // MIs[1] Operand 1 |
| 53379 | // No operand predicates |
| 53380 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 53381 | // (rotl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (RORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmSubFromXLen:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)) |
| 53382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORI), |
| 53383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53384 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53385 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFromXLen), // shamt |
| 53386 | GIR_RootConstrainSelectedInstOperands, |
| 53387 | // GIR_Coverage, 2615, |
| 53388 | GIR_EraseRootFromParent_Done, |
| 53389 | // Label 3770: @137779 |
| 53390 | GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(137826), // Rule ID 2817 // |
| 53391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 53392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 53393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53394 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53395 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53396 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 53397 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 53398 | // MIs[1] Operand 1 |
| 53399 | // No operand predicates |
| 53400 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 53401 | // (rotl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$rs2) => (RORIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmSubFrom32:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$rs2)) |
| 53402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORIW), |
| 53403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53404 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53405 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFrom32), // rs2 |
| 53406 | GIR_RootConstrainSelectedInstOperands, |
| 53407 | // GIR_Coverage, 2817, |
| 53408 | GIR_EraseRootFromParent_Done, |
| 53409 | // Label 3771: @137826 |
| 53410 | GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(137873), // Rule ID 2818 // |
| 53411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), |
| 53412 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 53413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53414 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53415 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53416 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 53417 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), |
| 53418 | // MIs[1] Operand 1 |
| 53419 | // No operand predicates |
| 53420 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 53421 | // (rotl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$rs2) => (RORIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmSubFrom32:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$rs2)) |
| 53422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORIW), |
| 53423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53424 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53425 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFrom32), // rs2 |
| 53426 | GIR_RootConstrainSelectedInstOperands, |
| 53427 | // GIR_Coverage, 2818, |
| 53428 | GIR_EraseRootFromParent_Done, |
| 53429 | // Label 3772: @137873 |
| 53430 | GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(137920), // Rule ID 63017 // |
| 53431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode1), |
| 53432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 53433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53435 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53436 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 53437 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 53438 | // MIs[1] Operand 1 |
| 53439 | // No operand predicates |
| 53440 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 53441 | // (rotl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (TH_SRRI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmSubFromXLen:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)) |
| 53442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_SRRI), |
| 53443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53444 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53445 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFromXLen), // shamt |
| 53446 | GIR_RootConstrainSelectedInstOperands, |
| 53447 | // GIR_Coverage, 63017, |
| 53448 | GIR_EraseRootFromParent_Done, |
| 53449 | // Label 3773: @137920 |
| 53450 | GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(137960), // Rule ID 2609 // |
| 53451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), |
| 53452 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 53453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53454 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 53456 | // (rotl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)) => (ROL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 53457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ROL), |
| 53458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53459 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 53461 | GIR_RootConstrainSelectedInstOperands, |
| 53462 | // GIR_Coverage, 2609, |
| 53463 | GIR_EraseRootFromParent_Done, |
| 53464 | // Label 3774: @137960 |
| 53465 | GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(138000), // Rule ID 2813 // |
| 53466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 53467 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 53468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53469 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMask32), |
| 53471 | // (rotl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMask32:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (ROLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 53472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ROLW), |
| 53473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53474 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 53476 | GIR_RootConstrainSelectedInstOperands, |
| 53477 | // GIR_Coverage, 2813, |
| 53478 | GIR_EraseRootFromParent_Done, |
| 53479 | // Label 3775: @138000 |
| 53480 | GIM_Reject, |
| 53481 | // Label 3769: @138001 |
| 53482 | GIM_Reject, |
| 53483 | // Label 3745: @138002 |
| 53484 | GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(138123), |
| 53485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 53486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 53487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 53489 | GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(138057), // Rule ID 2614 // |
| 53490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 53491 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53492 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 53493 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 53494 | // MIs[1] Operand 1 |
| 53495 | // No operand predicates |
| 53496 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 53497 | // (rotl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (RORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (ImmSubFromXLen:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)) |
| 53498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::RORI), |
| 53499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53501 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFromXLen), // shamt |
| 53502 | GIR_RootConstrainSelectedInstOperands, |
| 53503 | // GIR_Coverage, 2614, |
| 53504 | GIR_EraseRootFromParent_Done, |
| 53505 | // Label 3777: @138057 |
| 53506 | GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(138093), // Rule ID 63016 // |
| 53507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode0), |
| 53508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 53510 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), |
| 53511 | // MIs[1] Operand 1 |
| 53512 | // No operand predicates |
| 53513 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 53514 | // (rotl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (TH_SRRI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (ImmSubFromXLen:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)) |
| 53515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_SRRI), |
| 53516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53517 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53518 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmSubFromXLen), // shamt |
| 53519 | GIR_RootConstrainSelectedInstOperands, |
| 53520 | // GIR_Coverage, 63016, |
| 53521 | GIR_EraseRootFromParent_Done, |
| 53522 | // Label 3778: @138093 |
| 53523 | GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(138122), // Rule ID 2608 // |
| 53524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), |
| 53525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), |
| 53526 | // (rotl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)) => (ROL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 53527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ROL), |
| 53528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53529 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 |
| 53531 | GIR_RootConstrainSelectedInstOperands, |
| 53532 | // GIR_Coverage, 2608, |
| 53533 | GIR_EraseRootFromParent_Done, |
| 53534 | // Label 3779: @138122 |
| 53535 | GIM_Reject, |
| 53536 | // Label 3776: @138123 |
| 53537 | GIM_Reject, |
| 53538 | // Label 3746: @138124 |
| 53539 | GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(138238), |
| 53540 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 53541 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 53542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53543 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53544 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53545 | GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(138192), // Rule ID 59760 // |
| 53546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53547 | // (rotl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVROL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 53548 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 53549 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53550 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF8), |
| 53553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53555 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53556 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53560 | GIR_RootConstrainSelectedInstOperands, |
| 53561 | // GIR_Coverage, 59760, |
| 53562 | GIR_EraseRootFromParent_Done, |
| 53563 | // Label 3781: @138192 |
| 53564 | GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(138237), // Rule ID 59761 // |
| 53565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53566 | // (rotl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVROL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 53567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 53568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF8), |
| 53572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53573 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53574 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53575 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53579 | GIR_RootConstrainSelectedInstOperands, |
| 53580 | // GIR_Coverage, 59761, |
| 53581 | GIR_EraseRootFromParent_Done, |
| 53582 | // Label 3782: @138237 |
| 53583 | GIM_Reject, |
| 53584 | // Label 3780: @138238 |
| 53585 | GIM_Reject, |
| 53586 | // Label 3747: @138239 |
| 53587 | GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(138353), |
| 53588 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 53589 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 53590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53591 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53592 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53593 | GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(138307), // Rule ID 59772 // |
| 53594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53595 | // (rotl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVROL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 53596 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 53597 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53598 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF4), |
| 53601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53602 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53603 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53604 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53608 | GIR_RootConstrainSelectedInstOperands, |
| 53609 | // GIR_Coverage, 59772, |
| 53610 | GIR_EraseRootFromParent_Done, |
| 53611 | // Label 3784: @138307 |
| 53612 | GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(138352), // Rule ID 59773 // |
| 53613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53614 | // (rotl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVROL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 53615 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 53616 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53617 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53618 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF4), |
| 53620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53621 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53622 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53623 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53627 | GIR_RootConstrainSelectedInstOperands, |
| 53628 | // GIR_Coverage, 59773, |
| 53629 | GIR_EraseRootFromParent_Done, |
| 53630 | // Label 3785: @138352 |
| 53631 | GIM_Reject, |
| 53632 | // Label 3783: @138353 |
| 53633 | GIM_Reject, |
| 53634 | // Label 3748: @138354 |
| 53635 | GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(138468), |
| 53636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 53637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 53638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53639 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53640 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53641 | GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(138422), // Rule ID 59780 // |
| 53642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53643 | // (rotl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVROL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 53644 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 53645 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53646 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53647 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF2), |
| 53649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53650 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53651 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53652 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 53655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53656 | GIR_RootConstrainSelectedInstOperands, |
| 53657 | // GIR_Coverage, 59780, |
| 53658 | GIR_EraseRootFromParent_Done, |
| 53659 | // Label 3787: @138422 |
| 53660 | GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(138467), // Rule ID 59781 // |
| 53661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53662 | // (rotl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVROL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 53663 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 53664 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53665 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53666 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF2), |
| 53668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53669 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53670 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53671 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 53674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53675 | GIR_RootConstrainSelectedInstOperands, |
| 53676 | // GIR_Coverage, 59781, |
| 53677 | GIR_EraseRootFromParent_Done, |
| 53678 | // Label 3788: @138467 |
| 53679 | GIM_Reject, |
| 53680 | // Label 3786: @138468 |
| 53681 | GIM_Reject, |
| 53682 | // Label 3749: @138469 |
| 53683 | GIM_Try, /*On fail goto*//*Label 3789*/ GIMT_Encode4(138583), |
| 53684 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 53685 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 53686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53687 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53688 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53689 | GIM_Try, /*On fail goto*//*Label 3790*/ GIMT_Encode4(138537), // Rule ID 59796 // |
| 53690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 53691 | // (rotl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 53692 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 53693 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53694 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 53697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53698 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53699 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53700 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 53703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53704 | GIR_RootConstrainSelectedInstOperands, |
| 53705 | // GIR_Coverage, 59796, |
| 53706 | GIR_EraseRootFromParent_Done, |
| 53707 | // Label 3790: @138537 |
| 53708 | GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(138582), // Rule ID 59797 // |
| 53709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 53710 | // (rotl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 53711 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 53712 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53713 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53714 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 53716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53717 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53718 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53719 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 53722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53723 | GIR_RootConstrainSelectedInstOperands, |
| 53724 | // GIR_Coverage, 59797, |
| 53725 | GIR_EraseRootFromParent_Done, |
| 53726 | // Label 3791: @138582 |
| 53727 | GIM_Reject, |
| 53728 | // Label 3789: @138583 |
| 53729 | GIM_Reject, |
| 53730 | // Label 3750: @138584 |
| 53731 | GIM_Try, /*On fail goto*//*Label 3792*/ GIMT_Encode4(138698), |
| 53732 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 53733 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 53734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53735 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53736 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53737 | GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(138652), // Rule ID 59764 // |
| 53738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53739 | // (rotl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVROL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 53740 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 53741 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53742 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF4), |
| 53745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53746 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53747 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53748 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53752 | GIR_RootConstrainSelectedInstOperands, |
| 53753 | // GIR_Coverage, 59764, |
| 53754 | GIR_EraseRootFromParent_Done, |
| 53755 | // Label 3793: @138652 |
| 53756 | GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(138697), // Rule ID 59765 // |
| 53757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53758 | // (rotl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVROL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 53759 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 53760 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53761 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF4), |
| 53764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53765 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53767 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53771 | GIR_RootConstrainSelectedInstOperands, |
| 53772 | // GIR_Coverage, 59765, |
| 53773 | GIR_EraseRootFromParent_Done, |
| 53774 | // Label 3794: @138697 |
| 53775 | GIM_Reject, |
| 53776 | // Label 3792: @138698 |
| 53777 | GIM_Reject, |
| 53778 | // Label 3751: @138699 |
| 53779 | GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(138813), |
| 53780 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 53781 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 53782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53784 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53785 | GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(138767), // Rule ID 59776 // |
| 53786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53787 | // (rotl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVROL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 53788 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 53789 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53790 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF2), |
| 53793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53794 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53795 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53796 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53800 | GIR_RootConstrainSelectedInstOperands, |
| 53801 | // GIR_Coverage, 59776, |
| 53802 | GIR_EraseRootFromParent_Done, |
| 53803 | // Label 3796: @138767 |
| 53804 | GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(138812), // Rule ID 59777 // |
| 53805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53806 | // (rotl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVROL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 53807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 53808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF2), |
| 53812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53815 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53819 | GIR_RootConstrainSelectedInstOperands, |
| 53820 | // GIR_Coverage, 59777, |
| 53821 | GIR_EraseRootFromParent_Done, |
| 53822 | // Label 3797: @138812 |
| 53823 | GIM_Reject, |
| 53824 | // Label 3795: @138813 |
| 53825 | GIM_Reject, |
| 53826 | // Label 3752: @138814 |
| 53827 | GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(138928), |
| 53828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 53829 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 53830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53833 | GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(138882), // Rule ID 59792 // |
| 53834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53835 | // (rotl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 53836 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 53837 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53838 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 53841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53843 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53844 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 53847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53848 | GIR_RootConstrainSelectedInstOperands, |
| 53849 | // GIR_Coverage, 59792, |
| 53850 | GIR_EraseRootFromParent_Done, |
| 53851 | // Label 3799: @138882 |
| 53852 | GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(138927), // Rule ID 59793 // |
| 53853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53854 | // (rotl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 53855 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 53856 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53857 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 53860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53861 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53862 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53863 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 53866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53867 | GIR_RootConstrainSelectedInstOperands, |
| 53868 | // GIR_Coverage, 59793, |
| 53869 | GIR_EraseRootFromParent_Done, |
| 53870 | // Label 3800: @138927 |
| 53871 | GIM_Reject, |
| 53872 | // Label 3798: @138928 |
| 53873 | GIM_Reject, |
| 53874 | // Label 3753: @138929 |
| 53875 | GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(139043), |
| 53876 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 53877 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 53878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 53879 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 53880 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 53881 | GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(138997), // Rule ID 59836 // |
| 53882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 53883 | // (rotl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 53884 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 53885 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53886 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 53889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53890 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53891 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53892 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 53895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53896 | GIR_RootConstrainSelectedInstOperands, |
| 53897 | // GIR_Coverage, 59836, |
| 53898 | GIR_EraseRootFromParent_Done, |
| 53899 | // Label 3802: @138997 |
| 53900 | GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(139042), // Rule ID 59837 // |
| 53901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 53902 | // (rotl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 53903 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 53904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 53908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53909 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53910 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53911 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 53914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53915 | GIR_RootConstrainSelectedInstOperands, |
| 53916 | // GIR_Coverage, 59837, |
| 53917 | GIR_EraseRootFromParent_Done, |
| 53918 | // Label 3803: @139042 |
| 53919 | GIM_Reject, |
| 53920 | // Label 3801: @139043 |
| 53921 | GIM_Reject, |
| 53922 | // Label 3754: @139044 |
| 53923 | GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(139158), |
| 53924 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 53925 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 53926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53927 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53928 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53929 | GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(139112), // Rule ID 59768 // |
| 53930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53931 | // (rotl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVROL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 53932 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 53933 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53934 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF2), |
| 53937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53938 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53939 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53940 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53944 | GIR_RootConstrainSelectedInstOperands, |
| 53945 | // GIR_Coverage, 59768, |
| 53946 | GIR_EraseRootFromParent_Done, |
| 53947 | // Label 3805: @139112 |
| 53948 | GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(139157), // Rule ID 59769 // |
| 53949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53950 | // (rotl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVROL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 53951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 53952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53953 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_MF2), |
| 53956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53957 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53958 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53959 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53963 | GIR_RootConstrainSelectedInstOperands, |
| 53964 | // GIR_Coverage, 59769, |
| 53965 | GIR_EraseRootFromParent_Done, |
| 53966 | // Label 3806: @139157 |
| 53967 | GIM_Reject, |
| 53968 | // Label 3804: @139158 |
| 53969 | GIM_Reject, |
| 53970 | // Label 3755: @139159 |
| 53971 | GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(139273), |
| 53972 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 53973 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 53974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53976 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 53977 | GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(139227), // Rule ID 59788 // |
| 53978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 53979 | // (rotl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 53980 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 53981 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 53982 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 53983 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 53984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 53985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 53986 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 53987 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 53988 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 53989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 53990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 53991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 53992 | GIR_RootConstrainSelectedInstOperands, |
| 53993 | // GIR_Coverage, 59788, |
| 53994 | GIR_EraseRootFromParent_Done, |
| 53995 | // Label 3808: @139227 |
| 53996 | GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(139272), // Rule ID 59789 // |
| 53997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 53998 | // (rotl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 53999 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 54000 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 54004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54006 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54007 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54011 | GIR_RootConstrainSelectedInstOperands, |
| 54012 | // GIR_Coverage, 59789, |
| 54013 | GIR_EraseRootFromParent_Done, |
| 54014 | // Label 3809: @139272 |
| 54015 | GIM_Reject, |
| 54016 | // Label 3807: @139273 |
| 54017 | GIM_Reject, |
| 54018 | // Label 3756: @139274 |
| 54019 | GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(139388), |
| 54020 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 54021 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 54022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54023 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54024 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54025 | GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(139342), // Rule ID 59824 // |
| 54026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54027 | // (rotl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 54028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 54029 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54030 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 54033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54034 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54035 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54036 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 54039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54040 | GIR_RootConstrainSelectedInstOperands, |
| 54041 | // GIR_Coverage, 59824, |
| 54042 | GIR_EraseRootFromParent_Done, |
| 54043 | // Label 3811: @139342 |
| 54044 | GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(139387), // Rule ID 59825 // |
| 54045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54046 | // (rotl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 54047 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 54048 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54049 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 54052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54053 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54054 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54055 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 54058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54059 | GIR_RootConstrainSelectedInstOperands, |
| 54060 | // GIR_Coverage, 59825, |
| 54061 | GIR_EraseRootFromParent_Done, |
| 54062 | // Label 3812: @139387 |
| 54063 | GIM_Reject, |
| 54064 | // Label 3810: @139388 |
| 54065 | GIM_Reject, |
| 54066 | // Label 3757: @139389 |
| 54067 | GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(139503), |
| 54068 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 54069 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 54070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54071 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54072 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54073 | GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(139457), // Rule ID 59840 // |
| 54074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 54075 | // (rotl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 54076 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 54077 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54078 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54082 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54083 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54084 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 54087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54088 | GIR_RootConstrainSelectedInstOperands, |
| 54089 | // GIR_Coverage, 59840, |
| 54090 | GIR_EraseRootFromParent_Done, |
| 54091 | // Label 3814: @139457 |
| 54092 | GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(139502), // Rule ID 59841 // |
| 54093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 54094 | // (rotl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 54095 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 54096 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54097 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54101 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54102 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54103 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 54106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54107 | GIR_RootConstrainSelectedInstOperands, |
| 54108 | // GIR_Coverage, 59841, |
| 54109 | GIR_EraseRootFromParent_Done, |
| 54110 | // Label 3815: @139502 |
| 54111 | GIM_Reject, |
| 54112 | // Label 3813: @139503 |
| 54113 | GIM_Reject, |
| 54114 | // Label 3758: @139504 |
| 54115 | GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(139618), |
| 54116 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 54117 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 54118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 54119 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 54120 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 54121 | GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(139572), // Rule ID 59784 // |
| 54122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54123 | // (rotl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 54124 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 54125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 54129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54130 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54131 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54132 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54136 | GIR_RootConstrainSelectedInstOperands, |
| 54137 | // GIR_Coverage, 59784, |
| 54138 | GIR_EraseRootFromParent_Done, |
| 54139 | // Label 3817: @139572 |
| 54140 | GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(139617), // Rule ID 59785 // |
| 54141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54142 | // (rotl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVROL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 54143 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 54144 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54145 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M1), |
| 54148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54149 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54150 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54151 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54155 | GIR_RootConstrainSelectedInstOperands, |
| 54156 | // GIR_Coverage, 59785, |
| 54157 | GIR_EraseRootFromParent_Done, |
| 54158 | // Label 3818: @139617 |
| 54159 | GIM_Reject, |
| 54160 | // Label 3816: @139618 |
| 54161 | GIM_Reject, |
| 54162 | // Label 3759: @139619 |
| 54163 | GIM_Try, /*On fail goto*//*Label 3819*/ GIMT_Encode4(139733), |
| 54164 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 54165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 54166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54168 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54169 | GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(139687), // Rule ID 59812 // |
| 54170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54171 | // (rotl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 54172 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 54173 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54174 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 54177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54179 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54180 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54184 | GIR_RootConstrainSelectedInstOperands, |
| 54185 | // GIR_Coverage, 59812, |
| 54186 | GIR_EraseRootFromParent_Done, |
| 54187 | // Label 3820: @139687 |
| 54188 | GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(139732), // Rule ID 59813 // |
| 54189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54190 | // (rotl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 54191 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 54192 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54193 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 54196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54198 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54199 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54203 | GIR_RootConstrainSelectedInstOperands, |
| 54204 | // GIR_Coverage, 59813, |
| 54205 | GIR_EraseRootFromParent_Done, |
| 54206 | // Label 3821: @139732 |
| 54207 | GIM_Reject, |
| 54208 | // Label 3819: @139733 |
| 54209 | GIM_Reject, |
| 54210 | // Label 3760: @139734 |
| 54211 | GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(139848), |
| 54212 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 54213 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 54214 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54215 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54216 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54217 | GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(139802), // Rule ID 59828 // |
| 54218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54219 | // (rotl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 54220 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 54221 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54222 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54223 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54226 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54227 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54228 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 54231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54232 | GIR_RootConstrainSelectedInstOperands, |
| 54233 | // GIR_Coverage, 59828, |
| 54234 | GIR_EraseRootFromParent_Done, |
| 54235 | // Label 3823: @139802 |
| 54236 | GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(139847), // Rule ID 59829 // |
| 54237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54238 | // (rotl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 54239 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 54240 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54241 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54246 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54247 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 54250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54251 | GIR_RootConstrainSelectedInstOperands, |
| 54252 | // GIR_Coverage, 59829, |
| 54253 | GIR_EraseRootFromParent_Done, |
| 54254 | // Label 3824: @139847 |
| 54255 | GIM_Reject, |
| 54256 | // Label 3822: @139848 |
| 54257 | GIM_Reject, |
| 54258 | // Label 3761: @139849 |
| 54259 | GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(139963), |
| 54260 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 54261 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 54262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54263 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54265 | GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(139917), // Rule ID 59844 // |
| 54266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 54267 | // (rotl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 54268 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 54269 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54274 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54275 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54276 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 54279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54280 | GIR_RootConstrainSelectedInstOperands, |
| 54281 | // GIR_Coverage, 59844, |
| 54282 | GIR_EraseRootFromParent_Done, |
| 54283 | // Label 3826: @139917 |
| 54284 | GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(139962), // Rule ID 59845 // |
| 54285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 54286 | // (rotl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 54287 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 54288 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54289 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54290 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54293 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54294 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54295 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 54298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54299 | GIR_RootConstrainSelectedInstOperands, |
| 54300 | // GIR_Coverage, 59845, |
| 54301 | GIR_EraseRootFromParent_Done, |
| 54302 | // Label 3827: @139962 |
| 54303 | GIM_Reject, |
| 54304 | // Label 3825: @139963 |
| 54305 | GIM_Reject, |
| 54306 | // Label 3762: @139964 |
| 54307 | GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(140078), |
| 54308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 54309 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 54310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54311 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54312 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 54313 | GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(140032), // Rule ID 59800 // |
| 54314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54315 | // (rotl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 54316 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 54317 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54318 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 54321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54322 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54323 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54324 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54328 | GIR_RootConstrainSelectedInstOperands, |
| 54329 | // GIR_Coverage, 59800, |
| 54330 | GIR_EraseRootFromParent_Done, |
| 54331 | // Label 3829: @140032 |
| 54332 | GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(140077), // Rule ID 59801 // |
| 54333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54334 | // (rotl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVROL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 54335 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 54336 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54337 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M2), |
| 54340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54342 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54343 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54347 | GIR_RootConstrainSelectedInstOperands, |
| 54348 | // GIR_Coverage, 59801, |
| 54349 | GIR_EraseRootFromParent_Done, |
| 54350 | // Label 3830: @140077 |
| 54351 | GIM_Reject, |
| 54352 | // Label 3828: @140078 |
| 54353 | GIM_Reject, |
| 54354 | // Label 3763: @140079 |
| 54355 | GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(140193), |
| 54356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 54357 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 54358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54361 | GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(140147), // Rule ID 59816 // |
| 54362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54363 | // (rotl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 54364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 54365 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54366 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54371 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54372 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54376 | GIR_RootConstrainSelectedInstOperands, |
| 54377 | // GIR_Coverage, 59816, |
| 54378 | GIR_EraseRootFromParent_Done, |
| 54379 | // Label 3832: @140147 |
| 54380 | GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(140192), // Rule ID 59817 // |
| 54381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54382 | // (rotl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 54383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 54384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54390 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54391 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54395 | GIR_RootConstrainSelectedInstOperands, |
| 54396 | // GIR_Coverage, 59817, |
| 54397 | GIR_EraseRootFromParent_Done, |
| 54398 | // Label 3833: @140192 |
| 54399 | GIM_Reject, |
| 54400 | // Label 3831: @140193 |
| 54401 | GIM_Reject, |
| 54402 | // Label 3764: @140194 |
| 54403 | GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(140308), |
| 54404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 54405 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 54406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54407 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54408 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54409 | GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(140262), // Rule ID 59832 // |
| 54410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54411 | // (rotl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 54412 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 54413 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54414 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54418 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54419 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54420 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 54423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54424 | GIR_RootConstrainSelectedInstOperands, |
| 54425 | // GIR_Coverage, 59832, |
| 54426 | GIR_EraseRootFromParent_Done, |
| 54427 | // Label 3835: @140262 |
| 54428 | GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(140307), // Rule ID 59833 // |
| 54429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54430 | // (rotl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 54431 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 54432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54433 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54438 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54439 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 54442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54443 | GIR_RootConstrainSelectedInstOperands, |
| 54444 | // GIR_Coverage, 59833, |
| 54445 | GIR_EraseRootFromParent_Done, |
| 54446 | // Label 3836: @140307 |
| 54447 | GIM_Reject, |
| 54448 | // Label 3834: @140308 |
| 54449 | GIM_Reject, |
| 54450 | // Label 3765: @140309 |
| 54451 | GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(140423), |
| 54452 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 54453 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 54454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54455 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54456 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 54457 | GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(140377), // Rule ID 59804 // |
| 54458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54459 | // (rotl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 54460 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 54461 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54462 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54466 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54467 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54468 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54472 | GIR_RootConstrainSelectedInstOperands, |
| 54473 | // GIR_Coverage, 59804, |
| 54474 | GIR_EraseRootFromParent_Done, |
| 54475 | // Label 3838: @140377 |
| 54476 | GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(140422), // Rule ID 59805 // |
| 54477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54478 | // (rotl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVROL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 54479 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 54480 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54481 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M4), |
| 54484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54485 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54486 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54487 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54491 | GIR_RootConstrainSelectedInstOperands, |
| 54492 | // GIR_Coverage, 59805, |
| 54493 | GIR_EraseRootFromParent_Done, |
| 54494 | // Label 3839: @140422 |
| 54495 | GIM_Reject, |
| 54496 | // Label 3837: @140423 |
| 54497 | GIM_Reject, |
| 54498 | // Label 3766: @140424 |
| 54499 | GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(140538), |
| 54500 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 54501 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 54502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54504 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54505 | GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(140492), // Rule ID 59820 // |
| 54506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54507 | // (rotl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 54508 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 54509 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54510 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54514 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54515 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54516 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54520 | GIR_RootConstrainSelectedInstOperands, |
| 54521 | // GIR_Coverage, 59820, |
| 54522 | GIR_EraseRootFromParent_Done, |
| 54523 | // Label 3841: @140492 |
| 54524 | GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(140537), // Rule ID 59821 // |
| 54525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54526 | // (rotl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 54527 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 54528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54529 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54534 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54535 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 54538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54539 | GIR_RootConstrainSelectedInstOperands, |
| 54540 | // GIR_Coverage, 59821, |
| 54541 | GIR_EraseRootFromParent_Done, |
| 54542 | // Label 3842: @140537 |
| 54543 | GIM_Reject, |
| 54544 | // Label 3840: @140538 |
| 54545 | GIM_Reject, |
| 54546 | // Label 3767: @140539 |
| 54547 | GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(140653), |
| 54548 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 54549 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 54550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54551 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54552 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 54553 | GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(140607), // Rule ID 59808 // |
| 54554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 54555 | // (rotl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 54556 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 54557 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54562 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54563 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54564 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54568 | GIR_RootConstrainSelectedInstOperands, |
| 54569 | // GIR_Coverage, 59808, |
| 54570 | GIR_EraseRootFromParent_Done, |
| 54571 | // Label 3844: @140607 |
| 54572 | GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(140652), // Rule ID 59809 // |
| 54573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 54574 | // (rotl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVROL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 54575 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 54576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 54577 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVROL_VV_M8), |
| 54580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54581 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54582 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 54583 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 54584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 54587 | GIR_RootConstrainSelectedInstOperands, |
| 54588 | // GIR_Coverage, 59809, |
| 54589 | GIR_EraseRootFromParent_Done, |
| 54590 | // Label 3845: @140652 |
| 54591 | GIM_Reject, |
| 54592 | // Label 3843: @140653 |
| 54593 | GIM_Reject, |
| 54594 | // Label 3768: @140654 |
| 54595 | GIM_Reject, |
| 54596 | // Label 44: @140655 |
| 54597 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(33), /*)*//*default:*//*Label 3855*/ GIMT_Encode4(167317), |
| 54598 | /*GILLT_s32*//*Label 3846*/ GIMT_Encode4(140786), |
| 54599 | /*GILLT_s64*//*Label 3847*/ GIMT_Encode4(143580), |
| 54600 | /*GILLT_nxv1s1*//*Label 3848*/ GIMT_Encode4(146374), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 54601 | /*GILLT_nxv2s1*//*Label 3849*/ GIMT_Encode4(150215), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 54602 | /*GILLT_nxv4s1*//*Label 3850*/ GIMT_Encode4(154056), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 54603 | /*GILLT_nxv8s1*//*Label 3851*/ GIMT_Encode4(157897), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 54604 | /*GILLT_nxv16s1*//*Label 3852*/ GIMT_Encode4(161738), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 54605 | /*GILLT_nxv32s1*//*Label 3853*/ GIMT_Encode4(164619), GIMT_Encode4(0), GIMT_Encode4(0), |
| 54606 | /*GILLT_nxv64s1*//*Label 3854*/ GIMT_Encode4(166540), |
| 54607 | // Label 3846: @140786 |
| 54608 | GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(140829), // Rule ID 148 // |
| 54609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54611 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54613 | // MIs[0] Operand 1 |
| 54614 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 54615 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54616 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, uint8_t(-1), |
| 54617 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }) |
| 54618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54620 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 54622 | GIR_RootConstrainSelectedInstOperands, |
| 54623 | // GIR_Coverage, 148, |
| 54624 | GIR_EraseRootFromParent_Done, |
| 54625 | // Label 3856: @140829 |
| 54626 | GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(140872), // Rule ID 65060 // |
| 54627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54628 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54629 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 54630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54631 | // MIs[0] Operand 1 |
| 54632 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 54633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54634 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 54635 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }) |
| 54636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54640 | GIR_RootConstrainSelectedInstOperands, |
| 54641 | // GIR_Coverage, 65060, |
| 54642 | GIR_EraseRootFromParent_Done, |
| 54643 | // Label 3857: @140872 |
| 54644 | GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(140918), // Rule ID 65066 // |
| 54645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54646 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54647 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 54648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54649 | // MIs[0] Operand 1 |
| 54650 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 54651 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54652 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 54653 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1) |
| 54654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 54655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54656 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 54657 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54658 | GIR_RootConstrainSelectedInstOperands, |
| 54659 | // GIR_Coverage, 65066, |
| 54660 | GIR_EraseRootFromParent_Done, |
| 54661 | // Label 3858: @140918 |
| 54662 | GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(140961), // Rule ID 65096 // |
| 54663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54664 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54665 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54667 | // MIs[0] Operand 1 |
| 54668 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 54669 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54670 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 54671 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }) |
| 54672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54674 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54676 | GIR_RootConstrainSelectedInstOperands, |
| 54677 | // GIR_Coverage, 65096, |
| 54678 | GIR_EraseRootFromParent_Done, |
| 54679 | // Label 3859: @140961 |
| 54680 | GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(141007), // Rule ID 65102 // |
| 54681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54682 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54683 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54685 | // MIs[0] Operand 1 |
| 54686 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 54687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54688 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 54689 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1) |
| 54690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 54691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54692 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 54693 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54694 | GIR_RootConstrainSelectedInstOperands, |
| 54695 | // GIR_Coverage, 65102, |
| 54696 | GIR_EraseRootFromParent_Done, |
| 54697 | // Label 3860: @141007 |
| 54698 | GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(141060), // Rule ID 138 // |
| 54699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54701 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54703 | // MIs[0] Operand 1 |
| 54704 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 54705 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54706 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54707 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54708 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 54709 | // MIs[1] Operand 1 |
| 54710 | // No operand predicates |
| 54711 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54712 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) |
| 54713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 54714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54715 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54716 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 54717 | GIR_RootConstrainSelectedInstOperands, |
| 54718 | // GIR_Coverage, 138, |
| 54719 | GIR_EraseRootFromParent_Done, |
| 54720 | // Label 3861: @141060 |
| 54721 | GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(141113), // Rule ID 142 // |
| 54722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54723 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54724 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54726 | // MIs[0] Operand 1 |
| 54727 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 54728 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54729 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54730 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54731 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 54732 | // MIs[1] Operand 1 |
| 54733 | // No operand predicates |
| 54734 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54735 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) |
| 54736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54738 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54739 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 54740 | GIR_RootConstrainSelectedInstOperands, |
| 54741 | // GIR_Coverage, 142, |
| 54742 | GIR_EraseRootFromParent_Done, |
| 54743 | // Label 3862: @141113 |
| 54744 | GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(141166), // Rule ID 65052 // |
| 54745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54746 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54747 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54749 | // MIs[0] Operand 1 |
| 54750 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 54751 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54752 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54753 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54754 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 54755 | // MIs[1] Operand 1 |
| 54756 | // No operand predicates |
| 54757 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54758 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 54759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54761 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54762 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 |
| 54763 | GIR_RootConstrainSelectedInstOperands, |
| 54764 | // GIR_Coverage, 65052, |
| 54765 | GIR_EraseRootFromParent_Done, |
| 54766 | // Label 3863: @141166 |
| 54767 | GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(141219), // Rule ID 65056 // |
| 54768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54769 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54770 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54772 | // MIs[0] Operand 1 |
| 54773 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 54774 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54775 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54776 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54777 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 54778 | // MIs[1] Operand 1 |
| 54779 | // No operand predicates |
| 54780 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54781 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) |
| 54782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 54783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54784 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54785 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 |
| 54786 | GIR_RootConstrainSelectedInstOperands, |
| 54787 | // GIR_Coverage, 65056, |
| 54788 | GIR_EraseRootFromParent_Done, |
| 54789 | // Label 3864: @141219 |
| 54790 | GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(141296), // Rule ID 65062 // |
| 54791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54792 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54793 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54795 | // MIs[0] Operand 1 |
| 54796 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 54797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54800 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 54801 | // MIs[1] Operand 1 |
| 54802 | // No operand predicates |
| 54803 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54804 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12)), 1:{ *:[i32] }) |
| 54805 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 54806 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 54807 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54808 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 54809 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 54810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54815 | GIR_RootConstrainSelectedInstOperands, |
| 54816 | // GIR_Coverage, 65062, |
| 54817 | GIR_EraseRootFromParent_Done, |
| 54818 | // Label 3865: @141296 |
| 54819 | GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(141376), // Rule ID 65068 // |
| 54820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54821 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54822 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54824 | // MIs[0] Operand 1 |
| 54825 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 54826 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54827 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54828 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54829 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 54830 | // MIs[1] Operand 1 |
| 54831 | // No operand predicates |
| 54832 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54833 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12))) |
| 54834 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 54835 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 54836 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54837 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 54838 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 54839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 54841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54842 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 54843 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54844 | GIR_RootConstrainSelectedInstOperands, |
| 54845 | // GIR_Coverage, 65068, |
| 54846 | GIR_EraseRootFromParent_Done, |
| 54847 | // Label 3866: @141376 |
| 54848 | GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(141453), // Rule ID 65072 // |
| 54849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54851 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54853 | // MIs[0] Operand 1 |
| 54854 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 54855 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54856 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54857 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54858 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 54859 | // MIs[1] Operand 1 |
| 54860 | // No operand predicates |
| 54861 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54862 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETUGT:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)), 1:{ *:[i32] }) |
| 54863 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 54864 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54865 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54866 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 54867 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 54868 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 54870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54871 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54873 | GIR_RootConstrainSelectedInstOperands, |
| 54874 | // GIR_Coverage, 65072, |
| 54875 | GIR_EraseRootFromParent_Done, |
| 54876 | // Label 3867: @141453 |
| 54877 | GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(141530), // Rule ID 65076 // |
| 54878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54879 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54880 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54882 | // MIs[0] Operand 1 |
| 54883 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 54884 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54885 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54886 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54887 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 54888 | // MIs[1] Operand 1 |
| 54889 | // No operand predicates |
| 54890 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54891 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETGT:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)), 1:{ *:[i32] }) |
| 54892 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 54893 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 54894 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54895 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 54896 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 54897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 54899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54900 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54902 | GIR_RootConstrainSelectedInstOperands, |
| 54903 | // GIR_Coverage, 65076, |
| 54904 | GIR_EraseRootFromParent_Done, |
| 54905 | // Label 3868: @141530 |
| 54906 | GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(141605), // Rule ID 65080 // |
| 54907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54908 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54909 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54911 | // MIs[0] Operand 1 |
| 54912 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 54913 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54914 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54915 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54916 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 54917 | // MIs[1] Operand 1 |
| 54918 | // No operand predicates |
| 54919 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54920 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i32] }) |
| 54921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 54922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54923 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54924 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 54925 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 54926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 54928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54929 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54931 | GIR_RootConstrainSelectedInstOperands, |
| 54932 | // GIR_Coverage, 65080, |
| 54933 | GIR_EraseRootFromParent_Done, |
| 54934 | // Label 3869: @141605 |
| 54935 | GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(141680), // Rule ID 65084 // |
| 54936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54937 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54938 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54940 | // MIs[0] Operand 1 |
| 54941 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 54942 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54943 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54944 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54945 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 54946 | // MIs[1] Operand 1 |
| 54947 | // No operand predicates |
| 54948 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54949 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i32] }) |
| 54950 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 54951 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 54952 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 54953 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 54954 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 54955 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 54956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 54957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54958 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 54959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54960 | GIR_RootConstrainSelectedInstOperands, |
| 54961 | // GIR_Coverage, 65084, |
| 54962 | GIR_EraseRootFromParent_Done, |
| 54963 | // Label 3870: @141680 |
| 54964 | GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(141735), // Rule ID 65088 // |
| 54965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54966 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54967 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54969 | // MIs[0] Operand 1 |
| 54970 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 54971 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54972 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54973 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54974 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 54975 | // MIs[1] Operand 1 |
| 54976 | // No operand predicates |
| 54977 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 54978 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETULE:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)) |
| 54979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 54980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 54981 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 54982 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 54983 | GIR_RootConstrainSelectedInstOperands, |
| 54984 | // GIR_Coverage, 65088, |
| 54985 | GIR_EraseRootFromParent_Done, |
| 54986 | // Label 3871: @141735 |
| 54987 | GIM_Try, /*On fail goto*//*Label 3872*/ GIMT_Encode4(141790), // Rule ID 65092 // |
| 54988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 54989 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 54990 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 54991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54992 | // MIs[0] Operand 1 |
| 54993 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 54994 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 54995 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54996 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 54997 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 54998 | // MIs[1] Operand 1 |
| 54999 | // No operand predicates |
| 55000 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55001 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETLE:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)) |
| 55002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55004 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55005 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55006 | GIR_RootConstrainSelectedInstOperands, |
| 55007 | // GIR_Coverage, 65092, |
| 55008 | GIR_EraseRootFromParent_Done, |
| 55009 | // Label 3872: @141790 |
| 55010 | GIM_Try, /*On fail goto*//*Label 3873*/ GIMT_Encode4(141867), // Rule ID 65098 // |
| 55011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55012 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55013 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55015 | // MIs[0] Operand 1 |
| 55016 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 55017 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55018 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55019 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55020 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 55021 | // MIs[1] Operand 1 |
| 55022 | // No operand predicates |
| 55023 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55024 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12)), 1:{ *:[i32] }) |
| 55025 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55026 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 55027 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55028 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55029 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 55030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55033 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55035 | GIR_RootConstrainSelectedInstOperands, |
| 55036 | // GIR_Coverage, 65098, |
| 55037 | GIR_EraseRootFromParent_Done, |
| 55038 | // Label 3873: @141867 |
| 55039 | GIM_Try, /*On fail goto*//*Label 3874*/ GIMT_Encode4(141947), // Rule ID 65104 // |
| 55040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55041 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55042 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55044 | // MIs[0] Operand 1 |
| 55045 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55046 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55049 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 55050 | // MIs[1] Operand 1 |
| 55051 | // No operand predicates |
| 55052 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55053 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm12))) |
| 55054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 55056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55057 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55058 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 55059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55062 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 55063 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55064 | GIR_RootConstrainSelectedInstOperands, |
| 55065 | // GIR_Coverage, 65104, |
| 55066 | GIR_EraseRootFromParent_Done, |
| 55067 | // Label 3874: @141947 |
| 55068 | GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(142024), // Rule ID 65108 // |
| 55069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55070 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55071 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55073 | // MIs[0] Operand 1 |
| 55074 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 55075 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55076 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55077 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55078 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 55079 | // MIs[1] Operand 1 |
| 55080 | // No operand predicates |
| 55081 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55082 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETUGT:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)), 1:{ *:[i32] }) |
| 55083 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55084 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55085 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55086 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55087 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55091 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55093 | GIR_RootConstrainSelectedInstOperands, |
| 55094 | // GIR_Coverage, 65108, |
| 55095 | GIR_EraseRootFromParent_Done, |
| 55096 | // Label 3875: @142024 |
| 55097 | GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(142101), // Rule ID 65112 // |
| 55098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55099 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55100 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55102 | // MIs[0] Operand 1 |
| 55103 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 55104 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55106 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55107 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 55108 | // MIs[1] Operand 1 |
| 55109 | // No operand predicates |
| 55110 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55111 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETGT:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)), 1:{ *:[i32] }) |
| 55112 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55113 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55114 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55115 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55116 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55120 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55122 | GIR_RootConstrainSelectedInstOperands, |
| 55123 | // GIR_Coverage, 65112, |
| 55124 | GIR_EraseRootFromParent_Done, |
| 55125 | // Label 3876: @142101 |
| 55126 | GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(142176), // Rule ID 65116 // |
| 55127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55129 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55131 | // MIs[0] Operand 1 |
| 55132 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 55133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55134 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55135 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55136 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 55137 | // MIs[1] Operand 1 |
| 55138 | // No operand predicates |
| 55139 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55140 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i32] }) |
| 55141 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55142 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55143 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55144 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55145 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 55146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55149 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55151 | GIR_RootConstrainSelectedInstOperands, |
| 55152 | // GIR_Coverage, 65116, |
| 55153 | GIR_EraseRootFromParent_Done, |
| 55154 | // Label 3877: @142176 |
| 55155 | GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(142251), // Rule ID 65120 // |
| 55156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55157 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55158 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55160 | // MIs[0] Operand 1 |
| 55161 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 55162 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55163 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55164 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55165 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 55166 | // MIs[1] Operand 1 |
| 55167 | // No operand predicates |
| 55168 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55169 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i32] }) |
| 55170 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55171 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55172 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55173 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55174 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 55175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55180 | GIR_RootConstrainSelectedInstOperands, |
| 55181 | // GIR_Coverage, 65120, |
| 55182 | GIR_EraseRootFromParent_Done, |
| 55183 | // Label 3878: @142251 |
| 55184 | GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(142306), // Rule ID 65124 // |
| 55185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55187 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55189 | // MIs[0] Operand 1 |
| 55190 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 55191 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55192 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55193 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55194 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 55195 | // MIs[1] Operand 1 |
| 55196 | // No operand predicates |
| 55197 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55198 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETULE:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)) |
| 55199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55201 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55202 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55203 | GIR_RootConstrainSelectedInstOperands, |
| 55204 | // GIR_Coverage, 65124, |
| 55205 | GIR_EraseRootFromParent_Done, |
| 55206 | // Label 3879: @142306 |
| 55207 | GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(142361), // Rule ID 65128 // |
| 55208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55209 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55210 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55212 | // MIs[0] Operand 1 |
| 55213 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 55214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55215 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55216 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55217 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 55218 | // MIs[1] Operand 1 |
| 55219 | // No operand predicates |
| 55220 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55221 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETLE:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (ImmPlus1:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)) |
| 55222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55224 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55225 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55226 | GIR_RootConstrainSelectedInstOperands, |
| 55227 | // GIR_Coverage, 65128, |
| 55228 | GIR_EraseRootFromParent_Done, |
| 55229 | // Label 3880: @142361 |
| 55230 | GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(142403), // Rule ID 64976 // |
| 55231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 55232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55233 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55235 | // MIs[0] Operand 1 |
| 55236 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 55237 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55238 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55239 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (CV_SLET:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 55240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SLET), |
| 55241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55242 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55243 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55244 | GIR_RootConstrainSelectedInstOperands, |
| 55245 | // GIR_Coverage, 64976, |
| 55246 | GIR_EraseRootFromParent_Done, |
| 55247 | // Label 3881: @142403 |
| 55248 | GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(142445), // Rule ID 64978 // |
| 55249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 55250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55251 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55253 | // MIs[0] Operand 1 |
| 55254 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 55255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55256 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55257 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (CV_SLETU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 55258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SLETU), |
| 55259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55260 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55261 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55262 | GIR_RootConstrainSelectedInstOperands, |
| 55263 | // GIR_Coverage, 64978, |
| 55264 | GIR_EraseRootFromParent_Done, |
| 55265 | // Label 3882: @142445 |
| 55266 | GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(142487), // Rule ID 136 // |
| 55267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55268 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55269 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55271 | // MIs[0] Operand 1 |
| 55272 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 55273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55275 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 55276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55278 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55279 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55280 | GIR_RootConstrainSelectedInstOperands, |
| 55281 | // GIR_Coverage, 136, |
| 55282 | GIR_EraseRootFromParent_Done, |
| 55283 | // Label 3883: @142487 |
| 55284 | GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(142529), // Rule ID 140 // |
| 55285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55286 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55287 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55289 | // MIs[0] Operand 1 |
| 55290 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 55291 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55292 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55293 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 55294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55297 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55298 | GIR_RootConstrainSelectedInstOperands, |
| 55299 | // GIR_Coverage, 140, |
| 55300 | GIR_EraseRootFromParent_Done, |
| 55301 | // Label 3884: @142529 |
| 55302 | GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(142571), // Rule ID 65054 // |
| 55303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55305 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55307 | // MIs[0] Operand 1 |
| 55308 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 55309 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55310 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55311 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 55312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55314 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55315 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55316 | GIR_RootConstrainSelectedInstOperands, |
| 55317 | // GIR_Coverage, 65054, |
| 55318 | GIR_EraseRootFromParent_Done, |
| 55319 | // Label 3885: @142571 |
| 55320 | GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(142613), // Rule ID 65058 // |
| 55321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55322 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55323 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55325 | // MIs[0] Operand 1 |
| 55326 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 55327 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55328 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55329 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 55330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55332 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55333 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55334 | GIR_RootConstrainSelectedInstOperands, |
| 55335 | // GIR_Coverage, 65058, |
| 55336 | GIR_EraseRootFromParent_Done, |
| 55337 | // Label 3886: @142613 |
| 55338 | GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(142679), // Rule ID 65064 // |
| 55339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55340 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55341 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55343 | // MIs[0] Operand 1 |
| 55344 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 55345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55346 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55347 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) |
| 55348 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55349 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 55350 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55351 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55352 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55356 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55358 | GIR_RootConstrainSelectedInstOperands, |
| 55359 | // GIR_Coverage, 65064, |
| 55360 | GIR_EraseRootFromParent_Done, |
| 55361 | // Label 3887: @142679 |
| 55362 | GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(142748), // Rule ID 65070 // |
| 55363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55364 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55365 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55367 | // MIs[0] Operand 1 |
| 55368 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55369 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55370 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55371 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) |
| 55372 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55373 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 55374 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55375 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55376 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55380 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 55381 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55382 | GIR_RootConstrainSelectedInstOperands, |
| 55383 | // GIR_Coverage, 65070, |
| 55384 | GIR_EraseRootFromParent_Done, |
| 55385 | // Label 3888: @142748 |
| 55386 | GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(142790), // Rule ID 65074 // |
| 55387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55388 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55389 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55391 | // MIs[0] Operand 1 |
| 55392 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 55393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55394 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55395 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 55396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55398 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55399 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55400 | GIR_RootConstrainSelectedInstOperands, |
| 55401 | // GIR_Coverage, 65074, |
| 55402 | GIR_EraseRootFromParent_Done, |
| 55403 | // Label 3889: @142790 |
| 55404 | GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(142832), // Rule ID 65078 // |
| 55405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55406 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55407 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55409 | // MIs[0] Operand 1 |
| 55410 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 55411 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55412 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55413 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 55414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55416 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55417 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55418 | GIR_RootConstrainSelectedInstOperands, |
| 55419 | // GIR_Coverage, 65078, |
| 55420 | GIR_EraseRootFromParent_Done, |
| 55421 | // Label 3890: @142832 |
| 55422 | GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(142898), // Rule ID 65082 // |
| 55423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55424 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55425 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55427 | // MIs[0] Operand 1 |
| 55428 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 55429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55430 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55431 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) |
| 55432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55433 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55434 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55435 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55436 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55437 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55440 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55442 | GIR_RootConstrainSelectedInstOperands, |
| 55443 | // GIR_Coverage, 65082, |
| 55444 | GIR_EraseRootFromParent_Done, |
| 55445 | // Label 3891: @142898 |
| 55446 | GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(142964), // Rule ID 65086 // |
| 55447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55448 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55449 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55451 | // MIs[0] Operand 1 |
| 55452 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 55453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55454 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55455 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) |
| 55456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55459 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55460 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55464 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55466 | GIR_RootConstrainSelectedInstOperands, |
| 55467 | // GIR_Coverage, 65086, |
| 55468 | GIR_EraseRootFromParent_Done, |
| 55469 | // Label 3892: @142964 |
| 55470 | GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(143030), // Rule ID 65090 // |
| 55471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55473 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55475 | // MIs[0] Operand 1 |
| 55476 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 55477 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55478 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55479 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) |
| 55480 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55481 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55482 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55483 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55484 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55488 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55490 | GIR_RootConstrainSelectedInstOperands, |
| 55491 | // GIR_Coverage, 65090, |
| 55492 | GIR_EraseRootFromParent_Done, |
| 55493 | // Label 3893: @143030 |
| 55494 | GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(143096), // Rule ID 65094 // |
| 55495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, |
| 55497 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s32, |
| 55498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55499 | // MIs[0] Operand 1 |
| 55500 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 55501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55502 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55503 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) |
| 55504 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55505 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55506 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55507 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55508 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55514 | GIR_RootConstrainSelectedInstOperands, |
| 55515 | // GIR_Coverage, 65094, |
| 55516 | GIR_EraseRootFromParent_Done, |
| 55517 | // Label 3894: @143096 |
| 55518 | GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(143162), // Rule ID 65100 // |
| 55519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55523 | // MIs[0] Operand 1 |
| 55524 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 55525 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55526 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55527 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) |
| 55528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 55530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55531 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55532 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55533 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55536 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55538 | GIR_RootConstrainSelectedInstOperands, |
| 55539 | // GIR_Coverage, 65100, |
| 55540 | GIR_EraseRootFromParent_Done, |
| 55541 | // Label 3895: @143162 |
| 55542 | GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(143231), // Rule ID 65106 // |
| 55543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55544 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55545 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55547 | // MIs[0] Operand 1 |
| 55548 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55549 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55550 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55551 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) |
| 55552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 55554 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55555 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55556 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55557 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55560 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 55561 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55562 | GIR_RootConstrainSelectedInstOperands, |
| 55563 | // GIR_Coverage, 65106, |
| 55564 | GIR_EraseRootFromParent_Done, |
| 55565 | // Label 3896: @143231 |
| 55566 | GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(143273), // Rule ID 65110 // |
| 55567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55569 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55571 | // MIs[0] Operand 1 |
| 55572 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 55573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55574 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55575 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 55576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55578 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55579 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55580 | GIR_RootConstrainSelectedInstOperands, |
| 55581 | // GIR_Coverage, 65110, |
| 55582 | GIR_EraseRootFromParent_Done, |
| 55583 | // Label 3897: @143273 |
| 55584 | GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(143315), // Rule ID 65114 // |
| 55585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55586 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55587 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55589 | // MIs[0] Operand 1 |
| 55590 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 55591 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55592 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55593 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) |
| 55594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55596 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 55597 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55598 | GIR_RootConstrainSelectedInstOperands, |
| 55599 | // GIR_Coverage, 65114, |
| 55600 | GIR_EraseRootFromParent_Done, |
| 55601 | // Label 3898: @143315 |
| 55602 | GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(143381), // Rule ID 65118 // |
| 55603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55607 | // MIs[0] Operand 1 |
| 55608 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 55609 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55610 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55611 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) |
| 55612 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55615 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55616 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55622 | GIR_RootConstrainSelectedInstOperands, |
| 55623 | // GIR_Coverage, 65118, |
| 55624 | GIR_EraseRootFromParent_Done, |
| 55625 | // Label 3899: @143381 |
| 55626 | GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(143447), // Rule ID 65122 // |
| 55627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55628 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55629 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55631 | // MIs[0] Operand 1 |
| 55632 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 55633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55634 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55635 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) |
| 55636 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55638 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55639 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55640 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55646 | GIR_RootConstrainSelectedInstOperands, |
| 55647 | // GIR_Coverage, 65122, |
| 55648 | GIR_EraseRootFromParent_Done, |
| 55649 | // Label 3900: @143447 |
| 55650 | GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(143513), // Rule ID 65126 // |
| 55651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55652 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55653 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55655 | // MIs[0] Operand 1 |
| 55656 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 55657 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55658 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55659 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) |
| 55660 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55663 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55664 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55668 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55670 | GIR_RootConstrainSelectedInstOperands, |
| 55671 | // GIR_Coverage, 65126, |
| 55672 | GIR_EraseRootFromParent_Done, |
| 55673 | // Label 3901: @143513 |
| 55674 | GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(143579), // Rule ID 65130 // |
| 55675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), |
| 55676 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 55678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55679 | // MIs[0] Operand 1 |
| 55680 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 55681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55682 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55683 | // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) |
| 55684 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55685 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 55686 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55687 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 55688 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55692 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55694 | GIR_RootConstrainSelectedInstOperands, |
| 55695 | // GIR_Coverage, 65130, |
| 55696 | GIR_EraseRootFromParent_Done, |
| 55697 | // Label 3902: @143579 |
| 55698 | GIM_Reject, |
| 55699 | // Label 3847: @143580 |
| 55700 | GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(143623), // Rule ID 147 // |
| 55701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55702 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55703 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55705 | // MIs[0] Operand 1 |
| 55706 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55708 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, uint8_t(-1), |
| 55709 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }) |
| 55710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55712 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 55714 | GIR_RootConstrainSelectedInstOperands, |
| 55715 | // GIR_Coverage, 147, |
| 55716 | GIR_EraseRootFromParent_Done, |
| 55717 | // Label 3903: @143623 |
| 55718 | GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(143666), // Rule ID 65059 // |
| 55719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55720 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55721 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 55722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55723 | // MIs[0] Operand 1 |
| 55724 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 55725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55726 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 55727 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }) |
| 55728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55730 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55732 | GIR_RootConstrainSelectedInstOperands, |
| 55733 | // GIR_Coverage, 65059, |
| 55734 | GIR_EraseRootFromParent_Done, |
| 55735 | // Label 3904: @143666 |
| 55736 | GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(143712), // Rule ID 65065 // |
| 55737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55738 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55739 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 55740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55741 | // MIs[0] Operand 1 |
| 55742 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55743 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55744 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 55745 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1) |
| 55746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55748 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 55749 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55750 | GIR_RootConstrainSelectedInstOperands, |
| 55751 | // GIR_Coverage, 65065, |
| 55752 | GIR_EraseRootFromParent_Done, |
| 55753 | // Label 3905: @143712 |
| 55754 | GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(143755), // Rule ID 65095 // |
| 55755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55756 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55757 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55759 | // MIs[0] Operand 1 |
| 55760 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 55761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55762 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 55763 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }) |
| 55764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55766 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55768 | GIR_RootConstrainSelectedInstOperands, |
| 55769 | // GIR_Coverage, 65095, |
| 55770 | GIR_EraseRootFromParent_Done, |
| 55771 | // Label 3906: @143755 |
| 55772 | GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(143801), // Rule ID 65101 // |
| 55773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55774 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55775 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55777 | // MIs[0] Operand 1 |
| 55778 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55780 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 55781 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1) |
| 55782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55784 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 55785 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55786 | GIR_RootConstrainSelectedInstOperands, |
| 55787 | // GIR_Coverage, 65101, |
| 55788 | GIR_EraseRootFromParent_Done, |
| 55789 | // Label 3907: @143801 |
| 55790 | GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(143854), // Rule ID 137 // |
| 55791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55792 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55793 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55795 | // MIs[0] Operand 1 |
| 55796 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 55797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55800 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 55801 | // MIs[1] Operand 1 |
| 55802 | // No operand predicates |
| 55803 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55804 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETLT:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) |
| 55805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55807 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55808 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 55809 | GIR_RootConstrainSelectedInstOperands, |
| 55810 | // GIR_Coverage, 137, |
| 55811 | GIR_EraseRootFromParent_Done, |
| 55812 | // Label 3908: @143854 |
| 55813 | GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(143907), // Rule ID 141 // |
| 55814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55815 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55816 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55818 | // MIs[0] Operand 1 |
| 55819 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 55820 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55821 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55822 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55823 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 55824 | // MIs[1] Operand 1 |
| 55825 | // No operand predicates |
| 55826 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55827 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) |
| 55828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55830 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55831 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 55832 | GIR_RootConstrainSelectedInstOperands, |
| 55833 | // GIR_Coverage, 141, |
| 55834 | GIR_EraseRootFromParent_Done, |
| 55835 | // Label 3909: @143907 |
| 55836 | GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(143960), // Rule ID 65051 // |
| 55837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55839 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55841 | // MIs[0] Operand 1 |
| 55842 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 55843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55844 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55845 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55846 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 55847 | // MIs[1] Operand 1 |
| 55848 | // No operand predicates |
| 55849 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55850 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 55851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55853 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55854 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 |
| 55855 | GIR_RootConstrainSelectedInstOperands, |
| 55856 | // GIR_Coverage, 65051, |
| 55857 | GIR_EraseRootFromParent_Done, |
| 55858 | // Label 3910: @143960 |
| 55859 | GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(144013), // Rule ID 65055 // |
| 55860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55861 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55862 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55864 | // MIs[0] Operand 1 |
| 55865 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 55866 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55867 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55868 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55869 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 55870 | // MIs[1] Operand 1 |
| 55871 | // No operand predicates |
| 55872 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55873 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) |
| 55874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55876 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 55877 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 |
| 55878 | GIR_RootConstrainSelectedInstOperands, |
| 55879 | // GIR_Coverage, 65055, |
| 55880 | GIR_EraseRootFromParent_Done, |
| 55881 | // Label 3911: @144013 |
| 55882 | GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(144090), // Rule ID 65061 // |
| 55883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55885 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55887 | // MIs[0] Operand 1 |
| 55888 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 55889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55890 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55891 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55892 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 55893 | // MIs[1] Operand 1 |
| 55894 | // No operand predicates |
| 55895 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55896 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (ADDI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (NegImm:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12)), 1:{ *:[i64] }) |
| 55897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55898 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 55899 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55900 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55901 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 55902 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55905 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55907 | GIR_RootConstrainSelectedInstOperands, |
| 55908 | // GIR_Coverage, 65061, |
| 55909 | GIR_EraseRootFromParent_Done, |
| 55910 | // Label 3912: @144090 |
| 55911 | GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(144170), // Rule ID 65067 // |
| 55912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55913 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55914 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55916 | // MIs[0] Operand 1 |
| 55917 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 55918 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55920 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55921 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 55922 | // MIs[1] Operand 1 |
| 55923 | // No operand predicates |
| 55924 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55925 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (ADDI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (NegImm:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12))) |
| 55926 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55927 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 55928 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55929 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55930 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 55931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 55933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55934 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 55935 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55936 | GIR_RootConstrainSelectedInstOperands, |
| 55937 | // GIR_Coverage, 65067, |
| 55938 | GIR_EraseRootFromParent_Done, |
| 55939 | // Label 3913: @144170 |
| 55940 | GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(144247), // Rule ID 65071 // |
| 55941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55942 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55943 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55945 | // MIs[0] Operand 1 |
| 55946 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 55947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55948 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55949 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55950 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 55951 | // MIs[1] Operand 1 |
| 55952 | // No operand predicates |
| 55953 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55954 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETUGT:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTIU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)), 1:{ *:[i64] }) |
| 55955 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55956 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 55957 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55958 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55959 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55963 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55965 | GIR_RootConstrainSelectedInstOperands, |
| 55966 | // GIR_Coverage, 65071, |
| 55967 | GIR_EraseRootFromParent_Done, |
| 55968 | // Label 3914: @144247 |
| 55969 | GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(144324), // Rule ID 65075 // |
| 55970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 55971 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 55972 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 55973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55974 | // MIs[0] Operand 1 |
| 55975 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 55976 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 55977 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55978 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 55979 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 55980 | // MIs[1] Operand 1 |
| 55981 | // No operand predicates |
| 55982 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 55983 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETGT:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)), 1:{ *:[i64] }) |
| 55984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 55985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 55986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 55987 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 55988 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 55989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 55990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 55991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 55992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 55993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55994 | GIR_RootConstrainSelectedInstOperands, |
| 55995 | // GIR_Coverage, 65075, |
| 55996 | GIR_EraseRootFromParent_Done, |
| 55997 | // Label 3915: @144324 |
| 55998 | GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(144399), // Rule ID 65079 // |
| 55999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56003 | // MIs[0] Operand 1 |
| 56004 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 56005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56006 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56007 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56008 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 56009 | // MIs[1] Operand 1 |
| 56010 | // No operand predicates |
| 56011 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56012 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETUGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTIU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i64] }) |
| 56013 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56014 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56015 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56016 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56017 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 56018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56021 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56023 | GIR_RootConstrainSelectedInstOperands, |
| 56024 | // GIR_Coverage, 65079, |
| 56025 | GIR_EraseRootFromParent_Done, |
| 56026 | // Label 3916: @144399 |
| 56027 | GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(144474), // Rule ID 65083 // |
| 56028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56029 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56030 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56032 | // MIs[0] Operand 1 |
| 56033 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 56034 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56036 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56037 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 56038 | // MIs[1] Operand 1 |
| 56039 | // No operand predicates |
| 56040 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56041 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i64] }) |
| 56042 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56043 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 56044 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56045 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56046 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 56047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56050 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56052 | GIR_RootConstrainSelectedInstOperands, |
| 56053 | // GIR_Coverage, 65083, |
| 56054 | GIR_EraseRootFromParent_Done, |
| 56055 | // Label 3917: @144474 |
| 56056 | GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(144529), // Rule ID 65087 // |
| 56057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56061 | // MIs[0] Operand 1 |
| 56062 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 56063 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56064 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56065 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56066 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 56067 | // MIs[1] Operand 1 |
| 56068 | // No operand predicates |
| 56069 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56070 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETULE:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)) |
| 56071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56073 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56074 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 56075 | GIR_RootConstrainSelectedInstOperands, |
| 56076 | // GIR_Coverage, 65087, |
| 56077 | GIR_EraseRootFromParent_Done, |
| 56078 | // Label 3918: @144529 |
| 56079 | GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(144584), // Rule ID 65091 // |
| 56080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56081 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56082 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56084 | // MIs[0] Operand 1 |
| 56085 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 56086 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56087 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56088 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56089 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 56090 | // MIs[1] Operand 1 |
| 56091 | // No operand predicates |
| 56092 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56093 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETLE:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)) |
| 56094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 56095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56096 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56097 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 56098 | GIR_RootConstrainSelectedInstOperands, |
| 56099 | // GIR_Coverage, 65091, |
| 56100 | GIR_EraseRootFromParent_Done, |
| 56101 | // Label 3919: @144584 |
| 56102 | GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(144661), // Rule ID 65097 // |
| 56103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56107 | // MIs[0] Operand 1 |
| 56108 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56110 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56111 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56112 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 56113 | // MIs[1] Operand 1 |
| 56114 | // No operand predicates |
| 56115 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56116 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (ADDI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (NegImm:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12)), 1:{ *:[i64] }) |
| 56117 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56118 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 56119 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56120 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56121 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 56122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56125 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56127 | GIR_RootConstrainSelectedInstOperands, |
| 56128 | // GIR_Coverage, 65097, |
| 56129 | GIR_EraseRootFromParent_Done, |
| 56130 | // Label 3920: @144661 |
| 56131 | GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(144741), // Rule ID 65103 // |
| 56132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56134 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56135 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56136 | // MIs[0] Operand 1 |
| 56137 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 56138 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56140 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56141 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), |
| 56142 | // MIs[1] Operand 1 |
| 56143 | // No operand predicates |
| 56144 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56145 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (ADDI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (NegImm:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm12))) |
| 56146 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56147 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::ADDI), |
| 56148 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56149 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56150 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm12 |
| 56151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56154 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 56155 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56156 | GIR_RootConstrainSelectedInstOperands, |
| 56157 | // GIR_Coverage, 65103, |
| 56158 | GIR_EraseRootFromParent_Done, |
| 56159 | // Label 3921: @144741 |
| 56160 | GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(144818), // Rule ID 65107 // |
| 56161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56162 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56163 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56165 | // MIs[0] Operand 1 |
| 56166 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 56167 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56170 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 56171 | // MIs[1] Operand 1 |
| 56172 | // No operand predicates |
| 56173 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56174 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETUGT:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTIU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)), 1:{ *:[i64] }) |
| 56175 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56178 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56179 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 56180 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56183 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56185 | GIR_RootConstrainSelectedInstOperands, |
| 56186 | // GIR_Coverage, 65107, |
| 56187 | GIR_EraseRootFromParent_Done, |
| 56188 | // Label 3922: @144818 |
| 56189 | GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(144895), // Rule ID 65111 // |
| 56190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56191 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56192 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56193 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56194 | // MIs[0] Operand 1 |
| 56195 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 56196 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56197 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56198 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56199 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 56200 | // MIs[1] Operand 1 |
| 56201 | // No operand predicates |
| 56202 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56203 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETGT:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)), 1:{ *:[i64] }) |
| 56204 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56205 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 56206 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56207 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56208 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 56209 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56212 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56214 | GIR_RootConstrainSelectedInstOperands, |
| 56215 | // GIR_Coverage, 65111, |
| 56216 | GIR_EraseRootFromParent_Done, |
| 56217 | // Label 3923: @144895 |
| 56218 | GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(144970), // Rule ID 65115 // |
| 56219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56220 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56221 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56223 | // MIs[0] Operand 1 |
| 56224 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 56225 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56226 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56227 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56228 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 56229 | // MIs[1] Operand 1 |
| 56230 | // No operand predicates |
| 56231 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56232 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETUGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTIU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i64] }) |
| 56233 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56234 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56235 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56236 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56237 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 56238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56243 | GIR_RootConstrainSelectedInstOperands, |
| 56244 | // GIR_Coverage, 65115, |
| 56245 | GIR_EraseRootFromParent_Done, |
| 56246 | // Label 3924: @144970 |
| 56247 | GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(145045), // Rule ID 65119 // |
| 56248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56249 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56250 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56252 | // MIs[0] Operand 1 |
| 56253 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 56254 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56255 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56256 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56257 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), |
| 56258 | // MIs[1] Operand 1 |
| 56259 | // No operand predicates |
| 56260 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56261 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTI:{ *:[i32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm), 1:{ *:[i64] }) |
| 56262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 56264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56265 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56266 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 56267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56270 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56272 | GIR_RootConstrainSelectedInstOperands, |
| 56273 | // GIR_Coverage, 65119, |
| 56274 | GIR_EraseRootFromParent_Done, |
| 56275 | // Label 3925: @145045 |
| 56276 | GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(145100), // Rule ID 65123 // |
| 56277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56279 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56281 | // MIs[0] Operand 1 |
| 56282 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 56283 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56286 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1), |
| 56287 | // MIs[1] Operand 1 |
| 56288 | // No operand predicates |
| 56289 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56290 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm, SETULE:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1NonzeroNonNeg1>>:$imm)) |
| 56291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56293 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56294 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 56295 | GIR_RootConstrainSelectedInstOperands, |
| 56296 | // GIR_Coverage, 65123, |
| 56297 | GIR_EraseRootFromParent_Done, |
| 56298 | // Label 3926: @145100 |
| 56299 | GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(145155), // Rule ID 65127 // |
| 56300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56301 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56302 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56304 | // MIs[0] Operand 1 |
| 56305 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 56306 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56307 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 56308 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 56309 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Minus1Nonzero), |
| 56310 | // MIs[1] Operand 1 |
| 56311 | // No operand predicates |
| 56312 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 56313 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm, SETLE:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (ImmPlus1:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Minus1Nonzero>>:$imm)) |
| 56314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTI), |
| 56315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56316 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56317 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImmPlus1), // imm |
| 56318 | GIR_RootConstrainSelectedInstOperands, |
| 56319 | // GIR_Coverage, 65127, |
| 56320 | GIR_EraseRootFromParent_Done, |
| 56321 | // Label 3927: @145155 |
| 56322 | GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(145197), // Rule ID 64975 // |
| 56323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 56324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56325 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56327 | // MIs[0] Operand 1 |
| 56328 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 56329 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56330 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56331 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }) => (CV_SLET:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 56332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SLET), |
| 56333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56334 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56335 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56336 | GIR_RootConstrainSelectedInstOperands, |
| 56337 | // GIR_Coverage, 64975, |
| 56338 | GIR_EraseRootFromParent_Done, |
| 56339 | // Label 3928: @145197 |
| 56340 | GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(145239), // Rule ID 64977 // |
| 56341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 56342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56343 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56345 | // MIs[0] Operand 1 |
| 56346 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 56347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56348 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56349 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }) => (CV_SLETU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 56350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_SLETU), |
| 56351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56352 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56353 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56354 | GIR_RootConstrainSelectedInstOperands, |
| 56355 | // GIR_Coverage, 64977, |
| 56356 | GIR_EraseRootFromParent_Done, |
| 56357 | // Label 3929: @145239 |
| 56358 | GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(145281), // Rule ID 135 // |
| 56359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56361 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56363 | // MIs[0] Operand 1 |
| 56364 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 56365 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56366 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56367 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 56368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56371 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56372 | GIR_RootConstrainSelectedInstOperands, |
| 56373 | // GIR_Coverage, 135, |
| 56374 | GIR_EraseRootFromParent_Done, |
| 56375 | // Label 3930: @145281 |
| 56376 | GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(145323), // Rule ID 139 // |
| 56377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56378 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56379 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56381 | // MIs[0] Operand 1 |
| 56382 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 56383 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56384 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56385 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 56386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56388 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56389 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56390 | GIR_RootConstrainSelectedInstOperands, |
| 56391 | // GIR_Coverage, 139, |
| 56392 | GIR_EraseRootFromParent_Done, |
| 56393 | // Label 3931: @145323 |
| 56394 | GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(145365), // Rule ID 65053 // |
| 56395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56399 | // MIs[0] Operand 1 |
| 56400 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 56401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56402 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56403 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 56404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56407 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56408 | GIR_RootConstrainSelectedInstOperands, |
| 56409 | // GIR_Coverage, 65053, |
| 56410 | GIR_EraseRootFromParent_Done, |
| 56411 | // Label 3932: @145365 |
| 56412 | GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(145407), // Rule ID 65057 // |
| 56413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56414 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56415 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56417 | // MIs[0] Operand 1 |
| 56418 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 56419 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56420 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56421 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 56422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56424 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56425 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56426 | GIR_RootConstrainSelectedInstOperands, |
| 56427 | // GIR_Coverage, 65057, |
| 56428 | GIR_EraseRootFromParent_Done, |
| 56429 | // Label 3933: @145407 |
| 56430 | GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(145473), // Rule ID 65063 // |
| 56431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56433 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56435 | // MIs[0] Operand 1 |
| 56436 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56437 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56438 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56439 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (XOR:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) |
| 56440 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56441 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 56442 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56443 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56444 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56448 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56450 | GIR_RootConstrainSelectedInstOperands, |
| 56451 | // GIR_Coverage, 65063, |
| 56452 | GIR_EraseRootFromParent_Done, |
| 56453 | // Label 3934: @145473 |
| 56454 | GIM_Try, /*On fail goto*//*Label 3935*/ GIMT_Encode4(145542), // Rule ID 65069 // |
| 56455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56459 | // MIs[0] Operand 1 |
| 56460 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 56461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56462 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56463 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XOR:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) |
| 56464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 56466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56467 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56468 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56469 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56472 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 56473 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56474 | GIR_RootConstrainSelectedInstOperands, |
| 56475 | // GIR_Coverage, 65069, |
| 56476 | GIR_EraseRootFromParent_Done, |
| 56477 | // Label 3935: @145542 |
| 56478 | GIM_Try, /*On fail goto*//*Label 3936*/ GIMT_Encode4(145584), // Rule ID 65073 // |
| 56479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56481 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56483 | // MIs[0] Operand 1 |
| 56484 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 56485 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56486 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56487 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1) |
| 56488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56490 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56491 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56492 | GIR_RootConstrainSelectedInstOperands, |
| 56493 | // GIR_Coverage, 65073, |
| 56494 | GIR_EraseRootFromParent_Done, |
| 56495 | // Label 3936: @145584 |
| 56496 | GIM_Try, /*On fail goto*//*Label 3937*/ GIMT_Encode4(145626), // Rule ID 65077 // |
| 56497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56498 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56499 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56501 | // MIs[0] Operand 1 |
| 56502 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 56503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56504 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56505 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1) |
| 56506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56508 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56509 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56510 | GIR_RootConstrainSelectedInstOperands, |
| 56511 | // GIR_Coverage, 65077, |
| 56512 | GIR_EraseRootFromParent_Done, |
| 56513 | // Label 3937: @145626 |
| 56514 | GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(145692), // Rule ID 65081 // |
| 56515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56516 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56517 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56519 | // MIs[0] Operand 1 |
| 56520 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 56521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56522 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56523 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) |
| 56524 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56525 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56526 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56527 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56528 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56529 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56532 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56534 | GIR_RootConstrainSelectedInstOperands, |
| 56535 | // GIR_Coverage, 65081, |
| 56536 | GIR_EraseRootFromParent_Done, |
| 56537 | // Label 3938: @145692 |
| 56538 | GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(145758), // Rule ID 65085 // |
| 56539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56541 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56543 | // MIs[0] Operand 1 |
| 56544 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 56545 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56546 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56547 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) |
| 56548 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56549 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56550 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56551 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56552 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56556 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56558 | GIR_RootConstrainSelectedInstOperands, |
| 56559 | // GIR_Coverage, 65085, |
| 56560 | GIR_EraseRootFromParent_Done, |
| 56561 | // Label 3939: @145758 |
| 56562 | GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(145824), // Rule ID 65089 // |
| 56563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56564 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56565 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56567 | // MIs[0] Operand 1 |
| 56568 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 56569 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56570 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56571 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i32] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] }) |
| 56572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56573 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56574 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56575 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56576 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56580 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56582 | GIR_RootConstrainSelectedInstOperands, |
| 56583 | // GIR_Coverage, 65089, |
| 56584 | GIR_EraseRootFromParent_Done, |
| 56585 | // Label 3940: @145824 |
| 56586 | GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(145890), // Rule ID 65093 // |
| 56587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 56589 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 56590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56591 | // MIs[0] Operand 1 |
| 56592 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 56593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56594 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56595 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i32] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] }) |
| 56596 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56597 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56598 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56599 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56600 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56604 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56606 | GIR_RootConstrainSelectedInstOperands, |
| 56607 | // GIR_Coverage, 65093, |
| 56608 | GIR_EraseRootFromParent_Done, |
| 56609 | // Label 3941: @145890 |
| 56610 | GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(145956), // Rule ID 65099 // |
| 56611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56612 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56613 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56615 | // MIs[0] Operand 1 |
| 56616 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56618 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56619 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (XOR:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) |
| 56620 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56621 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 56622 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56623 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56624 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTIU), |
| 56627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56630 | GIR_RootConstrainSelectedInstOperands, |
| 56631 | // GIR_Coverage, 65099, |
| 56632 | GIR_EraseRootFromParent_Done, |
| 56633 | // Label 3942: @145956 |
| 56634 | GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(146025), // Rule ID 65105 // |
| 56635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56637 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56639 | // MIs[0] Operand 1 |
| 56640 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 56641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56642 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56643 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XOR:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) |
| 56644 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56645 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::XOR), |
| 56646 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56647 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56648 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56652 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 56653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56654 | GIR_RootConstrainSelectedInstOperands, |
| 56655 | // GIR_Coverage, 65105, |
| 56656 | GIR_EraseRootFromParent_Done, |
| 56657 | // Label 3943: @146025 |
| 56658 | GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(146067), // Rule ID 65109 // |
| 56659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56663 | // MIs[0] Operand 1 |
| 56664 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 56665 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56666 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56667 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1) |
| 56668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56670 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56671 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56672 | GIR_RootConstrainSelectedInstOperands, |
| 56673 | // GIR_Coverage, 65109, |
| 56674 | GIR_EraseRootFromParent_Done, |
| 56675 | // Label 3944: @146067 |
| 56676 | GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(146109), // Rule ID 65113 // |
| 56677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56678 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56679 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56681 | // MIs[0] Operand 1 |
| 56682 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 56683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56684 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56685 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1) |
| 56686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56688 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56689 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56690 | GIR_RootConstrainSelectedInstOperands, |
| 56691 | // GIR_Coverage, 65113, |
| 56692 | GIR_EraseRootFromParent_Done, |
| 56693 | // Label 3945: @146109 |
| 56694 | GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(146175), // Rule ID 65117 // |
| 56695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56697 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56699 | // MIs[0] Operand 1 |
| 56700 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 56701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56702 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56703 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) |
| 56704 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56705 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56706 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56707 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56708 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56714 | GIR_RootConstrainSelectedInstOperands, |
| 56715 | // GIR_Coverage, 65117, |
| 56716 | GIR_EraseRootFromParent_Done, |
| 56717 | // Label 3946: @146175 |
| 56718 | GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(146241), // Rule ID 65121 // |
| 56719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56720 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56721 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56723 | // MIs[0] Operand 1 |
| 56724 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 56725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56726 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56727 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i32] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) |
| 56728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56729 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56730 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56731 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56732 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56736 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56738 | GIR_RootConstrainSelectedInstOperands, |
| 56739 | // GIR_Coverage, 65121, |
| 56740 | GIR_EraseRootFromParent_Done, |
| 56741 | // Label 3947: @146241 |
| 56742 | GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(146307), // Rule ID 65125 // |
| 56743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56747 | // MIs[0] Operand 1 |
| 56748 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 56749 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56750 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56751 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i32] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] }) |
| 56752 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56753 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLTU), |
| 56754 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56755 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56756 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56760 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56762 | GIR_RootConstrainSelectedInstOperands, |
| 56763 | // GIR_Coverage, 65125, |
| 56764 | GIR_EraseRootFromParent_Done, |
| 56765 | // Label 3948: @146307 |
| 56766 | GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(146373), // Rule ID 65129 // |
| 56767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), |
| 56768 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56769 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 56770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56771 | // MIs[0] Operand 1 |
| 56772 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 56773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56774 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 56775 | // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i32] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] }) |
| 56776 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 56777 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLT), |
| 56778 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 56779 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 |
| 56780 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 |
| 56781 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 56782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::XORI), |
| 56783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56784 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 56785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56786 | GIR_RootConstrainSelectedInstOperands, |
| 56787 | // GIR_Coverage, 65129, |
| 56788 | GIR_EraseRootFromParent_Done, |
| 56789 | // Label 3949: @146373 |
| 56790 | GIM_Reject, |
| 56791 | // Label 3848: @146374 |
| 56792 | GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(146422), // Rule ID 46610 // |
| 56793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 56794 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 56795 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 56796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56797 | // MIs[0] Operand 1 |
| 56798 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56800 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56801 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 56802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF8), |
| 56803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56804 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56805 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 56808 | GIR_RootConstrainSelectedInstOperands, |
| 56809 | // GIR_Coverage, 46610, |
| 56810 | GIR_EraseRootFromParent_Done, |
| 56811 | // Label 3950: @146422 |
| 56812 | GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(146470), // Rule ID 46611 // |
| 56813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 56814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 56815 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 56816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56817 | // MIs[0] Operand 1 |
| 56818 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56819 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56820 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56821 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 56822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF8), |
| 56823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56824 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56825 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 56828 | GIR_RootConstrainSelectedInstOperands, |
| 56829 | // GIR_Coverage, 46611, |
| 56830 | GIR_EraseRootFromParent_Done, |
| 56831 | // Label 3951: @146470 |
| 56832 | GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(146518), // Rule ID 46612 // |
| 56833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 56834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 56835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 56836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56837 | // MIs[0] Operand 1 |
| 56838 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 56839 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56840 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56841 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 56842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF8), |
| 56843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56844 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 56845 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 56846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 56848 | GIR_RootConstrainSelectedInstOperands, |
| 56849 | // GIR_Coverage, 46612, |
| 56850 | GIR_EraseRootFromParent_Done, |
| 56851 | // Label 3952: @146518 |
| 56852 | GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(146566), // Rule ID 46613 // |
| 56853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 56854 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 56855 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 56856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56857 | // MIs[0] Operand 1 |
| 56858 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 56859 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56860 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56861 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 56862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF8), |
| 56863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56864 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 56865 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 56866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 56868 | GIR_RootConstrainSelectedInstOperands, |
| 56869 | // GIR_Coverage, 46613, |
| 56870 | GIR_EraseRootFromParent_Done, |
| 56871 | // Label 3953: @146566 |
| 56872 | GIM_Try, /*On fail goto*//*Label 3954*/ GIMT_Encode4(146614), // Rule ID 49120 // |
| 56873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 56874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 56875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 56876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56877 | // MIs[0] Operand 1 |
| 56878 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56880 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56881 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 56882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF4), |
| 56883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56885 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 56888 | GIR_RootConstrainSelectedInstOperands, |
| 56889 | // GIR_Coverage, 49120, |
| 56890 | GIR_EraseRootFromParent_Done, |
| 56891 | // Label 3954: @146614 |
| 56892 | GIM_Try, /*On fail goto*//*Label 3955*/ GIMT_Encode4(146662), // Rule ID 49121 // |
| 56893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 56894 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 56895 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 56896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56897 | // MIs[0] Operand 1 |
| 56898 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56899 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56900 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56901 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 56902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF4), |
| 56903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56904 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56905 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 56908 | GIR_RootConstrainSelectedInstOperands, |
| 56909 | // GIR_Coverage, 49121, |
| 56910 | GIR_EraseRootFromParent_Done, |
| 56911 | // Label 3955: @146662 |
| 56912 | GIM_Try, /*On fail goto*//*Label 3956*/ GIMT_Encode4(146710), // Rule ID 49124 // |
| 56913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 56914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 56915 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 56916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56917 | // MIs[0] Operand 1 |
| 56918 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56920 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56921 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 56922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF2), |
| 56923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56924 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56925 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 56928 | GIR_RootConstrainSelectedInstOperands, |
| 56929 | // GIR_Coverage, 49124, |
| 56930 | GIR_EraseRootFromParent_Done, |
| 56931 | // Label 3956: @146710 |
| 56932 | GIM_Try, /*On fail goto*//*Label 3957*/ GIMT_Encode4(146758), // Rule ID 49125 // |
| 56933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 56934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 56935 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 56936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56937 | // MIs[0] Operand 1 |
| 56938 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56940 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56941 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 56942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF2), |
| 56943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56944 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56945 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 56948 | GIR_RootConstrainSelectedInstOperands, |
| 56949 | // GIR_Coverage, 49125, |
| 56950 | GIR_EraseRootFromParent_Done, |
| 56951 | // Label 3957: @146758 |
| 56952 | GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(146806), // Rule ID 49132 // |
| 56953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 56954 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 56955 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 56956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56957 | // MIs[0] Operand 1 |
| 56958 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56960 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56961 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 56962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 56963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56964 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56965 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 56968 | GIR_RootConstrainSelectedInstOperands, |
| 56969 | // GIR_Coverage, 49132, |
| 56970 | GIR_EraseRootFromParent_Done, |
| 56971 | // Label 3958: @146806 |
| 56972 | GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(146854), // Rule ID 49133 // |
| 56973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 56974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 56975 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 56976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56977 | // MIs[0] Operand 1 |
| 56978 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 56979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56981 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 56982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 56983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 56984 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 56985 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 56986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 56987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 56988 | GIR_RootConstrainSelectedInstOperands, |
| 56989 | // GIR_Coverage, 49133, |
| 56990 | GIR_EraseRootFromParent_Done, |
| 56991 | // Label 3959: @146854 |
| 56992 | GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(146902), // Rule ID 49158 // |
| 56993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 56994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 56995 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 56996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 56997 | // MIs[0] Operand 1 |
| 56998 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 56999 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57000 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57001 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 57002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF8), |
| 57003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57004 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57005 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57008 | GIR_RootConstrainSelectedInstOperands, |
| 57009 | // GIR_Coverage, 49158, |
| 57010 | GIR_EraseRootFromParent_Done, |
| 57011 | // Label 3960: @146902 |
| 57012 | GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(146950), // Rule ID 49159 // |
| 57013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57015 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57017 | // MIs[0] Operand 1 |
| 57018 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57020 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57021 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 57022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF8), |
| 57023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57024 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57025 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57028 | GIR_RootConstrainSelectedInstOperands, |
| 57029 | // GIR_Coverage, 49159, |
| 57030 | GIR_EraseRootFromParent_Done, |
| 57031 | // Label 3961: @146950 |
| 57032 | GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(146998), // Rule ID 49164 // |
| 57033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57034 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57035 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57037 | // MIs[0] Operand 1 |
| 57038 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57040 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57041 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF4), |
| 57043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57044 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57045 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57048 | GIR_RootConstrainSelectedInstOperands, |
| 57049 | // GIR_Coverage, 49164, |
| 57050 | GIR_EraseRootFromParent_Done, |
| 57051 | // Label 3962: @146998 |
| 57052 | GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(147046), // Rule ID 49165 // |
| 57053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57055 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57057 | // MIs[0] Operand 1 |
| 57058 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57060 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57061 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF4), |
| 57063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57065 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57068 | GIR_RootConstrainSelectedInstOperands, |
| 57069 | // GIR_Coverage, 49165, |
| 57070 | GIR_EraseRootFromParent_Done, |
| 57071 | // Label 3963: @147046 |
| 57072 | GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(147094), // Rule ID 49168 // |
| 57073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57074 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57075 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57077 | // MIs[0] Operand 1 |
| 57078 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57079 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57080 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57081 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 57082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF2), |
| 57083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57084 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57085 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57088 | GIR_RootConstrainSelectedInstOperands, |
| 57089 | // GIR_Coverage, 49168, |
| 57090 | GIR_EraseRootFromParent_Done, |
| 57091 | // Label 3964: @147094 |
| 57092 | GIM_Try, /*On fail goto*//*Label 3965*/ GIMT_Encode4(147142), // Rule ID 49169 // |
| 57093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57094 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57095 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57097 | // MIs[0] Operand 1 |
| 57098 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57099 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57100 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57101 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 57102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF2), |
| 57103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57104 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57105 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57108 | GIR_RootConstrainSelectedInstOperands, |
| 57109 | // GIR_Coverage, 49169, |
| 57110 | GIR_EraseRootFromParent_Done, |
| 57111 | // Label 3965: @147142 |
| 57112 | GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(147190), // Rule ID 49176 // |
| 57113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 57114 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57115 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57117 | // MIs[0] Operand 1 |
| 57118 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57120 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57121 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 57122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 57123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57124 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57125 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57128 | GIR_RootConstrainSelectedInstOperands, |
| 57129 | // GIR_Coverage, 49176, |
| 57130 | GIR_EraseRootFromParent_Done, |
| 57131 | // Label 3966: @147190 |
| 57132 | GIM_Try, /*On fail goto*//*Label 3967*/ GIMT_Encode4(147238), // Rule ID 49177 // |
| 57133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 57134 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57135 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57137 | // MIs[0] Operand 1 |
| 57138 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 57139 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57140 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57141 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 57142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 57143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57144 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57145 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57148 | GIR_RootConstrainSelectedInstOperands, |
| 57149 | // GIR_Coverage, 49177, |
| 57150 | GIR_EraseRootFromParent_Done, |
| 57151 | // Label 3967: @147238 |
| 57152 | GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(147286), // Rule ID 49202 // |
| 57153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57155 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57157 | // MIs[0] Operand 1 |
| 57158 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57160 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57161 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 57162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF8), |
| 57163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57164 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57165 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57168 | GIR_RootConstrainSelectedInstOperands, |
| 57169 | // GIR_Coverage, 49202, |
| 57170 | GIR_EraseRootFromParent_Done, |
| 57171 | // Label 3968: @147286 |
| 57172 | GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(147334), // Rule ID 49203 // |
| 57173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57175 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57177 | // MIs[0] Operand 1 |
| 57178 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57180 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57181 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 57182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF8), |
| 57183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57184 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57185 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57188 | GIR_RootConstrainSelectedInstOperands, |
| 57189 | // GIR_Coverage, 49203, |
| 57190 | GIR_EraseRootFromParent_Done, |
| 57191 | // Label 3969: @147334 |
| 57192 | GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(147382), // Rule ID 49208 // |
| 57193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57195 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57197 | // MIs[0] Operand 1 |
| 57198 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57200 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57201 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 57203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57204 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57205 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57208 | GIR_RootConstrainSelectedInstOperands, |
| 57209 | // GIR_Coverage, 49208, |
| 57210 | GIR_EraseRootFromParent_Done, |
| 57211 | // Label 3970: @147382 |
| 57212 | GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(147430), // Rule ID 49209 // |
| 57213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57215 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57217 | // MIs[0] Operand 1 |
| 57218 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57220 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57221 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 57223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57224 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57225 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57228 | GIR_RootConstrainSelectedInstOperands, |
| 57229 | // GIR_Coverage, 49209, |
| 57230 | GIR_EraseRootFromParent_Done, |
| 57231 | // Label 3971: @147430 |
| 57232 | GIM_Try, /*On fail goto*//*Label 3972*/ GIMT_Encode4(147478), // Rule ID 49212 // |
| 57233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57235 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57237 | // MIs[0] Operand 1 |
| 57238 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57240 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57241 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 57242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 57243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57244 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57245 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57248 | GIR_RootConstrainSelectedInstOperands, |
| 57249 | // GIR_Coverage, 49212, |
| 57250 | GIR_EraseRootFromParent_Done, |
| 57251 | // Label 3972: @147478 |
| 57252 | GIM_Try, /*On fail goto*//*Label 3973*/ GIMT_Encode4(147526), // Rule ID 49213 // |
| 57253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57255 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57257 | // MIs[0] Operand 1 |
| 57258 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57259 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57260 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57261 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 57262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 57263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57264 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57265 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57268 | GIR_RootConstrainSelectedInstOperands, |
| 57269 | // GIR_Coverage, 49213, |
| 57270 | GIR_EraseRootFromParent_Done, |
| 57271 | // Label 3973: @147526 |
| 57272 | GIM_Try, /*On fail goto*//*Label 3974*/ GIMT_Encode4(147574), // Rule ID 49220 // |
| 57273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 57274 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57275 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57277 | // MIs[0] Operand 1 |
| 57278 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57279 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57280 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57281 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 57282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 57283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57284 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57285 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57288 | GIR_RootConstrainSelectedInstOperands, |
| 57289 | // GIR_Coverage, 49220, |
| 57290 | GIR_EraseRootFromParent_Done, |
| 57291 | // Label 3974: @147574 |
| 57292 | GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(147622), // Rule ID 49221 // |
| 57293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 57294 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57295 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57297 | // MIs[0] Operand 1 |
| 57298 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 57299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57300 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57301 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 57302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 57303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57304 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57305 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57308 | GIR_RootConstrainSelectedInstOperands, |
| 57309 | // GIR_Coverage, 49221, |
| 57310 | GIR_EraseRootFromParent_Done, |
| 57311 | // Label 3975: @147622 |
| 57312 | GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(147670), // Rule ID 49250 // |
| 57313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57314 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57315 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57317 | // MIs[0] Operand 1 |
| 57318 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 57319 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57320 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57321 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 57323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57324 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57325 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57328 | GIR_RootConstrainSelectedInstOperands, |
| 57329 | // GIR_Coverage, 49250, |
| 57330 | GIR_EraseRootFromParent_Done, |
| 57331 | // Label 3976: @147670 |
| 57332 | GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(147718), // Rule ID 49251 // |
| 57333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57334 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57335 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57337 | // MIs[0] Operand 1 |
| 57338 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 57339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57340 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57341 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 57343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57344 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57345 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57348 | GIR_RootConstrainSelectedInstOperands, |
| 57349 | // GIR_Coverage, 49251, |
| 57350 | GIR_EraseRootFromParent_Done, |
| 57351 | // Label 3977: @147718 |
| 57352 | GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(147766), // Rule ID 49254 // |
| 57353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57355 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57357 | // MIs[0] Operand 1 |
| 57358 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 57359 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57360 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57361 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 57362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 57363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57364 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57365 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57368 | GIR_RootConstrainSelectedInstOperands, |
| 57369 | // GIR_Coverage, 49254, |
| 57370 | GIR_EraseRootFromParent_Done, |
| 57371 | // Label 3978: @147766 |
| 57372 | GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(147814), // Rule ID 49255 // |
| 57373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57374 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57375 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57377 | // MIs[0] Operand 1 |
| 57378 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 57379 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57380 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57381 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 57382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 57383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57384 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57385 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57388 | GIR_RootConstrainSelectedInstOperands, |
| 57389 | // GIR_Coverage, 49255, |
| 57390 | GIR_EraseRootFromParent_Done, |
| 57391 | // Label 3979: @147814 |
| 57392 | GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(147862), // Rule ID 49262 // |
| 57393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 57394 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57395 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57397 | // MIs[0] Operand 1 |
| 57398 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 57399 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57400 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57401 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 57402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 57403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57404 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57405 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57408 | GIR_RootConstrainSelectedInstOperands, |
| 57409 | // GIR_Coverage, 49262, |
| 57410 | GIR_EraseRootFromParent_Done, |
| 57411 | // Label 3980: @147862 |
| 57412 | GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(147910), // Rule ID 49263 // |
| 57413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 57414 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57415 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57417 | // MIs[0] Operand 1 |
| 57418 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 57419 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57420 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57421 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 57422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 57423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57424 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57425 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57428 | GIR_RootConstrainSelectedInstOperands, |
| 57429 | // GIR_Coverage, 49263, |
| 57430 | GIR_EraseRootFromParent_Done, |
| 57431 | // Label 3981: @147910 |
| 57432 | GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(147958), // Rule ID 49288 // |
| 57433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57434 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57435 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57437 | // MIs[0] Operand 1 |
| 57438 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57439 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57440 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57441 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 57442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF8), |
| 57443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57444 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57445 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57448 | GIR_RootConstrainSelectedInstOperands, |
| 57449 | // GIR_Coverage, 49288, |
| 57450 | GIR_EraseRootFromParent_Done, |
| 57451 | // Label 3982: @147958 |
| 57452 | GIM_Try, /*On fail goto*//*Label 3983*/ GIMT_Encode4(148006), // Rule ID 49289 // |
| 57453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57454 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57455 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57457 | // MIs[0] Operand 1 |
| 57458 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57459 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57460 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57461 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 57462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF8), |
| 57463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57464 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57465 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57468 | GIR_RootConstrainSelectedInstOperands, |
| 57469 | // GIR_Coverage, 49289, |
| 57470 | GIR_EraseRootFromParent_Done, |
| 57471 | // Label 3983: @148006 |
| 57472 | GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(148054), // Rule ID 49294 // |
| 57473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57474 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57475 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57477 | // MIs[0] Operand 1 |
| 57478 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57479 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57480 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57481 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 57483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57484 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57485 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57488 | GIR_RootConstrainSelectedInstOperands, |
| 57489 | // GIR_Coverage, 49294, |
| 57490 | GIR_EraseRootFromParent_Done, |
| 57491 | // Label 3984: @148054 |
| 57492 | GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(148102), // Rule ID 49295 // |
| 57493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57495 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57497 | // MIs[0] Operand 1 |
| 57498 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57499 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57500 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57501 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 57503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57504 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57505 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57508 | GIR_RootConstrainSelectedInstOperands, |
| 57509 | // GIR_Coverage, 49295, |
| 57510 | GIR_EraseRootFromParent_Done, |
| 57511 | // Label 3985: @148102 |
| 57512 | GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(148150), // Rule ID 49298 // |
| 57513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57514 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57515 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57517 | // MIs[0] Operand 1 |
| 57518 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57519 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57520 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57521 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 57522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 57523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57524 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57525 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57528 | GIR_RootConstrainSelectedInstOperands, |
| 57529 | // GIR_Coverage, 49298, |
| 57530 | GIR_EraseRootFromParent_Done, |
| 57531 | // Label 3986: @148150 |
| 57532 | GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(148198), // Rule ID 49299 // |
| 57533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57534 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57535 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57537 | // MIs[0] Operand 1 |
| 57538 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57540 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57541 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 57542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 57543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57544 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57545 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57548 | GIR_RootConstrainSelectedInstOperands, |
| 57549 | // GIR_Coverage, 49299, |
| 57550 | GIR_EraseRootFromParent_Done, |
| 57551 | // Label 3987: @148198 |
| 57552 | GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(148246), // Rule ID 49306 // |
| 57553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 57554 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57555 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57557 | // MIs[0] Operand 1 |
| 57558 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57559 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57560 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57561 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 57562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 57563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57564 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57565 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57568 | GIR_RootConstrainSelectedInstOperands, |
| 57569 | // GIR_Coverage, 49306, |
| 57570 | GIR_EraseRootFromParent_Done, |
| 57571 | // Label 3988: @148246 |
| 57572 | GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(148294), // Rule ID 49307 // |
| 57573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 57574 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57575 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57577 | // MIs[0] Operand 1 |
| 57578 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 57579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57580 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57581 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 57582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 57583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57584 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57585 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57588 | GIR_RootConstrainSelectedInstOperands, |
| 57589 | // GIR_Coverage, 49307, |
| 57590 | GIR_EraseRootFromParent_Done, |
| 57591 | // Label 3989: @148294 |
| 57592 | GIM_Try, /*On fail goto*//*Label 3990*/ GIMT_Encode4(148342), // Rule ID 49332 // |
| 57593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57595 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57597 | // MIs[0] Operand 1 |
| 57598 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57599 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57600 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57601 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 57602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF8), |
| 57603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57604 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57605 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57608 | GIR_RootConstrainSelectedInstOperands, |
| 57609 | // GIR_Coverage, 49332, |
| 57610 | GIR_EraseRootFromParent_Done, |
| 57611 | // Label 3990: @148342 |
| 57612 | GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(148390), // Rule ID 49333 // |
| 57613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57614 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57615 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57617 | // MIs[0] Operand 1 |
| 57618 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57619 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57620 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57621 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 57622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF8), |
| 57623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57624 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57625 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57628 | GIR_RootConstrainSelectedInstOperands, |
| 57629 | // GIR_Coverage, 49333, |
| 57630 | GIR_EraseRootFromParent_Done, |
| 57631 | // Label 3991: @148390 |
| 57632 | GIM_Try, /*On fail goto*//*Label 3992*/ GIMT_Encode4(148438), // Rule ID 49338 // |
| 57633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57634 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57635 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57637 | // MIs[0] Operand 1 |
| 57638 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57639 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57640 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57641 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 57643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57644 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57645 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57648 | GIR_RootConstrainSelectedInstOperands, |
| 57649 | // GIR_Coverage, 49338, |
| 57650 | GIR_EraseRootFromParent_Done, |
| 57651 | // Label 3992: @148438 |
| 57652 | GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(148486), // Rule ID 49339 // |
| 57653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57654 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57655 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57657 | // MIs[0] Operand 1 |
| 57658 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57659 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57660 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57661 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 57663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57664 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57665 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57668 | GIR_RootConstrainSelectedInstOperands, |
| 57669 | // GIR_Coverage, 49339, |
| 57670 | GIR_EraseRootFromParent_Done, |
| 57671 | // Label 3993: @148486 |
| 57672 | GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(148534), // Rule ID 49342 // |
| 57673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57674 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57675 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57677 | // MIs[0] Operand 1 |
| 57678 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57680 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57681 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 57682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 57683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57684 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57685 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57688 | GIR_RootConstrainSelectedInstOperands, |
| 57689 | // GIR_Coverage, 49342, |
| 57690 | GIR_EraseRootFromParent_Done, |
| 57691 | // Label 3994: @148534 |
| 57692 | GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(148582), // Rule ID 49343 // |
| 57693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57694 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57695 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57697 | // MIs[0] Operand 1 |
| 57698 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57699 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57700 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57701 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 57702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 57703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57704 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57705 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57708 | GIR_RootConstrainSelectedInstOperands, |
| 57709 | // GIR_Coverage, 49343, |
| 57710 | GIR_EraseRootFromParent_Done, |
| 57711 | // Label 3995: @148582 |
| 57712 | GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(148630), // Rule ID 49350 // |
| 57713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 57714 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57715 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57717 | // MIs[0] Operand 1 |
| 57718 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57719 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57720 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57721 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 57722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 57723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57724 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57725 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57728 | GIR_RootConstrainSelectedInstOperands, |
| 57729 | // GIR_Coverage, 49350, |
| 57730 | GIR_EraseRootFromParent_Done, |
| 57731 | // Label 3996: @148630 |
| 57732 | GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(148678), // Rule ID 49351 // |
| 57733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 57734 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57735 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57737 | // MIs[0] Operand 1 |
| 57738 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 57739 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57740 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57741 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 57742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 57743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57744 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57745 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57748 | GIR_RootConstrainSelectedInstOperands, |
| 57749 | // GIR_Coverage, 49351, |
| 57750 | GIR_EraseRootFromParent_Done, |
| 57751 | // Label 3997: @148678 |
| 57752 | GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(148726), // Rule ID 49376 // |
| 57753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57755 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57757 | // MIs[0] Operand 1 |
| 57758 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57759 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57760 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57761 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 57762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF8), |
| 57763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57764 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57765 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57768 | GIR_RootConstrainSelectedInstOperands, |
| 57769 | // GIR_Coverage, 49376, |
| 57770 | GIR_EraseRootFromParent_Done, |
| 57771 | // Label 3998: @148726 |
| 57772 | GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(148774), // Rule ID 49377 // |
| 57773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57774 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57775 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57777 | // MIs[0] Operand 1 |
| 57778 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57780 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57781 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 57782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF8), |
| 57783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57784 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57785 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57788 | GIR_RootConstrainSelectedInstOperands, |
| 57789 | // GIR_Coverage, 49377, |
| 57790 | GIR_EraseRootFromParent_Done, |
| 57791 | // Label 3999: @148774 |
| 57792 | GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(148822), // Rule ID 49382 // |
| 57793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57794 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57795 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57797 | // MIs[0] Operand 1 |
| 57798 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57800 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57801 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 57803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57804 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57805 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57808 | GIR_RootConstrainSelectedInstOperands, |
| 57809 | // GIR_Coverage, 49382, |
| 57810 | GIR_EraseRootFromParent_Done, |
| 57811 | // Label 4000: @148822 |
| 57812 | GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(148870), // Rule ID 49383 // |
| 57813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57815 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57817 | // MIs[0] Operand 1 |
| 57818 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57819 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57820 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57821 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 57823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57824 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57825 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57828 | GIR_RootConstrainSelectedInstOperands, |
| 57829 | // GIR_Coverage, 49383, |
| 57830 | GIR_EraseRootFromParent_Done, |
| 57831 | // Label 4001: @148870 |
| 57832 | GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(148918), // Rule ID 49386 // |
| 57833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57837 | // MIs[0] Operand 1 |
| 57838 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57839 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57840 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57841 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 57842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 57843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57844 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57845 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57848 | GIR_RootConstrainSelectedInstOperands, |
| 57849 | // GIR_Coverage, 49386, |
| 57850 | GIR_EraseRootFromParent_Done, |
| 57851 | // Label 4002: @148918 |
| 57852 | GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(148966), // Rule ID 49387 // |
| 57853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57854 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57855 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57857 | // MIs[0] Operand 1 |
| 57858 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57859 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57860 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57861 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 57862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 57863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57864 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57865 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 57868 | GIR_RootConstrainSelectedInstOperands, |
| 57869 | // GIR_Coverage, 49387, |
| 57870 | GIR_EraseRootFromParent_Done, |
| 57871 | // Label 4003: @148966 |
| 57872 | GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(149014), // Rule ID 49394 // |
| 57873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 57874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57877 | // MIs[0] Operand 1 |
| 57878 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57880 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57881 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 57882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 57883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57885 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57888 | GIR_RootConstrainSelectedInstOperands, |
| 57889 | // GIR_Coverage, 49394, |
| 57890 | GIR_EraseRootFromParent_Done, |
| 57891 | // Label 4004: @149014 |
| 57892 | GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(149062), // Rule ID 49395 // |
| 57893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 57894 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 57895 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 57896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57897 | // MIs[0] Operand 1 |
| 57898 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 57899 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57900 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57901 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 57902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 57903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57904 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 57905 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 57906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 57908 | GIR_RootConstrainSelectedInstOperands, |
| 57909 | // GIR_Coverage, 49395, |
| 57910 | GIR_EraseRootFromParent_Done, |
| 57911 | // Label 4005: @149062 |
| 57912 | GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(149110), // Rule ID 49420 // |
| 57913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57915 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57917 | // MIs[0] Operand 1 |
| 57918 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 57919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57920 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57921 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 57922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF8), |
| 57923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57924 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57925 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57928 | GIR_RootConstrainSelectedInstOperands, |
| 57929 | // GIR_Coverage, 49420, |
| 57930 | GIR_EraseRootFromParent_Done, |
| 57931 | // Label 4006: @149110 |
| 57932 | GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(149158), // Rule ID 49421 // |
| 57933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 57935 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 57936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57937 | // MIs[0] Operand 1 |
| 57938 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 57939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57940 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57941 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 57942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF8), |
| 57943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57944 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57945 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 57948 | GIR_RootConstrainSelectedInstOperands, |
| 57949 | // GIR_Coverage, 49421, |
| 57950 | GIR_EraseRootFromParent_Done, |
| 57951 | // Label 4007: @149158 |
| 57952 | GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(149206), // Rule ID 49426 // |
| 57953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57954 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57955 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57957 | // MIs[0] Operand 1 |
| 57958 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 57959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57960 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57961 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 57962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 57963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57964 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57965 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57968 | GIR_RootConstrainSelectedInstOperands, |
| 57969 | // GIR_Coverage, 49426, |
| 57970 | GIR_EraseRootFromParent_Done, |
| 57971 | // Label 4008: @149206 |
| 57972 | GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(149254), // Rule ID 49427 // |
| 57973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 57974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 57975 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 57976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57977 | // MIs[0] Operand 1 |
| 57978 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 57979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57981 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 57982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 57983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 57984 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 57985 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 57986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 57987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 57988 | GIR_RootConstrainSelectedInstOperands, |
| 57989 | // GIR_Coverage, 49427, |
| 57990 | GIR_EraseRootFromParent_Done, |
| 57991 | // Label 4009: @149254 |
| 57992 | GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(149302), // Rule ID 49430 // |
| 57993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 57994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 57995 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 57996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 57997 | // MIs[0] Operand 1 |
| 57998 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 57999 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58000 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58001 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 58003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58004 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58005 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58008 | GIR_RootConstrainSelectedInstOperands, |
| 58009 | // GIR_Coverage, 49430, |
| 58010 | GIR_EraseRootFromParent_Done, |
| 58011 | // Label 4010: @149302 |
| 58012 | GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(149350), // Rule ID 49431 // |
| 58013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 58015 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 58016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58017 | // MIs[0] Operand 1 |
| 58018 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 58019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58020 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58021 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 58023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58024 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58025 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58028 | GIR_RootConstrainSelectedInstOperands, |
| 58029 | // GIR_Coverage, 49431, |
| 58030 | GIR_EraseRootFromParent_Done, |
| 58031 | // Label 4011: @149350 |
| 58032 | GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(149398), // Rule ID 49438 // |
| 58033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58034 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 58035 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 58036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58037 | // MIs[0] Operand 1 |
| 58038 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 58039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58040 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58041 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 58042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 58043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58044 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58045 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58048 | GIR_RootConstrainSelectedInstOperands, |
| 58049 | // GIR_Coverage, 49438, |
| 58050 | GIR_EraseRootFromParent_Done, |
| 58051 | // Label 4012: @149398 |
| 58052 | GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(149446), // Rule ID 49439 // |
| 58053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 58054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 58055 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 58056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58057 | // MIs[0] Operand 1 |
| 58058 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 58059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58060 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58061 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 58062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 58063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58064 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58065 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58068 | GIR_RootConstrainSelectedInstOperands, |
| 58069 | // GIR_Coverage, 49439, |
| 58070 | GIR_EraseRootFromParent_Done, |
| 58071 | // Label 4013: @149446 |
| 58072 | GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(149494), // Rule ID 49464 // |
| 58073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58074 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 58075 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 58076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58077 | // MIs[0] Operand 1 |
| 58078 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58079 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58080 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58081 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 58082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF8), |
| 58083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58084 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58085 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58088 | GIR_RootConstrainSelectedInstOperands, |
| 58089 | // GIR_Coverage, 49464, |
| 58090 | GIR_EraseRootFromParent_Done, |
| 58091 | // Label 4014: @149494 |
| 58092 | GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(149542), // Rule ID 49465 // |
| 58093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58094 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 58095 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 58096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58097 | // MIs[0] Operand 1 |
| 58098 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58099 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58100 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58101 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 58102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF8), |
| 58103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58104 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58105 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58108 | GIR_RootConstrainSelectedInstOperands, |
| 58109 | // GIR_Coverage, 49465, |
| 58110 | GIR_EraseRootFromParent_Done, |
| 58111 | // Label 4015: @149542 |
| 58112 | GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(149590), // Rule ID 49470 // |
| 58113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58114 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 58115 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 58116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58117 | // MIs[0] Operand 1 |
| 58118 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58120 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58121 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 58122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 58123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58124 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58125 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58128 | GIR_RootConstrainSelectedInstOperands, |
| 58129 | // GIR_Coverage, 49470, |
| 58130 | GIR_EraseRootFromParent_Done, |
| 58131 | // Label 4016: @149590 |
| 58132 | GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(149638), // Rule ID 49471 // |
| 58133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58134 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 58135 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 58136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58137 | // MIs[0] Operand 1 |
| 58138 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58139 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58140 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58141 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 58142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 58143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58144 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58145 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58148 | GIR_RootConstrainSelectedInstOperands, |
| 58149 | // GIR_Coverage, 49471, |
| 58150 | GIR_EraseRootFromParent_Done, |
| 58151 | // Label 4017: @149638 |
| 58152 | GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(149686), // Rule ID 49474 // |
| 58153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 58155 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 58156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58157 | // MIs[0] Operand 1 |
| 58158 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58160 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58161 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 58163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58164 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58165 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58168 | GIR_RootConstrainSelectedInstOperands, |
| 58169 | // GIR_Coverage, 49474, |
| 58170 | GIR_EraseRootFromParent_Done, |
| 58171 | // Label 4018: @149686 |
| 58172 | GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(149734), // Rule ID 49475 // |
| 58173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 58175 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 58176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58177 | // MIs[0] Operand 1 |
| 58178 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58180 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58181 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 58183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58184 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58185 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58188 | GIR_RootConstrainSelectedInstOperands, |
| 58189 | // GIR_Coverage, 49475, |
| 58190 | GIR_EraseRootFromParent_Done, |
| 58191 | // Label 4019: @149734 |
| 58192 | GIM_Try, /*On fail goto*//*Label 4020*/ GIMT_Encode4(149782), // Rule ID 49482 // |
| 58193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 58195 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 58196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58197 | // MIs[0] Operand 1 |
| 58198 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58200 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58201 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 58202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 58203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58204 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58205 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58208 | GIR_RootConstrainSelectedInstOperands, |
| 58209 | // GIR_Coverage, 49482, |
| 58210 | GIR_EraseRootFromParent_Done, |
| 58211 | // Label 4020: @149782 |
| 58212 | GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(149830), // Rule ID 49483 // |
| 58213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 58214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 58215 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 58216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58217 | // MIs[0] Operand 1 |
| 58218 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 58219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58220 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58221 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 58222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 58223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58224 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58225 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58228 | GIR_RootConstrainSelectedInstOperands, |
| 58229 | // GIR_Coverage, 49483, |
| 58230 | GIR_EraseRootFromParent_Done, |
| 58231 | // Label 4021: @149830 |
| 58232 | GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(149878), // Rule ID 49508 // |
| 58233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 58235 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 58236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58237 | // MIs[0] Operand 1 |
| 58238 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58240 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58241 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 58242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF8), |
| 58243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58244 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58245 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58248 | GIR_RootConstrainSelectedInstOperands, |
| 58249 | // GIR_Coverage, 49508, |
| 58250 | GIR_EraseRootFromParent_Done, |
| 58251 | // Label 4022: @149878 |
| 58252 | GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(149926), // Rule ID 49509 // |
| 58253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 58255 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 58256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58257 | // MIs[0] Operand 1 |
| 58258 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58259 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58260 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58261 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 58262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF8), |
| 58263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58264 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58265 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58268 | GIR_RootConstrainSelectedInstOperands, |
| 58269 | // GIR_Coverage, 49509, |
| 58270 | GIR_EraseRootFromParent_Done, |
| 58271 | // Label 4023: @149926 |
| 58272 | GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(149974), // Rule ID 49514 // |
| 58273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58274 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 58275 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 58276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58277 | // MIs[0] Operand 1 |
| 58278 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58279 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58280 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58281 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 58282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 58283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58284 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58285 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58288 | GIR_RootConstrainSelectedInstOperands, |
| 58289 | // GIR_Coverage, 49514, |
| 58290 | GIR_EraseRootFromParent_Done, |
| 58291 | // Label 4024: @149974 |
| 58292 | GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(150022), // Rule ID 49515 // |
| 58293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58294 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 58295 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 58296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58297 | // MIs[0] Operand 1 |
| 58298 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58300 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58301 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 58302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 58303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58304 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58305 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58308 | GIR_RootConstrainSelectedInstOperands, |
| 58309 | // GIR_Coverage, 49515, |
| 58310 | GIR_EraseRootFromParent_Done, |
| 58311 | // Label 4025: @150022 |
| 58312 | GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(150070), // Rule ID 49518 // |
| 58313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58314 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 58315 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 58316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58317 | // MIs[0] Operand 1 |
| 58318 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58319 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58320 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58321 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 58323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58324 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58325 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58328 | GIR_RootConstrainSelectedInstOperands, |
| 58329 | // GIR_Coverage, 49518, |
| 58330 | GIR_EraseRootFromParent_Done, |
| 58331 | // Label 4026: @150070 |
| 58332 | GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(150118), // Rule ID 49519 // |
| 58333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58334 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 58335 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 58336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58337 | // MIs[0] Operand 1 |
| 58338 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58340 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58341 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 58343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58344 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58345 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58348 | GIR_RootConstrainSelectedInstOperands, |
| 58349 | // GIR_Coverage, 49519, |
| 58350 | GIR_EraseRootFromParent_Done, |
| 58351 | // Label 4027: @150118 |
| 58352 | GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(150166), // Rule ID 49526 // |
| 58353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 58355 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 58356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58357 | // MIs[0] Operand 1 |
| 58358 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58359 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58360 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58361 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 58362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 58363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58364 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58365 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58368 | GIR_RootConstrainSelectedInstOperands, |
| 58369 | // GIR_Coverage, 49526, |
| 58370 | GIR_EraseRootFromParent_Done, |
| 58371 | // Label 4028: @150166 |
| 58372 | GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(150214), // Rule ID 49527 // |
| 58373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 58374 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 58375 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 58376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58377 | // MIs[0] Operand 1 |
| 58378 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 58379 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58380 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58381 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 58382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 58383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58384 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58385 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58388 | GIR_RootConstrainSelectedInstOperands, |
| 58389 | // GIR_Coverage, 49527, |
| 58390 | GIR_EraseRootFromParent_Done, |
| 58391 | // Label 4029: @150214 |
| 58392 | GIM_Reject, |
| 58393 | // Label 3849: @150215 |
| 58394 | GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(150263), // Rule ID 49116 // |
| 58395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58399 | // MIs[0] Operand 1 |
| 58400 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58402 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58403 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 58404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF4), |
| 58405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58407 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58410 | GIR_RootConstrainSelectedInstOperands, |
| 58411 | // GIR_Coverage, 49116, |
| 58412 | GIR_EraseRootFromParent_Done, |
| 58413 | // Label 4030: @150263 |
| 58414 | GIM_Try, /*On fail goto*//*Label 4031*/ GIMT_Encode4(150311), // Rule ID 49117 // |
| 58415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58419 | // MIs[0] Operand 1 |
| 58420 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58421 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58422 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58423 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 58424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF4), |
| 58425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58426 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58427 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58430 | GIR_RootConstrainSelectedInstOperands, |
| 58431 | // GIR_Coverage, 49117, |
| 58432 | GIR_EraseRootFromParent_Done, |
| 58433 | // Label 4031: @150311 |
| 58434 | GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(150359), // Rule ID 49122 // |
| 58435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58437 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58439 | // MIs[0] Operand 1 |
| 58440 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58442 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58443 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 58444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF2), |
| 58445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58447 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58450 | GIR_RootConstrainSelectedInstOperands, |
| 58451 | // GIR_Coverage, 49122, |
| 58452 | GIR_EraseRootFromParent_Done, |
| 58453 | // Label 4032: @150359 |
| 58454 | GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(150407), // Rule ID 49123 // |
| 58455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58459 | // MIs[0] Operand 1 |
| 58460 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58462 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58463 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 58464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF2), |
| 58465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58467 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58470 | GIR_RootConstrainSelectedInstOperands, |
| 58471 | // GIR_Coverage, 49123, |
| 58472 | GIR_EraseRootFromParent_Done, |
| 58473 | // Label 4033: @150407 |
| 58474 | GIM_Try, /*On fail goto*//*Label 4034*/ GIMT_Encode4(150455), // Rule ID 49130 // |
| 58475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58476 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58477 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58479 | // MIs[0] Operand 1 |
| 58480 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58481 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58482 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58483 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 58485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58486 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58487 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58490 | GIR_RootConstrainSelectedInstOperands, |
| 58491 | // GIR_Coverage, 49130, |
| 58492 | GIR_EraseRootFromParent_Done, |
| 58493 | // Label 4034: @150455 |
| 58494 | GIM_Try, /*On fail goto*//*Label 4035*/ GIMT_Encode4(150503), // Rule ID 49131 // |
| 58495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58497 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58499 | // MIs[0] Operand 1 |
| 58500 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58502 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58503 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 58505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58507 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58510 | GIR_RootConstrainSelectedInstOperands, |
| 58511 | // GIR_Coverage, 49131, |
| 58512 | GIR_EraseRootFromParent_Done, |
| 58513 | // Label 4035: @150503 |
| 58514 | GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(150551), // Rule ID 49152 // |
| 58515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58516 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58517 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58519 | // MIs[0] Operand 1 |
| 58520 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58522 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58523 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 58524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 58525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58526 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58527 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58530 | GIR_RootConstrainSelectedInstOperands, |
| 58531 | // GIR_Coverage, 49152, |
| 58532 | GIR_EraseRootFromParent_Done, |
| 58533 | // Label 4036: @150551 |
| 58534 | GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(150599), // Rule ID 49153 // |
| 58535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 58536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58537 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58539 | // MIs[0] Operand 1 |
| 58540 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 58541 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58542 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58543 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 58544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 58545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58546 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58547 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58550 | GIR_RootConstrainSelectedInstOperands, |
| 58551 | // GIR_Coverage, 49153, |
| 58552 | GIR_EraseRootFromParent_Done, |
| 58553 | // Label 4037: @150599 |
| 58554 | GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(150647), // Rule ID 49160 // |
| 58555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58556 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58557 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58559 | // MIs[0] Operand 1 |
| 58560 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58562 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58563 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 58564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF4), |
| 58565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58566 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58567 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58570 | GIR_RootConstrainSelectedInstOperands, |
| 58571 | // GIR_Coverage, 49160, |
| 58572 | GIR_EraseRootFromParent_Done, |
| 58573 | // Label 4038: @150647 |
| 58574 | GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(150695), // Rule ID 49161 // |
| 58575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58577 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58579 | // MIs[0] Operand 1 |
| 58580 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58582 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58583 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 58584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF4), |
| 58585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58586 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58587 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58590 | GIR_RootConstrainSelectedInstOperands, |
| 58591 | // GIR_Coverage, 49161, |
| 58592 | GIR_EraseRootFromParent_Done, |
| 58593 | // Label 4039: @150695 |
| 58594 | GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(150743), // Rule ID 49166 // |
| 58595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58596 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58597 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58599 | // MIs[0] Operand 1 |
| 58600 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58601 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58602 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58603 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 58604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF2), |
| 58605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58606 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58607 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58610 | GIR_RootConstrainSelectedInstOperands, |
| 58611 | // GIR_Coverage, 49166, |
| 58612 | GIR_EraseRootFromParent_Done, |
| 58613 | // Label 4040: @150743 |
| 58614 | GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(150791), // Rule ID 49167 // |
| 58615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58617 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58619 | // MIs[0] Operand 1 |
| 58620 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58621 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58622 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58623 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 58624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF2), |
| 58625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58626 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58627 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58630 | GIR_RootConstrainSelectedInstOperands, |
| 58631 | // GIR_Coverage, 49167, |
| 58632 | GIR_EraseRootFromParent_Done, |
| 58633 | // Label 4041: @150791 |
| 58634 | GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(150839), // Rule ID 49174 // |
| 58635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58637 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58639 | // MIs[0] Operand 1 |
| 58640 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58642 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58643 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 58645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58646 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58647 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58650 | GIR_RootConstrainSelectedInstOperands, |
| 58651 | // GIR_Coverage, 49174, |
| 58652 | GIR_EraseRootFromParent_Done, |
| 58653 | // Label 4042: @150839 |
| 58654 | GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(150887), // Rule ID 49175 // |
| 58655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58659 | // MIs[0] Operand 1 |
| 58660 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58662 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58663 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 58665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58667 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58670 | GIR_RootConstrainSelectedInstOperands, |
| 58671 | // GIR_Coverage, 49175, |
| 58672 | GIR_EraseRootFromParent_Done, |
| 58673 | // Label 4043: @150887 |
| 58674 | GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(150935), // Rule ID 49196 // |
| 58675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58676 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58679 | // MIs[0] Operand 1 |
| 58680 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58682 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58683 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 58684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 58685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58687 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58690 | GIR_RootConstrainSelectedInstOperands, |
| 58691 | // GIR_Coverage, 49196, |
| 58692 | GIR_EraseRootFromParent_Done, |
| 58693 | // Label 4044: @150935 |
| 58694 | GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(150983), // Rule ID 49197 // |
| 58695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 58696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58697 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58699 | // MIs[0] Operand 1 |
| 58700 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 58701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58702 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58703 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 58704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 58705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58706 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58707 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58710 | GIR_RootConstrainSelectedInstOperands, |
| 58711 | // GIR_Coverage, 49197, |
| 58712 | GIR_EraseRootFromParent_Done, |
| 58713 | // Label 4045: @150983 |
| 58714 | GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(151031), // Rule ID 49204 // |
| 58715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58716 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58719 | // MIs[0] Operand 1 |
| 58720 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58721 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58722 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58723 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 58724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 58725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58726 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58727 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58730 | GIR_RootConstrainSelectedInstOperands, |
| 58731 | // GIR_Coverage, 49204, |
| 58732 | GIR_EraseRootFromParent_Done, |
| 58733 | // Label 4046: @151031 |
| 58734 | GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(151079), // Rule ID 49205 // |
| 58735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58739 | // MIs[0] Operand 1 |
| 58740 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58741 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58742 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58743 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 58744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 58745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58746 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58747 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58750 | GIR_RootConstrainSelectedInstOperands, |
| 58751 | // GIR_Coverage, 49205, |
| 58752 | GIR_EraseRootFromParent_Done, |
| 58753 | // Label 4047: @151079 |
| 58754 | GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(151127), // Rule ID 49210 // |
| 58755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58756 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58757 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58759 | // MIs[0] Operand 1 |
| 58760 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58762 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58763 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 58764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 58765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58766 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58767 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58770 | GIR_RootConstrainSelectedInstOperands, |
| 58771 | // GIR_Coverage, 49210, |
| 58772 | GIR_EraseRootFromParent_Done, |
| 58773 | // Label 4048: @151127 |
| 58774 | GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(151175), // Rule ID 49211 // |
| 58775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58779 | // MIs[0] Operand 1 |
| 58780 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58781 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58782 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58783 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 58784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 58785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58786 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58787 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58790 | GIR_RootConstrainSelectedInstOperands, |
| 58791 | // GIR_Coverage, 49211, |
| 58792 | GIR_EraseRootFromParent_Done, |
| 58793 | // Label 4049: @151175 |
| 58794 | GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(151223), // Rule ID 49218 // |
| 58795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58796 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58797 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58799 | // MIs[0] Operand 1 |
| 58800 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58801 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58802 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58803 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 58805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58806 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58807 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58810 | GIR_RootConstrainSelectedInstOperands, |
| 58811 | // GIR_Coverage, 49218, |
| 58812 | GIR_EraseRootFromParent_Done, |
| 58813 | // Label 4050: @151223 |
| 58814 | GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(151271), // Rule ID 49219 // |
| 58815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58817 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58819 | // MIs[0] Operand 1 |
| 58820 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58821 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58822 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58823 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 58825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58826 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58827 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58830 | GIR_RootConstrainSelectedInstOperands, |
| 58831 | // GIR_Coverage, 49219, |
| 58832 | GIR_EraseRootFromParent_Done, |
| 58833 | // Label 4051: @151271 |
| 58834 | GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(151319), // Rule ID 49240 // |
| 58835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58837 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58839 | // MIs[0] Operand 1 |
| 58840 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58841 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58842 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58843 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 58844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 58845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58846 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58847 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58850 | GIR_RootConstrainSelectedInstOperands, |
| 58851 | // GIR_Coverage, 49240, |
| 58852 | GIR_EraseRootFromParent_Done, |
| 58853 | // Label 4052: @151319 |
| 58854 | GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(151367), // Rule ID 49241 // |
| 58855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 58856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58859 | // MIs[0] Operand 1 |
| 58860 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 58861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58862 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 58863 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 58864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 58865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58866 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 58867 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 58868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 58870 | GIR_RootConstrainSelectedInstOperands, |
| 58871 | // GIR_Coverage, 49241, |
| 58872 | GIR_EraseRootFromParent_Done, |
| 58873 | // Label 4053: @151367 |
| 58874 | GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(151415), // Rule ID 49246 // |
| 58875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58876 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58877 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58879 | // MIs[0] Operand 1 |
| 58880 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 58881 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58882 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58883 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 58884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 58885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58886 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58887 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58890 | GIR_RootConstrainSelectedInstOperands, |
| 58891 | // GIR_Coverage, 49246, |
| 58892 | GIR_EraseRootFromParent_Done, |
| 58893 | // Label 4054: @151415 |
| 58894 | GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(151463), // Rule ID 49247 // |
| 58895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 58897 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 58898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58899 | // MIs[0] Operand 1 |
| 58900 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 58901 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58902 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58903 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 58904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF4), |
| 58905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58906 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58907 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 58910 | GIR_RootConstrainSelectedInstOperands, |
| 58911 | // GIR_Coverage, 49247, |
| 58912 | GIR_EraseRootFromParent_Done, |
| 58913 | // Label 4055: @151463 |
| 58914 | GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(151511), // Rule ID 49252 // |
| 58915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58916 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58917 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58919 | // MIs[0] Operand 1 |
| 58920 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 58921 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58922 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58923 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 58924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 58925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58926 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58927 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58930 | GIR_RootConstrainSelectedInstOperands, |
| 58931 | // GIR_Coverage, 49252, |
| 58932 | GIR_EraseRootFromParent_Done, |
| 58933 | // Label 4056: @151511 |
| 58934 | GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(151559), // Rule ID 49253 // |
| 58935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58936 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 58937 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 58938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58939 | // MIs[0] Operand 1 |
| 58940 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 58941 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58942 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58943 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 58944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 58945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58946 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58947 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 58950 | GIR_RootConstrainSelectedInstOperands, |
| 58951 | // GIR_Coverage, 49253, |
| 58952 | GIR_EraseRootFromParent_Done, |
| 58953 | // Label 4057: @151559 |
| 58954 | GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(151607), // Rule ID 49260 // |
| 58955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 58956 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58957 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58959 | // MIs[0] Operand 1 |
| 58960 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 58961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58962 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58963 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 58964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 58965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58966 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58967 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58970 | GIR_RootConstrainSelectedInstOperands, |
| 58971 | // GIR_Coverage, 49260, |
| 58972 | GIR_EraseRootFromParent_Done, |
| 58973 | // Label 4058: @151607 |
| 58974 | GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(151655), // Rule ID 49261 // |
| 58975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 58976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 58977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 58978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58979 | // MIs[0] Operand 1 |
| 58980 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 58981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58982 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58983 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 58984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 58985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 58986 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 58987 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 58988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 58989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 58990 | GIR_RootConstrainSelectedInstOperands, |
| 58991 | // GIR_Coverage, 49261, |
| 58992 | GIR_EraseRootFromParent_Done, |
| 58993 | // Label 4059: @151655 |
| 58994 | GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(151703), // Rule ID 49282 // |
| 58995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 58996 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 58997 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 58998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 58999 | // MIs[0] Operand 1 |
| 59000 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 59001 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59002 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59003 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 59005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59006 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59007 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59010 | GIR_RootConstrainSelectedInstOperands, |
| 59011 | // GIR_Coverage, 49282, |
| 59012 | GIR_EraseRootFromParent_Done, |
| 59013 | // Label 4060: @151703 |
| 59014 | GIM_Try, /*On fail goto*//*Label 4061*/ GIMT_Encode4(151751), // Rule ID 49283 // |
| 59015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59017 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59019 | // MIs[0] Operand 1 |
| 59020 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 59021 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59022 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59023 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 59025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59026 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59027 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59030 | GIR_RootConstrainSelectedInstOperands, |
| 59031 | // GIR_Coverage, 49283, |
| 59032 | GIR_EraseRootFromParent_Done, |
| 59033 | // Label 4061: @151751 |
| 59034 | GIM_Try, /*On fail goto*//*Label 4062*/ GIMT_Encode4(151799), // Rule ID 49290 // |
| 59035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59036 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59037 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59039 | // MIs[0] Operand 1 |
| 59040 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59041 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59042 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59043 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 59044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 59045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59046 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59047 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59050 | GIR_RootConstrainSelectedInstOperands, |
| 59051 | // GIR_Coverage, 49290, |
| 59052 | GIR_EraseRootFromParent_Done, |
| 59053 | // Label 4062: @151799 |
| 59054 | GIM_Try, /*On fail goto*//*Label 4063*/ GIMT_Encode4(151847), // Rule ID 49291 // |
| 59055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59056 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59057 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59059 | // MIs[0] Operand 1 |
| 59060 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59061 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59062 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59063 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 59064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 59065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59066 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59067 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59070 | GIR_RootConstrainSelectedInstOperands, |
| 59071 | // GIR_Coverage, 49291, |
| 59072 | GIR_EraseRootFromParent_Done, |
| 59073 | // Label 4063: @151847 |
| 59074 | GIM_Try, /*On fail goto*//*Label 4064*/ GIMT_Encode4(151895), // Rule ID 49296 // |
| 59075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59076 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59077 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59079 | // MIs[0] Operand 1 |
| 59080 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59081 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59082 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59083 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 59084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 59085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59086 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59087 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59090 | GIR_RootConstrainSelectedInstOperands, |
| 59091 | // GIR_Coverage, 49296, |
| 59092 | GIR_EraseRootFromParent_Done, |
| 59093 | // Label 4064: @151895 |
| 59094 | GIM_Try, /*On fail goto*//*Label 4065*/ GIMT_Encode4(151943), // Rule ID 49297 // |
| 59095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59097 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59099 | // MIs[0] Operand 1 |
| 59100 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59101 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59102 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59103 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 59104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 59105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59106 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59107 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59110 | GIR_RootConstrainSelectedInstOperands, |
| 59111 | // GIR_Coverage, 49297, |
| 59112 | GIR_EraseRootFromParent_Done, |
| 59113 | // Label 4065: @151943 |
| 59114 | GIM_Try, /*On fail goto*//*Label 4066*/ GIMT_Encode4(151991), // Rule ID 49304 // |
| 59115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59116 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59117 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59119 | // MIs[0] Operand 1 |
| 59120 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59121 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59122 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59123 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 59124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 59125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59126 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59127 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59130 | GIR_RootConstrainSelectedInstOperands, |
| 59131 | // GIR_Coverage, 49304, |
| 59132 | GIR_EraseRootFromParent_Done, |
| 59133 | // Label 4066: @151991 |
| 59134 | GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(152039), // Rule ID 49305 // |
| 59135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59137 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59139 | // MIs[0] Operand 1 |
| 59140 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59141 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59142 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59143 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 59144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 59145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59146 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59147 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59150 | GIR_RootConstrainSelectedInstOperands, |
| 59151 | // GIR_Coverage, 49305, |
| 59152 | GIR_EraseRootFromParent_Done, |
| 59153 | // Label 4067: @152039 |
| 59154 | GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(152087), // Rule ID 49326 // |
| 59155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 59156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59157 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59159 | // MIs[0] Operand 1 |
| 59160 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59162 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59163 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 59165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59166 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59167 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59170 | GIR_RootConstrainSelectedInstOperands, |
| 59171 | // GIR_Coverage, 49326, |
| 59172 | GIR_EraseRootFromParent_Done, |
| 59173 | // Label 4068: @152087 |
| 59174 | GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(152135), // Rule ID 49327 // |
| 59175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59177 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59179 | // MIs[0] Operand 1 |
| 59180 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 59181 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59182 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59183 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 59185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59186 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59187 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59190 | GIR_RootConstrainSelectedInstOperands, |
| 59191 | // GIR_Coverage, 49327, |
| 59192 | GIR_EraseRootFromParent_Done, |
| 59193 | // Label 4069: @152135 |
| 59194 | GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(152183), // Rule ID 49334 // |
| 59195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59196 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59197 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59199 | // MIs[0] Operand 1 |
| 59200 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59202 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59203 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 59204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 59205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59206 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59207 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59210 | GIR_RootConstrainSelectedInstOperands, |
| 59211 | // GIR_Coverage, 49334, |
| 59212 | GIR_EraseRootFromParent_Done, |
| 59213 | // Label 4070: @152183 |
| 59214 | GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(152231), // Rule ID 49335 // |
| 59215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59217 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59219 | // MIs[0] Operand 1 |
| 59220 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59221 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59222 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59223 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 59224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF4), |
| 59225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59226 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59227 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59230 | GIR_RootConstrainSelectedInstOperands, |
| 59231 | // GIR_Coverage, 49335, |
| 59232 | GIR_EraseRootFromParent_Done, |
| 59233 | // Label 4071: @152231 |
| 59234 | GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(152279), // Rule ID 49340 // |
| 59235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59236 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59237 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59239 | // MIs[0] Operand 1 |
| 59240 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59241 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59242 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59243 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 59244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 59245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59246 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59247 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59250 | GIR_RootConstrainSelectedInstOperands, |
| 59251 | // GIR_Coverage, 49340, |
| 59252 | GIR_EraseRootFromParent_Done, |
| 59253 | // Label 4072: @152279 |
| 59254 | GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(152327), // Rule ID 49341 // |
| 59255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59256 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59257 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59259 | // MIs[0] Operand 1 |
| 59260 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59261 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59262 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59263 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 59264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 59265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59266 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59267 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59270 | GIR_RootConstrainSelectedInstOperands, |
| 59271 | // GIR_Coverage, 49341, |
| 59272 | GIR_EraseRootFromParent_Done, |
| 59273 | // Label 4073: @152327 |
| 59274 | GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(152375), // Rule ID 49348 // |
| 59275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59276 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59277 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59279 | // MIs[0] Operand 1 |
| 59280 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59282 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59283 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 59284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 59285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59286 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59287 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59290 | GIR_RootConstrainSelectedInstOperands, |
| 59291 | // GIR_Coverage, 49348, |
| 59292 | GIR_EraseRootFromParent_Done, |
| 59293 | // Label 4074: @152375 |
| 59294 | GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(152423), // Rule ID 49349 // |
| 59295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59296 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59297 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59299 | // MIs[0] Operand 1 |
| 59300 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59301 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59302 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59303 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 59304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 59305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59306 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59307 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59310 | GIR_RootConstrainSelectedInstOperands, |
| 59311 | // GIR_Coverage, 49349, |
| 59312 | GIR_EraseRootFromParent_Done, |
| 59313 | // Label 4075: @152423 |
| 59314 | GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(152471), // Rule ID 49370 // |
| 59315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 59316 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59317 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59319 | // MIs[0] Operand 1 |
| 59320 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59321 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59322 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59323 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 59325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59326 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59327 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59330 | GIR_RootConstrainSelectedInstOperands, |
| 59331 | // GIR_Coverage, 49370, |
| 59332 | GIR_EraseRootFromParent_Done, |
| 59333 | // Label 4076: @152471 |
| 59334 | GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(152519), // Rule ID 49371 // |
| 59335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59336 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59337 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59339 | // MIs[0] Operand 1 |
| 59340 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 59341 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59342 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59343 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 59345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59346 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59347 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59350 | GIR_RootConstrainSelectedInstOperands, |
| 59351 | // GIR_Coverage, 49371, |
| 59352 | GIR_EraseRootFromParent_Done, |
| 59353 | // Label 4077: @152519 |
| 59354 | GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(152567), // Rule ID 49378 // |
| 59355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59356 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59357 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59359 | // MIs[0] Operand 1 |
| 59360 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59362 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59363 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 59364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 59365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59366 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59367 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59370 | GIR_RootConstrainSelectedInstOperands, |
| 59371 | // GIR_Coverage, 49378, |
| 59372 | GIR_EraseRootFromParent_Done, |
| 59373 | // Label 4078: @152567 |
| 59374 | GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(152615), // Rule ID 49379 // |
| 59375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59376 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59377 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59379 | // MIs[0] Operand 1 |
| 59380 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59381 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59382 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59383 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 59384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 59385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59386 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59387 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59390 | GIR_RootConstrainSelectedInstOperands, |
| 59391 | // GIR_Coverage, 49379, |
| 59392 | GIR_EraseRootFromParent_Done, |
| 59393 | // Label 4079: @152615 |
| 59394 | GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(152663), // Rule ID 49384 // |
| 59395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59399 | // MIs[0] Operand 1 |
| 59400 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59402 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59403 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 59404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 59405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59407 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59410 | GIR_RootConstrainSelectedInstOperands, |
| 59411 | // GIR_Coverage, 49384, |
| 59412 | GIR_EraseRootFromParent_Done, |
| 59413 | // Label 4080: @152663 |
| 59414 | GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(152711), // Rule ID 49385 // |
| 59415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59419 | // MIs[0] Operand 1 |
| 59420 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59421 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59422 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59423 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 59424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 59425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59426 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59427 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59430 | GIR_RootConstrainSelectedInstOperands, |
| 59431 | // GIR_Coverage, 49385, |
| 59432 | GIR_EraseRootFromParent_Done, |
| 59433 | // Label 4081: @152711 |
| 59434 | GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(152759), // Rule ID 49392 // |
| 59435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59437 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59439 | // MIs[0] Operand 1 |
| 59440 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59442 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59443 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 59444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 59445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59447 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59450 | GIR_RootConstrainSelectedInstOperands, |
| 59451 | // GIR_Coverage, 49392, |
| 59452 | GIR_EraseRootFromParent_Done, |
| 59453 | // Label 4082: @152759 |
| 59454 | GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(152807), // Rule ID 49393 // |
| 59455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59459 | // MIs[0] Operand 1 |
| 59460 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59462 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59463 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 59464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 59465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59467 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59470 | GIR_RootConstrainSelectedInstOperands, |
| 59471 | // GIR_Coverage, 49393, |
| 59472 | GIR_EraseRootFromParent_Done, |
| 59473 | // Label 4083: @152807 |
| 59474 | GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(152855), // Rule ID 49414 // |
| 59475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 59476 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59477 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59479 | // MIs[0] Operand 1 |
| 59480 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59481 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59482 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59483 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 59485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59486 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59487 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59490 | GIR_RootConstrainSelectedInstOperands, |
| 59491 | // GIR_Coverage, 49414, |
| 59492 | GIR_EraseRootFromParent_Done, |
| 59493 | // Label 4084: @152855 |
| 59494 | GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(152903), // Rule ID 49415 // |
| 59495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59497 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59499 | // MIs[0] Operand 1 |
| 59500 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 59501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59502 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59503 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 59505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59507 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59510 | GIR_RootConstrainSelectedInstOperands, |
| 59511 | // GIR_Coverage, 49415, |
| 59512 | GIR_EraseRootFromParent_Done, |
| 59513 | // Label 4085: @152903 |
| 59514 | GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(152951), // Rule ID 49422 // |
| 59515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59516 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59517 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59519 | // MIs[0] Operand 1 |
| 59520 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59522 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59523 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 59524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 59525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59526 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59527 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59530 | GIR_RootConstrainSelectedInstOperands, |
| 59531 | // GIR_Coverage, 49422, |
| 59532 | GIR_EraseRootFromParent_Done, |
| 59533 | // Label 4086: @152951 |
| 59534 | GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(152999), // Rule ID 49423 // |
| 59535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59537 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59539 | // MIs[0] Operand 1 |
| 59540 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59541 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59542 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59543 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 59544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF4), |
| 59545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59546 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59547 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59550 | GIR_RootConstrainSelectedInstOperands, |
| 59551 | // GIR_Coverage, 49423, |
| 59552 | GIR_EraseRootFromParent_Done, |
| 59553 | // Label 4087: @152999 |
| 59554 | GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(153047), // Rule ID 49428 // |
| 59555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59556 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59557 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59559 | // MIs[0] Operand 1 |
| 59560 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59562 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59563 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 59564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 59565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59566 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59567 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59570 | GIR_RootConstrainSelectedInstOperands, |
| 59571 | // GIR_Coverage, 49428, |
| 59572 | GIR_EraseRootFromParent_Done, |
| 59573 | // Label 4088: @153047 |
| 59574 | GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(153095), // Rule ID 49429 // |
| 59575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59577 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59579 | // MIs[0] Operand 1 |
| 59580 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59582 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59583 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 59584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 59585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59586 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59587 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59590 | GIR_RootConstrainSelectedInstOperands, |
| 59591 | // GIR_Coverage, 49429, |
| 59592 | GIR_EraseRootFromParent_Done, |
| 59593 | // Label 4089: @153095 |
| 59594 | GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(153143), // Rule ID 49436 // |
| 59595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59596 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59597 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59599 | // MIs[0] Operand 1 |
| 59600 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59601 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59602 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59603 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 59604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 59605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59606 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59607 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59610 | GIR_RootConstrainSelectedInstOperands, |
| 59611 | // GIR_Coverage, 49436, |
| 59612 | GIR_EraseRootFromParent_Done, |
| 59613 | // Label 4090: @153143 |
| 59614 | GIM_Try, /*On fail goto*//*Label 4091*/ GIMT_Encode4(153191), // Rule ID 49437 // |
| 59615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59617 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59619 | // MIs[0] Operand 1 |
| 59620 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59621 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59622 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59623 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 59624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 59625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59626 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59627 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59630 | GIR_RootConstrainSelectedInstOperands, |
| 59631 | // GIR_Coverage, 49437, |
| 59632 | GIR_EraseRootFromParent_Done, |
| 59633 | // Label 4091: @153191 |
| 59634 | GIM_Try, /*On fail goto*//*Label 4092*/ GIMT_Encode4(153239), // Rule ID 49458 // |
| 59635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 59636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59637 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59639 | // MIs[0] Operand 1 |
| 59640 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59642 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59643 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 59645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59646 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59647 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59650 | GIR_RootConstrainSelectedInstOperands, |
| 59651 | // GIR_Coverage, 49458, |
| 59652 | GIR_EraseRootFromParent_Done, |
| 59653 | // Label 4092: @153239 |
| 59654 | GIM_Try, /*On fail goto*//*Label 4093*/ GIMT_Encode4(153287), // Rule ID 49459 // |
| 59655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59659 | // MIs[0] Operand 1 |
| 59660 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 59661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59662 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59663 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 59665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59666 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59667 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59670 | GIR_RootConstrainSelectedInstOperands, |
| 59671 | // GIR_Coverage, 49459, |
| 59672 | GIR_EraseRootFromParent_Done, |
| 59673 | // Label 4093: @153287 |
| 59674 | GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(153335), // Rule ID 49466 // |
| 59675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59676 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59679 | // MIs[0] Operand 1 |
| 59680 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59682 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59683 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 59684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 59685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59687 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59690 | GIR_RootConstrainSelectedInstOperands, |
| 59691 | // GIR_Coverage, 49466, |
| 59692 | GIR_EraseRootFromParent_Done, |
| 59693 | // Label 4094: @153335 |
| 59694 | GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(153383), // Rule ID 49467 // |
| 59695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59697 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59699 | // MIs[0] Operand 1 |
| 59700 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59702 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59703 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 59704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 59705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59706 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59707 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59710 | GIR_RootConstrainSelectedInstOperands, |
| 59711 | // GIR_Coverage, 49467, |
| 59712 | GIR_EraseRootFromParent_Done, |
| 59713 | // Label 4095: @153383 |
| 59714 | GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(153431), // Rule ID 49472 // |
| 59715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59716 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59719 | // MIs[0] Operand 1 |
| 59720 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59721 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59722 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59723 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 59724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 59725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59726 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59727 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59730 | GIR_RootConstrainSelectedInstOperands, |
| 59731 | // GIR_Coverage, 49472, |
| 59732 | GIR_EraseRootFromParent_Done, |
| 59733 | // Label 4096: @153431 |
| 59734 | GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(153479), // Rule ID 49473 // |
| 59735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59739 | // MIs[0] Operand 1 |
| 59740 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59741 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59742 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59743 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 59744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 59745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59746 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59747 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59750 | GIR_RootConstrainSelectedInstOperands, |
| 59751 | // GIR_Coverage, 49473, |
| 59752 | GIR_EraseRootFromParent_Done, |
| 59753 | // Label 4097: @153479 |
| 59754 | GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(153527), // Rule ID 49480 // |
| 59755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59756 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59757 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59759 | // MIs[0] Operand 1 |
| 59760 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59762 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59763 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 59764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 59765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59766 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59767 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59770 | GIR_RootConstrainSelectedInstOperands, |
| 59771 | // GIR_Coverage, 49480, |
| 59772 | GIR_EraseRootFromParent_Done, |
| 59773 | // Label 4098: @153527 |
| 59774 | GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(153575), // Rule ID 49481 // |
| 59775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59779 | // MIs[0] Operand 1 |
| 59780 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59781 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59782 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59783 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 59784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 59785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59786 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59787 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59790 | GIR_RootConstrainSelectedInstOperands, |
| 59791 | // GIR_Coverage, 49481, |
| 59792 | GIR_EraseRootFromParent_Done, |
| 59793 | // Label 4099: @153575 |
| 59794 | GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(153623), // Rule ID 49502 // |
| 59795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 59796 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59797 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59799 | // MIs[0] Operand 1 |
| 59800 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59801 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59802 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59803 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 59805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59806 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59807 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59810 | GIR_RootConstrainSelectedInstOperands, |
| 59811 | // GIR_Coverage, 49502, |
| 59812 | GIR_EraseRootFromParent_Done, |
| 59813 | // Label 4100: @153623 |
| 59814 | GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(153671), // Rule ID 49503 // |
| 59815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59817 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59819 | // MIs[0] Operand 1 |
| 59820 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 59821 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59822 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59823 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 59825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59826 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 59827 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 59828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59830 | GIR_RootConstrainSelectedInstOperands, |
| 59831 | // GIR_Coverage, 49503, |
| 59832 | GIR_EraseRootFromParent_Done, |
| 59833 | // Label 4101: @153671 |
| 59834 | GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(153719), // Rule ID 49510 // |
| 59835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59837 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59839 | // MIs[0] Operand 1 |
| 59840 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59841 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59842 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59843 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 59844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 59845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59846 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59847 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59850 | GIR_RootConstrainSelectedInstOperands, |
| 59851 | // GIR_Coverage, 49510, |
| 59852 | GIR_EraseRootFromParent_Done, |
| 59853 | // Label 4102: @153719 |
| 59854 | GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(153767), // Rule ID 49511 // |
| 59855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 59857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 59858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59859 | // MIs[0] Operand 1 |
| 59860 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59862 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59863 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 59864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF4), |
| 59865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59866 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59867 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 59870 | GIR_RootConstrainSelectedInstOperands, |
| 59871 | // GIR_Coverage, 49511, |
| 59872 | GIR_EraseRootFromParent_Done, |
| 59873 | // Label 4103: @153767 |
| 59874 | GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(153815), // Rule ID 49516 // |
| 59875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59876 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59877 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59879 | // MIs[0] Operand 1 |
| 59880 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59881 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59882 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59883 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 59884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 59885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59886 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59887 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59890 | GIR_RootConstrainSelectedInstOperands, |
| 59891 | // GIR_Coverage, 49516, |
| 59892 | GIR_EraseRootFromParent_Done, |
| 59893 | // Label 4104: @153815 |
| 59894 | GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(153863), // Rule ID 49517 // |
| 59895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 59897 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 59898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59899 | // MIs[0] Operand 1 |
| 59900 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59901 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59902 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59903 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 59904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 59905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59906 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59907 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 59910 | GIR_RootConstrainSelectedInstOperands, |
| 59911 | // GIR_Coverage, 49517, |
| 59912 | GIR_EraseRootFromParent_Done, |
| 59913 | // Label 4105: @153863 |
| 59914 | GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(153911), // Rule ID 49524 // |
| 59915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59916 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59917 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59919 | // MIs[0] Operand 1 |
| 59920 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59921 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59922 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59923 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 59924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 59925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59926 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59927 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59930 | GIR_RootConstrainSelectedInstOperands, |
| 59931 | // GIR_Coverage, 49524, |
| 59932 | GIR_EraseRootFromParent_Done, |
| 59933 | // Label 4106: @153911 |
| 59934 | GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(153959), // Rule ID 49525 // |
| 59935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 59936 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 59937 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 59938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59939 | // MIs[0] Operand 1 |
| 59940 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59941 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59942 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59943 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 59944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 59945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59946 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59947 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 59950 | GIR_RootConstrainSelectedInstOperands, |
| 59951 | // GIR_Coverage, 49525, |
| 59952 | GIR_EraseRootFromParent_Done, |
| 59953 | // Label 4107: @153959 |
| 59954 | GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(154007), // Rule ID 49546 // |
| 59955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 59956 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59957 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59959 | // MIs[0] Operand 1 |
| 59960 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59962 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59963 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 59964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 59965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59966 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59967 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59970 | GIR_RootConstrainSelectedInstOperands, |
| 59971 | // GIR_Coverage, 49546, |
| 59972 | GIR_EraseRootFromParent_Done, |
| 59973 | // Label 4108: @154007 |
| 59974 | GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(154055), // Rule ID 49547 // |
| 59975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 59976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 59977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 59978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 59979 | // MIs[0] Operand 1 |
| 59980 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 59981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59982 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 59983 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 59984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 59985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 59986 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 59987 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 59988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 59989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 59990 | GIR_RootConstrainSelectedInstOperands, |
| 59991 | // GIR_Coverage, 49547, |
| 59992 | GIR_EraseRootFromParent_Done, |
| 59993 | // Label 4109: @154055 |
| 59994 | GIM_Reject, |
| 59995 | // Label 3850: @154056 |
| 59996 | GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(154104), // Rule ID 49118 // |
| 59997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 59998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 59999 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60001 | // MIs[0] Operand 1 |
| 60002 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60003 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60004 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60005 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF2), |
| 60007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60008 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60009 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60012 | GIR_RootConstrainSelectedInstOperands, |
| 60013 | // GIR_Coverage, 49118, |
| 60014 | GIR_EraseRootFromParent_Done, |
| 60015 | // Label 4110: @154104 |
| 60016 | GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(154152), // Rule ID 49119 // |
| 60017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60021 | // MIs[0] Operand 1 |
| 60022 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60025 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_MF2), |
| 60027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60028 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60029 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60032 | GIR_RootConstrainSelectedInstOperands, |
| 60033 | // GIR_Coverage, 49119, |
| 60034 | GIR_EraseRootFromParent_Done, |
| 60035 | // Label 4111: @154152 |
| 60036 | GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(154200), // Rule ID 49128 // |
| 60037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60038 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60039 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60041 | // MIs[0] Operand 1 |
| 60042 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60044 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60045 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 60046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 60047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60049 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60052 | GIR_RootConstrainSelectedInstOperands, |
| 60053 | // GIR_Coverage, 49128, |
| 60054 | GIR_EraseRootFromParent_Done, |
| 60055 | // Label 4112: @154200 |
| 60056 | GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(154248), // Rule ID 49129 // |
| 60057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60061 | // MIs[0] Operand 1 |
| 60062 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60063 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60064 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60065 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 60066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 60067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60068 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60069 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60072 | GIR_RootConstrainSelectedInstOperands, |
| 60073 | // GIR_Coverage, 49129, |
| 60074 | GIR_EraseRootFromParent_Done, |
| 60075 | // Label 4113: @154248 |
| 60076 | GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(154296), // Rule ID 49146 // |
| 60077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60079 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60081 | // MIs[0] Operand 1 |
| 60082 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60083 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60084 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60085 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 60086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 60087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60089 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60092 | GIR_RootConstrainSelectedInstOperands, |
| 60093 | // GIR_Coverage, 49146, |
| 60094 | GIR_EraseRootFromParent_Done, |
| 60095 | // Label 4114: @154296 |
| 60096 | GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(154344), // Rule ID 49147 // |
| 60097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60098 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60099 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60101 | // MIs[0] Operand 1 |
| 60102 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60104 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60105 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 60106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 60107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60108 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60109 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60112 | GIR_RootConstrainSelectedInstOperands, |
| 60113 | // GIR_Coverage, 49147, |
| 60114 | GIR_EraseRootFromParent_Done, |
| 60115 | // Label 4115: @154344 |
| 60116 | GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(154392), // Rule ID 49154 // |
| 60117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 60118 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60119 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60121 | // MIs[0] Operand 1 |
| 60122 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60124 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60125 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 60126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 60127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60128 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60129 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60132 | GIR_RootConstrainSelectedInstOperands, |
| 60133 | // GIR_Coverage, 49154, |
| 60134 | GIR_EraseRootFromParent_Done, |
| 60135 | // Label 4116: @154392 |
| 60136 | GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(154440), // Rule ID 49155 // |
| 60137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 60138 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60139 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60141 | // MIs[0] Operand 1 |
| 60142 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 60143 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60144 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60145 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 60146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 60147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60148 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60149 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60152 | GIR_RootConstrainSelectedInstOperands, |
| 60153 | // GIR_Coverage, 49155, |
| 60154 | GIR_EraseRootFromParent_Done, |
| 60155 | // Label 4117: @154440 |
| 60156 | GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(154488), // Rule ID 49162 // |
| 60157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60158 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60159 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60161 | // MIs[0] Operand 1 |
| 60162 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60164 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60165 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF2), |
| 60167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60168 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60169 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60172 | GIR_RootConstrainSelectedInstOperands, |
| 60173 | // GIR_Coverage, 49162, |
| 60174 | GIR_EraseRootFromParent_Done, |
| 60175 | // Label 4118: @154488 |
| 60176 | GIM_Try, /*On fail goto*//*Label 4119*/ GIMT_Encode4(154536), // Rule ID 49163 // |
| 60177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60178 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60179 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60181 | // MIs[0] Operand 1 |
| 60182 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60183 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60184 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60185 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_MF2), |
| 60187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60188 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60189 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60192 | GIR_RootConstrainSelectedInstOperands, |
| 60193 | // GIR_Coverage, 49163, |
| 60194 | GIR_EraseRootFromParent_Done, |
| 60195 | // Label 4119: @154536 |
| 60196 | GIM_Try, /*On fail goto*//*Label 4120*/ GIMT_Encode4(154584), // Rule ID 49172 // |
| 60197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60199 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60201 | // MIs[0] Operand 1 |
| 60202 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60203 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60204 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60205 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 60206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 60207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60208 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60209 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60212 | GIR_RootConstrainSelectedInstOperands, |
| 60213 | // GIR_Coverage, 49172, |
| 60214 | GIR_EraseRootFromParent_Done, |
| 60215 | // Label 4120: @154584 |
| 60216 | GIM_Try, /*On fail goto*//*Label 4121*/ GIMT_Encode4(154632), // Rule ID 49173 // |
| 60217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60218 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60219 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60221 | // MIs[0] Operand 1 |
| 60222 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60223 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60224 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60225 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 60226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 60227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60228 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60229 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60232 | GIR_RootConstrainSelectedInstOperands, |
| 60233 | // GIR_Coverage, 49173, |
| 60234 | GIR_EraseRootFromParent_Done, |
| 60235 | // Label 4121: @154632 |
| 60236 | GIM_Try, /*On fail goto*//*Label 4122*/ GIMT_Encode4(154680), // Rule ID 49190 // |
| 60237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60241 | // MIs[0] Operand 1 |
| 60242 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60243 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60244 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60245 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 60246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 60247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60248 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60249 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60252 | GIR_RootConstrainSelectedInstOperands, |
| 60253 | // GIR_Coverage, 49190, |
| 60254 | GIR_EraseRootFromParent_Done, |
| 60255 | // Label 4122: @154680 |
| 60256 | GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(154728), // Rule ID 49191 // |
| 60257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60258 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60259 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60261 | // MIs[0] Operand 1 |
| 60262 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60263 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60264 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60265 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 60266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 60267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60268 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60269 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60272 | GIR_RootConstrainSelectedInstOperands, |
| 60273 | // GIR_Coverage, 49191, |
| 60274 | GIR_EraseRootFromParent_Done, |
| 60275 | // Label 4123: @154728 |
| 60276 | GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(154776), // Rule ID 49198 // |
| 60277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 60278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60279 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60281 | // MIs[0] Operand 1 |
| 60282 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60283 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60284 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60285 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 60286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 60287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60288 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60289 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60292 | GIR_RootConstrainSelectedInstOperands, |
| 60293 | // GIR_Coverage, 49198, |
| 60294 | GIR_EraseRootFromParent_Done, |
| 60295 | // Label 4124: @154776 |
| 60296 | GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(154824), // Rule ID 49199 // |
| 60297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 60298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60299 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60301 | // MIs[0] Operand 1 |
| 60302 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 60303 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60304 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60305 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 60306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 60307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60308 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60309 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60312 | GIR_RootConstrainSelectedInstOperands, |
| 60313 | // GIR_Coverage, 49199, |
| 60314 | GIR_EraseRootFromParent_Done, |
| 60315 | // Label 4125: @154824 |
| 60316 | GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(154872), // Rule ID 49206 // |
| 60317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60318 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60319 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60321 | // MIs[0] Operand 1 |
| 60322 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60324 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60325 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 60327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60329 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60332 | GIR_RootConstrainSelectedInstOperands, |
| 60333 | // GIR_Coverage, 49206, |
| 60334 | GIR_EraseRootFromParent_Done, |
| 60335 | // Label 4126: @154872 |
| 60336 | GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(154920), // Rule ID 49207 // |
| 60337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60338 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60339 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60341 | // MIs[0] Operand 1 |
| 60342 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60343 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60344 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60345 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 60347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60348 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60349 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60352 | GIR_RootConstrainSelectedInstOperands, |
| 60353 | // GIR_Coverage, 49207, |
| 60354 | GIR_EraseRootFromParent_Done, |
| 60355 | // Label 4127: @154920 |
| 60356 | GIM_Try, /*On fail goto*//*Label 4128*/ GIMT_Encode4(154968), // Rule ID 49216 // |
| 60357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60359 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60361 | // MIs[0] Operand 1 |
| 60362 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60363 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60364 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60365 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 60366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 60367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60368 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60369 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60372 | GIR_RootConstrainSelectedInstOperands, |
| 60373 | // GIR_Coverage, 49216, |
| 60374 | GIR_EraseRootFromParent_Done, |
| 60375 | // Label 4128: @154968 |
| 60376 | GIM_Try, /*On fail goto*//*Label 4129*/ GIMT_Encode4(155016), // Rule ID 49217 // |
| 60377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60378 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60379 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60381 | // MIs[0] Operand 1 |
| 60382 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60383 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60384 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60385 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 60386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 60387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60388 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60389 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60392 | GIR_RootConstrainSelectedInstOperands, |
| 60393 | // GIR_Coverage, 49217, |
| 60394 | GIR_EraseRootFromParent_Done, |
| 60395 | // Label 4129: @155016 |
| 60396 | GIM_Try, /*On fail goto*//*Label 4130*/ GIMT_Encode4(155064), // Rule ID 49234 // |
| 60397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60399 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60401 | // MIs[0] Operand 1 |
| 60402 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60403 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60404 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60405 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 60406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 60407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60408 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60409 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60412 | GIR_RootConstrainSelectedInstOperands, |
| 60413 | // GIR_Coverage, 49234, |
| 60414 | GIR_EraseRootFromParent_Done, |
| 60415 | // Label 4130: @155064 |
| 60416 | GIM_Try, /*On fail goto*//*Label 4131*/ GIMT_Encode4(155112), // Rule ID 49235 // |
| 60417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60418 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60419 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60421 | // MIs[0] Operand 1 |
| 60422 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60423 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60424 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60425 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 60426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 60427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60428 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60429 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60432 | GIR_RootConstrainSelectedInstOperands, |
| 60433 | // GIR_Coverage, 49235, |
| 60434 | GIR_EraseRootFromParent_Done, |
| 60435 | // Label 4131: @155112 |
| 60436 | GIM_Try, /*On fail goto*//*Label 4132*/ GIMT_Encode4(155160), // Rule ID 49242 // |
| 60437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 60438 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60439 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60441 | // MIs[0] Operand 1 |
| 60442 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60444 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60445 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 60446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 60447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60448 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60449 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60452 | GIR_RootConstrainSelectedInstOperands, |
| 60453 | // GIR_Coverage, 49242, |
| 60454 | GIR_EraseRootFromParent_Done, |
| 60455 | // Label 4132: @155160 |
| 60456 | GIM_Try, /*On fail goto*//*Label 4133*/ GIMT_Encode4(155208), // Rule ID 49243 // |
| 60457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 60458 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60459 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60461 | // MIs[0] Operand 1 |
| 60462 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 60463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60464 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60465 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 60466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 60467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60468 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60469 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60472 | GIR_RootConstrainSelectedInstOperands, |
| 60473 | // GIR_Coverage, 49243, |
| 60474 | GIR_EraseRootFromParent_Done, |
| 60475 | // Label 4133: @155208 |
| 60476 | GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(155256), // Rule ID 49248 // |
| 60477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60478 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60479 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60481 | // MIs[0] Operand 1 |
| 60482 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60484 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60485 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 60487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60488 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60489 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60492 | GIR_RootConstrainSelectedInstOperands, |
| 60493 | // GIR_Coverage, 49248, |
| 60494 | GIR_EraseRootFromParent_Done, |
| 60495 | // Label 4134: @155256 |
| 60496 | GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(155304), // Rule ID 49249 // |
| 60497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60498 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60499 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60501 | // MIs[0] Operand 1 |
| 60502 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60504 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60505 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_MF2), |
| 60507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60508 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60509 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60512 | GIR_RootConstrainSelectedInstOperands, |
| 60513 | // GIR_Coverage, 49249, |
| 60514 | GIR_EraseRootFromParent_Done, |
| 60515 | // Label 4135: @155304 |
| 60516 | GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(155352), // Rule ID 49258 // |
| 60517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60518 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60519 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60521 | // MIs[0] Operand 1 |
| 60522 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60524 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60525 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 60526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 60527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60528 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60529 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60532 | GIR_RootConstrainSelectedInstOperands, |
| 60533 | // GIR_Coverage, 49258, |
| 60534 | GIR_EraseRootFromParent_Done, |
| 60535 | // Label 4136: @155352 |
| 60536 | GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(155400), // Rule ID 49259 // |
| 60537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60538 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60539 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60541 | // MIs[0] Operand 1 |
| 60542 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60543 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60544 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60545 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 60546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 60547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60548 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60549 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60552 | GIR_RootConstrainSelectedInstOperands, |
| 60553 | // GIR_Coverage, 49259, |
| 60554 | GIR_EraseRootFromParent_Done, |
| 60555 | // Label 4137: @155400 |
| 60556 | GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(155448), // Rule ID 49276 // |
| 60557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60558 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60559 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60561 | // MIs[0] Operand 1 |
| 60562 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60563 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60564 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60565 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 60566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 60567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60568 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60569 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60572 | GIR_RootConstrainSelectedInstOperands, |
| 60573 | // GIR_Coverage, 49276, |
| 60574 | GIR_EraseRootFromParent_Done, |
| 60575 | // Label 4138: @155448 |
| 60576 | GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(155496), // Rule ID 49277 // |
| 60577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60578 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60579 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60581 | // MIs[0] Operand 1 |
| 60582 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60583 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60584 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60585 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 60586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 60587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60588 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60589 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60592 | GIR_RootConstrainSelectedInstOperands, |
| 60593 | // GIR_Coverage, 49277, |
| 60594 | GIR_EraseRootFromParent_Done, |
| 60595 | // Label 4139: @155496 |
| 60596 | GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(155544), // Rule ID 49284 // |
| 60597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 60598 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60599 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60601 | // MIs[0] Operand 1 |
| 60602 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60603 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60604 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60605 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 60606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 60607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60608 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60609 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60612 | GIR_RootConstrainSelectedInstOperands, |
| 60613 | // GIR_Coverage, 49284, |
| 60614 | GIR_EraseRootFromParent_Done, |
| 60615 | // Label 4140: @155544 |
| 60616 | GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(155592), // Rule ID 49285 // |
| 60617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 60618 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60619 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60621 | // MIs[0] Operand 1 |
| 60622 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 60623 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60624 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60625 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 60626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 60627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60628 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60629 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60632 | GIR_RootConstrainSelectedInstOperands, |
| 60633 | // GIR_Coverage, 49285, |
| 60634 | GIR_EraseRootFromParent_Done, |
| 60635 | // Label 4141: @155592 |
| 60636 | GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(155640), // Rule ID 49292 // |
| 60637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60638 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60639 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60641 | // MIs[0] Operand 1 |
| 60642 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60643 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60644 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60645 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 60647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60648 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60649 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60652 | GIR_RootConstrainSelectedInstOperands, |
| 60653 | // GIR_Coverage, 49292, |
| 60654 | GIR_EraseRootFromParent_Done, |
| 60655 | // Label 4142: @155640 |
| 60656 | GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(155688), // Rule ID 49293 // |
| 60657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60659 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60661 | // MIs[0] Operand 1 |
| 60662 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60663 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60664 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60665 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 60667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60668 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60669 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60672 | GIR_RootConstrainSelectedInstOperands, |
| 60673 | // GIR_Coverage, 49293, |
| 60674 | GIR_EraseRootFromParent_Done, |
| 60675 | // Label 4143: @155688 |
| 60676 | GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(155736), // Rule ID 49302 // |
| 60677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60678 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60679 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60681 | // MIs[0] Operand 1 |
| 60682 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60684 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60685 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 60686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 60687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60688 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60689 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60692 | GIR_RootConstrainSelectedInstOperands, |
| 60693 | // GIR_Coverage, 49302, |
| 60694 | GIR_EraseRootFromParent_Done, |
| 60695 | // Label 4144: @155736 |
| 60696 | GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(155784), // Rule ID 49303 // |
| 60697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60698 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60699 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60701 | // MIs[0] Operand 1 |
| 60702 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60703 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60704 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60705 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 60706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 60707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60708 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60709 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60712 | GIR_RootConstrainSelectedInstOperands, |
| 60713 | // GIR_Coverage, 49303, |
| 60714 | GIR_EraseRootFromParent_Done, |
| 60715 | // Label 4145: @155784 |
| 60716 | GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(155832), // Rule ID 49320 // |
| 60717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60718 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60719 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60721 | // MIs[0] Operand 1 |
| 60722 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60724 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60725 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 60726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 60727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60728 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60729 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60732 | GIR_RootConstrainSelectedInstOperands, |
| 60733 | // GIR_Coverage, 49320, |
| 60734 | GIR_EraseRootFromParent_Done, |
| 60735 | // Label 4146: @155832 |
| 60736 | GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(155880), // Rule ID 49321 // |
| 60737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60738 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60739 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60741 | // MIs[0] Operand 1 |
| 60742 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60743 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60744 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60745 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 60746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 60747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60748 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60749 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60752 | GIR_RootConstrainSelectedInstOperands, |
| 60753 | // GIR_Coverage, 49321, |
| 60754 | GIR_EraseRootFromParent_Done, |
| 60755 | // Label 4147: @155880 |
| 60756 | GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(155928), // Rule ID 49328 // |
| 60757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 60758 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60759 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60761 | // MIs[0] Operand 1 |
| 60762 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60763 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60764 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60765 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 60766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 60767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60768 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60769 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60772 | GIR_RootConstrainSelectedInstOperands, |
| 60773 | // GIR_Coverage, 49328, |
| 60774 | GIR_EraseRootFromParent_Done, |
| 60775 | // Label 4148: @155928 |
| 60776 | GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(155976), // Rule ID 49329 // |
| 60777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 60778 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60779 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60781 | // MIs[0] Operand 1 |
| 60782 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 60783 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60784 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60785 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 60786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 60787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60788 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60789 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60792 | GIR_RootConstrainSelectedInstOperands, |
| 60793 | // GIR_Coverage, 49329, |
| 60794 | GIR_EraseRootFromParent_Done, |
| 60795 | // Label 4149: @155976 |
| 60796 | GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(156024), // Rule ID 49336 // |
| 60797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60798 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60799 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60801 | // MIs[0] Operand 1 |
| 60802 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60804 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60805 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 60807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60808 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60809 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60812 | GIR_RootConstrainSelectedInstOperands, |
| 60813 | // GIR_Coverage, 49336, |
| 60814 | GIR_EraseRootFromParent_Done, |
| 60815 | // Label 4150: @156024 |
| 60816 | GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(156072), // Rule ID 49337 // |
| 60817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60818 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60819 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60821 | // MIs[0] Operand 1 |
| 60822 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60823 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60824 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60825 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_MF2), |
| 60827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60828 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60829 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60832 | GIR_RootConstrainSelectedInstOperands, |
| 60833 | // GIR_Coverage, 49337, |
| 60834 | GIR_EraseRootFromParent_Done, |
| 60835 | // Label 4151: @156072 |
| 60836 | GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(156120), // Rule ID 49346 // |
| 60837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60839 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60841 | // MIs[0] Operand 1 |
| 60842 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60844 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60845 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 60846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 60847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60848 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60849 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60852 | GIR_RootConstrainSelectedInstOperands, |
| 60853 | // GIR_Coverage, 49346, |
| 60854 | GIR_EraseRootFromParent_Done, |
| 60855 | // Label 4152: @156120 |
| 60856 | GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(156168), // Rule ID 49347 // |
| 60857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60859 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 60860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60861 | // MIs[0] Operand 1 |
| 60862 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60863 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60864 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60865 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 60866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 60867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60868 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60869 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 60872 | GIR_RootConstrainSelectedInstOperands, |
| 60873 | // GIR_Coverage, 49347, |
| 60874 | GIR_EraseRootFromParent_Done, |
| 60875 | // Label 4153: @156168 |
| 60876 | GIM_Try, /*On fail goto*//*Label 4154*/ GIMT_Encode4(156216), // Rule ID 49364 // |
| 60877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60878 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60879 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60881 | // MIs[0] Operand 1 |
| 60882 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60883 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60884 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60885 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 60886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 60887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60888 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60889 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60892 | GIR_RootConstrainSelectedInstOperands, |
| 60893 | // GIR_Coverage, 49364, |
| 60894 | GIR_EraseRootFromParent_Done, |
| 60895 | // Label 4154: @156216 |
| 60896 | GIM_Try, /*On fail goto*//*Label 4155*/ GIMT_Encode4(156264), // Rule ID 49365 // |
| 60897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60898 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 60899 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 60900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60901 | // MIs[0] Operand 1 |
| 60902 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60903 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60904 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 60905 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 60906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 60907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60908 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60909 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 60912 | GIR_RootConstrainSelectedInstOperands, |
| 60913 | // GIR_Coverage, 49365, |
| 60914 | GIR_EraseRootFromParent_Done, |
| 60915 | // Label 4155: @156264 |
| 60916 | GIM_Try, /*On fail goto*//*Label 4156*/ GIMT_Encode4(156312), // Rule ID 49372 // |
| 60917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 60918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60919 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60921 | // MIs[0] Operand 1 |
| 60922 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60924 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60925 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 60926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 60927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60928 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60929 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60932 | GIR_RootConstrainSelectedInstOperands, |
| 60933 | // GIR_Coverage, 49372, |
| 60934 | GIR_EraseRootFromParent_Done, |
| 60935 | // Label 4156: @156312 |
| 60936 | GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(156360), // Rule ID 49373 // |
| 60937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 60938 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 60939 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 60940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60941 | // MIs[0] Operand 1 |
| 60942 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 60943 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60944 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 60945 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 60946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 60947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60948 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 60949 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 60950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 60952 | GIR_RootConstrainSelectedInstOperands, |
| 60953 | // GIR_Coverage, 49373, |
| 60954 | GIR_EraseRootFromParent_Done, |
| 60955 | // Label 4157: @156360 |
| 60956 | GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(156408), // Rule ID 49380 // |
| 60957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60958 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60959 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60961 | // MIs[0] Operand 1 |
| 60962 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 60963 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60964 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60965 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 60966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 60967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60968 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60969 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60972 | GIR_RootConstrainSelectedInstOperands, |
| 60973 | // GIR_Coverage, 49380, |
| 60974 | GIR_EraseRootFromParent_Done, |
| 60975 | // Label 4158: @156408 |
| 60976 | GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(156456), // Rule ID 49381 // |
| 60977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 60978 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 60979 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 60980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60981 | // MIs[0] Operand 1 |
| 60982 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 60983 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60984 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 60985 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 60986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 60987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 60988 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 60989 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 60990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 60991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 60992 | GIR_RootConstrainSelectedInstOperands, |
| 60993 | // GIR_Coverage, 49381, |
| 60994 | GIR_EraseRootFromParent_Done, |
| 60995 | // Label 4159: @156456 |
| 60996 | GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(156504), // Rule ID 49390 // |
| 60997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 60998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 60999 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61001 | // MIs[0] Operand 1 |
| 61002 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 61003 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61004 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61005 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 61007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61008 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61009 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61012 | GIR_RootConstrainSelectedInstOperands, |
| 61013 | // GIR_Coverage, 49390, |
| 61014 | GIR_EraseRootFromParent_Done, |
| 61015 | // Label 4160: @156504 |
| 61016 | GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(156552), // Rule ID 49391 // |
| 61017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61021 | // MIs[0] Operand 1 |
| 61022 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 61023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61025 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 61027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61028 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61029 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61032 | GIR_RootConstrainSelectedInstOperands, |
| 61033 | // GIR_Coverage, 49391, |
| 61034 | GIR_EraseRootFromParent_Done, |
| 61035 | // Label 4161: @156552 |
| 61036 | GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(156600), // Rule ID 49408 // |
| 61037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61038 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61039 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61041 | // MIs[0] Operand 1 |
| 61042 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 61043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61044 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61045 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 61046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 61047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61049 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61052 | GIR_RootConstrainSelectedInstOperands, |
| 61053 | // GIR_Coverage, 49408, |
| 61054 | GIR_EraseRootFromParent_Done, |
| 61055 | // Label 4162: @156600 |
| 61056 | GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(156648), // Rule ID 49409 // |
| 61057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61061 | // MIs[0] Operand 1 |
| 61062 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 61063 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61064 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61065 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 61066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 61067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61068 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61069 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61072 | GIR_RootConstrainSelectedInstOperands, |
| 61073 | // GIR_Coverage, 49409, |
| 61074 | GIR_EraseRootFromParent_Done, |
| 61075 | // Label 4163: @156648 |
| 61076 | GIM_Try, /*On fail goto*//*Label 4164*/ GIMT_Encode4(156696), // Rule ID 49416 // |
| 61077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 61078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61079 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61081 | // MIs[0] Operand 1 |
| 61082 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 61083 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61084 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61085 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 61086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 61087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61089 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61092 | GIR_RootConstrainSelectedInstOperands, |
| 61093 | // GIR_Coverage, 49416, |
| 61094 | GIR_EraseRootFromParent_Done, |
| 61095 | // Label 4164: @156696 |
| 61096 | GIM_Try, /*On fail goto*//*Label 4165*/ GIMT_Encode4(156744), // Rule ID 49417 // |
| 61097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 61098 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61099 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61101 | // MIs[0] Operand 1 |
| 61102 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 61103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61104 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61105 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 61106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 61107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61108 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61109 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61112 | GIR_RootConstrainSelectedInstOperands, |
| 61113 | // GIR_Coverage, 49417, |
| 61114 | GIR_EraseRootFromParent_Done, |
| 61115 | // Label 4165: @156744 |
| 61116 | GIM_Try, /*On fail goto*//*Label 4166*/ GIMT_Encode4(156792), // Rule ID 49424 // |
| 61117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61118 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 61119 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 61120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61121 | // MIs[0] Operand 1 |
| 61122 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61124 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61125 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 61126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 61127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61128 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61129 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61132 | GIR_RootConstrainSelectedInstOperands, |
| 61133 | // GIR_Coverage, 49424, |
| 61134 | GIR_EraseRootFromParent_Done, |
| 61135 | // Label 4166: @156792 |
| 61136 | GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(156840), // Rule ID 49425 // |
| 61137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61138 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 61139 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 61140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61141 | // MIs[0] Operand 1 |
| 61142 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61143 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61144 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61145 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 61146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_MF2), |
| 61147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61148 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61149 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61152 | GIR_RootConstrainSelectedInstOperands, |
| 61153 | // GIR_Coverage, 49425, |
| 61154 | GIR_EraseRootFromParent_Done, |
| 61155 | // Label 4167: @156840 |
| 61156 | GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(156888), // Rule ID 49434 // |
| 61157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61158 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61159 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61161 | // MIs[0] Operand 1 |
| 61162 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61164 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61165 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 61167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61168 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61169 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61172 | GIR_RootConstrainSelectedInstOperands, |
| 61173 | // GIR_Coverage, 49434, |
| 61174 | GIR_EraseRootFromParent_Done, |
| 61175 | // Label 4168: @156888 |
| 61176 | GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(156936), // Rule ID 49435 // |
| 61177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61178 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61179 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61181 | // MIs[0] Operand 1 |
| 61182 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61183 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61184 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61185 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 61187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61188 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61189 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61192 | GIR_RootConstrainSelectedInstOperands, |
| 61193 | // GIR_Coverage, 49435, |
| 61194 | GIR_EraseRootFromParent_Done, |
| 61195 | // Label 4169: @156936 |
| 61196 | GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(156984), // Rule ID 49452 // |
| 61197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61199 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61201 | // MIs[0] Operand 1 |
| 61202 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61203 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61204 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61205 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 61206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 61207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61208 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61209 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61212 | GIR_RootConstrainSelectedInstOperands, |
| 61213 | // GIR_Coverage, 49452, |
| 61214 | GIR_EraseRootFromParent_Done, |
| 61215 | // Label 4170: @156984 |
| 61216 | GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(157032), // Rule ID 49453 // |
| 61217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61218 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61219 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61221 | // MIs[0] Operand 1 |
| 61222 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61223 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61224 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61225 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 61226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 61227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61228 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61229 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61232 | GIR_RootConstrainSelectedInstOperands, |
| 61233 | // GIR_Coverage, 49453, |
| 61234 | GIR_EraseRootFromParent_Done, |
| 61235 | // Label 4171: @157032 |
| 61236 | GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(157080), // Rule ID 49460 // |
| 61237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 61238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61241 | // MIs[0] Operand 1 |
| 61242 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61243 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61244 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61245 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 61246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 61247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61248 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61249 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61252 | GIR_RootConstrainSelectedInstOperands, |
| 61253 | // GIR_Coverage, 49460, |
| 61254 | GIR_EraseRootFromParent_Done, |
| 61255 | // Label 4172: @157080 |
| 61256 | GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(157128), // Rule ID 49461 // |
| 61257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 61258 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61259 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61261 | // MIs[0] Operand 1 |
| 61262 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 61263 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61264 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61265 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 61266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 61267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61268 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61269 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61272 | GIR_RootConstrainSelectedInstOperands, |
| 61273 | // GIR_Coverage, 49461, |
| 61274 | GIR_EraseRootFromParent_Done, |
| 61275 | // Label 4173: @157128 |
| 61276 | GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(157176), // Rule ID 49468 // |
| 61277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 61279 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 61280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61281 | // MIs[0] Operand 1 |
| 61282 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61283 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61284 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61285 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 61286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 61287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61288 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61289 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61292 | GIR_RootConstrainSelectedInstOperands, |
| 61293 | // GIR_Coverage, 49468, |
| 61294 | GIR_EraseRootFromParent_Done, |
| 61295 | // Label 4174: @157176 |
| 61296 | GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(157224), // Rule ID 49469 // |
| 61297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 61299 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 61300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61301 | // MIs[0] Operand 1 |
| 61302 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61303 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61304 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61305 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 61306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 61307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61308 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61309 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61312 | GIR_RootConstrainSelectedInstOperands, |
| 61313 | // GIR_Coverage, 49469, |
| 61314 | GIR_EraseRootFromParent_Done, |
| 61315 | // Label 4175: @157224 |
| 61316 | GIM_Try, /*On fail goto*//*Label 4176*/ GIMT_Encode4(157272), // Rule ID 49478 // |
| 61317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61318 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61319 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61321 | // MIs[0] Operand 1 |
| 61322 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61324 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61325 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 61327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61329 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61332 | GIR_RootConstrainSelectedInstOperands, |
| 61333 | // GIR_Coverage, 49478, |
| 61334 | GIR_EraseRootFromParent_Done, |
| 61335 | // Label 4176: @157272 |
| 61336 | GIM_Try, /*On fail goto*//*Label 4177*/ GIMT_Encode4(157320), // Rule ID 49479 // |
| 61337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61338 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61339 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61341 | // MIs[0] Operand 1 |
| 61342 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61343 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61344 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61345 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 61347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61348 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61349 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61352 | GIR_RootConstrainSelectedInstOperands, |
| 61353 | // GIR_Coverage, 49479, |
| 61354 | GIR_EraseRootFromParent_Done, |
| 61355 | // Label 4177: @157320 |
| 61356 | GIM_Try, /*On fail goto*//*Label 4178*/ GIMT_Encode4(157368), // Rule ID 49496 // |
| 61357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61359 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61361 | // MIs[0] Operand 1 |
| 61362 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61363 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61364 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61365 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 61366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 61367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61368 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61369 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61372 | GIR_RootConstrainSelectedInstOperands, |
| 61373 | // GIR_Coverage, 49496, |
| 61374 | GIR_EraseRootFromParent_Done, |
| 61375 | // Label 4178: @157368 |
| 61376 | GIM_Try, /*On fail goto*//*Label 4179*/ GIMT_Encode4(157416), // Rule ID 49497 // |
| 61377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61378 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61379 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61381 | // MIs[0] Operand 1 |
| 61382 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61383 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61384 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61385 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 61386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 61387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61388 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61389 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61392 | GIR_RootConstrainSelectedInstOperands, |
| 61393 | // GIR_Coverage, 49497, |
| 61394 | GIR_EraseRootFromParent_Done, |
| 61395 | // Label 4179: @157416 |
| 61396 | GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(157464), // Rule ID 49504 // |
| 61397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 61398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61399 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61401 | // MIs[0] Operand 1 |
| 61402 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61403 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61404 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61405 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 61406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 61407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61408 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61409 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61412 | GIR_RootConstrainSelectedInstOperands, |
| 61413 | // GIR_Coverage, 49504, |
| 61414 | GIR_EraseRootFromParent_Done, |
| 61415 | // Label 4180: @157464 |
| 61416 | GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(157512), // Rule ID 49505 // |
| 61417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 61418 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61419 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61421 | // MIs[0] Operand 1 |
| 61422 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 61423 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61424 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61425 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 61426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 61427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61428 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61429 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61432 | GIR_RootConstrainSelectedInstOperands, |
| 61433 | // GIR_Coverage, 49505, |
| 61434 | GIR_EraseRootFromParent_Done, |
| 61435 | // Label 4181: @157512 |
| 61436 | GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(157560), // Rule ID 49512 // |
| 61437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61438 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 61439 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 61440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61441 | // MIs[0] Operand 1 |
| 61442 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61444 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61445 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 61446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 61447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61448 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61449 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61452 | GIR_RootConstrainSelectedInstOperands, |
| 61453 | // GIR_Coverage, 49512, |
| 61454 | GIR_EraseRootFromParent_Done, |
| 61455 | // Label 4182: @157560 |
| 61456 | GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(157608), // Rule ID 49513 // |
| 61457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61458 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 61459 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 61460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61461 | // MIs[0] Operand 1 |
| 61462 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61464 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61465 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 61466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_MF2), |
| 61467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61468 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61469 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61472 | GIR_RootConstrainSelectedInstOperands, |
| 61473 | // GIR_Coverage, 49513, |
| 61474 | GIR_EraseRootFromParent_Done, |
| 61475 | // Label 4183: @157608 |
| 61476 | GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(157656), // Rule ID 49522 // |
| 61477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61478 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61479 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61481 | // MIs[0] Operand 1 |
| 61482 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61484 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61485 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 61487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61488 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61489 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61492 | GIR_RootConstrainSelectedInstOperands, |
| 61493 | // GIR_Coverage, 49522, |
| 61494 | GIR_EraseRootFromParent_Done, |
| 61495 | // Label 4184: @157656 |
| 61496 | GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(157704), // Rule ID 49523 // |
| 61497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61498 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 61499 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 61500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61501 | // MIs[0] Operand 1 |
| 61502 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61504 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61505 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 61507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61508 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61509 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61512 | GIR_RootConstrainSelectedInstOperands, |
| 61513 | // GIR_Coverage, 49523, |
| 61514 | GIR_EraseRootFromParent_Done, |
| 61515 | // Label 4185: @157704 |
| 61516 | GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(157752), // Rule ID 49540 // |
| 61517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61518 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61519 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61521 | // MIs[0] Operand 1 |
| 61522 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61524 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61525 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 61526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 61527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61528 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61529 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61532 | GIR_RootConstrainSelectedInstOperands, |
| 61533 | // GIR_Coverage, 49540, |
| 61534 | GIR_EraseRootFromParent_Done, |
| 61535 | // Label 4186: @157752 |
| 61536 | GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(157800), // Rule ID 49541 // |
| 61537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61538 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 61539 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 61540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61541 | // MIs[0] Operand 1 |
| 61542 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61543 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61544 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61545 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 61546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 61547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61548 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61549 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61552 | GIR_RootConstrainSelectedInstOperands, |
| 61553 | // GIR_Coverage, 49541, |
| 61554 | GIR_EraseRootFromParent_Done, |
| 61555 | // Label 4187: @157800 |
| 61556 | GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(157848), // Rule ID 49548 // |
| 61557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 61558 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61559 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61561 | // MIs[0] Operand 1 |
| 61562 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61563 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61564 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61565 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 61566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 61567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61568 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61569 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61572 | GIR_RootConstrainSelectedInstOperands, |
| 61573 | // GIR_Coverage, 49548, |
| 61574 | GIR_EraseRootFromParent_Done, |
| 61575 | // Label 4188: @157848 |
| 61576 | GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(157896), // Rule ID 49549 // |
| 61577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 61578 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 61579 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 61580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61581 | // MIs[0] Operand 1 |
| 61582 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 61583 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61584 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61585 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 61586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 61587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61588 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 61589 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 61590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61592 | GIR_RootConstrainSelectedInstOperands, |
| 61593 | // GIR_Coverage, 49549, |
| 61594 | GIR_EraseRootFromParent_Done, |
| 61595 | // Label 4189: @157896 |
| 61596 | GIM_Reject, |
| 61597 | // Label 3851: @157897 |
| 61598 | GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(157945), // Rule ID 49126 // |
| 61599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61600 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 61601 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 61602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61603 | // MIs[0] Operand 1 |
| 61604 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61606 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61607 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 61608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 61609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61610 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61611 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61614 | GIR_RootConstrainSelectedInstOperands, |
| 61615 | // GIR_Coverage, 49126, |
| 61616 | GIR_EraseRootFromParent_Done, |
| 61617 | // Label 4190: @157945 |
| 61618 | GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(157993), // Rule ID 49127 // |
| 61619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61620 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 61621 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 61622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61623 | // MIs[0] Operand 1 |
| 61624 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61625 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61626 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61627 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 61628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M1), |
| 61629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61630 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61631 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61634 | GIR_RootConstrainSelectedInstOperands, |
| 61635 | // GIR_Coverage, 49127, |
| 61636 | GIR_EraseRootFromParent_Done, |
| 61637 | // Label 4191: @157993 |
| 61638 | GIM_Try, /*On fail goto*//*Label 4192*/ GIMT_Encode4(158041), // Rule ID 49140 // |
| 61639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 61641 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 61642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61643 | // MIs[0] Operand 1 |
| 61644 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61646 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61647 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 61649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61650 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61651 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61654 | GIR_RootConstrainSelectedInstOperands, |
| 61655 | // GIR_Coverage, 49140, |
| 61656 | GIR_EraseRootFromParent_Done, |
| 61657 | // Label 4192: @158041 |
| 61658 | GIM_Try, /*On fail goto*//*Label 4193*/ GIMT_Encode4(158089), // Rule ID 49141 // |
| 61659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 61661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 61662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61663 | // MIs[0] Operand 1 |
| 61664 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61665 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61666 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61667 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 61669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61670 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61671 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61674 | GIR_RootConstrainSelectedInstOperands, |
| 61675 | // GIR_Coverage, 49141, |
| 61676 | GIR_EraseRootFromParent_Done, |
| 61677 | // Label 4193: @158089 |
| 61678 | GIM_Try, /*On fail goto*//*Label 4194*/ GIMT_Encode4(158137), // Rule ID 49148 // |
| 61679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61680 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 61681 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 61682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61683 | // MIs[0] Operand 1 |
| 61684 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61685 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61686 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61687 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 61688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 61689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61690 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61691 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61694 | GIR_RootConstrainSelectedInstOperands, |
| 61695 | // GIR_Coverage, 49148, |
| 61696 | GIR_EraseRootFromParent_Done, |
| 61697 | // Label 4194: @158137 |
| 61698 | GIM_Try, /*On fail goto*//*Label 4195*/ GIMT_Encode4(158185), // Rule ID 49149 // |
| 61699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 61701 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 61702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61703 | // MIs[0] Operand 1 |
| 61704 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61705 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61706 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61707 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 61708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 61709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61710 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61711 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61714 | GIR_RootConstrainSelectedInstOperands, |
| 61715 | // GIR_Coverage, 49149, |
| 61716 | GIR_EraseRootFromParent_Done, |
| 61717 | // Label 4195: @158185 |
| 61718 | GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(158233), // Rule ID 49156 // |
| 61719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 61720 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 61721 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 61722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61723 | // MIs[0] Operand 1 |
| 61724 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61726 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61727 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 61728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 61729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61730 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61731 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61734 | GIR_RootConstrainSelectedInstOperands, |
| 61735 | // GIR_Coverage, 49156, |
| 61736 | GIR_EraseRootFromParent_Done, |
| 61737 | // Label 4196: @158233 |
| 61738 | GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(158281), // Rule ID 49157 // |
| 61739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 61740 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 61741 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 61742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61743 | // MIs[0] Operand 1 |
| 61744 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 61745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61746 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61747 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 61748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 61749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61750 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61751 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61754 | GIR_RootConstrainSelectedInstOperands, |
| 61755 | // GIR_Coverage, 49157, |
| 61756 | GIR_EraseRootFromParent_Done, |
| 61757 | // Label 4197: @158281 |
| 61758 | GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(158329), // Rule ID 49170 // |
| 61759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 61761 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 61762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61763 | // MIs[0] Operand 1 |
| 61764 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61765 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61766 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61767 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 61768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 61769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61770 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61771 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61774 | GIR_RootConstrainSelectedInstOperands, |
| 61775 | // GIR_Coverage, 49170, |
| 61776 | GIR_EraseRootFromParent_Done, |
| 61777 | // Label 4198: @158329 |
| 61778 | GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(158377), // Rule ID 49171 // |
| 61779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 61781 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 61782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61783 | // MIs[0] Operand 1 |
| 61784 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61785 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61786 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61787 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 61788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M1), |
| 61789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61790 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61791 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61794 | GIR_RootConstrainSelectedInstOperands, |
| 61795 | // GIR_Coverage, 49171, |
| 61796 | GIR_EraseRootFromParent_Done, |
| 61797 | // Label 4199: @158377 |
| 61798 | GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(158425), // Rule ID 49184 // |
| 61799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 61801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 61802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61803 | // MIs[0] Operand 1 |
| 61804 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61806 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61807 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 61809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61810 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61811 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61814 | GIR_RootConstrainSelectedInstOperands, |
| 61815 | // GIR_Coverage, 49184, |
| 61816 | GIR_EraseRootFromParent_Done, |
| 61817 | // Label 4200: @158425 |
| 61818 | GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(158473), // Rule ID 49185 // |
| 61819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61820 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 61821 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 61822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61823 | // MIs[0] Operand 1 |
| 61824 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61826 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61827 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 61829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61830 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61831 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61834 | GIR_RootConstrainSelectedInstOperands, |
| 61835 | // GIR_Coverage, 49185, |
| 61836 | GIR_EraseRootFromParent_Done, |
| 61837 | // Label 4201: @158473 |
| 61838 | GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(158521), // Rule ID 49192 // |
| 61839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61840 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 61841 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 61842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61843 | // MIs[0] Operand 1 |
| 61844 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61845 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61846 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61847 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 61848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 61849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61850 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61851 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61854 | GIR_RootConstrainSelectedInstOperands, |
| 61855 | // GIR_Coverage, 49192, |
| 61856 | GIR_EraseRootFromParent_Done, |
| 61857 | // Label 4202: @158521 |
| 61858 | GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(158569), // Rule ID 49193 // |
| 61859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61860 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 61861 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 61862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61863 | // MIs[0] Operand 1 |
| 61864 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61866 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 61867 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 61868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 61869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61870 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61871 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 61874 | GIR_RootConstrainSelectedInstOperands, |
| 61875 | // GIR_Coverage, 49193, |
| 61876 | GIR_EraseRootFromParent_Done, |
| 61877 | // Label 4203: @158569 |
| 61878 | GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(158617), // Rule ID 49200 // |
| 61879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 61880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 61881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 61882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61883 | // MIs[0] Operand 1 |
| 61884 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61885 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61886 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61887 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 61888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 61889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61890 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61891 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61894 | GIR_RootConstrainSelectedInstOperands, |
| 61895 | // GIR_Coverage, 49200, |
| 61896 | GIR_EraseRootFromParent_Done, |
| 61897 | // Label 4204: @158617 |
| 61898 | GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(158665), // Rule ID 49201 // |
| 61899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 61900 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 61901 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 61902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61903 | // MIs[0] Operand 1 |
| 61904 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 61905 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61906 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 61907 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 61908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 61909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61910 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61911 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 61914 | GIR_RootConstrainSelectedInstOperands, |
| 61915 | // GIR_Coverage, 49201, |
| 61916 | GIR_EraseRootFromParent_Done, |
| 61917 | // Label 4205: @158665 |
| 61918 | GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(158713), // Rule ID 49214 // |
| 61919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 61921 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 61922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61923 | // MIs[0] Operand 1 |
| 61924 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 61925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61926 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61927 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 61928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 61929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61930 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61931 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61934 | GIR_RootConstrainSelectedInstOperands, |
| 61935 | // GIR_Coverage, 49214, |
| 61936 | GIR_EraseRootFromParent_Done, |
| 61937 | // Label 4206: @158713 |
| 61938 | GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(158761), // Rule ID 49215 // |
| 61939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 61941 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 61942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61943 | // MIs[0] Operand 1 |
| 61944 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 61945 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61946 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61947 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 61948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 61949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61950 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61951 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 61954 | GIR_RootConstrainSelectedInstOperands, |
| 61955 | // GIR_Coverage, 49215, |
| 61956 | GIR_EraseRootFromParent_Done, |
| 61957 | // Label 4207: @158761 |
| 61958 | GIM_Try, /*On fail goto*//*Label 4208*/ GIMT_Encode4(158809), // Rule ID 49228 // |
| 61959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 61960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 61961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 61962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61963 | // MIs[0] Operand 1 |
| 61964 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 61965 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61966 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61967 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 61968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 61969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61970 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61971 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61974 | GIR_RootConstrainSelectedInstOperands, |
| 61975 | // GIR_Coverage, 49228, |
| 61976 | GIR_EraseRootFromParent_Done, |
| 61977 | // Label 4208: @158809 |
| 61978 | GIM_Try, /*On fail goto*//*Label 4209*/ GIMT_Encode4(158857), // Rule ID 49229 // |
| 61979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 61980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 61981 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 61982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 61983 | // MIs[0] Operand 1 |
| 61984 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 61985 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61986 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 61987 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 61988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 61989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 61990 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 61991 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 61992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 61993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 61994 | GIR_RootConstrainSelectedInstOperands, |
| 61995 | // GIR_Coverage, 49229, |
| 61996 | GIR_EraseRootFromParent_Done, |
| 61997 | // Label 4209: @158857 |
| 61998 | GIM_Try, /*On fail goto*//*Label 4210*/ GIMT_Encode4(158905), // Rule ID 49236 // |
| 61999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62003 | // MIs[0] Operand 1 |
| 62004 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 62005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62006 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62007 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 62009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62010 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62011 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62014 | GIR_RootConstrainSelectedInstOperands, |
| 62015 | // GIR_Coverage, 49236, |
| 62016 | GIR_EraseRootFromParent_Done, |
| 62017 | // Label 4210: @158905 |
| 62018 | GIM_Try, /*On fail goto*//*Label 4211*/ GIMT_Encode4(158953), // Rule ID 49237 // |
| 62019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62020 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62021 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62023 | // MIs[0] Operand 1 |
| 62024 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 62025 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62026 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62027 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 62029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62030 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62031 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62034 | GIR_RootConstrainSelectedInstOperands, |
| 62035 | // GIR_Coverage, 49237, |
| 62036 | GIR_EraseRootFromParent_Done, |
| 62037 | // Label 4211: @158953 |
| 62038 | GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(159001), // Rule ID 49244 // |
| 62039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 62040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62041 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62043 | // MIs[0] Operand 1 |
| 62044 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 62045 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62046 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62047 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 62048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 62049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62050 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62051 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62054 | GIR_RootConstrainSelectedInstOperands, |
| 62055 | // GIR_Coverage, 49244, |
| 62056 | GIR_EraseRootFromParent_Done, |
| 62057 | // Label 4212: @159001 |
| 62058 | GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(159049), // Rule ID 49245 // |
| 62059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 62060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62063 | // MIs[0] Operand 1 |
| 62064 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 62065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62066 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62067 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 62068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 62069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62070 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62071 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62074 | GIR_RootConstrainSelectedInstOperands, |
| 62075 | // GIR_Coverage, 49245, |
| 62076 | GIR_EraseRootFromParent_Done, |
| 62077 | // Label 4213: @159049 |
| 62078 | GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(159097), // Rule ID 49256 // |
| 62079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62080 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62081 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62083 | // MIs[0] Operand 1 |
| 62084 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62085 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62086 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62087 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 62088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 62089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62090 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62091 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62094 | GIR_RootConstrainSelectedInstOperands, |
| 62095 | // GIR_Coverage, 49256, |
| 62096 | GIR_EraseRootFromParent_Done, |
| 62097 | // Label 4214: @159097 |
| 62098 | GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(159145), // Rule ID 49257 // |
| 62099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62100 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62101 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62103 | // MIs[0] Operand 1 |
| 62104 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62106 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62107 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 62108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M1), |
| 62109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62110 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62111 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62114 | GIR_RootConstrainSelectedInstOperands, |
| 62115 | // GIR_Coverage, 49257, |
| 62116 | GIR_EraseRootFromParent_Done, |
| 62117 | // Label 4215: @159145 |
| 62118 | GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(159193), // Rule ID 49270 // |
| 62119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62120 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62121 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62123 | // MIs[0] Operand 1 |
| 62124 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62125 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62126 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62127 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 62128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 62129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62130 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62131 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62134 | GIR_RootConstrainSelectedInstOperands, |
| 62135 | // GIR_Coverage, 49270, |
| 62136 | GIR_EraseRootFromParent_Done, |
| 62137 | // Label 4216: @159193 |
| 62138 | GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(159241), // Rule ID 49271 // |
| 62139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62140 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62141 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62143 | // MIs[0] Operand 1 |
| 62144 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62146 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62147 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 62148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 62149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62150 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62151 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62154 | GIR_RootConstrainSelectedInstOperands, |
| 62155 | // GIR_Coverage, 49271, |
| 62156 | GIR_EraseRootFromParent_Done, |
| 62157 | // Label 4217: @159241 |
| 62158 | GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(159289), // Rule ID 49278 // |
| 62159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62163 | // MIs[0] Operand 1 |
| 62164 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62165 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62166 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62167 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 62169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62170 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62171 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62174 | GIR_RootConstrainSelectedInstOperands, |
| 62175 | // GIR_Coverage, 49278, |
| 62176 | GIR_EraseRootFromParent_Done, |
| 62177 | // Label 4218: @159289 |
| 62178 | GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(159337), // Rule ID 49279 // |
| 62179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62180 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62181 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62183 | // MIs[0] Operand 1 |
| 62184 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62185 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62186 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62187 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 62189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62190 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62191 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62194 | GIR_RootConstrainSelectedInstOperands, |
| 62195 | // GIR_Coverage, 49279, |
| 62196 | GIR_EraseRootFromParent_Done, |
| 62197 | // Label 4219: @159337 |
| 62198 | GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(159385), // Rule ID 49286 // |
| 62199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 62200 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62201 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62203 | // MIs[0] Operand 1 |
| 62204 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62205 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62206 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62207 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 62208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 62209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62210 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62211 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62214 | GIR_RootConstrainSelectedInstOperands, |
| 62215 | // GIR_Coverage, 49286, |
| 62216 | GIR_EraseRootFromParent_Done, |
| 62217 | // Label 4220: @159385 |
| 62218 | GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(159433), // Rule ID 49287 // |
| 62219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 62220 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62221 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62223 | // MIs[0] Operand 1 |
| 62224 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 62225 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62226 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62227 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 62228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 62229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62230 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62231 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62234 | GIR_RootConstrainSelectedInstOperands, |
| 62235 | // GIR_Coverage, 49287, |
| 62236 | GIR_EraseRootFromParent_Done, |
| 62237 | // Label 4221: @159433 |
| 62238 | GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(159481), // Rule ID 49300 // |
| 62239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62241 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62243 | // MIs[0] Operand 1 |
| 62244 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62245 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62246 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62247 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 62248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 62249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62250 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62251 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62254 | GIR_RootConstrainSelectedInstOperands, |
| 62255 | // GIR_Coverage, 49300, |
| 62256 | GIR_EraseRootFromParent_Done, |
| 62257 | // Label 4222: @159481 |
| 62258 | GIM_Try, /*On fail goto*//*Label 4223*/ GIMT_Encode4(159529), // Rule ID 49301 // |
| 62259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62261 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62263 | // MIs[0] Operand 1 |
| 62264 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62266 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62267 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 62268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 62269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62270 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62271 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62274 | GIR_RootConstrainSelectedInstOperands, |
| 62275 | // GIR_Coverage, 49301, |
| 62276 | GIR_EraseRootFromParent_Done, |
| 62277 | // Label 4223: @159529 |
| 62278 | GIM_Try, /*On fail goto*//*Label 4224*/ GIMT_Encode4(159577), // Rule ID 49314 // |
| 62279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62280 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62281 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62283 | // MIs[0] Operand 1 |
| 62284 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62286 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62287 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 62288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 62289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62290 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62291 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62294 | GIR_RootConstrainSelectedInstOperands, |
| 62295 | // GIR_Coverage, 49314, |
| 62296 | GIR_EraseRootFromParent_Done, |
| 62297 | // Label 4224: @159577 |
| 62298 | GIM_Try, /*On fail goto*//*Label 4225*/ GIMT_Encode4(159625), // Rule ID 49315 // |
| 62299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62300 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62301 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62303 | // MIs[0] Operand 1 |
| 62304 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62305 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62306 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62307 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 62308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 62309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62310 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62311 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62314 | GIR_RootConstrainSelectedInstOperands, |
| 62315 | // GIR_Coverage, 49315, |
| 62316 | GIR_EraseRootFromParent_Done, |
| 62317 | // Label 4225: @159625 |
| 62318 | GIM_Try, /*On fail goto*//*Label 4226*/ GIMT_Encode4(159673), // Rule ID 49322 // |
| 62319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62320 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62321 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62323 | // MIs[0] Operand 1 |
| 62324 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62325 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62326 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62327 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 62329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62330 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62331 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62334 | GIR_RootConstrainSelectedInstOperands, |
| 62335 | // GIR_Coverage, 49322, |
| 62336 | GIR_EraseRootFromParent_Done, |
| 62337 | // Label 4226: @159673 |
| 62338 | GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(159721), // Rule ID 49323 // |
| 62339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62340 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62341 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62343 | // MIs[0] Operand 1 |
| 62344 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62346 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62347 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 62349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62350 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62351 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62354 | GIR_RootConstrainSelectedInstOperands, |
| 62355 | // GIR_Coverage, 49323, |
| 62356 | GIR_EraseRootFromParent_Done, |
| 62357 | // Label 4227: @159721 |
| 62358 | GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(159769), // Rule ID 49330 // |
| 62359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 62360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62361 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62363 | // MIs[0] Operand 1 |
| 62364 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62365 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62366 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62367 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 62368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 62369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62371 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62374 | GIR_RootConstrainSelectedInstOperands, |
| 62375 | // GIR_Coverage, 49330, |
| 62376 | GIR_EraseRootFromParent_Done, |
| 62377 | // Label 4228: @159769 |
| 62378 | GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(159817), // Rule ID 49331 // |
| 62379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 62380 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62381 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62383 | // MIs[0] Operand 1 |
| 62384 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 62385 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62386 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62387 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 62388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 62389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62390 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62391 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62394 | GIR_RootConstrainSelectedInstOperands, |
| 62395 | // GIR_Coverage, 49331, |
| 62396 | GIR_EraseRootFromParent_Done, |
| 62397 | // Label 4229: @159817 |
| 62398 | GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(159865), // Rule ID 49344 // |
| 62399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62400 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62401 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62403 | // MIs[0] Operand 1 |
| 62404 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62405 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62406 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62407 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 62408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 62409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62410 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62411 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62414 | GIR_RootConstrainSelectedInstOperands, |
| 62415 | // GIR_Coverage, 49344, |
| 62416 | GIR_EraseRootFromParent_Done, |
| 62417 | // Label 4230: @159865 |
| 62418 | GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(159913), // Rule ID 49345 // |
| 62419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62421 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62423 | // MIs[0] Operand 1 |
| 62424 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62425 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62426 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62427 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 62428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M1), |
| 62429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62430 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62431 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62434 | GIR_RootConstrainSelectedInstOperands, |
| 62435 | // GIR_Coverage, 49345, |
| 62436 | GIR_EraseRootFromParent_Done, |
| 62437 | // Label 4231: @159913 |
| 62438 | GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(159961), // Rule ID 49358 // |
| 62439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62441 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62443 | // MIs[0] Operand 1 |
| 62444 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62445 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62446 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62447 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 62448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 62449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62450 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62451 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62454 | GIR_RootConstrainSelectedInstOperands, |
| 62455 | // GIR_Coverage, 49358, |
| 62456 | GIR_EraseRootFromParent_Done, |
| 62457 | // Label 4232: @159961 |
| 62458 | GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(160009), // Rule ID 49359 // |
| 62459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62463 | // MIs[0] Operand 1 |
| 62464 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62465 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62466 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62467 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 62468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 62469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62470 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62471 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62474 | GIR_RootConstrainSelectedInstOperands, |
| 62475 | // GIR_Coverage, 49359, |
| 62476 | GIR_EraseRootFromParent_Done, |
| 62477 | // Label 4233: @160009 |
| 62478 | GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(160057), // Rule ID 49366 // |
| 62479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62481 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62483 | // MIs[0] Operand 1 |
| 62484 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62485 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62486 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62487 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 62489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62490 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62491 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62494 | GIR_RootConstrainSelectedInstOperands, |
| 62495 | // GIR_Coverage, 49366, |
| 62496 | GIR_EraseRootFromParent_Done, |
| 62497 | // Label 4234: @160057 |
| 62498 | GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(160105), // Rule ID 49367 // |
| 62499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62500 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62501 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62503 | // MIs[0] Operand 1 |
| 62504 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62505 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62506 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62507 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 62509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62510 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62511 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62514 | GIR_RootConstrainSelectedInstOperands, |
| 62515 | // GIR_Coverage, 49367, |
| 62516 | GIR_EraseRootFromParent_Done, |
| 62517 | // Label 4235: @160105 |
| 62518 | GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(160153), // Rule ID 49374 // |
| 62519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 62520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62523 | // MIs[0] Operand 1 |
| 62524 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62525 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62526 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62527 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 62528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 62529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62530 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62531 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62534 | GIR_RootConstrainSelectedInstOperands, |
| 62535 | // GIR_Coverage, 49374, |
| 62536 | GIR_EraseRootFromParent_Done, |
| 62537 | // Label 4236: @160153 |
| 62538 | GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(160201), // Rule ID 49375 // |
| 62539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 62540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62541 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62543 | // MIs[0] Operand 1 |
| 62544 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 62545 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62546 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62547 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 62548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 62549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62550 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62551 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62554 | GIR_RootConstrainSelectedInstOperands, |
| 62555 | // GIR_Coverage, 49375, |
| 62556 | GIR_EraseRootFromParent_Done, |
| 62557 | // Label 4237: @160201 |
| 62558 | GIM_Try, /*On fail goto*//*Label 4238*/ GIMT_Encode4(160249), // Rule ID 49388 // |
| 62559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62561 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62563 | // MIs[0] Operand 1 |
| 62564 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62565 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62566 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62567 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 62568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 62569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62570 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62571 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62574 | GIR_RootConstrainSelectedInstOperands, |
| 62575 | // GIR_Coverage, 49388, |
| 62576 | GIR_EraseRootFromParent_Done, |
| 62577 | // Label 4238: @160249 |
| 62578 | GIM_Try, /*On fail goto*//*Label 4239*/ GIMT_Encode4(160297), // Rule ID 49389 // |
| 62579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62580 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62581 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62583 | // MIs[0] Operand 1 |
| 62584 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62586 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62587 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 62588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 62589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62590 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62591 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62594 | GIR_RootConstrainSelectedInstOperands, |
| 62595 | // GIR_Coverage, 49389, |
| 62596 | GIR_EraseRootFromParent_Done, |
| 62597 | // Label 4239: @160297 |
| 62598 | GIM_Try, /*On fail goto*//*Label 4240*/ GIMT_Encode4(160345), // Rule ID 49402 // |
| 62599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62600 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62601 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62603 | // MIs[0] Operand 1 |
| 62604 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62606 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62607 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 62608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 62609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62610 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62611 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62614 | GIR_RootConstrainSelectedInstOperands, |
| 62615 | // GIR_Coverage, 49402, |
| 62616 | GIR_EraseRootFromParent_Done, |
| 62617 | // Label 4240: @160345 |
| 62618 | GIM_Try, /*On fail goto*//*Label 4241*/ GIMT_Encode4(160393), // Rule ID 49403 // |
| 62619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62620 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62621 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62623 | // MIs[0] Operand 1 |
| 62624 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62625 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62626 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62627 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 62628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 62629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62630 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62631 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62634 | GIR_RootConstrainSelectedInstOperands, |
| 62635 | // GIR_Coverage, 49403, |
| 62636 | GIR_EraseRootFromParent_Done, |
| 62637 | // Label 4241: @160393 |
| 62638 | GIM_Try, /*On fail goto*//*Label 4242*/ GIMT_Encode4(160441), // Rule ID 49410 // |
| 62639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62641 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62643 | // MIs[0] Operand 1 |
| 62644 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62646 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62647 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 62649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62650 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62651 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62654 | GIR_RootConstrainSelectedInstOperands, |
| 62655 | // GIR_Coverage, 49410, |
| 62656 | GIR_EraseRootFromParent_Done, |
| 62657 | // Label 4242: @160441 |
| 62658 | GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(160489), // Rule ID 49411 // |
| 62659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62663 | // MIs[0] Operand 1 |
| 62664 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62665 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62666 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62667 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 62669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62670 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62671 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62674 | GIR_RootConstrainSelectedInstOperands, |
| 62675 | // GIR_Coverage, 49411, |
| 62676 | GIR_EraseRootFromParent_Done, |
| 62677 | // Label 4243: @160489 |
| 62678 | GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(160537), // Rule ID 49418 // |
| 62679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 62680 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62681 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62683 | // MIs[0] Operand 1 |
| 62684 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62685 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62686 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62687 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 62688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 62689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62690 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62691 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62694 | GIR_RootConstrainSelectedInstOperands, |
| 62695 | // GIR_Coverage, 49418, |
| 62696 | GIR_EraseRootFromParent_Done, |
| 62697 | // Label 4244: @160537 |
| 62698 | GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(160585), // Rule ID 49419 // |
| 62699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 62700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62701 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62703 | // MIs[0] Operand 1 |
| 62704 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 62705 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62706 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62707 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 62708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 62709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62710 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62711 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62714 | GIR_RootConstrainSelectedInstOperands, |
| 62715 | // GIR_Coverage, 49419, |
| 62716 | GIR_EraseRootFromParent_Done, |
| 62717 | // Label 4245: @160585 |
| 62718 | GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(160633), // Rule ID 49432 // |
| 62719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62720 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62721 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62723 | // MIs[0] Operand 1 |
| 62724 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62726 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62727 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 62728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 62729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62730 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62731 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62734 | GIR_RootConstrainSelectedInstOperands, |
| 62735 | // GIR_Coverage, 49432, |
| 62736 | GIR_EraseRootFromParent_Done, |
| 62737 | // Label 4246: @160633 |
| 62738 | GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(160681), // Rule ID 49433 // |
| 62739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62740 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62741 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62743 | // MIs[0] Operand 1 |
| 62744 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62746 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62747 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 62748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M1), |
| 62749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62750 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62751 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62754 | GIR_RootConstrainSelectedInstOperands, |
| 62755 | // GIR_Coverage, 49433, |
| 62756 | GIR_EraseRootFromParent_Done, |
| 62757 | // Label 4247: @160681 |
| 62758 | GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(160729), // Rule ID 49446 // |
| 62759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62761 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62763 | // MIs[0] Operand 1 |
| 62764 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62765 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62766 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62767 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 62768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 62769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62770 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62771 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62774 | GIR_RootConstrainSelectedInstOperands, |
| 62775 | // GIR_Coverage, 49446, |
| 62776 | GIR_EraseRootFromParent_Done, |
| 62777 | // Label 4248: @160729 |
| 62778 | GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(160777), // Rule ID 49447 // |
| 62779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62781 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62783 | // MIs[0] Operand 1 |
| 62784 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62785 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62786 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62787 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 62788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 62789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62790 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62791 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62794 | GIR_RootConstrainSelectedInstOperands, |
| 62795 | // GIR_Coverage, 49447, |
| 62796 | GIR_EraseRootFromParent_Done, |
| 62797 | // Label 4249: @160777 |
| 62798 | GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(160825), // Rule ID 49454 // |
| 62799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62803 | // MIs[0] Operand 1 |
| 62804 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62806 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62807 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 62809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62810 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62811 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62814 | GIR_RootConstrainSelectedInstOperands, |
| 62815 | // GIR_Coverage, 49454, |
| 62816 | GIR_EraseRootFromParent_Done, |
| 62817 | // Label 4250: @160825 |
| 62818 | GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(160873), // Rule ID 49455 // |
| 62819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62820 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62821 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62823 | // MIs[0] Operand 1 |
| 62824 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62826 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62827 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 62829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62830 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62831 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62834 | GIR_RootConstrainSelectedInstOperands, |
| 62835 | // GIR_Coverage, 49455, |
| 62836 | GIR_EraseRootFromParent_Done, |
| 62837 | // Label 4251: @160873 |
| 62838 | GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(160921), // Rule ID 49462 // |
| 62839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 62840 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62841 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62843 | // MIs[0] Operand 1 |
| 62844 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62845 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62846 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62847 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 62848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 62849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62850 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62851 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62854 | GIR_RootConstrainSelectedInstOperands, |
| 62855 | // GIR_Coverage, 49462, |
| 62856 | GIR_EraseRootFromParent_Done, |
| 62857 | // Label 4252: @160921 |
| 62858 | GIM_Try, /*On fail goto*//*Label 4253*/ GIMT_Encode4(160969), // Rule ID 49463 // |
| 62859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 62860 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 62861 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 62862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62863 | // MIs[0] Operand 1 |
| 62864 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 62865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62866 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 62867 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 62868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 62869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62870 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 62871 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 62872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 62874 | GIR_RootConstrainSelectedInstOperands, |
| 62875 | // GIR_Coverage, 49463, |
| 62876 | GIR_EraseRootFromParent_Done, |
| 62877 | // Label 4253: @160969 |
| 62878 | GIM_Try, /*On fail goto*//*Label 4254*/ GIMT_Encode4(161017), // Rule ID 49476 // |
| 62879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62883 | // MIs[0] Operand 1 |
| 62884 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 62885 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62886 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62887 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 62888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 62889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62890 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62891 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62894 | GIR_RootConstrainSelectedInstOperands, |
| 62895 | // GIR_Coverage, 49476, |
| 62896 | GIR_EraseRootFromParent_Done, |
| 62897 | // Label 4254: @161017 |
| 62898 | GIM_Try, /*On fail goto*//*Label 4255*/ GIMT_Encode4(161065), // Rule ID 49477 // |
| 62899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62900 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 62901 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 62902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62903 | // MIs[0] Operand 1 |
| 62904 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 62905 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62906 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62907 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 62908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 62909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62910 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62911 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 62914 | GIR_RootConstrainSelectedInstOperands, |
| 62915 | // GIR_Coverage, 49477, |
| 62916 | GIR_EraseRootFromParent_Done, |
| 62917 | // Label 4255: @161065 |
| 62918 | GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(161113), // Rule ID 49490 // |
| 62919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62921 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62923 | // MIs[0] Operand 1 |
| 62924 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 62925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62926 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62927 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 62928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 62929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62930 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62931 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62934 | GIR_RootConstrainSelectedInstOperands, |
| 62935 | // GIR_Coverage, 49490, |
| 62936 | GIR_EraseRootFromParent_Done, |
| 62937 | // Label 4256: @161113 |
| 62938 | GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(161161), // Rule ID 49491 // |
| 62939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 62941 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 62942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62943 | // MIs[0] Operand 1 |
| 62944 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 62945 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62946 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 62947 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 62948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 62949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62950 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62951 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 62954 | GIR_RootConstrainSelectedInstOperands, |
| 62955 | // GIR_Coverage, 49491, |
| 62956 | GIR_EraseRootFromParent_Done, |
| 62957 | // Label 4257: @161161 |
| 62958 | GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(161209), // Rule ID 49498 // |
| 62959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 62960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62963 | // MIs[0] Operand 1 |
| 62964 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 62965 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62966 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62967 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 62968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 62969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62970 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62971 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62974 | GIR_RootConstrainSelectedInstOperands, |
| 62975 | // GIR_Coverage, 49498, |
| 62976 | GIR_EraseRootFromParent_Done, |
| 62977 | // Label 4258: @161209 |
| 62978 | GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(161257), // Rule ID 49499 // |
| 62979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 62980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 62981 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 62982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 62983 | // MIs[0] Operand 1 |
| 62984 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 62985 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62986 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 62987 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 62988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 62989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 62990 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 62991 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 62992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 62993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 62994 | GIR_RootConstrainSelectedInstOperands, |
| 62995 | // GIR_Coverage, 49499, |
| 62996 | GIR_EraseRootFromParent_Done, |
| 62997 | // Label 4259: @161257 |
| 62998 | GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(161305), // Rule ID 49506 // |
| 62999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 63000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 63001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 63002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63003 | // MIs[0] Operand 1 |
| 63004 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 63005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63006 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63007 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 63008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 63009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63010 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63011 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 63014 | GIR_RootConstrainSelectedInstOperands, |
| 63015 | // GIR_Coverage, 49506, |
| 63016 | GIR_EraseRootFromParent_Done, |
| 63017 | // Label 4260: @161305 |
| 63018 | GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(161353), // Rule ID 49507 // |
| 63019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 63020 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 63021 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 63022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63023 | // MIs[0] Operand 1 |
| 63024 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 63025 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63026 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63027 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 63028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 63029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63030 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63031 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 63034 | GIR_RootConstrainSelectedInstOperands, |
| 63035 | // GIR_Coverage, 49507, |
| 63036 | GIR_EraseRootFromParent_Done, |
| 63037 | // Label 4261: @161353 |
| 63038 | GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(161401), // Rule ID 49520 // |
| 63039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 63041 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 63042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63043 | // MIs[0] Operand 1 |
| 63044 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63045 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63046 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63047 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 63049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63050 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63051 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63054 | GIR_RootConstrainSelectedInstOperands, |
| 63055 | // GIR_Coverage, 49520, |
| 63056 | GIR_EraseRootFromParent_Done, |
| 63057 | // Label 4262: @161401 |
| 63058 | GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(161449), // Rule ID 49521 // |
| 63059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 63061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 63062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63063 | // MIs[0] Operand 1 |
| 63064 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63066 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63067 | // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M1), |
| 63069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63070 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63071 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63074 | GIR_RootConstrainSelectedInstOperands, |
| 63075 | // GIR_Coverage, 49521, |
| 63076 | GIR_EraseRootFromParent_Done, |
| 63077 | // Label 4263: @161449 |
| 63078 | GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(161497), // Rule ID 49534 // |
| 63079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63080 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 63081 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 63082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63083 | // MIs[0] Operand 1 |
| 63084 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63085 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63086 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63087 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 63089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63090 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63091 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63094 | GIR_RootConstrainSelectedInstOperands, |
| 63095 | // GIR_Coverage, 49534, |
| 63096 | GIR_EraseRootFromParent_Done, |
| 63097 | // Label 4264: @161497 |
| 63098 | GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(161545), // Rule ID 49535 // |
| 63099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63100 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 63101 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 63102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63103 | // MIs[0] Operand 1 |
| 63104 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63106 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63107 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 63109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63110 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63111 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63114 | GIR_RootConstrainSelectedInstOperands, |
| 63115 | // GIR_Coverage, 49535, |
| 63116 | GIR_EraseRootFromParent_Done, |
| 63117 | // Label 4265: @161545 |
| 63118 | GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(161593), // Rule ID 49542 // |
| 63119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63120 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 63121 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 63122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63123 | // MIs[0] Operand 1 |
| 63124 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63125 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63126 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63127 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 63129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63130 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63131 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63134 | GIR_RootConstrainSelectedInstOperands, |
| 63135 | // GIR_Coverage, 49542, |
| 63136 | GIR_EraseRootFromParent_Done, |
| 63137 | // Label 4266: @161593 |
| 63138 | GIM_Try, /*On fail goto*//*Label 4267*/ GIMT_Encode4(161641), // Rule ID 49543 // |
| 63139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63140 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 63141 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 63142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63143 | // MIs[0] Operand 1 |
| 63144 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63146 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63147 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 63149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63150 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63151 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63154 | GIR_RootConstrainSelectedInstOperands, |
| 63155 | // GIR_Coverage, 49543, |
| 63156 | GIR_EraseRootFromParent_Done, |
| 63157 | // Label 4267: @161641 |
| 63158 | GIM_Try, /*On fail goto*//*Label 4268*/ GIMT_Encode4(161689), // Rule ID 49550 // |
| 63159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 63160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 63161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 63162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63163 | // MIs[0] Operand 1 |
| 63164 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63165 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63166 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63167 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 63168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 63169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63170 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63171 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 63174 | GIR_RootConstrainSelectedInstOperands, |
| 63175 | // GIR_Coverage, 49550, |
| 63176 | GIR_EraseRootFromParent_Done, |
| 63177 | // Label 4268: @161689 |
| 63178 | GIM_Try, /*On fail goto*//*Label 4269*/ GIMT_Encode4(161737), // Rule ID 49551 // |
| 63179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 63180 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 63181 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 63182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63183 | // MIs[0] Operand 1 |
| 63184 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 63185 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63186 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63187 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 63188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 63189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63190 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63191 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 63194 | GIR_RootConstrainSelectedInstOperands, |
| 63195 | // GIR_Coverage, 49551, |
| 63196 | GIR_EraseRootFromParent_Done, |
| 63197 | // Label 4269: @161737 |
| 63198 | GIM_Reject, |
| 63199 | // Label 3852: @161738 |
| 63200 | GIM_Try, /*On fail goto*//*Label 4270*/ GIMT_Encode4(161786), // Rule ID 49134 // |
| 63201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63203 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63205 | // MIs[0] Operand 1 |
| 63206 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 63207 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63208 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63209 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 63211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63212 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63213 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63216 | GIR_RootConstrainSelectedInstOperands, |
| 63217 | // GIR_Coverage, 49134, |
| 63218 | GIR_EraseRootFromParent_Done, |
| 63219 | // Label 4270: @161786 |
| 63220 | GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(161834), // Rule ID 49135 // |
| 63221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63222 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63223 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63225 | // MIs[0] Operand 1 |
| 63226 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 63227 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63228 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63229 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M2), |
| 63231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63232 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63233 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63236 | GIR_RootConstrainSelectedInstOperands, |
| 63237 | // GIR_Coverage, 49135, |
| 63238 | GIR_EraseRootFromParent_Done, |
| 63239 | // Label 4271: @161834 |
| 63240 | GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(161882), // Rule ID 49142 // |
| 63241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63242 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63243 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63245 | // MIs[0] Operand 1 |
| 63246 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 63247 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63248 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63249 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 63251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63252 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63253 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63256 | GIR_RootConstrainSelectedInstOperands, |
| 63257 | // GIR_Coverage, 49142, |
| 63258 | GIR_EraseRootFromParent_Done, |
| 63259 | // Label 4272: @161882 |
| 63260 | GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(161930), // Rule ID 49143 // |
| 63261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63263 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63265 | // MIs[0] Operand 1 |
| 63266 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 63267 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63268 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63269 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 63271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63272 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63273 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63276 | GIR_RootConstrainSelectedInstOperands, |
| 63277 | // GIR_Coverage, 49143, |
| 63278 | GIR_EraseRootFromParent_Done, |
| 63279 | // Label 4273: @161930 |
| 63280 | GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(161978), // Rule ID 49150 // |
| 63281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63282 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63283 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63285 | // MIs[0] Operand 1 |
| 63286 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 63287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63288 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63289 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 63291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63292 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63293 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63296 | GIR_RootConstrainSelectedInstOperands, |
| 63297 | // GIR_Coverage, 49150, |
| 63298 | GIR_EraseRootFromParent_Done, |
| 63299 | // Label 4274: @161978 |
| 63300 | GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(162026), // Rule ID 49151 // |
| 63301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63303 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63305 | // MIs[0] Operand 1 |
| 63306 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 63307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63308 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63309 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 63311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63312 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63313 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63316 | GIR_RootConstrainSelectedInstOperands, |
| 63317 | // GIR_Coverage, 49151, |
| 63318 | GIR_EraseRootFromParent_Done, |
| 63319 | // Label 4275: @162026 |
| 63320 | GIM_Try, /*On fail goto*//*Label 4276*/ GIMT_Encode4(162074), // Rule ID 49178 // |
| 63321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63322 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63323 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63325 | // MIs[0] Operand 1 |
| 63326 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 63327 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63328 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63329 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 63331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63332 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63333 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63336 | GIR_RootConstrainSelectedInstOperands, |
| 63337 | // GIR_Coverage, 49178, |
| 63338 | GIR_EraseRootFromParent_Done, |
| 63339 | // Label 4276: @162074 |
| 63340 | GIM_Try, /*On fail goto*//*Label 4277*/ GIMT_Encode4(162122), // Rule ID 49179 // |
| 63341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63343 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63345 | // MIs[0] Operand 1 |
| 63346 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 63347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63348 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63349 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M2), |
| 63351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63352 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63353 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63356 | GIR_RootConstrainSelectedInstOperands, |
| 63357 | // GIR_Coverage, 49179, |
| 63358 | GIR_EraseRootFromParent_Done, |
| 63359 | // Label 4277: @162122 |
| 63360 | GIM_Try, /*On fail goto*//*Label 4278*/ GIMT_Encode4(162170), // Rule ID 49186 // |
| 63361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63362 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63363 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63365 | // MIs[0] Operand 1 |
| 63366 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 63367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63368 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63369 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 63371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63372 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63373 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63376 | GIR_RootConstrainSelectedInstOperands, |
| 63377 | // GIR_Coverage, 49186, |
| 63378 | GIR_EraseRootFromParent_Done, |
| 63379 | // Label 4278: @162170 |
| 63380 | GIM_Try, /*On fail goto*//*Label 4279*/ GIMT_Encode4(162218), // Rule ID 49187 // |
| 63381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63382 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63383 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63385 | // MIs[0] Operand 1 |
| 63386 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 63387 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63388 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63389 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 63391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63392 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63393 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63396 | GIR_RootConstrainSelectedInstOperands, |
| 63397 | // GIR_Coverage, 49187, |
| 63398 | GIR_EraseRootFromParent_Done, |
| 63399 | // Label 4279: @162218 |
| 63400 | GIM_Try, /*On fail goto*//*Label 4280*/ GIMT_Encode4(162266), // Rule ID 49194 // |
| 63401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63402 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63403 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63405 | // MIs[0] Operand 1 |
| 63406 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 63407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63408 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63409 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 63411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63412 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63413 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63416 | GIR_RootConstrainSelectedInstOperands, |
| 63417 | // GIR_Coverage, 49194, |
| 63418 | GIR_EraseRootFromParent_Done, |
| 63419 | // Label 4280: @162266 |
| 63420 | GIM_Try, /*On fail goto*//*Label 4281*/ GIMT_Encode4(162314), // Rule ID 49195 // |
| 63421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63422 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63423 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63425 | // MIs[0] Operand 1 |
| 63426 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 63427 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63428 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63429 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 63431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63432 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63433 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63436 | GIR_RootConstrainSelectedInstOperands, |
| 63437 | // GIR_Coverage, 49195, |
| 63438 | GIR_EraseRootFromParent_Done, |
| 63439 | // Label 4281: @162314 |
| 63440 | GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(162362), // Rule ID 49222 // |
| 63441 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63442 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63443 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63445 | // MIs[0] Operand 1 |
| 63446 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 63447 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63448 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63449 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 63451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63452 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63453 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63456 | GIR_RootConstrainSelectedInstOperands, |
| 63457 | // GIR_Coverage, 49222, |
| 63458 | GIR_EraseRootFromParent_Done, |
| 63459 | // Label 4282: @162362 |
| 63460 | GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(162410), // Rule ID 49223 // |
| 63461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63462 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63463 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63465 | // MIs[0] Operand 1 |
| 63466 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 63467 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63468 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63469 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 63471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63472 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63473 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63476 | GIR_RootConstrainSelectedInstOperands, |
| 63477 | // GIR_Coverage, 49223, |
| 63478 | GIR_EraseRootFromParent_Done, |
| 63479 | // Label 4283: @162410 |
| 63480 | GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(162458), // Rule ID 49230 // |
| 63481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63482 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63483 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63485 | // MIs[0] Operand 1 |
| 63486 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 63487 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63488 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63489 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 63491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63492 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63493 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63496 | GIR_RootConstrainSelectedInstOperands, |
| 63497 | // GIR_Coverage, 49230, |
| 63498 | GIR_EraseRootFromParent_Done, |
| 63499 | // Label 4284: @162458 |
| 63500 | GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(162506), // Rule ID 49231 // |
| 63501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63502 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63503 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63505 | // MIs[0] Operand 1 |
| 63506 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 63507 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63508 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63509 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 63511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63512 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63513 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63516 | GIR_RootConstrainSelectedInstOperands, |
| 63517 | // GIR_Coverage, 49231, |
| 63518 | GIR_EraseRootFromParent_Done, |
| 63519 | // Label 4285: @162506 |
| 63520 | GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(162554), // Rule ID 49238 // |
| 63521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63522 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63523 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63525 | // MIs[0] Operand 1 |
| 63526 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 63527 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63528 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63529 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 63531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63532 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63533 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63536 | GIR_RootConstrainSelectedInstOperands, |
| 63537 | // GIR_Coverage, 49238, |
| 63538 | GIR_EraseRootFromParent_Done, |
| 63539 | // Label 4286: @162554 |
| 63540 | GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(162602), // Rule ID 49239 // |
| 63541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63542 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63543 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63545 | // MIs[0] Operand 1 |
| 63546 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 63547 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63548 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63549 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 63551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63552 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63553 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63556 | GIR_RootConstrainSelectedInstOperands, |
| 63557 | // GIR_Coverage, 49239, |
| 63558 | GIR_EraseRootFromParent_Done, |
| 63559 | // Label 4287: @162602 |
| 63560 | GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(162650), // Rule ID 49264 // |
| 63561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63562 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63563 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63565 | // MIs[0] Operand 1 |
| 63566 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 63567 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63568 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63569 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 63571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63572 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63573 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63576 | GIR_RootConstrainSelectedInstOperands, |
| 63577 | // GIR_Coverage, 49264, |
| 63578 | GIR_EraseRootFromParent_Done, |
| 63579 | // Label 4288: @162650 |
| 63580 | GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(162698), // Rule ID 49265 // |
| 63581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63582 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63583 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63585 | // MIs[0] Operand 1 |
| 63586 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 63587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63588 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63589 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M2), |
| 63591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63592 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63593 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63596 | GIR_RootConstrainSelectedInstOperands, |
| 63597 | // GIR_Coverage, 49265, |
| 63598 | GIR_EraseRootFromParent_Done, |
| 63599 | // Label 4289: @162698 |
| 63600 | GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(162746), // Rule ID 49272 // |
| 63601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63602 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63603 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63605 | // MIs[0] Operand 1 |
| 63606 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 63607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63608 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63609 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 63611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63612 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63613 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63616 | GIR_RootConstrainSelectedInstOperands, |
| 63617 | // GIR_Coverage, 49272, |
| 63618 | GIR_EraseRootFromParent_Done, |
| 63619 | // Label 4290: @162746 |
| 63620 | GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(162794), // Rule ID 49273 // |
| 63621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63622 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63623 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63625 | // MIs[0] Operand 1 |
| 63626 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 63627 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63628 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63629 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 63631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63632 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63633 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63636 | GIR_RootConstrainSelectedInstOperands, |
| 63637 | // GIR_Coverage, 49273, |
| 63638 | GIR_EraseRootFromParent_Done, |
| 63639 | // Label 4291: @162794 |
| 63640 | GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(162842), // Rule ID 49280 // |
| 63641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63642 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63643 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63645 | // MIs[0] Operand 1 |
| 63646 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 63647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63648 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63649 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 63651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63652 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63653 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63656 | GIR_RootConstrainSelectedInstOperands, |
| 63657 | // GIR_Coverage, 49280, |
| 63658 | GIR_EraseRootFromParent_Done, |
| 63659 | // Label 4292: @162842 |
| 63660 | GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(162890), // Rule ID 49281 // |
| 63661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63662 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63663 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63665 | // MIs[0] Operand 1 |
| 63666 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 63667 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63668 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63669 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 63671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63672 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63673 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63676 | GIR_RootConstrainSelectedInstOperands, |
| 63677 | // GIR_Coverage, 49281, |
| 63678 | GIR_EraseRootFromParent_Done, |
| 63679 | // Label 4293: @162890 |
| 63680 | GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(162938), // Rule ID 49308 // |
| 63681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63682 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63683 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63685 | // MIs[0] Operand 1 |
| 63686 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 63687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63688 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63689 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 63691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63692 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63693 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63696 | GIR_RootConstrainSelectedInstOperands, |
| 63697 | // GIR_Coverage, 49308, |
| 63698 | GIR_EraseRootFromParent_Done, |
| 63699 | // Label 4294: @162938 |
| 63700 | GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(162986), // Rule ID 49309 // |
| 63701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63702 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63703 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63705 | // MIs[0] Operand 1 |
| 63706 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 63707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63708 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63709 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 63711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63712 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63713 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63716 | GIR_RootConstrainSelectedInstOperands, |
| 63717 | // GIR_Coverage, 49309, |
| 63718 | GIR_EraseRootFromParent_Done, |
| 63719 | // Label 4295: @162986 |
| 63720 | GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(163034), // Rule ID 49316 // |
| 63721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63722 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63723 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63725 | // MIs[0] Operand 1 |
| 63726 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 63727 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63728 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63729 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 63731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63732 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63733 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63736 | GIR_RootConstrainSelectedInstOperands, |
| 63737 | // GIR_Coverage, 49316, |
| 63738 | GIR_EraseRootFromParent_Done, |
| 63739 | // Label 4296: @163034 |
| 63740 | GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(163082), // Rule ID 49317 // |
| 63741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63743 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63745 | // MIs[0] Operand 1 |
| 63746 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 63747 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63748 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63749 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 63751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63752 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63753 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63756 | GIR_RootConstrainSelectedInstOperands, |
| 63757 | // GIR_Coverage, 49317, |
| 63758 | GIR_EraseRootFromParent_Done, |
| 63759 | // Label 4297: @163082 |
| 63760 | GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(163130), // Rule ID 49324 // |
| 63761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63762 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63763 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63765 | // MIs[0] Operand 1 |
| 63766 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 63767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63768 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63769 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 63771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63772 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63773 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63776 | GIR_RootConstrainSelectedInstOperands, |
| 63777 | // GIR_Coverage, 49324, |
| 63778 | GIR_EraseRootFromParent_Done, |
| 63779 | // Label 4298: @163130 |
| 63780 | GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(163178), // Rule ID 49325 // |
| 63781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63783 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63785 | // MIs[0] Operand 1 |
| 63786 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 63787 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63788 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63789 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 63791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63792 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63793 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63796 | GIR_RootConstrainSelectedInstOperands, |
| 63797 | // GIR_Coverage, 49325, |
| 63798 | GIR_EraseRootFromParent_Done, |
| 63799 | // Label 4299: @163178 |
| 63800 | GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(163226), // Rule ID 49352 // |
| 63801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63802 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63803 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63805 | // MIs[0] Operand 1 |
| 63806 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 63807 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63808 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63809 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 63811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63812 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63813 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63816 | GIR_RootConstrainSelectedInstOperands, |
| 63817 | // GIR_Coverage, 49352, |
| 63818 | GIR_EraseRootFromParent_Done, |
| 63819 | // Label 4300: @163226 |
| 63820 | GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(163274), // Rule ID 49353 // |
| 63821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63822 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63823 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63825 | // MIs[0] Operand 1 |
| 63826 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 63827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63828 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63829 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M2), |
| 63831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63832 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63833 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63836 | GIR_RootConstrainSelectedInstOperands, |
| 63837 | // GIR_Coverage, 49353, |
| 63838 | GIR_EraseRootFromParent_Done, |
| 63839 | // Label 4301: @163274 |
| 63840 | GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(163322), // Rule ID 49360 // |
| 63841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63842 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63843 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63845 | // MIs[0] Operand 1 |
| 63846 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 63847 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63848 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63849 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 63851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63852 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63853 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63856 | GIR_RootConstrainSelectedInstOperands, |
| 63857 | // GIR_Coverage, 49360, |
| 63858 | GIR_EraseRootFromParent_Done, |
| 63859 | // Label 4302: @163322 |
| 63860 | GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(163370), // Rule ID 49361 // |
| 63861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63862 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63863 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63865 | // MIs[0] Operand 1 |
| 63866 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 63867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63868 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63869 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 63871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63872 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63873 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63876 | GIR_RootConstrainSelectedInstOperands, |
| 63877 | // GIR_Coverage, 49361, |
| 63878 | GIR_EraseRootFromParent_Done, |
| 63879 | // Label 4303: @163370 |
| 63880 | GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(163418), // Rule ID 49368 // |
| 63881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63882 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63883 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63885 | // MIs[0] Operand 1 |
| 63886 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 63887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63888 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63889 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 63890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 63891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63892 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63893 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63896 | GIR_RootConstrainSelectedInstOperands, |
| 63897 | // GIR_Coverage, 49368, |
| 63898 | GIR_EraseRootFromParent_Done, |
| 63899 | // Label 4304: @163418 |
| 63900 | GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(163466), // Rule ID 49369 // |
| 63901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63902 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 63903 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 63904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63905 | // MIs[0] Operand 1 |
| 63906 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 63907 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63908 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 63909 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 63910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 63911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63912 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 63913 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 63914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 63916 | GIR_RootConstrainSelectedInstOperands, |
| 63917 | // GIR_Coverage, 49369, |
| 63918 | GIR_EraseRootFromParent_Done, |
| 63919 | // Label 4305: @163466 |
| 63920 | GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(163514), // Rule ID 49396 // |
| 63921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63923 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63925 | // MIs[0] Operand 1 |
| 63926 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 63927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63928 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63929 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 63930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 63931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63932 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63933 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63936 | GIR_RootConstrainSelectedInstOperands, |
| 63937 | // GIR_Coverage, 49396, |
| 63938 | GIR_EraseRootFromParent_Done, |
| 63939 | // Label 4306: @163514 |
| 63940 | GIM_Try, /*On fail goto*//*Label 4307*/ GIMT_Encode4(163562), // Rule ID 49397 // |
| 63941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63942 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 63943 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 63944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63945 | // MIs[0] Operand 1 |
| 63946 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 63947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63948 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 63949 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 63950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 63951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63952 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63953 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 63956 | GIR_RootConstrainSelectedInstOperands, |
| 63957 | // GIR_Coverage, 49397, |
| 63958 | GIR_EraseRootFromParent_Done, |
| 63959 | // Label 4307: @163562 |
| 63960 | GIM_Try, /*On fail goto*//*Label 4308*/ GIMT_Encode4(163610), // Rule ID 49404 // |
| 63961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 63962 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63963 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63965 | // MIs[0] Operand 1 |
| 63966 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 63967 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63968 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63969 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 63970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 63971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63972 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63973 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63976 | GIR_RootConstrainSelectedInstOperands, |
| 63977 | // GIR_Coverage, 49404, |
| 63978 | GIR_EraseRootFromParent_Done, |
| 63979 | // Label 4308: @163610 |
| 63980 | GIM_Try, /*On fail goto*//*Label 4309*/ GIMT_Encode4(163658), // Rule ID 49405 // |
| 63981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 63982 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 63983 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 63984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 63985 | // MIs[0] Operand 1 |
| 63986 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 63987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63988 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 63989 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 63990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 63991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 63992 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 63993 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 63994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 63995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 63996 | GIR_RootConstrainSelectedInstOperands, |
| 63997 | // GIR_Coverage, 49405, |
| 63998 | GIR_EraseRootFromParent_Done, |
| 63999 | // Label 4309: @163658 |
| 64000 | GIM_Try, /*On fail goto*//*Label 4310*/ GIMT_Encode4(163706), // Rule ID 49412 // |
| 64001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64002 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64003 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64005 | // MIs[0] Operand 1 |
| 64006 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 64007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64008 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64009 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 64010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 64011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64012 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64013 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64016 | GIR_RootConstrainSelectedInstOperands, |
| 64017 | // GIR_Coverage, 49412, |
| 64018 | GIR_EraseRootFromParent_Done, |
| 64019 | // Label 4310: @163706 |
| 64020 | GIM_Try, /*On fail goto*//*Label 4311*/ GIMT_Encode4(163754), // Rule ID 49413 // |
| 64021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64022 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64023 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64025 | // MIs[0] Operand 1 |
| 64026 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 64027 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64028 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64029 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 64030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 64031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64032 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64033 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64036 | GIR_RootConstrainSelectedInstOperands, |
| 64037 | // GIR_Coverage, 49413, |
| 64038 | GIR_EraseRootFromParent_Done, |
| 64039 | // Label 4311: @163754 |
| 64040 | GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(163802), // Rule ID 49440 // |
| 64041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64042 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 64043 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 64044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64045 | // MIs[0] Operand 1 |
| 64046 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64047 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64048 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64049 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 64051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64052 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64053 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64056 | GIR_RootConstrainSelectedInstOperands, |
| 64057 | // GIR_Coverage, 49440, |
| 64058 | GIR_EraseRootFromParent_Done, |
| 64059 | // Label 4312: @163802 |
| 64060 | GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(163850), // Rule ID 49441 // |
| 64061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64062 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 64063 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 64064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64065 | // MIs[0] Operand 1 |
| 64066 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64067 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64068 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64069 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M2), |
| 64071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64072 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64073 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64076 | GIR_RootConstrainSelectedInstOperands, |
| 64077 | // GIR_Coverage, 49441, |
| 64078 | GIR_EraseRootFromParent_Done, |
| 64079 | // Label 4313: @163850 |
| 64080 | GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(163898), // Rule ID 49448 // |
| 64081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64082 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 64083 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 64084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64085 | // MIs[0] Operand 1 |
| 64086 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64087 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64088 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64089 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 64091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64092 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64093 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64096 | GIR_RootConstrainSelectedInstOperands, |
| 64097 | // GIR_Coverage, 49448, |
| 64098 | GIR_EraseRootFromParent_Done, |
| 64099 | // Label 4314: @163898 |
| 64100 | GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(163946), // Rule ID 49449 // |
| 64101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64102 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 64103 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 64104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64105 | // MIs[0] Operand 1 |
| 64106 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64107 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64108 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64109 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 64111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64112 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64113 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64116 | GIR_RootConstrainSelectedInstOperands, |
| 64117 | // GIR_Coverage, 49449, |
| 64118 | GIR_EraseRootFromParent_Done, |
| 64119 | // Label 4315: @163946 |
| 64120 | GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(163994), // Rule ID 49456 // |
| 64121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64122 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64123 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64125 | // MIs[0] Operand 1 |
| 64126 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64127 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64128 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64129 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 64130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 64131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64132 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64133 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64136 | GIR_RootConstrainSelectedInstOperands, |
| 64137 | // GIR_Coverage, 49456, |
| 64138 | GIR_EraseRootFromParent_Done, |
| 64139 | // Label 4316: @163994 |
| 64140 | GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(164042), // Rule ID 49457 // |
| 64141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64142 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64143 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64145 | // MIs[0] Operand 1 |
| 64146 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64147 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64148 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64149 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 64150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 64151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64152 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64153 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64156 | GIR_RootConstrainSelectedInstOperands, |
| 64157 | // GIR_Coverage, 49457, |
| 64158 | GIR_EraseRootFromParent_Done, |
| 64159 | // Label 4317: @164042 |
| 64160 | GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(164090), // Rule ID 49484 // |
| 64161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64162 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 64163 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 64164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64165 | // MIs[0] Operand 1 |
| 64166 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 64167 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64168 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64169 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 64171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64172 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64173 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64176 | GIR_RootConstrainSelectedInstOperands, |
| 64177 | // GIR_Coverage, 49484, |
| 64178 | GIR_EraseRootFromParent_Done, |
| 64179 | // Label 4318: @164090 |
| 64180 | GIM_Try, /*On fail goto*//*Label 4319*/ GIMT_Encode4(164138), // Rule ID 49485 // |
| 64181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64182 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 64183 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 64184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64185 | // MIs[0] Operand 1 |
| 64186 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 64187 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64188 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64189 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 64191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64192 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64193 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64196 | GIR_RootConstrainSelectedInstOperands, |
| 64197 | // GIR_Coverage, 49485, |
| 64198 | GIR_EraseRootFromParent_Done, |
| 64199 | // Label 4319: @164138 |
| 64200 | GIM_Try, /*On fail goto*//*Label 4320*/ GIMT_Encode4(164186), // Rule ID 49492 // |
| 64201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 64203 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 64204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64205 | // MIs[0] Operand 1 |
| 64206 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 64207 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64208 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64209 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 64211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64212 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64213 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64216 | GIR_RootConstrainSelectedInstOperands, |
| 64217 | // GIR_Coverage, 49492, |
| 64218 | GIR_EraseRootFromParent_Done, |
| 64219 | // Label 4320: @164186 |
| 64220 | GIM_Try, /*On fail goto*//*Label 4321*/ GIMT_Encode4(164234), // Rule ID 49493 // |
| 64221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64222 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 64223 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 64224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64225 | // MIs[0] Operand 1 |
| 64226 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 64227 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64228 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64229 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 64231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64232 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64233 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64236 | GIR_RootConstrainSelectedInstOperands, |
| 64237 | // GIR_Coverage, 49493, |
| 64238 | GIR_EraseRootFromParent_Done, |
| 64239 | // Label 4321: @164234 |
| 64240 | GIM_Try, /*On fail goto*//*Label 4322*/ GIMT_Encode4(164282), // Rule ID 49500 // |
| 64241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64242 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64243 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64245 | // MIs[0] Operand 1 |
| 64246 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 64247 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64248 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64249 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 64250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 64251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64252 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64253 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64256 | GIR_RootConstrainSelectedInstOperands, |
| 64257 | // GIR_Coverage, 49500, |
| 64258 | GIR_EraseRootFromParent_Done, |
| 64259 | // Label 4322: @164282 |
| 64260 | GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(164330), // Rule ID 49501 // |
| 64261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64263 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64265 | // MIs[0] Operand 1 |
| 64266 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 64267 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64268 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64269 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 64270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 64271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64272 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64273 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64276 | GIR_RootConstrainSelectedInstOperands, |
| 64277 | // GIR_Coverage, 49501, |
| 64278 | GIR_EraseRootFromParent_Done, |
| 64279 | // Label 4323: @164330 |
| 64280 | GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(164378), // Rule ID 49528 // |
| 64281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64282 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 64283 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 64284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64285 | // MIs[0] Operand 1 |
| 64286 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 64287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64288 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64289 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 64291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64292 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64293 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64296 | GIR_RootConstrainSelectedInstOperands, |
| 64297 | // GIR_Coverage, 49528, |
| 64298 | GIR_EraseRootFromParent_Done, |
| 64299 | // Label 4324: @164378 |
| 64300 | GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(164426), // Rule ID 49529 // |
| 64301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 64303 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 64304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64305 | // MIs[0] Operand 1 |
| 64306 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 64307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64308 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 64309 | // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M2), |
| 64311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64312 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64313 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64316 | GIR_RootConstrainSelectedInstOperands, |
| 64317 | // GIR_Coverage, 49529, |
| 64318 | GIR_EraseRootFromParent_Done, |
| 64319 | // Label 4325: @164426 |
| 64320 | GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(164474), // Rule ID 49536 // |
| 64321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64322 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 64323 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 64324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64325 | // MIs[0] Operand 1 |
| 64326 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 64327 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64328 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64329 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 64331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64332 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64333 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64336 | GIR_RootConstrainSelectedInstOperands, |
| 64337 | // GIR_Coverage, 49536, |
| 64338 | GIR_EraseRootFromParent_Done, |
| 64339 | // Label 4326: @164474 |
| 64340 | GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(164522), // Rule ID 49537 // |
| 64341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 64343 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 64344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64345 | // MIs[0] Operand 1 |
| 64346 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 64347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64348 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64349 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 64351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64352 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64353 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64356 | GIR_RootConstrainSelectedInstOperands, |
| 64357 | // GIR_Coverage, 49537, |
| 64358 | GIR_EraseRootFromParent_Done, |
| 64359 | // Label 4327: @164522 |
| 64360 | GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(164570), // Rule ID 49544 // |
| 64361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64362 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64363 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64365 | // MIs[0] Operand 1 |
| 64366 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 64367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64368 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64369 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 64370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 64371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64372 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64373 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64376 | GIR_RootConstrainSelectedInstOperands, |
| 64377 | // GIR_Coverage, 49544, |
| 64378 | GIR_EraseRootFromParent_Done, |
| 64379 | // Label 4328: @164570 |
| 64380 | GIM_Try, /*On fail goto*//*Label 4329*/ GIMT_Encode4(164618), // Rule ID 49545 // |
| 64381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64382 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 64383 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 64384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64385 | // MIs[0] Operand 1 |
| 64386 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 64387 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64388 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64389 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 64390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 64391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64392 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64393 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 64396 | GIR_RootConstrainSelectedInstOperands, |
| 64397 | // GIR_Coverage, 49545, |
| 64398 | GIR_EraseRootFromParent_Done, |
| 64399 | // Label 4329: @164618 |
| 64400 | GIM_Reject, |
| 64401 | // Label 3853: @164619 |
| 64402 | GIM_Try, /*On fail goto*//*Label 4330*/ GIMT_Encode4(164667), // Rule ID 49136 // |
| 64403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64404 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64405 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64407 | // MIs[0] Operand 1 |
| 64408 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 64409 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64410 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64411 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 64413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64414 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64415 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64418 | GIR_RootConstrainSelectedInstOperands, |
| 64419 | // GIR_Coverage, 49136, |
| 64420 | GIR_EraseRootFromParent_Done, |
| 64421 | // Label 4330: @164667 |
| 64422 | GIM_Try, /*On fail goto*//*Label 4331*/ GIMT_Encode4(164715), // Rule ID 49137 // |
| 64423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64424 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64425 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64427 | // MIs[0] Operand 1 |
| 64428 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 64429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64430 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64431 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M4), |
| 64433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64434 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64435 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64438 | GIR_RootConstrainSelectedInstOperands, |
| 64439 | // GIR_Coverage, 49137, |
| 64440 | GIR_EraseRootFromParent_Done, |
| 64441 | // Label 4331: @164715 |
| 64442 | GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(164763), // Rule ID 49144 // |
| 64443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64444 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64445 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64447 | // MIs[0] Operand 1 |
| 64448 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 64449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64450 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64451 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 64453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64454 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64455 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64458 | GIR_RootConstrainSelectedInstOperands, |
| 64459 | // GIR_Coverage, 49144, |
| 64460 | GIR_EraseRootFromParent_Done, |
| 64461 | // Label 4332: @164763 |
| 64462 | GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(164811), // Rule ID 49145 // |
| 64463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64464 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64465 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64467 | // MIs[0] Operand 1 |
| 64468 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 64469 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64470 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64471 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 64473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64474 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64475 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64478 | GIR_RootConstrainSelectedInstOperands, |
| 64479 | // GIR_Coverage, 49145, |
| 64480 | GIR_EraseRootFromParent_Done, |
| 64481 | // Label 4333: @164811 |
| 64482 | GIM_Try, /*On fail goto*//*Label 4334*/ GIMT_Encode4(164859), // Rule ID 49180 // |
| 64483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64484 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64485 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64486 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64487 | // MIs[0] Operand 1 |
| 64488 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 64489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64490 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64491 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 64493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64494 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64495 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64498 | GIR_RootConstrainSelectedInstOperands, |
| 64499 | // GIR_Coverage, 49180, |
| 64500 | GIR_EraseRootFromParent_Done, |
| 64501 | // Label 4334: @164859 |
| 64502 | GIM_Try, /*On fail goto*//*Label 4335*/ GIMT_Encode4(164907), // Rule ID 49181 // |
| 64503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64507 | // MIs[0] Operand 1 |
| 64508 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 64509 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64510 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64511 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M4), |
| 64513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64515 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64518 | GIR_RootConstrainSelectedInstOperands, |
| 64519 | // GIR_Coverage, 49181, |
| 64520 | GIR_EraseRootFromParent_Done, |
| 64521 | // Label 4335: @164907 |
| 64522 | GIM_Try, /*On fail goto*//*Label 4336*/ GIMT_Encode4(164955), // Rule ID 49188 // |
| 64523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64524 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64525 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64527 | // MIs[0] Operand 1 |
| 64528 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 64529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64530 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64531 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 64533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64534 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64535 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64538 | GIR_RootConstrainSelectedInstOperands, |
| 64539 | // GIR_Coverage, 49188, |
| 64540 | GIR_EraseRootFromParent_Done, |
| 64541 | // Label 4336: @164955 |
| 64542 | GIM_Try, /*On fail goto*//*Label 4337*/ GIMT_Encode4(165003), // Rule ID 49189 // |
| 64543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64544 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64545 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64547 | // MIs[0] Operand 1 |
| 64548 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 64549 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64550 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64551 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 64553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64554 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64555 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64558 | GIR_RootConstrainSelectedInstOperands, |
| 64559 | // GIR_Coverage, 49189, |
| 64560 | GIR_EraseRootFromParent_Done, |
| 64561 | // Label 4337: @165003 |
| 64562 | GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(165051), // Rule ID 49224 // |
| 64563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64564 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64565 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64567 | // MIs[0] Operand 1 |
| 64568 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 64569 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64570 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64571 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 64573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64574 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64575 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64578 | GIR_RootConstrainSelectedInstOperands, |
| 64579 | // GIR_Coverage, 49224, |
| 64580 | GIR_EraseRootFromParent_Done, |
| 64581 | // Label 4338: @165051 |
| 64582 | GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(165099), // Rule ID 49225 // |
| 64583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64587 | // MIs[0] Operand 1 |
| 64588 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 64589 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64590 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64591 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 64593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64594 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64595 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64598 | GIR_RootConstrainSelectedInstOperands, |
| 64599 | // GIR_Coverage, 49225, |
| 64600 | GIR_EraseRootFromParent_Done, |
| 64601 | // Label 4339: @165099 |
| 64602 | GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(165147), // Rule ID 49232 // |
| 64603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64607 | // MIs[0] Operand 1 |
| 64608 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 64609 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64610 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64611 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 64613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64614 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64615 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64618 | GIR_RootConstrainSelectedInstOperands, |
| 64619 | // GIR_Coverage, 49232, |
| 64620 | GIR_EraseRootFromParent_Done, |
| 64621 | // Label 4340: @165147 |
| 64622 | GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(165195), // Rule ID 49233 // |
| 64623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64627 | // MIs[0] Operand 1 |
| 64628 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 64629 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64630 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64631 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 64633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64634 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64635 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64638 | GIR_RootConstrainSelectedInstOperands, |
| 64639 | // GIR_Coverage, 49233, |
| 64640 | GIR_EraseRootFromParent_Done, |
| 64641 | // Label 4341: @165195 |
| 64642 | GIM_Try, /*On fail goto*//*Label 4342*/ GIMT_Encode4(165243), // Rule ID 49266 // |
| 64643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64644 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64645 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64647 | // MIs[0] Operand 1 |
| 64648 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 64649 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64650 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64651 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 64653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64654 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64655 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64658 | GIR_RootConstrainSelectedInstOperands, |
| 64659 | // GIR_Coverage, 49266, |
| 64660 | GIR_EraseRootFromParent_Done, |
| 64661 | // Label 4342: @165243 |
| 64662 | GIM_Try, /*On fail goto*//*Label 4343*/ GIMT_Encode4(165291), // Rule ID 49267 // |
| 64663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64664 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64665 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64667 | // MIs[0] Operand 1 |
| 64668 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 64669 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64670 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64671 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M4), |
| 64673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64674 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64675 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64678 | GIR_RootConstrainSelectedInstOperands, |
| 64679 | // GIR_Coverage, 49267, |
| 64680 | GIR_EraseRootFromParent_Done, |
| 64681 | // Label 4343: @165291 |
| 64682 | GIM_Try, /*On fail goto*//*Label 4344*/ GIMT_Encode4(165339), // Rule ID 49274 // |
| 64683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64684 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64685 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64687 | // MIs[0] Operand 1 |
| 64688 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 64689 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64690 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64691 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 64693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64694 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64695 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64698 | GIR_RootConstrainSelectedInstOperands, |
| 64699 | // GIR_Coverage, 49274, |
| 64700 | GIR_EraseRootFromParent_Done, |
| 64701 | // Label 4344: @165339 |
| 64702 | GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(165387), // Rule ID 49275 // |
| 64703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64704 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64705 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64707 | // MIs[0] Operand 1 |
| 64708 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 64709 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64710 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64711 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 64713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64714 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64715 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64718 | GIR_RootConstrainSelectedInstOperands, |
| 64719 | // GIR_Coverage, 49275, |
| 64720 | GIR_EraseRootFromParent_Done, |
| 64721 | // Label 4345: @165387 |
| 64722 | GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(165435), // Rule ID 49310 // |
| 64723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64724 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64725 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64727 | // MIs[0] Operand 1 |
| 64728 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 64729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64730 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64731 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 64733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64734 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64735 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64738 | GIR_RootConstrainSelectedInstOperands, |
| 64739 | // GIR_Coverage, 49310, |
| 64740 | GIR_EraseRootFromParent_Done, |
| 64741 | // Label 4346: @165435 |
| 64742 | GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(165483), // Rule ID 49311 // |
| 64743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64747 | // MIs[0] Operand 1 |
| 64748 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 64749 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64750 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64751 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 64753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64754 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64755 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64758 | GIR_RootConstrainSelectedInstOperands, |
| 64759 | // GIR_Coverage, 49311, |
| 64760 | GIR_EraseRootFromParent_Done, |
| 64761 | // Label 4347: @165483 |
| 64762 | GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(165531), // Rule ID 49318 // |
| 64763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64765 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64767 | // MIs[0] Operand 1 |
| 64768 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 64769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64770 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64771 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 64773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64774 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64775 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64778 | GIR_RootConstrainSelectedInstOperands, |
| 64779 | // GIR_Coverage, 49318, |
| 64780 | GIR_EraseRootFromParent_Done, |
| 64781 | // Label 4348: @165531 |
| 64782 | GIM_Try, /*On fail goto*//*Label 4349*/ GIMT_Encode4(165579), // Rule ID 49319 // |
| 64783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64787 | // MIs[0] Operand 1 |
| 64788 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 64789 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64790 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64791 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 64793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64794 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64795 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64798 | GIR_RootConstrainSelectedInstOperands, |
| 64799 | // GIR_Coverage, 49319, |
| 64800 | GIR_EraseRootFromParent_Done, |
| 64801 | // Label 4349: @165579 |
| 64802 | GIM_Try, /*On fail goto*//*Label 4350*/ GIMT_Encode4(165627), // Rule ID 49354 // |
| 64803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64804 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64805 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64807 | // MIs[0] Operand 1 |
| 64808 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 64809 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64810 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64811 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 64813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64814 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64815 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64818 | GIR_RootConstrainSelectedInstOperands, |
| 64819 | // GIR_Coverage, 49354, |
| 64820 | GIR_EraseRootFromParent_Done, |
| 64821 | // Label 4350: @165627 |
| 64822 | GIM_Try, /*On fail goto*//*Label 4351*/ GIMT_Encode4(165675), // Rule ID 49355 // |
| 64823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64825 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64827 | // MIs[0] Operand 1 |
| 64828 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 64829 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64830 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64831 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M4), |
| 64833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64834 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64835 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64838 | GIR_RootConstrainSelectedInstOperands, |
| 64839 | // GIR_Coverage, 49355, |
| 64840 | GIR_EraseRootFromParent_Done, |
| 64841 | // Label 4351: @165675 |
| 64842 | GIM_Try, /*On fail goto*//*Label 4352*/ GIMT_Encode4(165723), // Rule ID 49362 // |
| 64843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64845 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64847 | // MIs[0] Operand 1 |
| 64848 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 64849 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64850 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64851 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 64853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64854 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64855 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64858 | GIR_RootConstrainSelectedInstOperands, |
| 64859 | // GIR_Coverage, 49362, |
| 64860 | GIR_EraseRootFromParent_Done, |
| 64861 | // Label 4352: @165723 |
| 64862 | GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(165771), // Rule ID 49363 // |
| 64863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64865 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64867 | // MIs[0] Operand 1 |
| 64868 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 64869 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64870 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64871 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 64873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64874 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64875 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64878 | GIR_RootConstrainSelectedInstOperands, |
| 64879 | // GIR_Coverage, 49363, |
| 64880 | GIR_EraseRootFromParent_Done, |
| 64881 | // Label 4353: @165771 |
| 64882 | GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(165819), // Rule ID 49398 // |
| 64883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64885 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64887 | // MIs[0] Operand 1 |
| 64888 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 64889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64890 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64891 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 64893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64894 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64895 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64898 | GIR_RootConstrainSelectedInstOperands, |
| 64899 | // GIR_Coverage, 49398, |
| 64900 | GIR_EraseRootFromParent_Done, |
| 64901 | // Label 4354: @165819 |
| 64902 | GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(165867), // Rule ID 49399 // |
| 64903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64907 | // MIs[0] Operand 1 |
| 64908 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 64909 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64910 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64911 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 64913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64914 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64915 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64918 | GIR_RootConstrainSelectedInstOperands, |
| 64919 | // GIR_Coverage, 49399, |
| 64920 | GIR_EraseRootFromParent_Done, |
| 64921 | // Label 4355: @165867 |
| 64922 | GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(165915), // Rule ID 49406 // |
| 64923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64925 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64927 | // MIs[0] Operand 1 |
| 64928 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 64929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64930 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64931 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 64932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 64933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64934 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64935 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64938 | GIR_RootConstrainSelectedInstOperands, |
| 64939 | // GIR_Coverage, 49406, |
| 64940 | GIR_EraseRootFromParent_Done, |
| 64941 | // Label 4356: @165915 |
| 64942 | GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(165963), // Rule ID 49407 // |
| 64943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 64945 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 64946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64947 | // MIs[0] Operand 1 |
| 64948 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 64949 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64950 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 64951 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 64952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 64953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64954 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 64955 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 64956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 64958 | GIR_RootConstrainSelectedInstOperands, |
| 64959 | // GIR_Coverage, 49407, |
| 64960 | GIR_EraseRootFromParent_Done, |
| 64961 | // Label 4357: @165963 |
| 64962 | GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(166011), // Rule ID 49442 // |
| 64963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 64964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64965 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64967 | // MIs[0] Operand 1 |
| 64968 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64970 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64971 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 64972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 64973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64974 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64975 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64978 | GIR_RootConstrainSelectedInstOperands, |
| 64979 | // GIR_Coverage, 49442, |
| 64980 | GIR_EraseRootFromParent_Done, |
| 64981 | // Label 4358: @166011 |
| 64982 | GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(166059), // Rule ID 49443 // |
| 64983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 64984 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 64985 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 64986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 64987 | // MIs[0] Operand 1 |
| 64988 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 64989 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64990 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 64991 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 64992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M4), |
| 64993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 64994 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 64995 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 64996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 64997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 64998 | GIR_RootConstrainSelectedInstOperands, |
| 64999 | // GIR_Coverage, 49443, |
| 65000 | GIR_EraseRootFromParent_Done, |
| 65001 | // Label 4359: @166059 |
| 65002 | GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(166107), // Rule ID 49450 // |
| 65003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65004 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 65005 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 65006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65007 | // MIs[0] Operand 1 |
| 65008 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 65009 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65010 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65011 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 65012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 65013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65014 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65015 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 65018 | GIR_RootConstrainSelectedInstOperands, |
| 65019 | // GIR_Coverage, 49450, |
| 65020 | GIR_EraseRootFromParent_Done, |
| 65021 | // Label 4360: @166107 |
| 65022 | GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(166155), // Rule ID 49451 // |
| 65023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 65025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 65026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65027 | // MIs[0] Operand 1 |
| 65028 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 65029 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65030 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65031 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 65032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 65033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65034 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65035 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 65038 | GIR_RootConstrainSelectedInstOperands, |
| 65039 | // GIR_Coverage, 49451, |
| 65040 | GIR_EraseRootFromParent_Done, |
| 65041 | // Label 4361: @166155 |
| 65042 | GIM_Try, /*On fail goto*//*Label 4362*/ GIMT_Encode4(166203), // Rule ID 49486 // |
| 65043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65044 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 65045 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 65046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65047 | // MIs[0] Operand 1 |
| 65048 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 65049 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65050 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65051 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 65053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65054 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65055 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65058 | GIR_RootConstrainSelectedInstOperands, |
| 65059 | // GIR_Coverage, 49486, |
| 65060 | GIR_EraseRootFromParent_Done, |
| 65061 | // Label 4362: @166203 |
| 65062 | GIM_Try, /*On fail goto*//*Label 4363*/ GIMT_Encode4(166251), // Rule ID 49487 // |
| 65063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65064 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 65065 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 65066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65067 | // MIs[0] Operand 1 |
| 65068 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 65069 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65070 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65071 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 65073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65074 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65075 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65078 | GIR_RootConstrainSelectedInstOperands, |
| 65079 | // GIR_Coverage, 49487, |
| 65080 | GIR_EraseRootFromParent_Done, |
| 65081 | // Label 4363: @166251 |
| 65082 | GIM_Try, /*On fail goto*//*Label 4364*/ GIMT_Encode4(166299), // Rule ID 49494 // |
| 65083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65084 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 65085 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 65086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65087 | // MIs[0] Operand 1 |
| 65088 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 65089 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65090 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65091 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 65092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65094 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65095 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 65098 | GIR_RootConstrainSelectedInstOperands, |
| 65099 | // GIR_Coverage, 49494, |
| 65100 | GIR_EraseRootFromParent_Done, |
| 65101 | // Label 4364: @166299 |
| 65102 | GIM_Try, /*On fail goto*//*Label 4365*/ GIMT_Encode4(166347), // Rule ID 49495 // |
| 65103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 65105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 65106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65107 | // MIs[0] Operand 1 |
| 65108 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 65109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65110 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65111 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 65112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65114 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65115 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 65118 | GIR_RootConstrainSelectedInstOperands, |
| 65119 | // GIR_Coverage, 49495, |
| 65120 | GIR_EraseRootFromParent_Done, |
| 65121 | // Label 4365: @166347 |
| 65122 | GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(166395), // Rule ID 49530 // |
| 65123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 65125 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 65126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65127 | // MIs[0] Operand 1 |
| 65128 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 65129 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65130 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65131 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 65133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65134 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65135 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65138 | GIR_RootConstrainSelectedInstOperands, |
| 65139 | // GIR_Coverage, 49530, |
| 65140 | GIR_EraseRootFromParent_Done, |
| 65141 | // Label 4366: @166395 |
| 65142 | GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(166443), // Rule ID 49531 // |
| 65143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 65145 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 65146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65147 | // MIs[0] Operand 1 |
| 65148 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 65149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65150 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 65151 | // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M4), |
| 65153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65154 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65155 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65158 | GIR_RootConstrainSelectedInstOperands, |
| 65159 | // GIR_Coverage, 49531, |
| 65160 | GIR_EraseRootFromParent_Done, |
| 65161 | // Label 4367: @166443 |
| 65162 | GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(166491), // Rule ID 49538 // |
| 65163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65164 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 65165 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 65166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65167 | // MIs[0] Operand 1 |
| 65168 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 65169 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65170 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65171 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 65172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65174 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65175 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 65178 | GIR_RootConstrainSelectedInstOperands, |
| 65179 | // GIR_Coverage, 49538, |
| 65180 | GIR_EraseRootFromParent_Done, |
| 65181 | // Label 4368: @166491 |
| 65182 | GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(166539), // Rule ID 49539 // |
| 65183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65184 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 65185 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 65186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65187 | // MIs[0] Operand 1 |
| 65188 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 65189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65190 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65191 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 65192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65194 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65195 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 65198 | GIR_RootConstrainSelectedInstOperands, |
| 65199 | // GIR_Coverage, 49539, |
| 65200 | GIR_EraseRootFromParent_Done, |
| 65201 | // Label 4369: @166539 |
| 65202 | GIM_Reject, |
| 65203 | // Label 3854: @166540 |
| 65204 | GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(167316), |
| 65205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 65206 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv64s8, |
| 65207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 65208 | GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(166593), // Rule ID 49138 // |
| 65209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65210 | // MIs[0] Operand 1 |
| 65211 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 65212 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65213 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65214 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 65216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65217 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65218 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65221 | GIR_RootConstrainSelectedInstOperands, |
| 65222 | // GIR_Coverage, 49138, |
| 65223 | GIR_EraseRootFromParent_Done, |
| 65224 | // Label 4371: @166593 |
| 65225 | GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(166631), // Rule ID 49139 // |
| 65226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65227 | // MIs[0] Operand 1 |
| 65228 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 65229 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65230 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65231 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETEQ:{ *:[Other] }) => (PseudoVMSEQ_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSEQ_VV_M8), |
| 65233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65234 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65235 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65238 | GIR_RootConstrainSelectedInstOperands, |
| 65239 | // GIR_Coverage, 49139, |
| 65240 | GIR_EraseRootFromParent_Done, |
| 65241 | // Label 4372: @166631 |
| 65242 | GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(166669), // Rule ID 49182 // |
| 65243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65244 | // MIs[0] Operand 1 |
| 65245 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 65246 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65247 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65248 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 65250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65251 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65252 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65255 | GIR_RootConstrainSelectedInstOperands, |
| 65256 | // GIR_Coverage, 49182, |
| 65257 | GIR_EraseRootFromParent_Done, |
| 65258 | // Label 4373: @166669 |
| 65259 | GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(166707), // Rule ID 49183 // |
| 65260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65261 | // MIs[0] Operand 1 |
| 65262 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 65263 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65264 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65265 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETNE:{ *:[Other] }) => (PseudoVMSNE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSNE_VV_M8), |
| 65267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65268 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65269 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65272 | GIR_RootConstrainSelectedInstOperands, |
| 65273 | // GIR_Coverage, 49183, |
| 65274 | GIR_EraseRootFromParent_Done, |
| 65275 | // Label 4374: @166707 |
| 65276 | GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(166745), // Rule ID 49226 // |
| 65277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65278 | // MIs[0] Operand 1 |
| 65279 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 65280 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65281 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65282 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 65284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65285 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65286 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65289 | GIR_RootConstrainSelectedInstOperands, |
| 65290 | // GIR_Coverage, 49226, |
| 65291 | GIR_EraseRootFromParent_Done, |
| 65292 | // Label 4375: @166745 |
| 65293 | GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(166783), // Rule ID 49227 // |
| 65294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65295 | // MIs[0] Operand 1 |
| 65296 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 65297 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65298 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65299 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 65301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65302 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65303 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65306 | GIR_RootConstrainSelectedInstOperands, |
| 65307 | // GIR_Coverage, 49227, |
| 65308 | GIR_EraseRootFromParent_Done, |
| 65309 | // Label 4376: @166783 |
| 65310 | GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(166821), // Rule ID 49268 // |
| 65311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65312 | // MIs[0] Operand 1 |
| 65313 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 65314 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65315 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65316 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 65318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65319 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65320 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65323 | GIR_RootConstrainSelectedInstOperands, |
| 65324 | // GIR_Coverage, 49268, |
| 65325 | GIR_EraseRootFromParent_Done, |
| 65326 | // Label 4377: @166821 |
| 65327 | GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(166859), // Rule ID 49269 // |
| 65328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65329 | // MIs[0] Operand 1 |
| 65330 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 65331 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65332 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65333 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGT:{ *:[Other] }) => (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLT_VV_M8), |
| 65335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65336 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65337 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65340 | GIR_RootConstrainSelectedInstOperands, |
| 65341 | // GIR_Coverage, 49269, |
| 65342 | GIR_EraseRootFromParent_Done, |
| 65343 | // Label 4378: @166859 |
| 65344 | GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(166897), // Rule ID 49312 // |
| 65345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65346 | // MIs[0] Operand 1 |
| 65347 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 65348 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65349 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65350 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 65352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65353 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65354 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65357 | GIR_RootConstrainSelectedInstOperands, |
| 65358 | // GIR_Coverage, 49312, |
| 65359 | GIR_EraseRootFromParent_Done, |
| 65360 | // Label 4379: @166897 |
| 65361 | GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(166935), // Rule ID 49313 // |
| 65362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65363 | // MIs[0] Operand 1 |
| 65364 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 65365 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65366 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65367 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 65369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65371 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65374 | GIR_RootConstrainSelectedInstOperands, |
| 65375 | // GIR_Coverage, 49313, |
| 65376 | GIR_EraseRootFromParent_Done, |
| 65377 | // Label 4380: @166935 |
| 65378 | GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(166973), // Rule ID 49356 // |
| 65379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65380 | // MIs[0] Operand 1 |
| 65381 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 65382 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65383 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65384 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 65386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65387 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65388 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65391 | GIR_RootConstrainSelectedInstOperands, |
| 65392 | // GIR_Coverage, 49356, |
| 65393 | GIR_EraseRootFromParent_Done, |
| 65394 | // Label 4381: @166973 |
| 65395 | GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(167011), // Rule ID 49357 // |
| 65396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65397 | // MIs[0] Operand 1 |
| 65398 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 65399 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65400 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65401 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGT:{ *:[Other] }) => (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLTU_VV_M8), |
| 65403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65404 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65405 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65408 | GIR_RootConstrainSelectedInstOperands, |
| 65409 | // GIR_Coverage, 49357, |
| 65410 | GIR_EraseRootFromParent_Done, |
| 65411 | // Label 4382: @167011 |
| 65412 | GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(167049), // Rule ID 49400 // |
| 65413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65414 | // MIs[0] Operand 1 |
| 65415 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 65416 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65417 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65418 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 65420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65421 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65422 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65425 | GIR_RootConstrainSelectedInstOperands, |
| 65426 | // GIR_Coverage, 49400, |
| 65427 | GIR_EraseRootFromParent_Done, |
| 65428 | // Label 4383: @167049 |
| 65429 | GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(167087), // Rule ID 49401 // |
| 65430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65431 | // MIs[0] Operand 1 |
| 65432 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 65433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65434 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65435 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 65437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65438 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65439 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65442 | GIR_RootConstrainSelectedInstOperands, |
| 65443 | // GIR_Coverage, 49401, |
| 65444 | GIR_EraseRootFromParent_Done, |
| 65445 | // Label 4384: @167087 |
| 65446 | GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(167125), // Rule ID 49444 // |
| 65447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65448 | // MIs[0] Operand 1 |
| 65449 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 65450 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65451 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65452 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 65454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65455 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65456 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65459 | GIR_RootConstrainSelectedInstOperands, |
| 65460 | // GIR_Coverage, 49444, |
| 65461 | GIR_EraseRootFromParent_Done, |
| 65462 | // Label 4385: @167125 |
| 65463 | GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(167163), // Rule ID 49445 // |
| 65464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65465 | // MIs[0] Operand 1 |
| 65466 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 65467 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65468 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65469 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGE:{ *:[Other] }) => (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLE_VV_M8), |
| 65471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65472 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65473 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65476 | GIR_RootConstrainSelectedInstOperands, |
| 65477 | // GIR_Coverage, 49445, |
| 65478 | GIR_EraseRootFromParent_Done, |
| 65479 | // Label 4386: @167163 |
| 65480 | GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(167201), // Rule ID 49488 // |
| 65481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65482 | // MIs[0] Operand 1 |
| 65483 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 65484 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65485 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65486 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65487 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65488 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65489 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65490 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65493 | GIR_RootConstrainSelectedInstOperands, |
| 65494 | // GIR_Coverage, 49488, |
| 65495 | GIR_EraseRootFromParent_Done, |
| 65496 | // Label 4387: @167201 |
| 65497 | GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(167239), // Rule ID 49489 // |
| 65498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65499 | // MIs[0] Operand 1 |
| 65500 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 65501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65502 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65503 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65507 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65510 | GIR_RootConstrainSelectedInstOperands, |
| 65511 | // GIR_Coverage, 49489, |
| 65512 | GIR_EraseRootFromParent_Done, |
| 65513 | // Label 4388: @167239 |
| 65514 | GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(167277), // Rule ID 49532 // |
| 65515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 65516 | // MIs[0] Operand 1 |
| 65517 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 65518 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65519 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65520 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 65521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65523 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65524 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65527 | GIR_RootConstrainSelectedInstOperands, |
| 65528 | // GIR_Coverage, 49532, |
| 65529 | GIR_EraseRootFromParent_Done, |
| 65530 | // Label 4389: @167277 |
| 65531 | GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(167315), // Rule ID 49533 // |
| 65532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 65533 | // MIs[0] Operand 1 |
| 65534 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 65535 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65536 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 65537 | // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGE:{ *:[Other] }) => (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 65538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMSLEU_VV_M8), |
| 65539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65540 | GIR_RootToRootCopy, /*OpIdx*/3, // rs1 |
| 65541 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 65542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 65543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 65544 | GIR_RootConstrainSelectedInstOperands, |
| 65545 | // GIR_Coverage, 49533, |
| 65546 | GIR_EraseRootFromParent_Done, |
| 65547 | // Label 4390: @167315 |
| 65548 | GIM_Reject, |
| 65549 | // Label 4370: @167316 |
| 65550 | GIM_Reject, |
| 65551 | // Label 3855: @167317 |
| 65552 | GIM_Reject, |
| 65553 | // Label 45: @167318 |
| 65554 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(30), /*)*//*default:*//*Label 4399*/ GIMT_Encode4(174779), |
| 65555 | /*GILLT_s32*//*Label 4391*/ GIMT_Encode4(167437), |
| 65556 | /*GILLT_s64*//*Label 4392*/ GIMT_Encode4(168194), |
| 65557 | /*GILLT_nxv1s1*//*Label 4393*/ GIMT_Encode4(169077), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 65558 | /*GILLT_nxv2s1*//*Label 4394*/ GIMT_Encode4(170230), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 65559 | /*GILLT_nxv4s1*//*Label 4395*/ GIMT_Encode4(171383), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 65560 | /*GILLT_nxv8s1*//*Label 4396*/ GIMT_Encode4(172536), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 65561 | /*GILLT_nxv16s1*//*Label 4397*/ GIMT_Encode4(173689), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 65562 | /*GILLT_nxv32s1*//*Label 4398*/ GIMT_Encode4(174458), |
| 65563 | // Label 4391: @167437 |
| 65564 | GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(167479), // Rule ID 1433 // |
| 65565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 65566 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65567 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65568 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65569 | // MIs[0] Operand 1 |
| 65570 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65571 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65572 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65573 | // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_S), |
| 65575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65576 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65577 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65578 | GIR_RootConstrainSelectedInstOperands, |
| 65579 | // GIR_Coverage, 1433, |
| 65580 | GIR_EraseRootFromParent_Done, |
| 65581 | // Label 4400: @167479 |
| 65582 | GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(167521), // Rule ID 1437 // |
| 65583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 65584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65587 | // MIs[0] Operand 1 |
| 65588 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65589 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65590 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65591 | // (setcc:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_S_INX), |
| 65593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65594 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65595 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65596 | GIR_RootConstrainSelectedInstOperands, |
| 65597 | // GIR_Coverage, 1437, |
| 65598 | GIR_EraseRootFromParent_Done, |
| 65599 | // Label 4401: @167521 |
| 65600 | GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(167563), // Rule ID 1481 // |
| 65601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 65602 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65603 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65605 | // MIs[0] Operand 1 |
| 65606 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65608 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65609 | // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_S), |
| 65611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65612 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65613 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65614 | GIR_RootConstrainSelectedInstOperands, |
| 65615 | // GIR_Coverage, 1481, |
| 65616 | GIR_EraseRootFromParent_Done, |
| 65617 | // Label 4402: @167563 |
| 65618 | GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(167605), // Rule ID 1485 // |
| 65619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 65620 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65621 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65623 | // MIs[0] Operand 1 |
| 65624 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65625 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65626 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65627 | // (setcc:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_S_INX), |
| 65629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65630 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65631 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65632 | GIR_RootConstrainSelectedInstOperands, |
| 65633 | // GIR_Coverage, 1485, |
| 65634 | GIR_EraseRootFromParent_Done, |
| 65635 | // Label 4403: @167605 |
| 65636 | GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(167647), // Rule ID 1497 // |
| 65637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 65638 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65639 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65641 | // MIs[0] Operand 1 |
| 65642 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65643 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65644 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65645 | // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_S), |
| 65647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65648 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65649 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65650 | GIR_RootConstrainSelectedInstOperands, |
| 65651 | // GIR_Coverage, 1497, |
| 65652 | GIR_EraseRootFromParent_Done, |
| 65653 | // Label 4404: @167647 |
| 65654 | GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(167689), // Rule ID 1501 // |
| 65655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 65656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65659 | // MIs[0] Operand 1 |
| 65660 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65662 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65663 | // (setcc:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_S_INX), |
| 65665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65667 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65668 | GIR_RootConstrainSelectedInstOperands, |
| 65669 | // GIR_Coverage, 1501, |
| 65670 | GIR_EraseRootFromParent_Done, |
| 65671 | // Label 4405: @167689 |
| 65672 | GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(167731), // Rule ID 1800 // |
| 65673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 65674 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65675 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 65676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65677 | // MIs[0] Operand 1 |
| 65678 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 65680 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 65681 | // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 65682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_D), |
| 65683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65684 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65685 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65686 | GIR_RootConstrainSelectedInstOperands, |
| 65687 | // GIR_Coverage, 1800, |
| 65688 | GIR_EraseRootFromParent_Done, |
| 65689 | // Label 4406: @167731 |
| 65690 | GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(167773), // Rule ID 1804 // |
| 65691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 65692 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65693 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 65694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65695 | // MIs[0] Operand 1 |
| 65696 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 65698 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 65699 | // (setcc:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 65700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_D_IN32X), |
| 65701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65702 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65703 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65704 | GIR_RootConstrainSelectedInstOperands, |
| 65705 | // GIR_Coverage, 1804, |
| 65706 | GIR_EraseRootFromParent_Done, |
| 65707 | // Label 4407: @167773 |
| 65708 | GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(167815), // Rule ID 1842 // |
| 65709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 65710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 65712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65713 | // MIs[0] Operand 1 |
| 65714 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65715 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 65716 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 65717 | // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 65718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_D), |
| 65719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65720 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65721 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65722 | GIR_RootConstrainSelectedInstOperands, |
| 65723 | // GIR_Coverage, 1842, |
| 65724 | GIR_EraseRootFromParent_Done, |
| 65725 | // Label 4408: @167815 |
| 65726 | GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(167857), // Rule ID 1850 // |
| 65727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 65728 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65729 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 65730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65731 | // MIs[0] Operand 1 |
| 65732 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 65734 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 65735 | // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 65736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_D), |
| 65737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65738 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65739 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65740 | GIR_RootConstrainSelectedInstOperands, |
| 65741 | // GIR_Coverage, 1850, |
| 65742 | GIR_EraseRootFromParent_Done, |
| 65743 | // Label 4409: @167857 |
| 65744 | GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(167899), // Rule ID 1878 // |
| 65745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 65746 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65747 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 65748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65749 | // MIs[0] Operand 1 |
| 65750 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65751 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 65752 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 65753 | // (setcc:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 65754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_D_IN32X), |
| 65755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65756 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65757 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65758 | GIR_RootConstrainSelectedInstOperands, |
| 65759 | // GIR_Coverage, 1878, |
| 65760 | GIR_EraseRootFromParent_Done, |
| 65761 | // Label 4410: @167899 |
| 65762 | GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(167941), // Rule ID 1886 // |
| 65763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 65764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65765 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 65766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65767 | // MIs[0] Operand 1 |
| 65768 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 65770 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 65771 | // (setcc:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 65772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_D_IN32X), |
| 65773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65774 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65775 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65776 | GIR_RootConstrainSelectedInstOperands, |
| 65777 | // GIR_Coverage, 1886, |
| 65778 | GIR_EraseRootFromParent_Done, |
| 65779 | // Label 4411: @167941 |
| 65780 | GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(167983), // Rule ID 2125 // |
| 65781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 65782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65783 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 65784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65785 | // MIs[0] Operand 1 |
| 65786 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65787 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 65788 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 65789 | // (setcc:{ *:[i32] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 65790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_H), |
| 65791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65792 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65793 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65794 | GIR_RootConstrainSelectedInstOperands, |
| 65795 | // GIR_Coverage, 2125, |
| 65796 | GIR_EraseRootFromParent_Done, |
| 65797 | // Label 4412: @167983 |
| 65798 | GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(168025), // Rule ID 2129 // |
| 65799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 65800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 65802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65803 | // MIs[0] Operand 1 |
| 65804 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 65806 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 65807 | // (setcc:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 65808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_H_INX), |
| 65809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65810 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65811 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65812 | GIR_RootConstrainSelectedInstOperands, |
| 65813 | // GIR_Coverage, 2129, |
| 65814 | GIR_EraseRootFromParent_Done, |
| 65815 | // Label 4413: @168025 |
| 65816 | GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(168067), // Rule ID 2173 // |
| 65817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 65818 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65819 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 65820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65821 | // MIs[0] Operand 1 |
| 65822 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65823 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 65824 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 65825 | // (setcc:{ *:[i32] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 65826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_H), |
| 65827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65828 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65829 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65830 | GIR_RootConstrainSelectedInstOperands, |
| 65831 | // GIR_Coverage, 2173, |
| 65832 | GIR_EraseRootFromParent_Done, |
| 65833 | // Label 4414: @168067 |
| 65834 | GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(168109), // Rule ID 2177 // |
| 65835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 65836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65837 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 65838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65839 | // MIs[0] Operand 1 |
| 65840 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65841 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 65842 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 65843 | // (setcc:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 65844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_H_INX), |
| 65845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65846 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65847 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65848 | GIR_RootConstrainSelectedInstOperands, |
| 65849 | // GIR_Coverage, 2177, |
| 65850 | GIR_EraseRootFromParent_Done, |
| 65851 | // Label 4415: @168109 |
| 65852 | GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(168151), // Rule ID 2189 // |
| 65853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 65854 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65855 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 65856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65857 | // MIs[0] Operand 1 |
| 65858 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65859 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 65860 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 65861 | // (setcc:{ *:[i32] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 65862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_H), |
| 65863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65864 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65865 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65866 | GIR_RootConstrainSelectedInstOperands, |
| 65867 | // GIR_Coverage, 2189, |
| 65868 | GIR_EraseRootFromParent_Done, |
| 65869 | // Label 4416: @168151 |
| 65870 | GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(168193), // Rule ID 2193 // |
| 65871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 65872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65873 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 65874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65875 | // MIs[0] Operand 1 |
| 65876 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65877 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 65878 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 65879 | // (setcc:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 65880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_H_INX), |
| 65881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65882 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65883 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65884 | GIR_RootConstrainSelectedInstOperands, |
| 65885 | // GIR_Coverage, 2193, |
| 65886 | GIR_EraseRootFromParent_Done, |
| 65887 | // Label 4417: @168193 |
| 65888 | GIM_Reject, |
| 65889 | // Label 4392: @168194 |
| 65890 | GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(168236), // Rule ID 1432 // |
| 65891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 65892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65893 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65895 | // MIs[0] Operand 1 |
| 65896 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65897 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65898 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65899 | // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_S), |
| 65901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65902 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65903 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65904 | GIR_RootConstrainSelectedInstOperands, |
| 65905 | // GIR_Coverage, 1432, |
| 65906 | GIR_EraseRootFromParent_Done, |
| 65907 | // Label 4418: @168236 |
| 65908 | GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(168278), // Rule ID 1436 // |
| 65909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 65910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65913 | // MIs[0] Operand 1 |
| 65914 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 65915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65916 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65917 | // (setcc:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_S_INX), |
| 65919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65920 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65921 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65922 | GIR_RootConstrainSelectedInstOperands, |
| 65923 | // GIR_Coverage, 1436, |
| 65924 | GIR_EraseRootFromParent_Done, |
| 65925 | // Label 4419: @168278 |
| 65926 | GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(168320), // Rule ID 1480 // |
| 65927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 65928 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65929 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65931 | // MIs[0] Operand 1 |
| 65932 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65933 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65934 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65935 | // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_S), |
| 65937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65938 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65939 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65940 | GIR_RootConstrainSelectedInstOperands, |
| 65941 | // GIR_Coverage, 1480, |
| 65942 | GIR_EraseRootFromParent_Done, |
| 65943 | // Label 4420: @168320 |
| 65944 | GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(168362), // Rule ID 1484 // |
| 65945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 65946 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65947 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65949 | // MIs[0] Operand 1 |
| 65950 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 65951 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65952 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65953 | // (setcc:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_S_INX), |
| 65955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65956 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65957 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65958 | GIR_RootConstrainSelectedInstOperands, |
| 65959 | // GIR_Coverage, 1484, |
| 65960 | GIR_EraseRootFromParent_Done, |
| 65961 | // Label 4421: @168362 |
| 65962 | GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(168404), // Rule ID 1496 // |
| 65963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 65964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65965 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65967 | // MIs[0] Operand 1 |
| 65968 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65970 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 65971 | // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_S), |
| 65973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65974 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65975 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65976 | GIR_RootConstrainSelectedInstOperands, |
| 65977 | // GIR_Coverage, 1496, |
| 65978 | GIR_EraseRootFromParent_Done, |
| 65979 | // Label 4422: @168404 |
| 65980 | GIM_Try, /*On fail goto*//*Label 4423*/ GIMT_Encode4(168446), // Rule ID 1500 // |
| 65981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 65982 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65983 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 65984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 65985 | // MIs[0] Operand 1 |
| 65986 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 65987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65988 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 65989 | // (setcc:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 65990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_S_INX), |
| 65991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 65992 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 65993 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 65994 | GIR_RootConstrainSelectedInstOperands, |
| 65995 | // GIR_Coverage, 1500, |
| 65996 | GIR_EraseRootFromParent_Done, |
| 65997 | // Label 4423: @168446 |
| 65998 | GIM_Try, /*On fail goto*//*Label 4424*/ GIMT_Encode4(168488), // Rule ID 1799 // |
| 65999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 66000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66003 | // MIs[0] Operand 1 |
| 66004 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 66006 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 66007 | // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_D), |
| 66009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66010 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66011 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66012 | GIR_RootConstrainSelectedInstOperands, |
| 66013 | // GIR_Coverage, 1799, |
| 66014 | GIR_EraseRootFromParent_Done, |
| 66015 | // Label 4424: @168488 |
| 66016 | GIM_Try, /*On fail goto*//*Label 4425*/ GIMT_Encode4(168530), // Rule ID 1803 // |
| 66017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 66018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66021 | // MIs[0] Operand 1 |
| 66022 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 66024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 66025 | // (setcc:{ *:[i64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_D_IN32X:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_D_IN32X), |
| 66027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66028 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66029 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66030 | GIR_RootConstrainSelectedInstOperands, |
| 66031 | // GIR_Coverage, 1803, |
| 66032 | GIR_EraseRootFromParent_Done, |
| 66033 | // Label 4425: @168530 |
| 66034 | GIM_Try, /*On fail goto*//*Label 4426*/ GIMT_Encode4(168572), // Rule ID 1806 // |
| 66035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 66036 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66037 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66039 | // MIs[0] Operand 1 |
| 66040 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66041 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66042 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66043 | // (setcc:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_D_INX), |
| 66045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66046 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66047 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66048 | GIR_RootConstrainSelectedInstOperands, |
| 66049 | // GIR_Coverage, 1806, |
| 66050 | GIR_EraseRootFromParent_Done, |
| 66051 | // Label 4426: @168572 |
| 66052 | GIM_Try, /*On fail goto*//*Label 4427*/ GIMT_Encode4(168614), // Rule ID 1841 // |
| 66053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 66054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66055 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66057 | // MIs[0] Operand 1 |
| 66058 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 66060 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 66061 | // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_D), |
| 66063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66065 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66066 | GIR_RootConstrainSelectedInstOperands, |
| 66067 | // GIR_Coverage, 1841, |
| 66068 | GIR_EraseRootFromParent_Done, |
| 66069 | // Label 4427: @168614 |
| 66070 | GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(168656), // Rule ID 1849 // |
| 66071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 66072 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66073 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66075 | // MIs[0] Operand 1 |
| 66076 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66077 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 66078 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 66079 | // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_D), |
| 66081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66082 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66083 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66084 | GIR_RootConstrainSelectedInstOperands, |
| 66085 | // GIR_Coverage, 1849, |
| 66086 | GIR_EraseRootFromParent_Done, |
| 66087 | // Label 4428: @168656 |
| 66088 | GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(168698), // Rule ID 1858 // |
| 66089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 66090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66091 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66093 | // MIs[0] Operand 1 |
| 66094 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66096 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66097 | // (setcc:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_D_INX), |
| 66099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66100 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66101 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66102 | GIR_RootConstrainSelectedInstOperands, |
| 66103 | // GIR_Coverage, 1858, |
| 66104 | GIR_EraseRootFromParent_Done, |
| 66105 | // Label 4429: @168698 |
| 66106 | GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(168740), // Rule ID 1862 // |
| 66107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 66108 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66109 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66111 | // MIs[0] Operand 1 |
| 66112 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66114 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66115 | // (setcc:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_D_INX), |
| 66117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66118 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66119 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66120 | GIR_RootConstrainSelectedInstOperands, |
| 66121 | // GIR_Coverage, 1862, |
| 66122 | GIR_EraseRootFromParent_Done, |
| 66123 | // Label 4430: @168740 |
| 66124 | GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(168782), // Rule ID 1877 // |
| 66125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 66126 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66127 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66129 | // MIs[0] Operand 1 |
| 66130 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66131 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 66132 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 66133 | // (setcc:{ *:[i64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_D_IN32X:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_D_IN32X), |
| 66135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66136 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66137 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66138 | GIR_RootConstrainSelectedInstOperands, |
| 66139 | // GIR_Coverage, 1877, |
| 66140 | GIR_EraseRootFromParent_Done, |
| 66141 | // Label 4431: @168782 |
| 66142 | GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(168824), // Rule ID 1885 // |
| 66143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 66144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66145 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 66146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66147 | // MIs[0] Operand 1 |
| 66148 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 66150 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 66151 | // (setcc:{ *:[i64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_D_IN32X:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 66152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_D_IN32X), |
| 66153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66154 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66155 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66156 | GIR_RootConstrainSelectedInstOperands, |
| 66157 | // GIR_Coverage, 1885, |
| 66158 | GIR_EraseRootFromParent_Done, |
| 66159 | // Label 4432: @168824 |
| 66160 | GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(168866), // Rule ID 2124 // |
| 66161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 66162 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66163 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 66164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66165 | // MIs[0] Operand 1 |
| 66166 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66167 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 66168 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 66169 | // (setcc:{ *:[i64] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 66170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_H), |
| 66171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66172 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66173 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66174 | GIR_RootConstrainSelectedInstOperands, |
| 66175 | // GIR_Coverage, 2124, |
| 66176 | GIR_EraseRootFromParent_Done, |
| 66177 | // Label 4433: @168866 |
| 66178 | GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(168908), // Rule ID 2128 // |
| 66179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 66180 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66181 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 66182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66183 | // MIs[0] Operand 1 |
| 66184 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66185 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 66186 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 66187 | // (setcc:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, SETOEQ:{ *:[Other] }) => (FEQ_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 66188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FEQ_H_INX), |
| 66189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66190 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66191 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66192 | GIR_RootConstrainSelectedInstOperands, |
| 66193 | // GIR_Coverage, 2128, |
| 66194 | GIR_EraseRootFromParent_Done, |
| 66195 | // Label 4434: @168908 |
| 66196 | GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(168950), // Rule ID 2172 // |
| 66197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 66198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66199 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 66200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66201 | // MIs[0] Operand 1 |
| 66202 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66203 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 66204 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 66205 | // (setcc:{ *:[i64] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 66206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_H), |
| 66207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66208 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66209 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66210 | GIR_RootConstrainSelectedInstOperands, |
| 66211 | // GIR_Coverage, 2172, |
| 66212 | GIR_EraseRootFromParent_Done, |
| 66213 | // Label 4435: @168950 |
| 66214 | GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(168992), // Rule ID 2176 // |
| 66215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 66216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66217 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 66218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66219 | // MIs[0] Operand 1 |
| 66220 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66221 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 66222 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 66223 | // (setcc:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, SETOLT:{ *:[Other] }) => (FLT_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 66224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLT_H_INX), |
| 66225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66226 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66227 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66228 | GIR_RootConstrainSelectedInstOperands, |
| 66229 | // GIR_Coverage, 2176, |
| 66230 | GIR_EraseRootFromParent_Done, |
| 66231 | // Label 4436: @168992 |
| 66232 | GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(169034), // Rule ID 2188 // |
| 66233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 66234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66235 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 66236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66237 | // MIs[0] Operand 1 |
| 66238 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 66240 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 66241 | // (setcc:{ *:[i64] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 66242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_H), |
| 66243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66244 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66245 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66246 | GIR_RootConstrainSelectedInstOperands, |
| 66247 | // GIR_Coverage, 2188, |
| 66248 | GIR_EraseRootFromParent_Done, |
| 66249 | // Label 4437: @169034 |
| 66250 | GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(169076), // Rule ID 2192 // |
| 66251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 66252 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66253 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 66254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 66255 | // MIs[0] Operand 1 |
| 66256 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 66258 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 66259 | // (setcc:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, SETOLE:{ *:[Other] }) => (FLE_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 66260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FLE_H_INX), |
| 66261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66262 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66263 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66264 | GIR_RootConstrainSelectedInstOperands, |
| 66265 | // GIR_Coverage, 2192, |
| 66266 | GIR_EraseRootFromParent_Done, |
| 66267 | // Label 4438: @169076 |
| 66268 | GIM_Reject, |
| 66269 | // Label 4393: @169077 |
| 66270 | GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(169125), // Rule ID 57474 // |
| 66271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66272 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66273 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66275 | // MIs[0] Operand 1 |
| 66276 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66277 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66278 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66279 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 66280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_MF4), |
| 66281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66282 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66283 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66286 | GIR_RootConstrainSelectedInstOperands, |
| 66287 | // GIR_Coverage, 57474, |
| 66288 | GIR_EraseRootFromParent_Done, |
| 66289 | // Label 4439: @169125 |
| 66290 | GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(169173), // Rule ID 57475 // |
| 66291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 66292 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66293 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66295 | // MIs[0] Operand 1 |
| 66296 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66297 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66298 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66299 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 66300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_MF4), |
| 66301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66302 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66303 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66306 | GIR_RootConstrainSelectedInstOperands, |
| 66307 | // GIR_Coverage, 57475, |
| 66308 | GIR_EraseRootFromParent_Done, |
| 66309 | // Label 4440: @169173 |
| 66310 | GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(169221), // Rule ID 57494 // |
| 66311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 66312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66313 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66315 | // MIs[0] Operand 1 |
| 66316 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66318 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66319 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 66320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_MF2), |
| 66321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66322 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66323 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66326 | GIR_RootConstrainSelectedInstOperands, |
| 66327 | // GIR_Coverage, 57494, |
| 66328 | GIR_EraseRootFromParent_Done, |
| 66329 | // Label 4441: @169221 |
| 66330 | GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(169269), // Rule ID 57495 // |
| 66331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 66332 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66333 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66335 | // MIs[0] Operand 1 |
| 66336 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66338 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66339 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 66340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_MF2), |
| 66341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66342 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66343 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66346 | GIR_RootConstrainSelectedInstOperands, |
| 66347 | // GIR_Coverage, 57495, |
| 66348 | GIR_EraseRootFromParent_Done, |
| 66349 | // Label 4442: @169269 |
| 66350 | GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(169317), // Rule ID 57524 // |
| 66351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 66352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66353 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66355 | // MIs[0] Operand 1 |
| 66356 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66358 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66359 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 66360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M1), |
| 66361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66362 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66363 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66366 | GIR_RootConstrainSelectedInstOperands, |
| 66367 | // GIR_Coverage, 57524, |
| 66368 | GIR_EraseRootFromParent_Done, |
| 66369 | // Label 4443: @169317 |
| 66370 | GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(169365), // Rule ID 57525 // |
| 66371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 66372 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66373 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66375 | // MIs[0] Operand 1 |
| 66376 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66378 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66379 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 66380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M1), |
| 66381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66382 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66383 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66386 | GIR_RootConstrainSelectedInstOperands, |
| 66387 | // GIR_Coverage, 57525, |
| 66388 | GIR_EraseRootFromParent_Done, |
| 66389 | // Label 4444: @169365 |
| 66390 | GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(169413), // Rule ID 57774 // |
| 66391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66393 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66395 | // MIs[0] Operand 1 |
| 66396 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66397 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66398 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66399 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 66400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_MF4), |
| 66401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66402 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66403 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66406 | GIR_RootConstrainSelectedInstOperands, |
| 66407 | // GIR_Coverage, 57774, |
| 66408 | GIR_EraseRootFromParent_Done, |
| 66409 | // Label 4445: @169413 |
| 66410 | GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(169461), // Rule ID 57775 // |
| 66411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 66412 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66413 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66415 | // MIs[0] Operand 1 |
| 66416 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66417 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66418 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66419 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 66420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_MF4), |
| 66421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66422 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66423 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66426 | GIR_RootConstrainSelectedInstOperands, |
| 66427 | // GIR_Coverage, 57775, |
| 66428 | GIR_EraseRootFromParent_Done, |
| 66429 | // Label 4446: @169461 |
| 66430 | GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(169509), // Rule ID 57794 // |
| 66431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 66432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66433 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66435 | // MIs[0] Operand 1 |
| 66436 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66437 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66438 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66439 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 66440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_MF2), |
| 66441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66442 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66443 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66446 | GIR_RootConstrainSelectedInstOperands, |
| 66447 | // GIR_Coverage, 57794, |
| 66448 | GIR_EraseRootFromParent_Done, |
| 66449 | // Label 4447: @169509 |
| 66450 | GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(169557), // Rule ID 57795 // |
| 66451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 66452 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66453 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66455 | // MIs[0] Operand 1 |
| 66456 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66458 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66459 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 66460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_MF2), |
| 66461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66462 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66463 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66466 | GIR_RootConstrainSelectedInstOperands, |
| 66467 | // GIR_Coverage, 57795, |
| 66468 | GIR_EraseRootFromParent_Done, |
| 66469 | // Label 4448: @169557 |
| 66470 | GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(169605), // Rule ID 57824 // |
| 66471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 66472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66473 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66475 | // MIs[0] Operand 1 |
| 66476 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66477 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66478 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66479 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 66480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M1), |
| 66481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66482 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66483 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66486 | GIR_RootConstrainSelectedInstOperands, |
| 66487 | // GIR_Coverage, 57824, |
| 66488 | GIR_EraseRootFromParent_Done, |
| 66489 | // Label 4449: @169605 |
| 66490 | GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(169653), // Rule ID 57825 // |
| 66491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 66492 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66493 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66495 | // MIs[0] Operand 1 |
| 66496 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66497 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66498 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66499 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 66500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M1), |
| 66501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66502 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66503 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66506 | GIR_RootConstrainSelectedInstOperands, |
| 66507 | // GIR_Coverage, 57825, |
| 66508 | GIR_EraseRootFromParent_Done, |
| 66509 | // Label 4450: @169653 |
| 66510 | GIM_Try, /*On fail goto*//*Label 4451*/ GIMT_Encode4(169701), // Rule ID 58074 // |
| 66511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66512 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66513 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66515 | // MIs[0] Operand 1 |
| 66516 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66517 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66518 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66519 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 66520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_MF4), |
| 66521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66522 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66523 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66526 | GIR_RootConstrainSelectedInstOperands, |
| 66527 | // GIR_Coverage, 58074, |
| 66528 | GIR_EraseRootFromParent_Done, |
| 66529 | // Label 4451: @169701 |
| 66530 | GIM_Try, /*On fail goto*//*Label 4452*/ GIMT_Encode4(169749), // Rule ID 58075 // |
| 66531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 66532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66533 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66535 | // MIs[0] Operand 1 |
| 66536 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66538 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66539 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 66540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_MF4), |
| 66541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66542 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66543 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66546 | GIR_RootConstrainSelectedInstOperands, |
| 66547 | // GIR_Coverage, 58075, |
| 66548 | GIR_EraseRootFromParent_Done, |
| 66549 | // Label 4452: @169749 |
| 66550 | GIM_Try, /*On fail goto*//*Label 4453*/ GIMT_Encode4(169797), // Rule ID 58094 // |
| 66551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 66552 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66553 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66555 | // MIs[0] Operand 1 |
| 66556 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66557 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66558 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66559 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 66560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_MF2), |
| 66561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66562 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66563 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66566 | GIR_RootConstrainSelectedInstOperands, |
| 66567 | // GIR_Coverage, 58094, |
| 66568 | GIR_EraseRootFromParent_Done, |
| 66569 | // Label 4453: @169797 |
| 66570 | GIM_Try, /*On fail goto*//*Label 4454*/ GIMT_Encode4(169845), // Rule ID 58095 // |
| 66571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 66572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66573 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66575 | // MIs[0] Operand 1 |
| 66576 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66578 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66579 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 66580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_MF2), |
| 66581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66582 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66583 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66586 | GIR_RootConstrainSelectedInstOperands, |
| 66587 | // GIR_Coverage, 58095, |
| 66588 | GIR_EraseRootFromParent_Done, |
| 66589 | // Label 4454: @169845 |
| 66590 | GIM_Try, /*On fail goto*//*Label 4455*/ GIMT_Encode4(169893), // Rule ID 58124 // |
| 66591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 66592 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66593 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66595 | // MIs[0] Operand 1 |
| 66596 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66597 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66598 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66599 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 66600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M1), |
| 66601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66602 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66603 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66606 | GIR_RootConstrainSelectedInstOperands, |
| 66607 | // GIR_Coverage, 58124, |
| 66608 | GIR_EraseRootFromParent_Done, |
| 66609 | // Label 4455: @169893 |
| 66610 | GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(169941), // Rule ID 58125 // |
| 66611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 66612 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66613 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66615 | // MIs[0] Operand 1 |
| 66616 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66618 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66619 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 66620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M1), |
| 66621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66622 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66623 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66626 | GIR_RootConstrainSelectedInstOperands, |
| 66627 | // GIR_Coverage, 58125, |
| 66628 | GIR_EraseRootFromParent_Done, |
| 66629 | // Label 4456: @169941 |
| 66630 | GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(169989), // Rule ID 58374 // |
| 66631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66635 | // MIs[0] Operand 1 |
| 66636 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66637 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66638 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66639 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 66640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_MF4), |
| 66641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66642 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66643 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66646 | GIR_RootConstrainSelectedInstOperands, |
| 66647 | // GIR_Coverage, 58374, |
| 66648 | GIR_EraseRootFromParent_Done, |
| 66649 | // Label 4457: @169989 |
| 66650 | GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(170037), // Rule ID 58375 // |
| 66651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 66652 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 66653 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 66654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66655 | // MIs[0] Operand 1 |
| 66656 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66657 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66658 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66659 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 66660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_MF4), |
| 66661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66662 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66663 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66666 | GIR_RootConstrainSelectedInstOperands, |
| 66667 | // GIR_Coverage, 58375, |
| 66668 | GIR_EraseRootFromParent_Done, |
| 66669 | // Label 4458: @170037 |
| 66670 | GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(170085), // Rule ID 58394 // |
| 66671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 66672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66673 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66675 | // MIs[0] Operand 1 |
| 66676 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66677 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66678 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66679 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 66680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_MF2), |
| 66681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66682 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66683 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66686 | GIR_RootConstrainSelectedInstOperands, |
| 66687 | // GIR_Coverage, 58394, |
| 66688 | GIR_EraseRootFromParent_Done, |
| 66689 | // Label 4459: @170085 |
| 66690 | GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(170133), // Rule ID 58395 // |
| 66691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 66692 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 66693 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 66694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66695 | // MIs[0] Operand 1 |
| 66696 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66698 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66699 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 66700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_MF2), |
| 66701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66702 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66703 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66706 | GIR_RootConstrainSelectedInstOperands, |
| 66707 | // GIR_Coverage, 58395, |
| 66708 | GIR_EraseRootFromParent_Done, |
| 66709 | // Label 4460: @170133 |
| 66710 | GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(170181), // Rule ID 58424 // |
| 66711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 66712 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66713 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66715 | // MIs[0] Operand 1 |
| 66716 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66717 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66718 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66719 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 66720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M1), |
| 66721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66722 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66723 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66726 | GIR_RootConstrainSelectedInstOperands, |
| 66727 | // GIR_Coverage, 58424, |
| 66728 | GIR_EraseRootFromParent_Done, |
| 66729 | // Label 4461: @170181 |
| 66730 | GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(170229), // Rule ID 58425 // |
| 66731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 66732 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 66733 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 66734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66735 | // MIs[0] Operand 1 |
| 66736 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 66737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66738 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66739 | // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 66740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M1), |
| 66741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66742 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66743 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66746 | GIR_RootConstrainSelectedInstOperands, |
| 66747 | // GIR_Coverage, 58425, |
| 66748 | GIR_EraseRootFromParent_Done, |
| 66749 | // Label 4462: @170229 |
| 66750 | GIM_Reject, |
| 66751 | // Label 4394: @170230 |
| 66752 | GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(170278), // Rule ID 57484 // |
| 66753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 66755 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 66756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66757 | // MIs[0] Operand 1 |
| 66758 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66759 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66760 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66761 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 66762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_MF2), |
| 66763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66764 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66765 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66768 | GIR_RootConstrainSelectedInstOperands, |
| 66769 | // GIR_Coverage, 57484, |
| 66770 | GIR_EraseRootFromParent_Done, |
| 66771 | // Label 4463: @170278 |
| 66772 | GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(170326), // Rule ID 57485 // |
| 66773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 66774 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 66775 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 66776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66777 | // MIs[0] Operand 1 |
| 66778 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66780 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66781 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 66782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_MF2), |
| 66783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66784 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66785 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66788 | GIR_RootConstrainSelectedInstOperands, |
| 66789 | // GIR_Coverage, 57485, |
| 66790 | GIR_EraseRootFromParent_Done, |
| 66791 | // Label 4464: @170326 |
| 66792 | GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(170374), // Rule ID 57514 // |
| 66793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 66794 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 66795 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 66796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66797 | // MIs[0] Operand 1 |
| 66798 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66800 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66801 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 66802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M1), |
| 66803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66804 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66805 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66808 | GIR_RootConstrainSelectedInstOperands, |
| 66809 | // GIR_Coverage, 57514, |
| 66810 | GIR_EraseRootFromParent_Done, |
| 66811 | // Label 4465: @170374 |
| 66812 | GIM_Try, /*On fail goto*//*Label 4466*/ GIMT_Encode4(170422), // Rule ID 57515 // |
| 66813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 66814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 66815 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 66816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66817 | // MIs[0] Operand 1 |
| 66818 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66819 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66820 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66821 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 66822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M1), |
| 66823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66824 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66825 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66828 | GIR_RootConstrainSelectedInstOperands, |
| 66829 | // GIR_Coverage, 57515, |
| 66830 | GIR_EraseRootFromParent_Done, |
| 66831 | // Label 4466: @170422 |
| 66832 | GIM_Try, /*On fail goto*//*Label 4467*/ GIMT_Encode4(170470), // Rule ID 57594 // |
| 66833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 66834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 66835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 66836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66837 | // MIs[0] Operand 1 |
| 66838 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66839 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66840 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66841 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 66842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M2), |
| 66843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66844 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66845 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66848 | GIR_RootConstrainSelectedInstOperands, |
| 66849 | // GIR_Coverage, 57594, |
| 66850 | GIR_EraseRootFromParent_Done, |
| 66851 | // Label 4467: @170470 |
| 66852 | GIM_Try, /*On fail goto*//*Label 4468*/ GIMT_Encode4(170518), // Rule ID 57595 // |
| 66853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 66854 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 66855 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 66856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66857 | // MIs[0] Operand 1 |
| 66858 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 66859 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66860 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66861 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 66862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M2), |
| 66863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66864 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66865 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66868 | GIR_RootConstrainSelectedInstOperands, |
| 66869 | // GIR_Coverage, 57595, |
| 66870 | GIR_EraseRootFromParent_Done, |
| 66871 | // Label 4468: @170518 |
| 66872 | GIM_Try, /*On fail goto*//*Label 4469*/ GIMT_Encode4(170566), // Rule ID 57784 // |
| 66873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 66875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 66876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66877 | // MIs[0] Operand 1 |
| 66878 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66880 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66881 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 66882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_MF2), |
| 66883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66885 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66888 | GIR_RootConstrainSelectedInstOperands, |
| 66889 | // GIR_Coverage, 57784, |
| 66890 | GIR_EraseRootFromParent_Done, |
| 66891 | // Label 4469: @170566 |
| 66892 | GIM_Try, /*On fail goto*//*Label 4470*/ GIMT_Encode4(170614), // Rule ID 57785 // |
| 66893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 66894 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 66895 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 66896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66897 | // MIs[0] Operand 1 |
| 66898 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66899 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66900 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66901 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 66902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_MF2), |
| 66903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66904 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66905 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 66908 | GIR_RootConstrainSelectedInstOperands, |
| 66909 | // GIR_Coverage, 57785, |
| 66910 | GIR_EraseRootFromParent_Done, |
| 66911 | // Label 4470: @170614 |
| 66912 | GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(170662), // Rule ID 57814 // |
| 66913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 66914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 66915 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 66916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66917 | // MIs[0] Operand 1 |
| 66918 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66920 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66921 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 66922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M1), |
| 66923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66924 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66925 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66928 | GIR_RootConstrainSelectedInstOperands, |
| 66929 | // GIR_Coverage, 57814, |
| 66930 | GIR_EraseRootFromParent_Done, |
| 66931 | // Label 4471: @170662 |
| 66932 | GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(170710), // Rule ID 57815 // |
| 66933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 66934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 66935 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 66936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66937 | // MIs[0] Operand 1 |
| 66938 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66940 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66941 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 66942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M1), |
| 66943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66944 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66945 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 66948 | GIR_RootConstrainSelectedInstOperands, |
| 66949 | // GIR_Coverage, 57815, |
| 66950 | GIR_EraseRootFromParent_Done, |
| 66951 | // Label 4472: @170710 |
| 66952 | GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(170758), // Rule ID 57894 // |
| 66953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 66954 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 66955 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 66956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66957 | // MIs[0] Operand 1 |
| 66958 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66960 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66961 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 66962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M2), |
| 66963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66964 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66965 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66968 | GIR_RootConstrainSelectedInstOperands, |
| 66969 | // GIR_Coverage, 57894, |
| 66970 | GIR_EraseRootFromParent_Done, |
| 66971 | // Label 4473: @170758 |
| 66972 | GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(170806), // Rule ID 57895 // |
| 66973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 66974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 66975 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 66976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66977 | // MIs[0] Operand 1 |
| 66978 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 66979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 66981 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 66982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M2), |
| 66983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 66984 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 66985 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 66986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 66987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 66988 | GIR_RootConstrainSelectedInstOperands, |
| 66989 | // GIR_Coverage, 57895, |
| 66990 | GIR_EraseRootFromParent_Done, |
| 66991 | // Label 4474: @170806 |
| 66992 | GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(170854), // Rule ID 58084 // |
| 66993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 66994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 66995 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 66996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 66997 | // MIs[0] Operand 1 |
| 66998 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 66999 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67000 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67001 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_MF2), |
| 67003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67004 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67005 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67008 | GIR_RootConstrainSelectedInstOperands, |
| 67009 | // GIR_Coverage, 58084, |
| 67010 | GIR_EraseRootFromParent_Done, |
| 67011 | // Label 4475: @170854 |
| 67012 | GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(170902), // Rule ID 58085 // |
| 67013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 67015 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 67016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67017 | // MIs[0] Operand 1 |
| 67018 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67020 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67021 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_MF2), |
| 67023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67024 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67025 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67028 | GIR_RootConstrainSelectedInstOperands, |
| 67029 | // GIR_Coverage, 58085, |
| 67030 | GIR_EraseRootFromParent_Done, |
| 67031 | // Label 4476: @170902 |
| 67032 | GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(170950), // Rule ID 58114 // |
| 67033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67034 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 67035 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 67036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67037 | // MIs[0] Operand 1 |
| 67038 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67040 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67041 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M1), |
| 67043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67044 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67045 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67048 | GIR_RootConstrainSelectedInstOperands, |
| 67049 | // GIR_Coverage, 58114, |
| 67050 | GIR_EraseRootFromParent_Done, |
| 67051 | // Label 4477: @170950 |
| 67052 | GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(170998), // Rule ID 58115 // |
| 67053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 67055 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 67056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67057 | // MIs[0] Operand 1 |
| 67058 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67060 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67061 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M1), |
| 67063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67065 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67068 | GIR_RootConstrainSelectedInstOperands, |
| 67069 | // GIR_Coverage, 58115, |
| 67070 | GIR_EraseRootFromParent_Done, |
| 67071 | // Label 4478: @170998 |
| 67072 | GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(171046), // Rule ID 58194 // |
| 67073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67074 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 67075 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 67076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67077 | // MIs[0] Operand 1 |
| 67078 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67079 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67080 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67081 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M2), |
| 67083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67084 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67085 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67088 | GIR_RootConstrainSelectedInstOperands, |
| 67089 | // GIR_Coverage, 58194, |
| 67090 | GIR_EraseRootFromParent_Done, |
| 67091 | // Label 4479: @171046 |
| 67092 | GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(171094), // Rule ID 58195 // |
| 67093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67094 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 67095 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 67096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67097 | // MIs[0] Operand 1 |
| 67098 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67099 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67100 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67101 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M2), |
| 67103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67104 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67105 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67108 | GIR_RootConstrainSelectedInstOperands, |
| 67109 | // GIR_Coverage, 58195, |
| 67110 | GIR_EraseRootFromParent_Done, |
| 67111 | // Label 4480: @171094 |
| 67112 | GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(171142), // Rule ID 58384 // |
| 67113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67114 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 67115 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 67116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67117 | // MIs[0] Operand 1 |
| 67118 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67120 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67121 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_MF2), |
| 67123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67124 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67125 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67128 | GIR_RootConstrainSelectedInstOperands, |
| 67129 | // GIR_Coverage, 58384, |
| 67130 | GIR_EraseRootFromParent_Done, |
| 67131 | // Label 4481: @171142 |
| 67132 | GIM_Try, /*On fail goto*//*Label 4482*/ GIMT_Encode4(171190), // Rule ID 58385 // |
| 67133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67134 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 67135 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 67136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67137 | // MIs[0] Operand 1 |
| 67138 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67139 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67140 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67141 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_MF2), |
| 67143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67144 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67145 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67148 | GIR_RootConstrainSelectedInstOperands, |
| 67149 | // GIR_Coverage, 58385, |
| 67150 | GIR_EraseRootFromParent_Done, |
| 67151 | // Label 4482: @171190 |
| 67152 | GIM_Try, /*On fail goto*//*Label 4483*/ GIMT_Encode4(171238), // Rule ID 58414 // |
| 67153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 67155 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 67156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67157 | // MIs[0] Operand 1 |
| 67158 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67160 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67161 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M1), |
| 67163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67164 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67165 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67168 | GIR_RootConstrainSelectedInstOperands, |
| 67169 | // GIR_Coverage, 58414, |
| 67170 | GIR_EraseRootFromParent_Done, |
| 67171 | // Label 4483: @171238 |
| 67172 | GIM_Try, /*On fail goto*//*Label 4484*/ GIMT_Encode4(171286), // Rule ID 58415 // |
| 67173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 67175 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 67176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67177 | // MIs[0] Operand 1 |
| 67178 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67180 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67181 | // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M1), |
| 67183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67184 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67185 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67188 | GIR_RootConstrainSelectedInstOperands, |
| 67189 | // GIR_Coverage, 58415, |
| 67190 | GIR_EraseRootFromParent_Done, |
| 67191 | // Label 4484: @171286 |
| 67192 | GIM_Try, /*On fail goto*//*Label 4485*/ GIMT_Encode4(171334), // Rule ID 58494 // |
| 67193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 67195 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 67196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67197 | // MIs[0] Operand 1 |
| 67198 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67200 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67201 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M2), |
| 67203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67204 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67205 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67208 | GIR_RootConstrainSelectedInstOperands, |
| 67209 | // GIR_Coverage, 58494, |
| 67210 | GIR_EraseRootFromParent_Done, |
| 67211 | // Label 4485: @171334 |
| 67212 | GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(171382), // Rule ID 58495 // |
| 67213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 67215 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 67216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67217 | // MIs[0] Operand 1 |
| 67218 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67220 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67221 | // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M2), |
| 67223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67224 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67225 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67228 | GIR_RootConstrainSelectedInstOperands, |
| 67229 | // GIR_Coverage, 58495, |
| 67230 | GIR_EraseRootFromParent_Done, |
| 67231 | // Label 4486: @171382 |
| 67232 | GIM_Reject, |
| 67233 | // Label 4395: @171383 |
| 67234 | GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(171431), // Rule ID 57504 // |
| 67235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67236 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67237 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67239 | // MIs[0] Operand 1 |
| 67240 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67241 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67242 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67243 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M1), |
| 67245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67246 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67247 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67250 | GIR_RootConstrainSelectedInstOperands, |
| 67251 | // GIR_Coverage, 57504, |
| 67252 | GIR_EraseRootFromParent_Done, |
| 67253 | // Label 4487: @171431 |
| 67254 | GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(171479), // Rule ID 57505 // |
| 67255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67256 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67257 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67259 | // MIs[0] Operand 1 |
| 67260 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67261 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67262 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67263 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M1), |
| 67265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67266 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67267 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67270 | GIR_RootConstrainSelectedInstOperands, |
| 67271 | // GIR_Coverage, 57505, |
| 67272 | GIR_EraseRootFromParent_Done, |
| 67273 | // Label 4488: @171479 |
| 67274 | GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(171527), // Rule ID 57564 // |
| 67275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67276 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67277 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67279 | // MIs[0] Operand 1 |
| 67280 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67282 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67283 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M2), |
| 67285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67286 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67287 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67290 | GIR_RootConstrainSelectedInstOperands, |
| 67291 | // GIR_Coverage, 57564, |
| 67292 | GIR_EraseRootFromParent_Done, |
| 67293 | // Label 4489: @171527 |
| 67294 | GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(171575), // Rule ID 57565 // |
| 67295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67296 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67297 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67299 | // MIs[0] Operand 1 |
| 67300 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67301 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67302 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67303 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M2), |
| 67305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67306 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67307 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67310 | GIR_RootConstrainSelectedInstOperands, |
| 67311 | // GIR_Coverage, 57565, |
| 67312 | GIR_EraseRootFromParent_Done, |
| 67313 | // Label 4490: @171575 |
| 67314 | GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(171623), // Rule ID 57604 // |
| 67315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67316 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67317 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67319 | // MIs[0] Operand 1 |
| 67320 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67321 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67322 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67323 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M4), |
| 67325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67326 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67327 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67330 | GIR_RootConstrainSelectedInstOperands, |
| 67331 | // GIR_Coverage, 57604, |
| 67332 | GIR_EraseRootFromParent_Done, |
| 67333 | // Label 4491: @171623 |
| 67334 | GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(171671), // Rule ID 57605 // |
| 67335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67336 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67337 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67339 | // MIs[0] Operand 1 |
| 67340 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67341 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67342 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67343 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M4), |
| 67345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67346 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67347 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67350 | GIR_RootConstrainSelectedInstOperands, |
| 67351 | // GIR_Coverage, 57605, |
| 67352 | GIR_EraseRootFromParent_Done, |
| 67353 | // Label 4492: @171671 |
| 67354 | GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(171719), // Rule ID 57804 // |
| 67355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67356 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67357 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67359 | // MIs[0] Operand 1 |
| 67360 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67362 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67363 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M1), |
| 67365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67366 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67367 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67370 | GIR_RootConstrainSelectedInstOperands, |
| 67371 | // GIR_Coverage, 57804, |
| 67372 | GIR_EraseRootFromParent_Done, |
| 67373 | // Label 4493: @171719 |
| 67374 | GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(171767), // Rule ID 57805 // |
| 67375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67376 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67377 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67379 | // MIs[0] Operand 1 |
| 67380 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67381 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67382 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67383 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M1), |
| 67385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67386 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67387 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67390 | GIR_RootConstrainSelectedInstOperands, |
| 67391 | // GIR_Coverage, 57805, |
| 67392 | GIR_EraseRootFromParent_Done, |
| 67393 | // Label 4494: @171767 |
| 67394 | GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(171815), // Rule ID 57864 // |
| 67395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67399 | // MIs[0] Operand 1 |
| 67400 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67402 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67403 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M2), |
| 67405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67407 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67410 | GIR_RootConstrainSelectedInstOperands, |
| 67411 | // GIR_Coverage, 57864, |
| 67412 | GIR_EraseRootFromParent_Done, |
| 67413 | // Label 4495: @171815 |
| 67414 | GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(171863), // Rule ID 57865 // |
| 67415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67419 | // MIs[0] Operand 1 |
| 67420 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67421 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67422 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67423 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M2), |
| 67425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67426 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67427 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67430 | GIR_RootConstrainSelectedInstOperands, |
| 67431 | // GIR_Coverage, 57865, |
| 67432 | GIR_EraseRootFromParent_Done, |
| 67433 | // Label 4496: @171863 |
| 67434 | GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(171911), // Rule ID 57904 // |
| 67435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67437 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67439 | // MIs[0] Operand 1 |
| 67440 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67442 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67443 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M4), |
| 67445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67447 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67450 | GIR_RootConstrainSelectedInstOperands, |
| 67451 | // GIR_Coverage, 57904, |
| 67452 | GIR_EraseRootFromParent_Done, |
| 67453 | // Label 4497: @171911 |
| 67454 | GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(171959), // Rule ID 57905 // |
| 67455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67459 | // MIs[0] Operand 1 |
| 67460 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67462 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67463 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M4), |
| 67465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67467 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67470 | GIR_RootConstrainSelectedInstOperands, |
| 67471 | // GIR_Coverage, 57905, |
| 67472 | GIR_EraseRootFromParent_Done, |
| 67473 | // Label 4498: @171959 |
| 67474 | GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(172007), // Rule ID 58104 // |
| 67475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67476 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67477 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67479 | // MIs[0] Operand 1 |
| 67480 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67481 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67482 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67483 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M1), |
| 67485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67486 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67487 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67490 | GIR_RootConstrainSelectedInstOperands, |
| 67491 | // GIR_Coverage, 58104, |
| 67492 | GIR_EraseRootFromParent_Done, |
| 67493 | // Label 4499: @172007 |
| 67494 | GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(172055), // Rule ID 58105 // |
| 67495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67497 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67499 | // MIs[0] Operand 1 |
| 67500 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67502 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67503 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M1), |
| 67505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67507 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67510 | GIR_RootConstrainSelectedInstOperands, |
| 67511 | // GIR_Coverage, 58105, |
| 67512 | GIR_EraseRootFromParent_Done, |
| 67513 | // Label 4500: @172055 |
| 67514 | GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(172103), // Rule ID 58164 // |
| 67515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67516 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67517 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67519 | // MIs[0] Operand 1 |
| 67520 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67522 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67523 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M2), |
| 67525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67526 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67527 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67530 | GIR_RootConstrainSelectedInstOperands, |
| 67531 | // GIR_Coverage, 58164, |
| 67532 | GIR_EraseRootFromParent_Done, |
| 67533 | // Label 4501: @172103 |
| 67534 | GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(172151), // Rule ID 58165 // |
| 67535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67537 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67539 | // MIs[0] Operand 1 |
| 67540 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67541 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67542 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67543 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M2), |
| 67545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67546 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67547 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67550 | GIR_RootConstrainSelectedInstOperands, |
| 67551 | // GIR_Coverage, 58165, |
| 67552 | GIR_EraseRootFromParent_Done, |
| 67553 | // Label 4502: @172151 |
| 67554 | GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(172199), // Rule ID 58204 // |
| 67555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67556 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67557 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67559 | // MIs[0] Operand 1 |
| 67560 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67562 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67563 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M4), |
| 67565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67566 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67567 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67570 | GIR_RootConstrainSelectedInstOperands, |
| 67571 | // GIR_Coverage, 58204, |
| 67572 | GIR_EraseRootFromParent_Done, |
| 67573 | // Label 4503: @172199 |
| 67574 | GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(172247), // Rule ID 58205 // |
| 67575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67577 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67579 | // MIs[0] Operand 1 |
| 67580 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67582 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67583 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M4), |
| 67585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67586 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67587 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67590 | GIR_RootConstrainSelectedInstOperands, |
| 67591 | // GIR_Coverage, 58205, |
| 67592 | GIR_EraseRootFromParent_Done, |
| 67593 | // Label 4504: @172247 |
| 67594 | GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(172295), // Rule ID 58404 // |
| 67595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67596 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67597 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67599 | // MIs[0] Operand 1 |
| 67600 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67601 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67602 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67603 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M1), |
| 67605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67606 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67607 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67610 | GIR_RootConstrainSelectedInstOperands, |
| 67611 | // GIR_Coverage, 58404, |
| 67612 | GIR_EraseRootFromParent_Done, |
| 67613 | // Label 4505: @172295 |
| 67614 | GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(172343), // Rule ID 58405 // |
| 67615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 67617 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 67618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67619 | // MIs[0] Operand 1 |
| 67620 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67621 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67622 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67623 | // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M1), |
| 67625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67626 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67627 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67630 | GIR_RootConstrainSelectedInstOperands, |
| 67631 | // GIR_Coverage, 58405, |
| 67632 | GIR_EraseRootFromParent_Done, |
| 67633 | // Label 4506: @172343 |
| 67634 | GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(172391), // Rule ID 58464 // |
| 67635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67637 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67639 | // MIs[0] Operand 1 |
| 67640 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67642 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67643 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M2), |
| 67645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67646 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67647 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67650 | GIR_RootConstrainSelectedInstOperands, |
| 67651 | // GIR_Coverage, 58464, |
| 67652 | GIR_EraseRootFromParent_Done, |
| 67653 | // Label 4507: @172391 |
| 67654 | GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(172439), // Rule ID 58465 // |
| 67655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 67657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 67658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67659 | // MIs[0] Operand 1 |
| 67660 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67662 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67663 | // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M2), |
| 67665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67667 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67670 | GIR_RootConstrainSelectedInstOperands, |
| 67671 | // GIR_Coverage, 58465, |
| 67672 | GIR_EraseRootFromParent_Done, |
| 67673 | // Label 4508: @172439 |
| 67674 | GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(172487), // Rule ID 58504 // |
| 67675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67676 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67679 | // MIs[0] Operand 1 |
| 67680 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67682 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67683 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M4), |
| 67685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67687 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67690 | GIR_RootConstrainSelectedInstOperands, |
| 67691 | // GIR_Coverage, 58504, |
| 67692 | GIR_EraseRootFromParent_Done, |
| 67693 | // Label 4509: @172487 |
| 67694 | GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(172535), // Rule ID 58505 // |
| 67695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 67697 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 67698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67699 | // MIs[0] Operand 1 |
| 67700 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 67701 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67702 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67703 | // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M4), |
| 67705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67706 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67707 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67710 | GIR_RootConstrainSelectedInstOperands, |
| 67711 | // GIR_Coverage, 58505, |
| 67712 | GIR_EraseRootFromParent_Done, |
| 67713 | // Label 4510: @172535 |
| 67714 | GIM_Reject, |
| 67715 | // Label 4396: @172536 |
| 67716 | GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(172584), // Rule ID 57534 // |
| 67717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67718 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 67719 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 67720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67721 | // MIs[0] Operand 1 |
| 67722 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67724 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67725 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M2), |
| 67727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67728 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67729 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67732 | GIR_RootConstrainSelectedInstOperands, |
| 67733 | // GIR_Coverage, 57534, |
| 67734 | GIR_EraseRootFromParent_Done, |
| 67735 | // Label 4511: @172584 |
| 67736 | GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(172632), // Rule ID 57535 // |
| 67737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67738 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 67739 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 67740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67741 | // MIs[0] Operand 1 |
| 67742 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67743 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67744 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67745 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M2), |
| 67747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67748 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67749 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67752 | GIR_RootConstrainSelectedInstOperands, |
| 67753 | // GIR_Coverage, 57535, |
| 67754 | GIR_EraseRootFromParent_Done, |
| 67755 | // Label 4512: @172632 |
| 67756 | GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(172680), // Rule ID 57574 // |
| 67757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67758 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 67759 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 67760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67761 | // MIs[0] Operand 1 |
| 67762 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67763 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67764 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67765 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M4), |
| 67767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67768 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67769 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67772 | GIR_RootConstrainSelectedInstOperands, |
| 67773 | // GIR_Coverage, 57574, |
| 67774 | GIR_EraseRootFromParent_Done, |
| 67775 | // Label 4513: @172680 |
| 67776 | GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(172728), // Rule ID 57575 // |
| 67777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67778 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 67779 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 67780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67781 | // MIs[0] Operand 1 |
| 67782 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67783 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67784 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67785 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M4), |
| 67787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67788 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67789 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67792 | GIR_RootConstrainSelectedInstOperands, |
| 67793 | // GIR_Coverage, 57575, |
| 67794 | GIR_EraseRootFromParent_Done, |
| 67795 | // Label 4514: @172728 |
| 67796 | GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(172776), // Rule ID 57614 // |
| 67797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67798 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 67799 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 67800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67801 | // MIs[0] Operand 1 |
| 67802 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67804 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67805 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M8), |
| 67807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67808 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67809 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67812 | GIR_RootConstrainSelectedInstOperands, |
| 67813 | // GIR_Coverage, 57614, |
| 67814 | GIR_EraseRootFromParent_Done, |
| 67815 | // Label 4515: @172776 |
| 67816 | GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(172824), // Rule ID 57615 // |
| 67817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67818 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 67819 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 67820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67821 | // MIs[0] Operand 1 |
| 67822 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 67823 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67824 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67825 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M8), |
| 67827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67828 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67829 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67832 | GIR_RootConstrainSelectedInstOperands, |
| 67833 | // GIR_Coverage, 57615, |
| 67834 | GIR_EraseRootFromParent_Done, |
| 67835 | // Label 4516: @172824 |
| 67836 | GIM_Try, /*On fail goto*//*Label 4517*/ GIMT_Encode4(172872), // Rule ID 57834 // |
| 67837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 67839 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 67840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67841 | // MIs[0] Operand 1 |
| 67842 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67844 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67845 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M2), |
| 67847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67848 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67849 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67852 | GIR_RootConstrainSelectedInstOperands, |
| 67853 | // GIR_Coverage, 57834, |
| 67854 | GIR_EraseRootFromParent_Done, |
| 67855 | // Label 4517: @172872 |
| 67856 | GIM_Try, /*On fail goto*//*Label 4518*/ GIMT_Encode4(172920), // Rule ID 57835 // |
| 67857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 67859 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 67860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67861 | // MIs[0] Operand 1 |
| 67862 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67863 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67864 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67865 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M2), |
| 67867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67868 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67869 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67872 | GIR_RootConstrainSelectedInstOperands, |
| 67873 | // GIR_Coverage, 57835, |
| 67874 | GIR_EraseRootFromParent_Done, |
| 67875 | // Label 4518: @172920 |
| 67876 | GIM_Try, /*On fail goto*//*Label 4519*/ GIMT_Encode4(172968), // Rule ID 57874 // |
| 67877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67878 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 67879 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 67880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67881 | // MIs[0] Operand 1 |
| 67882 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67883 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67884 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67885 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 67886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M4), |
| 67887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67888 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67889 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67892 | GIR_RootConstrainSelectedInstOperands, |
| 67893 | // GIR_Coverage, 57874, |
| 67894 | GIR_EraseRootFromParent_Done, |
| 67895 | // Label 4519: @172968 |
| 67896 | GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(173016), // Rule ID 57875 // |
| 67897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 67898 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 67899 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 67900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67901 | // MIs[0] Operand 1 |
| 67902 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67903 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67904 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 67905 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 67906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M4), |
| 67907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67908 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67909 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67912 | GIR_RootConstrainSelectedInstOperands, |
| 67913 | // GIR_Coverage, 57875, |
| 67914 | GIR_EraseRootFromParent_Done, |
| 67915 | // Label 4520: @173016 |
| 67916 | GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(173064), // Rule ID 57914 // |
| 67917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 67918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 67919 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 67920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67921 | // MIs[0] Operand 1 |
| 67922 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67924 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67925 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 67926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M8), |
| 67927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67928 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67929 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67932 | GIR_RootConstrainSelectedInstOperands, |
| 67933 | // GIR_Coverage, 57914, |
| 67934 | GIR_EraseRootFromParent_Done, |
| 67935 | // Label 4521: @173064 |
| 67936 | GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(173112), // Rule ID 57915 // |
| 67937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 67938 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 67939 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 67940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67941 | // MIs[0] Operand 1 |
| 67942 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 67943 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67944 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 67945 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 67946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M8), |
| 67947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67948 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67949 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 67952 | GIR_RootConstrainSelectedInstOperands, |
| 67953 | // GIR_Coverage, 57915, |
| 67954 | GIR_EraseRootFromParent_Done, |
| 67955 | // Label 4522: @173112 |
| 67956 | GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(173160), // Rule ID 58134 // |
| 67957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 67958 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 67959 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 67960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67961 | // MIs[0] Operand 1 |
| 67962 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67963 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67964 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67965 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 67966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M2), |
| 67967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67968 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67969 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67972 | GIR_RootConstrainSelectedInstOperands, |
| 67973 | // GIR_Coverage, 58134, |
| 67974 | GIR_EraseRootFromParent_Done, |
| 67975 | // Label 4523: @173160 |
| 67976 | GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(173208), // Rule ID 58135 // |
| 67977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 67978 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 67979 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 67980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 67981 | // MIs[0] Operand 1 |
| 67982 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 67983 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67984 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 67985 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 67986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M2), |
| 67987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 67988 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 67989 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 67990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 67991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67992 | GIR_RootConstrainSelectedInstOperands, |
| 67993 | // GIR_Coverage, 58135, |
| 67994 | GIR_EraseRootFromParent_Done, |
| 67995 | // Label 4524: @173208 |
| 67996 | GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(173256), // Rule ID 58174 // |
| 67997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 67998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 67999 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 68000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68001 | // MIs[0] Operand 1 |
| 68002 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68003 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68004 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68005 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 68006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M4), |
| 68007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68008 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68009 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68012 | GIR_RootConstrainSelectedInstOperands, |
| 68013 | // GIR_Coverage, 58174, |
| 68014 | GIR_EraseRootFromParent_Done, |
| 68015 | // Label 4525: @173256 |
| 68016 | GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(173304), // Rule ID 58175 // |
| 68017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 68018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 68019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 68020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68021 | // MIs[0] Operand 1 |
| 68022 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68025 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 68026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M4), |
| 68027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68028 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68029 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68032 | GIR_RootConstrainSelectedInstOperands, |
| 68033 | // GIR_Coverage, 58175, |
| 68034 | GIR_EraseRootFromParent_Done, |
| 68035 | // Label 4526: @173304 |
| 68036 | GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(173352), // Rule ID 58214 // |
| 68037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 68038 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 68039 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 68040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68041 | // MIs[0] Operand 1 |
| 68042 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68044 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68045 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 68046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M8), |
| 68047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68049 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 68052 | GIR_RootConstrainSelectedInstOperands, |
| 68053 | // GIR_Coverage, 58214, |
| 68054 | GIR_EraseRootFromParent_Done, |
| 68055 | // Label 4527: @173352 |
| 68056 | GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(173400), // Rule ID 58215 // |
| 68057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 68058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 68059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 68060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68061 | // MIs[0] Operand 1 |
| 68062 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68063 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68064 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68065 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 68066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M8), |
| 68067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68068 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68069 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 68072 | GIR_RootConstrainSelectedInstOperands, |
| 68073 | // GIR_Coverage, 58215, |
| 68074 | GIR_EraseRootFromParent_Done, |
| 68075 | // Label 4528: @173400 |
| 68076 | GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(173448), // Rule ID 58434 // |
| 68077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 68079 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 68080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68081 | // MIs[0] Operand 1 |
| 68082 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68083 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 68084 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 68085 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M2), |
| 68087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68089 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68092 | GIR_RootConstrainSelectedInstOperands, |
| 68093 | // GIR_Coverage, 58434, |
| 68094 | GIR_EraseRootFromParent_Done, |
| 68095 | // Label 4529: @173448 |
| 68096 | GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(173496), // Rule ID 58435 // |
| 68097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68098 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 68099 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 68100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68101 | // MIs[0] Operand 1 |
| 68102 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 68104 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 68105 | // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M2), |
| 68107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68108 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68109 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68112 | GIR_RootConstrainSelectedInstOperands, |
| 68113 | // GIR_Coverage, 58435, |
| 68114 | GIR_EraseRootFromParent_Done, |
| 68115 | // Label 4530: @173496 |
| 68116 | GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(173544), // Rule ID 58474 // |
| 68117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 68118 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 68119 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 68120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68121 | // MIs[0] Operand 1 |
| 68122 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68124 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68125 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 68126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M4), |
| 68127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68128 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68129 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68132 | GIR_RootConstrainSelectedInstOperands, |
| 68133 | // GIR_Coverage, 58474, |
| 68134 | GIR_EraseRootFromParent_Done, |
| 68135 | // Label 4531: @173544 |
| 68136 | GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(173592), // Rule ID 58475 // |
| 68137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 68138 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 68139 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 68140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68141 | // MIs[0] Operand 1 |
| 68142 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68143 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68144 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68145 | // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 68146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M4), |
| 68147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68148 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68149 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68152 | GIR_RootConstrainSelectedInstOperands, |
| 68153 | // GIR_Coverage, 58475, |
| 68154 | GIR_EraseRootFromParent_Done, |
| 68155 | // Label 4532: @173592 |
| 68156 | GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(173640), // Rule ID 58514 // |
| 68157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 68158 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 68159 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 68160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68161 | // MIs[0] Operand 1 |
| 68162 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68164 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68165 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 68166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M8), |
| 68167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68168 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68169 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 68172 | GIR_RootConstrainSelectedInstOperands, |
| 68173 | // GIR_Coverage, 58514, |
| 68174 | GIR_EraseRootFromParent_Done, |
| 68175 | // Label 4533: @173640 |
| 68176 | GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(173688), // Rule ID 58515 // |
| 68177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 68178 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 68179 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 68180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68181 | // MIs[0] Operand 1 |
| 68182 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68183 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68184 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68185 | // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 68186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M8), |
| 68187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68188 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68189 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 68192 | GIR_RootConstrainSelectedInstOperands, |
| 68193 | // GIR_Coverage, 58515, |
| 68194 | GIR_EraseRootFromParent_Done, |
| 68195 | // Label 4534: @173688 |
| 68196 | GIM_Reject, |
| 68197 | // Label 4397: @173689 |
| 68198 | GIM_Try, /*On fail goto*//*Label 4535*/ GIMT_Encode4(173737), // Rule ID 57544 // |
| 68199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68200 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68201 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68203 | // MIs[0] Operand 1 |
| 68204 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 68205 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68206 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68207 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M4), |
| 68209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68210 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68211 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68214 | GIR_RootConstrainSelectedInstOperands, |
| 68215 | // GIR_Coverage, 57544, |
| 68216 | GIR_EraseRootFromParent_Done, |
| 68217 | // Label 4535: @173737 |
| 68218 | GIM_Try, /*On fail goto*//*Label 4536*/ GIMT_Encode4(173785), // Rule ID 57545 // |
| 68219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68220 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68221 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68223 | // MIs[0] Operand 1 |
| 68224 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 68225 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68226 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68227 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M4), |
| 68229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68230 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68231 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68234 | GIR_RootConstrainSelectedInstOperands, |
| 68235 | // GIR_Coverage, 57545, |
| 68236 | GIR_EraseRootFromParent_Done, |
| 68237 | // Label 4536: @173785 |
| 68238 | GIM_Try, /*On fail goto*//*Label 4537*/ GIMT_Encode4(173833), // Rule ID 57584 // |
| 68239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 68240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68241 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68243 | // MIs[0] Operand 1 |
| 68244 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 68245 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68246 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68247 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 68248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M8), |
| 68249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68250 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68251 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68254 | GIR_RootConstrainSelectedInstOperands, |
| 68255 | // GIR_Coverage, 57584, |
| 68256 | GIR_EraseRootFromParent_Done, |
| 68257 | // Label 4537: @173833 |
| 68258 | GIM_Try, /*On fail goto*//*Label 4538*/ GIMT_Encode4(173881), // Rule ID 57585 // |
| 68259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 68260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68261 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68263 | // MIs[0] Operand 1 |
| 68264 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 68265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68266 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68267 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 68268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M8), |
| 68269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68270 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68271 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68274 | GIR_RootConstrainSelectedInstOperands, |
| 68275 | // GIR_Coverage, 57585, |
| 68276 | GIR_EraseRootFromParent_Done, |
| 68277 | // Label 4538: @173881 |
| 68278 | GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(173929), // Rule ID 57844 // |
| 68279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68280 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68281 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68283 | // MIs[0] Operand 1 |
| 68284 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 68285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68286 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68287 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M4), |
| 68289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68290 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68291 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68294 | GIR_RootConstrainSelectedInstOperands, |
| 68295 | // GIR_Coverage, 57844, |
| 68296 | GIR_EraseRootFromParent_Done, |
| 68297 | // Label 4539: @173929 |
| 68298 | GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(173977), // Rule ID 57845 // |
| 68299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68300 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68301 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68303 | // MIs[0] Operand 1 |
| 68304 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 68305 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68306 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68307 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M4), |
| 68309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68310 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68311 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68314 | GIR_RootConstrainSelectedInstOperands, |
| 68315 | // GIR_Coverage, 57845, |
| 68316 | GIR_EraseRootFromParent_Done, |
| 68317 | // Label 4540: @173977 |
| 68318 | GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(174025), // Rule ID 57884 // |
| 68319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 68320 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68321 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68323 | // MIs[0] Operand 1 |
| 68324 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 68325 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68326 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68327 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 68328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M8), |
| 68329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68330 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68331 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68334 | GIR_RootConstrainSelectedInstOperands, |
| 68335 | // GIR_Coverage, 57884, |
| 68336 | GIR_EraseRootFromParent_Done, |
| 68337 | // Label 4541: @174025 |
| 68338 | GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(174073), // Rule ID 57885 // |
| 68339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 68340 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68341 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68343 | // MIs[0] Operand 1 |
| 68344 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 68345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68346 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68347 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 68348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M8), |
| 68349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68350 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68351 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68354 | GIR_RootConstrainSelectedInstOperands, |
| 68355 | // GIR_Coverage, 57885, |
| 68356 | GIR_EraseRootFromParent_Done, |
| 68357 | // Label 4542: @174073 |
| 68358 | GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(174121), // Rule ID 58144 // |
| 68359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68361 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68363 | // MIs[0] Operand 1 |
| 68364 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68365 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68366 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68367 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M4), |
| 68369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68371 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68374 | GIR_RootConstrainSelectedInstOperands, |
| 68375 | // GIR_Coverage, 58144, |
| 68376 | GIR_EraseRootFromParent_Done, |
| 68377 | // Label 4543: @174121 |
| 68378 | GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(174169), // Rule ID 58145 // |
| 68379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68380 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68381 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68383 | // MIs[0] Operand 1 |
| 68384 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68385 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68386 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68387 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M4), |
| 68389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68390 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68391 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68394 | GIR_RootConstrainSelectedInstOperands, |
| 68395 | // GIR_Coverage, 58145, |
| 68396 | GIR_EraseRootFromParent_Done, |
| 68397 | // Label 4544: @174169 |
| 68398 | GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(174217), // Rule ID 58184 // |
| 68399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 68400 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68401 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68403 | // MIs[0] Operand 1 |
| 68404 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68405 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68406 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68407 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 68408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M8), |
| 68409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68410 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68411 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68414 | GIR_RootConstrainSelectedInstOperands, |
| 68415 | // GIR_Coverage, 58184, |
| 68416 | GIR_EraseRootFromParent_Done, |
| 68417 | // Label 4545: @174217 |
| 68418 | GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(174265), // Rule ID 58185 // |
| 68419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 68420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68421 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68423 | // MIs[0] Operand 1 |
| 68424 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68425 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68426 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68427 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 68428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M8), |
| 68429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68430 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68431 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68434 | GIR_RootConstrainSelectedInstOperands, |
| 68435 | // GIR_Coverage, 58185, |
| 68436 | GIR_EraseRootFromParent_Done, |
| 68437 | // Label 4546: @174265 |
| 68438 | GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(174313), // Rule ID 58444 // |
| 68439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68441 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68443 | // MIs[0] Operand 1 |
| 68444 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68445 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68446 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68447 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M4), |
| 68449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68450 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68451 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68454 | GIR_RootConstrainSelectedInstOperands, |
| 68455 | // GIR_Coverage, 58444, |
| 68456 | GIR_EraseRootFromParent_Done, |
| 68457 | // Label 4547: @174313 |
| 68458 | GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(174361), // Rule ID 58445 // |
| 68459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 68461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 68462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68463 | // MIs[0] Operand 1 |
| 68464 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68465 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68466 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 68467 | // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M4), |
| 68469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68470 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68471 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68474 | GIR_RootConstrainSelectedInstOperands, |
| 68475 | // GIR_Coverage, 58445, |
| 68476 | GIR_EraseRootFromParent_Done, |
| 68477 | // Label 4548: @174361 |
| 68478 | GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(174409), // Rule ID 58484 // |
| 68479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 68480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68481 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68483 | // MIs[0] Operand 1 |
| 68484 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68485 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68486 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68487 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 68488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M8), |
| 68489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68490 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68491 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68494 | GIR_RootConstrainSelectedInstOperands, |
| 68495 | // GIR_Coverage, 58484, |
| 68496 | GIR_EraseRootFromParent_Done, |
| 68497 | // Label 4549: @174409 |
| 68498 | GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(174457), // Rule ID 58485 // |
| 68499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 68500 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 68501 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 68502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68503 | // MIs[0] Operand 1 |
| 68504 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68505 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68506 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68507 | // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 68508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M8), |
| 68509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68510 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68511 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 68514 | GIR_RootConstrainSelectedInstOperands, |
| 68515 | // GIR_Coverage, 58485, |
| 68516 | GIR_EraseRootFromParent_Done, |
| 68517 | // Label 4550: @174457 |
| 68518 | GIM_Reject, |
| 68519 | // Label 4398: @174458 |
| 68520 | GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(174778), |
| 68521 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 68522 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 68523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68524 | GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(174511), // Rule ID 57554 // |
| 68525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68526 | // MIs[0] Operand 1 |
| 68527 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 68528 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68529 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68530 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M8), |
| 68532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68533 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68534 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68537 | GIR_RootConstrainSelectedInstOperands, |
| 68538 | // GIR_Coverage, 57554, |
| 68539 | GIR_EraseRootFromParent_Done, |
| 68540 | // Label 4552: @174511 |
| 68541 | GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(174549), // Rule ID 57555 // |
| 68542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68543 | // MIs[0] Operand 1 |
| 68544 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 68545 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68546 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68547 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOEQ:{ *:[Other] }) => (PseudoVMFEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFEQ_VV_M8), |
| 68549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68550 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68551 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68554 | GIR_RootConstrainSelectedInstOperands, |
| 68555 | // GIR_Coverage, 57555, |
| 68556 | GIR_EraseRootFromParent_Done, |
| 68557 | // Label 4553: @174549 |
| 68558 | GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(174587), // Rule ID 57854 // |
| 68559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68560 | // MIs[0] Operand 1 |
| 68561 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 68562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68563 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68564 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M8), |
| 68566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68567 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68568 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68571 | GIR_RootConstrainSelectedInstOperands, |
| 68572 | // GIR_Coverage, 57854, |
| 68573 | GIR_EraseRootFromParent_Done, |
| 68574 | // Label 4554: @174587 |
| 68575 | GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(174625), // Rule ID 57855 // |
| 68576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68577 | // MIs[0] Operand 1 |
| 68578 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 68579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68580 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68581 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETUNE:{ *:[Other] }) => (PseudoVMFNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFNE_VV_M8), |
| 68583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68584 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68585 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68588 | GIR_RootConstrainSelectedInstOperands, |
| 68589 | // GIR_Coverage, 57855, |
| 68590 | GIR_EraseRootFromParent_Done, |
| 68591 | // Label 4555: @174625 |
| 68592 | GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(174663), // Rule ID 58154 // |
| 68593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68594 | // MIs[0] Operand 1 |
| 68595 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68596 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68597 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68598 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M8), |
| 68600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68601 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68602 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68605 | GIR_RootConstrainSelectedInstOperands, |
| 68606 | // GIR_Coverage, 58154, |
| 68607 | GIR_EraseRootFromParent_Done, |
| 68608 | // Label 4556: @174663 |
| 68609 | GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(174701), // Rule ID 58155 // |
| 68610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68611 | // MIs[0] Operand 1 |
| 68612 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 68613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68614 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68615 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLT:{ *:[Other] }) => (PseudoVMFLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLT_VV_M8), |
| 68617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68618 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68619 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68622 | GIR_RootConstrainSelectedInstOperands, |
| 68623 | // GIR_Coverage, 58155, |
| 68624 | GIR_EraseRootFromParent_Done, |
| 68625 | // Label 4557: @174701 |
| 68626 | GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(174739), // Rule ID 58454 // |
| 68627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 68628 | // MIs[0] Operand 1 |
| 68629 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68630 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68631 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68632 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M8), |
| 68634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68635 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68636 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68639 | GIR_RootConstrainSelectedInstOperands, |
| 68640 | // GIR_Coverage, 58454, |
| 68641 | GIR_EraseRootFromParent_Done, |
| 68642 | // Label 4558: @174739 |
| 68643 | GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(174777), // Rule ID 58455 // |
| 68644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 68645 | // MIs[0] Operand 1 |
| 68646 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 68647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68648 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 68649 | // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLE:{ *:[Other] }) => (PseudoVMFLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 68650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMFLE_VV_M8), |
| 68651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68652 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68653 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68656 | GIR_RootConstrainSelectedInstOperands, |
| 68657 | // GIR_Coverage, 58455, |
| 68658 | GIR_EraseRootFromParent_Done, |
| 68659 | // Label 4559: @174777 |
| 68660 | GIM_Reject, |
| 68661 | // Label 4551: @174778 |
| 68662 | GIM_Reject, |
| 68663 | // Label 4399: @174779 |
| 68664 | GIM_Reject, |
| 68665 | // Label 46: @174780 |
| 68666 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 4584*/ GIMT_Encode4(181509), |
| 68667 | /*GILLT_s32*//*Label 4560*/ GIMT_Encode4(174915), |
| 68668 | /*GILLT_s64*//*Label 4561*/ GIMT_Encode4(175354), GIMT_Encode4(0), |
| 68669 | /*GILLT_nxv1s8*//*Label 4562*/ GIMT_Encode4(175473), |
| 68670 | /*GILLT_nxv1s16*//*Label 4563*/ GIMT_Encode4(175629), |
| 68671 | /*GILLT_nxv1s32*//*Label 4564*/ GIMT_Encode4(176033), |
| 68672 | /*GILLT_nxv1s64*//*Label 4565*/ GIMT_Encode4(176313), GIMT_Encode4(0), |
| 68673 | /*GILLT_nxv2s8*//*Label 4566*/ GIMT_Encode4(176593), |
| 68674 | /*GILLT_nxv2s16*//*Label 4567*/ GIMT_Encode4(176749), |
| 68675 | /*GILLT_nxv2s32*//*Label 4568*/ GIMT_Encode4(177153), |
| 68676 | /*GILLT_nxv2s64*//*Label 4569*/ GIMT_Encode4(177433), GIMT_Encode4(0), |
| 68677 | /*GILLT_nxv4s8*//*Label 4570*/ GIMT_Encode4(177713), |
| 68678 | /*GILLT_nxv4s16*//*Label 4571*/ GIMT_Encode4(177869), |
| 68679 | /*GILLT_nxv4s32*//*Label 4572*/ GIMT_Encode4(178273), |
| 68680 | /*GILLT_nxv4s64*//*Label 4573*/ GIMT_Encode4(178553), GIMT_Encode4(0), |
| 68681 | /*GILLT_nxv8s8*//*Label 4574*/ GIMT_Encode4(178833), |
| 68682 | /*GILLT_nxv8s16*//*Label 4575*/ GIMT_Encode4(178989), |
| 68683 | /*GILLT_nxv8s32*//*Label 4576*/ GIMT_Encode4(179393), |
| 68684 | /*GILLT_nxv8s64*//*Label 4577*/ GIMT_Encode4(179673), GIMT_Encode4(0), |
| 68685 | /*GILLT_nxv16s8*//*Label 4578*/ GIMT_Encode4(179953), |
| 68686 | /*GILLT_nxv16s16*//*Label 4579*/ GIMT_Encode4(180109), |
| 68687 | /*GILLT_nxv16s32*//*Label 4580*/ GIMT_Encode4(180513), GIMT_Encode4(0), |
| 68688 | /*GILLT_nxv32s8*//*Label 4581*/ GIMT_Encode4(180793), |
| 68689 | /*GILLT_nxv32s16*//*Label 4582*/ GIMT_Encode4(180949), GIMT_Encode4(0), |
| 68690 | /*GILLT_nxv64s8*//*Label 4583*/ GIMT_Encode4(181353), |
| 68691 | // Label 4560: @174915 |
| 68692 | GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(174965), // Rule ID 63045 // |
| 68693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_HwMode1), |
| 68694 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 68695 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68696 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68698 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68699 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 68700 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68701 | // (select:{ *:[i32] } GPR:{ *:[i32] }:$cond, 0:{ *:[i32] }, GPR:{ *:[i32] }:$b) => (TH_MVNEZ:{ *:[i32] } GPR:{ *:[i32] }:$b, X0:{ *:[i32] }, GPR:{ *:[i32] }:$cond) |
| 68702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVNEZ), |
| 68703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68704 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68705 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68706 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68707 | GIR_RootConstrainSelectedInstOperands, |
| 68708 | // GIR_Coverage, 63045, |
| 68709 | GIR_EraseRootFromParent_Done, |
| 68710 | // Label 4585: @174965 |
| 68711 | GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(175015), // Rule ID 63302 // |
| 68712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode0), |
| 68713 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 68714 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68715 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68718 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 68719 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68720 | // (select:{ *:[i32] } GPR:{ *:[i64] }:$cond, 0:{ *:[i32] }, GPR:{ *:[i32] }:$b) => (TH_MVNEZ:{ *:[i32] } GPR:{ *:[i32] }:$b, X0:{ *:[i64] }, GPR:{ *:[i64] }:$cond) |
| 68721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVNEZ), |
| 68722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68723 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68724 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68725 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68726 | GIR_RootConstrainSelectedInstOperands, |
| 68727 | // GIR_Coverage, 63302, |
| 68728 | GIR_EraseRootFromParent_Done, |
| 68729 | // Label 4586: @175015 |
| 68730 | GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(175065), // Rule ID 63303 // |
| 68731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode1), |
| 68732 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 68733 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68734 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68737 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 68738 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68739 | // (select:{ *:[i32] } GPR:{ *:[i32] }:$cond, 0:{ *:[i32] }, GPR:{ *:[i32] }:$b) => (TH_MVNEZ:{ *:[i32] } GPR:{ *:[i32] }:$b, X0:{ *:[i32] }, GPR:{ *:[i32] }:$cond) |
| 68740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVNEZ), |
| 68741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68742 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68743 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68744 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68745 | GIR_RootConstrainSelectedInstOperands, |
| 68746 | // GIR_Coverage, 63303, |
| 68747 | GIR_EraseRootFromParent_Done, |
| 68748 | // Label 4587: @175065 |
| 68749 | GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(175115), // Rule ID 63043 // |
| 68750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_HwMode1), |
| 68751 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 68752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68753 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68755 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68756 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68757 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 68758 | // (select:{ *:[i32] } GPR:{ *:[i32] }:$cond, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) => (TH_MVEQZ:{ *:[i32] } GPR:{ *:[i32] }:$a, X0:{ *:[i32] }, GPR:{ *:[i32] }:$cond) |
| 68759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68761 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68762 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68763 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68764 | GIR_RootConstrainSelectedInstOperands, |
| 68765 | // GIR_Coverage, 63043, |
| 68766 | GIR_EraseRootFromParent_Done, |
| 68767 | // Label 4588: @175115 |
| 68768 | GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(175165), // Rule ID 63300 // |
| 68769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode0), |
| 68770 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 68771 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68772 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68774 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68776 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 68777 | // (select:{ *:[i32] } GPR:{ *:[i64] }:$cond, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) => (TH_MVEQZ:{ *:[i32] } GPR:{ *:[i32] }:$a, X0:{ *:[i64] }, GPR:{ *:[i64] }:$cond) |
| 68778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68780 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68782 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68783 | GIR_RootConstrainSelectedInstOperands, |
| 68784 | // GIR_Coverage, 63300, |
| 68785 | GIR_EraseRootFromParent_Done, |
| 68786 | // Label 4589: @175165 |
| 68787 | GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(175215), // Rule ID 63301 // |
| 68788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode1), |
| 68789 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 68790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68791 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68794 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68795 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 68796 | // (select:{ *:[i32] } GPR:{ *:[i32] }:$cond, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) => (TH_MVEQZ:{ *:[i32] } GPR:{ *:[i32] }:$a, X0:{ *:[i32] }, GPR:{ *:[i32] }:$cond) |
| 68797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68799 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68800 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68801 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68802 | GIR_RootConstrainSelectedInstOperands, |
| 68803 | // GIR_Coverage, 63301, |
| 68804 | GIR_EraseRootFromParent_Done, |
| 68805 | // Label 4590: @175215 |
| 68806 | GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(175261), // Rule ID 63041 // |
| 68807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_HwMode1), |
| 68808 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 68809 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68810 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68812 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68813 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68814 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68815 | // (select:{ *:[i32] } GPR:{ *:[i32] }:$cond, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (TH_MVEQZ:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$cond) |
| 68816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68818 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68819 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68820 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68821 | GIR_RootConstrainSelectedInstOperands, |
| 68822 | // GIR_Coverage, 63041, |
| 68823 | GIR_EraseRootFromParent_Done, |
| 68824 | // Label 4591: @175261 |
| 68825 | GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(175307), // Rule ID 63298 // |
| 68826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode0), |
| 68827 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 68828 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68829 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68833 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68834 | // (select:{ *:[i32] } GPR:{ *:[i64] }:$cond, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (TH_MVEQZ:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i64] }:$cond) |
| 68835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68837 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68838 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68839 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68840 | GIR_RootConstrainSelectedInstOperands, |
| 68841 | // GIR_Coverage, 63298, |
| 68842 | GIR_EraseRootFromParent_Done, |
| 68843 | // Label 4592: @175307 |
| 68844 | GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(175353), // Rule ID 63299 // |
| 68845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode1), |
| 68846 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 68847 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68848 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68851 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68852 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68853 | // (select:{ *:[i32] } GPR:{ *:[i32] }:$cond, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (TH_MVEQZ:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$cond) |
| 68854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68856 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68857 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68858 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68859 | GIR_RootConstrainSelectedInstOperands, |
| 68860 | // GIR_Coverage, 63299, |
| 68861 | GIR_EraseRootFromParent_Done, |
| 68862 | // Label 4593: @175353 |
| 68863 | GIM_Reject, |
| 68864 | // Label 4561: @175354 |
| 68865 | GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(175472), |
| 68866 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 68867 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 68868 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 68869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68870 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68871 | GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(175409), // Rule ID 63044 // |
| 68872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_HwMode0), |
| 68873 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 68874 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68875 | // (select:{ *:[i64] } GPR:{ *:[i64] }:$cond, 0:{ *:[i64] }, GPR:{ *:[i64] }:$b) => (TH_MVNEZ:{ *:[i64] } GPR:{ *:[i64] }:$b, X0:{ *:[i64] }, GPR:{ *:[i64] }:$cond) |
| 68876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVNEZ), |
| 68877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68878 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68879 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68880 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68881 | GIR_RootConstrainSelectedInstOperands, |
| 68882 | // GIR_Coverage, 63044, |
| 68883 | GIR_EraseRootFromParent_Done, |
| 68884 | // Label 4595: @175409 |
| 68885 | GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(175442), // Rule ID 63042 // |
| 68886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_HwMode0), |
| 68887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68888 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 68889 | // (select:{ *:[i64] } GPR:{ *:[i64] }:$cond, GPR:{ *:[i64] }:$a, 0:{ *:[i64] }) => (TH_MVEQZ:{ *:[i64] } GPR:{ *:[i64] }:$a, X0:{ *:[i64] }, GPR:{ *:[i64] }:$cond) |
| 68890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68892 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68893 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68894 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68895 | GIR_RootConstrainSelectedInstOperands, |
| 68896 | // GIR_Coverage, 63042, |
| 68897 | GIR_EraseRootFromParent_Done, |
| 68898 | // Label 4596: @175442 |
| 68899 | GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(175471), // Rule ID 63040 // |
| 68900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadCondMov_HwMode0), |
| 68901 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68902 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 68903 | // (select:{ *:[i64] } GPR:{ *:[i64] }:$cond, GPR:{ *:[i64] }:$a, GPR:{ *:[i64] }:$b) => (TH_MVEQZ:{ *:[i64] } GPR:{ *:[i64] }:$a, GPR:{ *:[i64] }:$b, GPR:{ *:[i64] }:$cond) |
| 68904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MVEQZ), |
| 68905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] |
| 68906 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 68907 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 68908 | GIR_RootToRootCopy, /*OpIdx*/1, // cond |
| 68909 | GIR_RootConstrainSelectedInstOperands, |
| 68910 | // GIR_Coverage, 63040, |
| 68911 | GIR_EraseRootFromParent_Done, |
| 68912 | // Label 4597: @175471 |
| 68913 | GIM_Reject, |
| 68914 | // Label 4594: @175472 |
| 68915 | GIM_Reject, |
| 68916 | // Label 4562: @175473 |
| 68917 | GIM_Try, /*On fail goto*//*Label 4598*/ GIMT_Encode4(175628), |
| 68918 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 68919 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 68920 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s8, |
| 68921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 68922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 68923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68924 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68925 | GIM_Try, /*On fail goto*//*Label 4599*/ GIMT_Encode4(175565), // Rule ID 52864 // |
| 68926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 68927 | // (vselect:{ *:[nxv1i8] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMERGE_VVM_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 68928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 68929 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 68930 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 68931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 68932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 68933 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 68934 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 68935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF8), |
| 68936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 68938 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68939 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68940 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 68943 | GIR_RootConstrainSelectedInstOperands, |
| 68944 | // GIR_Coverage, 52864, |
| 68945 | GIR_EraseRootFromParent_Done, |
| 68946 | // Label 4599: @175565 |
| 68947 | GIM_Try, /*On fail goto*//*Label 4600*/ GIMT_Encode4(175627), // Rule ID 52865 // |
| 68948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 68949 | // (vselect:{ *:[nxv1i8] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMERGE_VVM_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 68950 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 68951 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 68952 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 68953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 68954 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 68955 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 68956 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 68957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF8), |
| 68958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 68960 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68961 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68962 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 68965 | GIR_RootConstrainSelectedInstOperands, |
| 68966 | // GIR_Coverage, 52865, |
| 68967 | GIR_EraseRootFromParent_Done, |
| 68968 | // Label 4600: @175627 |
| 68969 | GIM_Reject, |
| 68970 | // Label 4598: @175628 |
| 68971 | GIM_Reject, |
| 68972 | // Label 4563: @175629 |
| 68973 | GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(176032), |
| 68974 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 68975 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 68976 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 68977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 68978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 68979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 68981 | GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(175721), // Rule ID 52882 // |
| 68982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 68983 | // (vselect:{ *:[nxv1i16] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 68984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 68985 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 68986 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 68987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 68988 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 68989 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 68990 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 68991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 68992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 68993 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 68994 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 68995 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 68996 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 68997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 68998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 68999 | GIR_RootConstrainSelectedInstOperands, |
| 69000 | // GIR_Coverage, 52882, |
| 69001 | GIR_EraseRootFromParent_Done, |
| 69002 | // Label 4602: @175721 |
| 69003 | GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(175783), // Rule ID 52883 // |
| 69004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69005 | // (vselect:{ *:[nxv1i16] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69006 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 69007 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69008 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69009 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69010 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69011 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69012 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69015 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69016 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69017 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69018 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69021 | GIR_RootConstrainSelectedInstOperands, |
| 69022 | // GIR_Coverage, 52883, |
| 69023 | GIR_EraseRootFromParent_Done, |
| 69024 | // Label 4603: @175783 |
| 69025 | GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(175845), // Rule ID 58524 // |
| 69026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69027 | // (vselect:{ *:[nxv1f16] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs2, VR:{ *:[nxv1f16] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 69029 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69030 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69033 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69037 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69038 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69039 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69040 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69043 | GIR_RootConstrainSelectedInstOperands, |
| 69044 | // GIR_Coverage, 58524, |
| 69045 | GIR_EraseRootFromParent_Done, |
| 69046 | // Label 4604: @175845 |
| 69047 | GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(175907), // Rule ID 58525 // |
| 69048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69049 | // (vselect:{ *:[nxv1f16] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs2, VR:{ *:[nxv1f16] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69050 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 69051 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69052 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69054 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69055 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69056 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69060 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69061 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69062 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69065 | GIR_RootConstrainSelectedInstOperands, |
| 69066 | // GIR_Coverage, 58525, |
| 69067 | GIR_EraseRootFromParent_Done, |
| 69068 | // Label 4605: @175907 |
| 69069 | GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(175969), // Rule ID 58674 // |
| 69070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69071 | // (vselect:{ *:[nxv1bf16] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1bf16] }:$rs1, VR:{ *:[nxv1bf16] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv1bf16] } (IMPLICIT_DEF:{ *:[nxv1bf16] }), VR:{ *:[nxv1bf16] }:$rs2, VR:{ *:[nxv1bf16] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69072 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 69073 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69074 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69076 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69077 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69078 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69081 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69082 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69083 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69084 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69087 | GIR_RootConstrainSelectedInstOperands, |
| 69088 | // GIR_Coverage, 58674, |
| 69089 | GIR_EraseRootFromParent_Done, |
| 69090 | // Label 4606: @175969 |
| 69091 | GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(176031), // Rule ID 58675 // |
| 69092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69093 | // (vselect:{ *:[nxv1bf16] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1bf16] }:$rs1, VR:{ *:[nxv1bf16] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv1bf16] } (IMPLICIT_DEF:{ *:[nxv1bf16] }), VR:{ *:[nxv1bf16] }:$rs2, VR:{ *:[nxv1bf16] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69094 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 69095 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69096 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69099 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69100 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69104 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69105 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69106 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69109 | GIR_RootConstrainSelectedInstOperands, |
| 69110 | // GIR_Coverage, 58675, |
| 69111 | GIR_EraseRootFromParent_Done, |
| 69112 | // Label 4607: @176031 |
| 69113 | GIM_Reject, |
| 69114 | // Label 4601: @176032 |
| 69115 | GIM_Reject, |
| 69116 | // Label 4564: @176033 |
| 69117 | GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(176312), |
| 69118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 69119 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 69120 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 69121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69122 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69124 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69125 | GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(176125), // Rule ID 52894 // |
| 69126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69127 | // (vselect:{ *:[nxv1i32] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 69128 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 69129 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69130 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69133 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69134 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69138 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69139 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69140 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69143 | GIR_RootConstrainSelectedInstOperands, |
| 69144 | // GIR_Coverage, 52894, |
| 69145 | GIR_EraseRootFromParent_Done, |
| 69146 | // Label 4609: @176125 |
| 69147 | GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(176187), // Rule ID 52895 // |
| 69148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69149 | // (vselect:{ *:[nxv1i32] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 69150 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 69151 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69152 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69155 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69156 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69160 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69161 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69162 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69165 | GIR_RootConstrainSelectedInstOperands, |
| 69166 | // GIR_Coverage, 52895, |
| 69167 | GIR_EraseRootFromParent_Done, |
| 69168 | // Label 4610: @176187 |
| 69169 | GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(176249), // Rule ID 58544 // |
| 69170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69171 | // (vselect:{ *:[nxv1f32] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs2, VR:{ *:[nxv1f32] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 69172 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 69173 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69174 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69177 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69178 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69181 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69182 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69183 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69184 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69187 | GIR_RootConstrainSelectedInstOperands, |
| 69188 | // GIR_Coverage, 58544, |
| 69189 | GIR_EraseRootFromParent_Done, |
| 69190 | // Label 4611: @176249 |
| 69191 | GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(176311), // Rule ID 58545 // |
| 69192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69193 | // (vselect:{ *:[nxv1f32] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs2, VR:{ *:[nxv1f32] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 69194 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 69195 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69196 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69197 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69198 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69199 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69200 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69203 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69204 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69205 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69206 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69209 | GIR_RootConstrainSelectedInstOperands, |
| 69210 | // GIR_Coverage, 58545, |
| 69211 | GIR_EraseRootFromParent_Done, |
| 69212 | // Label 4612: @176311 |
| 69213 | GIM_Reject, |
| 69214 | // Label 4608: @176312 |
| 69215 | GIM_Reject, |
| 69216 | // Label 4565: @176313 |
| 69217 | GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(176592), |
| 69218 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, |
| 69219 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 69220 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 69221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69222 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69223 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69224 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69225 | GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(176405), // Rule ID 52918 // |
| 69226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 69227 | // (vselect:{ *:[nxv1i64] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 69228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 69229 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69230 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69232 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69233 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69237 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69238 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69239 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69240 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69243 | GIR_RootConstrainSelectedInstOperands, |
| 69244 | // GIR_Coverage, 52918, |
| 69245 | GIR_EraseRootFromParent_Done, |
| 69246 | // Label 4614: @176405 |
| 69247 | GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(176467), // Rule ID 52919 // |
| 69248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 69249 | // (vselect:{ *:[nxv1i64] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 69250 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 69251 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69252 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69255 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69256 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69260 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69261 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69262 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69265 | GIR_RootConstrainSelectedInstOperands, |
| 69266 | // GIR_Coverage, 52919, |
| 69267 | GIR_EraseRootFromParent_Done, |
| 69268 | // Label 4615: @176467 |
| 69269 | GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(176529), // Rule ID 58574 // |
| 69270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 69271 | // (vselect:{ *:[nxv1f64] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs2, VR:{ *:[nxv1f64] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 69272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 69273 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69274 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69276 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69277 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69278 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69281 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69282 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69283 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69284 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69287 | GIR_RootConstrainSelectedInstOperands, |
| 69288 | // GIR_Coverage, 58574, |
| 69289 | GIR_EraseRootFromParent_Done, |
| 69290 | // Label 4616: @176529 |
| 69291 | GIM_Try, /*On fail goto*//*Label 4617*/ GIMT_Encode4(176591), // Rule ID 58575 // |
| 69292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 69293 | // (vselect:{ *:[nxv1f64] } V0:{ *:[nxv1i1] }, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs2, VR:{ *:[nxv1f64] }:$rs1, V0:{ *:[nxv1i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 69294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 69295 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69296 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69299 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69300 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69303 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69304 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69305 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69306 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69309 | GIR_RootConstrainSelectedInstOperands, |
| 69310 | // GIR_Coverage, 58575, |
| 69311 | GIR_EraseRootFromParent_Done, |
| 69312 | // Label 4617: @176591 |
| 69313 | GIM_Reject, |
| 69314 | // Label 4613: @176592 |
| 69315 | GIM_Reject, |
| 69316 | // Label 4566: @176593 |
| 69317 | GIM_Try, /*On fail goto*//*Label 4618*/ GIMT_Encode4(176748), |
| 69318 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 69319 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 69320 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s8, |
| 69321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69324 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69325 | GIM_Try, /*On fail goto*//*Label 4619*/ GIMT_Encode4(176685), // Rule ID 52870 // |
| 69326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69327 | // (vselect:{ *:[nxv2i8] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 69328 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 69329 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69330 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69332 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69333 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69334 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69338 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69339 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69340 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 69343 | GIR_RootConstrainSelectedInstOperands, |
| 69344 | // GIR_Coverage, 52870, |
| 69345 | GIR_EraseRootFromParent_Done, |
| 69346 | // Label 4619: @176685 |
| 69347 | GIM_Try, /*On fail goto*//*Label 4620*/ GIMT_Encode4(176747), // Rule ID 52871 // |
| 69348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69349 | // (vselect:{ *:[nxv2i8] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMERGE_VVM_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 69350 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 69351 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69352 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69355 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69356 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF4), |
| 69358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69359 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69360 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69361 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69362 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 69365 | GIR_RootConstrainSelectedInstOperands, |
| 69366 | // GIR_Coverage, 52871, |
| 69367 | GIR_EraseRootFromParent_Done, |
| 69368 | // Label 4620: @176747 |
| 69369 | GIM_Reject, |
| 69370 | // Label 4618: @176748 |
| 69371 | GIM_Reject, |
| 69372 | // Label 4567: @176749 |
| 69373 | GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(177152), |
| 69374 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 69375 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 69376 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 69377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69378 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69379 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69380 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69381 | GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(176841), // Rule ID 52888 // |
| 69382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69383 | // (vselect:{ *:[nxv2i16] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 69385 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69386 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69388 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69389 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69390 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69394 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69395 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69396 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69399 | GIR_RootConstrainSelectedInstOperands, |
| 69400 | // GIR_Coverage, 52888, |
| 69401 | GIR_EraseRootFromParent_Done, |
| 69402 | // Label 4622: @176841 |
| 69403 | GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(176903), // Rule ID 52889 // |
| 69404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69405 | // (vselect:{ *:[nxv2i16] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 69407 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69408 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69410 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69411 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69412 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69415 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69416 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69417 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69418 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69421 | GIR_RootConstrainSelectedInstOperands, |
| 69422 | // GIR_Coverage, 52889, |
| 69423 | GIR_EraseRootFromParent_Done, |
| 69424 | // Label 4623: @176903 |
| 69425 | GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(176965), // Rule ID 58534 // |
| 69426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69427 | // (vselect:{ *:[nxv2f16] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs2, VR:{ *:[nxv2f16] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69428 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 69429 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69430 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69433 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69434 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69438 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69439 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69440 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69443 | GIR_RootConstrainSelectedInstOperands, |
| 69444 | // GIR_Coverage, 58534, |
| 69445 | GIR_EraseRootFromParent_Done, |
| 69446 | // Label 4624: @176965 |
| 69447 | GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(177027), // Rule ID 58535 // |
| 69448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69449 | // (vselect:{ *:[nxv2f16] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs2, VR:{ *:[nxv2f16] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 69451 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69452 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69455 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69456 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69460 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69461 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69462 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69465 | GIR_RootConstrainSelectedInstOperands, |
| 69466 | // GIR_Coverage, 58535, |
| 69467 | GIR_EraseRootFromParent_Done, |
| 69468 | // Label 4625: @177027 |
| 69469 | GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(177089), // Rule ID 58684 // |
| 69470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69471 | // (vselect:{ *:[nxv2bf16] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2bf16] }:$rs1, VR:{ *:[nxv2bf16] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv2bf16] } (IMPLICIT_DEF:{ *:[nxv2bf16] }), VR:{ *:[nxv2bf16] }:$rs2, VR:{ *:[nxv2bf16] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 69473 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69474 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69476 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69477 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69478 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69481 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69482 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69483 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69484 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69487 | GIR_RootConstrainSelectedInstOperands, |
| 69488 | // GIR_Coverage, 58684, |
| 69489 | GIR_EraseRootFromParent_Done, |
| 69490 | // Label 4626: @177089 |
| 69491 | GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(177151), // Rule ID 58685 // |
| 69492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69493 | // (vselect:{ *:[nxv2bf16] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2bf16] }:$rs1, VR:{ *:[nxv2bf16] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv2bf16] } (IMPLICIT_DEF:{ *:[nxv2bf16] }), VR:{ *:[nxv2bf16] }:$rs2, VR:{ *:[nxv2bf16] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 69495 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69496 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69499 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69500 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69504 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69505 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69506 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69509 | GIR_RootConstrainSelectedInstOperands, |
| 69510 | // GIR_Coverage, 58685, |
| 69511 | GIR_EraseRootFromParent_Done, |
| 69512 | // Label 4627: @177151 |
| 69513 | GIM_Reject, |
| 69514 | // Label 4621: @177152 |
| 69515 | GIM_Reject, |
| 69516 | // Label 4568: @177153 |
| 69517 | GIM_Try, /*On fail goto*//*Label 4628*/ GIMT_Encode4(177432), |
| 69518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 69519 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 69520 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 69521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69524 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69525 | GIM_Try, /*On fail goto*//*Label 4629*/ GIMT_Encode4(177245), // Rule ID 52912 // |
| 69526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69527 | // (vselect:{ *:[nxv2i32] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 69528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 69529 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69530 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69532 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69533 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69534 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69537 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69538 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69539 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69540 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69543 | GIR_RootConstrainSelectedInstOperands, |
| 69544 | // GIR_Coverage, 52912, |
| 69545 | GIR_EraseRootFromParent_Done, |
| 69546 | // Label 4629: @177245 |
| 69547 | GIM_Try, /*On fail goto*//*Label 4630*/ GIMT_Encode4(177307), // Rule ID 52913 // |
| 69548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69549 | // (vselect:{ *:[nxv2i32] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 69550 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 69551 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69552 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69555 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69556 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69559 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69560 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69561 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69562 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69565 | GIR_RootConstrainSelectedInstOperands, |
| 69566 | // GIR_Coverage, 52913, |
| 69567 | GIR_EraseRootFromParent_Done, |
| 69568 | // Label 4630: @177307 |
| 69569 | GIM_Try, /*On fail goto*//*Label 4631*/ GIMT_Encode4(177369), // Rule ID 58564 // |
| 69570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69571 | // (vselect:{ *:[nxv2f32] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs2, VR:{ *:[nxv2f32] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 69572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 69573 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69574 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69577 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69578 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69581 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69582 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69583 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69584 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69587 | GIR_RootConstrainSelectedInstOperands, |
| 69588 | // GIR_Coverage, 58564, |
| 69589 | GIR_EraseRootFromParent_Done, |
| 69590 | // Label 4631: @177369 |
| 69591 | GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(177431), // Rule ID 58565 // |
| 69592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69593 | // (vselect:{ *:[nxv2f32] } V0:{ *:[nxv2i1] }, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs2, VR:{ *:[nxv2f32] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 69594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 69595 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69596 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69599 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69600 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69604 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69605 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69606 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69609 | GIR_RootConstrainSelectedInstOperands, |
| 69610 | // GIR_Coverage, 58565, |
| 69611 | GIR_EraseRootFromParent_Done, |
| 69612 | // Label 4632: @177431 |
| 69613 | GIM_Reject, |
| 69614 | // Label 4628: @177432 |
| 69615 | GIM_Reject, |
| 69616 | // Label 4569: @177433 |
| 69617 | GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(177712), |
| 69618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, |
| 69619 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 69620 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 69621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2NoV0RegClassID), |
| 69622 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69623 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 69624 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 69625 | GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(177525), // Rule ID 52978 // |
| 69626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 69627 | // (vselect:{ *:[nxv2i64] } V0:{ *:[nxv2i1] }, VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 69628 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 69629 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69630 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69633 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69634 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69638 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69639 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69640 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69643 | GIR_RootConstrainSelectedInstOperands, |
| 69644 | // GIR_Coverage, 52978, |
| 69645 | GIR_EraseRootFromParent_Done, |
| 69646 | // Label 4634: @177525 |
| 69647 | GIM_Try, /*On fail goto*//*Label 4635*/ GIMT_Encode4(177587), // Rule ID 52979 // |
| 69648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 69649 | // (vselect:{ *:[nxv2i64] } V0:{ *:[nxv2i1] }, VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 69650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 69651 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69652 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69655 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69656 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69660 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69662 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69665 | GIR_RootConstrainSelectedInstOperands, |
| 69666 | // GIR_Coverage, 52979, |
| 69667 | GIR_EraseRootFromParent_Done, |
| 69668 | // Label 4635: @177587 |
| 69669 | GIM_Try, /*On fail goto*//*Label 4636*/ GIMT_Encode4(177649), // Rule ID 58644 // |
| 69670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 69671 | // (vselect:{ *:[nxv2f64] } V0:{ *:[nxv2i1] }, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs2, VRM2:{ *:[nxv2f64] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 69672 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 69673 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69674 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69676 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69677 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69678 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69681 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69682 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69683 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69684 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69687 | GIR_RootConstrainSelectedInstOperands, |
| 69688 | // GIR_Coverage, 58644, |
| 69689 | GIR_EraseRootFromParent_Done, |
| 69690 | // Label 4636: @177649 |
| 69691 | GIM_Try, /*On fail goto*//*Label 4637*/ GIMT_Encode4(177711), // Rule ID 58645 // |
| 69692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 69693 | // (vselect:{ *:[nxv2f64] } V0:{ *:[nxv2i1] }, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs2, VRM2:{ *:[nxv2f64] }:$rs1, V0:{ *:[nxv2i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 69694 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 69695 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69696 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69697 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69698 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69699 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69700 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69703 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69704 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69705 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69706 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 69709 | GIR_RootConstrainSelectedInstOperands, |
| 69710 | // GIR_Coverage, 58645, |
| 69711 | GIR_EraseRootFromParent_Done, |
| 69712 | // Label 4637: @177711 |
| 69713 | GIM_Reject, |
| 69714 | // Label 4633: @177712 |
| 69715 | GIM_Reject, |
| 69716 | // Label 4570: @177713 |
| 69717 | GIM_Try, /*On fail goto*//*Label 4638*/ GIMT_Encode4(177868), |
| 69718 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 69719 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 69720 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s8, |
| 69721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69722 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69724 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69725 | GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(177805), // Rule ID 52876 // |
| 69726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69727 | // (vselect:{ *:[nxv4i8] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 69728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 69729 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69730 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69732 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69733 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69734 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69737 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69738 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69739 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69740 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 69743 | GIR_RootConstrainSelectedInstOperands, |
| 69744 | // GIR_Coverage, 52876, |
| 69745 | GIR_EraseRootFromParent_Done, |
| 69746 | // Label 4639: @177805 |
| 69747 | GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(177867), // Rule ID 52877 // |
| 69748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69749 | // (vselect:{ *:[nxv4i8] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMERGE_VVM_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 69750 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 69751 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69752 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69755 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69756 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_MF2), |
| 69758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69759 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69760 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69761 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69762 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 69765 | GIR_RootConstrainSelectedInstOperands, |
| 69766 | // GIR_Coverage, 52877, |
| 69767 | GIR_EraseRootFromParent_Done, |
| 69768 | // Label 4640: @177867 |
| 69769 | GIM_Reject, |
| 69770 | // Label 4638: @177868 |
| 69771 | GIM_Reject, |
| 69772 | // Label 4571: @177869 |
| 69773 | GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(178272), |
| 69774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 69775 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 69776 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 69777 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 69778 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69780 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 69781 | GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(177961), // Rule ID 52906 // |
| 69782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69783 | // (vselect:{ *:[nxv4i16] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 69785 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69786 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69788 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69789 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69790 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69793 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69794 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69795 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69796 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69799 | GIR_RootConstrainSelectedInstOperands, |
| 69800 | // GIR_Coverage, 52906, |
| 69801 | GIR_EraseRootFromParent_Done, |
| 69802 | // Label 4642: @177961 |
| 69803 | GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(178023), // Rule ID 52907 // |
| 69804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69805 | // (vselect:{ *:[nxv4i16] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 69807 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69808 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69810 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69811 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69812 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69815 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69816 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69817 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69818 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69821 | GIR_RootConstrainSelectedInstOperands, |
| 69822 | // GIR_Coverage, 52907, |
| 69823 | GIR_EraseRootFromParent_Done, |
| 69824 | // Label 4643: @178023 |
| 69825 | GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(178085), // Rule ID 58554 // |
| 69826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69827 | // (vselect:{ *:[nxv4f16] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs2, VR:{ *:[nxv4f16] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 69829 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69830 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69832 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69833 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69834 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69837 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69838 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69839 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69840 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69843 | GIR_RootConstrainSelectedInstOperands, |
| 69844 | // GIR_Coverage, 58554, |
| 69845 | GIR_EraseRootFromParent_Done, |
| 69846 | // Label 4644: @178085 |
| 69847 | GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(178147), // Rule ID 58555 // |
| 69848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69849 | // (vselect:{ *:[nxv4f16] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs2, VR:{ *:[nxv4f16] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69850 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 69851 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69852 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69854 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69855 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69856 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69859 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69860 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69861 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69862 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69865 | GIR_RootConstrainSelectedInstOperands, |
| 69866 | // GIR_Coverage, 58555, |
| 69867 | GIR_EraseRootFromParent_Done, |
| 69868 | // Label 4645: @178147 |
| 69869 | GIM_Try, /*On fail goto*//*Label 4646*/ GIMT_Encode4(178209), // Rule ID 58694 // |
| 69870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69871 | // (vselect:{ *:[nxv4bf16] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4bf16] }:$rs1, VR:{ *:[nxv4bf16] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv4bf16] } (IMPLICIT_DEF:{ *:[nxv4bf16] }), VR:{ *:[nxv4bf16] }:$rs2, VR:{ *:[nxv4bf16] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 69872 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 69873 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69874 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69876 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69877 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69878 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69881 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69882 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69883 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69884 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69887 | GIR_RootConstrainSelectedInstOperands, |
| 69888 | // GIR_Coverage, 58694, |
| 69889 | GIR_EraseRootFromParent_Done, |
| 69890 | // Label 4646: @178209 |
| 69891 | GIM_Try, /*On fail goto*//*Label 4647*/ GIMT_Encode4(178271), // Rule ID 58695 // |
| 69892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69893 | // (vselect:{ *:[nxv4bf16] } V0:{ *:[nxv4i1] }, VR:{ *:[nxv4bf16] }:$rs1, VR:{ *:[nxv4bf16] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv4bf16] } (IMPLICIT_DEF:{ *:[nxv4bf16] }), VR:{ *:[nxv4bf16] }:$rs2, VR:{ *:[nxv4bf16] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 69894 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 69895 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69896 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69898 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69899 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69900 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 69902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69903 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69904 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69905 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69906 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69909 | GIR_RootConstrainSelectedInstOperands, |
| 69910 | // GIR_Coverage, 58695, |
| 69911 | GIR_EraseRootFromParent_Done, |
| 69912 | // Label 4647: @178271 |
| 69913 | GIM_Reject, |
| 69914 | // Label 4641: @178272 |
| 69915 | GIM_Reject, |
| 69916 | // Label 4572: @178273 |
| 69917 | GIM_Try, /*On fail goto*//*Label 4648*/ GIMT_Encode4(178552), |
| 69918 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 69919 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 69920 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 69921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2NoV0RegClassID), |
| 69922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 69923 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 69924 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 69925 | GIM_Try, /*On fail goto*//*Label 4649*/ GIMT_Encode4(178365), // Rule ID 52960 // |
| 69926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69927 | // (vselect:{ *:[nxv4i32] } V0:{ *:[nxv4i1] }, VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 69928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 69929 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69930 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69933 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69934 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69938 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69939 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69940 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69943 | GIR_RootConstrainSelectedInstOperands, |
| 69944 | // GIR_Coverage, 52960, |
| 69945 | GIR_EraseRootFromParent_Done, |
| 69946 | // Label 4649: @178365 |
| 69947 | GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(178427), // Rule ID 52961 // |
| 69948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69949 | // (vselect:{ *:[nxv4i32] } V0:{ *:[nxv4i1] }, VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 69950 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 69951 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69952 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69954 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69955 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69956 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69960 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69961 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69962 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69965 | GIR_RootConstrainSelectedInstOperands, |
| 69966 | // GIR_Coverage, 52961, |
| 69967 | GIR_EraseRootFromParent_Done, |
| 69968 | // Label 4650: @178427 |
| 69969 | GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(178489), // Rule ID 58614 // |
| 69970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 69971 | // (vselect:{ *:[nxv4f32] } V0:{ *:[nxv4i1] }, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs2, VRM2:{ *:[nxv4f32] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 69972 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 69973 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69974 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69976 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69977 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69978 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 69979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 69980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 69981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 69982 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 69983 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 69984 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 69985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 69986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 69987 | GIR_RootConstrainSelectedInstOperands, |
| 69988 | // GIR_Coverage, 58614, |
| 69989 | GIR_EraseRootFromParent_Done, |
| 69990 | // Label 4651: @178489 |
| 69991 | GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(178551), // Rule ID 58615 // |
| 69992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 69993 | // (vselect:{ *:[nxv4f32] } V0:{ *:[nxv4i1] }, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs2, VRM2:{ *:[nxv4f32] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 69994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 69995 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 69996 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 69997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 69998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69999 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70000 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70003 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70004 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70005 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70006 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70009 | GIR_RootConstrainSelectedInstOperands, |
| 70010 | // GIR_Coverage, 58615, |
| 70011 | GIR_EraseRootFromParent_Done, |
| 70012 | // Label 4652: @178551 |
| 70013 | GIM_Reject, |
| 70014 | // Label 4648: @178552 |
| 70015 | GIM_Reject, |
| 70016 | // Label 4573: @178553 |
| 70017 | GIM_Try, /*On fail goto*//*Label 4653*/ GIMT_Encode4(178832), |
| 70018 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, |
| 70019 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 70020 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 70021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4NoV0RegClassID), |
| 70022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70025 | GIM_Try, /*On fail goto*//*Label 4654*/ GIMT_Encode4(178645), // Rule ID 52984 // |
| 70026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 70027 | // (vselect:{ *:[nxv4i64] } V0:{ *:[nxv4i1] }, VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 70028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 70029 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70030 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70033 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70037 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70038 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70039 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70040 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70043 | GIR_RootConstrainSelectedInstOperands, |
| 70044 | // GIR_Coverage, 52984, |
| 70045 | GIR_EraseRootFromParent_Done, |
| 70046 | // Label 4654: @178645 |
| 70047 | GIM_Try, /*On fail goto*//*Label 4655*/ GIMT_Encode4(178707), // Rule ID 52985 // |
| 70048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 70049 | // (vselect:{ *:[nxv4i64] } V0:{ *:[nxv4i1] }, VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 70050 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 70051 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70052 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70054 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70055 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70056 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70060 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70061 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70062 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70065 | GIR_RootConstrainSelectedInstOperands, |
| 70066 | // GIR_Coverage, 52985, |
| 70067 | GIR_EraseRootFromParent_Done, |
| 70068 | // Label 4655: @178707 |
| 70069 | GIM_Try, /*On fail goto*//*Label 4656*/ GIMT_Encode4(178769), // Rule ID 58654 // |
| 70070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 70071 | // (vselect:{ *:[nxv4f64] } V0:{ *:[nxv4i1] }, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs2, VRM4:{ *:[nxv4f64] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 70072 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 70073 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70074 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70076 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70077 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70078 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70081 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70082 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70083 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70084 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70087 | GIR_RootConstrainSelectedInstOperands, |
| 70088 | // GIR_Coverage, 58654, |
| 70089 | GIR_EraseRootFromParent_Done, |
| 70090 | // Label 4656: @178769 |
| 70091 | GIM_Try, /*On fail goto*//*Label 4657*/ GIMT_Encode4(178831), // Rule ID 58655 // |
| 70092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 70093 | // (vselect:{ *:[nxv4f64] } V0:{ *:[nxv4i1] }, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs2, VRM4:{ *:[nxv4f64] }:$rs1, V0:{ *:[nxv4i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 70094 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 70095 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70096 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70099 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70100 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70104 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70105 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70106 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70109 | GIR_RootConstrainSelectedInstOperands, |
| 70110 | // GIR_Coverage, 58655, |
| 70111 | GIR_EraseRootFromParent_Done, |
| 70112 | // Label 4657: @178831 |
| 70113 | GIM_Reject, |
| 70114 | // Label 4653: @178832 |
| 70115 | GIM_Reject, |
| 70116 | // Label 4574: @178833 |
| 70117 | GIM_Try, /*On fail goto*//*Label 4658*/ GIMT_Encode4(178988), |
| 70118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 70119 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 70120 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s8, |
| 70121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRNoV0RegClassID), |
| 70122 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70123 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 70124 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 70125 | GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(178925), // Rule ID 52900 // |
| 70126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70127 | // (vselect:{ *:[nxv8i8] } V0:{ *:[nxv8i1] }, VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 70128 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 70129 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70130 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70133 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70134 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 70136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70138 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70139 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70140 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 70143 | GIR_RootConstrainSelectedInstOperands, |
| 70144 | // GIR_Coverage, 52900, |
| 70145 | GIR_EraseRootFromParent_Done, |
| 70146 | // Label 4659: @178925 |
| 70147 | GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(178987), // Rule ID 52901 // |
| 70148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70149 | // (vselect:{ *:[nxv8i8] } V0:{ *:[nxv8i1] }, VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMERGE_VVM_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 70150 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 70151 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70152 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70155 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70156 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M1), |
| 70158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70160 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70161 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70162 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 70165 | GIR_RootConstrainSelectedInstOperands, |
| 70166 | // GIR_Coverage, 52901, |
| 70167 | GIR_EraseRootFromParent_Done, |
| 70168 | // Label 4660: @178987 |
| 70169 | GIM_Reject, |
| 70170 | // Label 4658: @178988 |
| 70171 | GIM_Reject, |
| 70172 | // Label 4575: @178989 |
| 70173 | GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(179392), |
| 70174 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 70175 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 70176 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 70177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2NoV0RegClassID), |
| 70178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 70180 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 70181 | GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(179081), // Rule ID 52942 // |
| 70182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70183 | // (vselect:{ *:[nxv8i16] } V0:{ *:[nxv8i1] }, VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70184 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 70185 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70186 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70188 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70189 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70190 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70193 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70194 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70195 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70196 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70199 | GIR_RootConstrainSelectedInstOperands, |
| 70200 | // GIR_Coverage, 52942, |
| 70201 | GIR_EraseRootFromParent_Done, |
| 70202 | // Label 4662: @179081 |
| 70203 | GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(179143), // Rule ID 52943 // |
| 70204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70205 | // (vselect:{ *:[nxv8i16] } V0:{ *:[nxv8i1] }, VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70206 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 70207 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70208 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70209 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70210 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70211 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70212 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70215 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70216 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70217 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70218 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70221 | GIR_RootConstrainSelectedInstOperands, |
| 70222 | // GIR_Coverage, 52943, |
| 70223 | GIR_EraseRootFromParent_Done, |
| 70224 | // Label 4663: @179143 |
| 70225 | GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(179205), // Rule ID 58584 // |
| 70226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70227 | // (vselect:{ *:[nxv8f16] } V0:{ *:[nxv8i1] }, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs2, VRM2:{ *:[nxv8f16] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 70229 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70230 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70232 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70233 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70237 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70238 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70239 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70240 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70243 | GIR_RootConstrainSelectedInstOperands, |
| 70244 | // GIR_Coverage, 58584, |
| 70245 | GIR_EraseRootFromParent_Done, |
| 70246 | // Label 4664: @179205 |
| 70247 | GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(179267), // Rule ID 58585 // |
| 70248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70249 | // (vselect:{ *:[nxv8f16] } V0:{ *:[nxv8i1] }, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs2, VRM2:{ *:[nxv8f16] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70250 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 70251 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70252 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70255 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70256 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70260 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70261 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70262 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70265 | GIR_RootConstrainSelectedInstOperands, |
| 70266 | // GIR_Coverage, 58585, |
| 70267 | GIR_EraseRootFromParent_Done, |
| 70268 | // Label 4665: @179267 |
| 70269 | GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(179329), // Rule ID 58704 // |
| 70270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70271 | // (vselect:{ *:[nxv8bf16] } V0:{ *:[nxv8i1] }, VRM2:{ *:[nxv8bf16] }:$rs1, VRM2:{ *:[nxv8bf16] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv8bf16] } (IMPLICIT_DEF:{ *:[nxv8bf16] }), VRM2:{ *:[nxv8bf16] }:$rs2, VRM2:{ *:[nxv8bf16] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 70273 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70274 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70276 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70277 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70278 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70281 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70282 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70283 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70284 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70287 | GIR_RootConstrainSelectedInstOperands, |
| 70288 | // GIR_Coverage, 58704, |
| 70289 | GIR_EraseRootFromParent_Done, |
| 70290 | // Label 4666: @179329 |
| 70291 | GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(179391), // Rule ID 58705 // |
| 70292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70293 | // (vselect:{ *:[nxv8bf16] } V0:{ *:[nxv8i1] }, VRM2:{ *:[nxv8bf16] }:$rs1, VRM2:{ *:[nxv8bf16] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv8bf16] } (IMPLICIT_DEF:{ *:[nxv8bf16] }), VRM2:{ *:[nxv8bf16] }:$rs2, VRM2:{ *:[nxv8bf16] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 70295 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70296 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70299 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70300 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70303 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70304 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70305 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70306 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70309 | GIR_RootConstrainSelectedInstOperands, |
| 70310 | // GIR_Coverage, 58705, |
| 70311 | GIR_EraseRootFromParent_Done, |
| 70312 | // Label 4667: @179391 |
| 70313 | GIM_Reject, |
| 70314 | // Label 4661: @179392 |
| 70315 | GIM_Reject, |
| 70316 | // Label 4576: @179393 |
| 70317 | GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(179672), |
| 70318 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 70319 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 70320 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 70321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4NoV0RegClassID), |
| 70322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70324 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70325 | GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(179485), // Rule ID 52966 // |
| 70326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70327 | // (vselect:{ *:[nxv8i32] } V0:{ *:[nxv8i1] }, VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 70328 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 70329 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70330 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70332 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70333 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70334 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70338 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70339 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70340 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70343 | GIR_RootConstrainSelectedInstOperands, |
| 70344 | // GIR_Coverage, 52966, |
| 70345 | GIR_EraseRootFromParent_Done, |
| 70346 | // Label 4669: @179485 |
| 70347 | GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(179547), // Rule ID 52967 // |
| 70348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70349 | // (vselect:{ *:[nxv8i32] } V0:{ *:[nxv8i1] }, VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 70350 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 70351 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70352 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70355 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70356 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70359 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70360 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70361 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70362 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70365 | GIR_RootConstrainSelectedInstOperands, |
| 70366 | // GIR_Coverage, 52967, |
| 70367 | GIR_EraseRootFromParent_Done, |
| 70368 | // Label 4670: @179547 |
| 70369 | GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(179609), // Rule ID 58624 // |
| 70370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70371 | // (vselect:{ *:[nxv8f32] } V0:{ *:[nxv8i1] }, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs2, VRM4:{ *:[nxv8f32] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 70372 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 70373 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70374 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70376 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70377 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70378 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70381 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70382 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70383 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70384 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70387 | GIR_RootConstrainSelectedInstOperands, |
| 70388 | // GIR_Coverage, 58624, |
| 70389 | GIR_EraseRootFromParent_Done, |
| 70390 | // Label 4671: @179609 |
| 70391 | GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(179671), // Rule ID 58625 // |
| 70392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70393 | // (vselect:{ *:[nxv8f32] } V0:{ *:[nxv8i1] }, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs2, VRM4:{ *:[nxv8f32] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 70394 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 70395 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70396 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70398 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70399 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70400 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70404 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70405 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70406 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70409 | GIR_RootConstrainSelectedInstOperands, |
| 70410 | // GIR_Coverage, 58625, |
| 70411 | GIR_EraseRootFromParent_Done, |
| 70412 | // Label 4672: @179671 |
| 70413 | GIM_Reject, |
| 70414 | // Label 4668: @179672 |
| 70415 | GIM_Reject, |
| 70416 | // Label 4577: @179673 |
| 70417 | GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(179952), |
| 70418 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, |
| 70419 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 70420 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 70421 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8NoV0RegClassID), |
| 70422 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70423 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 70424 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 70425 | GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(179765), // Rule ID 52990 // |
| 70426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 70427 | // (vselect:{ *:[nxv8i64] } V0:{ *:[nxv8i1] }, VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 70428 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 70429 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70430 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70433 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70434 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70438 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70439 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70440 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70443 | GIR_RootConstrainSelectedInstOperands, |
| 70444 | // GIR_Coverage, 52990, |
| 70445 | GIR_EraseRootFromParent_Done, |
| 70446 | // Label 4674: @179765 |
| 70447 | GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(179827), // Rule ID 52991 // |
| 70448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 70449 | // (vselect:{ *:[nxv8i64] } V0:{ *:[nxv8i1] }, VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 70450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 70451 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70452 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70455 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70456 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70460 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70461 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70462 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70465 | GIR_RootConstrainSelectedInstOperands, |
| 70466 | // GIR_Coverage, 52991, |
| 70467 | GIR_EraseRootFromParent_Done, |
| 70468 | // Label 4675: @179827 |
| 70469 | GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(179889), // Rule ID 58664 // |
| 70470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 70471 | // (vselect:{ *:[nxv8f64] } V0:{ *:[nxv8i1] }, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs2, VRM8:{ *:[nxv8f64] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i64] }, 6:{ *:[i64] }) |
| 70472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 70473 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70474 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70476 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70477 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70478 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70481 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70482 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70483 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70484 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70487 | GIR_RootConstrainSelectedInstOperands, |
| 70488 | // GIR_Coverage, 58664, |
| 70489 | GIR_EraseRootFromParent_Done, |
| 70490 | // Label 4676: @179889 |
| 70491 | GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(179951), // Rule ID 58665 // |
| 70492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 70493 | // (vselect:{ *:[nxv8f64] } V0:{ *:[nxv8i1] }, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs2, VRM8:{ *:[nxv8f64] }:$rs1, V0:{ *:[nxv8i1] }, -1:{ *:[i32] }, 6:{ *:[i32] }) |
| 70494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 70495 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70496 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70499 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70500 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70504 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70505 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70506 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 70509 | GIR_RootConstrainSelectedInstOperands, |
| 70510 | // GIR_Coverage, 58665, |
| 70511 | GIR_EraseRootFromParent_Done, |
| 70512 | // Label 4677: @179951 |
| 70513 | GIM_Reject, |
| 70514 | // Label 4673: @179952 |
| 70515 | GIM_Reject, |
| 70516 | // Label 4578: @179953 |
| 70517 | GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(180108), |
| 70518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 70519 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 70520 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8, |
| 70521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2NoV0RegClassID), |
| 70522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70523 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 70524 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 70525 | GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(180045), // Rule ID 52924 // |
| 70526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70527 | // (vselect:{ *:[nxv16i8] } V0:{ *:[nxv16i1] }, VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 70528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 70529 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70530 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70532 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70533 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70534 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70537 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70538 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70539 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70540 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 70543 | GIR_RootConstrainSelectedInstOperands, |
| 70544 | // GIR_Coverage, 52924, |
| 70545 | GIR_EraseRootFromParent_Done, |
| 70546 | // Label 4679: @180045 |
| 70547 | GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(180107), // Rule ID 52925 // |
| 70548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70549 | // (vselect:{ *:[nxv16i8] } V0:{ *:[nxv16i1] }, VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMERGE_VVM_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 70550 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 70551 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70552 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70555 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70556 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M2), |
| 70558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70559 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70560 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70561 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70562 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 70565 | GIR_RootConstrainSelectedInstOperands, |
| 70566 | // GIR_Coverage, 52925, |
| 70567 | GIR_EraseRootFromParent_Done, |
| 70568 | // Label 4680: @180107 |
| 70569 | GIM_Reject, |
| 70570 | // Label 4678: @180108 |
| 70571 | GIM_Reject, |
| 70572 | // Label 4579: @180109 |
| 70573 | GIM_Try, /*On fail goto*//*Label 4681*/ GIMT_Encode4(180512), |
| 70574 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 70575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 70576 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 70577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4NoV0RegClassID), |
| 70578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70580 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70581 | GIM_Try, /*On fail goto*//*Label 4682*/ GIMT_Encode4(180201), // Rule ID 52948 // |
| 70582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70583 | // (vselect:{ *:[nxv16i16] } V0:{ *:[nxv16i1] }, VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70584 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 70585 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70586 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70589 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70590 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70593 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70594 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70595 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70596 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70599 | GIR_RootConstrainSelectedInstOperands, |
| 70600 | // GIR_Coverage, 52948, |
| 70601 | GIR_EraseRootFromParent_Done, |
| 70602 | // Label 4682: @180201 |
| 70603 | GIM_Try, /*On fail goto*//*Label 4683*/ GIMT_Encode4(180263), // Rule ID 52949 // |
| 70604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70605 | // (vselect:{ *:[nxv16i16] } V0:{ *:[nxv16i1] }, VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70606 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 70607 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70608 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70610 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70611 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70612 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70616 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70617 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70618 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70621 | GIR_RootConstrainSelectedInstOperands, |
| 70622 | // GIR_Coverage, 52949, |
| 70623 | GIR_EraseRootFromParent_Done, |
| 70624 | // Label 4683: @180263 |
| 70625 | GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(180325), // Rule ID 58594 // |
| 70626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70627 | // (vselect:{ *:[nxv16f16] } V0:{ *:[nxv16i1] }, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs2, VRM4:{ *:[nxv16f16] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70628 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 70629 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70630 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70633 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70634 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70638 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70639 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70640 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70643 | GIR_RootConstrainSelectedInstOperands, |
| 70644 | // GIR_Coverage, 58594, |
| 70645 | GIR_EraseRootFromParent_Done, |
| 70646 | // Label 4684: @180325 |
| 70647 | GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(180387), // Rule ID 58595 // |
| 70648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70649 | // (vselect:{ *:[nxv16f16] } V0:{ *:[nxv16i1] }, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs2, VRM4:{ *:[nxv16f16] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 70651 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70652 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70655 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70656 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70660 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70662 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70665 | GIR_RootConstrainSelectedInstOperands, |
| 70666 | // GIR_Coverage, 58595, |
| 70667 | GIR_EraseRootFromParent_Done, |
| 70668 | // Label 4685: @180387 |
| 70669 | GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(180449), // Rule ID 58714 // |
| 70670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70671 | // (vselect:{ *:[nxv16bf16] } V0:{ *:[nxv16i1] }, VRM4:{ *:[nxv16bf16] }:$rs1, VRM4:{ *:[nxv16bf16] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv16bf16] } (IMPLICIT_DEF:{ *:[nxv16bf16] }), VRM4:{ *:[nxv16bf16] }:$rs2, VRM4:{ *:[nxv16bf16] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70672 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 70673 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70674 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70676 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70677 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70678 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70681 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70682 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70683 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70684 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70687 | GIR_RootConstrainSelectedInstOperands, |
| 70688 | // GIR_Coverage, 58714, |
| 70689 | GIR_EraseRootFromParent_Done, |
| 70690 | // Label 4686: @180449 |
| 70691 | GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(180511), // Rule ID 58715 // |
| 70692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70693 | // (vselect:{ *:[nxv16bf16] } V0:{ *:[nxv16i1] }, VRM4:{ *:[nxv16bf16] }:$rs1, VRM4:{ *:[nxv16bf16] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv16bf16] } (IMPLICIT_DEF:{ *:[nxv16bf16] }), VRM4:{ *:[nxv16bf16] }:$rs2, VRM4:{ *:[nxv16bf16] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70694 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 70695 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70696 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70697 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70698 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70699 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70700 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70703 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70704 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70705 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70706 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70709 | GIR_RootConstrainSelectedInstOperands, |
| 70710 | // GIR_Coverage, 58715, |
| 70711 | GIR_EraseRootFromParent_Done, |
| 70712 | // Label 4687: @180511 |
| 70713 | GIM_Reject, |
| 70714 | // Label 4681: @180512 |
| 70715 | GIM_Reject, |
| 70716 | // Label 4580: @180513 |
| 70717 | GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(180792), |
| 70718 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1, |
| 70719 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 70720 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 70721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8NoV0RegClassID), |
| 70722 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 70724 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 70725 | GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(180605), // Rule ID 52972 // |
| 70726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70727 | // (vselect:{ *:[nxv16i32] } V0:{ *:[nxv16i1] }, VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 70728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 70729 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70730 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70732 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70733 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70734 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70737 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70738 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70739 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70740 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70743 | GIR_RootConstrainSelectedInstOperands, |
| 70744 | // GIR_Coverage, 52972, |
| 70745 | GIR_EraseRootFromParent_Done, |
| 70746 | // Label 4689: @180605 |
| 70747 | GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(180667), // Rule ID 52973 // |
| 70748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70749 | // (vselect:{ *:[nxv16i32] } V0:{ *:[nxv16i1] }, VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 70750 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 70751 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70752 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70755 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70756 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70759 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70760 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70761 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70762 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70765 | GIR_RootConstrainSelectedInstOperands, |
| 70766 | // GIR_Coverage, 52973, |
| 70767 | GIR_EraseRootFromParent_Done, |
| 70768 | // Label 4690: @180667 |
| 70769 | GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(180729), // Rule ID 58634 // |
| 70770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70771 | // (vselect:{ *:[nxv16f32] } V0:{ *:[nxv16i1] }, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs2, VRM8:{ *:[nxv16f32] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i64] }, 5:{ *:[i64] }) |
| 70772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 70773 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70774 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70776 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70777 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70778 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70781 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70782 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70783 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70784 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70787 | GIR_RootConstrainSelectedInstOperands, |
| 70788 | // GIR_Coverage, 58634, |
| 70789 | GIR_EraseRootFromParent_Done, |
| 70790 | // Label 4691: @180729 |
| 70791 | GIM_Try, /*On fail goto*//*Label 4692*/ GIMT_Encode4(180791), // Rule ID 58635 // |
| 70792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70793 | // (vselect:{ *:[nxv16f32] } V0:{ *:[nxv16i1] }, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs2, VRM8:{ *:[nxv16f32] }:$rs1, V0:{ *:[nxv16i1] }, -1:{ *:[i32] }, 5:{ *:[i32] }) |
| 70794 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 70795 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70796 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70797 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70798 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70799 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70800 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70803 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70804 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70805 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70806 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 70809 | GIR_RootConstrainSelectedInstOperands, |
| 70810 | // GIR_Coverage, 58635, |
| 70811 | GIR_EraseRootFromParent_Done, |
| 70812 | // Label 4692: @180791 |
| 70813 | GIM_Reject, |
| 70814 | // Label 4688: @180792 |
| 70815 | GIM_Reject, |
| 70816 | // Label 4581: @180793 |
| 70817 | GIM_Try, /*On fail goto*//*Label 4693*/ GIMT_Encode4(180948), |
| 70818 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 70819 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 70820 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s8, |
| 70821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4NoV0RegClassID), |
| 70822 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70823 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70824 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 70825 | GIM_Try, /*On fail goto*//*Label 4694*/ GIMT_Encode4(180885), // Rule ID 52930 // |
| 70826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70827 | // (vselect:{ *:[nxv32i8] } V0:{ *:[nxv32i1] }, VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 70828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 70829 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70830 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70832 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70833 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70834 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70837 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70838 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70839 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70840 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 70843 | GIR_RootConstrainSelectedInstOperands, |
| 70844 | // GIR_Coverage, 52930, |
| 70845 | GIR_EraseRootFromParent_Done, |
| 70846 | // Label 4694: @180885 |
| 70847 | GIM_Try, /*On fail goto*//*Label 4695*/ GIMT_Encode4(180947), // Rule ID 52931 // |
| 70848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70849 | // (vselect:{ *:[nxv32i8] } V0:{ *:[nxv32i1] }, VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMERGE_VVM_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 70850 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 70851 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70852 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70854 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70855 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70856 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M4), |
| 70858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70859 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70860 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70861 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70862 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 70865 | GIR_RootConstrainSelectedInstOperands, |
| 70866 | // GIR_Coverage, 52931, |
| 70867 | GIR_EraseRootFromParent_Done, |
| 70868 | // Label 4695: @180947 |
| 70869 | GIM_Reject, |
| 70870 | // Label 4693: @180948 |
| 70871 | GIM_Reject, |
| 70872 | // Label 4582: @180949 |
| 70873 | GIM_Try, /*On fail goto*//*Label 4696*/ GIMT_Encode4(181352), |
| 70874 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s1, |
| 70875 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 70876 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 70877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8NoV0RegClassID), |
| 70878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 70879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 70880 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 70881 | GIM_Try, /*On fail goto*//*Label 4697*/ GIMT_Encode4(181041), // Rule ID 52954 // |
| 70882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70883 | // (vselect:{ *:[nxv32i16] } V0:{ *:[nxv32i1] }, VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70884 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 70885 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70886 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70888 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70889 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70890 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70893 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70894 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70895 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70896 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70899 | GIR_RootConstrainSelectedInstOperands, |
| 70900 | // GIR_Coverage, 52954, |
| 70901 | GIR_EraseRootFromParent_Done, |
| 70902 | // Label 4697: @181041 |
| 70903 | GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(181103), // Rule ID 52955 // |
| 70904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70905 | // (vselect:{ *:[nxv32i16] } V0:{ *:[nxv32i1] }, VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70906 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 70907 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70908 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70909 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70910 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70911 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70912 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70915 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70916 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70917 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70918 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70921 | GIR_RootConstrainSelectedInstOperands, |
| 70922 | // GIR_Coverage, 52955, |
| 70923 | GIR_EraseRootFromParent_Done, |
| 70924 | // Label 4698: @181103 |
| 70925 | GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(181165), // Rule ID 58604 // |
| 70926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70927 | // (vselect:{ *:[nxv32f16] } V0:{ *:[nxv32i1] }, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs2, VRM8:{ *:[nxv32f16] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 70929 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70930 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70933 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70934 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70938 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70939 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70940 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70943 | GIR_RootConstrainSelectedInstOperands, |
| 70944 | // GIR_Coverage, 58604, |
| 70945 | GIR_EraseRootFromParent_Done, |
| 70946 | // Label 4699: @181165 |
| 70947 | GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(181227), // Rule ID 58605 // |
| 70948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70949 | // (vselect:{ *:[nxv32f16] } V0:{ *:[nxv32i1] }, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs2, VRM8:{ *:[nxv32f16] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70950 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 70951 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70952 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70954 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70955 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70956 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70960 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70961 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70962 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70965 | GIR_RootConstrainSelectedInstOperands, |
| 70966 | // GIR_Coverage, 58605, |
| 70967 | GIR_EraseRootFromParent_Done, |
| 70968 | // Label 4700: @181227 |
| 70969 | GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(181289), // Rule ID 58724 // |
| 70970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 70971 | // (vselect:{ *:[nxv32bf16] } V0:{ *:[nxv32i1] }, VRM8:{ *:[nxv32bf16] }:$rs1, VRM8:{ *:[nxv32bf16] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv32bf16] } (IMPLICIT_DEF:{ *:[nxv32bf16] }), VRM8:{ *:[nxv32bf16] }:$rs2, VRM8:{ *:[nxv32bf16] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i64] }, 4:{ *:[i64] }) |
| 70972 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 70973 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70974 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70976 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70977 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70978 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 70979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 70980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 70981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 70982 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 70983 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 70984 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 70987 | GIR_RootConstrainSelectedInstOperands, |
| 70988 | // GIR_Coverage, 58724, |
| 70989 | GIR_EraseRootFromParent_Done, |
| 70990 | // Label 4701: @181289 |
| 70991 | GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(181351), // Rule ID 58725 // |
| 70992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 70993 | // (vselect:{ *:[nxv32bf16] } V0:{ *:[nxv32i1] }, VRM8:{ *:[nxv32bf16] }:$rs1, VRM8:{ *:[nxv32bf16] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv32bf16] } (IMPLICIT_DEF:{ *:[nxv32bf16] }), VRM8:{ *:[nxv32bf16] }:$rs2, VRM8:{ *:[nxv32bf16] }:$rs1, V0:{ *:[nxv32i1] }, -1:{ *:[i32] }, 4:{ *:[i32] }) |
| 70994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 70995 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 70996 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 70997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 70998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70999 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 71000 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 71001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 71002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71003 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71004 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 71005 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 71006 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 71007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71009 | GIR_RootConstrainSelectedInstOperands, |
| 71010 | // GIR_Coverage, 58725, |
| 71011 | GIR_EraseRootFromParent_Done, |
| 71012 | // Label 4702: @181351 |
| 71013 | GIM_Reject, |
| 71014 | // Label 4696: @181352 |
| 71015 | GIM_Reject, |
| 71016 | // Label 4583: @181353 |
| 71017 | GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(181508), |
| 71018 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s1, |
| 71019 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 71020 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv64s8, |
| 71021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8NoV0RegClassID), |
| 71022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VMV0RegClassID), |
| 71023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 71024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 71025 | GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(181445), // Rule ID 52936 // |
| 71026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71027 | // (vselect:{ *:[nxv64i8] } V0:{ *:[nxv64i1] }, VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, V0:{ *:[nxv64i1] }, -1:{ *:[i64] }, 3:{ *:[i64] }) |
| 71028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 71029 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71030 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 71032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 71033 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 71034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 71035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 71036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71037 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71038 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 71039 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 71040 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 71041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71043 | GIR_RootConstrainSelectedInstOperands, |
| 71044 | // GIR_Coverage, 52936, |
| 71045 | GIR_EraseRootFromParent_Done, |
| 71046 | // Label 4704: @181445 |
| 71047 | GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(181507), // Rule ID 52937 // |
| 71048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71049 | // (vselect:{ *:[nxv64i8] } V0:{ *:[nxv64i1] }, VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMERGE_VVM_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, V0:{ *:[nxv64i1] }, -1:{ *:[i32] }, 3:{ *:[i32] }) |
| 71050 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 71051 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71052 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 71054 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 71055 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 71056 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // V0 |
| 71057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMERGE_VVM_M8), |
| 71058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71060 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 71061 | GIR_RootToRootCopy, /*OpIdx*/2, // rs1 |
| 71062 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::V0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 71063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71065 | GIR_RootConstrainSelectedInstOperands, |
| 71066 | // GIR_Coverage, 52937, |
| 71067 | GIR_EraseRootFromParent_Done, |
| 71068 | // Label 4705: @181507 |
| 71069 | GIM_Reject, |
| 71070 | // Label 4703: @181508 |
| 71071 | GIM_Reject, |
| 71072 | // Label 4584: @181509 |
| 71073 | GIM_Reject, |
| 71074 | // Label 47: @181510 |
| 71075 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 4730*/ GIMT_Encode4(184243), |
| 71076 | /*GILLT_s32*//*Label 4706*/ GIMT_Encode4(181645), |
| 71077 | /*GILLT_s64*//*Label 4707*/ GIMT_Encode4(181679), GIMT_Encode4(0), |
| 71078 | /*GILLT_nxv1s8*//*Label 4708*/ GIMT_Encode4(181713), |
| 71079 | /*GILLT_nxv1s16*//*Label 4709*/ GIMT_Encode4(181828), |
| 71080 | /*GILLT_nxv1s32*//*Label 4710*/ GIMT_Encode4(181943), |
| 71081 | /*GILLT_nxv1s64*//*Label 4711*/ GIMT_Encode4(182058), GIMT_Encode4(0), |
| 71082 | /*GILLT_nxv2s8*//*Label 4712*/ GIMT_Encode4(182173), |
| 71083 | /*GILLT_nxv2s16*//*Label 4713*/ GIMT_Encode4(182288), |
| 71084 | /*GILLT_nxv2s32*//*Label 4714*/ GIMT_Encode4(182403), |
| 71085 | /*GILLT_nxv2s64*//*Label 4715*/ GIMT_Encode4(182518), GIMT_Encode4(0), |
| 71086 | /*GILLT_nxv4s8*//*Label 4716*/ GIMT_Encode4(182633), |
| 71087 | /*GILLT_nxv4s16*//*Label 4717*/ GIMT_Encode4(182748), |
| 71088 | /*GILLT_nxv4s32*//*Label 4718*/ GIMT_Encode4(182863), |
| 71089 | /*GILLT_nxv4s64*//*Label 4719*/ GIMT_Encode4(182978), GIMT_Encode4(0), |
| 71090 | /*GILLT_nxv8s8*//*Label 4720*/ GIMT_Encode4(183093), |
| 71091 | /*GILLT_nxv8s16*//*Label 4721*/ GIMT_Encode4(183208), |
| 71092 | /*GILLT_nxv8s32*//*Label 4722*/ GIMT_Encode4(183323), |
| 71093 | /*GILLT_nxv8s64*//*Label 4723*/ GIMT_Encode4(183438), GIMT_Encode4(0), |
| 71094 | /*GILLT_nxv16s8*//*Label 4724*/ GIMT_Encode4(183553), |
| 71095 | /*GILLT_nxv16s16*//*Label 4725*/ GIMT_Encode4(183668), |
| 71096 | /*GILLT_nxv16s32*//*Label 4726*/ GIMT_Encode4(183783), GIMT_Encode4(0), |
| 71097 | /*GILLT_nxv32s8*//*Label 4727*/ GIMT_Encode4(183898), |
| 71098 | /*GILLT_nxv32s16*//*Label 4728*/ GIMT_Encode4(184013), GIMT_Encode4(0), |
| 71099 | /*GILLT_nxv64s8*//*Label 4729*/ GIMT_Encode4(184128), |
| 71100 | // Label 4706: @181645 |
| 71101 | GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(181678), // Rule ID 329 // |
| 71102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode1), |
| 71103 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 71104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 71105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 71106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 71107 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 71108 | // (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 71109 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULHU), |
| 71110 | GIR_RootConstrainSelectedInstOperands, |
| 71111 | // GIR_Coverage, 329, |
| 71112 | GIR_Done, |
| 71113 | // Label 4731: @181678 |
| 71114 | GIM_Reject, |
| 71115 | // Label 4707: @181679 |
| 71116 | GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(181712), // Rule ID 328 // |
| 71117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode0), |
| 71118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 71119 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 71120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 71121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 71122 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 71123 | // (mulhu:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MULHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 71124 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULHU), |
| 71125 | GIR_RootConstrainSelectedInstOperands, |
| 71126 | // GIR_Coverage, 328, |
| 71127 | GIR_Done, |
| 71128 | // Label 4732: @181712 |
| 71129 | GIM_Reject, |
| 71130 | // Label 4708: @181713 |
| 71131 | GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(181827), |
| 71132 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 71133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 71134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71136 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71137 | GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(181781), // Rule ID 51640 // |
| 71138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71139 | // (mulhu:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMULHU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 71140 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 71141 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71142 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF8), |
| 71145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71146 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71147 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71148 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71152 | GIR_RootConstrainSelectedInstOperands, |
| 71153 | // GIR_Coverage, 51640, |
| 71154 | GIR_EraseRootFromParent_Done, |
| 71155 | // Label 4734: @181781 |
| 71156 | GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(181826), // Rule ID 51641 // |
| 71157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71158 | // (mulhu:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMULHU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 71159 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 71160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF8), |
| 71164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71166 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71167 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71171 | GIR_RootConstrainSelectedInstOperands, |
| 71172 | // GIR_Coverage, 51641, |
| 71173 | GIR_EraseRootFromParent_Done, |
| 71174 | // Label 4735: @181826 |
| 71175 | GIM_Reject, |
| 71176 | // Label 4733: @181827 |
| 71177 | GIM_Reject, |
| 71178 | // Label 4709: @181828 |
| 71179 | GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(181942), |
| 71180 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 71181 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 71182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71183 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71184 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71185 | GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(181896), // Rule ID 51652 // |
| 71186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71187 | // (mulhu:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMULHU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 71188 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 71189 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71190 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF4), |
| 71193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71194 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71196 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71200 | GIR_RootConstrainSelectedInstOperands, |
| 71201 | // GIR_Coverage, 51652, |
| 71202 | GIR_EraseRootFromParent_Done, |
| 71203 | // Label 4737: @181896 |
| 71204 | GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(181941), // Rule ID 51653 // |
| 71205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71206 | // (mulhu:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMULHU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 71207 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 71208 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71209 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF4), |
| 71212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71213 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71214 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71215 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71219 | GIR_RootConstrainSelectedInstOperands, |
| 71220 | // GIR_Coverage, 51653, |
| 71221 | GIR_EraseRootFromParent_Done, |
| 71222 | // Label 4738: @181941 |
| 71223 | GIM_Reject, |
| 71224 | // Label 4736: @181942 |
| 71225 | GIM_Reject, |
| 71226 | // Label 4710: @181943 |
| 71227 | GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(182057), |
| 71228 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 71229 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 71230 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71231 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71232 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71233 | GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(182011), // Rule ID 51660 // |
| 71234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71235 | // (mulhu:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMULHU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 71236 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 71237 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71238 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF2), |
| 71241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71242 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71243 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71244 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71248 | GIR_RootConstrainSelectedInstOperands, |
| 71249 | // GIR_Coverage, 51660, |
| 71250 | GIR_EraseRootFromParent_Done, |
| 71251 | // Label 4740: @182011 |
| 71252 | GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(182056), // Rule ID 51661 // |
| 71253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71254 | // (mulhu:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMULHU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 71255 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 71256 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71257 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71258 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF2), |
| 71260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71261 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71262 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71263 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71267 | GIR_RootConstrainSelectedInstOperands, |
| 71268 | // GIR_Coverage, 51661, |
| 71269 | GIR_EraseRootFromParent_Done, |
| 71270 | // Label 4741: @182056 |
| 71271 | GIM_Reject, |
| 71272 | // Label 4739: @182057 |
| 71273 | GIM_Reject, |
| 71274 | // Label 4711: @182058 |
| 71275 | GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(182172), |
| 71276 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 71277 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 71278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71279 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71280 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71281 | GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(182126), // Rule ID 51728 // |
| 71282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 71283 | // (mulhu:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 71284 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 71285 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71286 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71287 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71290 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71291 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71292 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71296 | GIR_RootConstrainSelectedInstOperands, |
| 71297 | // GIR_Coverage, 51728, |
| 71298 | GIR_EraseRootFromParent_Done, |
| 71299 | // Label 4743: @182126 |
| 71300 | GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(182171), // Rule ID 51729 // |
| 71301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 71302 | // (mulhu:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 71303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 71304 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71305 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71310 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71311 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71315 | GIR_RootConstrainSelectedInstOperands, |
| 71316 | // GIR_Coverage, 51729, |
| 71317 | GIR_EraseRootFromParent_Done, |
| 71318 | // Label 4744: @182171 |
| 71319 | GIM_Reject, |
| 71320 | // Label 4742: @182172 |
| 71321 | GIM_Reject, |
| 71322 | // Label 4712: @182173 |
| 71323 | GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(182287), |
| 71324 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 71325 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 71326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71327 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71328 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71329 | GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(182241), // Rule ID 51644 // |
| 71330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71331 | // (mulhu:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMULHU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 71332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 71333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF4), |
| 71337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71339 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71340 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71344 | GIR_RootConstrainSelectedInstOperands, |
| 71345 | // GIR_Coverage, 51644, |
| 71346 | GIR_EraseRootFromParent_Done, |
| 71347 | // Label 4746: @182241 |
| 71348 | GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(182286), // Rule ID 51645 // |
| 71349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71350 | // (mulhu:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMULHU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 71351 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 71352 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71353 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71354 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF4), |
| 71356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71357 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71358 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71359 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71363 | GIR_RootConstrainSelectedInstOperands, |
| 71364 | // GIR_Coverage, 51645, |
| 71365 | GIR_EraseRootFromParent_Done, |
| 71366 | // Label 4747: @182286 |
| 71367 | GIM_Reject, |
| 71368 | // Label 4745: @182287 |
| 71369 | GIM_Reject, |
| 71370 | // Label 4713: @182288 |
| 71371 | GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(182402), |
| 71372 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 71373 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 71374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71375 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71377 | GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(182356), // Rule ID 51656 // |
| 71378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71379 | // (mulhu:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMULHU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 71380 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 71381 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71382 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF2), |
| 71385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71386 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71387 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71388 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71392 | GIR_RootConstrainSelectedInstOperands, |
| 71393 | // GIR_Coverage, 51656, |
| 71394 | GIR_EraseRootFromParent_Done, |
| 71395 | // Label 4749: @182356 |
| 71396 | GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(182401), // Rule ID 51657 // |
| 71397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71398 | // (mulhu:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMULHU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 71399 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 71400 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71401 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF2), |
| 71404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71405 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71406 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71407 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71411 | GIR_RootConstrainSelectedInstOperands, |
| 71412 | // GIR_Coverage, 51657, |
| 71413 | GIR_EraseRootFromParent_Done, |
| 71414 | // Label 4750: @182401 |
| 71415 | GIM_Reject, |
| 71416 | // Label 4748: @182402 |
| 71417 | GIM_Reject, |
| 71418 | // Label 4714: @182403 |
| 71419 | GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(182517), |
| 71420 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 71421 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 71422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71423 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71424 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71425 | GIM_Try, /*On fail goto*//*Label 4752*/ GIMT_Encode4(182471), // Rule ID 51672 // |
| 71426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71427 | // (mulhu:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 71428 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 71429 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71430 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71434 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71435 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71436 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71440 | GIR_RootConstrainSelectedInstOperands, |
| 71441 | // GIR_Coverage, 51672, |
| 71442 | GIR_EraseRootFromParent_Done, |
| 71443 | // Label 4752: @182471 |
| 71444 | GIM_Try, /*On fail goto*//*Label 4753*/ GIMT_Encode4(182516), // Rule ID 51673 // |
| 71445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71446 | // (mulhu:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 71447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 71448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71449 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71450 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71453 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71454 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71455 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71459 | GIR_RootConstrainSelectedInstOperands, |
| 71460 | // GIR_Coverage, 51673, |
| 71461 | GIR_EraseRootFromParent_Done, |
| 71462 | // Label 4753: @182516 |
| 71463 | GIM_Reject, |
| 71464 | // Label 4751: @182517 |
| 71465 | GIM_Reject, |
| 71466 | // Label 4715: @182518 |
| 71467 | GIM_Try, /*On fail goto*//*Label 4754*/ GIMT_Encode4(182632), |
| 71468 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 71469 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 71470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71471 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71472 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71473 | GIM_Try, /*On fail goto*//*Label 4755*/ GIMT_Encode4(182586), // Rule ID 51732 // |
| 71474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 71475 | // (mulhu:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 71476 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 71477 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71478 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71482 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71483 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71484 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71488 | GIR_RootConstrainSelectedInstOperands, |
| 71489 | // GIR_Coverage, 51732, |
| 71490 | GIR_EraseRootFromParent_Done, |
| 71491 | // Label 4755: @182586 |
| 71492 | GIM_Try, /*On fail goto*//*Label 4756*/ GIMT_Encode4(182631), // Rule ID 51733 // |
| 71493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 71494 | // (mulhu:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 71495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 71496 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71497 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71498 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71501 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71502 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71503 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71507 | GIR_RootConstrainSelectedInstOperands, |
| 71508 | // GIR_Coverage, 51733, |
| 71509 | GIR_EraseRootFromParent_Done, |
| 71510 | // Label 4756: @182631 |
| 71511 | GIM_Reject, |
| 71512 | // Label 4754: @182632 |
| 71513 | GIM_Reject, |
| 71514 | // Label 4716: @182633 |
| 71515 | GIM_Try, /*On fail goto*//*Label 4757*/ GIMT_Encode4(182747), |
| 71516 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 71517 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 71518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71519 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71520 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71521 | GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(182701), // Rule ID 51648 // |
| 71522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71523 | // (mulhu:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMULHU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 71524 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 71525 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71526 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF2), |
| 71529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71530 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71531 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71532 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71536 | GIR_RootConstrainSelectedInstOperands, |
| 71537 | // GIR_Coverage, 51648, |
| 71538 | GIR_EraseRootFromParent_Done, |
| 71539 | // Label 4758: @182701 |
| 71540 | GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(182746), // Rule ID 51649 // |
| 71541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71542 | // (mulhu:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMULHU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 71543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 71544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_MF2), |
| 71548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71550 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71551 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71555 | GIR_RootConstrainSelectedInstOperands, |
| 71556 | // GIR_Coverage, 51649, |
| 71557 | GIR_EraseRootFromParent_Done, |
| 71558 | // Label 4759: @182746 |
| 71559 | GIM_Reject, |
| 71560 | // Label 4757: @182747 |
| 71561 | GIM_Reject, |
| 71562 | // Label 4717: @182748 |
| 71563 | GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(182862), |
| 71564 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 71565 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 71566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71567 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71568 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71569 | GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(182816), // Rule ID 51668 // |
| 71570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71571 | // (mulhu:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 71572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 71573 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71574 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71578 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71579 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71580 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71584 | GIR_RootConstrainSelectedInstOperands, |
| 71585 | // GIR_Coverage, 51668, |
| 71586 | GIR_EraseRootFromParent_Done, |
| 71587 | // Label 4761: @182816 |
| 71588 | GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(182861), // Rule ID 51669 // |
| 71589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71590 | // (mulhu:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 71591 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 71592 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71593 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71594 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71597 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71598 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71599 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71603 | GIR_RootConstrainSelectedInstOperands, |
| 71604 | // GIR_Coverage, 51669, |
| 71605 | GIR_EraseRootFromParent_Done, |
| 71606 | // Label 4762: @182861 |
| 71607 | GIM_Reject, |
| 71608 | // Label 4760: @182862 |
| 71609 | GIM_Reject, |
| 71610 | // Label 4718: @182863 |
| 71611 | GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(182977), |
| 71612 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 71613 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 71614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71615 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71616 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71617 | GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(182931), // Rule ID 51700 // |
| 71618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71619 | // (mulhu:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 71620 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 71621 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71622 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71626 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71627 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71628 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71632 | GIR_RootConstrainSelectedInstOperands, |
| 71633 | // GIR_Coverage, 51700, |
| 71634 | GIR_EraseRootFromParent_Done, |
| 71635 | // Label 4764: @182931 |
| 71636 | GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(182976), // Rule ID 51701 // |
| 71637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71638 | // (mulhu:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 71639 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 71640 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71641 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71646 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71647 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71651 | GIR_RootConstrainSelectedInstOperands, |
| 71652 | // GIR_Coverage, 51701, |
| 71653 | GIR_EraseRootFromParent_Done, |
| 71654 | // Label 4765: @182976 |
| 71655 | GIM_Reject, |
| 71656 | // Label 4763: @182977 |
| 71657 | GIM_Reject, |
| 71658 | // Label 4719: @182978 |
| 71659 | GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(183092), |
| 71660 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 71661 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 71662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71664 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71665 | GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(183046), // Rule ID 51736 // |
| 71666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 71667 | // (mulhu:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 71668 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 71669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71670 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 71673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71674 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71675 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71676 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71680 | GIR_RootConstrainSelectedInstOperands, |
| 71681 | // GIR_Coverage, 51736, |
| 71682 | GIR_EraseRootFromParent_Done, |
| 71683 | // Label 4767: @183046 |
| 71684 | GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(183091), // Rule ID 51737 // |
| 71685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 71686 | // (mulhu:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 71687 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 71688 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71689 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71690 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 71692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71693 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71694 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71695 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71699 | GIR_RootConstrainSelectedInstOperands, |
| 71700 | // GIR_Coverage, 51737, |
| 71701 | GIR_EraseRootFromParent_Done, |
| 71702 | // Label 4768: @183091 |
| 71703 | GIM_Reject, |
| 71704 | // Label 4766: @183092 |
| 71705 | GIM_Reject, |
| 71706 | // Label 4720: @183093 |
| 71707 | GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(183207), |
| 71708 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 71709 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 71710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71711 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71712 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 71713 | GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(183161), // Rule ID 51664 // |
| 71714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71715 | // (mulhu:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 71716 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 71717 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71718 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71722 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71723 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71724 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71728 | GIR_RootConstrainSelectedInstOperands, |
| 71729 | // GIR_Coverage, 51664, |
| 71730 | GIR_EraseRootFromParent_Done, |
| 71731 | // Label 4770: @183161 |
| 71732 | GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(183206), // Rule ID 51665 // |
| 71733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71734 | // (mulhu:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMULHU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 71735 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 71736 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71737 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M1), |
| 71740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71742 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71743 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71747 | GIR_RootConstrainSelectedInstOperands, |
| 71748 | // GIR_Coverage, 51665, |
| 71749 | GIR_EraseRootFromParent_Done, |
| 71750 | // Label 4771: @183206 |
| 71751 | GIM_Reject, |
| 71752 | // Label 4769: @183207 |
| 71753 | GIM_Reject, |
| 71754 | // Label 4721: @183208 |
| 71755 | GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(183322), |
| 71756 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 71757 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 71758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71761 | GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(183276), // Rule ID 51688 // |
| 71762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71763 | // (mulhu:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 71764 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 71765 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71771 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71772 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71776 | GIR_RootConstrainSelectedInstOperands, |
| 71777 | // GIR_Coverage, 51688, |
| 71778 | GIR_EraseRootFromParent_Done, |
| 71779 | // Label 4773: @183276 |
| 71780 | GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(183321), // Rule ID 51689 // |
| 71781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71782 | // (mulhu:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 71783 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 71784 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71785 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71786 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71789 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71790 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71791 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71795 | GIR_RootConstrainSelectedInstOperands, |
| 71796 | // GIR_Coverage, 51689, |
| 71797 | GIR_EraseRootFromParent_Done, |
| 71798 | // Label 4774: @183321 |
| 71799 | GIM_Reject, |
| 71800 | // Label 4772: @183322 |
| 71801 | GIM_Reject, |
| 71802 | // Label 4722: @183323 |
| 71803 | GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(183437), |
| 71804 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 71805 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 71806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71807 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71808 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71809 | GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(183391), // Rule ID 51704 // |
| 71810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71811 | // (mulhu:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 71812 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 71813 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71814 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 71817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71818 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71819 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71820 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71824 | GIR_RootConstrainSelectedInstOperands, |
| 71825 | // GIR_Coverage, 51704, |
| 71826 | GIR_EraseRootFromParent_Done, |
| 71827 | // Label 4776: @183391 |
| 71828 | GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(183436), // Rule ID 51705 // |
| 71829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71830 | // (mulhu:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 71831 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 71832 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71833 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71834 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 71836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71837 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71838 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71839 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 71842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71843 | GIR_RootConstrainSelectedInstOperands, |
| 71844 | // GIR_Coverage, 51705, |
| 71845 | GIR_EraseRootFromParent_Done, |
| 71846 | // Label 4777: @183436 |
| 71847 | GIM_Reject, |
| 71848 | // Label 4775: @183437 |
| 71849 | GIM_Reject, |
| 71850 | // Label 4723: @183438 |
| 71851 | GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(183552), |
| 71852 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 71853 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 71854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 71855 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 71856 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 71857 | GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(183506), // Rule ID 51740 // |
| 71858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 71859 | // (mulhu:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 71860 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 71861 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71862 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 71865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71866 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71867 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71868 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71872 | GIR_RootConstrainSelectedInstOperands, |
| 71873 | // GIR_Coverage, 51740, |
| 71874 | GIR_EraseRootFromParent_Done, |
| 71875 | // Label 4779: @183506 |
| 71876 | GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(183551), // Rule ID 51741 // |
| 71877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 71878 | // (mulhu:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 71879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 71880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71881 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 71884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71885 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71886 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71887 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 71890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71891 | GIR_RootConstrainSelectedInstOperands, |
| 71892 | // GIR_Coverage, 51741, |
| 71893 | GIR_EraseRootFromParent_Done, |
| 71894 | // Label 4780: @183551 |
| 71895 | GIM_Reject, |
| 71896 | // Label 4778: @183552 |
| 71897 | GIM_Reject, |
| 71898 | // Label 4724: @183553 |
| 71899 | GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(183667), |
| 71900 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 71901 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 71902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71903 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71904 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 71905 | GIM_Try, /*On fail goto*//*Label 4782*/ GIMT_Encode4(183621), // Rule ID 51676 // |
| 71906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71907 | // (mulhu:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 71908 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 71909 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71910 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71914 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71915 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71916 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71920 | GIR_RootConstrainSelectedInstOperands, |
| 71921 | // GIR_Coverage, 51676, |
| 71922 | GIR_EraseRootFromParent_Done, |
| 71923 | // Label 4782: @183621 |
| 71924 | GIM_Try, /*On fail goto*//*Label 4783*/ GIMT_Encode4(183666), // Rule ID 51677 // |
| 71925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71926 | // (mulhu:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMULHU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 71927 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 71928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M2), |
| 71932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71933 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71934 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71935 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71939 | GIR_RootConstrainSelectedInstOperands, |
| 71940 | // GIR_Coverage, 51677, |
| 71941 | GIR_EraseRootFromParent_Done, |
| 71942 | // Label 4783: @183666 |
| 71943 | GIM_Reject, |
| 71944 | // Label 4781: @183667 |
| 71945 | GIM_Reject, |
| 71946 | // Label 4725: @183668 |
| 71947 | GIM_Try, /*On fail goto*//*Label 4784*/ GIMT_Encode4(183782), |
| 71948 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 71949 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 71950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71951 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71952 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 71953 | GIM_Try, /*On fail goto*//*Label 4785*/ GIMT_Encode4(183736), // Rule ID 51692 // |
| 71954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 71955 | // (mulhu:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 71956 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 71957 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71958 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71959 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 71961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71962 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71963 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71964 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71968 | GIR_RootConstrainSelectedInstOperands, |
| 71969 | // GIR_Coverage, 51692, |
| 71970 | GIR_EraseRootFromParent_Done, |
| 71971 | // Label 4785: @183736 |
| 71972 | GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(183781), // Rule ID 51693 // |
| 71973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 71974 | // (mulhu:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 71975 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 71976 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 71977 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 71980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 71981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 71982 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 71983 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 71984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 71985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 71986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 71987 | GIR_RootConstrainSelectedInstOperands, |
| 71988 | // GIR_Coverage, 51693, |
| 71989 | GIR_EraseRootFromParent_Done, |
| 71990 | // Label 4786: @183781 |
| 71991 | GIM_Reject, |
| 71992 | // Label 4784: @183782 |
| 71993 | GIM_Reject, |
| 71994 | // Label 4726: @183783 |
| 71995 | GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(183897), |
| 71996 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 71997 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 71998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 71999 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72000 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72001 | GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(183851), // Rule ID 51708 // |
| 72002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72003 | // (mulhu:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 72004 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 72005 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72006 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 72009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72010 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72011 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72012 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72016 | GIR_RootConstrainSelectedInstOperands, |
| 72017 | // GIR_Coverage, 51708, |
| 72018 | GIR_EraseRootFromParent_Done, |
| 72019 | // Label 4788: @183851 |
| 72020 | GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(183896), // Rule ID 51709 // |
| 72021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72022 | // (mulhu:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 72023 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 72024 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72025 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 72028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72029 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72030 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72031 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72035 | GIR_RootConstrainSelectedInstOperands, |
| 72036 | // GIR_Coverage, 51709, |
| 72037 | GIR_EraseRootFromParent_Done, |
| 72038 | // Label 4789: @183896 |
| 72039 | GIM_Reject, |
| 72040 | // Label 4787: @183897 |
| 72041 | GIM_Reject, |
| 72042 | // Label 4727: @183898 |
| 72043 | GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(184012), |
| 72044 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 72045 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 72046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72047 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72048 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72049 | GIM_Try, /*On fail goto*//*Label 4791*/ GIMT_Encode4(183966), // Rule ID 51680 // |
| 72050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72051 | // (mulhu:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 72052 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 72053 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72054 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 72057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72058 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72059 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72060 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72064 | GIR_RootConstrainSelectedInstOperands, |
| 72065 | // GIR_Coverage, 51680, |
| 72066 | GIR_EraseRootFromParent_Done, |
| 72067 | // Label 4791: @183966 |
| 72068 | GIM_Try, /*On fail goto*//*Label 4792*/ GIMT_Encode4(184011), // Rule ID 51681 // |
| 72069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72070 | // (mulhu:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMULHU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 72071 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 72072 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72073 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M4), |
| 72076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72077 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72078 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72079 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72083 | GIR_RootConstrainSelectedInstOperands, |
| 72084 | // GIR_Coverage, 51681, |
| 72085 | GIR_EraseRootFromParent_Done, |
| 72086 | // Label 4792: @184011 |
| 72087 | GIM_Reject, |
| 72088 | // Label 4790: @184012 |
| 72089 | GIM_Reject, |
| 72090 | // Label 4728: @184013 |
| 72091 | GIM_Try, /*On fail goto*//*Label 4793*/ GIMT_Encode4(184127), |
| 72092 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 72093 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 72094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72095 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72096 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72097 | GIM_Try, /*On fail goto*//*Label 4794*/ GIMT_Encode4(184081), // Rule ID 51696 // |
| 72098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72099 | // (mulhu:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 72100 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 72101 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72102 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 72105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72106 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72107 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72108 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72112 | GIR_RootConstrainSelectedInstOperands, |
| 72113 | // GIR_Coverage, 51696, |
| 72114 | GIR_EraseRootFromParent_Done, |
| 72115 | // Label 4794: @184081 |
| 72116 | GIM_Try, /*On fail goto*//*Label 4795*/ GIMT_Encode4(184126), // Rule ID 51697 // |
| 72117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72118 | // (mulhu:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 72119 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 72120 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72121 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 72124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72125 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72126 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72127 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72131 | GIR_RootConstrainSelectedInstOperands, |
| 72132 | // GIR_Coverage, 51697, |
| 72133 | GIR_EraseRootFromParent_Done, |
| 72134 | // Label 4795: @184126 |
| 72135 | GIM_Reject, |
| 72136 | // Label 4793: @184127 |
| 72137 | GIM_Reject, |
| 72138 | // Label 4729: @184128 |
| 72139 | GIM_Try, /*On fail goto*//*Label 4796*/ GIMT_Encode4(184242), |
| 72140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 72141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 72142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72144 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72145 | GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(184196), // Rule ID 51684 // |
| 72146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72147 | // (mulhu:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 72148 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 72149 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72150 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 72153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72154 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72156 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72160 | GIR_RootConstrainSelectedInstOperands, |
| 72161 | // GIR_Coverage, 51684, |
| 72162 | GIR_EraseRootFromParent_Done, |
| 72163 | // Label 4797: @184196 |
| 72164 | GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(184241), // Rule ID 51685 // |
| 72165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72166 | // (mulhu:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMULHU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 72167 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 72168 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72169 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULHU_VV_M8), |
| 72172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72174 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72175 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72179 | GIR_RootConstrainSelectedInstOperands, |
| 72180 | // GIR_Coverage, 51685, |
| 72181 | GIR_EraseRootFromParent_Done, |
| 72182 | // Label 4798: @184241 |
| 72183 | GIM_Reject, |
| 72184 | // Label 4796: @184242 |
| 72185 | GIM_Reject, |
| 72186 | // Label 4730: @184243 |
| 72187 | GIM_Reject, |
| 72188 | // Label 48: @184244 |
| 72189 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 4823*/ GIMT_Encode4(186977), |
| 72190 | /*GILLT_s32*//*Label 4799*/ GIMT_Encode4(184379), |
| 72191 | /*GILLT_s64*//*Label 4800*/ GIMT_Encode4(184413), GIMT_Encode4(0), |
| 72192 | /*GILLT_nxv1s8*//*Label 4801*/ GIMT_Encode4(184447), |
| 72193 | /*GILLT_nxv1s16*//*Label 4802*/ GIMT_Encode4(184562), |
| 72194 | /*GILLT_nxv1s32*//*Label 4803*/ GIMT_Encode4(184677), |
| 72195 | /*GILLT_nxv1s64*//*Label 4804*/ GIMT_Encode4(184792), GIMT_Encode4(0), |
| 72196 | /*GILLT_nxv2s8*//*Label 4805*/ GIMT_Encode4(184907), |
| 72197 | /*GILLT_nxv2s16*//*Label 4806*/ GIMT_Encode4(185022), |
| 72198 | /*GILLT_nxv2s32*//*Label 4807*/ GIMT_Encode4(185137), |
| 72199 | /*GILLT_nxv2s64*//*Label 4808*/ GIMT_Encode4(185252), GIMT_Encode4(0), |
| 72200 | /*GILLT_nxv4s8*//*Label 4809*/ GIMT_Encode4(185367), |
| 72201 | /*GILLT_nxv4s16*//*Label 4810*/ GIMT_Encode4(185482), |
| 72202 | /*GILLT_nxv4s32*//*Label 4811*/ GIMT_Encode4(185597), |
| 72203 | /*GILLT_nxv4s64*//*Label 4812*/ GIMT_Encode4(185712), GIMT_Encode4(0), |
| 72204 | /*GILLT_nxv8s8*//*Label 4813*/ GIMT_Encode4(185827), |
| 72205 | /*GILLT_nxv8s16*//*Label 4814*/ GIMT_Encode4(185942), |
| 72206 | /*GILLT_nxv8s32*//*Label 4815*/ GIMT_Encode4(186057), |
| 72207 | /*GILLT_nxv8s64*//*Label 4816*/ GIMT_Encode4(186172), GIMT_Encode4(0), |
| 72208 | /*GILLT_nxv16s8*//*Label 4817*/ GIMT_Encode4(186287), |
| 72209 | /*GILLT_nxv16s16*//*Label 4818*/ GIMT_Encode4(186402), |
| 72210 | /*GILLT_nxv16s32*//*Label 4819*/ GIMT_Encode4(186517), GIMT_Encode4(0), |
| 72211 | /*GILLT_nxv32s8*//*Label 4820*/ GIMT_Encode4(186632), |
| 72212 | /*GILLT_nxv32s16*//*Label 4821*/ GIMT_Encode4(186747), GIMT_Encode4(0), |
| 72213 | /*GILLT_nxv64s8*//*Label 4822*/ GIMT_Encode4(186862), |
| 72214 | // Label 4799: @184379 |
| 72215 | GIM_Try, /*On fail goto*//*Label 4824*/ GIMT_Encode4(184412), // Rule ID 327 // |
| 72216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode1), |
| 72217 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 72218 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 72219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 72220 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 72221 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 72222 | // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 72223 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULH), |
| 72224 | GIR_RootConstrainSelectedInstOperands, |
| 72225 | // GIR_Coverage, 327, |
| 72226 | GIR_Done, |
| 72227 | // Label 4824: @184412 |
| 72228 | GIM_Reject, |
| 72229 | // Label 4800: @184413 |
| 72230 | GIM_Try, /*On fail goto*//*Label 4825*/ GIMT_Encode4(184446), // Rule ID 326 // |
| 72231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode0), |
| 72232 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 72233 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 72234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 72235 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 72236 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 72237 | // (mulhs:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MULH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 72238 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULH), |
| 72239 | GIR_RootConstrainSelectedInstOperands, |
| 72240 | // GIR_Coverage, 326, |
| 72241 | GIR_Done, |
| 72242 | // Label 4825: @184446 |
| 72243 | GIM_Reject, |
| 72244 | // Label 4801: @184447 |
| 72245 | GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(184561), |
| 72246 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 72247 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 72248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72249 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72250 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72251 | GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(184515), // Rule ID 51568 // |
| 72252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72253 | // (mulhs:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMULH_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 72254 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 72255 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72256 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72257 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF8), |
| 72259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72260 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72261 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72262 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72266 | GIR_RootConstrainSelectedInstOperands, |
| 72267 | // GIR_Coverage, 51568, |
| 72268 | GIR_EraseRootFromParent_Done, |
| 72269 | // Label 4827: @184515 |
| 72270 | GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(184560), // Rule ID 51569 // |
| 72271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72272 | // (mulhs:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMULH_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 72273 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 72274 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72275 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF8), |
| 72278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72279 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72280 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72281 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72285 | GIR_RootConstrainSelectedInstOperands, |
| 72286 | // GIR_Coverage, 51569, |
| 72287 | GIR_EraseRootFromParent_Done, |
| 72288 | // Label 4828: @184560 |
| 72289 | GIM_Reject, |
| 72290 | // Label 4826: @184561 |
| 72291 | GIM_Reject, |
| 72292 | // Label 4802: @184562 |
| 72293 | GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(184676), |
| 72294 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 72295 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 72296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72297 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72298 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72299 | GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(184630), // Rule ID 51580 // |
| 72300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72301 | // (mulhs:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMULH_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 72302 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 72303 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72304 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF4), |
| 72307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72308 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72309 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72310 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72314 | GIR_RootConstrainSelectedInstOperands, |
| 72315 | // GIR_Coverage, 51580, |
| 72316 | GIR_EraseRootFromParent_Done, |
| 72317 | // Label 4830: @184630 |
| 72318 | GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(184675), // Rule ID 51581 // |
| 72319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72320 | // (mulhs:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMULH_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 72321 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 72322 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72323 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF4), |
| 72326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72327 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72328 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72329 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72333 | GIR_RootConstrainSelectedInstOperands, |
| 72334 | // GIR_Coverage, 51581, |
| 72335 | GIR_EraseRootFromParent_Done, |
| 72336 | // Label 4831: @184675 |
| 72337 | GIM_Reject, |
| 72338 | // Label 4829: @184676 |
| 72339 | GIM_Reject, |
| 72340 | // Label 4803: @184677 |
| 72341 | GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(184791), |
| 72342 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 72343 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 72344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72345 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72346 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72347 | GIM_Try, /*On fail goto*//*Label 4833*/ GIMT_Encode4(184745), // Rule ID 51588 // |
| 72348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72349 | // (mulhs:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMULH_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 72350 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 72351 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72352 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF2), |
| 72355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72356 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72357 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72358 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72362 | GIR_RootConstrainSelectedInstOperands, |
| 72363 | // GIR_Coverage, 51588, |
| 72364 | GIR_EraseRootFromParent_Done, |
| 72365 | // Label 4833: @184745 |
| 72366 | GIM_Try, /*On fail goto*//*Label 4834*/ GIMT_Encode4(184790), // Rule ID 51589 // |
| 72367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72368 | // (mulhs:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMULH_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 72369 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 72370 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72371 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72372 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72373 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF2), |
| 72374 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72375 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72376 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72377 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72381 | GIR_RootConstrainSelectedInstOperands, |
| 72382 | // GIR_Coverage, 51589, |
| 72383 | GIR_EraseRootFromParent_Done, |
| 72384 | // Label 4834: @184790 |
| 72385 | GIM_Reject, |
| 72386 | // Label 4832: @184791 |
| 72387 | GIM_Reject, |
| 72388 | // Label 4804: @184792 |
| 72389 | GIM_Try, /*On fail goto*//*Label 4835*/ GIMT_Encode4(184906), |
| 72390 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 72391 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 72392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72395 | GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(184860), // Rule ID 51712 // |
| 72396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 72397 | // (mulhs:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 72398 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 72399 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72400 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72404 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72405 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72410 | GIR_RootConstrainSelectedInstOperands, |
| 72411 | // GIR_Coverage, 51712, |
| 72412 | GIR_EraseRootFromParent_Done, |
| 72413 | // Label 4836: @184860 |
| 72414 | GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(184905), // Rule ID 51713 // |
| 72415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 72416 | // (mulhs:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 72417 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 72418 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72419 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72423 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72424 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72425 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72429 | GIR_RootConstrainSelectedInstOperands, |
| 72430 | // GIR_Coverage, 51713, |
| 72431 | GIR_EraseRootFromParent_Done, |
| 72432 | // Label 4837: @184905 |
| 72433 | GIM_Reject, |
| 72434 | // Label 4835: @184906 |
| 72435 | GIM_Reject, |
| 72436 | // Label 4805: @184907 |
| 72437 | GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(185021), |
| 72438 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 72439 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 72440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72441 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72442 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72443 | GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(184975), // Rule ID 51572 // |
| 72444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72445 | // (mulhs:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMULH_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 72446 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 72447 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72448 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF4), |
| 72451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72452 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72453 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72454 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72458 | GIR_RootConstrainSelectedInstOperands, |
| 72459 | // GIR_Coverage, 51572, |
| 72460 | GIR_EraseRootFromParent_Done, |
| 72461 | // Label 4839: @184975 |
| 72462 | GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(185020), // Rule ID 51573 // |
| 72463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72464 | // (mulhs:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMULH_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 72465 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 72466 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72467 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF4), |
| 72470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72471 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72472 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72473 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72477 | GIR_RootConstrainSelectedInstOperands, |
| 72478 | // GIR_Coverage, 51573, |
| 72479 | GIR_EraseRootFromParent_Done, |
| 72480 | // Label 4840: @185020 |
| 72481 | GIM_Reject, |
| 72482 | // Label 4838: @185021 |
| 72483 | GIM_Reject, |
| 72484 | // Label 4806: @185022 |
| 72485 | GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(185136), |
| 72486 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 72487 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 72488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72489 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72490 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72491 | GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(185090), // Rule ID 51584 // |
| 72492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72493 | // (mulhs:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMULH_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 72494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 72495 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72496 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF2), |
| 72499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72500 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72501 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72502 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72506 | GIR_RootConstrainSelectedInstOperands, |
| 72507 | // GIR_Coverage, 51584, |
| 72508 | GIR_EraseRootFromParent_Done, |
| 72509 | // Label 4842: @185090 |
| 72510 | GIM_Try, /*On fail goto*//*Label 4843*/ GIMT_Encode4(185135), // Rule ID 51585 // |
| 72511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72512 | // (mulhs:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMULH_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 72513 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 72514 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72515 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF2), |
| 72518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72519 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72520 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72521 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72525 | GIR_RootConstrainSelectedInstOperands, |
| 72526 | // GIR_Coverage, 51585, |
| 72527 | GIR_EraseRootFromParent_Done, |
| 72528 | // Label 4843: @185135 |
| 72529 | GIM_Reject, |
| 72530 | // Label 4841: @185136 |
| 72531 | GIM_Reject, |
| 72532 | // Label 4807: @185137 |
| 72533 | GIM_Try, /*On fail goto*//*Label 4844*/ GIMT_Encode4(185251), |
| 72534 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 72535 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 72536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72537 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72538 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72539 | GIM_Try, /*On fail goto*//*Label 4845*/ GIMT_Encode4(185205), // Rule ID 51600 // |
| 72540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72541 | // (mulhs:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 72542 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 72543 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72544 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72545 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72548 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72549 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72550 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72554 | GIR_RootConstrainSelectedInstOperands, |
| 72555 | // GIR_Coverage, 51600, |
| 72556 | GIR_EraseRootFromParent_Done, |
| 72557 | // Label 4845: @185205 |
| 72558 | GIM_Try, /*On fail goto*//*Label 4846*/ GIMT_Encode4(185250), // Rule ID 51601 // |
| 72559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72560 | // (mulhs:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 72561 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 72562 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72563 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72564 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72567 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72568 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72569 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72573 | GIR_RootConstrainSelectedInstOperands, |
| 72574 | // GIR_Coverage, 51601, |
| 72575 | GIR_EraseRootFromParent_Done, |
| 72576 | // Label 4846: @185250 |
| 72577 | GIM_Reject, |
| 72578 | // Label 4844: @185251 |
| 72579 | GIM_Reject, |
| 72580 | // Label 4808: @185252 |
| 72581 | GIM_Try, /*On fail goto*//*Label 4847*/ GIMT_Encode4(185366), |
| 72582 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 72583 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 72584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72586 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72587 | GIM_Try, /*On fail goto*//*Label 4848*/ GIMT_Encode4(185320), // Rule ID 51716 // |
| 72588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 72589 | // (mulhs:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 72590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 72591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 72595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72597 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72598 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72602 | GIR_RootConstrainSelectedInstOperands, |
| 72603 | // GIR_Coverage, 51716, |
| 72604 | GIR_EraseRootFromParent_Done, |
| 72605 | // Label 4848: @185320 |
| 72606 | GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(185365), // Rule ID 51717 // |
| 72607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 72608 | // (mulhs:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 72609 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 72610 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72611 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72612 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 72614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72616 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72617 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72621 | GIR_RootConstrainSelectedInstOperands, |
| 72622 | // GIR_Coverage, 51717, |
| 72623 | GIR_EraseRootFromParent_Done, |
| 72624 | // Label 4849: @185365 |
| 72625 | GIM_Reject, |
| 72626 | // Label 4847: @185366 |
| 72627 | GIM_Reject, |
| 72628 | // Label 4809: @185367 |
| 72629 | GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(185481), |
| 72630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 72631 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 72632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72635 | GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(185435), // Rule ID 51576 // |
| 72636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72637 | // (mulhs:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMULH_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 72638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 72639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF2), |
| 72643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72645 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72646 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72650 | GIR_RootConstrainSelectedInstOperands, |
| 72651 | // GIR_Coverage, 51576, |
| 72652 | GIR_EraseRootFromParent_Done, |
| 72653 | // Label 4851: @185435 |
| 72654 | GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(185480), // Rule ID 51577 // |
| 72655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72656 | // (mulhs:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMULH_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 72657 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 72658 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72659 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_MF2), |
| 72662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72664 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72665 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72669 | GIR_RootConstrainSelectedInstOperands, |
| 72670 | // GIR_Coverage, 51577, |
| 72671 | GIR_EraseRootFromParent_Done, |
| 72672 | // Label 4852: @185480 |
| 72673 | GIM_Reject, |
| 72674 | // Label 4850: @185481 |
| 72675 | GIM_Reject, |
| 72676 | // Label 4810: @185482 |
| 72677 | GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(185596), |
| 72678 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 72679 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 72680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72681 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72682 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72683 | GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(185550), // Rule ID 51596 // |
| 72684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72685 | // (mulhs:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 72686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 72687 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72692 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72693 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72694 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72698 | GIR_RootConstrainSelectedInstOperands, |
| 72699 | // GIR_Coverage, 51596, |
| 72700 | GIR_EraseRootFromParent_Done, |
| 72701 | // Label 4854: @185550 |
| 72702 | GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(185595), // Rule ID 51597 // |
| 72703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72704 | // (mulhs:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 72705 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 72706 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72707 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72708 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72711 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72712 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72713 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72717 | GIR_RootConstrainSelectedInstOperands, |
| 72718 | // GIR_Coverage, 51597, |
| 72719 | GIR_EraseRootFromParent_Done, |
| 72720 | // Label 4855: @185595 |
| 72721 | GIM_Reject, |
| 72722 | // Label 4853: @185596 |
| 72723 | GIM_Reject, |
| 72724 | // Label 4811: @185597 |
| 72725 | GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(185711), |
| 72726 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 72727 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 72728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72729 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72730 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72731 | GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(185665), // Rule ID 51628 // |
| 72732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72733 | // (mulhs:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 72734 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 72735 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72736 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 72739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72740 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72741 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72742 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72746 | GIR_RootConstrainSelectedInstOperands, |
| 72747 | // GIR_Coverage, 51628, |
| 72748 | GIR_EraseRootFromParent_Done, |
| 72749 | // Label 4857: @185665 |
| 72750 | GIM_Try, /*On fail goto*//*Label 4858*/ GIMT_Encode4(185710), // Rule ID 51629 // |
| 72751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72752 | // (mulhs:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 72753 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 72754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72755 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 72758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72759 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72760 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72761 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72765 | GIR_RootConstrainSelectedInstOperands, |
| 72766 | // GIR_Coverage, 51629, |
| 72767 | GIR_EraseRootFromParent_Done, |
| 72768 | // Label 4858: @185710 |
| 72769 | GIM_Reject, |
| 72770 | // Label 4856: @185711 |
| 72771 | GIM_Reject, |
| 72772 | // Label 4812: @185712 |
| 72773 | GIM_Try, /*On fail goto*//*Label 4859*/ GIMT_Encode4(185826), |
| 72774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 72775 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 72776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72777 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72778 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72779 | GIM_Try, /*On fail goto*//*Label 4860*/ GIMT_Encode4(185780), // Rule ID 51720 // |
| 72780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 72781 | // (mulhs:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 72782 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 72783 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72784 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72785 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 72787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72788 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72789 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72790 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72794 | GIR_RootConstrainSelectedInstOperands, |
| 72795 | // GIR_Coverage, 51720, |
| 72796 | GIR_EraseRootFromParent_Done, |
| 72797 | // Label 4860: @185780 |
| 72798 | GIM_Try, /*On fail goto*//*Label 4861*/ GIMT_Encode4(185825), // Rule ID 51721 // |
| 72799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 72800 | // (mulhs:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 72801 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 72802 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72803 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72804 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 72806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72807 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72808 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72809 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72813 | GIR_RootConstrainSelectedInstOperands, |
| 72814 | // GIR_Coverage, 51721, |
| 72815 | GIR_EraseRootFromParent_Done, |
| 72816 | // Label 4861: @185825 |
| 72817 | GIM_Reject, |
| 72818 | // Label 4859: @185826 |
| 72819 | GIM_Reject, |
| 72820 | // Label 4813: @185827 |
| 72821 | GIM_Try, /*On fail goto*//*Label 4862*/ GIMT_Encode4(185941), |
| 72822 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 72823 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 72824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72825 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72826 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 72827 | GIM_Try, /*On fail goto*//*Label 4863*/ GIMT_Encode4(185895), // Rule ID 51592 // |
| 72828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72829 | // (mulhs:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 72830 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 72831 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72832 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72833 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72836 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72837 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72838 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72842 | GIR_RootConstrainSelectedInstOperands, |
| 72843 | // GIR_Coverage, 51592, |
| 72844 | GIR_EraseRootFromParent_Done, |
| 72845 | // Label 4863: @185895 |
| 72846 | GIM_Try, /*On fail goto*//*Label 4864*/ GIMT_Encode4(185940), // Rule ID 51593 // |
| 72847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72848 | // (mulhs:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMULH_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 72849 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 72850 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72851 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M1), |
| 72854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72855 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72856 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72857 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72861 | GIR_RootConstrainSelectedInstOperands, |
| 72862 | // GIR_Coverage, 51593, |
| 72863 | GIR_EraseRootFromParent_Done, |
| 72864 | // Label 4864: @185940 |
| 72865 | GIM_Reject, |
| 72866 | // Label 4862: @185941 |
| 72867 | GIM_Reject, |
| 72868 | // Label 4814: @185942 |
| 72869 | GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(186056), |
| 72870 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 72871 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 72872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72873 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 72875 | GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(186010), // Rule ID 51616 // |
| 72876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72877 | // (mulhs:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 72878 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 72879 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72880 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 72883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72884 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72885 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72886 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72890 | GIR_RootConstrainSelectedInstOperands, |
| 72891 | // GIR_Coverage, 51616, |
| 72892 | GIR_EraseRootFromParent_Done, |
| 72893 | // Label 4866: @186010 |
| 72894 | GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(186055), // Rule ID 51617 // |
| 72895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72896 | // (mulhs:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 72897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 72898 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72899 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72900 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 72902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72903 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72904 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72905 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 72908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72909 | GIR_RootConstrainSelectedInstOperands, |
| 72910 | // GIR_Coverage, 51617, |
| 72911 | GIR_EraseRootFromParent_Done, |
| 72912 | // Label 4867: @186055 |
| 72913 | GIM_Reject, |
| 72914 | // Label 4865: @186056 |
| 72915 | GIM_Reject, |
| 72916 | // Label 4815: @186057 |
| 72917 | GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(186171), |
| 72918 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 72919 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 72920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72921 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72922 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 72923 | GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(186125), // Rule ID 51632 // |
| 72924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 72925 | // (mulhs:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 72926 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 72927 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72928 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72929 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 72931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72932 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72933 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72934 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72938 | GIR_RootConstrainSelectedInstOperands, |
| 72939 | // GIR_Coverage, 51632, |
| 72940 | GIR_EraseRootFromParent_Done, |
| 72941 | // Label 4869: @186125 |
| 72942 | GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(186170), // Rule ID 51633 // |
| 72943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 72944 | // (mulhs:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 72945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 72946 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72947 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 72950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72951 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72952 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72953 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 72956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72957 | GIR_RootConstrainSelectedInstOperands, |
| 72958 | // GIR_Coverage, 51633, |
| 72959 | GIR_EraseRootFromParent_Done, |
| 72960 | // Label 4870: @186170 |
| 72961 | GIM_Reject, |
| 72962 | // Label 4868: @186171 |
| 72963 | GIM_Reject, |
| 72964 | // Label 4816: @186172 |
| 72965 | GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(186286), |
| 72966 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 72967 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 72968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72970 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 72971 | GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(186240), // Rule ID 51724 // |
| 72972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode0), |
| 72973 | // (mulhs:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 72974 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 72975 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72976 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72977 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 72979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72980 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72981 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 72982 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 72983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 72984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 72985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 72986 | GIR_RootConstrainSelectedInstOperands, |
| 72987 | // GIR_Coverage, 51724, |
| 72988 | GIR_EraseRootFromParent_Done, |
| 72989 | // Label 4872: @186240 |
| 72990 | GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(186285), // Rule ID 51725 // |
| 72991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsFullMultiply_HwMode1), |
| 72992 | // (mulhs:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 72993 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 72994 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72995 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 72998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 72999 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73000 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73001 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73005 | GIR_RootConstrainSelectedInstOperands, |
| 73006 | // GIR_Coverage, 51725, |
| 73007 | GIR_EraseRootFromParent_Done, |
| 73008 | // Label 4873: @186285 |
| 73009 | GIM_Reject, |
| 73010 | // Label 4871: @186286 |
| 73011 | GIM_Reject, |
| 73012 | // Label 4817: @186287 |
| 73013 | GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(186401), |
| 73014 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 73015 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 73016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73017 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73018 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73019 | GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(186355), // Rule ID 51604 // |
| 73020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73021 | // (mulhs:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73022 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 73023 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73024 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73025 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 73027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73028 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73029 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73030 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73034 | GIR_RootConstrainSelectedInstOperands, |
| 73035 | // GIR_Coverage, 51604, |
| 73036 | GIR_EraseRootFromParent_Done, |
| 73037 | // Label 4875: @186355 |
| 73038 | GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(186400), // Rule ID 51605 // |
| 73039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73040 | // (mulhs:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMULH_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73041 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 73042 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73043 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73044 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M2), |
| 73046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73048 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73049 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73053 | GIR_RootConstrainSelectedInstOperands, |
| 73054 | // GIR_Coverage, 51605, |
| 73055 | GIR_EraseRootFromParent_Done, |
| 73056 | // Label 4876: @186400 |
| 73057 | GIM_Reject, |
| 73058 | // Label 4874: @186401 |
| 73059 | GIM_Reject, |
| 73060 | // Label 4818: @186402 |
| 73061 | GIM_Try, /*On fail goto*//*Label 4877*/ GIMT_Encode4(186516), |
| 73062 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 73063 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 73064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73065 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73066 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73067 | GIM_Try, /*On fail goto*//*Label 4878*/ GIMT_Encode4(186470), // Rule ID 51620 // |
| 73068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73069 | // (mulhs:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 73070 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 73071 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73072 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73073 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 73075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73076 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73077 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73078 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73082 | GIR_RootConstrainSelectedInstOperands, |
| 73083 | // GIR_Coverage, 51620, |
| 73084 | GIR_EraseRootFromParent_Done, |
| 73085 | // Label 4878: @186470 |
| 73086 | GIM_Try, /*On fail goto*//*Label 4879*/ GIMT_Encode4(186515), // Rule ID 51621 // |
| 73087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73088 | // (mulhs:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 73089 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 73090 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73091 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73092 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 73094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73095 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73096 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73097 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73101 | GIR_RootConstrainSelectedInstOperands, |
| 73102 | // GIR_Coverage, 51621, |
| 73103 | GIR_EraseRootFromParent_Done, |
| 73104 | // Label 4879: @186515 |
| 73105 | GIM_Reject, |
| 73106 | // Label 4877: @186516 |
| 73107 | GIM_Reject, |
| 73108 | // Label 4819: @186517 |
| 73109 | GIM_Try, /*On fail goto*//*Label 4880*/ GIMT_Encode4(186631), |
| 73110 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 73111 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 73112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73114 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73115 | GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(186585), // Rule ID 51636 // |
| 73116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73117 | // (mulhs:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 73118 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 73119 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73120 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 73123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73124 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73125 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73126 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73130 | GIR_RootConstrainSelectedInstOperands, |
| 73131 | // GIR_Coverage, 51636, |
| 73132 | GIR_EraseRootFromParent_Done, |
| 73133 | // Label 4881: @186585 |
| 73134 | GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(186630), // Rule ID 51637 // |
| 73135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73136 | // (mulhs:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 73137 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 73138 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73139 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73140 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 73142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73143 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73144 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73145 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73149 | GIR_RootConstrainSelectedInstOperands, |
| 73150 | // GIR_Coverage, 51637, |
| 73151 | GIR_EraseRootFromParent_Done, |
| 73152 | // Label 4882: @186630 |
| 73153 | GIM_Reject, |
| 73154 | // Label 4880: @186631 |
| 73155 | GIM_Reject, |
| 73156 | // Label 4820: @186632 |
| 73157 | GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(186746), |
| 73158 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 73159 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 73160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73161 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73162 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73163 | GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(186700), // Rule ID 51608 // |
| 73164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73165 | // (mulhs:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73166 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 73167 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73168 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73169 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 73171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73172 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73173 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73174 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73178 | GIR_RootConstrainSelectedInstOperands, |
| 73179 | // GIR_Coverage, 51608, |
| 73180 | GIR_EraseRootFromParent_Done, |
| 73181 | // Label 4884: @186700 |
| 73182 | GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(186745), // Rule ID 51609 // |
| 73183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73184 | // (mulhs:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMULH_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73185 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 73186 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73187 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M4), |
| 73190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73191 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73192 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73193 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73197 | GIR_RootConstrainSelectedInstOperands, |
| 73198 | // GIR_Coverage, 51609, |
| 73199 | GIR_EraseRootFromParent_Done, |
| 73200 | // Label 4885: @186745 |
| 73201 | GIM_Reject, |
| 73202 | // Label 4883: @186746 |
| 73203 | GIM_Reject, |
| 73204 | // Label 4821: @186747 |
| 73205 | GIM_Try, /*On fail goto*//*Label 4886*/ GIMT_Encode4(186861), |
| 73206 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 73207 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 73208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73211 | GIM_Try, /*On fail goto*//*Label 4887*/ GIMT_Encode4(186815), // Rule ID 51624 // |
| 73212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73213 | // (mulhs:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 73214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 73215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 73219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73220 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73221 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73222 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73226 | GIR_RootConstrainSelectedInstOperands, |
| 73227 | // GIR_Coverage, 51624, |
| 73228 | GIR_EraseRootFromParent_Done, |
| 73229 | // Label 4887: @186815 |
| 73230 | GIM_Try, /*On fail goto*//*Label 4888*/ GIMT_Encode4(186860), // Rule ID 51625 // |
| 73231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73232 | // (mulhs:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 73233 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 73234 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73235 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 73238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73239 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73240 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73241 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73245 | GIR_RootConstrainSelectedInstOperands, |
| 73246 | // GIR_Coverage, 51625, |
| 73247 | GIR_EraseRootFromParent_Done, |
| 73248 | // Label 4888: @186860 |
| 73249 | GIM_Reject, |
| 73250 | // Label 4886: @186861 |
| 73251 | GIM_Reject, |
| 73252 | // Label 4822: @186862 |
| 73253 | GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(186976), |
| 73254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 73255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 73256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73257 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73258 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 73259 | GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(186930), // Rule ID 51612 // |
| 73260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73261 | // (mulhs:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 73263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 73267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73268 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73270 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73274 | GIR_RootConstrainSelectedInstOperands, |
| 73275 | // GIR_Coverage, 51612, |
| 73276 | GIR_EraseRootFromParent_Done, |
| 73277 | // Label 4890: @186930 |
| 73278 | GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(186975), // Rule ID 51613 // |
| 73279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73280 | // (mulhs:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMULH_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73281 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 73282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMULH_VV_M8), |
| 73286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73287 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73288 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73289 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73293 | GIR_RootConstrainSelectedInstOperands, |
| 73294 | // GIR_Coverage, 51613, |
| 73295 | GIR_EraseRootFromParent_Done, |
| 73296 | // Label 4891: @186975 |
| 73297 | GIM_Reject, |
| 73298 | // Label 4889: @186976 |
| 73299 | GIM_Reject, |
| 73300 | // Label 4823: @186977 |
| 73301 | GIM_Reject, |
| 73302 | // Label 49: @186978 |
| 73303 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(34), /*)*//*default:*//*Label 4914*/ GIMT_Encode4(189763), |
| 73304 | /*GILLT_nxv1s8*//*Label 4892*/ GIMT_Encode4(187101), |
| 73305 | /*GILLT_nxv1s16*//*Label 4893*/ GIMT_Encode4(187222), |
| 73306 | /*GILLT_nxv1s32*//*Label 4894*/ GIMT_Encode4(187343), |
| 73307 | /*GILLT_nxv1s64*//*Label 4895*/ GIMT_Encode4(187464), GIMT_Encode4(0), |
| 73308 | /*GILLT_nxv2s8*//*Label 4896*/ GIMT_Encode4(187585), |
| 73309 | /*GILLT_nxv2s16*//*Label 4897*/ GIMT_Encode4(187706), |
| 73310 | /*GILLT_nxv2s32*//*Label 4898*/ GIMT_Encode4(187827), |
| 73311 | /*GILLT_nxv2s64*//*Label 4899*/ GIMT_Encode4(187948), GIMT_Encode4(0), |
| 73312 | /*GILLT_nxv4s8*//*Label 4900*/ GIMT_Encode4(188069), |
| 73313 | /*GILLT_nxv4s16*//*Label 4901*/ GIMT_Encode4(188190), |
| 73314 | /*GILLT_nxv4s32*//*Label 4902*/ GIMT_Encode4(188311), |
| 73315 | /*GILLT_nxv4s64*//*Label 4903*/ GIMT_Encode4(188432), GIMT_Encode4(0), |
| 73316 | /*GILLT_nxv8s8*//*Label 4904*/ GIMT_Encode4(188553), |
| 73317 | /*GILLT_nxv8s16*//*Label 4905*/ GIMT_Encode4(188674), |
| 73318 | /*GILLT_nxv8s32*//*Label 4906*/ GIMT_Encode4(188795), |
| 73319 | /*GILLT_nxv8s64*//*Label 4907*/ GIMT_Encode4(188916), GIMT_Encode4(0), |
| 73320 | /*GILLT_nxv16s8*//*Label 4908*/ GIMT_Encode4(189037), |
| 73321 | /*GILLT_nxv16s16*//*Label 4909*/ GIMT_Encode4(189158), |
| 73322 | /*GILLT_nxv16s32*//*Label 4910*/ GIMT_Encode4(189279), GIMT_Encode4(0), |
| 73323 | /*GILLT_nxv32s8*//*Label 4911*/ GIMT_Encode4(189400), |
| 73324 | /*GILLT_nxv32s16*//*Label 4912*/ GIMT_Encode4(189521), GIMT_Encode4(0), |
| 73325 | /*GILLT_nxv64s8*//*Label 4913*/ GIMT_Encode4(189642), |
| 73326 | // Label 4892: @187101 |
| 73327 | GIM_Try, /*On fail goto*//*Label 4915*/ GIMT_Encode4(187221), |
| 73328 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 73329 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 73330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73332 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73333 | GIM_Try, /*On fail goto*//*Label 4916*/ GIMT_Encode4(187172), // Rule ID 53128 // |
| 73334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73335 | // (uaddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSADDU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73336 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 73337 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73338 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF8), |
| 73341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73342 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73343 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73344 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73348 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73349 | GIR_RootConstrainSelectedInstOperands, |
| 73350 | // GIR_Coverage, 53128, |
| 73351 | GIR_EraseRootFromParent_Done, |
| 73352 | // Label 4916: @187172 |
| 73353 | GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(187220), // Rule ID 53129 // |
| 73354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73355 | // (uaddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSADDU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 73357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF8), |
| 73361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73363 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73364 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73368 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73369 | GIR_RootConstrainSelectedInstOperands, |
| 73370 | // GIR_Coverage, 53129, |
| 73371 | GIR_EraseRootFromParent_Done, |
| 73372 | // Label 4917: @187220 |
| 73373 | GIM_Reject, |
| 73374 | // Label 4915: @187221 |
| 73375 | GIM_Reject, |
| 73376 | // Label 4893: @187222 |
| 73377 | GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(187342), |
| 73378 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 73379 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 73380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73382 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73383 | GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(187293), // Rule ID 53140 // |
| 73384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73385 | // (uaddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSADDU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 73386 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 73387 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73388 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73389 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF4), |
| 73391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73392 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73393 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73394 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73398 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73399 | GIR_RootConstrainSelectedInstOperands, |
| 73400 | // GIR_Coverage, 53140, |
| 73401 | GIR_EraseRootFromParent_Done, |
| 73402 | // Label 4919: @187293 |
| 73403 | GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(187341), // Rule ID 53141 // |
| 73404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73405 | // (uaddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSADDU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 73406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 73407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73408 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF4), |
| 73411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73413 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73414 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73418 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73419 | GIR_RootConstrainSelectedInstOperands, |
| 73420 | // GIR_Coverage, 53141, |
| 73421 | GIR_EraseRootFromParent_Done, |
| 73422 | // Label 4920: @187341 |
| 73423 | GIM_Reject, |
| 73424 | // Label 4918: @187342 |
| 73425 | GIM_Reject, |
| 73426 | // Label 4894: @187343 |
| 73427 | GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(187463), |
| 73428 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 73429 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 73430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73431 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73432 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73433 | GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(187414), // Rule ID 53148 // |
| 73434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73435 | // (uaddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSADDU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 73436 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 73437 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73438 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF2), |
| 73441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73443 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73444 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73448 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73449 | GIR_RootConstrainSelectedInstOperands, |
| 73450 | // GIR_Coverage, 53148, |
| 73451 | GIR_EraseRootFromParent_Done, |
| 73452 | // Label 4922: @187414 |
| 73453 | GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(187462), // Rule ID 53149 // |
| 73454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73455 | // (uaddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSADDU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 73456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 73457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF2), |
| 73461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73463 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73464 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73468 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73469 | GIR_RootConstrainSelectedInstOperands, |
| 73470 | // GIR_Coverage, 53149, |
| 73471 | GIR_EraseRootFromParent_Done, |
| 73472 | // Label 4923: @187462 |
| 73473 | GIM_Reject, |
| 73474 | // Label 4921: @187463 |
| 73475 | GIM_Reject, |
| 73476 | // Label 4895: @187464 |
| 73477 | GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(187584), |
| 73478 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 73479 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 73480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73481 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73482 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73483 | GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(187535), // Rule ID 53164 // |
| 73484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 73485 | // (uaddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 73486 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 73487 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73488 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73492 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73493 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73494 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73498 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73499 | GIR_RootConstrainSelectedInstOperands, |
| 73500 | // GIR_Coverage, 53164, |
| 73501 | GIR_EraseRootFromParent_Done, |
| 73502 | // Label 4925: @187535 |
| 73503 | GIM_Try, /*On fail goto*//*Label 4926*/ GIMT_Encode4(187583), // Rule ID 53165 // |
| 73504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 73505 | // (uaddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 73506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 73507 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73513 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73518 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73519 | GIR_RootConstrainSelectedInstOperands, |
| 73520 | // GIR_Coverage, 53165, |
| 73521 | GIR_EraseRootFromParent_Done, |
| 73522 | // Label 4926: @187583 |
| 73523 | GIM_Reject, |
| 73524 | // Label 4924: @187584 |
| 73525 | GIM_Reject, |
| 73526 | // Label 4896: @187585 |
| 73527 | GIM_Try, /*On fail goto*//*Label 4927*/ GIMT_Encode4(187705), |
| 73528 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 73529 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 73530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73531 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73532 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73533 | GIM_Try, /*On fail goto*//*Label 4928*/ GIMT_Encode4(187656), // Rule ID 53132 // |
| 73534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73535 | // (uaddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSADDU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73536 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 73537 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73538 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73539 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF4), |
| 73541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73542 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73543 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73544 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73548 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73549 | GIR_RootConstrainSelectedInstOperands, |
| 73550 | // GIR_Coverage, 53132, |
| 73551 | GIR_EraseRootFromParent_Done, |
| 73552 | // Label 4928: @187656 |
| 73553 | GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(187704), // Rule ID 53133 // |
| 73554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73555 | // (uaddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSADDU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73556 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 73557 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF4), |
| 73561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73562 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73563 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73564 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73568 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73569 | GIR_RootConstrainSelectedInstOperands, |
| 73570 | // GIR_Coverage, 53133, |
| 73571 | GIR_EraseRootFromParent_Done, |
| 73572 | // Label 4929: @187704 |
| 73573 | GIM_Reject, |
| 73574 | // Label 4927: @187705 |
| 73575 | GIM_Reject, |
| 73576 | // Label 4897: @187706 |
| 73577 | GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(187826), |
| 73578 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 73579 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 73580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73582 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73583 | GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(187777), // Rule ID 53144 // |
| 73584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73585 | // (uaddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSADDU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 73586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 73587 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73588 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73589 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF2), |
| 73591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73592 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73593 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73594 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73598 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73599 | GIR_RootConstrainSelectedInstOperands, |
| 73600 | // GIR_Coverage, 53144, |
| 73601 | GIR_EraseRootFromParent_Done, |
| 73602 | // Label 4931: @187777 |
| 73603 | GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(187825), // Rule ID 53145 // |
| 73604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73605 | // (uaddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSADDU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 73606 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 73607 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73608 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF2), |
| 73611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73613 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73614 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73618 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73619 | GIR_RootConstrainSelectedInstOperands, |
| 73620 | // GIR_Coverage, 53145, |
| 73621 | GIR_EraseRootFromParent_Done, |
| 73622 | // Label 4932: @187825 |
| 73623 | GIM_Reject, |
| 73624 | // Label 4930: @187826 |
| 73625 | GIM_Reject, |
| 73626 | // Label 4898: @187827 |
| 73627 | GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(187947), |
| 73628 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 73629 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 73630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73631 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73632 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73633 | GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(187898), // Rule ID 53160 // |
| 73634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73635 | // (uaddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 73636 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 73637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73638 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73642 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73643 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73644 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73648 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73649 | GIR_RootConstrainSelectedInstOperands, |
| 73650 | // GIR_Coverage, 53160, |
| 73651 | GIR_EraseRootFromParent_Done, |
| 73652 | // Label 4934: @187898 |
| 73653 | GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(187946), // Rule ID 53161 // |
| 73654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73655 | // (uaddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 73656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 73657 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73658 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73663 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73664 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73668 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73669 | GIR_RootConstrainSelectedInstOperands, |
| 73670 | // GIR_Coverage, 53161, |
| 73671 | GIR_EraseRootFromParent_Done, |
| 73672 | // Label 4935: @187946 |
| 73673 | GIM_Reject, |
| 73674 | // Label 4933: @187947 |
| 73675 | GIM_Reject, |
| 73676 | // Label 4899: @187948 |
| 73677 | GIM_Try, /*On fail goto*//*Label 4936*/ GIMT_Encode4(188068), |
| 73678 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 73679 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 73680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73681 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73682 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73683 | GIM_Try, /*On fail goto*//*Label 4937*/ GIMT_Encode4(188019), // Rule ID 53204 // |
| 73684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 73685 | // (uaddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 73686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 73687 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 73691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73692 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73693 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73694 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73698 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73699 | GIR_RootConstrainSelectedInstOperands, |
| 73700 | // GIR_Coverage, 53204, |
| 73701 | GIR_EraseRootFromParent_Done, |
| 73702 | // Label 4937: @188019 |
| 73703 | GIM_Try, /*On fail goto*//*Label 4938*/ GIMT_Encode4(188067), // Rule ID 53205 // |
| 73704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 73705 | // (uaddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 73706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 73707 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73708 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 73711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73713 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73714 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73718 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73719 | GIR_RootConstrainSelectedInstOperands, |
| 73720 | // GIR_Coverage, 53205, |
| 73721 | GIR_EraseRootFromParent_Done, |
| 73722 | // Label 4938: @188067 |
| 73723 | GIM_Reject, |
| 73724 | // Label 4936: @188068 |
| 73725 | GIM_Reject, |
| 73726 | // Label 4900: @188069 |
| 73727 | GIM_Try, /*On fail goto*//*Label 4939*/ GIMT_Encode4(188189), |
| 73728 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 73729 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 73730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73731 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73732 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73733 | GIM_Try, /*On fail goto*//*Label 4940*/ GIMT_Encode4(188140), // Rule ID 53136 // |
| 73734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73735 | // (uaddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSADDU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73736 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 73737 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73738 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF2), |
| 73741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73742 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73743 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73744 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73748 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73749 | GIR_RootConstrainSelectedInstOperands, |
| 73750 | // GIR_Coverage, 53136, |
| 73751 | GIR_EraseRootFromParent_Done, |
| 73752 | // Label 4940: @188140 |
| 73753 | GIM_Try, /*On fail goto*//*Label 4941*/ GIMT_Encode4(188188), // Rule ID 53137 // |
| 73754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73755 | // (uaddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSADDU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73756 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 73757 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73758 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_MF2), |
| 73761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73762 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73763 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73764 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73768 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73769 | GIR_RootConstrainSelectedInstOperands, |
| 73770 | // GIR_Coverage, 53137, |
| 73771 | GIR_EraseRootFromParent_Done, |
| 73772 | // Label 4941: @188188 |
| 73773 | GIM_Reject, |
| 73774 | // Label 4939: @188189 |
| 73775 | GIM_Reject, |
| 73776 | // Label 4901: @188190 |
| 73777 | GIM_Try, /*On fail goto*//*Label 4942*/ GIMT_Encode4(188310), |
| 73778 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 73779 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 73780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73782 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73783 | GIM_Try, /*On fail goto*//*Label 4943*/ GIMT_Encode4(188261), // Rule ID 53156 // |
| 73784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73785 | // (uaddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 73786 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 73787 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73788 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73792 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73793 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73794 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73798 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73799 | GIR_RootConstrainSelectedInstOperands, |
| 73800 | // GIR_Coverage, 53156, |
| 73801 | GIR_EraseRootFromParent_Done, |
| 73802 | // Label 4943: @188261 |
| 73803 | GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(188309), // Rule ID 53157 // |
| 73804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73805 | // (uaddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 73806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 73807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73812 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73813 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73814 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73818 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73819 | GIR_RootConstrainSelectedInstOperands, |
| 73820 | // GIR_Coverage, 53157, |
| 73821 | GIR_EraseRootFromParent_Done, |
| 73822 | // Label 4944: @188309 |
| 73823 | GIM_Reject, |
| 73824 | // Label 4942: @188310 |
| 73825 | GIM_Reject, |
| 73826 | // Label 4902: @188311 |
| 73827 | GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(188431), |
| 73828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 73829 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 73830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73833 | GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(188382), // Rule ID 53192 // |
| 73834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73835 | // (uaddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 73836 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 73837 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73838 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 73841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73843 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73844 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73848 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73849 | GIR_RootConstrainSelectedInstOperands, |
| 73850 | // GIR_Coverage, 53192, |
| 73851 | GIR_EraseRootFromParent_Done, |
| 73852 | // Label 4946: @188382 |
| 73853 | GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(188430), // Rule ID 53193 // |
| 73854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73855 | // (uaddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 73856 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 73857 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73858 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73859 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 73861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73862 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73863 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73864 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 73867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73868 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73869 | GIR_RootConstrainSelectedInstOperands, |
| 73870 | // GIR_Coverage, 53193, |
| 73871 | GIR_EraseRootFromParent_Done, |
| 73872 | // Label 4947: @188430 |
| 73873 | GIM_Reject, |
| 73874 | // Label 4945: @188431 |
| 73875 | GIM_Reject, |
| 73876 | // Label 4903: @188432 |
| 73877 | GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(188552), |
| 73878 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 73879 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 73880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73882 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 73883 | GIM_Try, /*On fail goto*//*Label 4949*/ GIMT_Encode4(188503), // Rule ID 53208 // |
| 73884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 73885 | // (uaddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 73886 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 73887 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73888 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 73891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73892 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73893 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73894 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73898 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73899 | GIR_RootConstrainSelectedInstOperands, |
| 73900 | // GIR_Coverage, 53208, |
| 73901 | GIR_EraseRootFromParent_Done, |
| 73902 | // Label 4949: @188503 |
| 73903 | GIM_Try, /*On fail goto*//*Label 4950*/ GIMT_Encode4(188551), // Rule ID 53209 // |
| 73904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 73905 | // (uaddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 73906 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 73907 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73908 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73909 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 73911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73912 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73913 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73914 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 73917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73918 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73919 | GIR_RootConstrainSelectedInstOperands, |
| 73920 | // GIR_Coverage, 53209, |
| 73921 | GIR_EraseRootFromParent_Done, |
| 73922 | // Label 4950: @188551 |
| 73923 | GIM_Reject, |
| 73924 | // Label 4948: @188552 |
| 73925 | GIM_Reject, |
| 73926 | // Label 4904: @188553 |
| 73927 | GIM_Try, /*On fail goto*//*Label 4951*/ GIMT_Encode4(188673), |
| 73928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 73929 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 73930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73931 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73932 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 73933 | GIM_Try, /*On fail goto*//*Label 4952*/ GIMT_Encode4(188624), // Rule ID 53152 // |
| 73934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73935 | // (uaddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 73936 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 73937 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73938 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73942 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73943 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73944 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73948 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73949 | GIR_RootConstrainSelectedInstOperands, |
| 73950 | // GIR_Coverage, 53152, |
| 73951 | GIR_EraseRootFromParent_Done, |
| 73952 | // Label 4952: @188624 |
| 73953 | GIM_Try, /*On fail goto*//*Label 4953*/ GIMT_Encode4(188672), // Rule ID 53153 // |
| 73954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 73955 | // (uaddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSADDU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 73956 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 73957 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73958 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73959 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M1), |
| 73961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73962 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73963 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73964 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73968 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73969 | GIR_RootConstrainSelectedInstOperands, |
| 73970 | // GIR_Coverage, 53153, |
| 73971 | GIR_EraseRootFromParent_Done, |
| 73972 | // Label 4953: @188672 |
| 73973 | GIM_Reject, |
| 73974 | // Label 4951: @188673 |
| 73975 | GIM_Reject, |
| 73976 | // Label 4905: @188674 |
| 73977 | GIM_Try, /*On fail goto*//*Label 4954*/ GIMT_Encode4(188794), |
| 73978 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 73979 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 73980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73981 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73982 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 73983 | GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(188745), // Rule ID 53180 // |
| 73984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 73985 | // (uaddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 73986 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 73987 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 73988 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 73989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 73990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 73991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 73992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 73993 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 73994 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 73995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 73996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 73997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 73998 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 73999 | GIR_RootConstrainSelectedInstOperands, |
| 74000 | // GIR_Coverage, 53180, |
| 74001 | GIR_EraseRootFromParent_Done, |
| 74002 | // Label 4955: @188745 |
| 74003 | GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(188793), // Rule ID 53181 // |
| 74004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74005 | // (uaddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 74006 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 74007 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74008 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74009 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 74011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74012 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74013 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74014 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74018 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74019 | GIR_RootConstrainSelectedInstOperands, |
| 74020 | // GIR_Coverage, 53181, |
| 74021 | GIR_EraseRootFromParent_Done, |
| 74022 | // Label 4956: @188793 |
| 74023 | GIM_Reject, |
| 74024 | // Label 4954: @188794 |
| 74025 | GIM_Reject, |
| 74026 | // Label 4906: @188795 |
| 74027 | GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(188915), |
| 74028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 74029 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 74030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74033 | GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(188866), // Rule ID 53196 // |
| 74034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74035 | // (uaddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 74036 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 74037 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74038 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 74041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74042 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74043 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74044 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74048 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74049 | GIR_RootConstrainSelectedInstOperands, |
| 74050 | // GIR_Coverage, 53196, |
| 74051 | GIR_EraseRootFromParent_Done, |
| 74052 | // Label 4958: @188866 |
| 74053 | GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(188914), // Rule ID 53197 // |
| 74054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74055 | // (uaddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 74056 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 74057 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74058 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 74061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74063 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74068 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74069 | GIR_RootConstrainSelectedInstOperands, |
| 74070 | // GIR_Coverage, 53197, |
| 74071 | GIR_EraseRootFromParent_Done, |
| 74072 | // Label 4959: @188914 |
| 74073 | GIM_Reject, |
| 74074 | // Label 4957: @188915 |
| 74075 | GIM_Reject, |
| 74076 | // Label 4907: @188916 |
| 74077 | GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(189036), |
| 74078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 74079 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 74080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74081 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74082 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74083 | GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(188987), // Rule ID 53212 // |
| 74084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 74085 | // (uaddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 74086 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 74087 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74088 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74092 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74093 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74094 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 74097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74098 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74099 | GIR_RootConstrainSelectedInstOperands, |
| 74100 | // GIR_Coverage, 53212, |
| 74101 | GIR_EraseRootFromParent_Done, |
| 74102 | // Label 4961: @188987 |
| 74103 | GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(189035), // Rule ID 53213 // |
| 74104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 74105 | // (uaddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 74106 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 74107 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74108 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74112 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74113 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74114 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 74117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74118 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74119 | GIR_RootConstrainSelectedInstOperands, |
| 74120 | // GIR_Coverage, 53213, |
| 74121 | GIR_EraseRootFromParent_Done, |
| 74122 | // Label 4962: @189035 |
| 74123 | GIM_Reject, |
| 74124 | // Label 4960: @189036 |
| 74125 | GIM_Reject, |
| 74126 | // Label 4908: @189037 |
| 74127 | GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(189157), |
| 74128 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 74129 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 74130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74131 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74132 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74133 | GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(189108), // Rule ID 53168 // |
| 74134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74135 | // (uaddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 74136 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 74137 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74138 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 74141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74143 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74144 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74148 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74149 | GIR_RootConstrainSelectedInstOperands, |
| 74150 | // GIR_Coverage, 53168, |
| 74151 | GIR_EraseRootFromParent_Done, |
| 74152 | // Label 4964: @189108 |
| 74153 | GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(189156), // Rule ID 53169 // |
| 74154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74155 | // (uaddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSADDU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 74156 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 74157 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74158 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M2), |
| 74161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74162 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74163 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74164 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74168 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74169 | GIR_RootConstrainSelectedInstOperands, |
| 74170 | // GIR_Coverage, 53169, |
| 74171 | GIR_EraseRootFromParent_Done, |
| 74172 | // Label 4965: @189156 |
| 74173 | GIM_Reject, |
| 74174 | // Label 4963: @189157 |
| 74175 | GIM_Reject, |
| 74176 | // Label 4909: @189158 |
| 74177 | GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(189278), |
| 74178 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 74179 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 74180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74181 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74182 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74183 | GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(189229), // Rule ID 53184 // |
| 74184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74185 | // (uaddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 74186 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 74187 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74188 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74189 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 74191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74192 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74193 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74194 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74198 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74199 | GIR_RootConstrainSelectedInstOperands, |
| 74200 | // GIR_Coverage, 53184, |
| 74201 | GIR_EraseRootFromParent_Done, |
| 74202 | // Label 4967: @189229 |
| 74203 | GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(189277), // Rule ID 53185 // |
| 74204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74205 | // (uaddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 74206 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 74207 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74208 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74209 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 74211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74212 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74213 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74214 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74218 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74219 | GIR_RootConstrainSelectedInstOperands, |
| 74220 | // GIR_Coverage, 53185, |
| 74221 | GIR_EraseRootFromParent_Done, |
| 74222 | // Label 4968: @189277 |
| 74223 | GIM_Reject, |
| 74224 | // Label 4966: @189278 |
| 74225 | GIM_Reject, |
| 74226 | // Label 4910: @189279 |
| 74227 | GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(189399), |
| 74228 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 74229 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 74230 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74231 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74232 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74233 | GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(189350), // Rule ID 53200 // |
| 74234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74235 | // (uaddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 74236 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 74237 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74238 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74242 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74243 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74244 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74248 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74249 | GIR_RootConstrainSelectedInstOperands, |
| 74250 | // GIR_Coverage, 53200, |
| 74251 | GIR_EraseRootFromParent_Done, |
| 74252 | // Label 4970: @189350 |
| 74253 | GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(189398), // Rule ID 53201 // |
| 74254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74255 | // (uaddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 74256 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 74257 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74258 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74259 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74262 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74263 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74264 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74268 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74269 | GIR_RootConstrainSelectedInstOperands, |
| 74270 | // GIR_Coverage, 53201, |
| 74271 | GIR_EraseRootFromParent_Done, |
| 74272 | // Label 4971: @189398 |
| 74273 | GIM_Reject, |
| 74274 | // Label 4969: @189399 |
| 74275 | GIM_Reject, |
| 74276 | // Label 4911: @189400 |
| 74277 | GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(189520), |
| 74278 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 74279 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 74280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74281 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74282 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 74283 | GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(189471), // Rule ID 53172 // |
| 74284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74285 | // (uaddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 74286 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 74287 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74288 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 74291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74292 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74293 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74294 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74298 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74299 | GIR_RootConstrainSelectedInstOperands, |
| 74300 | // GIR_Coverage, 53172, |
| 74301 | GIR_EraseRootFromParent_Done, |
| 74302 | // Label 4973: @189471 |
| 74303 | GIM_Try, /*On fail goto*//*Label 4974*/ GIMT_Encode4(189519), // Rule ID 53173 // |
| 74304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74305 | // (uaddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSADDU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 74306 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 74307 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74308 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74309 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M4), |
| 74311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74312 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74313 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74314 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74318 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74319 | GIR_RootConstrainSelectedInstOperands, |
| 74320 | // GIR_Coverage, 53173, |
| 74321 | GIR_EraseRootFromParent_Done, |
| 74322 | // Label 4974: @189519 |
| 74323 | GIM_Reject, |
| 74324 | // Label 4972: @189520 |
| 74325 | GIM_Reject, |
| 74326 | // Label 4912: @189521 |
| 74327 | GIM_Try, /*On fail goto*//*Label 4975*/ GIMT_Encode4(189641), |
| 74328 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 74329 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 74330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74332 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74333 | GIM_Try, /*On fail goto*//*Label 4976*/ GIMT_Encode4(189592), // Rule ID 53188 // |
| 74334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74335 | // (uaddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 74336 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 74337 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74338 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74342 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74343 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74344 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74348 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74349 | GIR_RootConstrainSelectedInstOperands, |
| 74350 | // GIR_Coverage, 53188, |
| 74351 | GIR_EraseRootFromParent_Done, |
| 74352 | // Label 4976: @189592 |
| 74353 | GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(189640), // Rule ID 53189 // |
| 74354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74355 | // (uaddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 74356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 74357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74363 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74364 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74368 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74369 | GIR_RootConstrainSelectedInstOperands, |
| 74370 | // GIR_Coverage, 53189, |
| 74371 | GIR_EraseRootFromParent_Done, |
| 74372 | // Label 4977: @189640 |
| 74373 | GIM_Reject, |
| 74374 | // Label 4975: @189641 |
| 74375 | GIM_Reject, |
| 74376 | // Label 4913: @189642 |
| 74377 | GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(189762), |
| 74378 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 74379 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 74380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74382 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 74383 | GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(189713), // Rule ID 53176 // |
| 74384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74385 | // (uaddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 74386 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 74387 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74388 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74389 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74392 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74393 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74394 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74398 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74399 | GIR_RootConstrainSelectedInstOperands, |
| 74400 | // GIR_Coverage, 53176, |
| 74401 | GIR_EraseRootFromParent_Done, |
| 74402 | // Label 4979: @189713 |
| 74403 | GIM_Try, /*On fail goto*//*Label 4980*/ GIMT_Encode4(189761), // Rule ID 53177 // |
| 74404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74405 | // (uaddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSADDU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 74406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 74407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74408 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADDU_VV_M8), |
| 74411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74413 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74414 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74418 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74419 | GIR_RootConstrainSelectedInstOperands, |
| 74420 | // GIR_Coverage, 53177, |
| 74421 | GIR_EraseRootFromParent_Done, |
| 74422 | // Label 4980: @189761 |
| 74423 | GIM_Reject, |
| 74424 | // Label 4978: @189762 |
| 74425 | GIM_Reject, |
| 74426 | // Label 4914: @189763 |
| 74427 | GIM_Reject, |
| 74428 | // Label 50: @189764 |
| 74429 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(34), /*)*//*default:*//*Label 5003*/ GIMT_Encode4(192549), |
| 74430 | /*GILLT_nxv1s8*//*Label 4981*/ GIMT_Encode4(189887), |
| 74431 | /*GILLT_nxv1s16*//*Label 4982*/ GIMT_Encode4(190008), |
| 74432 | /*GILLT_nxv1s32*//*Label 4983*/ GIMT_Encode4(190129), |
| 74433 | /*GILLT_nxv1s64*//*Label 4984*/ GIMT_Encode4(190250), GIMT_Encode4(0), |
| 74434 | /*GILLT_nxv2s8*//*Label 4985*/ GIMT_Encode4(190371), |
| 74435 | /*GILLT_nxv2s16*//*Label 4986*/ GIMT_Encode4(190492), |
| 74436 | /*GILLT_nxv2s32*//*Label 4987*/ GIMT_Encode4(190613), |
| 74437 | /*GILLT_nxv2s64*//*Label 4988*/ GIMT_Encode4(190734), GIMT_Encode4(0), |
| 74438 | /*GILLT_nxv4s8*//*Label 4989*/ GIMT_Encode4(190855), |
| 74439 | /*GILLT_nxv4s16*//*Label 4990*/ GIMT_Encode4(190976), |
| 74440 | /*GILLT_nxv4s32*//*Label 4991*/ GIMT_Encode4(191097), |
| 74441 | /*GILLT_nxv4s64*//*Label 4992*/ GIMT_Encode4(191218), GIMT_Encode4(0), |
| 74442 | /*GILLT_nxv8s8*//*Label 4993*/ GIMT_Encode4(191339), |
| 74443 | /*GILLT_nxv8s16*//*Label 4994*/ GIMT_Encode4(191460), |
| 74444 | /*GILLT_nxv8s32*//*Label 4995*/ GIMT_Encode4(191581), |
| 74445 | /*GILLT_nxv8s64*//*Label 4996*/ GIMT_Encode4(191702), GIMT_Encode4(0), |
| 74446 | /*GILLT_nxv16s8*//*Label 4997*/ GIMT_Encode4(191823), |
| 74447 | /*GILLT_nxv16s16*//*Label 4998*/ GIMT_Encode4(191944), |
| 74448 | /*GILLT_nxv16s32*//*Label 4999*/ GIMT_Encode4(192065), GIMT_Encode4(0), |
| 74449 | /*GILLT_nxv32s8*//*Label 5000*/ GIMT_Encode4(192186), |
| 74450 | /*GILLT_nxv32s16*//*Label 5001*/ GIMT_Encode4(192307), GIMT_Encode4(0), |
| 74451 | /*GILLT_nxv64s8*//*Label 5002*/ GIMT_Encode4(192428), |
| 74452 | // Label 4981: @189887 |
| 74453 | GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(190007), |
| 74454 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 74455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 74456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74458 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74459 | GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(189958), // Rule ID 52996 // |
| 74460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74461 | // (saddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSADD_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 74462 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 74463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74464 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74465 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF8), |
| 74467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74468 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74469 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74470 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74474 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74475 | GIR_RootConstrainSelectedInstOperands, |
| 74476 | // GIR_Coverage, 52996, |
| 74477 | GIR_EraseRootFromParent_Done, |
| 74478 | // Label 5005: @189958 |
| 74479 | GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(190006), // Rule ID 52997 // |
| 74480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74481 | // (saddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSADD_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 74482 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 74483 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74484 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF8), |
| 74487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74488 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74489 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74490 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74494 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74495 | GIR_RootConstrainSelectedInstOperands, |
| 74496 | // GIR_Coverage, 52997, |
| 74497 | GIR_EraseRootFromParent_Done, |
| 74498 | // Label 5006: @190006 |
| 74499 | GIM_Reject, |
| 74500 | // Label 5004: @190007 |
| 74501 | GIM_Reject, |
| 74502 | // Label 4982: @190008 |
| 74503 | GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(190128), |
| 74504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 74505 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 74506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74507 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74508 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74509 | GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(190079), // Rule ID 53008 // |
| 74510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74511 | // (saddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSADD_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 74512 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 74513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF4), |
| 74517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74518 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74520 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74524 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74525 | GIR_RootConstrainSelectedInstOperands, |
| 74526 | // GIR_Coverage, 53008, |
| 74527 | GIR_EraseRootFromParent_Done, |
| 74528 | // Label 5008: @190079 |
| 74529 | GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(190127), // Rule ID 53009 // |
| 74530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74531 | // (saddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSADD_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 74532 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 74533 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74534 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF4), |
| 74537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74539 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74540 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74544 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74545 | GIR_RootConstrainSelectedInstOperands, |
| 74546 | // GIR_Coverage, 53009, |
| 74547 | GIR_EraseRootFromParent_Done, |
| 74548 | // Label 5009: @190127 |
| 74549 | GIM_Reject, |
| 74550 | // Label 5007: @190128 |
| 74551 | GIM_Reject, |
| 74552 | // Label 4983: @190129 |
| 74553 | GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(190249), |
| 74554 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 74555 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 74556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74558 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74559 | GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(190200), // Rule ID 53016 // |
| 74560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74561 | // (saddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSADD_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 74562 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 74563 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74564 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF2), |
| 74567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74568 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74569 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74570 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74574 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74575 | GIR_RootConstrainSelectedInstOperands, |
| 74576 | // GIR_Coverage, 53016, |
| 74577 | GIR_EraseRootFromParent_Done, |
| 74578 | // Label 5011: @190200 |
| 74579 | GIM_Try, /*On fail goto*//*Label 5012*/ GIMT_Encode4(190248), // Rule ID 53017 // |
| 74580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74581 | // (saddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSADD_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 74582 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 74583 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74584 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF2), |
| 74587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74588 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74589 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74590 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74594 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74595 | GIR_RootConstrainSelectedInstOperands, |
| 74596 | // GIR_Coverage, 53017, |
| 74597 | GIR_EraseRootFromParent_Done, |
| 74598 | // Label 5012: @190248 |
| 74599 | GIM_Reject, |
| 74600 | // Label 5010: @190249 |
| 74601 | GIM_Reject, |
| 74602 | // Label 4984: @190250 |
| 74603 | GIM_Try, /*On fail goto*//*Label 5013*/ GIMT_Encode4(190370), |
| 74604 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 74605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 74606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74607 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74608 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74609 | GIM_Try, /*On fail goto*//*Label 5014*/ GIMT_Encode4(190321), // Rule ID 53032 // |
| 74610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 74611 | // (saddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 74612 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 74613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 74617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74618 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74619 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74620 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 74623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74624 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74625 | GIR_RootConstrainSelectedInstOperands, |
| 74626 | // GIR_Coverage, 53032, |
| 74627 | GIR_EraseRootFromParent_Done, |
| 74628 | // Label 5014: @190321 |
| 74629 | GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(190369), // Rule ID 53033 // |
| 74630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 74631 | // (saddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 74632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 74633 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74634 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 74637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74638 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74639 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74640 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 74643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74644 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74645 | GIR_RootConstrainSelectedInstOperands, |
| 74646 | // GIR_Coverage, 53033, |
| 74647 | GIR_EraseRootFromParent_Done, |
| 74648 | // Label 5015: @190369 |
| 74649 | GIM_Reject, |
| 74650 | // Label 5013: @190370 |
| 74651 | GIM_Reject, |
| 74652 | // Label 4985: @190371 |
| 74653 | GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(190491), |
| 74654 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 74655 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 74656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74657 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74658 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74659 | GIM_Try, /*On fail goto*//*Label 5017*/ GIMT_Encode4(190442), // Rule ID 53000 // |
| 74660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74661 | // (saddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSADD_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 74662 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 74663 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74664 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF4), |
| 74667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74668 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74669 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74670 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74674 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74675 | GIR_RootConstrainSelectedInstOperands, |
| 74676 | // GIR_Coverage, 53000, |
| 74677 | GIR_EraseRootFromParent_Done, |
| 74678 | // Label 5017: @190442 |
| 74679 | GIM_Try, /*On fail goto*//*Label 5018*/ GIMT_Encode4(190490), // Rule ID 53001 // |
| 74680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74681 | // (saddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSADD_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 74682 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 74683 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74684 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74685 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF4), |
| 74687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74688 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74689 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74690 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74694 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74695 | GIR_RootConstrainSelectedInstOperands, |
| 74696 | // GIR_Coverage, 53001, |
| 74697 | GIR_EraseRootFromParent_Done, |
| 74698 | // Label 5018: @190490 |
| 74699 | GIM_Reject, |
| 74700 | // Label 5016: @190491 |
| 74701 | GIM_Reject, |
| 74702 | // Label 4986: @190492 |
| 74703 | GIM_Try, /*On fail goto*//*Label 5019*/ GIMT_Encode4(190612), |
| 74704 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 74705 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 74706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74708 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74709 | GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(190563), // Rule ID 53012 // |
| 74710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74711 | // (saddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSADD_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 74712 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 74713 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74714 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF2), |
| 74717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74718 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74719 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74720 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74724 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74725 | GIR_RootConstrainSelectedInstOperands, |
| 74726 | // GIR_Coverage, 53012, |
| 74727 | GIR_EraseRootFromParent_Done, |
| 74728 | // Label 5020: @190563 |
| 74729 | GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(190611), // Rule ID 53013 // |
| 74730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74731 | // (saddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSADD_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 74732 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 74733 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74734 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF2), |
| 74737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74738 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74739 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74740 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74744 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74745 | GIR_RootConstrainSelectedInstOperands, |
| 74746 | // GIR_Coverage, 53013, |
| 74747 | GIR_EraseRootFromParent_Done, |
| 74748 | // Label 5021: @190611 |
| 74749 | GIM_Reject, |
| 74750 | // Label 5019: @190612 |
| 74751 | GIM_Reject, |
| 74752 | // Label 4987: @190613 |
| 74753 | GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(190733), |
| 74754 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 74755 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 74756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74757 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74758 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74759 | GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(190684), // Rule ID 53028 // |
| 74760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74761 | // (saddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 74762 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 74763 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74764 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 74767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74768 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74769 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74770 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74774 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74775 | GIR_RootConstrainSelectedInstOperands, |
| 74776 | // GIR_Coverage, 53028, |
| 74777 | GIR_EraseRootFromParent_Done, |
| 74778 | // Label 5023: @190684 |
| 74779 | GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(190732), // Rule ID 53029 // |
| 74780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74781 | // (saddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 74782 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 74783 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74784 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74785 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 74787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74788 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74789 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74790 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74794 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74795 | GIR_RootConstrainSelectedInstOperands, |
| 74796 | // GIR_Coverage, 53029, |
| 74797 | GIR_EraseRootFromParent_Done, |
| 74798 | // Label 5024: @190732 |
| 74799 | GIM_Reject, |
| 74800 | // Label 5022: @190733 |
| 74801 | GIM_Reject, |
| 74802 | // Label 4988: @190734 |
| 74803 | GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(190854), |
| 74804 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 74805 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 74806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74807 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74808 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74809 | GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(190805), // Rule ID 53072 // |
| 74810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 74811 | // (saddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 74812 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 74813 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74814 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 74817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74818 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74819 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74820 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 74823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74824 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74825 | GIR_RootConstrainSelectedInstOperands, |
| 74826 | // GIR_Coverage, 53072, |
| 74827 | GIR_EraseRootFromParent_Done, |
| 74828 | // Label 5026: @190805 |
| 74829 | GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(190853), // Rule ID 53073 // |
| 74830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 74831 | // (saddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 74832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 74833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74834 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74835 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 74837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74838 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74839 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74840 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 74843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74844 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74845 | GIR_RootConstrainSelectedInstOperands, |
| 74846 | // GIR_Coverage, 53073, |
| 74847 | GIR_EraseRootFromParent_Done, |
| 74848 | // Label 5027: @190853 |
| 74849 | GIM_Reject, |
| 74850 | // Label 5025: @190854 |
| 74851 | GIM_Reject, |
| 74852 | // Label 4989: @190855 |
| 74853 | GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(190975), |
| 74854 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 74855 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 74856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74858 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74859 | GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(190926), // Rule ID 53004 // |
| 74860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74861 | // (saddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSADD_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 74862 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 74863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74864 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74865 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF2), |
| 74867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74868 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74869 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74870 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74874 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74875 | GIR_RootConstrainSelectedInstOperands, |
| 74876 | // GIR_Coverage, 53004, |
| 74877 | GIR_EraseRootFromParent_Done, |
| 74878 | // Label 5029: @190926 |
| 74879 | GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(190974), // Rule ID 53005 // |
| 74880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74881 | // (saddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSADD_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 74882 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 74883 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74884 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74885 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_MF2), |
| 74887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74888 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74889 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74890 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74894 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74895 | GIR_RootConstrainSelectedInstOperands, |
| 74896 | // GIR_Coverage, 53005, |
| 74897 | GIR_EraseRootFromParent_Done, |
| 74898 | // Label 5030: @190974 |
| 74899 | GIM_Reject, |
| 74900 | // Label 5028: @190975 |
| 74901 | GIM_Reject, |
| 74902 | // Label 4990: @190976 |
| 74903 | GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(191096), |
| 74904 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 74905 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 74906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74907 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74908 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 74909 | GIM_Try, /*On fail goto*//*Label 5032*/ GIMT_Encode4(191047), // Rule ID 53024 // |
| 74910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74911 | // (saddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 74912 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 74913 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74914 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 74917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74918 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74919 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74920 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74924 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74925 | GIR_RootConstrainSelectedInstOperands, |
| 74926 | // GIR_Coverage, 53024, |
| 74927 | GIR_EraseRootFromParent_Done, |
| 74928 | // Label 5032: @191047 |
| 74929 | GIM_Try, /*On fail goto*//*Label 5033*/ GIMT_Encode4(191095), // Rule ID 53025 // |
| 74930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74931 | // (saddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 74932 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 74933 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74934 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 74937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74938 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74939 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74940 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 74943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74944 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74945 | GIR_RootConstrainSelectedInstOperands, |
| 74946 | // GIR_Coverage, 53025, |
| 74947 | GIR_EraseRootFromParent_Done, |
| 74948 | // Label 5033: @191095 |
| 74949 | GIM_Reject, |
| 74950 | // Label 5031: @191096 |
| 74951 | GIM_Reject, |
| 74952 | // Label 4991: @191097 |
| 74953 | GIM_Try, /*On fail goto*//*Label 5034*/ GIMT_Encode4(191217), |
| 74954 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 74955 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 74956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74957 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74958 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 74959 | GIM_Try, /*On fail goto*//*Label 5035*/ GIMT_Encode4(191168), // Rule ID 53060 // |
| 74960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 74961 | // (saddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 74962 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 74963 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74964 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 74967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74968 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74969 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74970 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74974 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74975 | GIR_RootConstrainSelectedInstOperands, |
| 74976 | // GIR_Coverage, 53060, |
| 74977 | GIR_EraseRootFromParent_Done, |
| 74978 | // Label 5035: @191168 |
| 74979 | GIM_Try, /*On fail goto*//*Label 5036*/ GIMT_Encode4(191216), // Rule ID 53061 // |
| 74980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 74981 | // (saddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 74982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 74983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 74984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 74985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 74986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 74987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 74988 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 74989 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 74990 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 74991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 74992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 74993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 74994 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 74995 | GIR_RootConstrainSelectedInstOperands, |
| 74996 | // GIR_Coverage, 53061, |
| 74997 | GIR_EraseRootFromParent_Done, |
| 74998 | // Label 5036: @191216 |
| 74999 | GIM_Reject, |
| 75000 | // Label 5034: @191217 |
| 75001 | GIM_Reject, |
| 75002 | // Label 4992: @191218 |
| 75003 | GIM_Try, /*On fail goto*//*Label 5037*/ GIMT_Encode4(191338), |
| 75004 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 75005 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 75006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75007 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75008 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75009 | GIM_Try, /*On fail goto*//*Label 5038*/ GIMT_Encode4(191289), // Rule ID 53076 // |
| 75010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 75011 | // (saddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 75012 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 75013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75018 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75019 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75020 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75024 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75025 | GIR_RootConstrainSelectedInstOperands, |
| 75026 | // GIR_Coverage, 53076, |
| 75027 | GIR_EraseRootFromParent_Done, |
| 75028 | // Label 5038: @191289 |
| 75029 | GIM_Try, /*On fail goto*//*Label 5039*/ GIMT_Encode4(191337), // Rule ID 53077 // |
| 75030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 75031 | // (saddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 75032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 75033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75038 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75039 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75040 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75044 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75045 | GIR_RootConstrainSelectedInstOperands, |
| 75046 | // GIR_Coverage, 53077, |
| 75047 | GIR_EraseRootFromParent_Done, |
| 75048 | // Label 5039: @191337 |
| 75049 | GIM_Reject, |
| 75050 | // Label 5037: @191338 |
| 75051 | GIM_Reject, |
| 75052 | // Label 4993: @191339 |
| 75053 | GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(191459), |
| 75054 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 75055 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 75056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75057 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75058 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75059 | GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(191410), // Rule ID 53020 // |
| 75060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75061 | // (saddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75062 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 75063 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75064 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 75067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75068 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75069 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75070 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75074 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75075 | GIR_RootConstrainSelectedInstOperands, |
| 75076 | // GIR_Coverage, 53020, |
| 75077 | GIR_EraseRootFromParent_Done, |
| 75078 | // Label 5041: @191410 |
| 75079 | GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(191458), // Rule ID 53021 // |
| 75080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75081 | // (saddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSADD_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 75082 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 75083 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75084 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75085 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M1), |
| 75087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75088 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75089 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75090 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75094 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75095 | GIR_RootConstrainSelectedInstOperands, |
| 75096 | // GIR_Coverage, 53021, |
| 75097 | GIR_EraseRootFromParent_Done, |
| 75098 | // Label 5042: @191458 |
| 75099 | GIM_Reject, |
| 75100 | // Label 5040: @191459 |
| 75101 | GIM_Reject, |
| 75102 | // Label 4994: @191460 |
| 75103 | GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(191580), |
| 75104 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 75105 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 75106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75107 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75108 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75109 | GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(191531), // Rule ID 53048 // |
| 75110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75111 | // (saddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 75112 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 75113 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75114 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75115 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 75117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75118 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75119 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75120 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75124 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75125 | GIR_RootConstrainSelectedInstOperands, |
| 75126 | // GIR_Coverage, 53048, |
| 75127 | GIR_EraseRootFromParent_Done, |
| 75128 | // Label 5044: @191531 |
| 75129 | GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(191579), // Rule ID 53049 // |
| 75130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75131 | // (saddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 75132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 75133 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75134 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 75137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75138 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75139 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75140 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75144 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75145 | GIR_RootConstrainSelectedInstOperands, |
| 75146 | // GIR_Coverage, 53049, |
| 75147 | GIR_EraseRootFromParent_Done, |
| 75148 | // Label 5045: @191579 |
| 75149 | GIM_Reject, |
| 75150 | // Label 5043: @191580 |
| 75151 | GIM_Reject, |
| 75152 | // Label 4995: @191581 |
| 75153 | GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(191701), |
| 75154 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 75155 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 75156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75157 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75158 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75159 | GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(191652), // Rule ID 53064 // |
| 75160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75161 | // (saddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 75162 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 75163 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75164 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75168 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75169 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75170 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75174 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75175 | GIR_RootConstrainSelectedInstOperands, |
| 75176 | // GIR_Coverage, 53064, |
| 75177 | GIR_EraseRootFromParent_Done, |
| 75178 | // Label 5047: @191652 |
| 75179 | GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(191700), // Rule ID 53065 // |
| 75180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75181 | // (saddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 75182 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 75183 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75184 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75188 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75189 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75190 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75194 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75195 | GIR_RootConstrainSelectedInstOperands, |
| 75196 | // GIR_Coverage, 53065, |
| 75197 | GIR_EraseRootFromParent_Done, |
| 75198 | // Label 5048: @191700 |
| 75199 | GIM_Reject, |
| 75200 | // Label 5046: @191701 |
| 75201 | GIM_Reject, |
| 75202 | // Label 4996: @191702 |
| 75203 | GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(191822), |
| 75204 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 75205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 75206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75207 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75208 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75209 | GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(191773), // Rule ID 53080 // |
| 75210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 75211 | // (saddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 75212 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 75213 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75214 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75215 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75218 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75219 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75220 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75224 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75225 | GIR_RootConstrainSelectedInstOperands, |
| 75226 | // GIR_Coverage, 53080, |
| 75227 | GIR_EraseRootFromParent_Done, |
| 75228 | // Label 5050: @191773 |
| 75229 | GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(191821), // Rule ID 53081 // |
| 75230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 75231 | // (saddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 75232 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 75233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75239 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75240 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75244 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75245 | GIR_RootConstrainSelectedInstOperands, |
| 75246 | // GIR_Coverage, 53081, |
| 75247 | GIR_EraseRootFromParent_Done, |
| 75248 | // Label 5051: @191821 |
| 75249 | GIM_Reject, |
| 75250 | // Label 5049: @191822 |
| 75251 | GIM_Reject, |
| 75252 | // Label 4997: @191823 |
| 75253 | GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(191943), |
| 75254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 75255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 75256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75257 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75258 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75259 | GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(191894), // Rule ID 53036 // |
| 75260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75261 | // (saddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 75263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 75267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75268 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75270 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75274 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75275 | GIR_RootConstrainSelectedInstOperands, |
| 75276 | // GIR_Coverage, 53036, |
| 75277 | GIR_EraseRootFromParent_Done, |
| 75278 | // Label 5053: @191894 |
| 75279 | GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(191942), // Rule ID 53037 // |
| 75280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75281 | // (saddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSADD_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 75282 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 75283 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75284 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75285 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M2), |
| 75287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75288 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75289 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75290 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75294 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75295 | GIR_RootConstrainSelectedInstOperands, |
| 75296 | // GIR_Coverage, 53037, |
| 75297 | GIR_EraseRootFromParent_Done, |
| 75298 | // Label 5054: @191942 |
| 75299 | GIM_Reject, |
| 75300 | // Label 5052: @191943 |
| 75301 | GIM_Reject, |
| 75302 | // Label 4998: @191944 |
| 75303 | GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(192064), |
| 75304 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 75305 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 75306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75307 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75308 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75309 | GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(192015), // Rule ID 53052 // |
| 75310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75311 | // (saddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 75312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 75313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75314 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75315 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75318 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75319 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75320 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75324 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75325 | GIR_RootConstrainSelectedInstOperands, |
| 75326 | // GIR_Coverage, 53052, |
| 75327 | GIR_EraseRootFromParent_Done, |
| 75328 | // Label 5056: @192015 |
| 75329 | GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(192063), // Rule ID 53053 // |
| 75330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75331 | // (saddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 75332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 75333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75339 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75340 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75344 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75345 | GIR_RootConstrainSelectedInstOperands, |
| 75346 | // GIR_Coverage, 53053, |
| 75347 | GIR_EraseRootFromParent_Done, |
| 75348 | // Label 5057: @192063 |
| 75349 | GIM_Reject, |
| 75350 | // Label 5055: @192064 |
| 75351 | GIM_Reject, |
| 75352 | // Label 4999: @192065 |
| 75353 | GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(192185), |
| 75354 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 75355 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 75356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75357 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75358 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75359 | GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(192136), // Rule ID 53068 // |
| 75360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75361 | // (saddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 75362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 75363 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75364 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75368 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75369 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75374 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75375 | GIR_RootConstrainSelectedInstOperands, |
| 75376 | // GIR_Coverage, 53068, |
| 75377 | GIR_EraseRootFromParent_Done, |
| 75378 | // Label 5059: @192136 |
| 75379 | GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(192184), // Rule ID 53069 // |
| 75380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75381 | // (saddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 75382 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 75383 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75384 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75388 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75389 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75390 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75394 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75395 | GIR_RootConstrainSelectedInstOperands, |
| 75396 | // GIR_Coverage, 53069, |
| 75397 | GIR_EraseRootFromParent_Done, |
| 75398 | // Label 5060: @192184 |
| 75399 | GIM_Reject, |
| 75400 | // Label 5058: @192185 |
| 75401 | GIM_Reject, |
| 75402 | // Label 5000: @192186 |
| 75403 | GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(192306), |
| 75404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 75405 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 75406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75407 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75408 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 75409 | GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(192257), // Rule ID 53040 // |
| 75410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75411 | // (saddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75412 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 75413 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75414 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75418 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75419 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75420 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75424 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75425 | GIR_RootConstrainSelectedInstOperands, |
| 75426 | // GIR_Coverage, 53040, |
| 75427 | GIR_EraseRootFromParent_Done, |
| 75428 | // Label 5062: @192257 |
| 75429 | GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(192305), // Rule ID 53041 // |
| 75430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75431 | // (saddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSADD_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 75432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 75433 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75434 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M4), |
| 75437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75438 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75439 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75440 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75444 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75445 | GIR_RootConstrainSelectedInstOperands, |
| 75446 | // GIR_Coverage, 53041, |
| 75447 | GIR_EraseRootFromParent_Done, |
| 75448 | // Label 5063: @192305 |
| 75449 | GIM_Reject, |
| 75450 | // Label 5061: @192306 |
| 75451 | GIM_Reject, |
| 75452 | // Label 5001: @192307 |
| 75453 | GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(192427), |
| 75454 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 75455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 75456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75458 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75459 | GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(192378), // Rule ID 53056 // |
| 75460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75461 | // (saddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 75462 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 75463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75464 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75465 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75468 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75469 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75470 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75474 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75475 | GIR_RootConstrainSelectedInstOperands, |
| 75476 | // GIR_Coverage, 53056, |
| 75477 | GIR_EraseRootFromParent_Done, |
| 75478 | // Label 5065: @192378 |
| 75479 | GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(192426), // Rule ID 53057 // |
| 75480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75481 | // (saddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 75482 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 75483 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75484 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75488 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75489 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75490 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75494 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75495 | GIR_RootConstrainSelectedInstOperands, |
| 75496 | // GIR_Coverage, 53057, |
| 75497 | GIR_EraseRootFromParent_Done, |
| 75498 | // Label 5066: @192426 |
| 75499 | GIM_Reject, |
| 75500 | // Label 5064: @192427 |
| 75501 | GIM_Reject, |
| 75502 | // Label 5002: @192428 |
| 75503 | GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(192548), |
| 75504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 75505 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 75506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75507 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75508 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 75509 | GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(192499), // Rule ID 53044 // |
| 75510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75511 | // (saddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75512 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 75513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75518 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75520 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75524 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75525 | GIR_RootConstrainSelectedInstOperands, |
| 75526 | // GIR_Coverage, 53044, |
| 75527 | GIR_EraseRootFromParent_Done, |
| 75528 | // Label 5068: @192499 |
| 75529 | GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(192547), // Rule ID 53045 // |
| 75530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75531 | // (saddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSADD_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 75532 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 75533 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75534 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSADD_VV_M8), |
| 75537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75539 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75540 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75544 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75545 | GIR_RootConstrainSelectedInstOperands, |
| 75546 | // GIR_Coverage, 53045, |
| 75547 | GIR_EraseRootFromParent_Done, |
| 75548 | // Label 5069: @192547 |
| 75549 | GIM_Reject, |
| 75550 | // Label 5067: @192548 |
| 75551 | GIM_Reject, |
| 75552 | // Label 5003: @192549 |
| 75553 | GIM_Reject, |
| 75554 | // Label 51: @192550 |
| 75555 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(34), /*)*//*default:*//*Label 5092*/ GIMT_Encode4(195335), |
| 75556 | /*GILLT_nxv1s8*//*Label 5070*/ GIMT_Encode4(192673), |
| 75557 | /*GILLT_nxv1s16*//*Label 5071*/ GIMT_Encode4(192794), |
| 75558 | /*GILLT_nxv1s32*//*Label 5072*/ GIMT_Encode4(192915), |
| 75559 | /*GILLT_nxv1s64*//*Label 5073*/ GIMT_Encode4(193036), GIMT_Encode4(0), |
| 75560 | /*GILLT_nxv2s8*//*Label 5074*/ GIMT_Encode4(193157), |
| 75561 | /*GILLT_nxv2s16*//*Label 5075*/ GIMT_Encode4(193278), |
| 75562 | /*GILLT_nxv2s32*//*Label 5076*/ GIMT_Encode4(193399), |
| 75563 | /*GILLT_nxv2s64*//*Label 5077*/ GIMT_Encode4(193520), GIMT_Encode4(0), |
| 75564 | /*GILLT_nxv4s8*//*Label 5078*/ GIMT_Encode4(193641), |
| 75565 | /*GILLT_nxv4s16*//*Label 5079*/ GIMT_Encode4(193762), |
| 75566 | /*GILLT_nxv4s32*//*Label 5080*/ GIMT_Encode4(193883), |
| 75567 | /*GILLT_nxv4s64*//*Label 5081*/ GIMT_Encode4(194004), GIMT_Encode4(0), |
| 75568 | /*GILLT_nxv8s8*//*Label 5082*/ GIMT_Encode4(194125), |
| 75569 | /*GILLT_nxv8s16*//*Label 5083*/ GIMT_Encode4(194246), |
| 75570 | /*GILLT_nxv8s32*//*Label 5084*/ GIMT_Encode4(194367), |
| 75571 | /*GILLT_nxv8s64*//*Label 5085*/ GIMT_Encode4(194488), GIMT_Encode4(0), |
| 75572 | /*GILLT_nxv16s8*//*Label 5086*/ GIMT_Encode4(194609), |
| 75573 | /*GILLT_nxv16s16*//*Label 5087*/ GIMT_Encode4(194730), |
| 75574 | /*GILLT_nxv16s32*//*Label 5088*/ GIMT_Encode4(194851), GIMT_Encode4(0), |
| 75575 | /*GILLT_nxv32s8*//*Label 5089*/ GIMT_Encode4(194972), |
| 75576 | /*GILLT_nxv32s16*//*Label 5090*/ GIMT_Encode4(195093), GIMT_Encode4(0), |
| 75577 | /*GILLT_nxv64s8*//*Label 5091*/ GIMT_Encode4(195214), |
| 75578 | // Label 5070: @192673 |
| 75579 | GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(192793), |
| 75580 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 75581 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 75582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75583 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75584 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75585 | GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(192744), // Rule ID 53348 // |
| 75586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75587 | // (usubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSSUBU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 75589 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75590 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF8), |
| 75593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75595 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75596 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75600 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75601 | GIR_RootConstrainSelectedInstOperands, |
| 75602 | // GIR_Coverage, 53348, |
| 75603 | GIR_EraseRootFromParent_Done, |
| 75604 | // Label 5094: @192744 |
| 75605 | GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(192792), // Rule ID 53349 // |
| 75606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75607 | // (usubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSSUBU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 75608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 75609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF8), |
| 75613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75616 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75620 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75621 | GIR_RootConstrainSelectedInstOperands, |
| 75622 | // GIR_Coverage, 53349, |
| 75623 | GIR_EraseRootFromParent_Done, |
| 75624 | // Label 5095: @192792 |
| 75625 | GIM_Reject, |
| 75626 | // Label 5093: @192793 |
| 75627 | GIM_Reject, |
| 75628 | // Label 5071: @192794 |
| 75629 | GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(192914), |
| 75630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 75631 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 75632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75635 | GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(192865), // Rule ID 53360 // |
| 75636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75637 | // (usubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSSUBU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 75638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 75639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF4), |
| 75643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75645 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75646 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75650 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75651 | GIR_RootConstrainSelectedInstOperands, |
| 75652 | // GIR_Coverage, 53360, |
| 75653 | GIR_EraseRootFromParent_Done, |
| 75654 | // Label 5097: @192865 |
| 75655 | GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(192913), // Rule ID 53361 // |
| 75656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75657 | // (usubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSSUBU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 75658 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 75659 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75660 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF4), |
| 75663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75664 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75665 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75670 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75671 | GIR_RootConstrainSelectedInstOperands, |
| 75672 | // GIR_Coverage, 53361, |
| 75673 | GIR_EraseRootFromParent_Done, |
| 75674 | // Label 5098: @192913 |
| 75675 | GIM_Reject, |
| 75676 | // Label 5096: @192914 |
| 75677 | GIM_Reject, |
| 75678 | // Label 5072: @192915 |
| 75679 | GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(193035), |
| 75680 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 75681 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 75682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75684 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75685 | GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(192986), // Rule ID 53368 // |
| 75686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75687 | // (usubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSSUBU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 75688 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 75689 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75690 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF2), |
| 75693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75694 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75695 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75696 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75700 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75701 | GIR_RootConstrainSelectedInstOperands, |
| 75702 | // GIR_Coverage, 53368, |
| 75703 | GIR_EraseRootFromParent_Done, |
| 75704 | // Label 5100: @192986 |
| 75705 | GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(193034), // Rule ID 53369 // |
| 75706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75707 | // (usubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSSUBU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 75708 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 75709 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75710 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF2), |
| 75713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75714 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75715 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75716 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75720 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75721 | GIR_RootConstrainSelectedInstOperands, |
| 75722 | // GIR_Coverage, 53369, |
| 75723 | GIR_EraseRootFromParent_Done, |
| 75724 | // Label 5101: @193034 |
| 75725 | GIM_Reject, |
| 75726 | // Label 5099: @193035 |
| 75727 | GIM_Reject, |
| 75728 | // Label 5073: @193036 |
| 75729 | GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(193156), |
| 75730 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 75731 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 75732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75733 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75734 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75735 | GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(193107), // Rule ID 53384 // |
| 75736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 75737 | // (usubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 75738 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 75739 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75740 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75741 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 75743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75744 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75745 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75746 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75750 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75751 | GIR_RootConstrainSelectedInstOperands, |
| 75752 | // GIR_Coverage, 53384, |
| 75753 | GIR_EraseRootFromParent_Done, |
| 75754 | // Label 5103: @193107 |
| 75755 | GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(193155), // Rule ID 53385 // |
| 75756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 75757 | // (usubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 75758 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 75759 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75760 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 75763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75764 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75765 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75766 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75770 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75771 | GIR_RootConstrainSelectedInstOperands, |
| 75772 | // GIR_Coverage, 53385, |
| 75773 | GIR_EraseRootFromParent_Done, |
| 75774 | // Label 5104: @193155 |
| 75775 | GIM_Reject, |
| 75776 | // Label 5102: @193156 |
| 75777 | GIM_Reject, |
| 75778 | // Label 5074: @193157 |
| 75779 | GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(193277), |
| 75780 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 75781 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 75782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75784 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75785 | GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(193228), // Rule ID 53352 // |
| 75786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75787 | // (usubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSSUBU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75788 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 75789 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75790 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF4), |
| 75793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75794 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75795 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75796 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75800 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75801 | GIR_RootConstrainSelectedInstOperands, |
| 75802 | // GIR_Coverage, 53352, |
| 75803 | GIR_EraseRootFromParent_Done, |
| 75804 | // Label 5106: @193228 |
| 75805 | GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(193276), // Rule ID 53353 // |
| 75806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75807 | // (usubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSSUBU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 75808 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 75809 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75810 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF4), |
| 75813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75814 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75815 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75816 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75820 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75821 | GIR_RootConstrainSelectedInstOperands, |
| 75822 | // GIR_Coverage, 53353, |
| 75823 | GIR_EraseRootFromParent_Done, |
| 75824 | // Label 5107: @193276 |
| 75825 | GIM_Reject, |
| 75826 | // Label 5105: @193277 |
| 75827 | GIM_Reject, |
| 75828 | // Label 5075: @193278 |
| 75829 | GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(193398), |
| 75830 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 75831 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 75832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75834 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75835 | GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(193349), // Rule ID 53364 // |
| 75836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75837 | // (usubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSSUBU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 75838 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 75839 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75840 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF2), |
| 75843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75844 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75845 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75846 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75850 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75851 | GIR_RootConstrainSelectedInstOperands, |
| 75852 | // GIR_Coverage, 53364, |
| 75853 | GIR_EraseRootFromParent_Done, |
| 75854 | // Label 5109: @193349 |
| 75855 | GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(193397), // Rule ID 53365 // |
| 75856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75857 | // (usubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSSUBU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 75858 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 75859 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75860 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75861 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF2), |
| 75863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75864 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75865 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75866 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 75869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75870 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75871 | GIR_RootConstrainSelectedInstOperands, |
| 75872 | // GIR_Coverage, 53365, |
| 75873 | GIR_EraseRootFromParent_Done, |
| 75874 | // Label 5110: @193397 |
| 75875 | GIM_Reject, |
| 75876 | // Label 5108: @193398 |
| 75877 | GIM_Reject, |
| 75878 | // Label 5076: @193399 |
| 75879 | GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(193519), |
| 75880 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 75881 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 75882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75883 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75884 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75885 | GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(193470), // Rule ID 53380 // |
| 75886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75887 | // (usubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 75888 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 75889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75891 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 75893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75894 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75895 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75896 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75900 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75901 | GIR_RootConstrainSelectedInstOperands, |
| 75902 | // GIR_Coverage, 53380, |
| 75903 | GIR_EraseRootFromParent_Done, |
| 75904 | // Label 5112: @193470 |
| 75905 | GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(193518), // Rule ID 53381 // |
| 75906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 75907 | // (usubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 75908 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 75909 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75910 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 75913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75914 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75915 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75916 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 75919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75920 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75921 | GIR_RootConstrainSelectedInstOperands, |
| 75922 | // GIR_Coverage, 53381, |
| 75923 | GIR_EraseRootFromParent_Done, |
| 75924 | // Label 5113: @193518 |
| 75925 | GIM_Reject, |
| 75926 | // Label 5111: @193519 |
| 75927 | GIM_Reject, |
| 75928 | // Label 5077: @193520 |
| 75929 | GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(193640), |
| 75930 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 75931 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 75932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75934 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 75935 | GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(193591), // Rule ID 53424 // |
| 75936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 75937 | // (usubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 75938 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 75939 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75940 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 75943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75944 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75945 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75946 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75950 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75951 | GIR_RootConstrainSelectedInstOperands, |
| 75952 | // GIR_Coverage, 53424, |
| 75953 | GIR_EraseRootFromParent_Done, |
| 75954 | // Label 5115: @193591 |
| 75955 | GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(193639), // Rule ID 53425 // |
| 75956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 75957 | // (usubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 75958 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 75959 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75960 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 75963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75964 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75965 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75966 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 75969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75970 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 75971 | GIR_RootConstrainSelectedInstOperands, |
| 75972 | // GIR_Coverage, 53425, |
| 75973 | GIR_EraseRootFromParent_Done, |
| 75974 | // Label 5116: @193639 |
| 75975 | GIM_Reject, |
| 75976 | // Label 5114: @193640 |
| 75977 | GIM_Reject, |
| 75978 | // Label 5078: @193641 |
| 75979 | GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(193761), |
| 75980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 75981 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 75982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75983 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 75985 | GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(193712), // Rule ID 53356 // |
| 75986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 75987 | // (usubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSSUBU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 75988 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 75989 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 75990 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 75991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 75992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF2), |
| 75993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 75994 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 75995 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 75996 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 75997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 75998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 75999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76000 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76001 | GIR_RootConstrainSelectedInstOperands, |
| 76002 | // GIR_Coverage, 53356, |
| 76003 | GIR_EraseRootFromParent_Done, |
| 76004 | // Label 5118: @193712 |
| 76005 | GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(193760), // Rule ID 53357 // |
| 76006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76007 | // (usubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSSUBU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76008 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 76009 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76010 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_MF2), |
| 76013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76014 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76015 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76016 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76020 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76021 | GIR_RootConstrainSelectedInstOperands, |
| 76022 | // GIR_Coverage, 53357, |
| 76023 | GIR_EraseRootFromParent_Done, |
| 76024 | // Label 5119: @193760 |
| 76025 | GIM_Reject, |
| 76026 | // Label 5117: @193761 |
| 76027 | GIM_Reject, |
| 76028 | // Label 5079: @193762 |
| 76029 | GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(193882), |
| 76030 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 76031 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 76032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76033 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76034 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76035 | GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(193833), // Rule ID 53376 // |
| 76036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76037 | // (usubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 76038 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 76039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76040 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 76043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76044 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76045 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76046 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76050 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76051 | GIR_RootConstrainSelectedInstOperands, |
| 76052 | // GIR_Coverage, 53376, |
| 76053 | GIR_EraseRootFromParent_Done, |
| 76054 | // Label 5121: @193833 |
| 76055 | GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(193881), // Rule ID 53377 // |
| 76056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76057 | // (usubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 76058 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 76059 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76060 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 76063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76064 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76065 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76066 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76070 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76071 | GIR_RootConstrainSelectedInstOperands, |
| 76072 | // GIR_Coverage, 53377, |
| 76073 | GIR_EraseRootFromParent_Done, |
| 76074 | // Label 5122: @193881 |
| 76075 | GIM_Reject, |
| 76076 | // Label 5120: @193882 |
| 76077 | GIM_Reject, |
| 76078 | // Label 5080: @193883 |
| 76079 | GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(194003), |
| 76080 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 76081 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 76082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76084 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76085 | GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(193954), // Rule ID 53412 // |
| 76086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76087 | // (usubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 76088 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 76089 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76090 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 76093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76095 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76096 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76100 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76101 | GIR_RootConstrainSelectedInstOperands, |
| 76102 | // GIR_Coverage, 53412, |
| 76103 | GIR_EraseRootFromParent_Done, |
| 76104 | // Label 5124: @193954 |
| 76105 | GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(194002), // Rule ID 53413 // |
| 76106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76107 | // (usubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 76108 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 76109 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76110 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76111 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 76113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76114 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76115 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76116 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76120 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76121 | GIR_RootConstrainSelectedInstOperands, |
| 76122 | // GIR_Coverage, 53413, |
| 76123 | GIR_EraseRootFromParent_Done, |
| 76124 | // Label 5125: @194002 |
| 76125 | GIM_Reject, |
| 76126 | // Label 5123: @194003 |
| 76127 | GIM_Reject, |
| 76128 | // Label 5081: @194004 |
| 76129 | GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(194124), |
| 76130 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 76131 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 76132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76133 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76134 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76135 | GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(194075), // Rule ID 53428 // |
| 76136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 76137 | // (usubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 76138 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 76139 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76140 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76141 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76144 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76145 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76146 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 76149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76150 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76151 | GIR_RootConstrainSelectedInstOperands, |
| 76152 | // GIR_Coverage, 53428, |
| 76153 | GIR_EraseRootFromParent_Done, |
| 76154 | // Label 5127: @194075 |
| 76155 | GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(194123), // Rule ID 53429 // |
| 76156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 76157 | // (usubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 76158 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 76159 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76160 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76161 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76164 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76165 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76166 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 76169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76170 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76171 | GIR_RootConstrainSelectedInstOperands, |
| 76172 | // GIR_Coverage, 53429, |
| 76173 | GIR_EraseRootFromParent_Done, |
| 76174 | // Label 5128: @194123 |
| 76175 | GIM_Reject, |
| 76176 | // Label 5126: @194124 |
| 76177 | GIM_Reject, |
| 76178 | // Label 5082: @194125 |
| 76179 | GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(194245), |
| 76180 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 76181 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 76182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76183 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76184 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76185 | GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(194196), // Rule ID 53372 // |
| 76186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76187 | // (usubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 76188 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 76189 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76190 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 76193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76194 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76196 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76200 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76201 | GIR_RootConstrainSelectedInstOperands, |
| 76202 | // GIR_Coverage, 53372, |
| 76203 | GIR_EraseRootFromParent_Done, |
| 76204 | // Label 5130: @194196 |
| 76205 | GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(194244), // Rule ID 53373 // |
| 76206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76207 | // (usubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSSUBU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76208 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 76209 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76210 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76211 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M1), |
| 76213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76214 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76215 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76216 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76220 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76221 | GIR_RootConstrainSelectedInstOperands, |
| 76222 | // GIR_Coverage, 53373, |
| 76223 | GIR_EraseRootFromParent_Done, |
| 76224 | // Label 5131: @194244 |
| 76225 | GIM_Reject, |
| 76226 | // Label 5129: @194245 |
| 76227 | GIM_Reject, |
| 76228 | // Label 5083: @194246 |
| 76229 | GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(194366), |
| 76230 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 76231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 76232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76233 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76234 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76235 | GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(194317), // Rule ID 53400 // |
| 76236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76237 | // (usubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 76238 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 76239 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76240 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 76243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76244 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76245 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76246 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76250 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76251 | GIR_RootConstrainSelectedInstOperands, |
| 76252 | // GIR_Coverage, 53400, |
| 76253 | GIR_EraseRootFromParent_Done, |
| 76254 | // Label 5133: @194317 |
| 76255 | GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(194365), // Rule ID 53401 // |
| 76256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76257 | // (usubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 76258 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 76259 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76260 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76261 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 76263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76264 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76265 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76266 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76270 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76271 | GIR_RootConstrainSelectedInstOperands, |
| 76272 | // GIR_Coverage, 53401, |
| 76273 | GIR_EraseRootFromParent_Done, |
| 76274 | // Label 5134: @194365 |
| 76275 | GIM_Reject, |
| 76276 | // Label 5132: @194366 |
| 76277 | GIM_Reject, |
| 76278 | // Label 5084: @194367 |
| 76279 | GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(194487), |
| 76280 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 76281 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 76282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76284 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76285 | GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(194438), // Rule ID 53416 // |
| 76286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76287 | // (usubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 76288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 76289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76300 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76301 | GIR_RootConstrainSelectedInstOperands, |
| 76302 | // GIR_Coverage, 53416, |
| 76303 | GIR_EraseRootFromParent_Done, |
| 76304 | // Label 5136: @194438 |
| 76305 | GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(194486), // Rule ID 53417 // |
| 76306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76307 | // (usubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 76308 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 76309 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76310 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76311 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76314 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76315 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76316 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76320 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76321 | GIR_RootConstrainSelectedInstOperands, |
| 76322 | // GIR_Coverage, 53417, |
| 76323 | GIR_EraseRootFromParent_Done, |
| 76324 | // Label 5137: @194486 |
| 76325 | GIM_Reject, |
| 76326 | // Label 5135: @194487 |
| 76327 | GIM_Reject, |
| 76328 | // Label 5085: @194488 |
| 76329 | GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(194608), |
| 76330 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 76331 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 76332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76333 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76334 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76335 | GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(194559), // Rule ID 53432 // |
| 76336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 76337 | // (usubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 76338 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 76339 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76340 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76341 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76344 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76345 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76346 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 76349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76350 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76351 | GIR_RootConstrainSelectedInstOperands, |
| 76352 | // GIR_Coverage, 53432, |
| 76353 | GIR_EraseRootFromParent_Done, |
| 76354 | // Label 5139: @194559 |
| 76355 | GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(194607), // Rule ID 53433 // |
| 76356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 76357 | // (usubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 76358 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 76359 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76360 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76361 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76364 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76365 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76366 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 76369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76370 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76371 | GIR_RootConstrainSelectedInstOperands, |
| 76372 | // GIR_Coverage, 53433, |
| 76373 | GIR_EraseRootFromParent_Done, |
| 76374 | // Label 5140: @194607 |
| 76375 | GIM_Reject, |
| 76376 | // Label 5138: @194608 |
| 76377 | GIM_Reject, |
| 76378 | // Label 5086: @194609 |
| 76379 | GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(194729), |
| 76380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 76381 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 76382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76383 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76384 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 76385 | GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(194680), // Rule ID 53388 // |
| 76386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76387 | // (usubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 76388 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 76389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 76393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76394 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76395 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76396 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76400 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76401 | GIR_RootConstrainSelectedInstOperands, |
| 76402 | // GIR_Coverage, 53388, |
| 76403 | GIR_EraseRootFromParent_Done, |
| 76404 | // Label 5142: @194680 |
| 76405 | GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(194728), // Rule ID 53389 // |
| 76406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76407 | // (usubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSSUBU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76408 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 76409 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76410 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76411 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M2), |
| 76413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76414 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76415 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76416 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76420 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76421 | GIR_RootConstrainSelectedInstOperands, |
| 76422 | // GIR_Coverage, 53389, |
| 76423 | GIR_EraseRootFromParent_Done, |
| 76424 | // Label 5143: @194728 |
| 76425 | GIM_Reject, |
| 76426 | // Label 5141: @194729 |
| 76427 | GIM_Reject, |
| 76428 | // Label 5087: @194730 |
| 76429 | GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(194850), |
| 76430 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 76431 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 76432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76433 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76434 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76435 | GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(194801), // Rule ID 53404 // |
| 76436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76437 | // (usubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 76438 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 76439 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76440 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76441 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76444 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76445 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76450 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76451 | GIR_RootConstrainSelectedInstOperands, |
| 76452 | // GIR_Coverage, 53404, |
| 76453 | GIR_EraseRootFromParent_Done, |
| 76454 | // Label 5145: @194801 |
| 76455 | GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(194849), // Rule ID 53405 // |
| 76456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76457 | // (usubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 76458 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 76459 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76460 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76464 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76465 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76466 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76470 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76471 | GIR_RootConstrainSelectedInstOperands, |
| 76472 | // GIR_Coverage, 53405, |
| 76473 | GIR_EraseRootFromParent_Done, |
| 76474 | // Label 5146: @194849 |
| 76475 | GIM_Reject, |
| 76476 | // Label 5144: @194850 |
| 76477 | GIM_Reject, |
| 76478 | // Label 5088: @194851 |
| 76479 | GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(194971), |
| 76480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 76481 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 76482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76483 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76484 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76485 | GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(194922), // Rule ID 53420 // |
| 76486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76487 | // (usubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 76488 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 76489 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76490 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76494 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76495 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76496 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76500 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76501 | GIR_RootConstrainSelectedInstOperands, |
| 76502 | // GIR_Coverage, 53420, |
| 76503 | GIR_EraseRootFromParent_Done, |
| 76504 | // Label 5148: @194922 |
| 76505 | GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(194970), // Rule ID 53421 // |
| 76506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76507 | // (usubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 76508 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 76509 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76510 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76514 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76515 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76516 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76520 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76521 | GIR_RootConstrainSelectedInstOperands, |
| 76522 | // GIR_Coverage, 53421, |
| 76523 | GIR_EraseRootFromParent_Done, |
| 76524 | // Label 5149: @194970 |
| 76525 | GIM_Reject, |
| 76526 | // Label 5147: @194971 |
| 76527 | GIM_Reject, |
| 76528 | // Label 5089: @194972 |
| 76529 | GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(195092), |
| 76530 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 76531 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 76532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76534 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 76535 | GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(195043), // Rule ID 53392 // |
| 76536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76537 | // (usubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 76538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 76539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76545 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76546 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76550 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76551 | GIR_RootConstrainSelectedInstOperands, |
| 76552 | // GIR_Coverage, 53392, |
| 76553 | GIR_EraseRootFromParent_Done, |
| 76554 | // Label 5151: @195043 |
| 76555 | GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(195091), // Rule ID 53393 // |
| 76556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76557 | // (usubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSSUBU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76558 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 76559 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76560 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M4), |
| 76563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76564 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76565 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76566 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76570 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76571 | GIR_RootConstrainSelectedInstOperands, |
| 76572 | // GIR_Coverage, 53393, |
| 76573 | GIR_EraseRootFromParent_Done, |
| 76574 | // Label 5152: @195091 |
| 76575 | GIM_Reject, |
| 76576 | // Label 5150: @195092 |
| 76577 | GIM_Reject, |
| 76578 | // Label 5090: @195093 |
| 76579 | GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(195213), |
| 76580 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 76581 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 76582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76583 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76584 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76585 | GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(195164), // Rule ID 53408 // |
| 76586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76587 | // (usubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 76588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 76589 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76590 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76595 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76596 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76600 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76601 | GIR_RootConstrainSelectedInstOperands, |
| 76602 | // GIR_Coverage, 53408, |
| 76603 | GIR_EraseRootFromParent_Done, |
| 76604 | // Label 5154: @195164 |
| 76605 | GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(195212), // Rule ID 53409 // |
| 76606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76607 | // (usubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 76608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 76609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76616 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76620 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76621 | GIR_RootConstrainSelectedInstOperands, |
| 76622 | // GIR_Coverage, 53409, |
| 76623 | GIR_EraseRootFromParent_Done, |
| 76624 | // Label 5155: @195212 |
| 76625 | GIM_Reject, |
| 76626 | // Label 5153: @195213 |
| 76627 | GIM_Reject, |
| 76628 | // Label 5091: @195214 |
| 76629 | GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(195334), |
| 76630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 76631 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 76632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 76635 | GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(195285), // Rule ID 53396 // |
| 76636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76637 | // (usubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 76638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 76639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76645 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76646 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76650 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76651 | GIR_RootConstrainSelectedInstOperands, |
| 76652 | // GIR_Coverage, 53396, |
| 76653 | GIR_EraseRootFromParent_Done, |
| 76654 | // Label 5157: @195285 |
| 76655 | GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(195333), // Rule ID 53397 // |
| 76656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76657 | // (usubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSSUBU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76658 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 76659 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76660 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUBU_VV_M8), |
| 76663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76664 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76665 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76666 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76670 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76671 | GIR_RootConstrainSelectedInstOperands, |
| 76672 | // GIR_Coverage, 53397, |
| 76673 | GIR_EraseRootFromParent_Done, |
| 76674 | // Label 5158: @195333 |
| 76675 | GIM_Reject, |
| 76676 | // Label 5156: @195334 |
| 76677 | GIM_Reject, |
| 76678 | // Label 5092: @195335 |
| 76679 | GIM_Reject, |
| 76680 | // Label 52: @195336 |
| 76681 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(34), /*)*//*default:*//*Label 5181*/ GIMT_Encode4(198121), |
| 76682 | /*GILLT_nxv1s8*//*Label 5159*/ GIMT_Encode4(195459), |
| 76683 | /*GILLT_nxv1s16*//*Label 5160*/ GIMT_Encode4(195580), |
| 76684 | /*GILLT_nxv1s32*//*Label 5161*/ GIMT_Encode4(195701), |
| 76685 | /*GILLT_nxv1s64*//*Label 5162*/ GIMT_Encode4(195822), GIMT_Encode4(0), |
| 76686 | /*GILLT_nxv2s8*//*Label 5163*/ GIMT_Encode4(195943), |
| 76687 | /*GILLT_nxv2s16*//*Label 5164*/ GIMT_Encode4(196064), |
| 76688 | /*GILLT_nxv2s32*//*Label 5165*/ GIMT_Encode4(196185), |
| 76689 | /*GILLT_nxv2s64*//*Label 5166*/ GIMT_Encode4(196306), GIMT_Encode4(0), |
| 76690 | /*GILLT_nxv4s8*//*Label 5167*/ GIMT_Encode4(196427), |
| 76691 | /*GILLT_nxv4s16*//*Label 5168*/ GIMT_Encode4(196548), |
| 76692 | /*GILLT_nxv4s32*//*Label 5169*/ GIMT_Encode4(196669), |
| 76693 | /*GILLT_nxv4s64*//*Label 5170*/ GIMT_Encode4(196790), GIMT_Encode4(0), |
| 76694 | /*GILLT_nxv8s8*//*Label 5171*/ GIMT_Encode4(196911), |
| 76695 | /*GILLT_nxv8s16*//*Label 5172*/ GIMT_Encode4(197032), |
| 76696 | /*GILLT_nxv8s32*//*Label 5173*/ GIMT_Encode4(197153), |
| 76697 | /*GILLT_nxv8s64*//*Label 5174*/ GIMT_Encode4(197274), GIMT_Encode4(0), |
| 76698 | /*GILLT_nxv16s8*//*Label 5175*/ GIMT_Encode4(197395), |
| 76699 | /*GILLT_nxv16s16*//*Label 5176*/ GIMT_Encode4(197516), |
| 76700 | /*GILLT_nxv16s32*//*Label 5177*/ GIMT_Encode4(197637), GIMT_Encode4(0), |
| 76701 | /*GILLT_nxv32s8*//*Label 5178*/ GIMT_Encode4(197758), |
| 76702 | /*GILLT_nxv32s16*//*Label 5179*/ GIMT_Encode4(197879), GIMT_Encode4(0), |
| 76703 | /*GILLT_nxv64s8*//*Label 5180*/ GIMT_Encode4(198000), |
| 76704 | // Label 5159: @195459 |
| 76705 | GIM_Try, /*On fail goto*//*Label 5182*/ GIMT_Encode4(195579), |
| 76706 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 76707 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 76708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76709 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76710 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76711 | GIM_Try, /*On fail goto*//*Label 5183*/ GIMT_Encode4(195530), // Rule ID 53260 // |
| 76712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76713 | // (ssubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSSUB_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 76714 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 76715 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76716 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76717 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF8), |
| 76719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76721 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76722 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76726 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76727 | GIR_RootConstrainSelectedInstOperands, |
| 76728 | // GIR_Coverage, 53260, |
| 76729 | GIR_EraseRootFromParent_Done, |
| 76730 | // Label 5183: @195530 |
| 76731 | GIM_Try, /*On fail goto*//*Label 5184*/ GIMT_Encode4(195578), // Rule ID 53261 // |
| 76732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76733 | // (ssubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSSUB_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76734 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 76735 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76736 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF8), |
| 76739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76740 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76741 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76742 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76746 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76747 | GIR_RootConstrainSelectedInstOperands, |
| 76748 | // GIR_Coverage, 53261, |
| 76749 | GIR_EraseRootFromParent_Done, |
| 76750 | // Label 5184: @195578 |
| 76751 | GIM_Reject, |
| 76752 | // Label 5182: @195579 |
| 76753 | GIM_Reject, |
| 76754 | // Label 5160: @195580 |
| 76755 | GIM_Try, /*On fail goto*//*Label 5185*/ GIMT_Encode4(195700), |
| 76756 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 76757 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 76758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76761 | GIM_Try, /*On fail goto*//*Label 5186*/ GIMT_Encode4(195651), // Rule ID 53272 // |
| 76762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76763 | // (ssubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSSUB_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 76764 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 76765 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF4), |
| 76769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76771 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76772 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76776 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76777 | GIR_RootConstrainSelectedInstOperands, |
| 76778 | // GIR_Coverage, 53272, |
| 76779 | GIR_EraseRootFromParent_Done, |
| 76780 | // Label 5186: @195651 |
| 76781 | GIM_Try, /*On fail goto*//*Label 5187*/ GIMT_Encode4(195699), // Rule ID 53273 // |
| 76782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76783 | // (ssubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSSUB_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 76784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 76785 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF4), |
| 76789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76790 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76791 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76792 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76796 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76797 | GIR_RootConstrainSelectedInstOperands, |
| 76798 | // GIR_Coverage, 53273, |
| 76799 | GIR_EraseRootFromParent_Done, |
| 76800 | // Label 5187: @195699 |
| 76801 | GIM_Reject, |
| 76802 | // Label 5185: @195700 |
| 76803 | GIM_Reject, |
| 76804 | // Label 5161: @195701 |
| 76805 | GIM_Try, /*On fail goto*//*Label 5188*/ GIMT_Encode4(195821), |
| 76806 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 76807 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 76808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76809 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76810 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76811 | GIM_Try, /*On fail goto*//*Label 5189*/ GIMT_Encode4(195772), // Rule ID 53280 // |
| 76812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76813 | // (ssubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSSUB_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 76814 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 76815 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76816 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76817 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF2), |
| 76819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76820 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76821 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76822 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76826 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76827 | GIR_RootConstrainSelectedInstOperands, |
| 76828 | // GIR_Coverage, 53280, |
| 76829 | GIR_EraseRootFromParent_Done, |
| 76830 | // Label 5189: @195772 |
| 76831 | GIM_Try, /*On fail goto*//*Label 5190*/ GIMT_Encode4(195820), // Rule ID 53281 // |
| 76832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76833 | // (ssubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSSUB_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 76834 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 76835 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76836 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF2), |
| 76839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76840 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76841 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76842 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 76845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76846 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76847 | GIR_RootConstrainSelectedInstOperands, |
| 76848 | // GIR_Coverage, 53281, |
| 76849 | GIR_EraseRootFromParent_Done, |
| 76850 | // Label 5190: @195820 |
| 76851 | GIM_Reject, |
| 76852 | // Label 5188: @195821 |
| 76853 | GIM_Reject, |
| 76854 | // Label 5162: @195822 |
| 76855 | GIM_Try, /*On fail goto*//*Label 5191*/ GIMT_Encode4(195942), |
| 76856 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 76857 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 76858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76859 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76860 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76861 | GIM_Try, /*On fail goto*//*Label 5192*/ GIMT_Encode4(195893), // Rule ID 53296 // |
| 76862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 76863 | // (ssubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 76864 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 76865 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76866 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 76869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76870 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76871 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 76875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76876 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76877 | GIR_RootConstrainSelectedInstOperands, |
| 76878 | // GIR_Coverage, 53296, |
| 76879 | GIR_EraseRootFromParent_Done, |
| 76880 | // Label 5192: @195893 |
| 76881 | GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(195941), // Rule ID 53297 // |
| 76882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 76883 | // (ssubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 76884 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 76885 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76886 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 76889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76890 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76891 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76892 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 76895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76896 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76897 | GIR_RootConstrainSelectedInstOperands, |
| 76898 | // GIR_Coverage, 53297, |
| 76899 | GIR_EraseRootFromParent_Done, |
| 76900 | // Label 5193: @195941 |
| 76901 | GIM_Reject, |
| 76902 | // Label 5191: @195942 |
| 76903 | GIM_Reject, |
| 76904 | // Label 5163: @195943 |
| 76905 | GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(196063), |
| 76906 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 76907 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 76908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76911 | GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(196014), // Rule ID 53264 // |
| 76912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76913 | // (ssubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSSUB_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 76914 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 76915 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76916 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF4), |
| 76919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76920 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76921 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76922 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76926 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76927 | GIR_RootConstrainSelectedInstOperands, |
| 76928 | // GIR_Coverage, 53264, |
| 76929 | GIR_EraseRootFromParent_Done, |
| 76930 | // Label 5195: @196014 |
| 76931 | GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(196062), // Rule ID 53265 // |
| 76932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76933 | // (ssubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSSUB_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 76934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 76935 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76936 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76937 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF4), |
| 76939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76940 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76941 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76942 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76946 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76947 | GIR_RootConstrainSelectedInstOperands, |
| 76948 | // GIR_Coverage, 53265, |
| 76949 | GIR_EraseRootFromParent_Done, |
| 76950 | // Label 5196: @196062 |
| 76951 | GIM_Reject, |
| 76952 | // Label 5194: @196063 |
| 76953 | GIM_Reject, |
| 76954 | // Label 5164: @196064 |
| 76955 | GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(196184), |
| 76956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 76957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 76958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76960 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 76961 | GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(196135), // Rule ID 53276 // |
| 76962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 76963 | // (ssubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSSUB_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 76964 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 76965 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76966 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF2), |
| 76969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76970 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76971 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76972 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76976 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76977 | GIR_RootConstrainSelectedInstOperands, |
| 76978 | // GIR_Coverage, 53276, |
| 76979 | GIR_EraseRootFromParent_Done, |
| 76980 | // Label 5198: @196135 |
| 76981 | GIM_Try, /*On fail goto*//*Label 5199*/ GIMT_Encode4(196183), // Rule ID 53277 // |
| 76982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 76983 | // (ssubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSSUB_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 76984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 76985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 76986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 76987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 76988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF2), |
| 76989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 76990 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 76991 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 76992 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 76993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 76994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 76995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 76996 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 76997 | GIR_RootConstrainSelectedInstOperands, |
| 76998 | // GIR_Coverage, 53277, |
| 76999 | GIR_EraseRootFromParent_Done, |
| 77000 | // Label 5199: @196183 |
| 77001 | GIM_Reject, |
| 77002 | // Label 5197: @196184 |
| 77003 | GIM_Reject, |
| 77004 | // Label 5165: @196185 |
| 77005 | GIM_Try, /*On fail goto*//*Label 5200*/ GIMT_Encode4(196305), |
| 77006 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 77007 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 77008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77010 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77011 | GIM_Try, /*On fail goto*//*Label 5201*/ GIMT_Encode4(196256), // Rule ID 53292 // |
| 77012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77013 | // (ssubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 77014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 77015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77017 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 77019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77020 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77021 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77022 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77026 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77027 | GIR_RootConstrainSelectedInstOperands, |
| 77028 | // GIR_Coverage, 53292, |
| 77029 | GIR_EraseRootFromParent_Done, |
| 77030 | // Label 5201: @196256 |
| 77031 | GIM_Try, /*On fail goto*//*Label 5202*/ GIMT_Encode4(196304), // Rule ID 53293 // |
| 77032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77033 | // (ssubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 77034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 77035 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77036 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77037 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 77039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77040 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77041 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77042 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77046 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77047 | GIR_RootConstrainSelectedInstOperands, |
| 77048 | // GIR_Coverage, 53293, |
| 77049 | GIR_EraseRootFromParent_Done, |
| 77050 | // Label 5202: @196304 |
| 77051 | GIM_Reject, |
| 77052 | // Label 5200: @196305 |
| 77053 | GIM_Reject, |
| 77054 | // Label 5166: @196306 |
| 77055 | GIM_Try, /*On fail goto*//*Label 5203*/ GIMT_Encode4(196426), |
| 77056 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 77057 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 77058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77059 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77060 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77061 | GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(196377), // Rule ID 53336 // |
| 77062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 77063 | // (ssubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 77064 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 77065 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77066 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77070 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77071 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77072 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 77075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77076 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77077 | GIR_RootConstrainSelectedInstOperands, |
| 77078 | // GIR_Coverage, 53336, |
| 77079 | GIR_EraseRootFromParent_Done, |
| 77080 | // Label 5204: @196377 |
| 77081 | GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(196425), // Rule ID 53337 // |
| 77082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 77083 | // (ssubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 77084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 77085 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77086 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77090 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77091 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77092 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 77095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77096 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77097 | GIR_RootConstrainSelectedInstOperands, |
| 77098 | // GIR_Coverage, 53337, |
| 77099 | GIR_EraseRootFromParent_Done, |
| 77100 | // Label 5205: @196425 |
| 77101 | GIM_Reject, |
| 77102 | // Label 5203: @196426 |
| 77103 | GIM_Reject, |
| 77104 | // Label 5167: @196427 |
| 77105 | GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(196547), |
| 77106 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 77107 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 77108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77110 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77111 | GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(196498), // Rule ID 53268 // |
| 77112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77113 | // (ssubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSSUB_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 77114 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 77115 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77116 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF2), |
| 77119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77120 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77121 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77122 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77126 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77127 | GIR_RootConstrainSelectedInstOperands, |
| 77128 | // GIR_Coverage, 53268, |
| 77129 | GIR_EraseRootFromParent_Done, |
| 77130 | // Label 5207: @196498 |
| 77131 | GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(196546), // Rule ID 53269 // |
| 77132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77133 | // (ssubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSSUB_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 77134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 77135 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77136 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_MF2), |
| 77139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77141 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77142 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77146 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77147 | GIR_RootConstrainSelectedInstOperands, |
| 77148 | // GIR_Coverage, 53269, |
| 77149 | GIR_EraseRootFromParent_Done, |
| 77150 | // Label 5208: @196546 |
| 77151 | GIM_Reject, |
| 77152 | // Label 5206: @196547 |
| 77153 | GIM_Reject, |
| 77154 | // Label 5168: @196548 |
| 77155 | GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(196668), |
| 77156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 77157 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 77158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77159 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77160 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77161 | GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(196619), // Rule ID 53288 // |
| 77162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77163 | // (ssubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 77164 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 77165 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77166 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 77169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77170 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77171 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77172 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77176 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77177 | GIR_RootConstrainSelectedInstOperands, |
| 77178 | // GIR_Coverage, 53288, |
| 77179 | GIR_EraseRootFromParent_Done, |
| 77180 | // Label 5210: @196619 |
| 77181 | GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(196667), // Rule ID 53289 // |
| 77182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77183 | // (ssubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 77184 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 77185 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77186 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 77189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77190 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77191 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77192 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77196 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77197 | GIR_RootConstrainSelectedInstOperands, |
| 77198 | // GIR_Coverage, 53289, |
| 77199 | GIR_EraseRootFromParent_Done, |
| 77200 | // Label 5211: @196667 |
| 77201 | GIM_Reject, |
| 77202 | // Label 5209: @196668 |
| 77203 | GIM_Reject, |
| 77204 | // Label 5169: @196669 |
| 77205 | GIM_Try, /*On fail goto*//*Label 5212*/ GIMT_Encode4(196789), |
| 77206 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 77207 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 77208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77211 | GIM_Try, /*On fail goto*//*Label 5213*/ GIMT_Encode4(196740), // Rule ID 53324 // |
| 77212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77213 | // (ssubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 77214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 77215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77220 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77221 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77222 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77226 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77227 | GIR_RootConstrainSelectedInstOperands, |
| 77228 | // GIR_Coverage, 53324, |
| 77229 | GIR_EraseRootFromParent_Done, |
| 77230 | // Label 5213: @196740 |
| 77231 | GIM_Try, /*On fail goto*//*Label 5214*/ GIMT_Encode4(196788), // Rule ID 53325 // |
| 77232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77233 | // (ssubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 77234 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 77235 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77236 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77237 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77240 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77241 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77242 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77246 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77247 | GIR_RootConstrainSelectedInstOperands, |
| 77248 | // GIR_Coverage, 53325, |
| 77249 | GIR_EraseRootFromParent_Done, |
| 77250 | // Label 5214: @196788 |
| 77251 | GIM_Reject, |
| 77252 | // Label 5212: @196789 |
| 77253 | GIM_Reject, |
| 77254 | // Label 5170: @196790 |
| 77255 | GIM_Try, /*On fail goto*//*Label 5215*/ GIMT_Encode4(196910), |
| 77256 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 77257 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 77258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77261 | GIM_Try, /*On fail goto*//*Label 5216*/ GIMT_Encode4(196861), // Rule ID 53340 // |
| 77262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 77263 | // (ssubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 77264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 77265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77270 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77272 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 77275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77276 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77277 | GIR_RootConstrainSelectedInstOperands, |
| 77278 | // GIR_Coverage, 53340, |
| 77279 | GIR_EraseRootFromParent_Done, |
| 77280 | // Label 5216: @196861 |
| 77281 | GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(196909), // Rule ID 53341 // |
| 77282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 77283 | // (ssubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 77284 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 77285 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77286 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77287 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77290 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77291 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77292 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 77295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77296 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77297 | GIR_RootConstrainSelectedInstOperands, |
| 77298 | // GIR_Coverage, 53341, |
| 77299 | GIR_EraseRootFromParent_Done, |
| 77300 | // Label 5217: @196909 |
| 77301 | GIM_Reject, |
| 77302 | // Label 5215: @196910 |
| 77303 | GIM_Reject, |
| 77304 | // Label 5171: @196911 |
| 77305 | GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(197031), |
| 77306 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 77307 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 77308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77309 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 77311 | GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(196982), // Rule ID 53284 // |
| 77312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77313 | // (ssubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 77314 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 77315 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77316 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77317 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 77319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77320 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77321 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77322 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77326 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77327 | GIR_RootConstrainSelectedInstOperands, |
| 77328 | // GIR_Coverage, 53284, |
| 77329 | GIR_EraseRootFromParent_Done, |
| 77330 | // Label 5219: @196982 |
| 77331 | GIM_Try, /*On fail goto*//*Label 5220*/ GIMT_Encode4(197030), // Rule ID 53285 // |
| 77332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77333 | // (ssubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSSUB_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 77334 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 77335 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77336 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M1), |
| 77339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77340 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77341 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77342 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77346 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77347 | GIR_RootConstrainSelectedInstOperands, |
| 77348 | // GIR_Coverage, 53285, |
| 77349 | GIR_EraseRootFromParent_Done, |
| 77350 | // Label 5220: @197030 |
| 77351 | GIM_Reject, |
| 77352 | // Label 5218: @197031 |
| 77353 | GIM_Reject, |
| 77354 | // Label 5172: @197032 |
| 77355 | GIM_Try, /*On fail goto*//*Label 5221*/ GIMT_Encode4(197152), |
| 77356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 77357 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 77358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77361 | GIM_Try, /*On fail goto*//*Label 5222*/ GIMT_Encode4(197103), // Rule ID 53312 // |
| 77362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77363 | // (ssubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 77364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 77365 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77366 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77371 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77372 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77376 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77377 | GIR_RootConstrainSelectedInstOperands, |
| 77378 | // GIR_Coverage, 53312, |
| 77379 | GIR_EraseRootFromParent_Done, |
| 77380 | // Label 5222: @197103 |
| 77381 | GIM_Try, /*On fail goto*//*Label 5223*/ GIMT_Encode4(197151), // Rule ID 53313 // |
| 77382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77383 | // (ssubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 77384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 77385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77390 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77391 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77392 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77396 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77397 | GIR_RootConstrainSelectedInstOperands, |
| 77398 | // GIR_Coverage, 53313, |
| 77399 | GIR_EraseRootFromParent_Done, |
| 77400 | // Label 5223: @197151 |
| 77401 | GIM_Reject, |
| 77402 | // Label 5221: @197152 |
| 77403 | GIM_Reject, |
| 77404 | // Label 5173: @197153 |
| 77405 | GIM_Try, /*On fail goto*//*Label 5224*/ GIMT_Encode4(197273), |
| 77406 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 77407 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 77408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77409 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77410 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77411 | GIM_Try, /*On fail goto*//*Label 5225*/ GIMT_Encode4(197224), // Rule ID 53328 // |
| 77412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77413 | // (ssubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 77414 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 77415 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77416 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77417 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77420 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77421 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77422 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77426 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77427 | GIR_RootConstrainSelectedInstOperands, |
| 77428 | // GIR_Coverage, 53328, |
| 77429 | GIR_EraseRootFromParent_Done, |
| 77430 | // Label 5225: @197224 |
| 77431 | GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(197272), // Rule ID 53329 // |
| 77432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77433 | // (ssubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 77434 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 77435 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77436 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77437 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77440 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77441 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77442 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77446 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77447 | GIR_RootConstrainSelectedInstOperands, |
| 77448 | // GIR_Coverage, 53329, |
| 77449 | GIR_EraseRootFromParent_Done, |
| 77450 | // Label 5226: @197272 |
| 77451 | GIM_Reject, |
| 77452 | // Label 5224: @197273 |
| 77453 | GIM_Reject, |
| 77454 | // Label 5174: @197274 |
| 77455 | GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(197394), |
| 77456 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 77457 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 77458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77459 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77460 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77461 | GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(197345), // Rule ID 53344 // |
| 77462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 77463 | // (ssubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 77464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 77465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77470 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77471 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77472 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 77475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77476 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77477 | GIR_RootConstrainSelectedInstOperands, |
| 77478 | // GIR_Coverage, 53344, |
| 77479 | GIR_EraseRootFromParent_Done, |
| 77480 | // Label 5228: @197345 |
| 77481 | GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(197393), // Rule ID 53345 // |
| 77482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 77483 | // (ssubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 77484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 77485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77490 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77491 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77492 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 77495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77496 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77497 | GIR_RootConstrainSelectedInstOperands, |
| 77498 | // GIR_Coverage, 53345, |
| 77499 | GIR_EraseRootFromParent_Done, |
| 77500 | // Label 5229: @197393 |
| 77501 | GIM_Reject, |
| 77502 | // Label 5227: @197394 |
| 77503 | GIM_Reject, |
| 77504 | // Label 5175: @197395 |
| 77505 | GIM_Try, /*On fail goto*//*Label 5230*/ GIMT_Encode4(197515), |
| 77506 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 77507 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 77508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77509 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77510 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 77511 | GIM_Try, /*On fail goto*//*Label 5231*/ GIMT_Encode4(197466), // Rule ID 53300 // |
| 77512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77513 | // (ssubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 77514 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 77515 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77516 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77517 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77520 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77521 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77522 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77526 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77527 | GIR_RootConstrainSelectedInstOperands, |
| 77528 | // GIR_Coverage, 53300, |
| 77529 | GIR_EraseRootFromParent_Done, |
| 77530 | // Label 5231: @197466 |
| 77531 | GIM_Try, /*On fail goto*//*Label 5232*/ GIMT_Encode4(197514), // Rule ID 53301 // |
| 77532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77533 | // (ssubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSSUB_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 77534 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 77535 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77536 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77537 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M2), |
| 77539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77540 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77541 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77542 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77546 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77547 | GIR_RootConstrainSelectedInstOperands, |
| 77548 | // GIR_Coverage, 53301, |
| 77549 | GIR_EraseRootFromParent_Done, |
| 77550 | // Label 5232: @197514 |
| 77551 | GIM_Reject, |
| 77552 | // Label 5230: @197515 |
| 77553 | GIM_Reject, |
| 77554 | // Label 5176: @197516 |
| 77555 | GIM_Try, /*On fail goto*//*Label 5233*/ GIMT_Encode4(197636), |
| 77556 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 77557 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 77558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77559 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77560 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77561 | GIM_Try, /*On fail goto*//*Label 5234*/ GIMT_Encode4(197587), // Rule ID 53316 // |
| 77562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77563 | // (ssubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 77564 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 77565 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77566 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77570 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77571 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77572 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77576 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77577 | GIR_RootConstrainSelectedInstOperands, |
| 77578 | // GIR_Coverage, 53316, |
| 77579 | GIR_EraseRootFromParent_Done, |
| 77580 | // Label 5234: @197587 |
| 77581 | GIM_Try, /*On fail goto*//*Label 5235*/ GIMT_Encode4(197635), // Rule ID 53317 // |
| 77582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77583 | // (ssubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 77584 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 77585 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77586 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77590 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77591 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77592 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77596 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77597 | GIR_RootConstrainSelectedInstOperands, |
| 77598 | // GIR_Coverage, 53317, |
| 77599 | GIR_EraseRootFromParent_Done, |
| 77600 | // Label 5235: @197635 |
| 77601 | GIM_Reject, |
| 77602 | // Label 5233: @197636 |
| 77603 | GIM_Reject, |
| 77604 | // Label 5177: @197637 |
| 77605 | GIM_Try, /*On fail goto*//*Label 5236*/ GIMT_Encode4(197757), |
| 77606 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 77607 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 77608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77609 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77610 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77611 | GIM_Try, /*On fail goto*//*Label 5237*/ GIMT_Encode4(197708), // Rule ID 53332 // |
| 77612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77613 | // (ssubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 77614 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 77615 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77616 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77621 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77622 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77626 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77627 | GIR_RootConstrainSelectedInstOperands, |
| 77628 | // GIR_Coverage, 53332, |
| 77629 | GIR_EraseRootFromParent_Done, |
| 77630 | // Label 5237: @197708 |
| 77631 | GIM_Try, /*On fail goto*//*Label 5238*/ GIMT_Encode4(197756), // Rule ID 53333 // |
| 77632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77633 | // (ssubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 77634 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 77635 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77636 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77637 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77640 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77641 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77642 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 77645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77646 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77647 | GIR_RootConstrainSelectedInstOperands, |
| 77648 | // GIR_Coverage, 53333, |
| 77649 | GIR_EraseRootFromParent_Done, |
| 77650 | // Label 5238: @197756 |
| 77651 | GIM_Reject, |
| 77652 | // Label 5236: @197757 |
| 77653 | GIM_Reject, |
| 77654 | // Label 5178: @197758 |
| 77655 | GIM_Try, /*On fail goto*//*Label 5239*/ GIMT_Encode4(197878), |
| 77656 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 77657 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 77658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77660 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 77661 | GIM_Try, /*On fail goto*//*Label 5240*/ GIMT_Encode4(197829), // Rule ID 53304 // |
| 77662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77663 | // (ssubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 77664 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 77665 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77666 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77667 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77671 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77672 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77676 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77677 | GIR_RootConstrainSelectedInstOperands, |
| 77678 | // GIR_Coverage, 53304, |
| 77679 | GIR_EraseRootFromParent_Done, |
| 77680 | // Label 5240: @197829 |
| 77681 | GIM_Try, /*On fail goto*//*Label 5241*/ GIMT_Encode4(197877), // Rule ID 53305 // |
| 77682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77683 | // (ssubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSSUB_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 77684 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 77685 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77686 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M4), |
| 77689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77690 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77691 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77692 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77696 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77697 | GIR_RootConstrainSelectedInstOperands, |
| 77698 | // GIR_Coverage, 53305, |
| 77699 | GIR_EraseRootFromParent_Done, |
| 77700 | // Label 5241: @197877 |
| 77701 | GIM_Reject, |
| 77702 | // Label 5239: @197878 |
| 77703 | GIM_Reject, |
| 77704 | // Label 5179: @197879 |
| 77705 | GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(197999), |
| 77706 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 77707 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 77708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77709 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77710 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77711 | GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(197950), // Rule ID 53320 // |
| 77712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77713 | // (ssubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 77714 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 77715 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77716 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77717 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77721 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77722 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77726 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77727 | GIR_RootConstrainSelectedInstOperands, |
| 77728 | // GIR_Coverage, 53320, |
| 77729 | GIR_EraseRootFromParent_Done, |
| 77730 | // Label 5243: @197950 |
| 77731 | GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(197998), // Rule ID 53321 // |
| 77732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77733 | // (ssubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 77734 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 77735 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77736 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77740 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77741 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77742 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 77745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77746 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77747 | GIR_RootConstrainSelectedInstOperands, |
| 77748 | // GIR_Coverage, 53321, |
| 77749 | GIR_EraseRootFromParent_Done, |
| 77750 | // Label 5244: @197998 |
| 77751 | GIM_Reject, |
| 77752 | // Label 5242: @197999 |
| 77753 | GIM_Reject, |
| 77754 | // Label 5180: @198000 |
| 77755 | GIM_Try, /*On fail goto*//*Label 5245*/ GIMT_Encode4(198120), |
| 77756 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 77757 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 77758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 77761 | GIM_Try, /*On fail goto*//*Label 5246*/ GIMT_Encode4(198071), // Rule ID 53308 // |
| 77762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 77763 | // (ssubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 77764 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 77765 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77771 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77772 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77776 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77777 | GIR_RootConstrainSelectedInstOperands, |
| 77778 | // GIR_Coverage, 53308, |
| 77779 | GIR_EraseRootFromParent_Done, |
| 77780 | // Label 5246: @198071 |
| 77781 | GIM_Try, /*On fail goto*//*Label 5247*/ GIMT_Encode4(198119), // Rule ID 53309 // |
| 77782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 77783 | // (ssubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSSUB_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 77784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 77785 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 77786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 77787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 77788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSSUB_VV_M8), |
| 77789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77790 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 77791 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77792 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 77794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 77796 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for RISCV::VXSAT*/0, |
| 77797 | GIR_RootConstrainSelectedInstOperands, |
| 77798 | // GIR_Coverage, 53309, |
| 77799 | GIR_EraseRootFromParent_Done, |
| 77800 | // Label 5247: @198119 |
| 77801 | GIM_Reject, |
| 77802 | // Label 5245: @198120 |
| 77803 | GIM_Reject, |
| 77804 | // Label 5181: @198121 |
| 77805 | GIM_Reject, |
| 77806 | // Label 53: @198122 |
| 77807 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 5266*/ GIMT_Encode4(200549), |
| 77808 | /*GILLT_s16*//*Label 5248*/ GIMT_Encode4(198253), |
| 77809 | /*GILLT_s32*//*Label 5249*/ GIMT_Encode4(198402), |
| 77810 | /*GILLT_s64*//*Label 5250*/ GIMT_Encode4(198551), GIMT_Encode4(0), GIMT_Encode4(0), |
| 77811 | /*GILLT_nxv1s16*//*Label 5251*/ GIMT_Encode4(198734), |
| 77812 | /*GILLT_nxv1s32*//*Label 5252*/ GIMT_Encode4(198855), |
| 77813 | /*GILLT_nxv1s64*//*Label 5253*/ GIMT_Encode4(198976), GIMT_Encode4(0), GIMT_Encode4(0), |
| 77814 | /*GILLT_nxv2s16*//*Label 5254*/ GIMT_Encode4(199097), |
| 77815 | /*GILLT_nxv2s32*//*Label 5255*/ GIMT_Encode4(199218), |
| 77816 | /*GILLT_nxv2s64*//*Label 5256*/ GIMT_Encode4(199339), GIMT_Encode4(0), GIMT_Encode4(0), |
| 77817 | /*GILLT_nxv4s16*//*Label 5257*/ GIMT_Encode4(199460), |
| 77818 | /*GILLT_nxv4s32*//*Label 5258*/ GIMT_Encode4(199581), |
| 77819 | /*GILLT_nxv4s64*//*Label 5259*/ GIMT_Encode4(199702), GIMT_Encode4(0), GIMT_Encode4(0), |
| 77820 | /*GILLT_nxv8s16*//*Label 5260*/ GIMT_Encode4(199823), |
| 77821 | /*GILLT_nxv8s32*//*Label 5261*/ GIMT_Encode4(199944), |
| 77822 | /*GILLT_nxv8s64*//*Label 5262*/ GIMT_Encode4(200065), GIMT_Encode4(0), GIMT_Encode4(0), |
| 77823 | /*GILLT_nxv16s16*//*Label 5263*/ GIMT_Encode4(200186), |
| 77824 | /*GILLT_nxv16s32*//*Label 5264*/ GIMT_Encode4(200307), GIMT_Encode4(0), GIMT_Encode4(0), |
| 77825 | /*GILLT_nxv32s16*//*Label 5265*/ GIMT_Encode4(200428), |
| 77826 | // Label 5248: @198253 |
| 77827 | GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(198401), |
| 77828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 77829 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 77830 | GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(198298), // Rule ID 2012 // |
| 77831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 77832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 77833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 77834 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 77835 | // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 77836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H), |
| 77837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77838 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77839 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77841 | GIR_RootConstrainSelectedInstOperands, |
| 77842 | // GIR_Coverage, 2012, |
| 77843 | GIR_EraseRootFromParent_Done, |
| 77844 | // Label 5268: @198298 |
| 77845 | GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(198332), // Rule ID 2013 // |
| 77846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 77847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 77848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 77849 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 77850 | // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 77851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H), |
| 77852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77853 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77854 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77856 | GIR_RootConstrainSelectedInstOperands, |
| 77857 | // GIR_Coverage, 2013, |
| 77858 | GIR_EraseRootFromParent_Done, |
| 77859 | // Label 5269: @198332 |
| 77860 | GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(198366), // Rule ID 2016 // |
| 77861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 77862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 77863 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 77864 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 77865 | // (fadd:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 77866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H_INX), |
| 77867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77868 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77869 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77871 | GIR_RootConstrainSelectedInstOperands, |
| 77872 | // GIR_Coverage, 2016, |
| 77873 | GIR_EraseRootFromParent_Done, |
| 77874 | // Label 5270: @198366 |
| 77875 | GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(198400), // Rule ID 2017 // |
| 77876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 77877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 77878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 77879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 77880 | // (fadd:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 77881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H_INX), |
| 77882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77883 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77886 | GIR_RootConstrainSelectedInstOperands, |
| 77887 | // GIR_Coverage, 2017, |
| 77888 | GIR_EraseRootFromParent_Done, |
| 77889 | // Label 5271: @198400 |
| 77890 | GIM_Reject, |
| 77891 | // Label 5267: @198401 |
| 77892 | GIM_Reject, |
| 77893 | // Label 5249: @198402 |
| 77894 | GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(198550), |
| 77895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 77896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77897 | GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(198447), // Rule ID 1324 // |
| 77898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 77899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 77900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 77901 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 77902 | // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 77903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S), |
| 77904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77905 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77906 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77908 | GIR_RootConstrainSelectedInstOperands, |
| 77909 | // GIR_Coverage, 1324, |
| 77910 | GIR_EraseRootFromParent_Done, |
| 77911 | // Label 5273: @198447 |
| 77912 | GIM_Try, /*On fail goto*//*Label 5274*/ GIMT_Encode4(198481), // Rule ID 1325 // |
| 77913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 77914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 77915 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 77916 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 77917 | // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 77918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S), |
| 77919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77920 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77921 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77923 | GIR_RootConstrainSelectedInstOperands, |
| 77924 | // GIR_Coverage, 1325, |
| 77925 | GIR_EraseRootFromParent_Done, |
| 77926 | // Label 5274: @198481 |
| 77927 | GIM_Try, /*On fail goto*//*Label 5275*/ GIMT_Encode4(198515), // Rule ID 1328 // |
| 77928 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 77929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 77930 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 77931 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 77932 | // (fadd:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 77933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S_INX), |
| 77934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77935 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77936 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77938 | GIR_RootConstrainSelectedInstOperands, |
| 77939 | // GIR_Coverage, 1328, |
| 77940 | GIR_EraseRootFromParent_Done, |
| 77941 | // Label 5275: @198515 |
| 77942 | GIM_Try, /*On fail goto*//*Label 5276*/ GIMT_Encode4(198549), // Rule ID 1329 // |
| 77943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 77944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 77945 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 77946 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 77947 | // (fadd:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 77948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S_INX), |
| 77949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77950 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77951 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77953 | GIR_RootConstrainSelectedInstOperands, |
| 77954 | // GIR_Coverage, 1329, |
| 77955 | GIR_EraseRootFromParent_Done, |
| 77956 | // Label 5276: @198549 |
| 77957 | GIM_Reject, |
| 77958 | // Label 5272: @198550 |
| 77959 | GIM_Reject, |
| 77960 | // Label 5250: @198551 |
| 77961 | GIM_Try, /*On fail goto*//*Label 5277*/ GIMT_Encode4(198733), |
| 77962 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 77963 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 77964 | GIM_Try, /*On fail goto*//*Label 5278*/ GIMT_Encode4(198596), // Rule ID 1651 // |
| 77965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 77966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 77967 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 77968 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 77969 | // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 77970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D), |
| 77971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77973 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77975 | GIR_RootConstrainSelectedInstOperands, |
| 77976 | // GIR_Coverage, 1651, |
| 77977 | GIR_EraseRootFromParent_Done, |
| 77978 | // Label 5278: @198596 |
| 77979 | GIM_Try, /*On fail goto*//*Label 5279*/ GIMT_Encode4(198630), // Rule ID 1652 // |
| 77980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 77981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 77982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 77983 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 77984 | // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 77985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D), |
| 77986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 77987 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 77988 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 77989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 77990 | GIR_RootConstrainSelectedInstOperands, |
| 77991 | // GIR_Coverage, 1652, |
| 77992 | GIR_EraseRootFromParent_Done, |
| 77993 | // Label 5279: @198630 |
| 77994 | GIM_Try, /*On fail goto*//*Label 5280*/ GIMT_Encode4(198664), // Rule ID 1655 // |
| 77995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 77996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 77997 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 77998 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 77999 | // (fadd:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 78000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D_IN32X), |
| 78001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78002 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78003 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78005 | GIR_RootConstrainSelectedInstOperands, |
| 78006 | // GIR_Coverage, 1655, |
| 78007 | GIR_EraseRootFromParent_Done, |
| 78008 | // Label 5280: @198664 |
| 78009 | GIM_Try, /*On fail goto*//*Label 5281*/ GIMT_Encode4(198698), // Rule ID 1656 // |
| 78010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 78011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 78012 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 78013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 78014 | // (fadd:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 78015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D_IN32X), |
| 78016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78017 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78018 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78020 | GIR_RootConstrainSelectedInstOperands, |
| 78021 | // GIR_Coverage, 1656, |
| 78022 | GIR_EraseRootFromParent_Done, |
| 78023 | // Label 5281: @198698 |
| 78024 | GIM_Try, /*On fail goto*//*Label 5282*/ GIMT_Encode4(198732), // Rule ID 1658 // |
| 78025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 78026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 78027 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 78028 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 78029 | // (fadd:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FADD_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 78030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D_INX), |
| 78031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78032 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78033 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78035 | GIR_RootConstrainSelectedInstOperands, |
| 78036 | // GIR_Coverage, 1658, |
| 78037 | GIR_EraseRootFromParent_Done, |
| 78038 | // Label 5282: @198732 |
| 78039 | GIM_Reject, |
| 78040 | // Label 5277: @198733 |
| 78041 | GIM_Reject, |
| 78042 | // Label 5251: @198734 |
| 78043 | GIM_Try, /*On fail goto*//*Label 5283*/ GIMT_Encode4(198854), |
| 78044 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 78045 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 78046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78047 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78048 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78049 | GIM_Try, /*On fail goto*//*Label 5284*/ GIMT_Encode4(198805), // Rule ID 46592 // |
| 78050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 78051 | // (fadd:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFADD_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 78052 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 78053 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78054 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF4_E16), |
| 78057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78058 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78059 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78060 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78065 | GIR_RootConstrainSelectedInstOperands, |
| 78066 | // GIR_Coverage, 46592, |
| 78067 | GIR_EraseRootFromParent_Done, |
| 78068 | // Label 5284: @198805 |
| 78069 | GIM_Try, /*On fail goto*//*Label 5285*/ GIMT_Encode4(198853), // Rule ID 46593 // |
| 78070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 78071 | // (fadd:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFADD_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 78072 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 78073 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78074 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF4_E16), |
| 78077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78078 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78079 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78080 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78085 | GIR_RootConstrainSelectedInstOperands, |
| 78086 | // GIR_Coverage, 46593, |
| 78087 | GIR_EraseRootFromParent_Done, |
| 78088 | // Label 5285: @198853 |
| 78089 | GIM_Reject, |
| 78090 | // Label 5283: @198854 |
| 78091 | GIM_Reject, |
| 78092 | // Label 5252: @198855 |
| 78093 | GIM_Try, /*On fail goto*//*Label 5286*/ GIMT_Encode4(198975), |
| 78094 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 78095 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 78096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78097 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78098 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78099 | GIM_Try, /*On fail goto*//*Label 5287*/ GIMT_Encode4(198926), // Rule ID 53924 // |
| 78100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 78101 | // (fadd:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFADD_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 78102 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 78103 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78104 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E32), |
| 78107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78108 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78109 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78110 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78115 | GIR_RootConstrainSelectedInstOperands, |
| 78116 | // GIR_Coverage, 53924, |
| 78117 | GIR_EraseRootFromParent_Done, |
| 78118 | // Label 5287: @198926 |
| 78119 | GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(198974), // Rule ID 53925 // |
| 78120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 78121 | // (fadd:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFADD_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 78122 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 78123 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78124 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78125 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E32), |
| 78127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78128 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78129 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78130 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78135 | GIR_RootConstrainSelectedInstOperands, |
| 78136 | // GIR_Coverage, 53925, |
| 78137 | GIR_EraseRootFromParent_Done, |
| 78138 | // Label 5288: @198974 |
| 78139 | GIM_Reject, |
| 78140 | // Label 5286: @198975 |
| 78141 | GIM_Reject, |
| 78142 | // Label 5253: @198976 |
| 78143 | GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(199096), |
| 78144 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 78145 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 78146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78147 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78148 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78149 | GIM_Try, /*On fail goto*//*Label 5290*/ GIMT_Encode4(199047), // Rule ID 53960 // |
| 78150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 78151 | // (fadd:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFADD_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 78152 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 78153 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78154 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E64), |
| 78157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78159 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78160 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78165 | GIR_RootConstrainSelectedInstOperands, |
| 78166 | // GIR_Coverage, 53960, |
| 78167 | GIR_EraseRootFromParent_Done, |
| 78168 | // Label 5290: @199047 |
| 78169 | GIM_Try, /*On fail goto*//*Label 5291*/ GIMT_Encode4(199095), // Rule ID 53961 // |
| 78170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 78171 | // (fadd:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFADD_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 78172 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 78173 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78174 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E64), |
| 78177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78179 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78180 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78185 | GIR_RootConstrainSelectedInstOperands, |
| 78186 | // GIR_Coverage, 53961, |
| 78187 | GIR_EraseRootFromParent_Done, |
| 78188 | // Label 5291: @199095 |
| 78189 | GIM_Reject, |
| 78190 | // Label 5289: @199096 |
| 78191 | GIM_Reject, |
| 78192 | // Label 5254: @199097 |
| 78193 | GIM_Try, /*On fail goto*//*Label 5292*/ GIMT_Encode4(199217), |
| 78194 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 78195 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 78196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78198 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78199 | GIM_Try, /*On fail goto*//*Label 5293*/ GIMT_Encode4(199168), // Rule ID 53912 // |
| 78200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 78201 | // (fadd:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFADD_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 78202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 78203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E16), |
| 78207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78208 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78209 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78210 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78215 | GIR_RootConstrainSelectedInstOperands, |
| 78216 | // GIR_Coverage, 53912, |
| 78217 | GIR_EraseRootFromParent_Done, |
| 78218 | // Label 5293: @199168 |
| 78219 | GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(199216), // Rule ID 53913 // |
| 78220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 78221 | // (fadd:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFADD_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 78222 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 78223 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78224 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78225 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E16), |
| 78227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78228 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78229 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78230 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78235 | GIR_RootConstrainSelectedInstOperands, |
| 78236 | // GIR_Coverage, 53913, |
| 78237 | GIR_EraseRootFromParent_Done, |
| 78238 | // Label 5294: @199216 |
| 78239 | GIM_Reject, |
| 78240 | // Label 5292: @199217 |
| 78241 | GIM_Reject, |
| 78242 | // Label 5255: @199218 |
| 78243 | GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(199338), |
| 78244 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 78245 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 78246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78247 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78248 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78249 | GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(199289), // Rule ID 53948 // |
| 78250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 78251 | // (fadd:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFADD_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 78252 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 78253 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78254 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E32), |
| 78257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78258 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78259 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78260 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78265 | GIR_RootConstrainSelectedInstOperands, |
| 78266 | // GIR_Coverage, 53948, |
| 78267 | GIR_EraseRootFromParent_Done, |
| 78268 | // Label 5296: @199289 |
| 78269 | GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(199337), // Rule ID 53949 // |
| 78270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 78271 | // (fadd:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFADD_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 78272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 78273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E32), |
| 78277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78278 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78279 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78280 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78285 | GIR_RootConstrainSelectedInstOperands, |
| 78286 | // GIR_Coverage, 53949, |
| 78287 | GIR_EraseRootFromParent_Done, |
| 78288 | // Label 5297: @199337 |
| 78289 | GIM_Reject, |
| 78290 | // Label 5295: @199338 |
| 78291 | GIM_Reject, |
| 78292 | // Label 5256: @199339 |
| 78293 | GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(199459), |
| 78294 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 78295 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 78296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78297 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78298 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78299 | GIM_Try, /*On fail goto*//*Label 5299*/ GIMT_Encode4(199410), // Rule ID 54044 // |
| 78300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 78301 | // (fadd:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFADD_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 78302 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 78303 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78304 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E64), |
| 78307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78308 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78309 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78310 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78315 | GIR_RootConstrainSelectedInstOperands, |
| 78316 | // GIR_Coverage, 54044, |
| 78317 | GIR_EraseRootFromParent_Done, |
| 78318 | // Label 5299: @199410 |
| 78319 | GIM_Try, /*On fail goto*//*Label 5300*/ GIMT_Encode4(199458), // Rule ID 54045 // |
| 78320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 78321 | // (fadd:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFADD_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 78322 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 78323 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78324 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78325 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E64), |
| 78327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78328 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78329 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78330 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78335 | GIR_RootConstrainSelectedInstOperands, |
| 78336 | // GIR_Coverage, 54045, |
| 78337 | GIR_EraseRootFromParent_Done, |
| 78338 | // Label 5300: @199458 |
| 78339 | GIM_Reject, |
| 78340 | // Label 5298: @199459 |
| 78341 | GIM_Reject, |
| 78342 | // Label 5257: @199460 |
| 78343 | GIM_Try, /*On fail goto*//*Label 5301*/ GIMT_Encode4(199580), |
| 78344 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 78345 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 78346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78347 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78348 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 78349 | GIM_Try, /*On fail goto*//*Label 5302*/ GIMT_Encode4(199531), // Rule ID 53936 // |
| 78350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 78351 | // (fadd:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFADD_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 78352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 78353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78354 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78355 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E16), |
| 78357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78358 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78359 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78360 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78365 | GIR_RootConstrainSelectedInstOperands, |
| 78366 | // GIR_Coverage, 53936, |
| 78367 | GIR_EraseRootFromParent_Done, |
| 78368 | // Label 5302: @199531 |
| 78369 | GIM_Try, /*On fail goto*//*Label 5303*/ GIMT_Encode4(199579), // Rule ID 53937 // |
| 78370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 78371 | // (fadd:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFADD_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 78372 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 78373 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78374 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E16), |
| 78377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78378 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78379 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78380 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78385 | GIR_RootConstrainSelectedInstOperands, |
| 78386 | // GIR_Coverage, 53937, |
| 78387 | GIR_EraseRootFromParent_Done, |
| 78388 | // Label 5303: @199579 |
| 78389 | GIM_Reject, |
| 78390 | // Label 5301: @199580 |
| 78391 | GIM_Reject, |
| 78392 | // Label 5258: @199581 |
| 78393 | GIM_Try, /*On fail goto*//*Label 5304*/ GIMT_Encode4(199701), |
| 78394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 78395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 78396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78397 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78398 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78399 | GIM_Try, /*On fail goto*//*Label 5305*/ GIMT_Encode4(199652), // Rule ID 54008 // |
| 78400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 78401 | // (fadd:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFADD_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 78402 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 78403 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78404 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E32), |
| 78407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78408 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78409 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78410 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78415 | GIR_RootConstrainSelectedInstOperands, |
| 78416 | // GIR_Coverage, 54008, |
| 78417 | GIR_EraseRootFromParent_Done, |
| 78418 | // Label 5305: @199652 |
| 78419 | GIM_Try, /*On fail goto*//*Label 5306*/ GIMT_Encode4(199700), // Rule ID 54009 // |
| 78420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 78421 | // (fadd:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFADD_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 78422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 78423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E32), |
| 78427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78428 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78429 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78430 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78435 | GIR_RootConstrainSelectedInstOperands, |
| 78436 | // GIR_Coverage, 54009, |
| 78437 | GIR_EraseRootFromParent_Done, |
| 78438 | // Label 5306: @199700 |
| 78439 | GIM_Reject, |
| 78440 | // Label 5304: @199701 |
| 78441 | GIM_Reject, |
| 78442 | // Label 5259: @199702 |
| 78443 | GIM_Try, /*On fail goto*//*Label 5307*/ GIMT_Encode4(199822), |
| 78444 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 78445 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 78446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78447 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78448 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78449 | GIM_Try, /*On fail goto*//*Label 5308*/ GIMT_Encode4(199773), // Rule ID 54056 // |
| 78450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 78451 | // (fadd:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFADD_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 78452 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 78453 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78454 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E64), |
| 78457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78458 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78459 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78460 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78465 | GIR_RootConstrainSelectedInstOperands, |
| 78466 | // GIR_Coverage, 54056, |
| 78467 | GIR_EraseRootFromParent_Done, |
| 78468 | // Label 5308: @199773 |
| 78469 | GIM_Try, /*On fail goto*//*Label 5309*/ GIMT_Encode4(199821), // Rule ID 54057 // |
| 78470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 78471 | // (fadd:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFADD_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 78472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 78473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E64), |
| 78477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78479 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78480 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78485 | GIR_RootConstrainSelectedInstOperands, |
| 78486 | // GIR_Coverage, 54057, |
| 78487 | GIR_EraseRootFromParent_Done, |
| 78488 | // Label 5309: @199821 |
| 78489 | GIM_Reject, |
| 78490 | // Label 5307: @199822 |
| 78491 | GIM_Reject, |
| 78492 | // Label 5260: @199823 |
| 78493 | GIM_Try, /*On fail goto*//*Label 5310*/ GIMT_Encode4(199943), |
| 78494 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 78495 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 78496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78497 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78498 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 78499 | GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(199894), // Rule ID 53972 // |
| 78500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 78501 | // (fadd:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFADD_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 78502 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 78503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78504 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E16), |
| 78507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78508 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78509 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78510 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78515 | GIR_RootConstrainSelectedInstOperands, |
| 78516 | // GIR_Coverage, 53972, |
| 78517 | GIR_EraseRootFromParent_Done, |
| 78518 | // Label 5311: @199894 |
| 78519 | GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(199942), // Rule ID 53973 // |
| 78520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 78521 | // (fadd:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFADD_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 78522 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 78523 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78524 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78525 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E16), |
| 78527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78528 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78529 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78530 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78535 | GIR_RootConstrainSelectedInstOperands, |
| 78536 | // GIR_Coverage, 53973, |
| 78537 | GIR_EraseRootFromParent_Done, |
| 78538 | // Label 5312: @199942 |
| 78539 | GIM_Reject, |
| 78540 | // Label 5310: @199943 |
| 78541 | GIM_Reject, |
| 78542 | // Label 5261: @199944 |
| 78543 | GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(200064), |
| 78544 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 78545 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 78546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78547 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78548 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78549 | GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(200015), // Rule ID 54020 // |
| 78550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 78551 | // (fadd:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFADD_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 78552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 78553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78554 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E32), |
| 78557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78558 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78559 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78560 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78565 | GIR_RootConstrainSelectedInstOperands, |
| 78566 | // GIR_Coverage, 54020, |
| 78567 | GIR_EraseRootFromParent_Done, |
| 78568 | // Label 5314: @200015 |
| 78569 | GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(200063), // Rule ID 54021 // |
| 78570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 78571 | // (fadd:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFADD_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 78572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 78573 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78574 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E32), |
| 78577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78578 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78579 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78580 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78585 | GIR_RootConstrainSelectedInstOperands, |
| 78586 | // GIR_Coverage, 54021, |
| 78587 | GIR_EraseRootFromParent_Done, |
| 78588 | // Label 5315: @200063 |
| 78589 | GIM_Reject, |
| 78590 | // Label 5313: @200064 |
| 78591 | GIM_Reject, |
| 78592 | // Label 5262: @200065 |
| 78593 | GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(200185), |
| 78594 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 78595 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 78596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78597 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78598 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78599 | GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(200136), // Rule ID 54068 // |
| 78600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 78601 | // (fadd:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFADD_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 78602 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 78603 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78604 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E64), |
| 78607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78608 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78609 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78610 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78615 | GIR_RootConstrainSelectedInstOperands, |
| 78616 | // GIR_Coverage, 54068, |
| 78617 | GIR_EraseRootFromParent_Done, |
| 78618 | // Label 5317: @200136 |
| 78619 | GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(200184), // Rule ID 54069 // |
| 78620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 78621 | // (fadd:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFADD_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 78622 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 78623 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78624 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E64), |
| 78627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78629 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78630 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 78634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78635 | GIR_RootConstrainSelectedInstOperands, |
| 78636 | // GIR_Coverage, 54069, |
| 78637 | GIR_EraseRootFromParent_Done, |
| 78638 | // Label 5318: @200184 |
| 78639 | GIM_Reject, |
| 78640 | // Label 5316: @200185 |
| 78641 | GIM_Reject, |
| 78642 | // Label 5263: @200186 |
| 78643 | GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(200306), |
| 78644 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 78645 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 78646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78647 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78648 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 78649 | GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(200257), // Rule ID 53984 // |
| 78650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 78651 | // (fadd:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFADD_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 78652 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 78653 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78654 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E16), |
| 78657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78658 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78659 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78660 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78665 | GIR_RootConstrainSelectedInstOperands, |
| 78666 | // GIR_Coverage, 53984, |
| 78667 | GIR_EraseRootFromParent_Done, |
| 78668 | // Label 5320: @200257 |
| 78669 | GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(200305), // Rule ID 53985 // |
| 78670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 78671 | // (fadd:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFADD_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 78672 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 78673 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78674 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E16), |
| 78677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78679 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78680 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78685 | GIR_RootConstrainSelectedInstOperands, |
| 78686 | // GIR_Coverage, 53985, |
| 78687 | GIR_EraseRootFromParent_Done, |
| 78688 | // Label 5321: @200305 |
| 78689 | GIM_Reject, |
| 78690 | // Label 5319: @200306 |
| 78691 | GIM_Reject, |
| 78692 | // Label 5264: @200307 |
| 78693 | GIM_Try, /*On fail goto*//*Label 5322*/ GIMT_Encode4(200427), |
| 78694 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 78695 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 78696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78697 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78698 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78699 | GIM_Try, /*On fail goto*//*Label 5323*/ GIMT_Encode4(200378), // Rule ID 54032 // |
| 78700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 78701 | // (fadd:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFADD_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 78702 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 78703 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78704 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78705 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E32), |
| 78707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78708 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78709 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78710 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78715 | GIR_RootConstrainSelectedInstOperands, |
| 78716 | // GIR_Coverage, 54032, |
| 78717 | GIR_EraseRootFromParent_Done, |
| 78718 | // Label 5323: @200378 |
| 78719 | GIM_Try, /*On fail goto*//*Label 5324*/ GIMT_Encode4(200426), // Rule ID 54033 // |
| 78720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 78721 | // (fadd:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFADD_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 78722 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 78723 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78724 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78725 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E32), |
| 78727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78728 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78729 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78730 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 78734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78735 | GIR_RootConstrainSelectedInstOperands, |
| 78736 | // GIR_Coverage, 54033, |
| 78737 | GIR_EraseRootFromParent_Done, |
| 78738 | // Label 5324: @200426 |
| 78739 | GIM_Reject, |
| 78740 | // Label 5322: @200427 |
| 78741 | GIM_Reject, |
| 78742 | // Label 5265: @200428 |
| 78743 | GIM_Try, /*On fail goto*//*Label 5325*/ GIMT_Encode4(200548), |
| 78744 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 78745 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 78746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78747 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78748 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 78749 | GIM_Try, /*On fail goto*//*Label 5326*/ GIMT_Encode4(200499), // Rule ID 53996 // |
| 78750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 78751 | // (fadd:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFADD_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 78752 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 78753 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78754 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E16), |
| 78757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78758 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78759 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78760 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78765 | GIR_RootConstrainSelectedInstOperands, |
| 78766 | // GIR_Coverage, 53996, |
| 78767 | GIR_EraseRootFromParent_Done, |
| 78768 | // Label 5326: @200499 |
| 78769 | GIM_Try, /*On fail goto*//*Label 5327*/ GIMT_Encode4(200547), // Rule ID 53997 // |
| 78770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 78771 | // (fadd:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFADD_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 78772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 78773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 78774 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 78775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 78776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E16), |
| 78777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78778 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 78779 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78780 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 78783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 78784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 78785 | GIR_RootConstrainSelectedInstOperands, |
| 78786 | // GIR_Coverage, 53997, |
| 78787 | GIR_EraseRootFromParent_Done, |
| 78788 | // Label 5327: @200547 |
| 78789 | GIM_Reject, |
| 78790 | // Label 5325: @200548 |
| 78791 | GIM_Reject, |
| 78792 | // Label 5266: @200549 |
| 78793 | GIM_Reject, |
| 78794 | // Label 54: @200550 |
| 78795 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 5346*/ GIMT_Encode4(202977), |
| 78796 | /*GILLT_s16*//*Label 5328*/ GIMT_Encode4(200681), |
| 78797 | /*GILLT_s32*//*Label 5329*/ GIMT_Encode4(200830), |
| 78798 | /*GILLT_s64*//*Label 5330*/ GIMT_Encode4(200979), GIMT_Encode4(0), GIMT_Encode4(0), |
| 78799 | /*GILLT_nxv1s16*//*Label 5331*/ GIMT_Encode4(201162), |
| 78800 | /*GILLT_nxv1s32*//*Label 5332*/ GIMT_Encode4(201283), |
| 78801 | /*GILLT_nxv1s64*//*Label 5333*/ GIMT_Encode4(201404), GIMT_Encode4(0), GIMT_Encode4(0), |
| 78802 | /*GILLT_nxv2s16*//*Label 5334*/ GIMT_Encode4(201525), |
| 78803 | /*GILLT_nxv2s32*//*Label 5335*/ GIMT_Encode4(201646), |
| 78804 | /*GILLT_nxv2s64*//*Label 5336*/ GIMT_Encode4(201767), GIMT_Encode4(0), GIMT_Encode4(0), |
| 78805 | /*GILLT_nxv4s16*//*Label 5337*/ GIMT_Encode4(201888), |
| 78806 | /*GILLT_nxv4s32*//*Label 5338*/ GIMT_Encode4(202009), |
| 78807 | /*GILLT_nxv4s64*//*Label 5339*/ GIMT_Encode4(202130), GIMT_Encode4(0), GIMT_Encode4(0), |
| 78808 | /*GILLT_nxv8s16*//*Label 5340*/ GIMT_Encode4(202251), |
| 78809 | /*GILLT_nxv8s32*//*Label 5341*/ GIMT_Encode4(202372), |
| 78810 | /*GILLT_nxv8s64*//*Label 5342*/ GIMT_Encode4(202493), GIMT_Encode4(0), GIMT_Encode4(0), |
| 78811 | /*GILLT_nxv16s16*//*Label 5343*/ GIMT_Encode4(202614), |
| 78812 | /*GILLT_nxv16s32*//*Label 5344*/ GIMT_Encode4(202735), GIMT_Encode4(0), GIMT_Encode4(0), |
| 78813 | /*GILLT_nxv32s16*//*Label 5345*/ GIMT_Encode4(202856), |
| 78814 | // Label 5328: @200681 |
| 78815 | GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(200829), |
| 78816 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 78817 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 78818 | GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(200726), // Rule ID 2020 // |
| 78819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 78820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 78821 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 78822 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 78823 | // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSUB_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 78824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H), |
| 78825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78826 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78827 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78829 | GIR_RootConstrainSelectedInstOperands, |
| 78830 | // GIR_Coverage, 2020, |
| 78831 | GIR_EraseRootFromParent_Done, |
| 78832 | // Label 5348: @200726 |
| 78833 | GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(200760), // Rule ID 2021 // |
| 78834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 78835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 78836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 78837 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 78838 | // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSUB_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 78839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H), |
| 78840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78841 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78842 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78844 | GIR_RootConstrainSelectedInstOperands, |
| 78845 | // GIR_Coverage, 2021, |
| 78846 | GIR_EraseRootFromParent_Done, |
| 78847 | // Label 5349: @200760 |
| 78848 | GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(200794), // Rule ID 2024 // |
| 78849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 78850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 78851 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 78852 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 78853 | // (fsub:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSUB_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 78854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H_INX), |
| 78855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78856 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78857 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78859 | GIR_RootConstrainSelectedInstOperands, |
| 78860 | // GIR_Coverage, 2024, |
| 78861 | GIR_EraseRootFromParent_Done, |
| 78862 | // Label 5350: @200794 |
| 78863 | GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(200828), // Rule ID 2025 // |
| 78864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 78865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 78866 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 78867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 78868 | // (fsub:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSUB_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 78869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H_INX), |
| 78870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78871 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78874 | GIR_RootConstrainSelectedInstOperands, |
| 78875 | // GIR_Coverage, 2025, |
| 78876 | GIR_EraseRootFromParent_Done, |
| 78877 | // Label 5351: @200828 |
| 78878 | GIM_Reject, |
| 78879 | // Label 5347: @200829 |
| 78880 | GIM_Reject, |
| 78881 | // Label 5329: @200830 |
| 78882 | GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(200978), |
| 78883 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 78884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 78885 | GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(200875), // Rule ID 1332 // |
| 78886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 78887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 78888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 78889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 78890 | // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 78891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S), |
| 78892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78893 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78894 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78896 | GIR_RootConstrainSelectedInstOperands, |
| 78897 | // GIR_Coverage, 1332, |
| 78898 | GIR_EraseRootFromParent_Done, |
| 78899 | // Label 5353: @200875 |
| 78900 | GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(200909), // Rule ID 1333 // |
| 78901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 78902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 78903 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 78904 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 78905 | // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 78906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S), |
| 78907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78909 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78911 | GIR_RootConstrainSelectedInstOperands, |
| 78912 | // GIR_Coverage, 1333, |
| 78913 | GIR_EraseRootFromParent_Done, |
| 78914 | // Label 5354: @200909 |
| 78915 | GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(200943), // Rule ID 1336 // |
| 78916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 78917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 78918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 78919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 78920 | // (fsub:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSUB_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 78921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S_INX), |
| 78922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78923 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78924 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78926 | GIR_RootConstrainSelectedInstOperands, |
| 78927 | // GIR_Coverage, 1336, |
| 78928 | GIR_EraseRootFromParent_Done, |
| 78929 | // Label 5355: @200943 |
| 78930 | GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(200977), // Rule ID 1337 // |
| 78931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 78932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 78933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 78934 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 78935 | // (fsub:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSUB_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 78936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S_INX), |
| 78937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78938 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78939 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78941 | GIR_RootConstrainSelectedInstOperands, |
| 78942 | // GIR_Coverage, 1337, |
| 78943 | GIR_EraseRootFromParent_Done, |
| 78944 | // Label 5356: @200977 |
| 78945 | GIM_Reject, |
| 78946 | // Label 5352: @200978 |
| 78947 | GIM_Reject, |
| 78948 | // Label 5330: @200979 |
| 78949 | GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(201161), |
| 78950 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 78951 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78952 | GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(201024), // Rule ID 1661 // |
| 78953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 78954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 78955 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 78956 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 78957 | // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 78958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D), |
| 78959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78960 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78961 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78963 | GIR_RootConstrainSelectedInstOperands, |
| 78964 | // GIR_Coverage, 1661, |
| 78965 | GIR_EraseRootFromParent_Done, |
| 78966 | // Label 5358: @201024 |
| 78967 | GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(201058), // Rule ID 1662 // |
| 78968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 78969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 78970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 78971 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 78972 | // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 78973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D), |
| 78974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78975 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78976 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78978 | GIR_RootConstrainSelectedInstOperands, |
| 78979 | // GIR_Coverage, 1662, |
| 78980 | GIR_EraseRootFromParent_Done, |
| 78981 | // Label 5359: @201058 |
| 78982 | GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(201092), // Rule ID 1665 // |
| 78983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 78984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 78985 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 78986 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 78987 | // (fsub:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSUB_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 78988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D_IN32X), |
| 78989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 78990 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 78991 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 78992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 78993 | GIR_RootConstrainSelectedInstOperands, |
| 78994 | // GIR_Coverage, 1665, |
| 78995 | GIR_EraseRootFromParent_Done, |
| 78996 | // Label 5360: @201092 |
| 78997 | GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(201126), // Rule ID 1666 // |
| 78998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 78999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79000 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79001 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79002 | // (fsub:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSUB_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 79003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D_IN32X), |
| 79004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79006 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79008 | GIR_RootConstrainSelectedInstOperands, |
| 79009 | // GIR_Coverage, 1666, |
| 79010 | GIR_EraseRootFromParent_Done, |
| 79011 | // Label 5361: @201126 |
| 79012 | GIM_Try, /*On fail goto*//*Label 5362*/ GIMT_Encode4(201160), // Rule ID 1668 // |
| 79013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 79014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 79015 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 79016 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 79017 | // (fsub:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FSUB_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 79018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D_INX), |
| 79019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79020 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79021 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79023 | GIR_RootConstrainSelectedInstOperands, |
| 79024 | // GIR_Coverage, 1668, |
| 79025 | GIR_EraseRootFromParent_Done, |
| 79026 | // Label 5362: @201160 |
| 79027 | GIM_Reject, |
| 79028 | // Label 5357: @201161 |
| 79029 | GIM_Reject, |
| 79030 | // Label 5331: @201162 |
| 79031 | GIM_Try, /*On fail goto*//*Label 5363*/ GIMT_Encode4(201282), |
| 79032 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 79033 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 79034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79036 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79037 | GIM_Try, /*On fail goto*//*Label 5364*/ GIMT_Encode4(201233), // Rule ID 54080 // |
| 79038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 79039 | // (fsub:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSUB_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 79040 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 79041 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79042 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF4_E16), |
| 79045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79046 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79047 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79053 | GIR_RootConstrainSelectedInstOperands, |
| 79054 | // GIR_Coverage, 54080, |
| 79055 | GIR_EraseRootFromParent_Done, |
| 79056 | // Label 5364: @201233 |
| 79057 | GIM_Try, /*On fail goto*//*Label 5365*/ GIMT_Encode4(201281), // Rule ID 54081 // |
| 79058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 79059 | // (fsub:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSUB_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 79060 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 79061 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79062 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF4_E16), |
| 79065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79066 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79067 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79068 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79073 | GIR_RootConstrainSelectedInstOperands, |
| 79074 | // GIR_Coverage, 54081, |
| 79075 | GIR_EraseRootFromParent_Done, |
| 79076 | // Label 5365: @201281 |
| 79077 | GIM_Reject, |
| 79078 | // Label 5363: @201282 |
| 79079 | GIM_Reject, |
| 79080 | // Label 5332: @201283 |
| 79081 | GIM_Try, /*On fail goto*//*Label 5366*/ GIMT_Encode4(201403), |
| 79082 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 79083 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 79084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79085 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79086 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79087 | GIM_Try, /*On fail goto*//*Label 5367*/ GIMT_Encode4(201354), // Rule ID 54104 // |
| 79088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 79089 | // (fsub:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSUB_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 79090 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 79091 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79092 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79093 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E32), |
| 79095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79096 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79097 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79098 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79103 | GIR_RootConstrainSelectedInstOperands, |
| 79104 | // GIR_Coverage, 54104, |
| 79105 | GIR_EraseRootFromParent_Done, |
| 79106 | // Label 5367: @201354 |
| 79107 | GIM_Try, /*On fail goto*//*Label 5368*/ GIMT_Encode4(201402), // Rule ID 54105 // |
| 79108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 79109 | // (fsub:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSUB_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 79110 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 79111 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79112 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79113 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E32), |
| 79115 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79116 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79117 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79118 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79123 | GIR_RootConstrainSelectedInstOperands, |
| 79124 | // GIR_Coverage, 54105, |
| 79125 | GIR_EraseRootFromParent_Done, |
| 79126 | // Label 5368: @201402 |
| 79127 | GIM_Reject, |
| 79128 | // Label 5366: @201403 |
| 79129 | GIM_Reject, |
| 79130 | // Label 5333: @201404 |
| 79131 | GIM_Try, /*On fail goto*//*Label 5369*/ GIMT_Encode4(201524), |
| 79132 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 79133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 79134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79136 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79137 | GIM_Try, /*On fail goto*//*Label 5370*/ GIMT_Encode4(201475), // Rule ID 54140 // |
| 79138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 79139 | // (fsub:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSUB_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 79140 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 79141 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79142 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E64), |
| 79145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79146 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79147 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79148 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79153 | GIR_RootConstrainSelectedInstOperands, |
| 79154 | // GIR_Coverage, 54140, |
| 79155 | GIR_EraseRootFromParent_Done, |
| 79156 | // Label 5370: @201475 |
| 79157 | GIM_Try, /*On fail goto*//*Label 5371*/ GIMT_Encode4(201523), // Rule ID 54141 // |
| 79158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 79159 | // (fsub:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSUB_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 79160 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 79161 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79162 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E64), |
| 79165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79166 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79167 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79168 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79173 | GIR_RootConstrainSelectedInstOperands, |
| 79174 | // GIR_Coverage, 54141, |
| 79175 | GIR_EraseRootFromParent_Done, |
| 79176 | // Label 5371: @201523 |
| 79177 | GIM_Reject, |
| 79178 | // Label 5369: @201524 |
| 79179 | GIM_Reject, |
| 79180 | // Label 5334: @201525 |
| 79181 | GIM_Try, /*On fail goto*//*Label 5372*/ GIMT_Encode4(201645), |
| 79182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 79183 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 79184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79185 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79186 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79187 | GIM_Try, /*On fail goto*//*Label 5373*/ GIMT_Encode4(201596), // Rule ID 54092 // |
| 79188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 79189 | // (fsub:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSUB_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 79190 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 79191 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79192 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E16), |
| 79195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79196 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79197 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79198 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79203 | GIR_RootConstrainSelectedInstOperands, |
| 79204 | // GIR_Coverage, 54092, |
| 79205 | GIR_EraseRootFromParent_Done, |
| 79206 | // Label 5373: @201596 |
| 79207 | GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(201644), // Rule ID 54093 // |
| 79208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 79209 | // (fsub:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSUB_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 79210 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 79211 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79212 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E16), |
| 79215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79216 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79217 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79218 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79223 | GIR_RootConstrainSelectedInstOperands, |
| 79224 | // GIR_Coverage, 54093, |
| 79225 | GIR_EraseRootFromParent_Done, |
| 79226 | // Label 5374: @201644 |
| 79227 | GIM_Reject, |
| 79228 | // Label 5372: @201645 |
| 79229 | GIM_Reject, |
| 79230 | // Label 5335: @201646 |
| 79231 | GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(201766), |
| 79232 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 79233 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 79234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79235 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79236 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79237 | GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(201717), // Rule ID 54128 // |
| 79238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 79239 | // (fsub:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSUB_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 79240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 79241 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79242 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E32), |
| 79245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79247 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79248 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79253 | GIR_RootConstrainSelectedInstOperands, |
| 79254 | // GIR_Coverage, 54128, |
| 79255 | GIR_EraseRootFromParent_Done, |
| 79256 | // Label 5376: @201717 |
| 79257 | GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(201765), // Rule ID 54129 // |
| 79258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 79259 | // (fsub:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSUB_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 79260 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 79261 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79262 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E32), |
| 79265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79266 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79267 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79268 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79273 | GIR_RootConstrainSelectedInstOperands, |
| 79274 | // GIR_Coverage, 54129, |
| 79275 | GIR_EraseRootFromParent_Done, |
| 79276 | // Label 5377: @201765 |
| 79277 | GIM_Reject, |
| 79278 | // Label 5375: @201766 |
| 79279 | GIM_Reject, |
| 79280 | // Label 5336: @201767 |
| 79281 | GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(201887), |
| 79282 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 79283 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 79284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79285 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79286 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79287 | GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(201838), // Rule ID 54224 // |
| 79288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 79289 | // (fsub:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSUB_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 79290 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 79291 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79292 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E64), |
| 79295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79296 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79297 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79298 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79303 | GIR_RootConstrainSelectedInstOperands, |
| 79304 | // GIR_Coverage, 54224, |
| 79305 | GIR_EraseRootFromParent_Done, |
| 79306 | // Label 5379: @201838 |
| 79307 | GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(201886), // Rule ID 54225 // |
| 79308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 79309 | // (fsub:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSUB_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 79310 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 79311 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79312 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E64), |
| 79315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79316 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79317 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79318 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79323 | GIR_RootConstrainSelectedInstOperands, |
| 79324 | // GIR_Coverage, 54225, |
| 79325 | GIR_EraseRootFromParent_Done, |
| 79326 | // Label 5380: @201886 |
| 79327 | GIM_Reject, |
| 79328 | // Label 5378: @201887 |
| 79329 | GIM_Reject, |
| 79330 | // Label 5337: @201888 |
| 79331 | GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(202008), |
| 79332 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 79333 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 79334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79335 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79336 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 79337 | GIM_Try, /*On fail goto*//*Label 5382*/ GIMT_Encode4(201959), // Rule ID 54116 // |
| 79338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 79339 | // (fsub:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSUB_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 79340 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 79341 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79342 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E16), |
| 79345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79346 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79347 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79348 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79353 | GIR_RootConstrainSelectedInstOperands, |
| 79354 | // GIR_Coverage, 54116, |
| 79355 | GIR_EraseRootFromParent_Done, |
| 79356 | // Label 5382: @201959 |
| 79357 | GIM_Try, /*On fail goto*//*Label 5383*/ GIMT_Encode4(202007), // Rule ID 54117 // |
| 79358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 79359 | // (fsub:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSUB_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 79360 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 79361 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79362 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79363 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E16), |
| 79365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79366 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79367 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79368 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79373 | GIR_RootConstrainSelectedInstOperands, |
| 79374 | // GIR_Coverage, 54117, |
| 79375 | GIR_EraseRootFromParent_Done, |
| 79376 | // Label 5383: @202007 |
| 79377 | GIM_Reject, |
| 79378 | // Label 5381: @202008 |
| 79379 | GIM_Reject, |
| 79380 | // Label 5338: @202009 |
| 79381 | GIM_Try, /*On fail goto*//*Label 5384*/ GIMT_Encode4(202129), |
| 79382 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 79383 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 79384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79385 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79386 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79387 | GIM_Try, /*On fail goto*//*Label 5385*/ GIMT_Encode4(202080), // Rule ID 54188 // |
| 79388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 79389 | // (fsub:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSUB_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 79390 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 79391 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79392 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E32), |
| 79395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79396 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79397 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79398 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79403 | GIR_RootConstrainSelectedInstOperands, |
| 79404 | // GIR_Coverage, 54188, |
| 79405 | GIR_EraseRootFromParent_Done, |
| 79406 | // Label 5385: @202080 |
| 79407 | GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(202128), // Rule ID 54189 // |
| 79408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 79409 | // (fsub:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSUB_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 79410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 79411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E32), |
| 79415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79416 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79417 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79418 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79423 | GIR_RootConstrainSelectedInstOperands, |
| 79424 | // GIR_Coverage, 54189, |
| 79425 | GIR_EraseRootFromParent_Done, |
| 79426 | // Label 5386: @202128 |
| 79427 | GIM_Reject, |
| 79428 | // Label 5384: @202129 |
| 79429 | GIM_Reject, |
| 79430 | // Label 5339: @202130 |
| 79431 | GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(202250), |
| 79432 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 79433 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 79434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79435 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79436 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79437 | GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(202201), // Rule ID 54236 // |
| 79438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 79439 | // (fsub:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSUB_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 79440 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 79441 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79442 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79443 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E64), |
| 79445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79446 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79447 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79448 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79453 | GIR_RootConstrainSelectedInstOperands, |
| 79454 | // GIR_Coverage, 54236, |
| 79455 | GIR_EraseRootFromParent_Done, |
| 79456 | // Label 5388: @202201 |
| 79457 | GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(202249), // Rule ID 54237 // |
| 79458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 79459 | // (fsub:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSUB_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 79460 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 79461 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79462 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E64), |
| 79465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79466 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79467 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79468 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79473 | GIR_RootConstrainSelectedInstOperands, |
| 79474 | // GIR_Coverage, 54237, |
| 79475 | GIR_EraseRootFromParent_Done, |
| 79476 | // Label 5389: @202249 |
| 79477 | GIM_Reject, |
| 79478 | // Label 5387: @202250 |
| 79479 | GIM_Reject, |
| 79480 | // Label 5340: @202251 |
| 79481 | GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(202371), |
| 79482 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 79483 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 79484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79486 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 79487 | GIM_Try, /*On fail goto*//*Label 5391*/ GIMT_Encode4(202322), // Rule ID 54152 // |
| 79488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 79489 | // (fsub:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSUB_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 79490 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 79491 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79492 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79493 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E16), |
| 79495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79496 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79497 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79498 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79503 | GIR_RootConstrainSelectedInstOperands, |
| 79504 | // GIR_Coverage, 54152, |
| 79505 | GIR_EraseRootFromParent_Done, |
| 79506 | // Label 5391: @202322 |
| 79507 | GIM_Try, /*On fail goto*//*Label 5392*/ GIMT_Encode4(202370), // Rule ID 54153 // |
| 79508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 79509 | // (fsub:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSUB_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 79510 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 79511 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79512 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79513 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E16), |
| 79515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79516 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79517 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79518 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79523 | GIR_RootConstrainSelectedInstOperands, |
| 79524 | // GIR_Coverage, 54153, |
| 79525 | GIR_EraseRootFromParent_Done, |
| 79526 | // Label 5392: @202370 |
| 79527 | GIM_Reject, |
| 79528 | // Label 5390: @202371 |
| 79529 | GIM_Reject, |
| 79530 | // Label 5341: @202372 |
| 79531 | GIM_Try, /*On fail goto*//*Label 5393*/ GIMT_Encode4(202492), |
| 79532 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 79533 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 79534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79535 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79536 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79537 | GIM_Try, /*On fail goto*//*Label 5394*/ GIMT_Encode4(202443), // Rule ID 54200 // |
| 79538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 79539 | // (fsub:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSUB_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 79540 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 79541 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79542 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E32), |
| 79545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79546 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79547 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79548 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79553 | GIR_RootConstrainSelectedInstOperands, |
| 79554 | // GIR_Coverage, 54200, |
| 79555 | GIR_EraseRootFromParent_Done, |
| 79556 | // Label 5394: @202443 |
| 79557 | GIM_Try, /*On fail goto*//*Label 5395*/ GIMT_Encode4(202491), // Rule ID 54201 // |
| 79558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 79559 | // (fsub:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSUB_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 79560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 79561 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79562 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E32), |
| 79565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79566 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79567 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79568 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79573 | GIR_RootConstrainSelectedInstOperands, |
| 79574 | // GIR_Coverage, 54201, |
| 79575 | GIR_EraseRootFromParent_Done, |
| 79576 | // Label 5395: @202491 |
| 79577 | GIM_Reject, |
| 79578 | // Label 5393: @202492 |
| 79579 | GIM_Reject, |
| 79580 | // Label 5342: @202493 |
| 79581 | GIM_Try, /*On fail goto*//*Label 5396*/ GIMT_Encode4(202613), |
| 79582 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 79583 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 79584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79586 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79587 | GIM_Try, /*On fail goto*//*Label 5397*/ GIMT_Encode4(202564), // Rule ID 54248 // |
| 79588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 79589 | // (fsub:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSUB_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 79590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 79591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E64), |
| 79595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79597 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79598 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79603 | GIR_RootConstrainSelectedInstOperands, |
| 79604 | // GIR_Coverage, 54248, |
| 79605 | GIR_EraseRootFromParent_Done, |
| 79606 | // Label 5397: @202564 |
| 79607 | GIM_Try, /*On fail goto*//*Label 5398*/ GIMT_Encode4(202612), // Rule ID 54249 // |
| 79608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 79609 | // (fsub:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSUB_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 79610 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 79611 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79612 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79613 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E64), |
| 79615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79617 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79618 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 79622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79623 | GIR_RootConstrainSelectedInstOperands, |
| 79624 | // GIR_Coverage, 54249, |
| 79625 | GIR_EraseRootFromParent_Done, |
| 79626 | // Label 5398: @202612 |
| 79627 | GIM_Reject, |
| 79628 | // Label 5396: @202613 |
| 79629 | GIM_Reject, |
| 79630 | // Label 5343: @202614 |
| 79631 | GIM_Try, /*On fail goto*//*Label 5399*/ GIMT_Encode4(202734), |
| 79632 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 79633 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 79634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79635 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79636 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 79637 | GIM_Try, /*On fail goto*//*Label 5400*/ GIMT_Encode4(202685), // Rule ID 54164 // |
| 79638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 79639 | // (fsub:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSUB_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 79640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 79641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E16), |
| 79645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79647 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79648 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79653 | GIR_RootConstrainSelectedInstOperands, |
| 79654 | // GIR_Coverage, 54164, |
| 79655 | GIR_EraseRootFromParent_Done, |
| 79656 | // Label 5400: @202685 |
| 79657 | GIM_Try, /*On fail goto*//*Label 5401*/ GIMT_Encode4(202733), // Rule ID 54165 // |
| 79658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 79659 | // (fsub:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSUB_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 79660 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 79661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E16), |
| 79665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79666 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79667 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79668 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79673 | GIR_RootConstrainSelectedInstOperands, |
| 79674 | // GIR_Coverage, 54165, |
| 79675 | GIR_EraseRootFromParent_Done, |
| 79676 | // Label 5401: @202733 |
| 79677 | GIM_Reject, |
| 79678 | // Label 5399: @202734 |
| 79679 | GIM_Reject, |
| 79680 | // Label 5344: @202735 |
| 79681 | GIM_Try, /*On fail goto*//*Label 5402*/ GIMT_Encode4(202855), |
| 79682 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 79683 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 79684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79686 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79687 | GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(202806), // Rule ID 54212 // |
| 79688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 79689 | // (fsub:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSUB_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 79690 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 79691 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79692 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79693 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E32), |
| 79695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79696 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79697 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79698 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79703 | GIR_RootConstrainSelectedInstOperands, |
| 79704 | // GIR_Coverage, 54212, |
| 79705 | GIR_EraseRootFromParent_Done, |
| 79706 | // Label 5403: @202806 |
| 79707 | GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(202854), // Rule ID 54213 // |
| 79708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 79709 | // (fsub:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSUB_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 79710 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 79711 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E32), |
| 79715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79716 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79717 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79718 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 79722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79723 | GIR_RootConstrainSelectedInstOperands, |
| 79724 | // GIR_Coverage, 54213, |
| 79725 | GIR_EraseRootFromParent_Done, |
| 79726 | // Label 5404: @202854 |
| 79727 | GIM_Reject, |
| 79728 | // Label 5402: @202855 |
| 79729 | GIM_Reject, |
| 79730 | // Label 5345: @202856 |
| 79731 | GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(202976), |
| 79732 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 79733 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 79734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79735 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79736 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 79737 | GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(202927), // Rule ID 54176 // |
| 79738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 79739 | // (fsub:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSUB_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 79740 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 79741 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79742 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E16), |
| 79745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79746 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79747 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79748 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79753 | GIR_RootConstrainSelectedInstOperands, |
| 79754 | // GIR_Coverage, 54176, |
| 79755 | GIR_EraseRootFromParent_Done, |
| 79756 | // Label 5406: @202927 |
| 79757 | GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(202975), // Rule ID 54177 // |
| 79758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 79759 | // (fsub:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSUB_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 79760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 79761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 79762 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 79763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 79764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E16), |
| 79765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 79767 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79768 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 79771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 79772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 79773 | GIR_RootConstrainSelectedInstOperands, |
| 79774 | // GIR_Coverage, 54177, |
| 79775 | GIR_EraseRootFromParent_Done, |
| 79776 | // Label 5407: @202975 |
| 79777 | GIM_Reject, |
| 79778 | // Label 5405: @202976 |
| 79779 | GIM_Reject, |
| 79780 | // Label 5346: @202977 |
| 79781 | GIM_Reject, |
| 79782 | // Label 55: @202978 |
| 79783 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 5426*/ GIMT_Encode4(205405), |
| 79784 | /*GILLT_s16*//*Label 5408*/ GIMT_Encode4(203109), |
| 79785 | /*GILLT_s32*//*Label 5409*/ GIMT_Encode4(203258), |
| 79786 | /*GILLT_s64*//*Label 5410*/ GIMT_Encode4(203407), GIMT_Encode4(0), GIMT_Encode4(0), |
| 79787 | /*GILLT_nxv1s16*//*Label 5411*/ GIMT_Encode4(203590), |
| 79788 | /*GILLT_nxv1s32*//*Label 5412*/ GIMT_Encode4(203711), |
| 79789 | /*GILLT_nxv1s64*//*Label 5413*/ GIMT_Encode4(203832), GIMT_Encode4(0), GIMT_Encode4(0), |
| 79790 | /*GILLT_nxv2s16*//*Label 5414*/ GIMT_Encode4(203953), |
| 79791 | /*GILLT_nxv2s32*//*Label 5415*/ GIMT_Encode4(204074), |
| 79792 | /*GILLT_nxv2s64*//*Label 5416*/ GIMT_Encode4(204195), GIMT_Encode4(0), GIMT_Encode4(0), |
| 79793 | /*GILLT_nxv4s16*//*Label 5417*/ GIMT_Encode4(204316), |
| 79794 | /*GILLT_nxv4s32*//*Label 5418*/ GIMT_Encode4(204437), |
| 79795 | /*GILLT_nxv4s64*//*Label 5419*/ GIMT_Encode4(204558), GIMT_Encode4(0), GIMT_Encode4(0), |
| 79796 | /*GILLT_nxv8s16*//*Label 5420*/ GIMT_Encode4(204679), |
| 79797 | /*GILLT_nxv8s32*//*Label 5421*/ GIMT_Encode4(204800), |
| 79798 | /*GILLT_nxv8s64*//*Label 5422*/ GIMT_Encode4(204921), GIMT_Encode4(0), GIMT_Encode4(0), |
| 79799 | /*GILLT_nxv16s16*//*Label 5423*/ GIMT_Encode4(205042), |
| 79800 | /*GILLT_nxv16s32*//*Label 5424*/ GIMT_Encode4(205163), GIMT_Encode4(0), GIMT_Encode4(0), |
| 79801 | /*GILLT_nxv32s16*//*Label 5425*/ GIMT_Encode4(205284), |
| 79802 | // Label 5408: @203109 |
| 79803 | GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(203257), |
| 79804 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 79805 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 79806 | GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(203154), // Rule ID 2028 // |
| 79807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 79808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 79809 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 79810 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 79811 | // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMUL_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 79812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H), |
| 79813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79815 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79817 | GIR_RootConstrainSelectedInstOperands, |
| 79818 | // GIR_Coverage, 2028, |
| 79819 | GIR_EraseRootFromParent_Done, |
| 79820 | // Label 5428: @203154 |
| 79821 | GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(203188), // Rule ID 2029 // |
| 79822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 79823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 79824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 79825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 79826 | // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMUL_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 79827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H), |
| 79828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79829 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79830 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79832 | GIR_RootConstrainSelectedInstOperands, |
| 79833 | // GIR_Coverage, 2029, |
| 79834 | GIR_EraseRootFromParent_Done, |
| 79835 | // Label 5429: @203188 |
| 79836 | GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(203222), // Rule ID 2032 // |
| 79837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 79838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 79839 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 79840 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 79841 | // (fmul:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FMUL_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 79842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H_INX), |
| 79843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79844 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79845 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79847 | GIR_RootConstrainSelectedInstOperands, |
| 79848 | // GIR_Coverage, 2032, |
| 79849 | GIR_EraseRootFromParent_Done, |
| 79850 | // Label 5430: @203222 |
| 79851 | GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(203256), // Rule ID 2033 // |
| 79852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 79853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 79854 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 79855 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 79856 | // (fmul:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FMUL_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 79857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H_INX), |
| 79858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79859 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79860 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79862 | GIR_RootConstrainSelectedInstOperands, |
| 79863 | // GIR_Coverage, 2033, |
| 79864 | GIR_EraseRootFromParent_Done, |
| 79865 | // Label 5431: @203256 |
| 79866 | GIM_Reject, |
| 79867 | // Label 5427: @203257 |
| 79868 | GIM_Reject, |
| 79869 | // Label 5409: @203258 |
| 79870 | GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(203406), |
| 79871 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 79872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 79873 | GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(203303), // Rule ID 1340 // |
| 79874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 79875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 79876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 79877 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 79878 | // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 79879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S), |
| 79880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79881 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79882 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79884 | GIR_RootConstrainSelectedInstOperands, |
| 79885 | // GIR_Coverage, 1340, |
| 79886 | GIR_EraseRootFromParent_Done, |
| 79887 | // Label 5433: @203303 |
| 79888 | GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(203337), // Rule ID 1341 // |
| 79889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 79890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 79891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 79892 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 79893 | // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 79894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S), |
| 79895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79896 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79897 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79899 | GIR_RootConstrainSelectedInstOperands, |
| 79900 | // GIR_Coverage, 1341, |
| 79901 | GIR_EraseRootFromParent_Done, |
| 79902 | // Label 5434: @203337 |
| 79903 | GIM_Try, /*On fail goto*//*Label 5435*/ GIMT_Encode4(203371), // Rule ID 1344 // |
| 79904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 79905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 79906 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 79907 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 79908 | // (fmul:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FMUL_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 79909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S_INX), |
| 79910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79911 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79912 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79914 | GIR_RootConstrainSelectedInstOperands, |
| 79915 | // GIR_Coverage, 1344, |
| 79916 | GIR_EraseRootFromParent_Done, |
| 79917 | // Label 5435: @203371 |
| 79918 | GIM_Try, /*On fail goto*//*Label 5436*/ GIMT_Encode4(203405), // Rule ID 1345 // |
| 79919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 79920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 79921 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 79922 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 79923 | // (fmul:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FMUL_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 79924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S_INX), |
| 79925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79926 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79927 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79929 | GIR_RootConstrainSelectedInstOperands, |
| 79930 | // GIR_Coverage, 1345, |
| 79931 | GIR_EraseRootFromParent_Done, |
| 79932 | // Label 5436: @203405 |
| 79933 | GIM_Reject, |
| 79934 | // Label 5432: @203406 |
| 79935 | GIM_Reject, |
| 79936 | // Label 5410: @203407 |
| 79937 | GIM_Try, /*On fail goto*//*Label 5437*/ GIMT_Encode4(203589), |
| 79938 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 79939 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 79940 | GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(203452), // Rule ID 1671 // |
| 79941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 79942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 79943 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 79944 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 79945 | // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 79946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D), |
| 79947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79948 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79949 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79951 | GIR_RootConstrainSelectedInstOperands, |
| 79952 | // GIR_Coverage, 1671, |
| 79953 | GIR_EraseRootFromParent_Done, |
| 79954 | // Label 5438: @203452 |
| 79955 | GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(203486), // Rule ID 1672 // |
| 79956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 79957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 79958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 79959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 79960 | // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 79961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D), |
| 79962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79963 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79964 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79966 | GIR_RootConstrainSelectedInstOperands, |
| 79967 | // GIR_Coverage, 1672, |
| 79968 | GIR_EraseRootFromParent_Done, |
| 79969 | // Label 5439: @203486 |
| 79970 | GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(203520), // Rule ID 1675 // |
| 79971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 79972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79973 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79974 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79975 | // (fmul:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FMUL_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 79976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D_IN32X), |
| 79977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79978 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79979 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79981 | GIR_RootConstrainSelectedInstOperands, |
| 79982 | // GIR_Coverage, 1675, |
| 79983 | GIR_EraseRootFromParent_Done, |
| 79984 | // Label 5440: @203520 |
| 79985 | GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(203554), // Rule ID 1676 // |
| 79986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 79987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79988 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79989 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 79990 | // (fmul:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FMUL_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 79991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D_IN32X), |
| 79992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 79993 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 79994 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 79995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 79996 | GIR_RootConstrainSelectedInstOperands, |
| 79997 | // GIR_Coverage, 1676, |
| 79998 | GIR_EraseRootFromParent_Done, |
| 79999 | // Label 5441: @203554 |
| 80000 | GIM_Try, /*On fail goto*//*Label 5442*/ GIMT_Encode4(203588), // Rule ID 1678 // |
| 80001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 80002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 80003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 80004 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 80005 | // (fmul:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FMUL_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 80006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D_INX), |
| 80007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80008 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80009 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80011 | GIR_RootConstrainSelectedInstOperands, |
| 80012 | // GIR_Coverage, 1678, |
| 80013 | GIR_EraseRootFromParent_Done, |
| 80014 | // Label 5442: @203588 |
| 80015 | GIM_Reject, |
| 80016 | // Label 5437: @203589 |
| 80017 | GIM_Reject, |
| 80018 | // Label 5411: @203590 |
| 80019 | GIM_Try, /*On fail goto*//*Label 5443*/ GIMT_Encode4(203710), |
| 80020 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 80021 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 80022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80023 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80024 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80025 | GIM_Try, /*On fail goto*//*Label 5444*/ GIMT_Encode4(203661), // Rule ID 54848 // |
| 80026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 80027 | // (fmul:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMUL_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 80028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 80029 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80030 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF4_E16), |
| 80033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80034 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80035 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80036 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80041 | GIR_RootConstrainSelectedInstOperands, |
| 80042 | // GIR_Coverage, 54848, |
| 80043 | GIR_EraseRootFromParent_Done, |
| 80044 | // Label 5444: @203661 |
| 80045 | GIM_Try, /*On fail goto*//*Label 5445*/ GIMT_Encode4(203709), // Rule ID 54849 // |
| 80046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 80047 | // (fmul:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMUL_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 80048 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 80049 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80050 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF4_E16), |
| 80053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80054 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80055 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80056 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80061 | GIR_RootConstrainSelectedInstOperands, |
| 80062 | // GIR_Coverage, 54849, |
| 80063 | GIR_EraseRootFromParent_Done, |
| 80064 | // Label 5445: @203709 |
| 80065 | GIM_Reject, |
| 80066 | // Label 5443: @203710 |
| 80067 | GIM_Reject, |
| 80068 | // Label 5412: @203711 |
| 80069 | GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(203831), |
| 80070 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 80071 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 80072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80073 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80074 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80075 | GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(203782), // Rule ID 54872 // |
| 80076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 80077 | // (fmul:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMUL_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 80078 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 80079 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80080 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E32), |
| 80083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80084 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80085 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80086 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80091 | GIR_RootConstrainSelectedInstOperands, |
| 80092 | // GIR_Coverage, 54872, |
| 80093 | GIR_EraseRootFromParent_Done, |
| 80094 | // Label 5447: @203782 |
| 80095 | GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(203830), // Rule ID 54873 // |
| 80096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 80097 | // (fmul:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMUL_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 80098 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 80099 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80100 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E32), |
| 80103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80104 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80105 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80106 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80111 | GIR_RootConstrainSelectedInstOperands, |
| 80112 | // GIR_Coverage, 54873, |
| 80113 | GIR_EraseRootFromParent_Done, |
| 80114 | // Label 5448: @203830 |
| 80115 | GIM_Reject, |
| 80116 | // Label 5446: @203831 |
| 80117 | GIM_Reject, |
| 80118 | // Label 5413: @203832 |
| 80119 | GIM_Try, /*On fail goto*//*Label 5449*/ GIMT_Encode4(203952), |
| 80120 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 80121 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 80122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80124 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80125 | GIM_Try, /*On fail goto*//*Label 5450*/ GIMT_Encode4(203903), // Rule ID 54908 // |
| 80126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 80127 | // (fmul:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMUL_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 80128 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 80129 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80130 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E64), |
| 80133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80134 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80135 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80136 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80141 | GIR_RootConstrainSelectedInstOperands, |
| 80142 | // GIR_Coverage, 54908, |
| 80143 | GIR_EraseRootFromParent_Done, |
| 80144 | // Label 5450: @203903 |
| 80145 | GIM_Try, /*On fail goto*//*Label 5451*/ GIMT_Encode4(203951), // Rule ID 54909 // |
| 80146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 80147 | // (fmul:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMUL_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 80148 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 80149 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80150 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E64), |
| 80153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80154 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80156 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80161 | GIR_RootConstrainSelectedInstOperands, |
| 80162 | // GIR_Coverage, 54909, |
| 80163 | GIR_EraseRootFromParent_Done, |
| 80164 | // Label 5451: @203951 |
| 80165 | GIM_Reject, |
| 80166 | // Label 5449: @203952 |
| 80167 | GIM_Reject, |
| 80168 | // Label 5414: @203953 |
| 80169 | GIM_Try, /*On fail goto*//*Label 5452*/ GIMT_Encode4(204073), |
| 80170 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 80171 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 80172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80174 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80175 | GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(204024), // Rule ID 54860 // |
| 80176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 80177 | // (fmul:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMUL_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 80178 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 80179 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80180 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E16), |
| 80183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80184 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80185 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80186 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80191 | GIR_RootConstrainSelectedInstOperands, |
| 80192 | // GIR_Coverage, 54860, |
| 80193 | GIR_EraseRootFromParent_Done, |
| 80194 | // Label 5453: @204024 |
| 80195 | GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(204072), // Rule ID 54861 // |
| 80196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 80197 | // (fmul:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMUL_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 80198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 80199 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80200 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E16), |
| 80203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80204 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80205 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80206 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80211 | GIR_RootConstrainSelectedInstOperands, |
| 80212 | // GIR_Coverage, 54861, |
| 80213 | GIR_EraseRootFromParent_Done, |
| 80214 | // Label 5454: @204072 |
| 80215 | GIM_Reject, |
| 80216 | // Label 5452: @204073 |
| 80217 | GIM_Reject, |
| 80218 | // Label 5415: @204074 |
| 80219 | GIM_Try, /*On fail goto*//*Label 5455*/ GIMT_Encode4(204194), |
| 80220 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 80221 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 80222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80223 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80224 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80225 | GIM_Try, /*On fail goto*//*Label 5456*/ GIMT_Encode4(204145), // Rule ID 54896 // |
| 80226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 80227 | // (fmul:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMUL_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 80228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 80229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80230 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E32), |
| 80233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80234 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80235 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80236 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80241 | GIR_RootConstrainSelectedInstOperands, |
| 80242 | // GIR_Coverage, 54896, |
| 80243 | GIR_EraseRootFromParent_Done, |
| 80244 | // Label 5456: @204145 |
| 80245 | GIM_Try, /*On fail goto*//*Label 5457*/ GIMT_Encode4(204193), // Rule ID 54897 // |
| 80246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 80247 | // (fmul:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMUL_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 80248 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 80249 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80250 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80251 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E32), |
| 80253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80254 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80255 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80256 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80261 | GIR_RootConstrainSelectedInstOperands, |
| 80262 | // GIR_Coverage, 54897, |
| 80263 | GIR_EraseRootFromParent_Done, |
| 80264 | // Label 5457: @204193 |
| 80265 | GIM_Reject, |
| 80266 | // Label 5455: @204194 |
| 80267 | GIM_Reject, |
| 80268 | // Label 5416: @204195 |
| 80269 | GIM_Try, /*On fail goto*//*Label 5458*/ GIMT_Encode4(204315), |
| 80270 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 80271 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 80272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80274 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80275 | GIM_Try, /*On fail goto*//*Label 5459*/ GIMT_Encode4(204266), // Rule ID 54992 // |
| 80276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 80277 | // (fmul:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMUL_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 80278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 80279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E64), |
| 80283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80286 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80291 | GIR_RootConstrainSelectedInstOperands, |
| 80292 | // GIR_Coverage, 54992, |
| 80293 | GIR_EraseRootFromParent_Done, |
| 80294 | // Label 5459: @204266 |
| 80295 | GIM_Try, /*On fail goto*//*Label 5460*/ GIMT_Encode4(204314), // Rule ID 54993 // |
| 80296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 80297 | // (fmul:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMUL_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 80298 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 80299 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80300 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E64), |
| 80303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80304 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80305 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80306 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80311 | GIR_RootConstrainSelectedInstOperands, |
| 80312 | // GIR_Coverage, 54993, |
| 80313 | GIR_EraseRootFromParent_Done, |
| 80314 | // Label 5460: @204314 |
| 80315 | GIM_Reject, |
| 80316 | // Label 5458: @204315 |
| 80317 | GIM_Reject, |
| 80318 | // Label 5417: @204316 |
| 80319 | GIM_Try, /*On fail goto*//*Label 5461*/ GIMT_Encode4(204436), |
| 80320 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 80321 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 80322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80323 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80324 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 80325 | GIM_Try, /*On fail goto*//*Label 5462*/ GIMT_Encode4(204387), // Rule ID 54884 // |
| 80326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 80327 | // (fmul:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMUL_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 80328 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 80329 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80330 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E16), |
| 80333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80334 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80335 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80336 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80341 | GIR_RootConstrainSelectedInstOperands, |
| 80342 | // GIR_Coverage, 54884, |
| 80343 | GIR_EraseRootFromParent_Done, |
| 80344 | // Label 5462: @204387 |
| 80345 | GIM_Try, /*On fail goto*//*Label 5463*/ GIMT_Encode4(204435), // Rule ID 54885 // |
| 80346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 80347 | // (fmul:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMUL_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 80348 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 80349 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80350 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E16), |
| 80353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80354 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80355 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80356 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80361 | GIR_RootConstrainSelectedInstOperands, |
| 80362 | // GIR_Coverage, 54885, |
| 80363 | GIR_EraseRootFromParent_Done, |
| 80364 | // Label 5463: @204435 |
| 80365 | GIM_Reject, |
| 80366 | // Label 5461: @204436 |
| 80367 | GIM_Reject, |
| 80368 | // Label 5418: @204437 |
| 80369 | GIM_Try, /*On fail goto*//*Label 5464*/ GIMT_Encode4(204557), |
| 80370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 80371 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 80372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80373 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80374 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80375 | GIM_Try, /*On fail goto*//*Label 5465*/ GIMT_Encode4(204508), // Rule ID 54956 // |
| 80376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 80377 | // (fmul:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMUL_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 80378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 80379 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80380 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80381 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E32), |
| 80383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80384 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80385 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80386 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80391 | GIR_RootConstrainSelectedInstOperands, |
| 80392 | // GIR_Coverage, 54956, |
| 80393 | GIR_EraseRootFromParent_Done, |
| 80394 | // Label 5465: @204508 |
| 80395 | GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(204556), // Rule ID 54957 // |
| 80396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 80397 | // (fmul:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMUL_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 80398 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 80399 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80400 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E32), |
| 80403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80404 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80405 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80406 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80411 | GIR_RootConstrainSelectedInstOperands, |
| 80412 | // GIR_Coverage, 54957, |
| 80413 | GIR_EraseRootFromParent_Done, |
| 80414 | // Label 5466: @204556 |
| 80415 | GIM_Reject, |
| 80416 | // Label 5464: @204557 |
| 80417 | GIM_Reject, |
| 80418 | // Label 5419: @204558 |
| 80419 | GIM_Try, /*On fail goto*//*Label 5467*/ GIMT_Encode4(204678), |
| 80420 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 80421 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 80422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80423 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80424 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80425 | GIM_Try, /*On fail goto*//*Label 5468*/ GIMT_Encode4(204629), // Rule ID 55004 // |
| 80426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 80427 | // (fmul:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMUL_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 80428 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 80429 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80430 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E64), |
| 80433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80434 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80435 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80436 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80441 | GIR_RootConstrainSelectedInstOperands, |
| 80442 | // GIR_Coverage, 55004, |
| 80443 | GIR_EraseRootFromParent_Done, |
| 80444 | // Label 5468: @204629 |
| 80445 | GIM_Try, /*On fail goto*//*Label 5469*/ GIMT_Encode4(204677), // Rule ID 55005 // |
| 80446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 80447 | // (fmul:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMUL_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 80448 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 80449 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80450 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E64), |
| 80453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80454 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80455 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80456 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80461 | GIR_RootConstrainSelectedInstOperands, |
| 80462 | // GIR_Coverage, 55005, |
| 80463 | GIR_EraseRootFromParent_Done, |
| 80464 | // Label 5469: @204677 |
| 80465 | GIM_Reject, |
| 80466 | // Label 5467: @204678 |
| 80467 | GIM_Reject, |
| 80468 | // Label 5420: @204679 |
| 80469 | GIM_Try, /*On fail goto*//*Label 5470*/ GIMT_Encode4(204799), |
| 80470 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 80471 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 80472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80474 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 80475 | GIM_Try, /*On fail goto*//*Label 5471*/ GIMT_Encode4(204750), // Rule ID 54920 // |
| 80476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 80477 | // (fmul:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMUL_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 80478 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 80479 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80480 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E16), |
| 80483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80484 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80485 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80486 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80491 | GIR_RootConstrainSelectedInstOperands, |
| 80492 | // GIR_Coverage, 54920, |
| 80493 | GIR_EraseRootFromParent_Done, |
| 80494 | // Label 5471: @204750 |
| 80495 | GIM_Try, /*On fail goto*//*Label 5472*/ GIMT_Encode4(204798), // Rule ID 54921 // |
| 80496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 80497 | // (fmul:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMUL_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 80498 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 80499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E16), |
| 80503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80504 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80505 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80506 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80511 | GIR_RootConstrainSelectedInstOperands, |
| 80512 | // GIR_Coverage, 54921, |
| 80513 | GIR_EraseRootFromParent_Done, |
| 80514 | // Label 5472: @204798 |
| 80515 | GIM_Reject, |
| 80516 | // Label 5470: @204799 |
| 80517 | GIM_Reject, |
| 80518 | // Label 5421: @204800 |
| 80519 | GIM_Try, /*On fail goto*//*Label 5473*/ GIMT_Encode4(204920), |
| 80520 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 80521 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 80522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80523 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80524 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80525 | GIM_Try, /*On fail goto*//*Label 5474*/ GIMT_Encode4(204871), // Rule ID 54968 // |
| 80526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 80527 | // (fmul:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMUL_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 80528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 80529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E32), |
| 80533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80534 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80535 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80536 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80541 | GIR_RootConstrainSelectedInstOperands, |
| 80542 | // GIR_Coverage, 54968, |
| 80543 | GIR_EraseRootFromParent_Done, |
| 80544 | // Label 5474: @204871 |
| 80545 | GIM_Try, /*On fail goto*//*Label 5475*/ GIMT_Encode4(204919), // Rule ID 54969 // |
| 80546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 80547 | // (fmul:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMUL_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 80548 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 80549 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80550 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E32), |
| 80553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80555 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80556 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80561 | GIR_RootConstrainSelectedInstOperands, |
| 80562 | // GIR_Coverage, 54969, |
| 80563 | GIR_EraseRootFromParent_Done, |
| 80564 | // Label 5475: @204919 |
| 80565 | GIM_Reject, |
| 80566 | // Label 5473: @204920 |
| 80567 | GIM_Reject, |
| 80568 | // Label 5422: @204921 |
| 80569 | GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(205041), |
| 80570 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 80571 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 80572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80574 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80575 | GIM_Try, /*On fail goto*//*Label 5477*/ GIMT_Encode4(204992), // Rule ID 55016 // |
| 80576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 80577 | // (fmul:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMUL_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 80578 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 80579 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80580 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E64), |
| 80583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80585 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80586 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80591 | GIR_RootConstrainSelectedInstOperands, |
| 80592 | // GIR_Coverage, 55016, |
| 80593 | GIR_EraseRootFromParent_Done, |
| 80594 | // Label 5477: @204992 |
| 80595 | GIM_Try, /*On fail goto*//*Label 5478*/ GIMT_Encode4(205040), // Rule ID 55017 // |
| 80596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 80597 | // (fmul:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMUL_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 80598 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 80599 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80600 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E64), |
| 80603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80604 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80605 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80606 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 80610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80611 | GIR_RootConstrainSelectedInstOperands, |
| 80612 | // GIR_Coverage, 55017, |
| 80613 | GIR_EraseRootFromParent_Done, |
| 80614 | // Label 5478: @205040 |
| 80615 | GIM_Reject, |
| 80616 | // Label 5476: @205041 |
| 80617 | GIM_Reject, |
| 80618 | // Label 5423: @205042 |
| 80619 | GIM_Try, /*On fail goto*//*Label 5479*/ GIMT_Encode4(205162), |
| 80620 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 80621 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 80622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80624 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 80625 | GIM_Try, /*On fail goto*//*Label 5480*/ GIMT_Encode4(205113), // Rule ID 54932 // |
| 80626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 80627 | // (fmul:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMUL_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 80628 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 80629 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80630 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E16), |
| 80633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80634 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80635 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80636 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80641 | GIR_RootConstrainSelectedInstOperands, |
| 80642 | // GIR_Coverage, 54932, |
| 80643 | GIR_EraseRootFromParent_Done, |
| 80644 | // Label 5480: @205113 |
| 80645 | GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(205161), // Rule ID 54933 // |
| 80646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 80647 | // (fmul:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMUL_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 80648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 80649 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E16), |
| 80653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80654 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80655 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80656 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80661 | GIR_RootConstrainSelectedInstOperands, |
| 80662 | // GIR_Coverage, 54933, |
| 80663 | GIR_EraseRootFromParent_Done, |
| 80664 | // Label 5481: @205161 |
| 80665 | GIM_Reject, |
| 80666 | // Label 5479: @205162 |
| 80667 | GIM_Reject, |
| 80668 | // Label 5424: @205163 |
| 80669 | GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(205283), |
| 80670 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 80671 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 80672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80673 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80674 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80675 | GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(205234), // Rule ID 54980 // |
| 80676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 80677 | // (fmul:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMUL_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 80678 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 80679 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80680 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80681 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E32), |
| 80683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80684 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80685 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80686 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80691 | GIR_RootConstrainSelectedInstOperands, |
| 80692 | // GIR_Coverage, 54980, |
| 80693 | GIR_EraseRootFromParent_Done, |
| 80694 | // Label 5483: @205234 |
| 80695 | GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(205282), // Rule ID 54981 // |
| 80696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 80697 | // (fmul:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMUL_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 80698 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 80699 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80700 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80701 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E32), |
| 80703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80704 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80705 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80706 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 80710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80711 | GIR_RootConstrainSelectedInstOperands, |
| 80712 | // GIR_Coverage, 54981, |
| 80713 | GIR_EraseRootFromParent_Done, |
| 80714 | // Label 5484: @205282 |
| 80715 | GIM_Reject, |
| 80716 | // Label 5482: @205283 |
| 80717 | GIM_Reject, |
| 80718 | // Label 5425: @205284 |
| 80719 | GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(205404), |
| 80720 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 80721 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 80722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80723 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80724 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 80725 | GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(205355), // Rule ID 54944 // |
| 80726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 80727 | // (fmul:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMUL_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 80728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 80729 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80730 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E16), |
| 80733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80734 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80735 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80736 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80741 | GIR_RootConstrainSelectedInstOperands, |
| 80742 | // GIR_Coverage, 54944, |
| 80743 | GIR_EraseRootFromParent_Done, |
| 80744 | // Label 5486: @205355 |
| 80745 | GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(205403), // Rule ID 54945 // |
| 80746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 80747 | // (fmul:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMUL_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 80748 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 80749 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80750 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E16), |
| 80753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80754 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80755 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 80756 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 80760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 80761 | GIR_RootConstrainSelectedInstOperands, |
| 80762 | // GIR_Coverage, 54945, |
| 80763 | GIR_EraseRootFromParent_Done, |
| 80764 | // Label 5487: @205403 |
| 80765 | GIM_Reject, |
| 80766 | // Label 5485: @205404 |
| 80767 | GIM_Reject, |
| 80768 | // Label 5426: @205405 |
| 80769 | GIM_Reject, |
| 80770 | // Label 56: @205406 |
| 80771 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 5506*/ GIMT_Encode4(222050), |
| 80772 | /*GILLT_s16*//*Label 5488*/ GIMT_Encode4(205537), |
| 80773 | /*GILLT_s32*//*Label 5489*/ GIMT_Encode4(206973), |
| 80774 | /*GILLT_s64*//*Label 5490*/ GIMT_Encode4(208409), GIMT_Encode4(0), GIMT_Encode4(0), |
| 80775 | /*GILLT_nxv1s16*//*Label 5491*/ GIMT_Encode4(210200), |
| 80776 | /*GILLT_nxv1s32*//*Label 5492*/ GIMT_Encode4(210990), |
| 80777 | /*GILLT_nxv1s64*//*Label 5493*/ GIMT_Encode4(211780), GIMT_Encode4(0), GIMT_Encode4(0), |
| 80778 | /*GILLT_nxv2s16*//*Label 5494*/ GIMT_Encode4(212570), |
| 80779 | /*GILLT_nxv2s32*//*Label 5495*/ GIMT_Encode4(213360), |
| 80780 | /*GILLT_nxv2s64*//*Label 5496*/ GIMT_Encode4(214150), GIMT_Encode4(0), GIMT_Encode4(0), |
| 80781 | /*GILLT_nxv4s16*//*Label 5497*/ GIMT_Encode4(214940), |
| 80782 | /*GILLT_nxv4s32*//*Label 5498*/ GIMT_Encode4(215730), |
| 80783 | /*GILLT_nxv4s64*//*Label 5499*/ GIMT_Encode4(216520), GIMT_Encode4(0), GIMT_Encode4(0), |
| 80784 | /*GILLT_nxv8s16*//*Label 5500*/ GIMT_Encode4(217310), |
| 80785 | /*GILLT_nxv8s32*//*Label 5501*/ GIMT_Encode4(218100), |
| 80786 | /*GILLT_nxv8s64*//*Label 5502*/ GIMT_Encode4(218890), GIMT_Encode4(0), GIMT_Encode4(0), |
| 80787 | /*GILLT_nxv16s16*//*Label 5503*/ GIMT_Encode4(219680), |
| 80788 | /*GILLT_nxv16s32*//*Label 5504*/ GIMT_Encode4(220470), GIMT_Encode4(0), GIMT_Encode4(0), |
| 80789 | /*GILLT_nxv32s16*//*Label 5505*/ GIMT_Encode4(221260), |
| 80790 | // Label 5488: @205537 |
| 80791 | GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(206972), |
| 80792 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80793 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 80794 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 80795 | GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(205623), // Rule ID 2068 // |
| 80796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 80797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80801 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80802 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80803 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80804 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80805 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80806 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80807 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80808 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 80809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 80810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80812 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80815 | GIR_RootConstrainSelectedInstOperands, |
| 80816 | // GIR_Coverage, 2068, |
| 80817 | GIR_EraseRootFromParent_Done, |
| 80818 | // Label 5508: @205623 |
| 80819 | GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(205695), // Rule ID 2069 // |
| 80820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 80821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80822 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80823 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80824 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80825 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80826 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80827 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80828 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80829 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80830 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80831 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80832 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 80833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 80834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80836 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80839 | GIR_RootConstrainSelectedInstOperands, |
| 80840 | // GIR_Coverage, 2069, |
| 80841 | GIR_EraseRootFromParent_Done, |
| 80842 | // Label 5509: @205695 |
| 80843 | GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(205767), // Rule ID 2100 // |
| 80844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 80845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80846 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80847 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80848 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80849 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80850 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80851 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80852 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80853 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80854 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80855 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80856 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 80857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 80858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80860 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80863 | GIR_RootConstrainSelectedInstOperands, |
| 80864 | // GIR_Coverage, 2100, |
| 80865 | GIR_EraseRootFromParent_Done, |
| 80866 | // Label 5510: @205767 |
| 80867 | GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(205839), // Rule ID 2101 // |
| 80868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 80869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80870 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80871 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80872 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80873 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80875 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80876 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80877 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80878 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80879 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80880 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 80881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 80882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80883 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 80885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80887 | GIR_RootConstrainSelectedInstOperands, |
| 80888 | // GIR_Coverage, 2101, |
| 80889 | GIR_EraseRootFromParent_Done, |
| 80890 | // Label 5511: @205839 |
| 80891 | GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(205911), // Rule ID 65181 // |
| 80892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 80893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80894 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 80896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80898 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80899 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80900 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80901 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80902 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80903 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80904 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 80905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 80906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80907 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 80909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80911 | GIR_RootConstrainSelectedInstOperands, |
| 80912 | // GIR_Coverage, 65181, |
| 80913 | GIR_EraseRootFromParent_Done, |
| 80914 | // Label 5512: @205911 |
| 80915 | GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(205983), // Rule ID 65182 // |
| 80916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 80917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 80920 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80921 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80922 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80923 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80924 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80925 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80926 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80927 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80928 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 80929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 80930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80932 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 80933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80935 | GIR_RootConstrainSelectedInstOperands, |
| 80936 | // GIR_Coverage, 65182, |
| 80937 | GIR_EraseRootFromParent_Done, |
| 80938 | // Label 5513: @205983 |
| 80939 | GIM_Try, /*On fail goto*//*Label 5514*/ GIMT_Encode4(206055), // Rule ID 65189 // |
| 80940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 80941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80942 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80943 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 80944 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80945 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80946 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80947 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80948 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80949 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80950 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80951 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80952 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 80953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 80954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80955 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80956 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 80957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80959 | GIR_RootConstrainSelectedInstOperands, |
| 80960 | // GIR_Coverage, 65189, |
| 80961 | GIR_EraseRootFromParent_Done, |
| 80962 | // Label 5514: @206055 |
| 80963 | GIM_Try, /*On fail goto*//*Label 5515*/ GIMT_Encode4(206127), // Rule ID 65190 // |
| 80964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 80965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80966 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80967 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 80968 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80969 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80970 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80971 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 80972 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80973 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80974 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 80975 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80976 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 80977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 80978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 80979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 80980 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 80981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 80982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 80983 | GIR_RootConstrainSelectedInstOperands, |
| 80984 | // GIR_Coverage, 65190, |
| 80985 | GIR_EraseRootFromParent_Done, |
| 80986 | // Label 5515: @206127 |
| 80987 | GIM_Try, /*On fail goto*//*Label 5516*/ GIMT_Encode4(206184), // Rule ID 2064 // |
| 80988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 80989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80990 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80991 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 80992 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80993 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80994 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80995 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 80996 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80997 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 80998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 80999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81001 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81002 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81004 | GIR_RootConstrainSelectedInstOperands, |
| 81005 | // GIR_Coverage, 2064, |
| 81006 | GIR_EraseRootFromParent_Done, |
| 81007 | // Label 5516: @206184 |
| 81008 | GIM_Try, /*On fail goto*//*Label 5517*/ GIMT_Encode4(206241), // Rule ID 2065 // |
| 81009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 81010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81011 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81012 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81013 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81014 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81015 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81016 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81017 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81018 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 81020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81022 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81023 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81025 | GIR_RootConstrainSelectedInstOperands, |
| 81026 | // GIR_Coverage, 2065, |
| 81027 | GIR_EraseRootFromParent_Done, |
| 81028 | // Label 5517: @206241 |
| 81029 | GIM_Try, /*On fail goto*//*Label 5518*/ GIMT_Encode4(206298), // Rule ID 2096 // |
| 81030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 81031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81032 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81033 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81034 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81035 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81036 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81037 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81038 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81039 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 81041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81043 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81044 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81046 | GIR_RootConstrainSelectedInstOperands, |
| 81047 | // GIR_Coverage, 2096, |
| 81048 | GIR_EraseRootFromParent_Done, |
| 81049 | // Label 5518: @206298 |
| 81050 | GIM_Try, /*On fail goto*//*Label 5519*/ GIMT_Encode4(206355), // Rule ID 2097 // |
| 81051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 81052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81053 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81054 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81055 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81056 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81057 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81058 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81059 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81060 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 81062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81063 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81065 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81067 | GIR_RootConstrainSelectedInstOperands, |
| 81068 | // GIR_Coverage, 2097, |
| 81069 | GIR_EraseRootFromParent_Done, |
| 81070 | // Label 5519: @206355 |
| 81071 | GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(206412), // Rule ID 65177 // |
| 81072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 81073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81074 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81075 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81076 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81077 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81078 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81079 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81080 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81081 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 81083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81085 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81086 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81088 | GIR_RootConstrainSelectedInstOperands, |
| 81089 | // GIR_Coverage, 65177, |
| 81090 | GIR_EraseRootFromParent_Done, |
| 81091 | // Label 5520: @206412 |
| 81092 | GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(206469), // Rule ID 65178 // |
| 81093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 81094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81095 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81096 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81097 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81098 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81099 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81100 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81101 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81102 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 81104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81106 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81107 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81109 | GIR_RootConstrainSelectedInstOperands, |
| 81110 | // GIR_Coverage, 65178, |
| 81111 | GIR_EraseRootFromParent_Done, |
| 81112 | // Label 5521: @206469 |
| 81113 | GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(206526), // Rule ID 65185 // |
| 81114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 81115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81117 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81118 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81119 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81120 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81121 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81122 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81123 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 81125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81126 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81127 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81128 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81130 | GIR_RootConstrainSelectedInstOperands, |
| 81131 | // GIR_Coverage, 65185, |
| 81132 | GIR_EraseRootFromParent_Done, |
| 81133 | // Label 5522: @206526 |
| 81134 | GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(206583), // Rule ID 65186 // |
| 81135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 81136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81138 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81139 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81140 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81141 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81142 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81143 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81144 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 81146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81148 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81149 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81151 | GIR_RootConstrainSelectedInstOperands, |
| 81152 | // GIR_Coverage, 65186, |
| 81153 | GIR_EraseRootFromParent_Done, |
| 81154 | // Label 5523: @206583 |
| 81155 | GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(206640), // Rule ID 2060 // |
| 81156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 81157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81161 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81163 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81164 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81165 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H), |
| 81167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81169 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81172 | GIR_RootConstrainSelectedInstOperands, |
| 81173 | // GIR_Coverage, 2060, |
| 81174 | GIR_EraseRootFromParent_Done, |
| 81175 | // Label 5524: @206640 |
| 81176 | GIM_Try, /*On fail goto*//*Label 5525*/ GIMT_Encode4(206697), // Rule ID 2061 // |
| 81177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 81178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81179 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81180 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81181 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81182 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81184 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81185 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81186 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H), |
| 81188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81189 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81190 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81193 | GIR_RootConstrainSelectedInstOperands, |
| 81194 | // GIR_Coverage, 2061, |
| 81195 | GIR_EraseRootFromParent_Done, |
| 81196 | // Label 5525: @206697 |
| 81197 | GIM_Try, /*On fail goto*//*Label 5526*/ GIMT_Encode4(206754), // Rule ID 2092 // |
| 81198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 81199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81202 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81203 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81204 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81205 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81206 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81207 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H_INX), |
| 81209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81210 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81211 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81214 | GIR_RootConstrainSelectedInstOperands, |
| 81215 | // GIR_Coverage, 2092, |
| 81216 | GIR_EraseRootFromParent_Done, |
| 81217 | // Label 5526: @206754 |
| 81218 | GIM_Try, /*On fail goto*//*Label 5527*/ GIMT_Encode4(206811), // Rule ID 2093 // |
| 81219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 81220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81221 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81222 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81224 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81225 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81226 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81227 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81228 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H_INX), |
| 81230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81231 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81232 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81233 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81235 | GIR_RootConstrainSelectedInstOperands, |
| 81236 | // GIR_Coverage, 2093, |
| 81237 | GIR_EraseRootFromParent_Done, |
| 81238 | // Label 5527: @206811 |
| 81239 | GIM_Try, /*On fail goto*//*Label 5528*/ GIMT_Encode4(206851), // Rule ID 2056 // |
| 81240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 81241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81242 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81243 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81244 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81245 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FMADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H), |
| 81247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81248 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81249 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81250 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81252 | GIR_RootConstrainSelectedInstOperands, |
| 81253 | // GIR_Coverage, 2056, |
| 81254 | GIR_EraseRootFromParent_Done, |
| 81255 | // Label 5528: @206851 |
| 81256 | GIM_Try, /*On fail goto*//*Label 5529*/ GIMT_Encode4(206891), // Rule ID 2057 // |
| 81257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 81258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81261 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 81262 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FMADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H), |
| 81264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81265 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81266 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81267 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81269 | GIR_RootConstrainSelectedInstOperands, |
| 81270 | // GIR_Coverage, 2057, |
| 81271 | GIR_EraseRootFromParent_Done, |
| 81272 | // Label 5529: @206891 |
| 81273 | GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(206931), // Rule ID 2088 // |
| 81274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 81275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81277 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81278 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81279 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FMADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 81280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H_INX), |
| 81281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81282 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81283 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81284 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81286 | GIR_RootConstrainSelectedInstOperands, |
| 81287 | // GIR_Coverage, 2088, |
| 81288 | GIR_EraseRootFromParent_Done, |
| 81289 | // Label 5530: @206931 |
| 81290 | GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(206971), // Rule ID 2089 // |
| 81291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 81292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81293 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81294 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81295 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 81296 | // (fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FMADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 81297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H_INX), |
| 81298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81299 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81300 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81301 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81303 | GIR_RootConstrainSelectedInstOperands, |
| 81304 | // GIR_Coverage, 2089, |
| 81305 | GIR_EraseRootFromParent_Done, |
| 81306 | // Label 5531: @206971 |
| 81307 | GIM_Reject, |
| 81308 | // Label 5507: @206972 |
| 81309 | GIM_Reject, |
| 81310 | // Label 5489: @206973 |
| 81311 | GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(208408), |
| 81312 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 81313 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 81314 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 81315 | GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(207059), // Rule ID 1387 // |
| 81316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 81317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81321 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81322 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81323 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81324 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81325 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81326 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81327 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81328 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 81330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81332 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81335 | GIR_RootConstrainSelectedInstOperands, |
| 81336 | // GIR_Coverage, 1387, |
| 81337 | GIR_EraseRootFromParent_Done, |
| 81338 | // Label 5533: @207059 |
| 81339 | GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(207131), // Rule ID 1388 // |
| 81340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 81341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81342 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81343 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81344 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81345 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81346 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81347 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81348 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81349 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81350 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81351 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81352 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 81354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81356 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81359 | GIR_RootConstrainSelectedInstOperands, |
| 81360 | // GIR_Coverage, 1388, |
| 81361 | GIR_EraseRootFromParent_Done, |
| 81362 | // Label 5534: @207131 |
| 81363 | GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(207203), // Rule ID 1408 // |
| 81364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 81365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81366 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81367 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81368 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81369 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81370 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81371 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81372 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81373 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81374 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81375 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81376 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 81378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81380 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81383 | GIR_RootConstrainSelectedInstOperands, |
| 81384 | // GIR_Coverage, 1408, |
| 81385 | GIR_EraseRootFromParent_Done, |
| 81386 | // Label 5535: @207203 |
| 81387 | GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(207275), // Rule ID 1409 // |
| 81388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 81389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81390 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81391 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81392 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81393 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81395 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81396 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81397 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81398 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81399 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81400 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 81402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81404 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81407 | GIR_RootConstrainSelectedInstOperands, |
| 81408 | // GIR_Coverage, 1409, |
| 81409 | GIR_EraseRootFromParent_Done, |
| 81410 | // Label 5536: @207275 |
| 81411 | GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(207347), // Rule ID 65145 // |
| 81412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 81413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81414 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81415 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81416 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81417 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81418 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81419 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81420 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81421 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81422 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81423 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81424 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 81426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81428 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81431 | GIR_RootConstrainSelectedInstOperands, |
| 81432 | // GIR_Coverage, 65145, |
| 81433 | GIR_EraseRootFromParent_Done, |
| 81434 | // Label 5537: @207347 |
| 81435 | GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(207419), // Rule ID 65146 // |
| 81436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 81437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81438 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81439 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81440 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81441 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81442 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81443 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81444 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81445 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81446 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81447 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81448 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 81450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81452 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81455 | GIR_RootConstrainSelectedInstOperands, |
| 81456 | // GIR_Coverage, 65146, |
| 81457 | GIR_EraseRootFromParent_Done, |
| 81458 | // Label 5538: @207419 |
| 81459 | GIM_Try, /*On fail goto*//*Label 5539*/ GIMT_Encode4(207491), // Rule ID 65153 // |
| 81460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 81461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81463 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81464 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81465 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81466 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81467 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81468 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81469 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81470 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81471 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81472 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 81474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81476 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81479 | GIR_RootConstrainSelectedInstOperands, |
| 81480 | // GIR_Coverage, 65153, |
| 81481 | GIR_EraseRootFromParent_Done, |
| 81482 | // Label 5539: @207491 |
| 81483 | GIM_Try, /*On fail goto*//*Label 5540*/ GIMT_Encode4(207563), // Rule ID 65154 // |
| 81484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 81485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81486 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81487 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81488 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81489 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81490 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81491 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81492 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81493 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81494 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81495 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81496 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 81498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81503 | GIR_RootConstrainSelectedInstOperands, |
| 81504 | // GIR_Coverage, 65154, |
| 81505 | GIR_EraseRootFromParent_Done, |
| 81506 | // Label 5540: @207563 |
| 81507 | GIM_Try, /*On fail goto*//*Label 5541*/ GIMT_Encode4(207620), // Rule ID 1383 // |
| 81508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 81509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81510 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81511 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81512 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81513 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81514 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81515 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81516 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81517 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 81519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81521 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81522 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81524 | GIR_RootConstrainSelectedInstOperands, |
| 81525 | // GIR_Coverage, 1383, |
| 81526 | GIR_EraseRootFromParent_Done, |
| 81527 | // Label 5541: @207620 |
| 81528 | GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(207677), // Rule ID 1384 // |
| 81529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 81530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81531 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81532 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81533 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81534 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81535 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81536 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81537 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81538 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 81540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81542 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81543 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81545 | GIR_RootConstrainSelectedInstOperands, |
| 81546 | // GIR_Coverage, 1384, |
| 81547 | GIR_EraseRootFromParent_Done, |
| 81548 | // Label 5542: @207677 |
| 81549 | GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(207734), // Rule ID 1404 // |
| 81550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 81551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81552 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81553 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81554 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81555 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81556 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81557 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81558 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81559 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 81561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81563 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81564 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81566 | GIR_RootConstrainSelectedInstOperands, |
| 81567 | // GIR_Coverage, 1404, |
| 81568 | GIR_EraseRootFromParent_Done, |
| 81569 | // Label 5543: @207734 |
| 81570 | GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(207791), // Rule ID 1405 // |
| 81571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 81572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81573 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81574 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81575 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81576 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81578 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81579 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81580 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 81582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81583 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81584 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81585 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81587 | GIR_RootConstrainSelectedInstOperands, |
| 81588 | // GIR_Coverage, 1405, |
| 81589 | GIR_EraseRootFromParent_Done, |
| 81590 | // Label 5544: @207791 |
| 81591 | GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(207848), // Rule ID 65141 // |
| 81592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 81593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81594 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81595 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81596 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81597 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81598 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81599 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81600 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81601 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 81603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81605 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81606 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81608 | GIR_RootConstrainSelectedInstOperands, |
| 81609 | // GIR_Coverage, 65141, |
| 81610 | GIR_EraseRootFromParent_Done, |
| 81611 | // Label 5545: @207848 |
| 81612 | GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(207905), // Rule ID 65142 // |
| 81613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 81614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81615 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81616 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81617 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81618 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81619 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81620 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81621 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81622 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 81624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81626 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81627 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81629 | GIR_RootConstrainSelectedInstOperands, |
| 81630 | // GIR_Coverage, 65142, |
| 81631 | GIR_EraseRootFromParent_Done, |
| 81632 | // Label 5546: @207905 |
| 81633 | GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(207962), // Rule ID 65149 // |
| 81634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 81635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81636 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81637 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81638 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81639 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81640 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81641 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81642 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81643 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 81645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81647 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81648 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81650 | GIR_RootConstrainSelectedInstOperands, |
| 81651 | // GIR_Coverage, 65149, |
| 81652 | GIR_EraseRootFromParent_Done, |
| 81653 | // Label 5547: @207962 |
| 81654 | GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(208019), // Rule ID 65150 // |
| 81655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 81656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81657 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81658 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81659 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81660 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81661 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81662 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81663 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81664 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 81666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81667 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81668 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81669 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81671 | GIR_RootConstrainSelectedInstOperands, |
| 81672 | // GIR_Coverage, 65150, |
| 81673 | GIR_EraseRootFromParent_Done, |
| 81674 | // Label 5548: @208019 |
| 81675 | GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(208076), // Rule ID 1379 // |
| 81676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 81677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81678 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81680 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81681 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81682 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81683 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81684 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81685 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S), |
| 81687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81688 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81689 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81692 | GIR_RootConstrainSelectedInstOperands, |
| 81693 | // GIR_Coverage, 1379, |
| 81694 | GIR_EraseRootFromParent_Done, |
| 81695 | // Label 5549: @208076 |
| 81696 | GIM_Try, /*On fail goto*//*Label 5550*/ GIMT_Encode4(208133), // Rule ID 1380 // |
| 81697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 81698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81699 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81700 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81701 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81702 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81703 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81704 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81705 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81706 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S), |
| 81708 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81709 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81710 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81713 | GIR_RootConstrainSelectedInstOperands, |
| 81714 | // GIR_Coverage, 1380, |
| 81715 | GIR_EraseRootFromParent_Done, |
| 81716 | // Label 5550: @208133 |
| 81717 | GIM_Try, /*On fail goto*//*Label 5551*/ GIMT_Encode4(208190), // Rule ID 1400 // |
| 81718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 81719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81720 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81721 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81723 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81724 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81725 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81726 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81727 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S_INX), |
| 81729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81730 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81731 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81734 | GIR_RootConstrainSelectedInstOperands, |
| 81735 | // GIR_Coverage, 1400, |
| 81736 | GIR_EraseRootFromParent_Done, |
| 81737 | // Label 5551: @208190 |
| 81738 | GIM_Try, /*On fail goto*//*Label 5552*/ GIMT_Encode4(208247), // Rule ID 1401 // |
| 81739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 81740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81741 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81742 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 81744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81746 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81747 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81748 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S_INX), |
| 81750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81752 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 81754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81755 | GIR_RootConstrainSelectedInstOperands, |
| 81756 | // GIR_Coverage, 1401, |
| 81757 | GIR_EraseRootFromParent_Done, |
| 81758 | // Label 5552: @208247 |
| 81759 | GIM_Try, /*On fail goto*//*Label 5553*/ GIMT_Encode4(208287), // Rule ID 1375 // |
| 81760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 81761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81763 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81764 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81765 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S), |
| 81767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81768 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81769 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81770 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81772 | GIR_RootConstrainSelectedInstOperands, |
| 81773 | // GIR_Coverage, 1375, |
| 81774 | GIR_EraseRootFromParent_Done, |
| 81775 | // Label 5553: @208287 |
| 81776 | GIM_Try, /*On fail goto*//*Label 5554*/ GIMT_Encode4(208327), // Rule ID 1376 // |
| 81777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 81778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81779 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81780 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81781 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 81782 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S), |
| 81784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81785 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81786 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81787 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81789 | GIR_RootConstrainSelectedInstOperands, |
| 81790 | // GIR_Coverage, 1376, |
| 81791 | GIR_EraseRootFromParent_Done, |
| 81792 | // Label 5554: @208327 |
| 81793 | GIM_Try, /*On fail goto*//*Label 5555*/ GIMT_Encode4(208367), // Rule ID 1396 // |
| 81794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 81795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81798 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81799 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FMADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 81800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S_INX), |
| 81801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81802 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81803 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81804 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81806 | GIR_RootConstrainSelectedInstOperands, |
| 81807 | // GIR_Coverage, 1396, |
| 81808 | GIR_EraseRootFromParent_Done, |
| 81809 | // Label 5555: @208367 |
| 81810 | GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(208407), // Rule ID 1397 // |
| 81811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 81812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81813 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81814 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81815 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 81816 | // (fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FMADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 81817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S_INX), |
| 81818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81819 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 81820 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81821 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 81822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81823 | GIR_RootConstrainSelectedInstOperands, |
| 81824 | // GIR_Coverage, 1397, |
| 81825 | GIR_EraseRootFromParent_Done, |
| 81826 | // Label 5556: @208407 |
| 81827 | GIM_Reject, |
| 81828 | // Label 5532: @208408 |
| 81829 | GIM_Reject, |
| 81830 | // Label 5490: @208409 |
| 81831 | GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(210199), |
| 81832 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 81833 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 81834 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 81835 | GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(208495), // Rule ID 1717 // |
| 81836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 81837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81839 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81841 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81843 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81844 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81845 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81846 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81847 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81848 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 81849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 81850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81852 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81855 | GIR_RootConstrainSelectedInstOperands, |
| 81856 | // GIR_Coverage, 1717, |
| 81857 | GIR_EraseRootFromParent_Done, |
| 81858 | // Label 5558: @208495 |
| 81859 | GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(208567), // Rule ID 1718 // |
| 81860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 81861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81862 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81863 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81864 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81865 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81866 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81867 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81868 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81869 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81870 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81871 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81872 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 81873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 81874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81876 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81879 | GIR_RootConstrainSelectedInstOperands, |
| 81880 | // GIR_Coverage, 1718, |
| 81881 | GIR_EraseRootFromParent_Done, |
| 81882 | // Label 5559: @208567 |
| 81883 | GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(208639), // Rule ID 1739 // |
| 81884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 81885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 81886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81887 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81889 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 81890 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 81891 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81892 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81893 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81894 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 81895 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81896 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs3)) => (FNMADD_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 81897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_INX), |
| 81898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81900 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81903 | GIR_RootConstrainSelectedInstOperands, |
| 81904 | // GIR_Coverage, 1739, |
| 81905 | GIR_EraseRootFromParent_Done, |
| 81906 | // Label 5560: @208639 |
| 81907 | GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(208711), // Rule ID 1769 // |
| 81908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 81909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81910 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81911 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81912 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81913 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81914 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81915 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81916 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81917 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81918 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81919 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81920 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 81921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 81922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81924 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81927 | GIR_RootConstrainSelectedInstOperands, |
| 81928 | // GIR_Coverage, 1769, |
| 81929 | GIR_EraseRootFromParent_Done, |
| 81930 | // Label 5561: @208711 |
| 81931 | GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(208783), // Rule ID 1770 // |
| 81932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 81933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81934 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81935 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81936 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81937 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81938 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81939 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81940 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81941 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81942 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 81943 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81944 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 81945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 81946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81948 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 81949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81951 | GIR_RootConstrainSelectedInstOperands, |
| 81952 | // GIR_Coverage, 1770, |
| 81953 | GIR_EraseRootFromParent_Done, |
| 81954 | // Label 5562: @208783 |
| 81955 | GIM_Try, /*On fail goto*//*Label 5563*/ GIMT_Encode4(208855), // Rule ID 65161 // |
| 81956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 81957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81960 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81962 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81963 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81964 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81965 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81966 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81967 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81968 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 81969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 81970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81975 | GIR_RootConstrainSelectedInstOperands, |
| 81976 | // GIR_Coverage, 65161, |
| 81977 | GIR_EraseRootFromParent_Done, |
| 81978 | // Label 5563: @208855 |
| 81979 | GIM_Try, /*On fail goto*//*Label 5564*/ GIMT_Encode4(208927), // Rule ID 65162 // |
| 81980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 81981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81984 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81985 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 81986 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81987 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 81988 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 81989 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 81990 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 81991 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81992 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 81993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 81994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 81995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 81996 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 81997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 81998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 81999 | GIR_RootConstrainSelectedInstOperands, |
| 82000 | // GIR_Coverage, 65162, |
| 82001 | GIR_EraseRootFromParent_Done, |
| 82002 | // Label 5564: @208927 |
| 82003 | GIM_Try, /*On fail goto*//*Label 5565*/ GIMT_Encode4(208999), // Rule ID 65166 // |
| 82004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 82005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82007 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82008 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82009 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82010 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82011 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82012 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82013 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 82014 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82015 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82016 | // (fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs3)) => (FNMADD_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_INX), |
| 82018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82020 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 82022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82023 | GIR_RootConstrainSelectedInstOperands, |
| 82024 | // GIR_Coverage, 65166, |
| 82025 | GIR_EraseRootFromParent_Done, |
| 82026 | // Label 5565: @208999 |
| 82027 | GIM_Try, /*On fail goto*//*Label 5566*/ GIMT_Encode4(209071), // Rule ID 65173 // |
| 82028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 82029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82031 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82032 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82033 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82034 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82035 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82036 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82037 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 82038 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82039 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82040 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 82042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82044 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 82046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82047 | GIR_RootConstrainSelectedInstOperands, |
| 82048 | // GIR_Coverage, 65173, |
| 82049 | GIR_EraseRootFromParent_Done, |
| 82050 | // Label 5566: @209071 |
| 82051 | GIM_Try, /*On fail goto*//*Label 5567*/ GIMT_Encode4(209143), // Rule ID 65174 // |
| 82052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 82053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82054 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82055 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82056 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82057 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82058 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82059 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82060 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82061 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 82062 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82063 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82064 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 82066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 82070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82071 | GIR_RootConstrainSelectedInstOperands, |
| 82072 | // GIR_Coverage, 65174, |
| 82073 | GIR_EraseRootFromParent_Done, |
| 82074 | // Label 5567: @209143 |
| 82075 | GIM_Try, /*On fail goto*//*Label 5568*/ GIMT_Encode4(209200), // Rule ID 1713 // |
| 82076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 82077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82078 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82079 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82080 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82081 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82082 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82083 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82084 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82085 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 82087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82088 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82089 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82090 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82092 | GIR_RootConstrainSelectedInstOperands, |
| 82093 | // GIR_Coverage, 1713, |
| 82094 | GIR_EraseRootFromParent_Done, |
| 82095 | // Label 5568: @209200 |
| 82096 | GIM_Try, /*On fail goto*//*Label 5569*/ GIMT_Encode4(209257), // Rule ID 1714 // |
| 82097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 82098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82099 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82100 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82101 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82102 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82104 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82105 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82106 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 82108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82110 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82111 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82113 | GIR_RootConstrainSelectedInstOperands, |
| 82114 | // GIR_Coverage, 1714, |
| 82115 | GIR_EraseRootFromParent_Done, |
| 82116 | // Label 5569: @209257 |
| 82117 | GIM_Try, /*On fail goto*//*Label 5570*/ GIMT_Encode4(209314), // Rule ID 1737 // |
| 82118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 82119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82120 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82121 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82122 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82123 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82124 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82125 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82126 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82127 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3) => (FNMSUB_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_INX), |
| 82129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82131 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82132 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82134 | GIR_RootConstrainSelectedInstOperands, |
| 82135 | // GIR_Coverage, 1737, |
| 82136 | GIR_EraseRootFromParent_Done, |
| 82137 | // Label 5570: @209314 |
| 82138 | GIM_Try, /*On fail goto*//*Label 5571*/ GIMT_Encode4(209371), // Rule ID 1765 // |
| 82139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 82140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82141 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82142 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82143 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82144 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82146 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82147 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82148 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 82150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82152 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82153 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82155 | GIR_RootConstrainSelectedInstOperands, |
| 82156 | // GIR_Coverage, 1765, |
| 82157 | GIR_EraseRootFromParent_Done, |
| 82158 | // Label 5571: @209371 |
| 82159 | GIM_Try, /*On fail goto*//*Label 5572*/ GIMT_Encode4(209428), // Rule ID 1766 // |
| 82160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 82161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82163 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82164 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82165 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82166 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82167 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82168 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82169 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 82171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82173 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82174 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82176 | GIR_RootConstrainSelectedInstOperands, |
| 82177 | // GIR_Coverage, 1766, |
| 82178 | GIR_EraseRootFromParent_Done, |
| 82179 | // Label 5572: @209428 |
| 82180 | GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(209485), // Rule ID 65157 // |
| 82181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 82182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82183 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82184 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82185 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82186 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82187 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82188 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82189 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82190 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 82192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82194 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82195 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82197 | GIR_RootConstrainSelectedInstOperands, |
| 82198 | // GIR_Coverage, 65157, |
| 82199 | GIR_EraseRootFromParent_Done, |
| 82200 | // Label 5573: @209485 |
| 82201 | GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(209542), // Rule ID 65158 // |
| 82202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 82203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82204 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82205 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82206 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82207 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82208 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82209 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82210 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82211 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 82213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82215 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82216 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82218 | GIR_RootConstrainSelectedInstOperands, |
| 82219 | // GIR_Coverage, 65158, |
| 82220 | GIR_EraseRootFromParent_Done, |
| 82221 | // Label 5574: @209542 |
| 82222 | GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(209599), // Rule ID 65164 // |
| 82223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 82224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82226 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82227 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82228 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82229 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82230 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82231 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82232 | // (fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), FPR64INX:{ *:[f64] }:$rs3) => (FNMSUB_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_INX), |
| 82234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82236 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82237 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82239 | GIR_RootConstrainSelectedInstOperands, |
| 82240 | // GIR_Coverage, 65164, |
| 82241 | GIR_EraseRootFromParent_Done, |
| 82242 | // Label 5575: @209599 |
| 82243 | GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(209656), // Rule ID 65169 // |
| 82244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 82245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82246 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82247 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82248 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82249 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82250 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82251 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82252 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82253 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 82255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82256 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82257 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82258 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82260 | GIR_RootConstrainSelectedInstOperands, |
| 82261 | // GIR_Coverage, 65169, |
| 82262 | GIR_EraseRootFromParent_Done, |
| 82263 | // Label 5576: @209656 |
| 82264 | GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(209713), // Rule ID 65170 // |
| 82265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 82266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82267 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82269 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82271 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82272 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82273 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82274 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 82276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82278 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 82279 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82281 | GIR_RootConstrainSelectedInstOperands, |
| 82282 | // GIR_Coverage, 65170, |
| 82283 | GIR_EraseRootFromParent_Done, |
| 82284 | // Label 5577: @209713 |
| 82285 | GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(209770), // Rule ID 1709 // |
| 82286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 82287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82289 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82290 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82291 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82292 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82293 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82294 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82295 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D), |
| 82297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82298 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82299 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 82301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82302 | GIR_RootConstrainSelectedInstOperands, |
| 82303 | // GIR_Coverage, 1709, |
| 82304 | GIR_EraseRootFromParent_Done, |
| 82305 | // Label 5578: @209770 |
| 82306 | GIM_Try, /*On fail goto*//*Label 5579*/ GIMT_Encode4(209827), // Rule ID 1710 // |
| 82307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 82308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82309 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82311 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82312 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82313 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82314 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82315 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82316 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D), |
| 82318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82319 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82320 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 82322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82323 | GIR_RootConstrainSelectedInstOperands, |
| 82324 | // GIR_Coverage, 1710, |
| 82325 | GIR_EraseRootFromParent_Done, |
| 82326 | // Label 5579: @209827 |
| 82327 | GIM_Try, /*On fail goto*//*Label 5580*/ GIMT_Encode4(209884), // Rule ID 1735 // |
| 82328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 82329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82330 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82331 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82335 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82336 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82337 | // (fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs3)) => (FMSUB_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D_INX), |
| 82339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82340 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82341 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 82343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82344 | GIR_RootConstrainSelectedInstOperands, |
| 82345 | // GIR_Coverage, 1735, |
| 82346 | GIR_EraseRootFromParent_Done, |
| 82347 | // Label 5580: @209884 |
| 82348 | GIM_Try, /*On fail goto*//*Label 5581*/ GIMT_Encode4(209941), // Rule ID 1761 // |
| 82349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 82350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82351 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82352 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82353 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82354 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82355 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82356 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82357 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82358 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D_IN32X), |
| 82360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82361 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82362 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82363 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 82364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82365 | GIR_RootConstrainSelectedInstOperands, |
| 82366 | // GIR_Coverage, 1761, |
| 82367 | GIR_EraseRootFromParent_Done, |
| 82368 | // Label 5581: @209941 |
| 82369 | GIM_Try, /*On fail goto*//*Label 5582*/ GIMT_Encode4(209998), // Rule ID 1762 // |
| 82370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 82371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82374 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82375 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82376 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 82377 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82378 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82379 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D_IN32X), |
| 82381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82382 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82383 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 82385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82386 | GIR_RootConstrainSelectedInstOperands, |
| 82387 | // GIR_Coverage, 1762, |
| 82388 | GIR_EraseRootFromParent_Done, |
| 82389 | // Label 5582: @209998 |
| 82390 | GIM_Try, /*On fail goto*//*Label 5583*/ GIMT_Encode4(210038), // Rule ID 1705 // |
| 82391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 82392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82395 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82396 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D), |
| 82398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82399 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82400 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82401 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82403 | GIR_RootConstrainSelectedInstOperands, |
| 82404 | // GIR_Coverage, 1705, |
| 82405 | GIR_EraseRootFromParent_Done, |
| 82406 | // Label 5583: @210038 |
| 82407 | GIM_Try, /*On fail goto*//*Label 5584*/ GIMT_Encode4(210078), // Rule ID 1706 // |
| 82408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 82409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82410 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82411 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82412 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 82413 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D), |
| 82415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82416 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82417 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82418 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82420 | GIR_RootConstrainSelectedInstOperands, |
| 82421 | // GIR_Coverage, 1706, |
| 82422 | GIR_EraseRootFromParent_Done, |
| 82423 | // Label 5584: @210078 |
| 82424 | GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(210118), // Rule ID 1733 // |
| 82425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 82426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82427 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82428 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82429 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 82430 | // (fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3) => (FMADD_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D_INX), |
| 82432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82433 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82434 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82435 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82437 | GIR_RootConstrainSelectedInstOperands, |
| 82438 | // GIR_Coverage, 1733, |
| 82439 | GIR_EraseRootFromParent_Done, |
| 82440 | // Label 5585: @210118 |
| 82441 | GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(210158), // Rule ID 1757 // |
| 82442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 82443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82444 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82445 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82446 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82447 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FMADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 82448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D_IN32X), |
| 82449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82450 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82451 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82452 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82454 | GIR_RootConstrainSelectedInstOperands, |
| 82455 | // GIR_Coverage, 1757, |
| 82456 | GIR_EraseRootFromParent_Done, |
| 82457 | // Label 5586: @210158 |
| 82458 | GIM_Try, /*On fail goto*//*Label 5587*/ GIMT_Encode4(210198), // Rule ID 1758 // |
| 82459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 82460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82461 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82462 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82463 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 82464 | // (fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FMADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 82465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D_IN32X), |
| 82466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82467 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82468 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 82469 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 82470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82471 | GIR_RootConstrainSelectedInstOperands, |
| 82472 | // GIR_Coverage, 1758, |
| 82473 | GIR_EraseRootFromParent_Done, |
| 82474 | // Label 5587: @210198 |
| 82475 | GIM_Reject, |
| 82476 | // Label 5557: @210199 |
| 82477 | GIM_Reject, |
| 82478 | // Label 5491: @210200 |
| 82479 | GIM_Try, /*On fail goto*//*Label 5588*/ GIMT_Encode4(210989), |
| 82480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82481 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 82482 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 82483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82484 | GIM_Try, /*On fail goto*//*Label 5589*/ GIMT_Encode4(210295), // Rule ID 55462 // |
| 82485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 82486 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82487 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82488 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82489 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82490 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82491 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82492 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82493 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82494 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82495 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82496 | // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 82497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 82498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82499 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82506 | GIR_RootConstrainSelectedInstOperands, |
| 82507 | // GIR_Coverage, 55462, |
| 82508 | GIR_EraseRootFromParent_Done, |
| 82509 | // Label 5589: @210295 |
| 82510 | GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(210372), // Rule ID 55463 // |
| 82511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 82512 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82513 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82514 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82515 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82516 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82517 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82518 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82519 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82520 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82521 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82522 | // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 82523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 82524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82525 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82532 | GIR_RootConstrainSelectedInstOperands, |
| 82533 | // GIR_Coverage, 55463, |
| 82534 | GIR_EraseRootFromParent_Done, |
| 82535 | // Label 5590: @210372 |
| 82536 | GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(210449), // Rule ID 71996 // |
| 82537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 82538 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82539 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82540 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82541 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82542 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82543 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82544 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82545 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82546 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82547 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82548 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 82549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 82550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82551 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82558 | GIR_RootConstrainSelectedInstOperands, |
| 82559 | // GIR_Coverage, 71996, |
| 82560 | GIR_EraseRootFromParent_Done, |
| 82561 | // Label 5591: @210449 |
| 82562 | GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(210526), // Rule ID 71997 // |
| 82563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 82564 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82568 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82569 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82570 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82571 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82572 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82573 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82574 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 82575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 82576 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82577 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82584 | GIR_RootConstrainSelectedInstOperands, |
| 82585 | // GIR_Coverage, 71997, |
| 82586 | GIR_EraseRootFromParent_Done, |
| 82587 | // Label 5592: @210526 |
| 82588 | GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(210588), // Rule ID 55466 // |
| 82589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 82590 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82591 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82592 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82593 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82594 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82595 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82596 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82597 | // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 82598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 82599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82600 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82602 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82607 | GIR_RootConstrainSelectedInstOperands, |
| 82608 | // GIR_Coverage, 55466, |
| 82609 | GIR_EraseRootFromParent_Done, |
| 82610 | // Label 5593: @210588 |
| 82611 | GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(210650), // Rule ID 55467 // |
| 82612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 82613 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82614 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82615 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82616 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82618 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82619 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82620 | // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 82621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 82622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82623 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82625 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82630 | GIR_RootConstrainSelectedInstOperands, |
| 82631 | // GIR_Coverage, 55467, |
| 82632 | GIR_EraseRootFromParent_Done, |
| 82633 | // Label 5594: @210650 |
| 82634 | GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(210712), // Rule ID 72000 // |
| 82635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 82636 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82637 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82638 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82639 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82640 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82641 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82642 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82643 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 82644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 82645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82646 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82648 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82653 | GIR_RootConstrainSelectedInstOperands, |
| 82654 | // GIR_Coverage, 72000, |
| 82655 | GIR_EraseRootFromParent_Done, |
| 82656 | // Label 5595: @210712 |
| 82657 | GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(210774), // Rule ID 72001 // |
| 82658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 82659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82661 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82662 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82663 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82664 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82665 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82666 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 82667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 82668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82669 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82671 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82676 | GIR_RootConstrainSelectedInstOperands, |
| 82677 | // GIR_Coverage, 72001, |
| 82678 | GIR_EraseRootFromParent_Done, |
| 82679 | // Label 5596: @210774 |
| 82680 | GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(210836), // Rule ID 55458 // |
| 82681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 82682 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82687 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82688 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82689 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 82690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF4_E16), |
| 82691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82692 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82693 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 82695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82699 | GIR_RootConstrainSelectedInstOperands, |
| 82700 | // GIR_Coverage, 55458, |
| 82701 | GIR_EraseRootFromParent_Done, |
| 82702 | // Label 5597: @210836 |
| 82703 | GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(210898), // Rule ID 55459 // |
| 82704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 82705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82706 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82708 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82709 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 82710 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82711 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82712 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 82713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF4_E16), |
| 82714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82715 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82716 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 82718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82722 | GIR_RootConstrainSelectedInstOperands, |
| 82723 | // GIR_Coverage, 55459, |
| 82724 | GIR_EraseRootFromParent_Done, |
| 82725 | // Label 5598: @210898 |
| 82726 | GIM_Try, /*On fail goto*//*Label 5599*/ GIMT_Encode4(210943), // Rule ID 55454 // |
| 82727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 82728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82730 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82731 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 82732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF4_E16), |
| 82733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82734 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82735 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82736 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82741 | GIR_RootConstrainSelectedInstOperands, |
| 82742 | // GIR_Coverage, 55454, |
| 82743 | GIR_EraseRootFromParent_Done, |
| 82744 | // Label 5599: @210943 |
| 82745 | GIM_Try, /*On fail goto*//*Label 5600*/ GIMT_Encode4(210988), // Rule ID 55455 // |
| 82746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 82747 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82748 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82749 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82750 | // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 82751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF4_E16), |
| 82752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82753 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82754 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82755 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 82759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82760 | GIR_RootConstrainSelectedInstOperands, |
| 82761 | // GIR_Coverage, 55455, |
| 82762 | GIR_EraseRootFromParent_Done, |
| 82763 | // Label 5600: @210988 |
| 82764 | GIM_Reject, |
| 82765 | // Label 5588: @210989 |
| 82766 | GIM_Reject, |
| 82767 | // Label 5492: @210990 |
| 82768 | GIM_Try, /*On fail goto*//*Label 5601*/ GIMT_Encode4(211779), |
| 82769 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 82771 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 82772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82773 | GIM_Try, /*On fail goto*//*Label 5602*/ GIMT_Encode4(211085), // Rule ID 55590 // |
| 82774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 82775 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82776 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82777 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82778 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82780 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82781 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82782 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82783 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82784 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82785 | // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 82786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 82787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82788 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82795 | GIR_RootConstrainSelectedInstOperands, |
| 82796 | // GIR_Coverage, 55590, |
| 82797 | GIR_EraseRootFromParent_Done, |
| 82798 | // Label 5602: @211085 |
| 82799 | GIM_Try, /*On fail goto*//*Label 5603*/ GIMT_Encode4(211162), // Rule ID 55591 // |
| 82800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 82801 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82802 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82803 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82804 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82806 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82807 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82808 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82809 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82810 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82811 | // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 82812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 82813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82814 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82821 | GIR_RootConstrainSelectedInstOperands, |
| 82822 | // GIR_Coverage, 55591, |
| 82823 | GIR_EraseRootFromParent_Done, |
| 82824 | // Label 5603: @211162 |
| 82825 | GIM_Try, /*On fail goto*//*Label 5604*/ GIMT_Encode4(211239), // Rule ID 72108 // |
| 82826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 82827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82831 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82832 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82833 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82834 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82835 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82836 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82837 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 82838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 82839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82840 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82841 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82842 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82847 | GIR_RootConstrainSelectedInstOperands, |
| 82848 | // GIR_Coverage, 72108, |
| 82849 | GIR_EraseRootFromParent_Done, |
| 82850 | // Label 5604: @211239 |
| 82851 | GIM_Try, /*On fail goto*//*Label 5605*/ GIMT_Encode4(211316), // Rule ID 72109 // |
| 82852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 82853 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82854 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82855 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82856 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82857 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82858 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 82859 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82860 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82861 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82862 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82863 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 82864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 82865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82866 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 82869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82873 | GIR_RootConstrainSelectedInstOperands, |
| 82874 | // GIR_Coverage, 72109, |
| 82875 | GIR_EraseRootFromParent_Done, |
| 82876 | // Label 5605: @211316 |
| 82877 | GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(211378), // Rule ID 55594 // |
| 82878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 82879 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82880 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82881 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82882 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82883 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82884 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82885 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82886 | // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 82887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 82888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82889 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82891 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82896 | GIR_RootConstrainSelectedInstOperands, |
| 82897 | // GIR_Coverage, 55594, |
| 82898 | GIR_EraseRootFromParent_Done, |
| 82899 | // Label 5606: @211378 |
| 82900 | GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(211440), // Rule ID 55595 // |
| 82901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 82902 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 82903 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82904 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82905 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82906 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82907 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82908 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82909 | // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 82910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 82911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82912 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82914 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82919 | GIR_RootConstrainSelectedInstOperands, |
| 82920 | // GIR_Coverage, 55595, |
| 82921 | GIR_EraseRootFromParent_Done, |
| 82922 | // Label 5607: @211440 |
| 82923 | GIM_Try, /*On fail goto*//*Label 5608*/ GIMT_Encode4(211502), // Rule ID 72112 // |
| 82924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 82925 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82926 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82927 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82928 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82929 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82930 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82931 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82932 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 82933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 82934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82935 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82937 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82942 | GIR_RootConstrainSelectedInstOperands, |
| 82943 | // GIR_Coverage, 72112, |
| 82944 | GIR_EraseRootFromParent_Done, |
| 82945 | // Label 5608: @211502 |
| 82946 | GIM_Try, /*On fail goto*//*Label 5609*/ GIMT_Encode4(211564), // Rule ID 72113 // |
| 82947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 82948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82950 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82951 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82952 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82953 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82954 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82955 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 82956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 82957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82958 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 82959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 82960 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 82961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82965 | GIR_RootConstrainSelectedInstOperands, |
| 82966 | // GIR_Coverage, 72113, |
| 82967 | GIR_EraseRootFromParent_Done, |
| 82968 | // Label 5609: @211564 |
| 82969 | GIM_Try, /*On fail goto*//*Label 5610*/ GIMT_Encode4(211626), // Rule ID 55586 // |
| 82970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 82971 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82972 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82973 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82974 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82975 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82977 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 82978 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 82979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E32), |
| 82980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 82981 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 82982 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 82983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 82984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 82985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 82986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 82987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 82988 | GIR_RootConstrainSelectedInstOperands, |
| 82989 | // GIR_Coverage, 55586, |
| 82990 | GIR_EraseRootFromParent_Done, |
| 82991 | // Label 5610: @211626 |
| 82992 | GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(211688), // Rule ID 55587 // |
| 82993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 82994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 82996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 82997 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 82998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 82999 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83000 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83001 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E32), |
| 83003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83004 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83011 | GIR_RootConstrainSelectedInstOperands, |
| 83012 | // GIR_Coverage, 55587, |
| 83013 | GIR_EraseRootFromParent_Done, |
| 83014 | // Label 5611: @211688 |
| 83015 | GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(211733), // Rule ID 55582 // |
| 83016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83017 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83018 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83019 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83020 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E32), |
| 83022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83023 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83024 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83025 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83030 | GIR_RootConstrainSelectedInstOperands, |
| 83031 | // GIR_Coverage, 55582, |
| 83032 | GIR_EraseRootFromParent_Done, |
| 83033 | // Label 5612: @211733 |
| 83034 | GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(211778), // Rule ID 55583 // |
| 83035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83036 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83038 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83039 | // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E32), |
| 83041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83042 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83043 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83044 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83049 | GIR_RootConstrainSelectedInstOperands, |
| 83050 | // GIR_Coverage, 55583, |
| 83051 | GIR_EraseRootFromParent_Done, |
| 83052 | // Label 5613: @211778 |
| 83053 | GIM_Reject, |
| 83054 | // Label 5601: @211779 |
| 83055 | GIM_Reject, |
| 83056 | // Label 5493: @211780 |
| 83057 | GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(212569), |
| 83058 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83059 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 83060 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 83061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83062 | GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(211875), // Rule ID 55782 // |
| 83063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83064 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83065 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83066 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83067 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83068 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83069 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83070 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83071 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83072 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83073 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83074 | // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 83076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83077 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83078 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83084 | GIR_RootConstrainSelectedInstOperands, |
| 83085 | // GIR_Coverage, 55782, |
| 83086 | GIR_EraseRootFromParent_Done, |
| 83087 | // Label 5615: @211875 |
| 83088 | GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(211952), // Rule ID 55783 // |
| 83089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83090 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83091 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83092 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83093 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83094 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83095 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83096 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83097 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83098 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83099 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83100 | // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 83102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83103 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83104 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83110 | GIR_RootConstrainSelectedInstOperands, |
| 83111 | // GIR_Coverage, 55783, |
| 83112 | GIR_EraseRootFromParent_Done, |
| 83113 | // Label 5616: @211952 |
| 83114 | GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(212029), // Rule ID 72276 // |
| 83115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83117 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83118 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83119 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83120 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83121 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83122 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83123 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83124 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83125 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83126 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 83128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83129 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83131 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83136 | GIR_RootConstrainSelectedInstOperands, |
| 83137 | // GIR_Coverage, 72276, |
| 83138 | GIR_EraseRootFromParent_Done, |
| 83139 | // Label 5617: @212029 |
| 83140 | GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(212106), // Rule ID 72277 // |
| 83141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83144 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83145 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83146 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83147 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83148 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83149 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83150 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83151 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83152 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 83154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83155 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83162 | GIR_RootConstrainSelectedInstOperands, |
| 83163 | // GIR_Coverage, 72277, |
| 83164 | GIR_EraseRootFromParent_Done, |
| 83165 | // Label 5618: @212106 |
| 83166 | GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(212168), // Rule ID 55786 // |
| 83167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83170 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83171 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83172 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83173 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83174 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83175 | // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 83177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83178 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83180 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83185 | GIR_RootConstrainSelectedInstOperands, |
| 83186 | // GIR_Coverage, 55786, |
| 83187 | GIR_EraseRootFromParent_Done, |
| 83188 | // Label 5619: @212168 |
| 83189 | GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(212230), // Rule ID 55787 // |
| 83190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83191 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83192 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83193 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83194 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83195 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83196 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83197 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83198 | // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 83200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83201 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83203 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83208 | GIR_RootConstrainSelectedInstOperands, |
| 83209 | // GIR_Coverage, 55787, |
| 83210 | GIR_EraseRootFromParent_Done, |
| 83211 | // Label 5620: @212230 |
| 83212 | GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(212292), // Rule ID 72280 // |
| 83213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83215 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83216 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83217 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83218 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83219 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83220 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83221 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 83223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83224 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83226 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83231 | GIR_RootConstrainSelectedInstOperands, |
| 83232 | // GIR_Coverage, 72280, |
| 83233 | GIR_EraseRootFromParent_Done, |
| 83234 | // Label 5621: @212292 |
| 83235 | GIM_Try, /*On fail goto*//*Label 5622*/ GIMT_Encode4(212354), // Rule ID 72281 // |
| 83236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83237 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83238 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83239 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83240 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83241 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83242 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83243 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83244 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 83246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83247 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83249 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83254 | GIR_RootConstrainSelectedInstOperands, |
| 83255 | // GIR_Coverage, 72281, |
| 83256 | GIR_EraseRootFromParent_Done, |
| 83257 | // Label 5622: @212354 |
| 83258 | GIM_Try, /*On fail goto*//*Label 5623*/ GIMT_Encode4(212416), // Rule ID 55778 // |
| 83259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83261 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 83263 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83265 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83266 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83267 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E64), |
| 83269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83270 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83277 | GIR_RootConstrainSelectedInstOperands, |
| 83278 | // GIR_Coverage, 55778, |
| 83279 | GIR_EraseRootFromParent_Done, |
| 83280 | // Label 5623: @212416 |
| 83281 | GIM_Try, /*On fail goto*//*Label 5624*/ GIMT_Encode4(212478), // Rule ID 55779 // |
| 83282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83284 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 83286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 83288 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83289 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83290 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E64), |
| 83292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83293 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83294 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83295 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83300 | GIR_RootConstrainSelectedInstOperands, |
| 83301 | // GIR_Coverage, 55779, |
| 83302 | GIR_EraseRootFromParent_Done, |
| 83303 | // Label 5624: @212478 |
| 83304 | GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(212523), // Rule ID 55774 // |
| 83305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83308 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83309 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E64), |
| 83311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83312 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83313 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83314 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83319 | GIR_RootConstrainSelectedInstOperands, |
| 83320 | // GIR_Coverage, 55774, |
| 83321 | GIR_EraseRootFromParent_Done, |
| 83322 | // Label 5625: @212523 |
| 83323 | GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(212568), // Rule ID 55775 // |
| 83324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83326 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83327 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83328 | // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E64), |
| 83330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83331 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83332 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83333 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83338 | GIR_RootConstrainSelectedInstOperands, |
| 83339 | // GIR_Coverage, 55775, |
| 83340 | GIR_EraseRootFromParent_Done, |
| 83341 | // Label 5626: @212568 |
| 83342 | GIM_Reject, |
| 83343 | // Label 5614: @212569 |
| 83344 | GIM_Reject, |
| 83345 | // Label 5494: @212570 |
| 83346 | GIM_Try, /*On fail goto*//*Label 5627*/ GIMT_Encode4(213359), |
| 83347 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83348 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 83349 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 83350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83351 | GIM_Try, /*On fail goto*//*Label 5628*/ GIMT_Encode4(212665), // Rule ID 55526 // |
| 83352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 83353 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83354 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83355 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83356 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83358 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83359 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83360 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83361 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83362 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83363 | // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 83364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 83365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83366 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83373 | GIR_RootConstrainSelectedInstOperands, |
| 83374 | // GIR_Coverage, 55526, |
| 83375 | GIR_EraseRootFromParent_Done, |
| 83376 | // Label 5628: @212665 |
| 83377 | GIM_Try, /*On fail goto*//*Label 5629*/ GIMT_Encode4(212742), // Rule ID 55527 // |
| 83378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 83379 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83380 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83381 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83382 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83383 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83384 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83385 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83386 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83387 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83388 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83389 | // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 83390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 83391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83392 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83399 | GIR_RootConstrainSelectedInstOperands, |
| 83400 | // GIR_Coverage, 55527, |
| 83401 | GIR_EraseRootFromParent_Done, |
| 83402 | // Label 5629: @212742 |
| 83403 | GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(212819), // Rule ID 72052 // |
| 83404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 83405 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83406 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83407 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83408 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83409 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83410 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83411 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83412 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83413 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83414 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83415 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 83416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 83417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83418 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83425 | GIR_RootConstrainSelectedInstOperands, |
| 83426 | // GIR_Coverage, 72052, |
| 83427 | GIR_EraseRootFromParent_Done, |
| 83428 | // Label 5630: @212819 |
| 83429 | GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(212896), // Rule ID 72053 // |
| 83430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 83431 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83433 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83435 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83436 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83437 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83438 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83439 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83440 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83441 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 83442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 83443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83444 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83451 | GIR_RootConstrainSelectedInstOperands, |
| 83452 | // GIR_Coverage, 72053, |
| 83453 | GIR_EraseRootFromParent_Done, |
| 83454 | // Label 5631: @212896 |
| 83455 | GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(212958), // Rule ID 55530 // |
| 83456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 83457 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83458 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83459 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83460 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83462 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83463 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83464 | // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 83465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 83466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83467 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83469 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83474 | GIR_RootConstrainSelectedInstOperands, |
| 83475 | // GIR_Coverage, 55530, |
| 83476 | GIR_EraseRootFromParent_Done, |
| 83477 | // Label 5632: @212958 |
| 83478 | GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(213020), // Rule ID 55531 // |
| 83479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 83480 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83481 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83482 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83483 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83484 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83485 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83486 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83487 | // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 83488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 83489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83490 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83491 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83492 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83497 | GIR_RootConstrainSelectedInstOperands, |
| 83498 | // GIR_Coverage, 55531, |
| 83499 | GIR_EraseRootFromParent_Done, |
| 83500 | // Label 5633: @213020 |
| 83501 | GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(213082), // Rule ID 72056 // |
| 83502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 83503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83504 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83505 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83506 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83507 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83508 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83509 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83510 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 83511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 83512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83513 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83515 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83520 | GIR_RootConstrainSelectedInstOperands, |
| 83521 | // GIR_Coverage, 72056, |
| 83522 | GIR_EraseRootFromParent_Done, |
| 83523 | // Label 5634: @213082 |
| 83524 | GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(213144), // Rule ID 72057 // |
| 83525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 83526 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83527 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83528 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83529 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83530 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83531 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83532 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83533 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 83534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 83535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83536 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83538 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83543 | GIR_RootConstrainSelectedInstOperands, |
| 83544 | // GIR_Coverage, 72057, |
| 83545 | GIR_EraseRootFromParent_Done, |
| 83546 | // Label 5635: @213144 |
| 83547 | GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(213206), // Rule ID 55522 // |
| 83548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 83549 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83550 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83551 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 83552 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83553 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83554 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83555 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83556 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 83557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E16), |
| 83558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83559 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83566 | GIR_RootConstrainSelectedInstOperands, |
| 83567 | // GIR_Coverage, 55522, |
| 83568 | GIR_EraseRootFromParent_Done, |
| 83569 | // Label 5636: @213206 |
| 83570 | GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(213268), // Rule ID 55523 // |
| 83571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 83572 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83574 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 83575 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83576 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 83577 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83578 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83579 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 83580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E16), |
| 83581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83582 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83583 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83589 | GIR_RootConstrainSelectedInstOperands, |
| 83590 | // GIR_Coverage, 55523, |
| 83591 | GIR_EraseRootFromParent_Done, |
| 83592 | // Label 5637: @213268 |
| 83593 | GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(213313), // Rule ID 55518 // |
| 83594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 83595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83596 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83597 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83598 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 83599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E16), |
| 83600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83601 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83602 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83603 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83608 | GIR_RootConstrainSelectedInstOperands, |
| 83609 | // GIR_Coverage, 55518, |
| 83610 | GIR_EraseRootFromParent_Done, |
| 83611 | // Label 5638: @213313 |
| 83612 | GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(213358), // Rule ID 55519 // |
| 83613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 83614 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83615 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83616 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83617 | // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 83618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E16), |
| 83619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83620 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83621 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83622 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 83626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83627 | GIR_RootConstrainSelectedInstOperands, |
| 83628 | // GIR_Coverage, 55519, |
| 83629 | GIR_EraseRootFromParent_Done, |
| 83630 | // Label 5639: @213358 |
| 83631 | GIM_Reject, |
| 83632 | // Label 5627: @213359 |
| 83633 | GIM_Reject, |
| 83634 | // Label 5495: @213360 |
| 83635 | GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(214149), |
| 83636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 83638 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 83639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83640 | GIM_Try, /*On fail goto*//*Label 5641*/ GIMT_Encode4(213455), // Rule ID 55718 // |
| 83641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83642 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83643 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83644 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83645 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83646 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83647 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83648 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83649 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83650 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83651 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83652 | // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 83654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83655 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83662 | GIR_RootConstrainSelectedInstOperands, |
| 83663 | // GIR_Coverage, 55718, |
| 83664 | GIR_EraseRootFromParent_Done, |
| 83665 | // Label 5641: @213455 |
| 83666 | GIM_Try, /*On fail goto*//*Label 5642*/ GIMT_Encode4(213532), // Rule ID 55719 // |
| 83667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83668 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83669 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83670 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83671 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83672 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83673 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83674 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83675 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83676 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83677 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83678 | // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 83680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83681 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83688 | GIR_RootConstrainSelectedInstOperands, |
| 83689 | // GIR_Coverage, 55719, |
| 83690 | GIR_EraseRootFromParent_Done, |
| 83691 | // Label 5642: @213532 |
| 83692 | GIM_Try, /*On fail goto*//*Label 5643*/ GIMT_Encode4(213609), // Rule ID 72220 // |
| 83693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83695 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83696 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83697 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83698 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83699 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83700 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83701 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83702 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83703 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83704 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 83706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83707 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83714 | GIR_RootConstrainSelectedInstOperands, |
| 83715 | // GIR_Coverage, 72220, |
| 83716 | GIR_EraseRootFromParent_Done, |
| 83717 | // Label 5643: @213609 |
| 83718 | GIM_Try, /*On fail goto*//*Label 5644*/ GIMT_Encode4(213686), // Rule ID 72221 // |
| 83719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83720 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83721 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83722 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83723 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83724 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83725 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83726 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83727 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83728 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83729 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83730 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 83732 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83733 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83740 | GIR_RootConstrainSelectedInstOperands, |
| 83741 | // GIR_Coverage, 72221, |
| 83742 | GIR_EraseRootFromParent_Done, |
| 83743 | // Label 5644: @213686 |
| 83744 | GIM_Try, /*On fail goto*//*Label 5645*/ GIMT_Encode4(213748), // Rule ID 55722 // |
| 83745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83746 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83747 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83748 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83749 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83750 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83751 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83752 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83753 | // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 83755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83756 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83758 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83763 | GIR_RootConstrainSelectedInstOperands, |
| 83764 | // GIR_Coverage, 55722, |
| 83765 | GIR_EraseRootFromParent_Done, |
| 83766 | // Label 5645: @213748 |
| 83767 | GIM_Try, /*On fail goto*//*Label 5646*/ GIMT_Encode4(213810), // Rule ID 55723 // |
| 83768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83769 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83770 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83771 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83772 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83774 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83775 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83776 | // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 83778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83779 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83781 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83786 | GIR_RootConstrainSelectedInstOperands, |
| 83787 | // GIR_Coverage, 55723, |
| 83788 | GIR_EraseRootFromParent_Done, |
| 83789 | // Label 5646: @213810 |
| 83790 | GIM_Try, /*On fail goto*//*Label 5647*/ GIMT_Encode4(213872), // Rule ID 72224 // |
| 83791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83792 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83796 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83797 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83798 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83799 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 83801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83802 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83804 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83809 | GIR_RootConstrainSelectedInstOperands, |
| 83810 | // GIR_Coverage, 72224, |
| 83811 | GIR_EraseRootFromParent_Done, |
| 83812 | // Label 5647: @213872 |
| 83813 | GIM_Try, /*On fail goto*//*Label 5648*/ GIMT_Encode4(213934), // Rule ID 72225 // |
| 83814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83816 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83817 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83818 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83819 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83820 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83821 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83822 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 83824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83825 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83827 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83832 | GIR_RootConstrainSelectedInstOperands, |
| 83833 | // GIR_Coverage, 72225, |
| 83834 | GIR_EraseRootFromParent_Done, |
| 83835 | // Label 5648: @213934 |
| 83836 | GIM_Try, /*On fail goto*//*Label 5649*/ GIMT_Encode4(213996), // Rule ID 55714 // |
| 83837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83838 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83839 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83840 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 83841 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83842 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83843 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83844 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83845 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E32), |
| 83847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83848 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83849 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83855 | GIR_RootConstrainSelectedInstOperands, |
| 83856 | // GIR_Coverage, 55714, |
| 83857 | GIR_EraseRootFromParent_Done, |
| 83858 | // Label 5649: @213996 |
| 83859 | GIM_Try, /*On fail goto*//*Label 5650*/ GIMT_Encode4(214058), // Rule ID 55715 // |
| 83860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83862 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83863 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 83864 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83865 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 83866 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83867 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 83868 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E32), |
| 83870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83871 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83872 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 83874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83878 | GIR_RootConstrainSelectedInstOperands, |
| 83879 | // GIR_Coverage, 55715, |
| 83880 | GIR_EraseRootFromParent_Done, |
| 83881 | // Label 5650: @214058 |
| 83882 | GIM_Try, /*On fail goto*//*Label 5651*/ GIMT_Encode4(214103), // Rule ID 55710 // |
| 83883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 83884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83885 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83886 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83887 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 83888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E32), |
| 83889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83890 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83891 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83892 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83897 | GIR_RootConstrainSelectedInstOperands, |
| 83898 | // GIR_Coverage, 55710, |
| 83899 | GIR_EraseRootFromParent_Done, |
| 83900 | // Label 5651: @214103 |
| 83901 | GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(214148), // Rule ID 55711 // |
| 83902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 83903 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83904 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83905 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 83906 | // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 83907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E32), |
| 83908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83909 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83910 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 83911 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 83912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 83915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83916 | GIR_RootConstrainSelectedInstOperands, |
| 83917 | // GIR_Coverage, 55711, |
| 83918 | GIR_EraseRootFromParent_Done, |
| 83919 | // Label 5652: @214148 |
| 83920 | GIM_Reject, |
| 83921 | // Label 5640: @214149 |
| 83922 | GIM_Reject, |
| 83923 | // Label 5496: @214150 |
| 83924 | GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(214939), |
| 83925 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83926 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 83927 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 83928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83929 | GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(214245), // Rule ID 56230 // |
| 83930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83932 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83934 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83935 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83936 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83937 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83938 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83939 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83940 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83941 | // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 83943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83944 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83951 | GIR_RootConstrainSelectedInstOperands, |
| 83952 | // GIR_Coverage, 56230, |
| 83953 | GIR_EraseRootFromParent_Done, |
| 83954 | // Label 5654: @214245 |
| 83955 | GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(214322), // Rule ID 56231 // |
| 83956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 83957 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 83958 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83959 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83960 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83962 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83963 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83964 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83965 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83966 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83967 | // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 83968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 83969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83970 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 83971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 83974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 83975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 83976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 83977 | GIR_RootConstrainSelectedInstOperands, |
| 83978 | // GIR_Coverage, 56231, |
| 83979 | GIR_EraseRootFromParent_Done, |
| 83980 | // Label 5655: @214322 |
| 83981 | GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(214399), // Rule ID 72668 // |
| 83982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 83983 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83984 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 83985 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83986 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83987 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83988 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 83989 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 83990 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 83991 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 83992 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 83993 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 83994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 83995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 83996 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 83997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 83998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 83999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84003 | GIR_RootConstrainSelectedInstOperands, |
| 84004 | // GIR_Coverage, 72668, |
| 84005 | GIR_EraseRootFromParent_Done, |
| 84006 | // Label 5656: @214399 |
| 84007 | GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(214476), // Rule ID 72669 // |
| 84008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84011 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84012 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84013 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84014 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84015 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84016 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84017 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84018 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84019 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 84021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84022 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84029 | GIR_RootConstrainSelectedInstOperands, |
| 84030 | // GIR_Coverage, 72669, |
| 84031 | GIR_EraseRootFromParent_Done, |
| 84032 | // Label 5657: @214476 |
| 84033 | GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(214538), // Rule ID 56234 // |
| 84034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84036 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84037 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84038 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84040 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84041 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84042 | // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 84044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84045 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84047 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84052 | GIR_RootConstrainSelectedInstOperands, |
| 84053 | // GIR_Coverage, 56234, |
| 84054 | GIR_EraseRootFromParent_Done, |
| 84055 | // Label 5658: @214538 |
| 84056 | GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(214600), // Rule ID 56235 // |
| 84057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84058 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84059 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84060 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84061 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84062 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84063 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84064 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84065 | // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 84067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84068 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84070 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84075 | GIR_RootConstrainSelectedInstOperands, |
| 84076 | // GIR_Coverage, 56235, |
| 84077 | GIR_EraseRootFromParent_Done, |
| 84078 | // Label 5659: @214600 |
| 84079 | GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(214662), // Rule ID 72672 // |
| 84080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84081 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84082 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84083 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84084 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84085 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84086 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84087 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84088 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 84090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84091 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84093 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84098 | GIR_RootConstrainSelectedInstOperands, |
| 84099 | // GIR_Coverage, 72672, |
| 84100 | GIR_EraseRootFromParent_Done, |
| 84101 | // Label 5660: @214662 |
| 84102 | GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(214724), // Rule ID 72673 // |
| 84103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84106 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84107 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84108 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84109 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84110 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84111 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 84113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84114 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84116 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84121 | GIR_RootConstrainSelectedInstOperands, |
| 84122 | // GIR_Coverage, 72673, |
| 84123 | GIR_EraseRootFromParent_Done, |
| 84124 | // Label 5661: @214724 |
| 84125 | GIM_Try, /*On fail goto*//*Label 5662*/ GIMT_Encode4(214786), // Rule ID 56226 // |
| 84126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84128 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84129 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84130 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84131 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84132 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84133 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84134 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E64), |
| 84136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84137 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84138 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 84140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84144 | GIR_RootConstrainSelectedInstOperands, |
| 84145 | // GIR_Coverage, 56226, |
| 84146 | GIR_EraseRootFromParent_Done, |
| 84147 | // Label 5662: @214786 |
| 84148 | GIM_Try, /*On fail goto*//*Label 5663*/ GIMT_Encode4(214848), // Rule ID 56227 // |
| 84149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84151 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84153 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 84155 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84156 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84157 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E64), |
| 84159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84160 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84161 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 84163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84167 | GIR_RootConstrainSelectedInstOperands, |
| 84168 | // GIR_Coverage, 56227, |
| 84169 | GIR_EraseRootFromParent_Done, |
| 84170 | // Label 5663: @214848 |
| 84171 | GIM_Try, /*On fail goto*//*Label 5664*/ GIMT_Encode4(214893), // Rule ID 56222 // |
| 84172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84174 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84175 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84176 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E64), |
| 84178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84179 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84180 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84181 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84186 | GIR_RootConstrainSelectedInstOperands, |
| 84187 | // GIR_Coverage, 56222, |
| 84188 | GIR_EraseRootFromParent_Done, |
| 84189 | // Label 5664: @214893 |
| 84190 | GIM_Try, /*On fail goto*//*Label 5665*/ GIMT_Encode4(214938), // Rule ID 56223 // |
| 84191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84192 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84193 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84194 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84195 | // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E64), |
| 84197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84198 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84199 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84200 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84205 | GIR_RootConstrainSelectedInstOperands, |
| 84206 | // GIR_Coverage, 56223, |
| 84207 | GIR_EraseRootFromParent_Done, |
| 84208 | // Label 5665: @214938 |
| 84209 | GIM_Reject, |
| 84210 | // Label 5653: @214939 |
| 84211 | GIM_Reject, |
| 84212 | // Label 5497: @214940 |
| 84213 | GIM_Try, /*On fail goto*//*Label 5666*/ GIMT_Encode4(215729), |
| 84214 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84215 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 84216 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 84217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84218 | GIM_Try, /*On fail goto*//*Label 5667*/ GIMT_Encode4(215035), // Rule ID 55654 // |
| 84219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 84220 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84221 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84222 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84223 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84224 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84225 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84226 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84227 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84228 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84229 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84230 | // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 84231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 84232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84233 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84234 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84240 | GIR_RootConstrainSelectedInstOperands, |
| 84241 | // GIR_Coverage, 55654, |
| 84242 | GIR_EraseRootFromParent_Done, |
| 84243 | // Label 5667: @215035 |
| 84244 | GIM_Try, /*On fail goto*//*Label 5668*/ GIMT_Encode4(215112), // Rule ID 55655 // |
| 84245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 84246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84247 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84249 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84250 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84251 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84252 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84253 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84254 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84255 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84256 | // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 84257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 84258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84259 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84266 | GIR_RootConstrainSelectedInstOperands, |
| 84267 | // GIR_Coverage, 55655, |
| 84268 | GIR_EraseRootFromParent_Done, |
| 84269 | // Label 5668: @215112 |
| 84270 | GIM_Try, /*On fail goto*//*Label 5669*/ GIMT_Encode4(215189), // Rule ID 72164 // |
| 84271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 84272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84273 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84274 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84275 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84276 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84277 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84278 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84279 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84280 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84281 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84282 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 84283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 84284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84285 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84292 | GIR_RootConstrainSelectedInstOperands, |
| 84293 | // GIR_Coverage, 72164, |
| 84294 | GIR_EraseRootFromParent_Done, |
| 84295 | // Label 5669: @215189 |
| 84296 | GIM_Try, /*On fail goto*//*Label 5670*/ GIMT_Encode4(215266), // Rule ID 72165 // |
| 84297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 84298 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84299 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84300 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84301 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84302 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84303 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84304 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84305 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84306 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84307 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84308 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 84309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 84310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84311 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84318 | GIR_RootConstrainSelectedInstOperands, |
| 84319 | // GIR_Coverage, 72165, |
| 84320 | GIR_EraseRootFromParent_Done, |
| 84321 | // Label 5670: @215266 |
| 84322 | GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(215328), // Rule ID 55658 // |
| 84323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 84324 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84325 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84326 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84327 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84328 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84329 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84330 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84331 | // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 84332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 84333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84334 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84336 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84341 | GIR_RootConstrainSelectedInstOperands, |
| 84342 | // GIR_Coverage, 55658, |
| 84343 | GIR_EraseRootFromParent_Done, |
| 84344 | // Label 5671: @215328 |
| 84345 | GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(215390), // Rule ID 55659 // |
| 84346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 84347 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84348 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84349 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84350 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84351 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84352 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84353 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84354 | // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 84355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 84356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84357 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84359 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84364 | GIR_RootConstrainSelectedInstOperands, |
| 84365 | // GIR_Coverage, 55659, |
| 84366 | GIR_EraseRootFromParent_Done, |
| 84367 | // Label 5672: @215390 |
| 84368 | GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(215452), // Rule ID 72168 // |
| 84369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 84370 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84371 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84372 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84373 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84374 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84375 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84376 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84377 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 84378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 84379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84380 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84382 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84387 | GIR_RootConstrainSelectedInstOperands, |
| 84388 | // GIR_Coverage, 72168, |
| 84389 | GIR_EraseRootFromParent_Done, |
| 84390 | // Label 5673: @215452 |
| 84391 | GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(215514), // Rule ID 72169 // |
| 84392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 84393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84397 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84398 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84399 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84400 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 84401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 84402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84403 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84405 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84410 | GIR_RootConstrainSelectedInstOperands, |
| 84411 | // GIR_Coverage, 72169, |
| 84412 | GIR_EraseRootFromParent_Done, |
| 84413 | // Label 5674: @215514 |
| 84414 | GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(215576), // Rule ID 55650 // |
| 84415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 84416 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84417 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84418 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84419 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84420 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84421 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84422 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84423 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 84424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E16), |
| 84425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84426 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84427 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 84429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84433 | GIR_RootConstrainSelectedInstOperands, |
| 84434 | // GIR_Coverage, 55650, |
| 84435 | GIR_EraseRootFromParent_Done, |
| 84436 | // Label 5675: @215576 |
| 84437 | GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(215638), // Rule ID 55651 // |
| 84438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 84439 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84440 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84441 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84442 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84443 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 84444 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84445 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84446 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 84447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E16), |
| 84448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84449 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84450 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 84452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84456 | GIR_RootConstrainSelectedInstOperands, |
| 84457 | // GIR_Coverage, 55651, |
| 84458 | GIR_EraseRootFromParent_Done, |
| 84459 | // Label 5676: @215638 |
| 84460 | GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(215683), // Rule ID 55646 // |
| 84461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 84462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84464 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84465 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 84466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E16), |
| 84467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84468 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84469 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84470 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84475 | GIR_RootConstrainSelectedInstOperands, |
| 84476 | // GIR_Coverage, 55646, |
| 84477 | GIR_EraseRootFromParent_Done, |
| 84478 | // Label 5677: @215683 |
| 84479 | GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(215728), // Rule ID 55647 // |
| 84480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 84481 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84482 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84483 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 84484 | // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 84485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E16), |
| 84486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84487 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84488 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84489 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 84493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84494 | GIR_RootConstrainSelectedInstOperands, |
| 84495 | // GIR_Coverage, 55647, |
| 84496 | GIR_EraseRootFromParent_Done, |
| 84497 | // Label 5678: @215728 |
| 84498 | GIM_Reject, |
| 84499 | // Label 5666: @215729 |
| 84500 | GIM_Reject, |
| 84501 | // Label 5498: @215730 |
| 84502 | GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(216519), |
| 84503 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 84505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 84506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84507 | GIM_Try, /*On fail goto*//*Label 5680*/ GIMT_Encode4(215825), // Rule ID 56038 // |
| 84508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 84509 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84510 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84511 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84512 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84513 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84514 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84515 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84516 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84517 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84518 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84519 | // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 84520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 84521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84522 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84524 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84529 | GIR_RootConstrainSelectedInstOperands, |
| 84530 | // GIR_Coverage, 56038, |
| 84531 | GIR_EraseRootFromParent_Done, |
| 84532 | // Label 5680: @215825 |
| 84533 | GIM_Try, /*On fail goto*//*Label 5681*/ GIMT_Encode4(215902), // Rule ID 56039 // |
| 84534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 84535 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84536 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84537 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84538 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84540 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84541 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84542 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84543 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84544 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84545 | // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 84546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 84547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84548 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84555 | GIR_RootConstrainSelectedInstOperands, |
| 84556 | // GIR_Coverage, 56039, |
| 84557 | GIR_EraseRootFromParent_Done, |
| 84558 | // Label 5681: @215902 |
| 84559 | GIM_Try, /*On fail goto*//*Label 5682*/ GIMT_Encode4(215979), // Rule ID 72500 // |
| 84560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 84561 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84562 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84563 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84564 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84565 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84566 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84567 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84568 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84569 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84570 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84571 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 84572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 84573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84574 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84581 | GIR_RootConstrainSelectedInstOperands, |
| 84582 | // GIR_Coverage, 72500, |
| 84583 | GIR_EraseRootFromParent_Done, |
| 84584 | // Label 5682: @215979 |
| 84585 | GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(216056), // Rule ID 72501 // |
| 84586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 84587 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84589 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84590 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84591 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84592 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84593 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84594 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84595 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84596 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84597 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 84598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 84599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84600 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84607 | GIR_RootConstrainSelectedInstOperands, |
| 84608 | // GIR_Coverage, 72501, |
| 84609 | GIR_EraseRootFromParent_Done, |
| 84610 | // Label 5683: @216056 |
| 84611 | GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(216118), // Rule ID 56042 // |
| 84612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 84613 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84614 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84615 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84616 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84618 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84619 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84620 | // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 84621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 84622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84623 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84625 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84630 | GIR_RootConstrainSelectedInstOperands, |
| 84631 | // GIR_Coverage, 56042, |
| 84632 | GIR_EraseRootFromParent_Done, |
| 84633 | // Label 5684: @216118 |
| 84634 | GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(216180), // Rule ID 56043 // |
| 84635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 84636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84639 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84640 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84641 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84642 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84643 | // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 84644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 84645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84646 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84648 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84653 | GIR_RootConstrainSelectedInstOperands, |
| 84654 | // GIR_Coverage, 56043, |
| 84655 | GIR_EraseRootFromParent_Done, |
| 84656 | // Label 5685: @216180 |
| 84657 | GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(216242), // Rule ID 72504 // |
| 84658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 84659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84661 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84662 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84663 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84664 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84665 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84666 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 84667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 84668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84669 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84671 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84676 | GIR_RootConstrainSelectedInstOperands, |
| 84677 | // GIR_Coverage, 72504, |
| 84678 | GIR_EraseRootFromParent_Done, |
| 84679 | // Label 5686: @216242 |
| 84680 | GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(216304), // Rule ID 72505 // |
| 84681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 84682 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84683 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84684 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84685 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84686 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84687 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84688 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84689 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 84690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 84691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84692 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84694 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84699 | GIR_RootConstrainSelectedInstOperands, |
| 84700 | // GIR_Coverage, 72505, |
| 84701 | GIR_EraseRootFromParent_Done, |
| 84702 | // Label 5687: @216304 |
| 84703 | GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(216366), // Rule ID 56034 // |
| 84704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 84705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84706 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84708 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84709 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84710 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84711 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84712 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 84713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E32), |
| 84714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84715 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84716 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 84718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84722 | GIR_RootConstrainSelectedInstOperands, |
| 84723 | // GIR_Coverage, 56034, |
| 84724 | GIR_EraseRootFromParent_Done, |
| 84725 | // Label 5688: @216366 |
| 84726 | GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(216428), // Rule ID 56035 // |
| 84727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 84728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84730 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84731 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84732 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 84733 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84734 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84735 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 84736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E32), |
| 84737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84738 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84739 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 84741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84745 | GIR_RootConstrainSelectedInstOperands, |
| 84746 | // GIR_Coverage, 56035, |
| 84747 | GIR_EraseRootFromParent_Done, |
| 84748 | // Label 5689: @216428 |
| 84749 | GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(216473), // Rule ID 56030 // |
| 84750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 84751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84752 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84753 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84754 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 84755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E32), |
| 84756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84757 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84758 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84759 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84764 | GIR_RootConstrainSelectedInstOperands, |
| 84765 | // GIR_Coverage, 56030, |
| 84766 | GIR_EraseRootFromParent_Done, |
| 84767 | // Label 5690: @216473 |
| 84768 | GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(216518), // Rule ID 56031 // |
| 84769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 84770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84771 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84772 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 84773 | // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 84774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E32), |
| 84775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84776 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84777 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 84778 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 84782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84783 | GIR_RootConstrainSelectedInstOperands, |
| 84784 | // GIR_Coverage, 56031, |
| 84785 | GIR_EraseRootFromParent_Done, |
| 84786 | // Label 5691: @216518 |
| 84787 | GIM_Reject, |
| 84788 | // Label 5679: @216519 |
| 84789 | GIM_Reject, |
| 84790 | // Label 5499: @216520 |
| 84791 | GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(217309), |
| 84792 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84793 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 84794 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 84795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84796 | GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(216615), // Rule ID 56294 // |
| 84797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84801 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84802 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84803 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84804 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84805 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84806 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84807 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84808 | // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 84810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84811 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84818 | GIR_RootConstrainSelectedInstOperands, |
| 84819 | // GIR_Coverage, 56294, |
| 84820 | GIR_EraseRootFromParent_Done, |
| 84821 | // Label 5693: @216615 |
| 84822 | GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(216692), // Rule ID 56295 // |
| 84823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84825 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84827 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84828 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84829 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84830 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84831 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84832 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84833 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84834 | // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 84836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84837 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84844 | GIR_RootConstrainSelectedInstOperands, |
| 84845 | // GIR_Coverage, 56295, |
| 84846 | GIR_EraseRootFromParent_Done, |
| 84847 | // Label 5694: @216692 |
| 84848 | GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(216769), // Rule ID 72724 // |
| 84849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84851 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84852 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84853 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84854 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84855 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84856 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84857 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84858 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84859 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84860 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 84862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84863 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84864 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84870 | GIR_RootConstrainSelectedInstOperands, |
| 84871 | // GIR_Coverage, 72724, |
| 84872 | GIR_EraseRootFromParent_Done, |
| 84873 | // Label 5695: @216769 |
| 84874 | GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(216846), // Rule ID 72725 // |
| 84875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84877 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84878 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84879 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84880 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84881 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 84882 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84883 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84884 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84885 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 84886 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 84888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84889 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 84892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84896 | GIR_RootConstrainSelectedInstOperands, |
| 84897 | // GIR_Coverage, 72725, |
| 84898 | GIR_EraseRootFromParent_Done, |
| 84899 | // Label 5696: @216846 |
| 84900 | GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(216908), // Rule ID 56298 // |
| 84901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84902 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84903 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84904 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84905 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84906 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84907 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84908 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84909 | // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 84911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84912 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84914 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84919 | GIR_RootConstrainSelectedInstOperands, |
| 84920 | // GIR_Coverage, 56298, |
| 84921 | GIR_EraseRootFromParent_Done, |
| 84922 | // Label 5697: @216908 |
| 84923 | GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(216970), // Rule ID 56299 // |
| 84924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84926 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84928 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84930 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84931 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84932 | // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 84934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84935 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 84936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84937 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84942 | GIR_RootConstrainSelectedInstOperands, |
| 84943 | // GIR_Coverage, 56299, |
| 84944 | GIR_EraseRootFromParent_Done, |
| 84945 | // Label 5698: @216970 |
| 84946 | GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(217032), // Rule ID 72728 // |
| 84947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84950 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84951 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84952 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84953 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84954 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84955 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 84956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 84957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84958 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84960 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84965 | GIR_RootConstrainSelectedInstOperands, |
| 84966 | // GIR_Coverage, 72728, |
| 84967 | GIR_EraseRootFromParent_Done, |
| 84968 | // Label 5699: @217032 |
| 84969 | GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(217094), // Rule ID 72729 // |
| 84970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 84971 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84972 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84973 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84974 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84975 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84976 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84977 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84978 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 84979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 84980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 84981 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 84982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 84983 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 84984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 84985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 84986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 84987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84988 | GIR_RootConstrainSelectedInstOperands, |
| 84989 | // GIR_Coverage, 72729, |
| 84990 | GIR_EraseRootFromParent_Done, |
| 84991 | // Label 5700: @217094 |
| 84992 | GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(217156), // Rule ID 56290 // |
| 84993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 84994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 84996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 84997 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 84998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 84999 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85000 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85001 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E64), |
| 85003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85004 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85011 | GIR_RootConstrainSelectedInstOperands, |
| 85012 | // GIR_Coverage, 56290, |
| 85013 | GIR_EraseRootFromParent_Done, |
| 85014 | // Label 5701: @217156 |
| 85015 | GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(217218), // Rule ID 56291 // |
| 85016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85017 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85018 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85019 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85020 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85021 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 85022 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85023 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85024 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E64), |
| 85026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85027 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85028 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85034 | GIR_RootConstrainSelectedInstOperands, |
| 85035 | // GIR_Coverage, 56291, |
| 85036 | GIR_EraseRootFromParent_Done, |
| 85037 | // Label 5702: @217218 |
| 85038 | GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(217263), // Rule ID 56286 // |
| 85039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85040 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85041 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85042 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85043 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E64), |
| 85045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85046 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85047 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85048 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85053 | GIR_RootConstrainSelectedInstOperands, |
| 85054 | // GIR_Coverage, 56286, |
| 85055 | GIR_EraseRootFromParent_Done, |
| 85056 | // Label 5703: @217263 |
| 85057 | GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(217308), // Rule ID 56287 // |
| 85058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85059 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85060 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85061 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85062 | // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E64), |
| 85064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85065 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85066 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85067 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85072 | GIR_RootConstrainSelectedInstOperands, |
| 85073 | // GIR_Coverage, 56287, |
| 85074 | GIR_EraseRootFromParent_Done, |
| 85075 | // Label 5704: @217308 |
| 85076 | GIM_Reject, |
| 85077 | // Label 5692: @217309 |
| 85078 | GIM_Reject, |
| 85079 | // Label 5500: @217310 |
| 85080 | GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(218099), |
| 85081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85082 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 85083 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 85084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85085 | GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(217405), // Rule ID 55846 // |
| 85086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85087 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85088 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85089 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85090 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85091 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85092 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85093 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85094 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85095 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85096 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85097 | // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 85099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85100 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85107 | GIR_RootConstrainSelectedInstOperands, |
| 85108 | // GIR_Coverage, 55846, |
| 85109 | GIR_EraseRootFromParent_Done, |
| 85110 | // Label 5706: @217405 |
| 85111 | GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(217482), // Rule ID 55847 // |
| 85112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85113 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85114 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85115 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85116 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85117 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85118 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85119 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85120 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85121 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85122 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85123 | // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 85125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85126 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85127 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85133 | GIR_RootConstrainSelectedInstOperands, |
| 85134 | // GIR_Coverage, 55847, |
| 85135 | GIR_EraseRootFromParent_Done, |
| 85136 | // Label 5707: @217482 |
| 85137 | GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(217559), // Rule ID 72332 // |
| 85138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85141 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85143 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85144 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85145 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85146 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85147 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85148 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85149 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 85151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85152 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85159 | GIR_RootConstrainSelectedInstOperands, |
| 85160 | // GIR_Coverage, 72332, |
| 85161 | GIR_EraseRootFromParent_Done, |
| 85162 | // Label 5708: @217559 |
| 85163 | GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(217636), // Rule ID 72333 // |
| 85164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85165 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85166 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85167 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85168 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85169 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85170 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85171 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85172 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85173 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85174 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85175 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 85177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85178 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85185 | GIR_RootConstrainSelectedInstOperands, |
| 85186 | // GIR_Coverage, 72333, |
| 85187 | GIR_EraseRootFromParent_Done, |
| 85188 | // Label 5709: @217636 |
| 85189 | GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(217698), // Rule ID 55850 // |
| 85190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85191 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85192 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85193 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85194 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85195 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85196 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85197 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85198 | // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 85200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85201 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85203 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85208 | GIR_RootConstrainSelectedInstOperands, |
| 85209 | // GIR_Coverage, 55850, |
| 85210 | GIR_EraseRootFromParent_Done, |
| 85211 | // Label 5710: @217698 |
| 85212 | GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(217760), // Rule ID 55851 // |
| 85213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85215 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85217 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85218 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85219 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85220 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85221 | // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 85223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85224 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85226 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85231 | GIR_RootConstrainSelectedInstOperands, |
| 85232 | // GIR_Coverage, 55851, |
| 85233 | GIR_EraseRootFromParent_Done, |
| 85234 | // Label 5711: @217760 |
| 85235 | GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(217822), // Rule ID 72336 // |
| 85236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85237 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85238 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85239 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85240 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85241 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85242 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85243 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85244 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 85246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85247 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85249 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85254 | GIR_RootConstrainSelectedInstOperands, |
| 85255 | // GIR_Coverage, 72336, |
| 85256 | GIR_EraseRootFromParent_Done, |
| 85257 | // Label 5712: @217822 |
| 85258 | GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(217884), // Rule ID 72337 // |
| 85259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85262 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85264 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85265 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85266 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85267 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 85269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85270 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85272 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85277 | GIR_RootConstrainSelectedInstOperands, |
| 85278 | // GIR_Coverage, 72337, |
| 85279 | GIR_EraseRootFromParent_Done, |
| 85280 | // Label 5713: @217884 |
| 85281 | GIM_Try, /*On fail goto*//*Label 5714*/ GIMT_Encode4(217946), // Rule ID 55842 // |
| 85282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85284 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85288 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85289 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85290 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E16), |
| 85292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85293 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85294 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85295 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85300 | GIR_RootConstrainSelectedInstOperands, |
| 85301 | // GIR_Coverage, 55842, |
| 85302 | GIR_EraseRootFromParent_Done, |
| 85303 | // Label 5714: @217946 |
| 85304 | GIM_Try, /*On fail goto*//*Label 5715*/ GIMT_Encode4(218008), // Rule ID 55843 // |
| 85305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85309 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85310 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 85311 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85312 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85313 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E16), |
| 85315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85316 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85317 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85318 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85323 | GIR_RootConstrainSelectedInstOperands, |
| 85324 | // GIR_Coverage, 55843, |
| 85325 | GIR_EraseRootFromParent_Done, |
| 85326 | // Label 5715: @218008 |
| 85327 | GIM_Try, /*On fail goto*//*Label 5716*/ GIMT_Encode4(218053), // Rule ID 55838 // |
| 85328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85329 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85330 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85331 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85332 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E16), |
| 85334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85335 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85336 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85337 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85342 | GIR_RootConstrainSelectedInstOperands, |
| 85343 | // GIR_Coverage, 55838, |
| 85344 | GIR_EraseRootFromParent_Done, |
| 85345 | // Label 5716: @218053 |
| 85346 | GIM_Try, /*On fail goto*//*Label 5717*/ GIMT_Encode4(218098), // Rule ID 55839 // |
| 85347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85348 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85349 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85350 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 85351 | // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E16), |
| 85353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85354 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85355 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85356 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85361 | GIR_RootConstrainSelectedInstOperands, |
| 85362 | // GIR_Coverage, 55839, |
| 85363 | GIR_EraseRootFromParent_Done, |
| 85364 | // Label 5717: @218098 |
| 85365 | GIM_Reject, |
| 85366 | // Label 5705: @218099 |
| 85367 | GIM_Reject, |
| 85368 | // Label 5501: @218100 |
| 85369 | GIM_Try, /*On fail goto*//*Label 5718*/ GIMT_Encode4(218889), |
| 85370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85371 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 85372 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 85373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85374 | GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(218195), // Rule ID 56102 // |
| 85375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 85376 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85377 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85378 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85379 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85380 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85381 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85382 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85383 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85384 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85385 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85386 | // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 85387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 85388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85389 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85390 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85396 | GIR_RootConstrainSelectedInstOperands, |
| 85397 | // GIR_Coverage, 56102, |
| 85398 | GIR_EraseRootFromParent_Done, |
| 85399 | // Label 5719: @218195 |
| 85400 | GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(218272), // Rule ID 56103 // |
| 85401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 85402 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85403 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85404 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85405 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85406 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85407 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85408 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85409 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85410 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85411 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85412 | // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 85413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 85414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85415 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85422 | GIR_RootConstrainSelectedInstOperands, |
| 85423 | // GIR_Coverage, 56103, |
| 85424 | GIR_EraseRootFromParent_Done, |
| 85425 | // Label 5720: @218272 |
| 85426 | GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(218349), // Rule ID 72556 // |
| 85427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 85428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85429 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85430 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85431 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85432 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85433 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85434 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85435 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85436 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85437 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85438 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 85439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 85440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85441 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85448 | GIR_RootConstrainSelectedInstOperands, |
| 85449 | // GIR_Coverage, 72556, |
| 85450 | GIR_EraseRootFromParent_Done, |
| 85451 | // Label 5721: @218349 |
| 85452 | GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(218426), // Rule ID 72557 // |
| 85453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 85454 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85455 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85456 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85457 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85458 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85459 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85460 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85461 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85462 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85463 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85464 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 85465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 85466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85467 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85474 | GIR_RootConstrainSelectedInstOperands, |
| 85475 | // GIR_Coverage, 72557, |
| 85476 | GIR_EraseRootFromParent_Done, |
| 85477 | // Label 5722: @218426 |
| 85478 | GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(218488), // Rule ID 56106 // |
| 85479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 85480 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85481 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85482 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85483 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85484 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85485 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85486 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85487 | // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 85488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 85489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85490 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85491 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85492 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85497 | GIR_RootConstrainSelectedInstOperands, |
| 85498 | // GIR_Coverage, 56106, |
| 85499 | GIR_EraseRootFromParent_Done, |
| 85500 | // Label 5723: @218488 |
| 85501 | GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(218550), // Rule ID 56107 // |
| 85502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 85503 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85504 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85505 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85506 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85507 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85508 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85509 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85510 | // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 85511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 85512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85513 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85515 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85520 | GIR_RootConstrainSelectedInstOperands, |
| 85521 | // GIR_Coverage, 56107, |
| 85522 | GIR_EraseRootFromParent_Done, |
| 85523 | // Label 5724: @218550 |
| 85524 | GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(218612), // Rule ID 72560 // |
| 85525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 85526 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85527 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85528 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85529 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85530 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85531 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85532 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85533 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 85534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 85535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85536 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85538 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85543 | GIR_RootConstrainSelectedInstOperands, |
| 85544 | // GIR_Coverage, 72560, |
| 85545 | GIR_EraseRootFromParent_Done, |
| 85546 | // Label 5725: @218612 |
| 85547 | GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(218674), // Rule ID 72561 // |
| 85548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 85549 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85550 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85551 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85552 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85553 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85554 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85555 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85556 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 85557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 85558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85559 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85560 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85561 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85566 | GIR_RootConstrainSelectedInstOperands, |
| 85567 | // GIR_Coverage, 72561, |
| 85568 | GIR_EraseRootFromParent_Done, |
| 85569 | // Label 5726: @218674 |
| 85570 | GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(218736), // Rule ID 56098 // |
| 85571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 85572 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85574 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85575 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85576 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85577 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85578 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85579 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 85580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E32), |
| 85581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85582 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85583 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85589 | GIR_RootConstrainSelectedInstOperands, |
| 85590 | // GIR_Coverage, 56098, |
| 85591 | GIR_EraseRootFromParent_Done, |
| 85592 | // Label 5727: @218736 |
| 85593 | GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(218798), // Rule ID 56099 // |
| 85594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 85595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85596 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85597 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85598 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85599 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 85600 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85601 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85602 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 85603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E32), |
| 85604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85605 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85606 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85612 | GIR_RootConstrainSelectedInstOperands, |
| 85613 | // GIR_Coverage, 56099, |
| 85614 | GIR_EraseRootFromParent_Done, |
| 85615 | // Label 5728: @218798 |
| 85616 | GIM_Try, /*On fail goto*//*Label 5729*/ GIMT_Encode4(218843), // Rule ID 56094 // |
| 85617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 85618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85619 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85620 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85621 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 85622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E32), |
| 85623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85624 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85625 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85626 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85631 | GIR_RootConstrainSelectedInstOperands, |
| 85632 | // GIR_Coverage, 56094, |
| 85633 | GIR_EraseRootFromParent_Done, |
| 85634 | // Label 5729: @218843 |
| 85635 | GIM_Try, /*On fail goto*//*Label 5730*/ GIMT_Encode4(218888), // Rule ID 56095 // |
| 85636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 85637 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85638 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85639 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85640 | // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 85641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E32), |
| 85642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85643 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85644 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85645 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 85649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85650 | GIR_RootConstrainSelectedInstOperands, |
| 85651 | // GIR_Coverage, 56095, |
| 85652 | GIR_EraseRootFromParent_Done, |
| 85653 | // Label 5730: @218888 |
| 85654 | GIM_Reject, |
| 85655 | // Label 5718: @218889 |
| 85656 | GIM_Reject, |
| 85657 | // Label 5502: @218890 |
| 85658 | GIM_Try, /*On fail goto*//*Label 5731*/ GIMT_Encode4(219679), |
| 85659 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 85661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 85662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85663 | GIM_Try, /*On fail goto*//*Label 5732*/ GIMT_Encode4(218985), // Rule ID 56358 // |
| 85664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85665 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85666 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85667 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85668 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85669 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85670 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85671 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85672 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85673 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85674 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85675 | // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 85677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85678 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85679 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85685 | GIR_RootConstrainSelectedInstOperands, |
| 85686 | // GIR_Coverage, 56358, |
| 85687 | GIR_EraseRootFromParent_Done, |
| 85688 | // Label 5732: @218985 |
| 85689 | GIM_Try, /*On fail goto*//*Label 5733*/ GIMT_Encode4(219062), // Rule ID 56359 // |
| 85690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85691 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85692 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85693 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85694 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85696 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85697 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85698 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85699 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85700 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85701 | // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 85703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85704 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85711 | GIR_RootConstrainSelectedInstOperands, |
| 85712 | // GIR_Coverage, 56359, |
| 85713 | GIR_EraseRootFromParent_Done, |
| 85714 | // Label 5733: @219062 |
| 85715 | GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(219139), // Rule ID 72780 // |
| 85716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85718 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85719 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85720 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85721 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85722 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85723 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85724 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85725 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85726 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85727 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 85729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85730 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85737 | GIR_RootConstrainSelectedInstOperands, |
| 85738 | // GIR_Coverage, 72780, |
| 85739 | GIR_EraseRootFromParent_Done, |
| 85740 | // Label 5734: @219139 |
| 85741 | GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(219216), // Rule ID 72781 // |
| 85742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85743 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85744 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85745 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85746 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85747 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85748 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85749 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85750 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85751 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85752 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85753 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 85755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85756 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85763 | GIR_RootConstrainSelectedInstOperands, |
| 85764 | // GIR_Coverage, 72781, |
| 85765 | GIR_EraseRootFromParent_Done, |
| 85766 | // Label 5735: @219216 |
| 85767 | GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(219278), // Rule ID 56362 // |
| 85768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85769 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85770 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85771 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85772 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85774 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85775 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85776 | // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 85778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85779 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85781 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85786 | GIR_RootConstrainSelectedInstOperands, |
| 85787 | // GIR_Coverage, 56362, |
| 85788 | GIR_EraseRootFromParent_Done, |
| 85789 | // Label 5736: @219278 |
| 85790 | GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(219340), // Rule ID 56363 // |
| 85791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85792 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85793 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85794 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85795 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85796 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85797 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85798 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85799 | // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 85801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85802 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85804 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85809 | GIR_RootConstrainSelectedInstOperands, |
| 85810 | // GIR_Coverage, 56363, |
| 85811 | GIR_EraseRootFromParent_Done, |
| 85812 | // Label 5737: @219340 |
| 85813 | GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(219402), // Rule ID 72784 // |
| 85814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85816 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85817 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85818 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85819 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85820 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85821 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85822 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 85824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85825 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85827 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85832 | GIR_RootConstrainSelectedInstOperands, |
| 85833 | // GIR_Coverage, 72784, |
| 85834 | GIR_EraseRootFromParent_Done, |
| 85835 | // Label 5738: @219402 |
| 85836 | GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(219464), // Rule ID 72785 // |
| 85837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85838 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85839 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85840 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85841 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85842 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85843 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85844 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85845 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 85847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85848 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 85849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85850 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85855 | GIR_RootConstrainSelectedInstOperands, |
| 85856 | // GIR_Coverage, 72785, |
| 85857 | GIR_EraseRootFromParent_Done, |
| 85858 | // Label 5739: @219464 |
| 85859 | GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(219526), // Rule ID 56354 // |
| 85860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85862 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85863 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85864 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85865 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85866 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85867 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85868 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E64), |
| 85870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85871 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85872 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85878 | GIR_RootConstrainSelectedInstOperands, |
| 85879 | // GIR_Coverage, 56354, |
| 85880 | GIR_EraseRootFromParent_Done, |
| 85881 | // Label 5740: @219526 |
| 85882 | GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(219588), // Rule ID 56355 // |
| 85883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85885 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 85887 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 85889 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85890 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85891 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E64), |
| 85893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85894 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85895 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85896 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 85897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85901 | GIR_RootConstrainSelectedInstOperands, |
| 85902 | // GIR_Coverage, 56355, |
| 85903 | GIR_EraseRootFromParent_Done, |
| 85904 | // Label 5741: @219588 |
| 85905 | GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(219633), // Rule ID 56350 // |
| 85906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 85907 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85908 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85909 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85910 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 85911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E64), |
| 85912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85913 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85915 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85920 | GIR_RootConstrainSelectedInstOperands, |
| 85921 | // GIR_Coverage, 56350, |
| 85922 | GIR_EraseRootFromParent_Done, |
| 85923 | // Label 5742: @219633 |
| 85924 | GIM_Try, /*On fail goto*//*Label 5743*/ GIMT_Encode4(219678), // Rule ID 56351 // |
| 85925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 85926 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85928 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 85929 | // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 85930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E64), |
| 85931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85932 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85933 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 85934 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 85935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 85938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85939 | GIR_RootConstrainSelectedInstOperands, |
| 85940 | // GIR_Coverage, 56351, |
| 85941 | GIR_EraseRootFromParent_Done, |
| 85942 | // Label 5743: @219678 |
| 85943 | GIM_Reject, |
| 85944 | // Label 5731: @219679 |
| 85945 | GIM_Reject, |
| 85946 | // Label 5503: @219680 |
| 85947 | GIM_Try, /*On fail goto*//*Label 5744*/ GIMT_Encode4(220469), |
| 85948 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 85949 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 85950 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 85951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85952 | GIM_Try, /*On fail goto*//*Label 5745*/ GIMT_Encode4(219775), // Rule ID 55910 // |
| 85953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 85954 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85955 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85956 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 85957 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85958 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85959 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85960 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85961 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 85962 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85963 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85964 | // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 85965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 85966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85967 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85974 | GIR_RootConstrainSelectedInstOperands, |
| 85975 | // GIR_Coverage, 55910, |
| 85976 | GIR_EraseRootFromParent_Done, |
| 85977 | // Label 5745: @219775 |
| 85978 | GIM_Try, /*On fail goto*//*Label 5746*/ GIMT_Encode4(219852), // Rule ID 55911 // |
| 85979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 85980 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85981 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85982 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 85983 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85985 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 85986 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 85987 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 85988 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 85989 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85990 | // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 85991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 85992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 85993 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 85994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 85995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 85996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 85997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 85998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 85999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86000 | GIR_RootConstrainSelectedInstOperands, |
| 86001 | // GIR_Coverage, 55911, |
| 86002 | GIR_EraseRootFromParent_Done, |
| 86003 | // Label 5746: @219852 |
| 86004 | GIM_Try, /*On fail goto*//*Label 5747*/ GIMT_Encode4(219929), // Rule ID 72388 // |
| 86005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86007 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86008 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86009 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86010 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86011 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86012 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86013 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86014 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86015 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86016 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 86018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86019 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86026 | GIR_RootConstrainSelectedInstOperands, |
| 86027 | // GIR_Coverage, 72388, |
| 86028 | GIR_EraseRootFromParent_Done, |
| 86029 | // Label 5747: @219929 |
| 86030 | GIM_Try, /*On fail goto*//*Label 5748*/ GIMT_Encode4(220006), // Rule ID 72389 // |
| 86031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86032 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86036 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86037 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86038 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86039 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86040 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86041 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86042 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 86044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86045 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86047 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86052 | GIR_RootConstrainSelectedInstOperands, |
| 86053 | // GIR_Coverage, 72389, |
| 86054 | GIR_EraseRootFromParent_Done, |
| 86055 | // Label 5748: @220006 |
| 86056 | GIM_Try, /*On fail goto*//*Label 5749*/ GIMT_Encode4(220068), // Rule ID 55914 // |
| 86057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86058 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86059 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86060 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86061 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86062 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86063 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86064 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86065 | // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 86067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86068 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86070 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86075 | GIR_RootConstrainSelectedInstOperands, |
| 86076 | // GIR_Coverage, 55914, |
| 86077 | GIR_EraseRootFromParent_Done, |
| 86078 | // Label 5749: @220068 |
| 86079 | GIM_Try, /*On fail goto*//*Label 5750*/ GIMT_Encode4(220130), // Rule ID 55915 // |
| 86080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86081 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86082 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86083 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86084 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86085 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86086 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86087 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86088 | // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 86090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86091 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86093 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86098 | GIR_RootConstrainSelectedInstOperands, |
| 86099 | // GIR_Coverage, 55915, |
| 86100 | GIR_EraseRootFromParent_Done, |
| 86101 | // Label 5750: @220130 |
| 86102 | GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(220192), // Rule ID 72392 // |
| 86103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86106 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86107 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86108 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86109 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86110 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86111 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 86113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86114 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86116 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86121 | GIR_RootConstrainSelectedInstOperands, |
| 86122 | // GIR_Coverage, 72392, |
| 86123 | GIR_EraseRootFromParent_Done, |
| 86124 | // Label 5751: @220192 |
| 86125 | GIM_Try, /*On fail goto*//*Label 5752*/ GIMT_Encode4(220254), // Rule ID 72393 // |
| 86126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86128 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86129 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86130 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86131 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86132 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86133 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86134 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 86136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86137 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86139 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86144 | GIR_RootConstrainSelectedInstOperands, |
| 86145 | // GIR_Coverage, 72393, |
| 86146 | GIR_EraseRootFromParent_Done, |
| 86147 | // Label 5752: @220254 |
| 86148 | GIM_Try, /*On fail goto*//*Label 5753*/ GIMT_Encode4(220316), // Rule ID 55906 // |
| 86149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86151 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 86153 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86155 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86156 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86157 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E16), |
| 86159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86160 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86161 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 86163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86167 | GIR_RootConstrainSelectedInstOperands, |
| 86168 | // GIR_Coverage, 55906, |
| 86169 | GIR_EraseRootFromParent_Done, |
| 86170 | // Label 5753: @220316 |
| 86171 | GIM_Try, /*On fail goto*//*Label 5754*/ GIMT_Encode4(220378), // Rule ID 55907 // |
| 86172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86174 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86175 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 86176 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86177 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 86178 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86179 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86180 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E16), |
| 86182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86183 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86184 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 86186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86190 | GIR_RootConstrainSelectedInstOperands, |
| 86191 | // GIR_Coverage, 55907, |
| 86192 | GIR_EraseRootFromParent_Done, |
| 86193 | // Label 5754: @220378 |
| 86194 | GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(220423), // Rule ID 55902 // |
| 86195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86196 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86197 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86198 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86199 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E16), |
| 86201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86202 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86203 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86204 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86209 | GIR_RootConstrainSelectedInstOperands, |
| 86210 | // GIR_Coverage, 55902, |
| 86211 | GIR_EraseRootFromParent_Done, |
| 86212 | // Label 5755: @220423 |
| 86213 | GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(220468), // Rule ID 55903 // |
| 86214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86215 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86216 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86217 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 86218 | // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E16), |
| 86220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86221 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86222 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86223 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86228 | GIR_RootConstrainSelectedInstOperands, |
| 86229 | // GIR_Coverage, 55903, |
| 86230 | GIR_EraseRootFromParent_Done, |
| 86231 | // Label 5756: @220468 |
| 86232 | GIM_Reject, |
| 86233 | // Label 5744: @220469 |
| 86234 | GIM_Reject, |
| 86235 | // Label 5504: @220470 |
| 86236 | GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(221259), |
| 86237 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 86239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 86240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86241 | GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(220565), // Rule ID 56166 // |
| 86242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 86243 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86244 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86245 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86246 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86247 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86248 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86249 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86250 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86251 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86252 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86253 | // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 86254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 86255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86256 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86257 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86263 | GIR_RootConstrainSelectedInstOperands, |
| 86264 | // GIR_Coverage, 56166, |
| 86265 | GIR_EraseRootFromParent_Done, |
| 86266 | // Label 5758: @220565 |
| 86267 | GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(220642), // Rule ID 56167 // |
| 86268 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 86269 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86270 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86271 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86272 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86274 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86275 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86276 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86277 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86278 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86279 | // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 86280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 86281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86282 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86289 | GIR_RootConstrainSelectedInstOperands, |
| 86290 | // GIR_Coverage, 56167, |
| 86291 | GIR_EraseRootFromParent_Done, |
| 86292 | // Label 5759: @220642 |
| 86293 | GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(220719), // Rule ID 72612 // |
| 86294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 86295 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86296 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86297 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86298 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86299 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86300 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86301 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86302 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86303 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86304 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86305 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 86306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 86307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86308 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86315 | GIR_RootConstrainSelectedInstOperands, |
| 86316 | // GIR_Coverage, 72612, |
| 86317 | GIR_EraseRootFromParent_Done, |
| 86318 | // Label 5760: @220719 |
| 86319 | GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(220796), // Rule ID 72613 // |
| 86320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 86321 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86322 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86323 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86324 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86325 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86326 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86327 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86328 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86329 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86330 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86331 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 86332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 86333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86334 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86341 | GIR_RootConstrainSelectedInstOperands, |
| 86342 | // GIR_Coverage, 72613, |
| 86343 | GIR_EraseRootFromParent_Done, |
| 86344 | // Label 5761: @220796 |
| 86345 | GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(220858), // Rule ID 56170 // |
| 86346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 86347 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86348 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86349 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86350 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86351 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86352 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86353 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86354 | // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 86355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 86356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86357 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86359 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86364 | GIR_RootConstrainSelectedInstOperands, |
| 86365 | // GIR_Coverage, 56170, |
| 86366 | GIR_EraseRootFromParent_Done, |
| 86367 | // Label 5762: @220858 |
| 86368 | GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(220920), // Rule ID 56171 // |
| 86369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 86370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86371 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86372 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86373 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86374 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86375 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86376 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86377 | // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 86378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 86379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86380 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86382 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86387 | GIR_RootConstrainSelectedInstOperands, |
| 86388 | // GIR_Coverage, 56171, |
| 86389 | GIR_EraseRootFromParent_Done, |
| 86390 | // Label 5763: @220920 |
| 86391 | GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(220982), // Rule ID 72616 // |
| 86392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 86393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86397 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86398 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86399 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86400 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 86401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 86402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86403 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86405 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86410 | GIR_RootConstrainSelectedInstOperands, |
| 86411 | // GIR_Coverage, 72616, |
| 86412 | GIR_EraseRootFromParent_Done, |
| 86413 | // Label 5764: @220982 |
| 86414 | GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(221044), // Rule ID 72617 // |
| 86415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 86416 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86417 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86418 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86419 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86420 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86421 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86422 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86423 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 86424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 86425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86426 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86428 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86433 | GIR_RootConstrainSelectedInstOperands, |
| 86434 | // GIR_Coverage, 72617, |
| 86435 | GIR_EraseRootFromParent_Done, |
| 86436 | // Label 5765: @221044 |
| 86437 | GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(221106), // Rule ID 56162 // |
| 86438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 86439 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86440 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86441 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 86442 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86443 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86444 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86445 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86446 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 86447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E32), |
| 86448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86449 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86450 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 86452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86456 | GIR_RootConstrainSelectedInstOperands, |
| 86457 | // GIR_Coverage, 56162, |
| 86458 | GIR_EraseRootFromParent_Done, |
| 86459 | // Label 5766: @221106 |
| 86460 | GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(221168), // Rule ID 56163 // |
| 86461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 86462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86464 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 86465 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86466 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 86467 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86468 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86469 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 86470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E32), |
| 86471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86472 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86473 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 86475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86479 | GIR_RootConstrainSelectedInstOperands, |
| 86480 | // GIR_Coverage, 56163, |
| 86481 | GIR_EraseRootFromParent_Done, |
| 86482 | // Label 5767: @221168 |
| 86483 | GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(221213), // Rule ID 56158 // |
| 86484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 86485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86486 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86487 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86488 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 86489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E32), |
| 86490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86491 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86492 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86493 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86498 | GIR_RootConstrainSelectedInstOperands, |
| 86499 | // GIR_Coverage, 56158, |
| 86500 | GIR_EraseRootFromParent_Done, |
| 86501 | // Label 5768: @221213 |
| 86502 | GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(221258), // Rule ID 56159 // |
| 86503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 86504 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86505 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86506 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86507 | // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 86508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E32), |
| 86509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86510 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86511 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86512 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 86516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86517 | GIR_RootConstrainSelectedInstOperands, |
| 86518 | // GIR_Coverage, 56159, |
| 86519 | GIR_EraseRootFromParent_Done, |
| 86520 | // Label 5769: @221258 |
| 86521 | GIM_Reject, |
| 86522 | // Label 5757: @221259 |
| 86523 | GIM_Reject, |
| 86524 | // Label 5505: @221260 |
| 86525 | GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(222049), |
| 86526 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86527 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 86528 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 86529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86530 | GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(221355), // Rule ID 55974 // |
| 86531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86532 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86533 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86534 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86535 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86536 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86537 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86538 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86539 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86540 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86541 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86542 | // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 86544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86545 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86547 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86552 | GIR_RootConstrainSelectedInstOperands, |
| 86553 | // GIR_Coverage, 55974, |
| 86554 | GIR_EraseRootFromParent_Done, |
| 86555 | // Label 5771: @221355 |
| 86556 | GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(221432), // Rule ID 55975 // |
| 86557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86558 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86559 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86560 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86561 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86563 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86564 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86565 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86566 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86567 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86568 | // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 86570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86571 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86578 | GIR_RootConstrainSelectedInstOperands, |
| 86579 | // GIR_Coverage, 55975, |
| 86580 | GIR_EraseRootFromParent_Done, |
| 86581 | // Label 5772: @221432 |
| 86582 | GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(221509), // Rule ID 72444 // |
| 86583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86585 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86586 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86587 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86588 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86589 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86590 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86591 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86592 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86593 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86594 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 86596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86597 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86598 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86599 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86604 | GIR_RootConstrainSelectedInstOperands, |
| 86605 | // GIR_Coverage, 72444, |
| 86606 | GIR_EraseRootFromParent_Done, |
| 86607 | // Label 5773: @221509 |
| 86608 | GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(221586), // Rule ID 72445 // |
| 86609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86610 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86611 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86612 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86613 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86614 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86615 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 86616 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86617 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86618 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86619 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 86620 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 86622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86623 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 86626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86630 | GIR_RootConstrainSelectedInstOperands, |
| 86631 | // GIR_Coverage, 72445, |
| 86632 | GIR_EraseRootFromParent_Done, |
| 86633 | // Label 5774: @221586 |
| 86634 | GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(221648), // Rule ID 55978 // |
| 86635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86639 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86640 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86641 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86642 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86643 | // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 86645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86646 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86648 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86653 | GIR_RootConstrainSelectedInstOperands, |
| 86654 | // GIR_Coverage, 55978, |
| 86655 | GIR_EraseRootFromParent_Done, |
| 86656 | // Label 5775: @221648 |
| 86657 | GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(221710), // Rule ID 55979 // |
| 86658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86659 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86660 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86661 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86662 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86663 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86664 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86665 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86666 | // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 86668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86669 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86671 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86676 | GIR_RootConstrainSelectedInstOperands, |
| 86677 | // GIR_Coverage, 55979, |
| 86678 | GIR_EraseRootFromParent_Done, |
| 86679 | // Label 5776: @221710 |
| 86680 | GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(221772), // Rule ID 72448 // |
| 86681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86682 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86683 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86684 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86685 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86686 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86687 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86688 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86689 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 86691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86692 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86694 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86699 | GIR_RootConstrainSelectedInstOperands, |
| 86700 | // GIR_Coverage, 72448, |
| 86701 | GIR_EraseRootFromParent_Done, |
| 86702 | // Label 5777: @221772 |
| 86703 | GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(221834), // Rule ID 72449 // |
| 86704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86706 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 86707 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86708 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86709 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86710 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86711 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86712 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 86714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86715 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 86716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 86717 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86722 | GIR_RootConstrainSelectedInstOperands, |
| 86723 | // GIR_Coverage, 72449, |
| 86724 | GIR_EraseRootFromParent_Done, |
| 86725 | // Label 5778: @221834 |
| 86726 | GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(221896), // Rule ID 55970 // |
| 86727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86730 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 86731 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86732 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86733 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86734 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86735 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E16), |
| 86737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86738 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86739 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 86741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86745 | GIR_RootConstrainSelectedInstOperands, |
| 86746 | // GIR_Coverage, 55970, |
| 86747 | GIR_EraseRootFromParent_Done, |
| 86748 | // Label 5779: @221896 |
| 86749 | GIM_Try, /*On fail goto*//*Label 5780*/ GIMT_Encode4(221958), // Rule ID 55971 // |
| 86750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86752 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86753 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 86754 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 86755 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 86756 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86757 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86758 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E16), |
| 86760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86761 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86762 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 86764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86768 | GIR_RootConstrainSelectedInstOperands, |
| 86769 | // GIR_Coverage, 55971, |
| 86770 | GIR_EraseRootFromParent_Done, |
| 86771 | // Label 5780: @221958 |
| 86772 | GIM_Try, /*On fail goto*//*Label 5781*/ GIMT_Encode4(222003), // Rule ID 55966 // |
| 86773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 86774 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86776 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86777 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 86778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E16), |
| 86779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86780 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86781 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86782 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86787 | GIR_RootConstrainSelectedInstOperands, |
| 86788 | // GIR_Coverage, 55966, |
| 86789 | GIR_EraseRootFromParent_Done, |
| 86790 | // Label 5781: @222003 |
| 86791 | GIM_Try, /*On fail goto*//*Label 5782*/ GIMT_Encode4(222048), // Rule ID 55967 // |
| 86792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 86793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86794 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86795 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 86796 | // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 86797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E16), |
| 86798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86799 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 86800 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86801 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 86802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 86804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 86805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 86806 | GIR_RootConstrainSelectedInstOperands, |
| 86807 | // GIR_Coverage, 55967, |
| 86808 | GIR_EraseRootFromParent_Done, |
| 86809 | // Label 5782: @222048 |
| 86810 | GIM_Reject, |
| 86811 | // Label 5770: @222049 |
| 86812 | GIM_Reject, |
| 86813 | // Label 5506: @222050 |
| 86814 | GIM_Reject, |
| 86815 | // Label 57: @222051 |
| 86816 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 5801*/ GIMT_Encode4(224478), |
| 86817 | /*GILLT_s16*//*Label 5783*/ GIMT_Encode4(222182), |
| 86818 | /*GILLT_s32*//*Label 5784*/ GIMT_Encode4(222331), |
| 86819 | /*GILLT_s64*//*Label 5785*/ GIMT_Encode4(222480), GIMT_Encode4(0), GIMT_Encode4(0), |
| 86820 | /*GILLT_nxv1s16*//*Label 5786*/ GIMT_Encode4(222663), |
| 86821 | /*GILLT_nxv1s32*//*Label 5787*/ GIMT_Encode4(222784), |
| 86822 | /*GILLT_nxv1s64*//*Label 5788*/ GIMT_Encode4(222905), GIMT_Encode4(0), GIMT_Encode4(0), |
| 86823 | /*GILLT_nxv2s16*//*Label 5789*/ GIMT_Encode4(223026), |
| 86824 | /*GILLT_nxv2s32*//*Label 5790*/ GIMT_Encode4(223147), |
| 86825 | /*GILLT_nxv2s64*//*Label 5791*/ GIMT_Encode4(223268), GIMT_Encode4(0), GIMT_Encode4(0), |
| 86826 | /*GILLT_nxv4s16*//*Label 5792*/ GIMT_Encode4(223389), |
| 86827 | /*GILLT_nxv4s32*//*Label 5793*/ GIMT_Encode4(223510), |
| 86828 | /*GILLT_nxv4s64*//*Label 5794*/ GIMT_Encode4(223631), GIMT_Encode4(0), GIMT_Encode4(0), |
| 86829 | /*GILLT_nxv8s16*//*Label 5795*/ GIMT_Encode4(223752), |
| 86830 | /*GILLT_nxv8s32*//*Label 5796*/ GIMT_Encode4(223873), |
| 86831 | /*GILLT_nxv8s64*//*Label 5797*/ GIMT_Encode4(223994), GIMT_Encode4(0), GIMT_Encode4(0), |
| 86832 | /*GILLT_nxv16s16*//*Label 5798*/ GIMT_Encode4(224115), |
| 86833 | /*GILLT_nxv16s32*//*Label 5799*/ GIMT_Encode4(224236), GIMT_Encode4(0), GIMT_Encode4(0), |
| 86834 | /*GILLT_nxv32s16*//*Label 5800*/ GIMT_Encode4(224357), |
| 86835 | // Label 5783: @222182 |
| 86836 | GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(222330), |
| 86837 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 86838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 86839 | GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(222227), // Rule ID 2036 // |
| 86840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 86841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 86842 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 86843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 86844 | // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FDIV_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 86845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H), |
| 86846 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86847 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86848 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86850 | GIR_RootConstrainSelectedInstOperands, |
| 86851 | // GIR_Coverage, 2036, |
| 86852 | GIR_EraseRootFromParent_Done, |
| 86853 | // Label 5803: @222227 |
| 86854 | GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(222261), // Rule ID 2037 // |
| 86855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 86856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 86857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 86858 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 86859 | // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FDIV_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 86860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H), |
| 86861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86862 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86863 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86865 | GIR_RootConstrainSelectedInstOperands, |
| 86866 | // GIR_Coverage, 2037, |
| 86867 | GIR_EraseRootFromParent_Done, |
| 86868 | // Label 5804: @222261 |
| 86869 | GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(222295), // Rule ID 2040 // |
| 86870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 86871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 86872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 86873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 86874 | // (fdiv:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FDIV_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 86875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H_INX), |
| 86876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86877 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86878 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86880 | GIR_RootConstrainSelectedInstOperands, |
| 86881 | // GIR_Coverage, 2040, |
| 86882 | GIR_EraseRootFromParent_Done, |
| 86883 | // Label 5805: @222295 |
| 86884 | GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(222329), // Rule ID 2041 // |
| 86885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 86886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 86887 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 86888 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 86889 | // (fdiv:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FDIV_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 86890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H_INX), |
| 86891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86892 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86893 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86895 | GIR_RootConstrainSelectedInstOperands, |
| 86896 | // GIR_Coverage, 2041, |
| 86897 | GIR_EraseRootFromParent_Done, |
| 86898 | // Label 5806: @222329 |
| 86899 | GIM_Reject, |
| 86900 | // Label 5802: @222330 |
| 86901 | GIM_Reject, |
| 86902 | // Label 5784: @222331 |
| 86903 | GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(222479), |
| 86904 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 86905 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 86906 | GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(222376), // Rule ID 1348 // |
| 86907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 86908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 86909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 86910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 86911 | // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 86912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S), |
| 86913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86915 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86917 | GIR_RootConstrainSelectedInstOperands, |
| 86918 | // GIR_Coverage, 1348, |
| 86919 | GIR_EraseRootFromParent_Done, |
| 86920 | // Label 5808: @222376 |
| 86921 | GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(222410), // Rule ID 1349 // |
| 86922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 86923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 86924 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 86925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 86926 | // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 86927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S), |
| 86928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86929 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86930 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86932 | GIR_RootConstrainSelectedInstOperands, |
| 86933 | // GIR_Coverage, 1349, |
| 86934 | GIR_EraseRootFromParent_Done, |
| 86935 | // Label 5809: @222410 |
| 86936 | GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(222444), // Rule ID 1352 // |
| 86937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 86938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 86939 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 86940 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 86941 | // (fdiv:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FDIV_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 86942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S_INX), |
| 86943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86944 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86945 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86947 | GIR_RootConstrainSelectedInstOperands, |
| 86948 | // GIR_Coverage, 1352, |
| 86949 | GIR_EraseRootFromParent_Done, |
| 86950 | // Label 5810: @222444 |
| 86951 | GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(222478), // Rule ID 1353 // |
| 86952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 86953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 86954 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 86955 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 86956 | // (fdiv:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FDIV_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 86957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S_INX), |
| 86958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86959 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86960 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86962 | GIR_RootConstrainSelectedInstOperands, |
| 86963 | // GIR_Coverage, 1353, |
| 86964 | GIR_EraseRootFromParent_Done, |
| 86965 | // Label 5811: @222478 |
| 86966 | GIM_Reject, |
| 86967 | // Label 5807: @222479 |
| 86968 | GIM_Reject, |
| 86969 | // Label 5785: @222480 |
| 86970 | GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(222662), |
| 86971 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 86972 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 86973 | GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(222525), // Rule ID 1681 // |
| 86974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 86975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 86976 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 86977 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 86978 | // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 86979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D), |
| 86980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86981 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86982 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86984 | GIR_RootConstrainSelectedInstOperands, |
| 86985 | // GIR_Coverage, 1681, |
| 86986 | GIR_EraseRootFromParent_Done, |
| 86987 | // Label 5813: @222525 |
| 86988 | GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(222559), // Rule ID 1682 // |
| 86989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 86990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 86991 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 86992 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 86993 | // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 86994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D), |
| 86995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 86996 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 86997 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 86998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 86999 | GIR_RootConstrainSelectedInstOperands, |
| 87000 | // GIR_Coverage, 1682, |
| 87001 | GIR_EraseRootFromParent_Done, |
| 87002 | // Label 5814: @222559 |
| 87003 | GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(222593), // Rule ID 1685 // |
| 87004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 87005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87008 | // (fdiv:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FDIV_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 87009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D_IN32X), |
| 87010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87011 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87012 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87014 | GIR_RootConstrainSelectedInstOperands, |
| 87015 | // GIR_Coverage, 1685, |
| 87016 | GIR_EraseRootFromParent_Done, |
| 87017 | // Label 5815: @222593 |
| 87018 | GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(222627), // Rule ID 1686 // |
| 87019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 87020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87021 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87022 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87023 | // (fdiv:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FDIV_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 87024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D_IN32X), |
| 87025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87026 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87027 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87029 | GIR_RootConstrainSelectedInstOperands, |
| 87030 | // GIR_Coverage, 1686, |
| 87031 | GIR_EraseRootFromParent_Done, |
| 87032 | // Label 5816: @222627 |
| 87033 | GIM_Try, /*On fail goto*//*Label 5817*/ GIMT_Encode4(222661), // Rule ID 1688 // |
| 87034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 87035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 87036 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 87037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 87038 | // (fdiv:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FDIV_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 87039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D_INX), |
| 87040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87041 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87042 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87044 | GIR_RootConstrainSelectedInstOperands, |
| 87045 | // GIR_Coverage, 1688, |
| 87046 | GIR_EraseRootFromParent_Done, |
| 87047 | // Label 5817: @222661 |
| 87048 | GIM_Reject, |
| 87049 | // Label 5812: @222662 |
| 87050 | GIM_Reject, |
| 87051 | // Label 5786: @222663 |
| 87052 | GIM_Try, /*On fail goto*//*Label 5818*/ GIMT_Encode4(222783), |
| 87053 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 87054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 87055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87056 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87057 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87058 | GIM_Try, /*On fail goto*//*Label 5819*/ GIMT_Encode4(222734), // Rule ID 55028 // |
| 87059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87060 | // (fdiv:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFDIV_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87061 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 87062 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87063 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87064 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF4_E16), |
| 87066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87067 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87069 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87074 | GIR_RootConstrainSelectedInstOperands, |
| 87075 | // GIR_Coverage, 55028, |
| 87076 | GIR_EraseRootFromParent_Done, |
| 87077 | // Label 5819: @222734 |
| 87078 | GIM_Try, /*On fail goto*//*Label 5820*/ GIMT_Encode4(222782), // Rule ID 55029 // |
| 87079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87080 | // (fdiv:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFDIV_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 87082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF4_E16), |
| 87086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87087 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87088 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87089 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87094 | GIR_RootConstrainSelectedInstOperands, |
| 87095 | // GIR_Coverage, 55029, |
| 87096 | GIR_EraseRootFromParent_Done, |
| 87097 | // Label 5820: @222782 |
| 87098 | GIM_Reject, |
| 87099 | // Label 5818: @222783 |
| 87100 | GIM_Reject, |
| 87101 | // Label 5787: @222784 |
| 87102 | GIM_Try, /*On fail goto*//*Label 5821*/ GIMT_Encode4(222904), |
| 87103 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 87104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 87105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87107 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87108 | GIM_Try, /*On fail goto*//*Label 5822*/ GIMT_Encode4(222855), // Rule ID 55052 // |
| 87109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 87110 | // (fdiv:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFDIV_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 87111 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 87112 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87113 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E32), |
| 87116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87117 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87118 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87119 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87124 | GIR_RootConstrainSelectedInstOperands, |
| 87125 | // GIR_Coverage, 55052, |
| 87126 | GIR_EraseRootFromParent_Done, |
| 87127 | // Label 5822: @222855 |
| 87128 | GIM_Try, /*On fail goto*//*Label 5823*/ GIMT_Encode4(222903), // Rule ID 55053 // |
| 87129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 87130 | // (fdiv:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFDIV_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 87131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 87132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E32), |
| 87136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87138 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87139 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87144 | GIR_RootConstrainSelectedInstOperands, |
| 87145 | // GIR_Coverage, 55053, |
| 87146 | GIR_EraseRootFromParent_Done, |
| 87147 | // Label 5823: @222903 |
| 87148 | GIM_Reject, |
| 87149 | // Label 5821: @222904 |
| 87150 | GIM_Reject, |
| 87151 | // Label 5788: @222905 |
| 87152 | GIM_Try, /*On fail goto*//*Label 5824*/ GIMT_Encode4(223025), |
| 87153 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 87154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 87155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87157 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87158 | GIM_Try, /*On fail goto*//*Label 5825*/ GIMT_Encode4(222976), // Rule ID 55088 // |
| 87159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 87160 | // (fdiv:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFDIV_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 87161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 87162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E64), |
| 87166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87167 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87169 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87174 | GIR_RootConstrainSelectedInstOperands, |
| 87175 | // GIR_Coverage, 55088, |
| 87176 | GIR_EraseRootFromParent_Done, |
| 87177 | // Label 5825: @222976 |
| 87178 | GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(223024), // Rule ID 55089 // |
| 87179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 87180 | // (fdiv:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFDIV_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 87181 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 87182 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87183 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E64), |
| 87186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87187 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87188 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87189 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87194 | GIR_RootConstrainSelectedInstOperands, |
| 87195 | // GIR_Coverage, 55089, |
| 87196 | GIR_EraseRootFromParent_Done, |
| 87197 | // Label 5826: @223024 |
| 87198 | GIM_Reject, |
| 87199 | // Label 5824: @223025 |
| 87200 | GIM_Reject, |
| 87201 | // Label 5789: @223026 |
| 87202 | GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(223146), |
| 87203 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 87204 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 87205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87206 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87207 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87208 | GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(223097), // Rule ID 55040 // |
| 87209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87210 | // (fdiv:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFDIV_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87211 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 87212 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87213 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87214 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E16), |
| 87216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87217 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87218 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87219 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87224 | GIR_RootConstrainSelectedInstOperands, |
| 87225 | // GIR_Coverage, 55040, |
| 87226 | GIR_EraseRootFromParent_Done, |
| 87227 | // Label 5828: @223097 |
| 87228 | GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(223145), // Rule ID 55041 // |
| 87229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87230 | // (fdiv:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFDIV_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87231 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 87232 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87233 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87234 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E16), |
| 87236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87237 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87238 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87239 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87244 | GIR_RootConstrainSelectedInstOperands, |
| 87245 | // GIR_Coverage, 55041, |
| 87246 | GIR_EraseRootFromParent_Done, |
| 87247 | // Label 5829: @223145 |
| 87248 | GIM_Reject, |
| 87249 | // Label 5827: @223146 |
| 87250 | GIM_Reject, |
| 87251 | // Label 5790: @223147 |
| 87252 | GIM_Try, /*On fail goto*//*Label 5830*/ GIMT_Encode4(223267), |
| 87253 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 87254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 87255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87258 | GIM_Try, /*On fail goto*//*Label 5831*/ GIMT_Encode4(223218), // Rule ID 55076 // |
| 87259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 87260 | // (fdiv:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFDIV_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 87261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 87262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E32), |
| 87266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87268 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87269 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87274 | GIR_RootConstrainSelectedInstOperands, |
| 87275 | // GIR_Coverage, 55076, |
| 87276 | GIR_EraseRootFromParent_Done, |
| 87277 | // Label 5831: @223218 |
| 87278 | GIM_Try, /*On fail goto*//*Label 5832*/ GIMT_Encode4(223266), // Rule ID 55077 // |
| 87279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 87280 | // (fdiv:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFDIV_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 87281 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 87282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E32), |
| 87286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87287 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87288 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87289 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87294 | GIR_RootConstrainSelectedInstOperands, |
| 87295 | // GIR_Coverage, 55077, |
| 87296 | GIR_EraseRootFromParent_Done, |
| 87297 | // Label 5832: @223266 |
| 87298 | GIM_Reject, |
| 87299 | // Label 5830: @223267 |
| 87300 | GIM_Reject, |
| 87301 | // Label 5791: @223268 |
| 87302 | GIM_Try, /*On fail goto*//*Label 5833*/ GIMT_Encode4(223388), |
| 87303 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 87304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 87305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87308 | GIM_Try, /*On fail goto*//*Label 5834*/ GIMT_Encode4(223339), // Rule ID 55172 // |
| 87309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 87310 | // (fdiv:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFDIV_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 87311 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 87312 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87313 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E64), |
| 87316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87317 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87318 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87319 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87324 | GIR_RootConstrainSelectedInstOperands, |
| 87325 | // GIR_Coverage, 55172, |
| 87326 | GIR_EraseRootFromParent_Done, |
| 87327 | // Label 5834: @223339 |
| 87328 | GIM_Try, /*On fail goto*//*Label 5835*/ GIMT_Encode4(223387), // Rule ID 55173 // |
| 87329 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 87330 | // (fdiv:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFDIV_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 87331 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 87332 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87333 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87334 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E64), |
| 87336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87338 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87339 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87344 | GIR_RootConstrainSelectedInstOperands, |
| 87345 | // GIR_Coverage, 55173, |
| 87346 | GIR_EraseRootFromParent_Done, |
| 87347 | // Label 5835: @223387 |
| 87348 | GIM_Reject, |
| 87349 | // Label 5833: @223388 |
| 87350 | GIM_Reject, |
| 87351 | // Label 5792: @223389 |
| 87352 | GIM_Try, /*On fail goto*//*Label 5836*/ GIMT_Encode4(223509), |
| 87353 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 87354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 87355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87356 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87358 | GIM_Try, /*On fail goto*//*Label 5837*/ GIMT_Encode4(223460), // Rule ID 55064 // |
| 87359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87360 | // (fdiv:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFDIV_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87361 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 87362 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87363 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E16), |
| 87366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87367 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87368 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87369 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87374 | GIR_RootConstrainSelectedInstOperands, |
| 87375 | // GIR_Coverage, 55064, |
| 87376 | GIR_EraseRootFromParent_Done, |
| 87377 | // Label 5837: @223460 |
| 87378 | GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(223508), // Rule ID 55065 // |
| 87379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87380 | // (fdiv:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFDIV_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87381 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 87382 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E16), |
| 87386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87387 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87388 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87389 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87394 | GIR_RootConstrainSelectedInstOperands, |
| 87395 | // GIR_Coverage, 55065, |
| 87396 | GIR_EraseRootFromParent_Done, |
| 87397 | // Label 5838: @223508 |
| 87398 | GIM_Reject, |
| 87399 | // Label 5836: @223509 |
| 87400 | GIM_Reject, |
| 87401 | // Label 5793: @223510 |
| 87402 | GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(223630), |
| 87403 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 87404 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 87405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87408 | GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(223581), // Rule ID 55136 // |
| 87409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 87410 | // (fdiv:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFDIV_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 87411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 87412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87413 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E32), |
| 87416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87417 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87418 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87419 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87424 | GIR_RootConstrainSelectedInstOperands, |
| 87425 | // GIR_Coverage, 55136, |
| 87426 | GIR_EraseRootFromParent_Done, |
| 87427 | // Label 5840: @223581 |
| 87428 | GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(223629), // Rule ID 55137 // |
| 87429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 87430 | // (fdiv:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFDIV_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 87431 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 87432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87433 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E32), |
| 87436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87438 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87439 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87444 | GIR_RootConstrainSelectedInstOperands, |
| 87445 | // GIR_Coverage, 55137, |
| 87446 | GIR_EraseRootFromParent_Done, |
| 87447 | // Label 5841: @223629 |
| 87448 | GIM_Reject, |
| 87449 | // Label 5839: @223630 |
| 87450 | GIM_Reject, |
| 87451 | // Label 5794: @223631 |
| 87452 | GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(223751), |
| 87453 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 87454 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 87455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87456 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87458 | GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(223702), // Rule ID 55184 // |
| 87459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 87460 | // (fdiv:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFDIV_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 87461 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 87462 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87463 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E64), |
| 87466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87467 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87468 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87469 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87474 | GIR_RootConstrainSelectedInstOperands, |
| 87475 | // GIR_Coverage, 55184, |
| 87476 | GIR_EraseRootFromParent_Done, |
| 87477 | // Label 5843: @223702 |
| 87478 | GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(223750), // Rule ID 55185 // |
| 87479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 87480 | // (fdiv:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFDIV_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 87481 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 87482 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87483 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E64), |
| 87486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87487 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87488 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87489 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87494 | GIR_RootConstrainSelectedInstOperands, |
| 87495 | // GIR_Coverage, 55185, |
| 87496 | GIR_EraseRootFromParent_Done, |
| 87497 | // Label 5844: @223750 |
| 87498 | GIM_Reject, |
| 87499 | // Label 5842: @223751 |
| 87500 | GIM_Reject, |
| 87501 | // Label 5795: @223752 |
| 87502 | GIM_Try, /*On fail goto*//*Label 5845*/ GIMT_Encode4(223872), |
| 87503 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 87504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 87505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87506 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87507 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 87508 | GIM_Try, /*On fail goto*//*Label 5846*/ GIMT_Encode4(223823), // Rule ID 55100 // |
| 87509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87510 | // (fdiv:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFDIV_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87511 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 87512 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87513 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E16), |
| 87516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87517 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87518 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87519 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87524 | GIR_RootConstrainSelectedInstOperands, |
| 87525 | // GIR_Coverage, 55100, |
| 87526 | GIR_EraseRootFromParent_Done, |
| 87527 | // Label 5846: @223823 |
| 87528 | GIM_Try, /*On fail goto*//*Label 5847*/ GIMT_Encode4(223871), // Rule ID 55101 // |
| 87529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87530 | // (fdiv:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFDIV_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87531 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 87532 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87533 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87534 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E16), |
| 87536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87537 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87538 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87539 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87544 | GIR_RootConstrainSelectedInstOperands, |
| 87545 | // GIR_Coverage, 55101, |
| 87546 | GIR_EraseRootFromParent_Done, |
| 87547 | // Label 5847: @223871 |
| 87548 | GIM_Reject, |
| 87549 | // Label 5845: @223872 |
| 87550 | GIM_Reject, |
| 87551 | // Label 5796: @223873 |
| 87552 | GIM_Try, /*On fail goto*//*Label 5848*/ GIMT_Encode4(223993), |
| 87553 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 87554 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 87555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87556 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87557 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87558 | GIM_Try, /*On fail goto*//*Label 5849*/ GIMT_Encode4(223944), // Rule ID 55148 // |
| 87559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 87560 | // (fdiv:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFDIV_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 87561 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 87562 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87563 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87564 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E32), |
| 87566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87567 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87568 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87569 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87574 | GIR_RootConstrainSelectedInstOperands, |
| 87575 | // GIR_Coverage, 55148, |
| 87576 | GIR_EraseRootFromParent_Done, |
| 87577 | // Label 5849: @223944 |
| 87578 | GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(223992), // Rule ID 55149 // |
| 87579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 87580 | // (fdiv:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFDIV_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 87581 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 87582 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87583 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E32), |
| 87586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87587 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87588 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87589 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87594 | GIR_RootConstrainSelectedInstOperands, |
| 87595 | // GIR_Coverage, 55149, |
| 87596 | GIR_EraseRootFromParent_Done, |
| 87597 | // Label 5850: @223992 |
| 87598 | GIM_Reject, |
| 87599 | // Label 5848: @223993 |
| 87600 | GIM_Reject, |
| 87601 | // Label 5797: @223994 |
| 87602 | GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(224114), |
| 87603 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 87604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 87605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87606 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87608 | GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(224065), // Rule ID 55196 // |
| 87609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 87610 | // (fdiv:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFDIV_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 87611 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 87612 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87613 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E64), |
| 87616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87618 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87619 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87624 | GIR_RootConstrainSelectedInstOperands, |
| 87625 | // GIR_Coverage, 55196, |
| 87626 | GIR_EraseRootFromParent_Done, |
| 87627 | // Label 5852: @224065 |
| 87628 | GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(224113), // Rule ID 55197 // |
| 87629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 87630 | // (fdiv:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFDIV_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 87631 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 87632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87633 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E64), |
| 87636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87638 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87639 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 87643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87644 | GIR_RootConstrainSelectedInstOperands, |
| 87645 | // GIR_Coverage, 55197, |
| 87646 | GIR_EraseRootFromParent_Done, |
| 87647 | // Label 5853: @224113 |
| 87648 | GIM_Reject, |
| 87649 | // Label 5851: @224114 |
| 87650 | GIM_Reject, |
| 87651 | // Label 5798: @224115 |
| 87652 | GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(224235), |
| 87653 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 87654 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 87655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87656 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87657 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 87658 | GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(224186), // Rule ID 55112 // |
| 87659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87660 | // (fdiv:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFDIV_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87661 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 87662 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87663 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E16), |
| 87666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87667 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87668 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87669 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87674 | GIR_RootConstrainSelectedInstOperands, |
| 87675 | // GIR_Coverage, 55112, |
| 87676 | GIR_EraseRootFromParent_Done, |
| 87677 | // Label 5855: @224186 |
| 87678 | GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(224234), // Rule ID 55113 // |
| 87679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87680 | // (fdiv:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFDIV_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87681 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 87682 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87683 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E16), |
| 87686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87687 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87688 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87689 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87694 | GIR_RootConstrainSelectedInstOperands, |
| 87695 | // GIR_Coverage, 55113, |
| 87696 | GIR_EraseRootFromParent_Done, |
| 87697 | // Label 5856: @224234 |
| 87698 | GIM_Reject, |
| 87699 | // Label 5854: @224235 |
| 87700 | GIM_Reject, |
| 87701 | // Label 5799: @224236 |
| 87702 | GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(224356), |
| 87703 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 87704 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 87705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87708 | GIM_Try, /*On fail goto*//*Label 5858*/ GIMT_Encode4(224307), // Rule ID 55160 // |
| 87709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 87710 | // (fdiv:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFDIV_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 87711 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 87712 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87713 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87714 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E32), |
| 87716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87717 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87718 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87719 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87724 | GIR_RootConstrainSelectedInstOperands, |
| 87725 | // GIR_Coverage, 55160, |
| 87726 | GIR_EraseRootFromParent_Done, |
| 87727 | // Label 5858: @224307 |
| 87728 | GIM_Try, /*On fail goto*//*Label 5859*/ GIMT_Encode4(224355), // Rule ID 55161 // |
| 87729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 87730 | // (fdiv:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFDIV_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 87731 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 87732 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87733 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E32), |
| 87736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87737 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87738 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87739 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87744 | GIR_RootConstrainSelectedInstOperands, |
| 87745 | // GIR_Coverage, 55161, |
| 87746 | GIR_EraseRootFromParent_Done, |
| 87747 | // Label 5859: @224355 |
| 87748 | GIM_Reject, |
| 87749 | // Label 5857: @224356 |
| 87750 | GIM_Reject, |
| 87751 | // Label 5800: @224357 |
| 87752 | GIM_Try, /*On fail goto*//*Label 5860*/ GIMT_Encode4(224477), |
| 87753 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 87754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 87755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87757 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 87758 | GIM_Try, /*On fail goto*//*Label 5861*/ GIMT_Encode4(224428), // Rule ID 55124 // |
| 87759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87760 | // (fdiv:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFDIV_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87761 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 87762 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87763 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E16), |
| 87766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87768 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87769 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87774 | GIR_RootConstrainSelectedInstOperands, |
| 87775 | // GIR_Coverage, 55124, |
| 87776 | GIR_EraseRootFromParent_Done, |
| 87777 | // Label 5861: @224428 |
| 87778 | GIM_Try, /*On fail goto*//*Label 5862*/ GIMT_Encode4(224476), // Rule ID 55125 // |
| 87779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87780 | // (fdiv:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFDIV_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87781 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 87782 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87783 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E16), |
| 87786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87787 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87788 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87789 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 87790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 87791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87794 | GIR_RootConstrainSelectedInstOperands, |
| 87795 | // GIR_Coverage, 55125, |
| 87796 | GIR_EraseRootFromParent_Done, |
| 87797 | // Label 5862: @224476 |
| 87798 | GIM_Reject, |
| 87799 | // Label 5860: @224477 |
| 87800 | GIM_Reject, |
| 87801 | // Label 5801: @224478 |
| 87802 | GIM_Reject, |
| 87803 | // Label 58: @224479 |
| 87804 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 5881*/ GIMT_Encode4(226449), |
| 87805 | /*GILLT_s16*//*Label 5863*/ GIMT_Encode4(224610), |
| 87806 | /*GILLT_s32*//*Label 5864*/ GIMT_Encode4(224674), |
| 87807 | /*GILLT_s64*//*Label 5865*/ GIMT_Encode4(224738), GIMT_Encode4(0), GIMT_Encode4(0), |
| 87808 | /*GILLT_nxv1s16*//*Label 5866*/ GIMT_Encode4(224829), |
| 87809 | /*GILLT_nxv1s32*//*Label 5867*/ GIMT_Encode4(224937), |
| 87810 | /*GILLT_nxv1s64*//*Label 5868*/ GIMT_Encode4(225045), GIMT_Encode4(0), GIMT_Encode4(0), |
| 87811 | /*GILLT_nxv2s16*//*Label 5869*/ GIMT_Encode4(225153), |
| 87812 | /*GILLT_nxv2s32*//*Label 5870*/ GIMT_Encode4(225261), |
| 87813 | /*GILLT_nxv2s64*//*Label 5871*/ GIMT_Encode4(225369), GIMT_Encode4(0), GIMT_Encode4(0), |
| 87814 | /*GILLT_nxv4s16*//*Label 5872*/ GIMT_Encode4(225477), |
| 87815 | /*GILLT_nxv4s32*//*Label 5873*/ GIMT_Encode4(225585), |
| 87816 | /*GILLT_nxv4s64*//*Label 5874*/ GIMT_Encode4(225693), GIMT_Encode4(0), GIMT_Encode4(0), |
| 87817 | /*GILLT_nxv8s16*//*Label 5875*/ GIMT_Encode4(225801), |
| 87818 | /*GILLT_nxv8s32*//*Label 5876*/ GIMT_Encode4(225909), |
| 87819 | /*GILLT_nxv8s64*//*Label 5877*/ GIMT_Encode4(226017), GIMT_Encode4(0), GIMT_Encode4(0), |
| 87820 | /*GILLT_nxv16s16*//*Label 5878*/ GIMT_Encode4(226125), |
| 87821 | /*GILLT_nxv16s32*//*Label 5879*/ GIMT_Encode4(226233), GIMT_Encode4(0), GIMT_Encode4(0), |
| 87822 | /*GILLT_nxv32s16*//*Label 5880*/ GIMT_Encode4(226341), |
| 87823 | // Label 5863: @224610 |
| 87824 | GIM_Try, /*On fail goto*//*Label 5882*/ GIMT_Encode4(224673), |
| 87825 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87826 | GIM_Try, /*On fail goto*//*Label 5883*/ GIMT_Encode4(224645), // Rule ID 2046 // |
| 87827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh), |
| 87828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 87829 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 87830 | // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FSGNJN_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs1) |
| 87831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_H), |
| 87832 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87833 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87834 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87835 | GIR_RootConstrainSelectedInstOperands, |
| 87836 | // GIR_Coverage, 2046, |
| 87837 | GIR_EraseRootFromParent_Done, |
| 87838 | // Label 5883: @224645 |
| 87839 | GIM_Try, /*On fail goto*//*Label 5884*/ GIMT_Encode4(224672), // Rule ID 2078 // |
| 87840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx), |
| 87841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 87842 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 87843 | // (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1) => (FSGNJN_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs1) |
| 87844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_H_INX), |
| 87845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87846 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87847 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87848 | GIR_RootConstrainSelectedInstOperands, |
| 87849 | // GIR_Coverage, 2078, |
| 87850 | GIR_EraseRootFromParent_Done, |
| 87851 | // Label 5884: @224672 |
| 87852 | GIM_Reject, |
| 87853 | // Label 5882: @224673 |
| 87854 | GIM_Reject, |
| 87855 | // Label 5864: @224674 |
| 87856 | GIM_Try, /*On fail goto*//*Label 5885*/ GIMT_Encode4(224737), |
| 87857 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87858 | GIM_Try, /*On fail goto*//*Label 5886*/ GIMT_Encode4(224709), // Rule ID 1358 // |
| 87859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF), |
| 87860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 87861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 87862 | // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSGNJN_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs1) |
| 87863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_S), |
| 87864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87865 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87866 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87867 | GIR_RootConstrainSelectedInstOperands, |
| 87868 | // GIR_Coverage, 1358, |
| 87869 | GIR_EraseRootFromParent_Done, |
| 87870 | // Label 5886: @224709 |
| 87871 | GIM_Try, /*On fail goto*//*Label 5887*/ GIMT_Encode4(224736), // Rule ID 1366 // |
| 87872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx), |
| 87873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 87874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 87875 | // (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1) => (FSGNJN_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs1) |
| 87876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_S_INX), |
| 87877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87878 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87879 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87880 | GIR_RootConstrainSelectedInstOperands, |
| 87881 | // GIR_Coverage, 1366, |
| 87882 | GIR_EraseRootFromParent_Done, |
| 87883 | // Label 5887: @224736 |
| 87884 | GIM_Reject, |
| 87885 | // Label 5885: @224737 |
| 87886 | GIM_Reject, |
| 87887 | // Label 5865: @224738 |
| 87888 | GIM_Try, /*On fail goto*//*Label 5888*/ GIMT_Encode4(224828), |
| 87889 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 87890 | GIM_Try, /*On fail goto*//*Label 5889*/ GIMT_Encode4(224773), // Rule ID 1693 // |
| 87891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD), |
| 87892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 87893 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 87894 | // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSGNJN_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1) |
| 87895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_D), |
| 87896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87897 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87898 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87899 | GIR_RootConstrainSelectedInstOperands, |
| 87900 | // GIR_Coverage, 1693, |
| 87901 | GIR_EraseRootFromParent_Done, |
| 87902 | // Label 5889: @224773 |
| 87903 | GIM_Try, /*On fail goto*//*Label 5890*/ GIMT_Encode4(224800), // Rule ID 1725 // |
| 87904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 87905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 87906 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 87907 | // (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1) => (FSGNJN_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1) |
| 87908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_D_INX), |
| 87909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87910 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87911 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87912 | GIR_RootConstrainSelectedInstOperands, |
| 87913 | // GIR_Coverage, 1725, |
| 87914 | GIR_EraseRootFromParent_Done, |
| 87915 | // Label 5890: @224800 |
| 87916 | GIM_Try, /*On fail goto*//*Label 5891*/ GIMT_Encode4(224827), // Rule ID 1746 // |
| 87917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32), |
| 87918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87919 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 87920 | // (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FSGNJN_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1) |
| 87921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJN_D_IN32X), |
| 87922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87923 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87924 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 87925 | GIR_RootConstrainSelectedInstOperands, |
| 87926 | // GIR_Coverage, 1746, |
| 87927 | GIR_EraseRootFromParent_Done, |
| 87928 | // Label 5891: @224827 |
| 87929 | GIM_Reject, |
| 87930 | // Label 5888: @224828 |
| 87931 | GIM_Reject, |
| 87932 | // Label 5866: @224829 |
| 87933 | GIM_Try, /*On fail goto*//*Label 5892*/ GIMT_Encode4(224936), |
| 87934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 87935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87937 | GIM_Try, /*On fail goto*//*Label 5893*/ GIMT_Encode4(224890), // Rule ID 56866 // |
| 87938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 87939 | // (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs) => (PseudoVFSGNJN_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 87940 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 87941 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87942 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF4_E16), |
| 87945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87946 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87947 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 87948 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 87949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87952 | GIR_RootConstrainSelectedInstOperands, |
| 87953 | // GIR_Coverage, 56866, |
| 87954 | GIR_EraseRootFromParent_Done, |
| 87955 | // Label 5893: @224890 |
| 87956 | GIM_Try, /*On fail goto*//*Label 5894*/ GIMT_Encode4(224935), // Rule ID 56867 // |
| 87957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 87958 | // (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs) => (PseudoVFSGNJN_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 87959 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 87960 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87961 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF4_E16), |
| 87964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87965 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87966 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 87967 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 87968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 87970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87971 | GIR_RootConstrainSelectedInstOperands, |
| 87972 | // GIR_Coverage, 56867, |
| 87973 | GIR_EraseRootFromParent_Done, |
| 87974 | // Label 5894: @224935 |
| 87975 | GIM_Reject, |
| 87976 | // Label 5892: @224936 |
| 87977 | GIM_Reject, |
| 87978 | // Label 5867: @224937 |
| 87979 | GIM_Try, /*On fail goto*//*Label 5895*/ GIMT_Encode4(225044), |
| 87980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 87981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 87983 | GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(224998), // Rule ID 56906 // |
| 87984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 87985 | // (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs) => (PseudoVFSGNJN_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 87986 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 87987 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87988 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E32), |
| 87991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 87992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87993 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 87994 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 87995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 87996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 87997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 87998 | GIR_RootConstrainSelectedInstOperands, |
| 87999 | // GIR_Coverage, 56906, |
| 88000 | GIR_EraseRootFromParent_Done, |
| 88001 | // Label 5896: @224998 |
| 88002 | GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(225043), // Rule ID 56907 // |
| 88003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 88004 | // (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs) => (PseudoVFSGNJN_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 88005 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 88006 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88007 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E32), |
| 88010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88011 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88012 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88013 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88017 | GIR_RootConstrainSelectedInstOperands, |
| 88018 | // GIR_Coverage, 56907, |
| 88019 | GIR_EraseRootFromParent_Done, |
| 88020 | // Label 5897: @225043 |
| 88021 | GIM_Reject, |
| 88022 | // Label 5895: @225044 |
| 88023 | GIM_Reject, |
| 88024 | // Label 5868: @225045 |
| 88025 | GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(225152), |
| 88026 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 88027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88028 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88029 | GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(225106), // Rule ID 56966 // |
| 88030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 88031 | // (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs) => (PseudoVFSGNJN_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 88032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 88033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E64), |
| 88037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88038 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88039 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88040 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88044 | GIR_RootConstrainSelectedInstOperands, |
| 88045 | // GIR_Coverage, 56966, |
| 88046 | GIR_EraseRootFromParent_Done, |
| 88047 | // Label 5899: @225106 |
| 88048 | GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(225151), // Rule ID 56967 // |
| 88049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 88050 | // (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs) => (PseudoVFSGNJN_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 88051 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 88052 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88053 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E64), |
| 88056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88057 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88058 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88059 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88063 | GIR_RootConstrainSelectedInstOperands, |
| 88064 | // GIR_Coverage, 56967, |
| 88065 | GIR_EraseRootFromParent_Done, |
| 88066 | // Label 5900: @225151 |
| 88067 | GIM_Reject, |
| 88068 | // Label 5898: @225152 |
| 88069 | GIM_Reject, |
| 88070 | // Label 5869: @225153 |
| 88071 | GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(225260), |
| 88072 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 88073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88074 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88075 | GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(225214), // Rule ID 56886 // |
| 88076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 88077 | // (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs) => (PseudoVFSGNJN_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 88078 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 88079 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88080 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E16), |
| 88083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88084 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88085 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88086 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88090 | GIR_RootConstrainSelectedInstOperands, |
| 88091 | // GIR_Coverage, 56886, |
| 88092 | GIR_EraseRootFromParent_Done, |
| 88093 | // Label 5902: @225214 |
| 88094 | GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(225259), // Rule ID 56887 // |
| 88095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 88096 | // (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs) => (PseudoVFSGNJN_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 88097 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 88098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88099 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E16), |
| 88102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88104 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88105 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88109 | GIR_RootConstrainSelectedInstOperands, |
| 88110 | // GIR_Coverage, 56887, |
| 88111 | GIR_EraseRootFromParent_Done, |
| 88112 | // Label 5903: @225259 |
| 88113 | GIM_Reject, |
| 88114 | // Label 5901: @225260 |
| 88115 | GIM_Reject, |
| 88116 | // Label 5870: @225261 |
| 88117 | GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(225368), |
| 88118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 88119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88120 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88121 | GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(225322), // Rule ID 56946 // |
| 88122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 88123 | // (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs) => (PseudoVFSGNJN_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 88124 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 88125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E32), |
| 88129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88130 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88131 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88136 | GIR_RootConstrainSelectedInstOperands, |
| 88137 | // GIR_Coverage, 56946, |
| 88138 | GIR_EraseRootFromParent_Done, |
| 88139 | // Label 5905: @225322 |
| 88140 | GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(225367), // Rule ID 56947 // |
| 88141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 88142 | // (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs) => (PseudoVFSGNJN_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 88143 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 88144 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88145 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E32), |
| 88148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88149 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88150 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88151 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88155 | GIR_RootConstrainSelectedInstOperands, |
| 88156 | // GIR_Coverage, 56947, |
| 88157 | GIR_EraseRootFromParent_Done, |
| 88158 | // Label 5906: @225367 |
| 88159 | GIM_Reject, |
| 88160 | // Label 5904: @225368 |
| 88161 | GIM_Reject, |
| 88162 | // Label 5871: @225369 |
| 88163 | GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(225476), |
| 88164 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 88165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 88166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 88167 | GIM_Try, /*On fail goto*//*Label 5908*/ GIMT_Encode4(225430), // Rule ID 57106 // |
| 88168 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 88169 | // (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs) => (PseudoVFSGNJN_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 88170 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 88171 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88172 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88173 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E64), |
| 88175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88176 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88177 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88178 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88182 | GIR_RootConstrainSelectedInstOperands, |
| 88183 | // GIR_Coverage, 57106, |
| 88184 | GIR_EraseRootFromParent_Done, |
| 88185 | // Label 5908: @225430 |
| 88186 | GIM_Try, /*On fail goto*//*Label 5909*/ GIMT_Encode4(225475), // Rule ID 57107 // |
| 88187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 88188 | // (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs) => (PseudoVFSGNJN_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 88189 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 88190 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88191 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88192 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E64), |
| 88194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88195 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88196 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88197 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88201 | GIR_RootConstrainSelectedInstOperands, |
| 88202 | // GIR_Coverage, 57107, |
| 88203 | GIR_EraseRootFromParent_Done, |
| 88204 | // Label 5909: @225475 |
| 88205 | GIM_Reject, |
| 88206 | // Label 5907: @225476 |
| 88207 | GIM_Reject, |
| 88208 | // Label 5872: @225477 |
| 88209 | GIM_Try, /*On fail goto*//*Label 5910*/ GIMT_Encode4(225584), |
| 88210 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 88211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 88213 | GIM_Try, /*On fail goto*//*Label 5911*/ GIMT_Encode4(225538), // Rule ID 56926 // |
| 88214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 88215 | // (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs) => (PseudoVFSGNJN_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 88216 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 88217 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88218 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E16), |
| 88221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88222 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88223 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88224 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88228 | GIR_RootConstrainSelectedInstOperands, |
| 88229 | // GIR_Coverage, 56926, |
| 88230 | GIR_EraseRootFromParent_Done, |
| 88231 | // Label 5911: @225538 |
| 88232 | GIM_Try, /*On fail goto*//*Label 5912*/ GIMT_Encode4(225583), // Rule ID 56927 // |
| 88233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 88234 | // (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs) => (PseudoVFSGNJN_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 88235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 88236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E16), |
| 88240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88242 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88243 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88247 | GIR_RootConstrainSelectedInstOperands, |
| 88248 | // GIR_Coverage, 56927, |
| 88249 | GIR_EraseRootFromParent_Done, |
| 88250 | // Label 5912: @225583 |
| 88251 | GIM_Reject, |
| 88252 | // Label 5910: @225584 |
| 88253 | GIM_Reject, |
| 88254 | // Label 5873: @225585 |
| 88255 | GIM_Try, /*On fail goto*//*Label 5913*/ GIMT_Encode4(225692), |
| 88256 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 88257 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 88258 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 88259 | GIM_Try, /*On fail goto*//*Label 5914*/ GIMT_Encode4(225646), // Rule ID 57046 // |
| 88260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 88261 | // (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs) => (PseudoVFSGNJN_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 88262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 88263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E32), |
| 88267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88268 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88270 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88274 | GIR_RootConstrainSelectedInstOperands, |
| 88275 | // GIR_Coverage, 57046, |
| 88276 | GIR_EraseRootFromParent_Done, |
| 88277 | // Label 5914: @225646 |
| 88278 | GIM_Try, /*On fail goto*//*Label 5915*/ GIMT_Encode4(225691), // Rule ID 57047 // |
| 88279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 88280 | // (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs) => (PseudoVFSGNJN_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 88281 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 88282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E32), |
| 88286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88287 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88288 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88289 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88293 | GIR_RootConstrainSelectedInstOperands, |
| 88294 | // GIR_Coverage, 57047, |
| 88295 | GIR_EraseRootFromParent_Done, |
| 88296 | // Label 5915: @225691 |
| 88297 | GIM_Reject, |
| 88298 | // Label 5913: @225692 |
| 88299 | GIM_Reject, |
| 88300 | // Label 5874: @225693 |
| 88301 | GIM_Try, /*On fail goto*//*Label 5916*/ GIMT_Encode4(225800), |
| 88302 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 88303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 88304 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 88305 | GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(225754), // Rule ID 57126 // |
| 88306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 88307 | // (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs) => (PseudoVFSGNJN_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 88308 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 88309 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88310 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88311 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E64), |
| 88313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88314 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88315 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88320 | GIR_RootConstrainSelectedInstOperands, |
| 88321 | // GIR_Coverage, 57126, |
| 88322 | GIR_EraseRootFromParent_Done, |
| 88323 | // Label 5917: @225754 |
| 88324 | GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(225799), // Rule ID 57127 // |
| 88325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 88326 | // (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs) => (PseudoVFSGNJN_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 88327 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 88328 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88329 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88330 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E64), |
| 88332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88333 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88334 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88335 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88339 | GIR_RootConstrainSelectedInstOperands, |
| 88340 | // GIR_Coverage, 57127, |
| 88341 | GIR_EraseRootFromParent_Done, |
| 88342 | // Label 5918: @225799 |
| 88343 | GIM_Reject, |
| 88344 | // Label 5916: @225800 |
| 88345 | GIM_Reject, |
| 88346 | // Label 5875: @225801 |
| 88347 | GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(225908), |
| 88348 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 88349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 88350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 88351 | GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(225862), // Rule ID 56986 // |
| 88352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 88353 | // (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs) => (PseudoVFSGNJN_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 88354 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 88355 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88356 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E16), |
| 88359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88360 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88361 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88362 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88366 | GIR_RootConstrainSelectedInstOperands, |
| 88367 | // GIR_Coverage, 56986, |
| 88368 | GIR_EraseRootFromParent_Done, |
| 88369 | // Label 5920: @225862 |
| 88370 | GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(225907), // Rule ID 56987 // |
| 88371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 88372 | // (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs) => (PseudoVFSGNJN_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 88373 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 88374 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88375 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88376 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E16), |
| 88378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88379 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88380 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88381 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88385 | GIR_RootConstrainSelectedInstOperands, |
| 88386 | // GIR_Coverage, 56987, |
| 88387 | GIR_EraseRootFromParent_Done, |
| 88388 | // Label 5921: @225907 |
| 88389 | GIM_Reject, |
| 88390 | // Label 5919: @225908 |
| 88391 | GIM_Reject, |
| 88392 | // Label 5876: @225909 |
| 88393 | GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(226016), |
| 88394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 88395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 88396 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 88397 | GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(225970), // Rule ID 57066 // |
| 88398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 88399 | // (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs) => (PseudoVFSGNJN_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 88400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 88401 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88402 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E32), |
| 88405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88406 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88407 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88408 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88412 | GIR_RootConstrainSelectedInstOperands, |
| 88413 | // GIR_Coverage, 57066, |
| 88414 | GIR_EraseRootFromParent_Done, |
| 88415 | // Label 5923: @225970 |
| 88416 | GIM_Try, /*On fail goto*//*Label 5924*/ GIMT_Encode4(226015), // Rule ID 57067 // |
| 88417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 88418 | // (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs) => (PseudoVFSGNJN_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 88419 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 88420 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88421 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E32), |
| 88424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88425 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88426 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88427 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88431 | GIR_RootConstrainSelectedInstOperands, |
| 88432 | // GIR_Coverage, 57067, |
| 88433 | GIR_EraseRootFromParent_Done, |
| 88434 | // Label 5924: @226015 |
| 88435 | GIM_Reject, |
| 88436 | // Label 5922: @226016 |
| 88437 | GIM_Reject, |
| 88438 | // Label 5877: @226017 |
| 88439 | GIM_Try, /*On fail goto*//*Label 5925*/ GIMT_Encode4(226124), |
| 88440 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 88441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 88442 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 88443 | GIM_Try, /*On fail goto*//*Label 5926*/ GIMT_Encode4(226078), // Rule ID 57146 // |
| 88444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 88445 | // (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs) => (PseudoVFSGNJN_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 88446 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 88447 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88448 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E64), |
| 88451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88452 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88453 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88454 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88458 | GIR_RootConstrainSelectedInstOperands, |
| 88459 | // GIR_Coverage, 57146, |
| 88460 | GIR_EraseRootFromParent_Done, |
| 88461 | // Label 5926: @226078 |
| 88462 | GIM_Try, /*On fail goto*//*Label 5927*/ GIMT_Encode4(226123), // Rule ID 57147 // |
| 88463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 88464 | // (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs) => (PseudoVFSGNJN_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 88465 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 88466 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88467 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E64), |
| 88470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88471 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88472 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88473 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 88476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88477 | GIR_RootConstrainSelectedInstOperands, |
| 88478 | // GIR_Coverage, 57147, |
| 88479 | GIR_EraseRootFromParent_Done, |
| 88480 | // Label 5927: @226123 |
| 88481 | GIM_Reject, |
| 88482 | // Label 5925: @226124 |
| 88483 | GIM_Reject, |
| 88484 | // Label 5878: @226125 |
| 88485 | GIM_Try, /*On fail goto*//*Label 5928*/ GIMT_Encode4(226232), |
| 88486 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 88487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 88488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 88489 | GIM_Try, /*On fail goto*//*Label 5929*/ GIMT_Encode4(226186), // Rule ID 57006 // |
| 88490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 88491 | // (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs) => (PseudoVFSGNJN_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 88492 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 88493 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88494 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88495 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E16), |
| 88497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88498 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88499 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88504 | GIR_RootConstrainSelectedInstOperands, |
| 88505 | // GIR_Coverage, 57006, |
| 88506 | GIR_EraseRootFromParent_Done, |
| 88507 | // Label 5929: @226186 |
| 88508 | GIM_Try, /*On fail goto*//*Label 5930*/ GIMT_Encode4(226231), // Rule ID 57007 // |
| 88509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 88510 | // (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs) => (PseudoVFSGNJN_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 88511 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 88512 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88513 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E16), |
| 88516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88517 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88518 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88523 | GIR_RootConstrainSelectedInstOperands, |
| 88524 | // GIR_Coverage, 57007, |
| 88525 | GIR_EraseRootFromParent_Done, |
| 88526 | // Label 5930: @226231 |
| 88527 | GIM_Reject, |
| 88528 | // Label 5928: @226232 |
| 88529 | GIM_Reject, |
| 88530 | // Label 5879: @226233 |
| 88531 | GIM_Try, /*On fail goto*//*Label 5931*/ GIMT_Encode4(226340), |
| 88532 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 88533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 88534 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 88535 | GIM_Try, /*On fail goto*//*Label 5932*/ GIMT_Encode4(226294), // Rule ID 57086 // |
| 88536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 88537 | // (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs) => (PseudoVFSGNJN_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 88538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 88539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E32), |
| 88543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88545 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88546 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88550 | GIR_RootConstrainSelectedInstOperands, |
| 88551 | // GIR_Coverage, 57086, |
| 88552 | GIR_EraseRootFromParent_Done, |
| 88553 | // Label 5932: @226294 |
| 88554 | GIM_Try, /*On fail goto*//*Label 5933*/ GIMT_Encode4(226339), // Rule ID 57087 // |
| 88555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 88556 | // (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs) => (PseudoVFSGNJN_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 88557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 88558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E32), |
| 88562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88564 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88565 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 88568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88569 | GIR_RootConstrainSelectedInstOperands, |
| 88570 | // GIR_Coverage, 57087, |
| 88571 | GIR_EraseRootFromParent_Done, |
| 88572 | // Label 5933: @226339 |
| 88573 | GIM_Reject, |
| 88574 | // Label 5931: @226340 |
| 88575 | GIM_Reject, |
| 88576 | // Label 5880: @226341 |
| 88577 | GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(226448), |
| 88578 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 88579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 88580 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 88581 | GIM_Try, /*On fail goto*//*Label 5935*/ GIMT_Encode4(226402), // Rule ID 57026 // |
| 88582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 88583 | // (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs) => (PseudoVFSGNJN_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 88584 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 88585 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88586 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E16), |
| 88589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88590 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88591 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88592 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88596 | GIR_RootConstrainSelectedInstOperands, |
| 88597 | // GIR_Coverage, 57026, |
| 88598 | GIR_EraseRootFromParent_Done, |
| 88599 | // Label 5935: @226402 |
| 88600 | GIM_Try, /*On fail goto*//*Label 5936*/ GIMT_Encode4(226447), // Rule ID 57027 // |
| 88601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 88602 | // (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs) => (PseudoVFSGNJN_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 88603 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 88604 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 88605 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E16), |
| 88608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88609 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88610 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88611 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 88612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 88613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 88614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 88615 | GIR_RootConstrainSelectedInstOperands, |
| 88616 | // GIR_Coverage, 57027, |
| 88617 | GIR_EraseRootFromParent_Done, |
| 88618 | // Label 5936: @226447 |
| 88619 | GIM_Reject, |
| 88620 | // Label 5934: @226448 |
| 88621 | GIM_Reject, |
| 88622 | // Label 5881: @226449 |
| 88623 | GIM_Reject, |
| 88624 | // Label 59: @226450 |
| 88625 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 5939*/ GIMT_Encode4(226902), |
| 88626 | /*GILLT_s32*//*Label 5937*/ GIMT_Encode4(226469), |
| 88627 | /*GILLT_s64*//*Label 5938*/ GIMT_Encode4(226591), |
| 88628 | // Label 5937: @226469 |
| 88629 | GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(226590), |
| 88630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88631 | GIM_Try, /*On fail goto*//*Label 5941*/ GIMT_Encode4(226505), // Rule ID 2212 // |
| 88632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode0), |
| 88633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88634 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88635 | // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_S_H:{ *:[f32] } FPR16:{ *:[f16] }:$rs1, 0:{ *:[i64] }) |
| 88636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 88637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88638 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88640 | GIR_RootConstrainSelectedInstOperands, |
| 88641 | // GIR_Coverage, 2212, |
| 88642 | GIR_EraseRootFromParent_Done, |
| 88643 | // Label 5941: @226505 |
| 88644 | GIM_Try, /*On fail goto*//*Label 5942*/ GIMT_Encode4(226533), // Rule ID 2213 // |
| 88645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode1), |
| 88646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88647 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88648 | // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_S_H:{ *:[f32] } FPR16:{ *:[f16] }:$rs1, 0:{ *:[i32] }) |
| 88649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 88650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88651 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88653 | GIR_RootConstrainSelectedInstOperands, |
| 88654 | // GIR_Coverage, 2213, |
| 88655 | GIR_EraseRootFromParent_Done, |
| 88656 | // Label 5942: @226533 |
| 88657 | GIM_Try, /*On fail goto*//*Label 5943*/ GIMT_Encode4(226561), // Rule ID 2228 // |
| 88658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode0), |
| 88659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88660 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88661 | // (fpextend:{ *:[f32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_S_H_INX:{ *:[f32] } FPR16INX:{ *:[f16] }:$rs1, 0:{ *:[i64] }) |
| 88662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 88663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88664 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88666 | GIR_RootConstrainSelectedInstOperands, |
| 88667 | // GIR_Coverage, 2228, |
| 88668 | GIR_EraseRootFromParent_Done, |
| 88669 | // Label 5943: @226561 |
| 88670 | GIM_Try, /*On fail goto*//*Label 5944*/ GIMT_Encode4(226589), // Rule ID 2229 // |
| 88671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode1), |
| 88672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88673 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88674 | // (fpextend:{ *:[f32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_S_H_INX:{ *:[f32] } FPR16INX:{ *:[f16] }:$rs1, 0:{ *:[i32] }) |
| 88675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 88676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88677 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88679 | GIR_RootConstrainSelectedInstOperands, |
| 88680 | // GIR_Coverage, 2229, |
| 88681 | GIR_EraseRootFromParent_Done, |
| 88682 | // Label 5944: @226589 |
| 88683 | GIM_Reject, |
| 88684 | // Label 5940: @226590 |
| 88685 | GIM_Reject, |
| 88686 | // Label 5938: @226591 |
| 88687 | GIM_Try, /*On fail goto*//*Label 5945*/ GIMT_Encode4(226622), // Rule ID 1635 // |
| 88688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 88689 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88691 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88692 | // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_D_S:{ *:[f64] } FPR32:{ *:[f32] }:$rs1, 0:{ *:[i64] }) |
| 88693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S), |
| 88694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88695 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88697 | GIR_RootConstrainSelectedInstOperands, |
| 88698 | // GIR_Coverage, 1635, |
| 88699 | GIR_EraseRootFromParent_Done, |
| 88700 | // Label 5945: @226622 |
| 88701 | GIM_Try, /*On fail goto*//*Label 5946*/ GIMT_Encode4(226653), // Rule ID 1636 // |
| 88702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 88703 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88706 | // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_D_S:{ *:[f64] } FPR32:{ *:[f32] }:$rs1, 0:{ *:[i32] }) |
| 88707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S), |
| 88708 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88709 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88711 | GIR_RootConstrainSelectedInstOperands, |
| 88712 | // GIR_Coverage, 1636, |
| 88713 | GIR_EraseRootFromParent_Done, |
| 88714 | // Label 5946: @226653 |
| 88715 | GIM_Try, /*On fail goto*//*Label 5947*/ GIMT_Encode4(226684), // Rule ID 1640 // |
| 88716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 88717 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 88719 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88720 | // (fpextend:{ *:[f64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_D_S_INX:{ *:[f64] } FPR32INX:{ *:[f32] }:$rs1, 0:{ *:[i64] }) |
| 88721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S_INX), |
| 88722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88723 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88725 | GIR_RootConstrainSelectedInstOperands, |
| 88726 | // GIR_Coverage, 1640, |
| 88727 | GIR_EraseRootFromParent_Done, |
| 88728 | // Label 5947: @226684 |
| 88729 | GIM_Try, /*On fail goto*//*Label 5948*/ GIMT_Encode4(226715), // Rule ID 1647 // |
| 88730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 88731 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 88733 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88734 | // (fpextend:{ *:[f64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_D_S_IN32X:{ *:[f64] } FPR32INX:{ *:[f32] }:$rs1, 0:{ *:[i64] }) |
| 88735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S_IN32X), |
| 88736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88737 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88739 | GIR_RootConstrainSelectedInstOperands, |
| 88740 | // GIR_Coverage, 1647, |
| 88741 | GIR_EraseRootFromParent_Done, |
| 88742 | // Label 5948: @226715 |
| 88743 | GIM_Try, /*On fail goto*//*Label 5949*/ GIMT_Encode4(226746), // Rule ID 1648 // |
| 88744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 88745 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 88747 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88748 | // (fpextend:{ *:[f64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_D_S_IN32X:{ *:[f64] } FPR32INX:{ *:[f32] }:$rs1, 0:{ *:[i32] }) |
| 88749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S_IN32X), |
| 88750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88753 | GIR_RootConstrainSelectedInstOperands, |
| 88754 | // GIR_Coverage, 1648, |
| 88755 | GIR_EraseRootFromParent_Done, |
| 88756 | // Label 5949: @226746 |
| 88757 | GIM_Try, /*On fail goto*//*Label 5950*/ GIMT_Encode4(226777), // Rule ID 2348 // |
| 88758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode0), |
| 88759 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88761 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88762 | // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_D_H:{ *:[f64] } FPR16:{ *:[f16] }:$rs1, 0:{ *:[i64] }) |
| 88763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H), |
| 88764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88765 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88767 | GIR_RootConstrainSelectedInstOperands, |
| 88768 | // GIR_Coverage, 2348, |
| 88769 | GIR_EraseRootFromParent_Done, |
| 88770 | // Label 5950: @226777 |
| 88771 | GIM_Try, /*On fail goto*//*Label 5951*/ GIMT_Encode4(226808), // Rule ID 2349 // |
| 88772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode1), |
| 88773 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88776 | // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_D_H:{ *:[f64] } FPR16:{ *:[f16] }:$rs1, 0:{ *:[i32] }) |
| 88777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H), |
| 88778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88779 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88781 | GIR_RootConstrainSelectedInstOperands, |
| 88782 | // GIR_Coverage, 2349, |
| 88783 | GIR_EraseRootFromParent_Done, |
| 88784 | // Label 5951: @226808 |
| 88785 | GIM_Try, /*On fail goto*//*Label 5952*/ GIMT_Encode4(226839), // Rule ID 2360 // |
| 88786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode0), |
| 88787 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 88789 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88790 | // (fpextend:{ *:[f64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_D_H_IN32X:{ *:[f64] } FPR16INX:{ *:[f16] }:$rs1, 0:{ *:[i64] }) |
| 88791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H_IN32X), |
| 88792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88793 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88795 | GIR_RootConstrainSelectedInstOperands, |
| 88796 | // GIR_Coverage, 2360, |
| 88797 | GIR_EraseRootFromParent_Done, |
| 88798 | // Label 5952: @226839 |
| 88799 | GIM_Try, /*On fail goto*//*Label 5953*/ GIMT_Encode4(226870), // Rule ID 2361 // |
| 88800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode1), |
| 88801 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 88803 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88804 | // (fpextend:{ *:[f64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_D_H_IN32X:{ *:[f64] } FPR16INX:{ *:[f16] }:$rs1, 0:{ *:[i32] }) |
| 88805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H_IN32X), |
| 88806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88807 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88809 | GIR_RootConstrainSelectedInstOperands, |
| 88810 | // GIR_Coverage, 2361, |
| 88811 | GIR_EraseRootFromParent_Done, |
| 88812 | // Label 5953: @226870 |
| 88813 | GIM_Try, /*On fail goto*//*Label 5954*/ GIMT_Encode4(226901), // Rule ID 2369 // |
| 88814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV64_HwMode0), |
| 88815 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 88817 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88818 | // (fpextend:{ *:[f64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_D_H_INX:{ *:[f64] } FPR16INX:{ *:[f16] }:$rs1, 0:{ *:[i64] }) |
| 88819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H_INX), |
| 88820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88821 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88823 | GIR_RootConstrainSelectedInstOperands, |
| 88824 | // GIR_Coverage, 2369, |
| 88825 | GIR_EraseRootFromParent_Done, |
| 88826 | // Label 5954: @226901 |
| 88827 | GIM_Reject, |
| 88828 | // Label 5939: @226902 |
| 88829 | GIM_Reject, |
| 88830 | // Label 60: @226903 |
| 88831 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(28), /*)*//*default:*//*Label 5966*/ GIMT_Encode4(228898), |
| 88832 | /*GILLT_s16*//*Label 5955*/ GIMT_Encode4(227018), |
| 88833 | /*GILLT_s32*//*Label 5956*/ GIMT_Encode4(227298), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 88834 | /*GILLT_nxv1s16*//*Label 5957*/ GIMT_Encode4(227448), |
| 88835 | /*GILLT_nxv1s32*//*Label 5958*/ GIMT_Encode4(227650), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 88836 | /*GILLT_nxv2s16*//*Label 5959*/ GIMT_Encode4(227760), |
| 88837 | /*GILLT_nxv2s32*//*Label 5960*/ GIMT_Encode4(227962), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 88838 | /*GILLT_nxv4s16*//*Label 5961*/ GIMT_Encode4(228072), |
| 88839 | /*GILLT_nxv4s32*//*Label 5962*/ GIMT_Encode4(228274), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 88840 | /*GILLT_nxv8s16*//*Label 5963*/ GIMT_Encode4(228384), |
| 88841 | /*GILLT_nxv8s32*//*Label 5964*/ GIMT_Encode4(228586), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 88842 | /*GILLT_nxv16s16*//*Label 5965*/ GIMT_Encode4(228696), |
| 88843 | // Label 5955: @227018 |
| 88844 | GIM_Try, /*On fail goto*//*Label 5967*/ GIMT_Encode4(227049), // Rule ID 2208 // |
| 88845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode0), |
| 88846 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88849 | // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$rs1) => (FCVT_H_S:{ *:[f16] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 88850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 88851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88852 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88854 | GIR_RootConstrainSelectedInstOperands, |
| 88855 | // GIR_Coverage, 2208, |
| 88856 | GIR_EraseRootFromParent_Done, |
| 88857 | // Label 5967: @227049 |
| 88858 | GIM_Try, /*On fail goto*//*Label 5968*/ GIMT_Encode4(227080), // Rule ID 2209 // |
| 88859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode1), |
| 88860 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88862 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88863 | // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$rs1) => (FCVT_H_S:{ *:[f16] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 88864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 88865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88866 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88868 | GIR_RootConstrainSelectedInstOperands, |
| 88869 | // GIR_Coverage, 2209, |
| 88870 | GIR_EraseRootFromParent_Done, |
| 88871 | // Label 5968: @227080 |
| 88872 | GIM_Try, /*On fail goto*//*Label 5969*/ GIMT_Encode4(227111), // Rule ID 2224 // |
| 88873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode0), |
| 88874 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88877 | // (fpround:{ *:[f16] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } FPR32INX:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 88878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 88879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88880 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88882 | GIR_RootConstrainSelectedInstOperands, |
| 88883 | // GIR_Coverage, 2224, |
| 88884 | GIR_EraseRootFromParent_Done, |
| 88885 | // Label 5969: @227111 |
| 88886 | GIM_Try, /*On fail goto*//*Label 5970*/ GIMT_Encode4(227142), // Rule ID 2225 // |
| 88887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode1), |
| 88888 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88890 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 88891 | // (fpround:{ *:[f16] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } FPR32INX:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 88892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 88893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88894 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88896 | GIR_RootConstrainSelectedInstOperands, |
| 88897 | // GIR_Coverage, 2225, |
| 88898 | GIR_EraseRootFromParent_Done, |
| 88899 | // Label 5970: @227142 |
| 88900 | GIM_Try, /*On fail goto*//*Label 5971*/ GIMT_Encode4(227173), // Rule ID 2344 // |
| 88901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode0), |
| 88902 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88904 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88905 | // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$rs1) => (FCVT_H_D:{ *:[f16] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 88906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D), |
| 88907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88910 | GIR_RootConstrainSelectedInstOperands, |
| 88911 | // GIR_Coverage, 2344, |
| 88912 | GIR_EraseRootFromParent_Done, |
| 88913 | // Label 5971: @227173 |
| 88914 | GIM_Try, /*On fail goto*//*Label 5972*/ GIMT_Encode4(227204), // Rule ID 2345 // |
| 88915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode1), |
| 88916 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 88918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88919 | // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$rs1) => (FCVT_H_D:{ *:[f16] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 88920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D), |
| 88921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88922 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88924 | GIR_RootConstrainSelectedInstOperands, |
| 88925 | // GIR_Coverage, 2345, |
| 88926 | GIR_EraseRootFromParent_Done, |
| 88927 | // Label 5972: @227204 |
| 88928 | GIM_Try, /*On fail goto*//*Label 5973*/ GIMT_Encode4(227235), // Rule ID 2356 // |
| 88929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode0), |
| 88930 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88932 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 88933 | // (fpround:{ *:[f16] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_H_D_IN32X:{ *:[f16] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 88934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D_IN32X), |
| 88935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88936 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88938 | GIR_RootConstrainSelectedInstOperands, |
| 88939 | // GIR_Coverage, 2356, |
| 88940 | GIR_EraseRootFromParent_Done, |
| 88941 | // Label 5973: @227235 |
| 88942 | GIM_Try, /*On fail goto*//*Label 5974*/ GIMT_Encode4(227266), // Rule ID 2357 // |
| 88943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode1), |
| 88944 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 88947 | // (fpround:{ *:[f16] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_H_D_IN32X:{ *:[f16] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 88948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D_IN32X), |
| 88949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88950 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88952 | GIR_RootConstrainSelectedInstOperands, |
| 88953 | // GIR_Coverage, 2357, |
| 88954 | GIR_EraseRootFromParent_Done, |
| 88955 | // Label 5974: @227266 |
| 88956 | GIM_Try, /*On fail goto*//*Label 5975*/ GIMT_Encode4(227297), // Rule ID 2367 // |
| 88957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV64_HwMode0), |
| 88958 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 88960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 88961 | // (fpround:{ *:[f16] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_H_D_INX:{ *:[f16] } FPR64INX:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 88962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D_INX), |
| 88963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88964 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88966 | GIR_RootConstrainSelectedInstOperands, |
| 88967 | // GIR_Coverage, 2367, |
| 88968 | GIR_EraseRootFromParent_Done, |
| 88969 | // Label 5975: @227297 |
| 88970 | GIM_Reject, |
| 88971 | // Label 5956: @227298 |
| 88972 | GIM_Try, /*On fail goto*//*Label 5976*/ GIMT_Encode4(227447), |
| 88973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88974 | GIM_Try, /*On fail goto*//*Label 5977*/ GIMT_Encode4(227334), // Rule ID 1631 // |
| 88975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 88976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88977 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88978 | // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 88979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D), |
| 88980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88981 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88983 | GIR_RootConstrainSelectedInstOperands, |
| 88984 | // GIR_Coverage, 1631, |
| 88985 | GIR_EraseRootFromParent_Done, |
| 88986 | // Label 5977: @227334 |
| 88987 | GIM_Try, /*On fail goto*//*Label 5978*/ GIMT_Encode4(227362), // Rule ID 1632 // |
| 88988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 88989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 88990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 88991 | // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 88992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D), |
| 88993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 88994 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 88995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 88996 | GIR_RootConstrainSelectedInstOperands, |
| 88997 | // GIR_Coverage, 1632, |
| 88998 | GIR_EraseRootFromParent_Done, |
| 88999 | // Label 5978: @227362 |
| 89000 | GIM_Try, /*On fail goto*//*Label 5979*/ GIMT_Encode4(227390), // Rule ID 1638 // |
| 89001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 89002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 89003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89004 | // (fpround:{ *:[f32] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_S_D_INX:{ *:[f32] } FPR64INX:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 89005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D_INX), |
| 89006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89007 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89009 | GIR_RootConstrainSelectedInstOperands, |
| 89010 | // GIR_Coverage, 1638, |
| 89011 | GIR_EraseRootFromParent_Done, |
| 89012 | // Label 5979: @227390 |
| 89013 | GIM_Try, /*On fail goto*//*Label 5980*/ GIMT_Encode4(227418), // Rule ID 1643 // |
| 89014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 89015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 89016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 89017 | // (fpround:{ *:[f32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_S_D_IN32X:{ *:[f32] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 89018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D_IN32X), |
| 89019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89020 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89022 | GIR_RootConstrainSelectedInstOperands, |
| 89023 | // GIR_Coverage, 1643, |
| 89024 | GIR_EraseRootFromParent_Done, |
| 89025 | // Label 5980: @227418 |
| 89026 | GIM_Try, /*On fail goto*//*Label 5981*/ GIMT_Encode4(227446), // Rule ID 1644 // |
| 89027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 89028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 89029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 89030 | // (fpround:{ *:[f32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_S_D_IN32X:{ *:[f32] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 89031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D_IN32X), |
| 89032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89033 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89035 | GIR_RootConstrainSelectedInstOperands, |
| 89036 | // GIR_Coverage, 1644, |
| 89037 | GIR_EraseRootFromParent_Done, |
| 89038 | // Label 5981: @227446 |
| 89039 | GIM_Reject, |
| 89040 | // Label 5976: @227447 |
| 89041 | GIM_Reject, |
| 89042 | // Label 5957: @227448 |
| 89043 | GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(227649), |
| 89044 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 89045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89046 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89047 | GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(227510), // Rule ID 59394 // |
| 89048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode0), |
| 89049 | // (fpround:{ *:[nxv1f16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVT_F_F_W_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89050 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 89051 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89052 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_MF4_E16), |
| 89055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89056 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89057 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89062 | GIR_RootConstrainSelectedInstOperands, |
| 89063 | // GIR_Coverage, 59394, |
| 89064 | GIR_EraseRootFromParent_Done, |
| 89065 | // Label 5983: @227510 |
| 89066 | GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(227556), // Rule ID 59395 // |
| 89067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 89068 | // (fpround:{ *:[nxv1f16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVT_F_F_W_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 89070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_MF4_E16), |
| 89074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89076 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89081 | GIR_RootConstrainSelectedInstOperands, |
| 89082 | // GIR_Coverage, 59395, |
| 89083 | GIR_EraseRootFromParent_Done, |
| 89084 | // Label 5984: @227556 |
| 89085 | GIM_Try, /*On fail goto*//*Label 5985*/ GIMT_Encode4(227602), // Rule ID 59412 // |
| 89086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode0), |
| 89087 | // (fpround:{ *:[nxv1bf16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_MF4_E16:{ *:[nxv1bf16] } (IMPLICIT_DEF:{ *:[nxv1bf16] }), VR:{ *:[nxv1f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89088 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 89089 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89090 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_MF4_E16), |
| 89093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89095 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89100 | GIR_RootConstrainSelectedInstOperands, |
| 89101 | // GIR_Coverage, 59412, |
| 89102 | GIR_EraseRootFromParent_Done, |
| 89103 | // Label 5985: @227602 |
| 89104 | GIM_Try, /*On fail goto*//*Label 5986*/ GIMT_Encode4(227648), // Rule ID 59413 // |
| 89105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 89106 | // (fpround:{ *:[nxv1bf16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_MF4_E16:{ *:[nxv1bf16] } (IMPLICIT_DEF:{ *:[nxv1bf16] }), VR:{ *:[nxv1f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89107 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 89108 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89109 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_MF4_E16), |
| 89112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89113 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89114 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89119 | GIR_RootConstrainSelectedInstOperands, |
| 89120 | // GIR_Coverage, 59413, |
| 89121 | GIR_EraseRootFromParent_Done, |
| 89122 | // Label 5986: @227648 |
| 89123 | GIM_Reject, |
| 89124 | // Label 5982: @227649 |
| 89125 | GIM_Reject, |
| 89126 | // Label 5958: @227650 |
| 89127 | GIM_Try, /*On fail goto*//*Label 5987*/ GIMT_Encode4(227759), |
| 89128 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 89129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89130 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89131 | GIM_Try, /*On fail goto*//*Label 5988*/ GIMT_Encode4(227712), // Rule ID 59404 // |
| 89132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode0), |
| 89133 | // (fpround:{ *:[nxv1f32] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFNCVT_F_F_W_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 89134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 89135 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89136 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_MF2_E32), |
| 89139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89141 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89146 | GIR_RootConstrainSelectedInstOperands, |
| 89147 | // GIR_Coverage, 59404, |
| 89148 | GIR_EraseRootFromParent_Done, |
| 89149 | // Label 5988: @227712 |
| 89150 | GIM_Try, /*On fail goto*//*Label 5989*/ GIMT_Encode4(227758), // Rule ID 59405 // |
| 89151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode1), |
| 89152 | // (fpround:{ *:[nxv1f32] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFNCVT_F_F_W_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 89153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 89154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_MF2_E32), |
| 89158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89165 | GIR_RootConstrainSelectedInstOperands, |
| 89166 | // GIR_Coverage, 59405, |
| 89167 | GIR_EraseRootFromParent_Done, |
| 89168 | // Label 5989: @227758 |
| 89169 | GIM_Reject, |
| 89170 | // Label 5987: @227759 |
| 89171 | GIM_Reject, |
| 89172 | // Label 5959: @227760 |
| 89173 | GIM_Try, /*On fail goto*//*Label 5990*/ GIMT_Encode4(227961), |
| 89174 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 89175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89176 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89177 | GIM_Try, /*On fail goto*//*Label 5991*/ GIMT_Encode4(227822), // Rule ID 59396 // |
| 89178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode0), |
| 89179 | // (fpround:{ *:[nxv2f16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVT_F_F_W_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89180 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 89181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_MF2_E16), |
| 89185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89187 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89192 | GIR_RootConstrainSelectedInstOperands, |
| 89193 | // GIR_Coverage, 59396, |
| 89194 | GIR_EraseRootFromParent_Done, |
| 89195 | // Label 5991: @227822 |
| 89196 | GIM_Try, /*On fail goto*//*Label 5992*/ GIMT_Encode4(227868), // Rule ID 59397 // |
| 89197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 89198 | // (fpround:{ *:[nxv2f16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVT_F_F_W_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89199 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 89200 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89201 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_MF2_E16), |
| 89204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89205 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89206 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89211 | GIR_RootConstrainSelectedInstOperands, |
| 89212 | // GIR_Coverage, 59397, |
| 89213 | GIR_EraseRootFromParent_Done, |
| 89214 | // Label 5992: @227868 |
| 89215 | GIM_Try, /*On fail goto*//*Label 5993*/ GIMT_Encode4(227914), // Rule ID 59414 // |
| 89216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode0), |
| 89217 | // (fpround:{ *:[nxv2bf16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_MF2_E16:{ *:[nxv2bf16] } (IMPLICIT_DEF:{ *:[nxv2bf16] }), VR:{ *:[nxv2f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89218 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 89219 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89220 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_MF2_E16), |
| 89223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89224 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89225 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89230 | GIR_RootConstrainSelectedInstOperands, |
| 89231 | // GIR_Coverage, 59414, |
| 89232 | GIR_EraseRootFromParent_Done, |
| 89233 | // Label 5993: @227914 |
| 89234 | GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(227960), // Rule ID 59415 // |
| 89235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 89236 | // (fpround:{ *:[nxv2bf16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_MF2_E16:{ *:[nxv2bf16] } (IMPLICIT_DEF:{ *:[nxv2bf16] }), VR:{ *:[nxv2f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89237 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 89238 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89239 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89240 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_MF2_E16), |
| 89242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89243 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89244 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89249 | GIR_RootConstrainSelectedInstOperands, |
| 89250 | // GIR_Coverage, 59415, |
| 89251 | GIR_EraseRootFromParent_Done, |
| 89252 | // Label 5994: @227960 |
| 89253 | GIM_Reject, |
| 89254 | // Label 5990: @227961 |
| 89255 | GIM_Reject, |
| 89256 | // Label 5960: @227962 |
| 89257 | GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(228071), |
| 89258 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 89259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 89261 | GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(228024), // Rule ID 59406 // |
| 89262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode0), |
| 89263 | // (fpround:{ *:[nxv2f32] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFNCVT_F_F_W_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VRM2:{ *:[nxv2f64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 89264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 89265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M1_E32), |
| 89269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89270 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89276 | GIR_RootConstrainSelectedInstOperands, |
| 89277 | // GIR_Coverage, 59406, |
| 89278 | GIR_EraseRootFromParent_Done, |
| 89279 | // Label 5996: @228024 |
| 89280 | GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(228070), // Rule ID 59407 // |
| 89281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode1), |
| 89282 | // (fpround:{ *:[nxv2f32] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFNCVT_F_F_W_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VRM2:{ *:[nxv2f64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 89283 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 89284 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89285 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M1_E32), |
| 89288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89289 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89290 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89295 | GIR_RootConstrainSelectedInstOperands, |
| 89296 | // GIR_Coverage, 59407, |
| 89297 | GIR_EraseRootFromParent_Done, |
| 89298 | // Label 5997: @228070 |
| 89299 | GIM_Reject, |
| 89300 | // Label 5995: @228071 |
| 89301 | GIM_Reject, |
| 89302 | // Label 5961: @228072 |
| 89303 | GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(228273), |
| 89304 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 89305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 89306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 89307 | GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(228134), // Rule ID 59398 // |
| 89308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode0), |
| 89309 | // (fpround:{ *:[nxv4f16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVT_F_F_W_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VRM2:{ *:[nxv4f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89310 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 89311 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89312 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M1_E16), |
| 89315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89316 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89317 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89322 | GIR_RootConstrainSelectedInstOperands, |
| 89323 | // GIR_Coverage, 59398, |
| 89324 | GIR_EraseRootFromParent_Done, |
| 89325 | // Label 5999: @228134 |
| 89326 | GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(228180), // Rule ID 59399 // |
| 89327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 89328 | // (fpround:{ *:[nxv4f16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVT_F_F_W_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VRM2:{ *:[nxv4f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89329 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 89330 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89331 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M1_E16), |
| 89334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89335 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89336 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89341 | GIR_RootConstrainSelectedInstOperands, |
| 89342 | // GIR_Coverage, 59399, |
| 89343 | GIR_EraseRootFromParent_Done, |
| 89344 | // Label 6000: @228180 |
| 89345 | GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(228226), // Rule ID 59416 // |
| 89346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode0), |
| 89347 | // (fpround:{ *:[nxv4bf16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_M1_E16:{ *:[nxv4bf16] } (IMPLICIT_DEF:{ *:[nxv4bf16] }), VRM2:{ *:[nxv4f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89348 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 89349 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89350 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_M1_E16), |
| 89353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89354 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89355 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89360 | GIR_RootConstrainSelectedInstOperands, |
| 89361 | // GIR_Coverage, 59416, |
| 89362 | GIR_EraseRootFromParent_Done, |
| 89363 | // Label 6001: @228226 |
| 89364 | GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(228272), // Rule ID 59417 // |
| 89365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 89366 | // (fpround:{ *:[nxv4bf16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_M1_E16:{ *:[nxv4bf16] } (IMPLICIT_DEF:{ *:[nxv4bf16] }), VRM2:{ *:[nxv4f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89367 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 89368 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89369 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_M1_E16), |
| 89372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89373 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89374 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89379 | GIR_RootConstrainSelectedInstOperands, |
| 89380 | // GIR_Coverage, 59417, |
| 89381 | GIR_EraseRootFromParent_Done, |
| 89382 | // Label 6002: @228272 |
| 89383 | GIM_Reject, |
| 89384 | // Label 5998: @228273 |
| 89385 | GIM_Reject, |
| 89386 | // Label 5962: @228274 |
| 89387 | GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(228383), |
| 89388 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 89389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 89390 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 89391 | GIM_Try, /*On fail goto*//*Label 6004*/ GIMT_Encode4(228336), // Rule ID 59408 // |
| 89392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode0), |
| 89393 | // (fpround:{ *:[nxv4f32] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFNCVT_F_F_W_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM4:{ *:[nxv4f64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 89394 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 89395 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89396 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M2_E32), |
| 89399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89400 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89401 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89406 | GIR_RootConstrainSelectedInstOperands, |
| 89407 | // GIR_Coverage, 59408, |
| 89408 | GIR_EraseRootFromParent_Done, |
| 89409 | // Label 6004: @228336 |
| 89410 | GIM_Try, /*On fail goto*//*Label 6005*/ GIMT_Encode4(228382), // Rule ID 59409 // |
| 89411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode1), |
| 89412 | // (fpround:{ *:[nxv4f32] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFNCVT_F_F_W_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM4:{ *:[nxv4f64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 89413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 89414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89415 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M2_E32), |
| 89418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89419 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89420 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89425 | GIR_RootConstrainSelectedInstOperands, |
| 89426 | // GIR_Coverage, 59409, |
| 89427 | GIR_EraseRootFromParent_Done, |
| 89428 | // Label 6005: @228382 |
| 89429 | GIM_Reject, |
| 89430 | // Label 6003: @228383 |
| 89431 | GIM_Reject, |
| 89432 | // Label 5963: @228384 |
| 89433 | GIM_Try, /*On fail goto*//*Label 6006*/ GIMT_Encode4(228585), |
| 89434 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 89435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 89436 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 89437 | GIM_Try, /*On fail goto*//*Label 6007*/ GIMT_Encode4(228446), // Rule ID 59400 // |
| 89438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode0), |
| 89439 | // (fpround:{ *:[nxv8f16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVT_F_F_W_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM4:{ *:[nxv8f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89440 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 89441 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89442 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89443 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M2_E16), |
| 89445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89446 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89447 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89452 | GIR_RootConstrainSelectedInstOperands, |
| 89453 | // GIR_Coverage, 59400, |
| 89454 | GIR_EraseRootFromParent_Done, |
| 89455 | // Label 6007: @228446 |
| 89456 | GIM_Try, /*On fail goto*//*Label 6008*/ GIMT_Encode4(228492), // Rule ID 59401 // |
| 89457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 89458 | // (fpround:{ *:[nxv8f16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVT_F_F_W_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM4:{ *:[nxv8f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89459 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 89460 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89461 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M2_E16), |
| 89464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89465 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89466 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89471 | GIR_RootConstrainSelectedInstOperands, |
| 89472 | // GIR_Coverage, 59401, |
| 89473 | GIR_EraseRootFromParent_Done, |
| 89474 | // Label 6008: @228492 |
| 89475 | GIM_Try, /*On fail goto*//*Label 6009*/ GIMT_Encode4(228538), // Rule ID 59418 // |
| 89476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode0), |
| 89477 | // (fpround:{ *:[nxv8bf16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_M2_E16:{ *:[nxv8bf16] } (IMPLICIT_DEF:{ *:[nxv8bf16] }), VRM4:{ *:[nxv8f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89478 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 89479 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89480 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_M2_E16), |
| 89483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89484 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89485 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89490 | GIR_RootConstrainSelectedInstOperands, |
| 89491 | // GIR_Coverage, 59418, |
| 89492 | GIR_EraseRootFromParent_Done, |
| 89493 | // Label 6009: @228538 |
| 89494 | GIM_Try, /*On fail goto*//*Label 6010*/ GIMT_Encode4(228584), // Rule ID 59419 // |
| 89495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 89496 | // (fpround:{ *:[nxv8bf16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_M2_E16:{ *:[nxv8bf16] } (IMPLICIT_DEF:{ *:[nxv8bf16] }), VRM4:{ *:[nxv8f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 89498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89499 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_M2_E16), |
| 89502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89504 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89509 | GIR_RootConstrainSelectedInstOperands, |
| 89510 | // GIR_Coverage, 59419, |
| 89511 | GIR_EraseRootFromParent_Done, |
| 89512 | // Label 6010: @228584 |
| 89513 | GIM_Reject, |
| 89514 | // Label 6006: @228585 |
| 89515 | GIM_Reject, |
| 89516 | // Label 5964: @228586 |
| 89517 | GIM_Try, /*On fail goto*//*Label 6011*/ GIMT_Encode4(228695), |
| 89518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 89519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 89520 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 89521 | GIM_Try, /*On fail goto*//*Label 6012*/ GIMT_Encode4(228648), // Rule ID 59410 // |
| 89522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode0), |
| 89523 | // (fpround:{ *:[nxv8f32] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFNCVT_F_F_W_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM8:{ *:[nxv8f64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 89524 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 89525 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89526 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M4_E32), |
| 89529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89530 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89531 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89536 | GIR_RootConstrainSelectedInstOperands, |
| 89537 | // GIR_Coverage, 59410, |
| 89538 | GIR_EraseRootFromParent_Done, |
| 89539 | // Label 6012: @228648 |
| 89540 | GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(228694), // Rule ID 59411 // |
| 89541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode1), |
| 89542 | // (fpround:{ *:[nxv8f32] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFNCVT_F_F_W_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM8:{ *:[nxv8f64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 89543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 89544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M4_E32), |
| 89548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89550 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 89554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89555 | GIR_RootConstrainSelectedInstOperands, |
| 89556 | // GIR_Coverage, 59411, |
| 89557 | GIR_EraseRootFromParent_Done, |
| 89558 | // Label 6013: @228694 |
| 89559 | GIM_Reject, |
| 89560 | // Label 6011: @228695 |
| 89561 | GIM_Reject, |
| 89562 | // Label 5965: @228696 |
| 89563 | GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(228897), |
| 89564 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 89565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 89566 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 89567 | GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(228758), // Rule ID 59402 // |
| 89568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode0), |
| 89569 | // (fpround:{ *:[nxv16f16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVT_F_F_W_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM8:{ *:[nxv16f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89570 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 89571 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89572 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89573 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M4_E16), |
| 89575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89576 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89577 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89582 | GIR_RootConstrainSelectedInstOperands, |
| 89583 | // GIR_Coverage, 59402, |
| 89584 | GIR_EraseRootFromParent_Done, |
| 89585 | // Label 6015: @228758 |
| 89586 | GIM_Try, /*On fail goto*//*Label 6016*/ GIMT_Encode4(228804), // Rule ID 59403 // |
| 89587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16Minimal_HwMode1), |
| 89588 | // (fpround:{ *:[nxv16f16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVT_F_F_W_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM8:{ *:[nxv16f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89589 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 89590 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89591 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_F_W_M4_E16), |
| 89594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89595 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89596 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89601 | GIR_RootConstrainSelectedInstOperands, |
| 89602 | // GIR_Coverage, 59403, |
| 89603 | GIR_EraseRootFromParent_Done, |
| 89604 | // Label 6016: @228804 |
| 89605 | GIM_Try, /*On fail goto*//*Label 6017*/ GIMT_Encode4(228850), // Rule ID 59420 // |
| 89606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode0), |
| 89607 | // (fpround:{ *:[nxv16bf16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_M4_E16:{ *:[nxv16bf16] } (IMPLICIT_DEF:{ *:[nxv16bf16] }), VRM8:{ *:[nxv16f32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 89608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 89609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_M4_E16), |
| 89613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89620 | GIR_RootConstrainSelectedInstOperands, |
| 89621 | // GIR_Coverage, 59420, |
| 89622 | GIR_EraseRootFromParent_Done, |
| 89623 | // Label 6017: @228850 |
| 89624 | GIM_Try, /*On fail goto*//*Label 6018*/ GIMT_Encode4(228896), // Rule ID 59421 // |
| 89625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsBF16_HwMode1), |
| 89626 | // (fpround:{ *:[nxv16bf16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVTBF16_F_F_W_M4_E16:{ *:[nxv16bf16] } (IMPLICIT_DEF:{ *:[nxv16bf16] }), VRM8:{ *:[nxv16f32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 89627 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 89628 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 89629 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89630 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVTBF16_F_F_W_M4_E16), |
| 89632 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89633 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89634 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 89636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 89637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 89638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 89639 | GIR_RootConstrainSelectedInstOperands, |
| 89640 | // GIR_Coverage, 59421, |
| 89641 | GIR_EraseRootFromParent_Done, |
| 89642 | // Label 6018: @228896 |
| 89643 | GIM_Reject, |
| 89644 | // Label 6014: @228897 |
| 89645 | GIM_Reject, |
| 89646 | // Label 5966: @228898 |
| 89647 | GIM_Reject, |
| 89648 | // Label 61: @228899 |
| 89649 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(32), /*)*//*default:*//*Label 6042*/ GIMT_Encode4(234261), |
| 89650 | /*GILLT_s32*//*Label 6019*/ GIMT_Encode4(229026), |
| 89651 | /*GILLT_s64*//*Label 6020*/ GIMT_Encode4(229717), GIMT_Encode4(0), |
| 89652 | /*GILLT_nxv1s8*//*Label 6021*/ GIMT_Encode4(230063), |
| 89653 | /*GILLT_nxv1s16*//*Label 6022*/ GIMT_Encode4(230167), |
| 89654 | /*GILLT_nxv1s32*//*Label 6023*/ GIMT_Encode4(230384), |
| 89655 | /*GILLT_nxv1s64*//*Label 6024*/ GIMT_Encode4(230709), GIMT_Encode4(0), |
| 89656 | /*GILLT_nxv2s8*//*Label 6025*/ GIMT_Encode4(230926), |
| 89657 | /*GILLT_nxv2s16*//*Label 6026*/ GIMT_Encode4(231030), |
| 89658 | /*GILLT_nxv2s32*//*Label 6027*/ GIMT_Encode4(231247), |
| 89659 | /*GILLT_nxv2s64*//*Label 6028*/ GIMT_Encode4(231572), GIMT_Encode4(0), |
| 89660 | /*GILLT_nxv4s8*//*Label 6029*/ GIMT_Encode4(231789), |
| 89661 | /*GILLT_nxv4s16*//*Label 6030*/ GIMT_Encode4(231893), |
| 89662 | /*GILLT_nxv4s32*//*Label 6031*/ GIMT_Encode4(232110), |
| 89663 | /*GILLT_nxv4s64*//*Label 6032*/ GIMT_Encode4(232435), GIMT_Encode4(0), |
| 89664 | /*GILLT_nxv8s8*//*Label 6033*/ GIMT_Encode4(232652), |
| 89665 | /*GILLT_nxv8s16*//*Label 6034*/ GIMT_Encode4(232756), |
| 89666 | /*GILLT_nxv8s32*//*Label 6035*/ GIMT_Encode4(232973), |
| 89667 | /*GILLT_nxv8s64*//*Label 6036*/ GIMT_Encode4(233298), GIMT_Encode4(0), |
| 89668 | /*GILLT_nxv16s8*//*Label 6037*/ GIMT_Encode4(233515), |
| 89669 | /*GILLT_nxv16s16*//*Label 6038*/ GIMT_Encode4(233619), |
| 89670 | /*GILLT_nxv16s32*//*Label 6039*/ GIMT_Encode4(233836), GIMT_Encode4(0), |
| 89671 | /*GILLT_nxv32s8*//*Label 6040*/ GIMT_Encode4(234053), |
| 89672 | /*GILLT_nxv32s16*//*Label 6041*/ GIMT_Encode4(234157), |
| 89673 | // Label 6019: @229026 |
| 89674 | GIM_Try, /*On fail goto*//*Label 6043*/ GIMT_Encode4(229057), // Rule ID 1523 // |
| 89675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 89676 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 89677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89678 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 89679 | // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 89680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 89681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89684 | GIR_RootConstrainSelectedInstOperands, |
| 89685 | // GIR_Coverage, 1523, |
| 89686 | GIR_EraseRootFromParent_Done, |
| 89687 | // Label 6043: @229057 |
| 89688 | GIM_Try, /*On fail goto*//*Label 6044*/ GIMT_Encode4(229088), // Rule ID 1524 // |
| 89689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 89690 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 89691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 89693 | // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] }) |
| 89694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 89695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89696 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89698 | GIR_RootConstrainSelectedInstOperands, |
| 89699 | // GIR_Coverage, 1524, |
| 89700 | GIR_EraseRootFromParent_Done, |
| 89701 | // Label 6044: @229088 |
| 89702 | GIM_Try, /*On fail goto*//*Label 6045*/ GIMT_Encode4(229119), // Rule ID 1549 // |
| 89703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 89704 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 89705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 89707 | // (fp_to_sint:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 89708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 89709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89710 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89712 | GIR_RootConstrainSelectedInstOperands, |
| 89713 | // GIR_Coverage, 1549, |
| 89714 | GIR_EraseRootFromParent_Done, |
| 89715 | // Label 6045: @229119 |
| 89716 | GIM_Try, /*On fail goto*//*Label 6046*/ GIMT_Encode4(229150), // Rule ID 1550 // |
| 89717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 89718 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 89719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89720 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 89721 | // (fp_to_sint:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] }) |
| 89722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 89723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89726 | GIR_RootConstrainSelectedInstOperands, |
| 89727 | // GIR_Coverage, 1550, |
| 89728 | GIR_EraseRootFromParent_Done, |
| 89729 | // Label 6046: @229150 |
| 89730 | GIM_Try, /*On fail goto*//*Label 6047*/ GIMT_Encode4(229181), // Rule ID 1904 // |
| 89731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 89732 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 89733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 89735 | // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 89736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D), |
| 89737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89738 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89740 | GIR_RootConstrainSelectedInstOperands, |
| 89741 | // GIR_Coverage, 1904, |
| 89742 | GIR_EraseRootFromParent_Done, |
| 89743 | // Label 6047: @229181 |
| 89744 | GIM_Try, /*On fail goto*//*Label 6048*/ GIMT_Encode4(229212), // Rule ID 1905 // |
| 89745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 89746 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 89747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89748 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 89749 | // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) |
| 89750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D), |
| 89751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89752 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89754 | GIR_RootConstrainSelectedInstOperands, |
| 89755 | // GIR_Coverage, 1905, |
| 89756 | GIR_EraseRootFromParent_Done, |
| 89757 | // Label 6048: @229212 |
| 89758 | GIM_Try, /*On fail goto*//*Label 6049*/ GIMT_Encode4(229243), // Rule ID 1930 // |
| 89759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 89760 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 89761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 89763 | // (fp_to_sint:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_W_D_IN32X:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 89764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D_IN32X), |
| 89765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89768 | GIR_RootConstrainSelectedInstOperands, |
| 89769 | // GIR_Coverage, 1930, |
| 89770 | GIR_EraseRootFromParent_Done, |
| 89771 | // Label 6049: @229243 |
| 89772 | GIM_Try, /*On fail goto*//*Label 6050*/ GIMT_Encode4(229274), // Rule ID 1931 // |
| 89773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 89774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 89775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 89777 | // (fp_to_sint:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_W_D_IN32X:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, 1:{ *:[i32] }) |
| 89778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D_IN32X), |
| 89779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89782 | GIR_RootConstrainSelectedInstOperands, |
| 89783 | // GIR_Coverage, 1931, |
| 89784 | GIR_EraseRootFromParent_Done, |
| 89785 | // Label 6050: @229274 |
| 89786 | GIM_Try, /*On fail goto*//*Label 6051*/ GIMT_Encode4(229305), // Rule ID 2240 // |
| 89787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 89788 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 89791 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 89792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H), |
| 89793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89794 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89796 | GIR_RootConstrainSelectedInstOperands, |
| 89797 | // GIR_Coverage, 2240, |
| 89798 | GIR_EraseRootFromParent_Done, |
| 89799 | // Label 6051: @229305 |
| 89800 | GIM_Try, /*On fail goto*//*Label 6052*/ GIMT_Encode4(229336), // Rule ID 2241 // |
| 89801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 89802 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89804 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 89805 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i32] }) |
| 89806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H), |
| 89807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89808 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89810 | GIR_RootConstrainSelectedInstOperands, |
| 89811 | // GIR_Coverage, 2241, |
| 89812 | GIR_EraseRootFromParent_Done, |
| 89813 | // Label 6052: @229336 |
| 89814 | GIM_Try, /*On fail goto*//*Label 6053*/ GIMT_Encode4(229367), // Rule ID 2266 // |
| 89815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 89816 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89818 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 89819 | // (fp_to_sint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 89820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H_INX), |
| 89821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89822 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89824 | GIR_RootConstrainSelectedInstOperands, |
| 89825 | // GIR_Coverage, 2266, |
| 89826 | GIR_EraseRootFromParent_Done, |
| 89827 | // Label 6053: @229367 |
| 89828 | GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(229398), // Rule ID 2267 // |
| 89829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 89830 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89832 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 89833 | // (fp_to_sint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i32] }) |
| 89834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H_INX), |
| 89835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89836 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89838 | GIR_RootConstrainSelectedInstOperands, |
| 89839 | // GIR_Coverage, 2267, |
| 89840 | GIR_EraseRootFromParent_Done, |
| 89841 | // Label 6054: @229398 |
| 89842 | GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(229451), // Rule ID 2374 // |
| 89843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0), |
| 89844 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 89847 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 89848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 89849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 89850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89851 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 89852 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 89853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 89855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89856 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89858 | GIR_RootConstrainSelectedInstOperands, |
| 89859 | // GIR_Coverage, 2374, |
| 89860 | GIR_EraseRootFromParent_Done, |
| 89861 | // Label 6055: @229451 |
| 89862 | GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(229504), // Rule ID 2375 // |
| 89863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1), |
| 89864 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89866 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 89867 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 1:{ *:[i32] }) |
| 89868 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 89869 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 89870 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89871 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 89872 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 89873 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 89875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89876 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89878 | GIR_RootConstrainSelectedInstOperands, |
| 89879 | // GIR_Coverage, 2375, |
| 89880 | GIR_EraseRootFromParent_Done, |
| 89881 | // Label 6056: @229504 |
| 89882 | GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(229557), // Rule ID 2398 // |
| 89883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0), |
| 89884 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 89887 | // (fp_to_sint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 89888 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 89889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 89890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89891 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 89892 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 89893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 89895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89896 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89898 | GIR_RootConstrainSelectedInstOperands, |
| 89899 | // GIR_Coverage, 2398, |
| 89900 | GIR_EraseRootFromParent_Done, |
| 89901 | // Label 6057: @229557 |
| 89902 | GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(229610), // Rule ID 2399 // |
| 89903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1), |
| 89904 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89906 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 89907 | // (fp_to_sint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 1:{ *:[i32] }) |
| 89908 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 89909 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 89910 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89911 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 89912 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 89913 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 89915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89916 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89918 | GIR_RootConstrainSelectedInstOperands, |
| 89919 | // GIR_Coverage, 2399, |
| 89920 | GIR_EraseRootFromParent_Done, |
| 89921 | // Label 6058: @229610 |
| 89922 | GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(229663), // Rule ID 2468 // |
| 89923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode0), |
| 89924 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89926 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 89927 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[bf16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_BF16:{ *:[f32] } ?:{ *:[bf16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 89928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 89929 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_BF16), |
| 89930 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89931 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 89932 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 89933 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 89935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89936 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89938 | GIR_RootConstrainSelectedInstOperands, |
| 89939 | // GIR_Coverage, 2468, |
| 89940 | GIR_EraseRootFromParent_Done, |
| 89941 | // Label 6059: @229663 |
| 89942 | GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(229716), // Rule ID 2469 // |
| 89943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode1), |
| 89944 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 89947 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[bf16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_BF16:{ *:[f32] } ?:{ *:[bf16] }:$rs1, 0:{ *:[i32] }), 1:{ *:[i32] }) |
| 89948 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 89949 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_BF16), |
| 89950 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 89951 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 89952 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 89953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 89954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 89955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89956 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 89957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89958 | GIR_RootConstrainSelectedInstOperands, |
| 89959 | // GIR_Coverage, 2469, |
| 89960 | GIR_EraseRootFromParent_Done, |
| 89961 | // Label 6060: @229716 |
| 89962 | GIM_Reject, |
| 89963 | // Label 6020: @229717 |
| 89964 | GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(229748), // Rule ID 1580 // |
| 89965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 89966 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 89967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89968 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 89969 | // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_L_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 89970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 89971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89974 | GIR_RootConstrainSelectedInstOperands, |
| 89975 | // GIR_Coverage, 1580, |
| 89976 | GIR_EraseRootFromParent_Done, |
| 89977 | // Label 6061: @229748 |
| 89978 | GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(229779), // Rule ID 1608 // |
| 89979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 89980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 89981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 89983 | // (fp_to_sint:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 89984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 89985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 89986 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 89987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 89988 | GIR_RootConstrainSelectedInstOperands, |
| 89989 | // GIR_Coverage, 1608, |
| 89990 | GIR_EraseRootFromParent_Done, |
| 89991 | // Label 6062: @229779 |
| 89992 | GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(229810), // Rule ID 1967 // |
| 89993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 89994 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 89995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 89996 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 89997 | // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 89998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D), |
| 89999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90000 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90002 | GIR_RootConstrainSelectedInstOperands, |
| 90003 | // GIR_Coverage, 1967, |
| 90004 | GIR_EraseRootFromParent_Done, |
| 90005 | // Label 6063: @229810 |
| 90006 | GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(229841), // Rule ID 1995 // |
| 90007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 90008 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 90009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90010 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90011 | // (fp_to_sint:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_L_D_INX:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 90012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D_INX), |
| 90013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90014 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90016 | GIR_RootConstrainSelectedInstOperands, |
| 90017 | // GIR_Coverage, 1995, |
| 90018 | GIR_EraseRootFromParent_Done, |
| 90019 | // Label 6064: @229841 |
| 90020 | GIM_Try, /*On fail goto*//*Label 6065*/ GIMT_Encode4(229872), // Rule ID 2295 // |
| 90021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 90022 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 90023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90024 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 90025 | // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 90026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H), |
| 90027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90028 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90030 | GIR_RootConstrainSelectedInstOperands, |
| 90031 | // GIR_Coverage, 2295, |
| 90032 | GIR_EraseRootFromParent_Done, |
| 90033 | // Label 6065: @229872 |
| 90034 | GIM_Try, /*On fail goto*//*Label 6066*/ GIMT_Encode4(229903), // Rule ID 2321 // |
| 90035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 90036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 90037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90038 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 90039 | // (fp_to_sint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 90040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H_INX), |
| 90041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90042 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90044 | GIR_RootConstrainSelectedInstOperands, |
| 90045 | // GIR_Coverage, 2321, |
| 90046 | GIR_EraseRootFromParent_Done, |
| 90047 | // Label 6066: @229903 |
| 90048 | GIM_Try, /*On fail goto*//*Label 6067*/ GIMT_Encode4(229956), // Rule ID 2421 // |
| 90049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 90050 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 90051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90052 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 90053 | // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_S:{ *:[i64] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 90054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 90055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 90056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90057 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 90058 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 90059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 90061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90064 | GIR_RootConstrainSelectedInstOperands, |
| 90065 | // GIR_Coverage, 2421, |
| 90066 | GIR_EraseRootFromParent_Done, |
| 90067 | // Label 6067: @229956 |
| 90068 | GIM_Try, /*On fail goto*//*Label 6068*/ GIMT_Encode4(230009), // Rule ID 2437 // |
| 90069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 90070 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 90071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90072 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 90073 | // (fp_to_sint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 90074 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 90075 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 90076 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90077 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 90078 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 90079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 90081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90082 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90084 | GIR_RootConstrainSelectedInstOperands, |
| 90085 | // GIR_Coverage, 2437, |
| 90086 | GIR_EraseRootFromParent_Done, |
| 90087 | // Label 6068: @230009 |
| 90088 | GIM_Try, /*On fail goto*//*Label 6069*/ GIMT_Encode4(230062), // Rule ID 2483 // |
| 90089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_IsRV64_HwMode0), |
| 90090 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 90091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 90092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 90093 | // (fp_to_sint:{ *:[i64] } FPR16:{ *:[bf16] }:$rs1) => (FCVT_L_S:{ *:[i64] } (FCVT_S_BF16:{ *:[f32] } ?:{ *:[bf16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 90094 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 90095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_BF16), |
| 90096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90097 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 90098 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 90099 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 90101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90102 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 90104 | GIR_RootConstrainSelectedInstOperands, |
| 90105 | // GIR_Coverage, 2483, |
| 90106 | GIR_EraseRootFromParent_Done, |
| 90107 | // Label 6069: @230062 |
| 90108 | GIM_Reject, |
| 90109 | // Label 6021: @230063 |
| 90110 | GIM_Try, /*On fail goto*//*Label 6070*/ GIMT_Encode4(230166), |
| 90111 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 90112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90114 | GIM_Try, /*On fail goto*//*Label 6071*/ GIMT_Encode4(230122), // Rule ID 46656 // |
| 90115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90116 | // (fp_to_sint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 90117 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 90118 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90119 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF8), |
| 90122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90123 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90124 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90128 | GIR_RootConstrainSelectedInstOperands, |
| 90129 | // GIR_Coverage, 46656, |
| 90130 | GIR_EraseRootFromParent_Done, |
| 90131 | // Label 6071: @230122 |
| 90132 | GIM_Try, /*On fail goto*//*Label 6072*/ GIMT_Encode4(230165), // Rule ID 46657 // |
| 90133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90134 | // (fp_to_sint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 90135 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 90136 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90137 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90138 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF8), |
| 90140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90141 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90142 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90146 | GIR_RootConstrainSelectedInstOperands, |
| 90147 | // GIR_Coverage, 46657, |
| 90148 | GIR_EraseRootFromParent_Done, |
| 90149 | // Label 6072: @230165 |
| 90150 | GIM_Reject, |
| 90151 | // Label 6070: @230166 |
| 90152 | GIM_Reject, |
| 90153 | // Label 6022: @230167 |
| 90154 | GIM_Try, /*On fail goto*//*Label 6073*/ GIMT_Encode4(230221), // Rule ID 46640 // |
| 90155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 90157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90159 | // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90160 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 90161 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90162 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_MF4), |
| 90165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90166 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90167 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90171 | GIR_RootConstrainSelectedInstOperands, |
| 90172 | // GIR_Coverage, 46640, |
| 90173 | GIR_EraseRootFromParent_Done, |
| 90174 | // Label 6073: @230221 |
| 90175 | GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(230275), // Rule ID 46641 // |
| 90176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90177 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 90178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90179 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90180 | // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90181 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 90182 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90183 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_MF4), |
| 90186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90187 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90188 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90192 | GIR_RootConstrainSelectedInstOperands, |
| 90193 | // GIR_Coverage, 46641, |
| 90194 | GIR_EraseRootFromParent_Done, |
| 90195 | // Label 6074: @230275 |
| 90196 | GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(230329), // Rule ID 59232 // |
| 90197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 90198 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 90199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90201 | // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 90203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4), |
| 90207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90208 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90209 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90213 | GIR_RootConstrainSelectedInstOperands, |
| 90214 | // GIR_Coverage, 59232, |
| 90215 | GIR_EraseRootFromParent_Done, |
| 90216 | // Label 6075: @230329 |
| 90217 | GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(230383), // Rule ID 59233 // |
| 90218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 90219 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 90220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90221 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90222 | // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90223 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 90224 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90225 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4), |
| 90228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90229 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90230 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90234 | GIR_RootConstrainSelectedInstOperands, |
| 90235 | // GIR_Coverage, 59233, |
| 90236 | GIR_EraseRootFromParent_Done, |
| 90237 | // Label 6076: @230383 |
| 90238 | GIM_Reject, |
| 90239 | // Label 6023: @230384 |
| 90240 | GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(230438), // Rule ID 46648 // |
| 90241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90242 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 90243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90244 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90245 | // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_MF4:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90246 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 90247 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90248 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_MF4), |
| 90251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90252 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90253 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90257 | GIR_RootConstrainSelectedInstOperands, |
| 90258 | // GIR_Coverage, 46648, |
| 90259 | GIR_EraseRootFromParent_Done, |
| 90260 | // Label 6077: @230438 |
| 90261 | GIM_Try, /*On fail goto*//*Label 6078*/ GIMT_Encode4(230492), // Rule ID 46649 // |
| 90262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90263 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 90264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90265 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90266 | // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_MF4:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90267 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 90268 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90269 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90270 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_MF4), |
| 90272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90273 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90274 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90278 | GIR_RootConstrainSelectedInstOperands, |
| 90279 | // GIR_Coverage, 46649, |
| 90280 | GIR_EraseRootFromParent_Done, |
| 90281 | // Label 6078: @230492 |
| 90282 | GIM_Try, /*On fail goto*//*Label 6079*/ GIMT_Encode4(230546), // Rule ID 58800 // |
| 90283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 90284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 90285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90287 | // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 90289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_MF2), |
| 90293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90299 | GIR_RootConstrainSelectedInstOperands, |
| 90300 | // GIR_Coverage, 58800, |
| 90301 | GIR_EraseRootFromParent_Done, |
| 90302 | // Label 6079: @230546 |
| 90303 | GIM_Try, /*On fail goto*//*Label 6080*/ GIMT_Encode4(230600), // Rule ID 58801 // |
| 90304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 90305 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 90306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90307 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90308 | // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 90310 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90311 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_MF2), |
| 90314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90315 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90320 | GIR_RootConstrainSelectedInstOperands, |
| 90321 | // GIR_Coverage, 58801, |
| 90322 | GIR_EraseRootFromParent_Done, |
| 90323 | // Label 6080: @230600 |
| 90324 | GIM_Try, /*On fail goto*//*Label 6081*/ GIMT_Encode4(230654), // Rule ID 59252 // |
| 90325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 90326 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 90327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90328 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90329 | // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90330 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 90331 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90332 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90333 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2), |
| 90335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90336 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90337 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90341 | GIR_RootConstrainSelectedInstOperands, |
| 90342 | // GIR_Coverage, 59252, |
| 90343 | GIR_EraseRootFromParent_Done, |
| 90344 | // Label 6081: @230654 |
| 90345 | GIM_Try, /*On fail goto*//*Label 6082*/ GIMT_Encode4(230708), // Rule ID 59253 // |
| 90346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 90347 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 90348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90349 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90350 | // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90351 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 90352 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90353 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90354 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2), |
| 90356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90357 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90358 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90362 | GIR_RootConstrainSelectedInstOperands, |
| 90363 | // GIR_Coverage, 59253, |
| 90364 | GIR_EraseRootFromParent_Done, |
| 90365 | // Label 6082: @230708 |
| 90366 | GIM_Reject, |
| 90367 | // Label 6024: @230709 |
| 90368 | GIM_Try, /*On fail goto*//*Label 6083*/ GIMT_Encode4(230763), // Rule ID 58812 // |
| 90369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 90370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 90371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90373 | // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 90374 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 90375 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90376 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M1), |
| 90379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90380 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90381 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 90384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90385 | GIR_RootConstrainSelectedInstOperands, |
| 90386 | // GIR_Coverage, 58812, |
| 90387 | GIR_EraseRootFromParent_Done, |
| 90388 | // Label 6083: @230763 |
| 90389 | GIM_Try, /*On fail goto*//*Label 6084*/ GIMT_Encode4(230817), // Rule ID 58813 // |
| 90390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 90391 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 90392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90394 | // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 90395 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 90396 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90397 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90398 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M1), |
| 90400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90401 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90402 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 90405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90406 | GIR_RootConstrainSelectedInstOperands, |
| 90407 | // GIR_Coverage, 58813, |
| 90408 | GIR_EraseRootFromParent_Done, |
| 90409 | // Label 6084: @230817 |
| 90410 | GIM_Try, /*On fail goto*//*Label 6085*/ GIMT_Encode4(230871), // Rule ID 59044 // |
| 90411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 90412 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 90413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90414 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90415 | // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90416 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 90417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2), |
| 90421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90422 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90423 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90427 | GIR_RootConstrainSelectedInstOperands, |
| 90428 | // GIR_Coverage, 59044, |
| 90429 | GIR_EraseRootFromParent_Done, |
| 90430 | // Label 6085: @230871 |
| 90431 | GIM_Try, /*On fail goto*//*Label 6086*/ GIMT_Encode4(230925), // Rule ID 59045 // |
| 90432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 90433 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 90434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90435 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90436 | // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90437 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 90438 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90439 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90440 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2), |
| 90442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90443 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90444 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90448 | GIR_RootConstrainSelectedInstOperands, |
| 90449 | // GIR_Coverage, 59045, |
| 90450 | GIR_EraseRootFromParent_Done, |
| 90451 | // Label 6086: @230925 |
| 90452 | GIM_Reject, |
| 90453 | // Label 6025: @230926 |
| 90454 | GIM_Try, /*On fail goto*//*Label 6087*/ GIMT_Encode4(231029), |
| 90455 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 90456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90458 | GIM_Try, /*On fail goto*//*Label 6088*/ GIMT_Encode4(230985), // Rule ID 59212 // |
| 90459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90460 | // (fp_to_sint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 90461 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 90462 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90463 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4), |
| 90466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90467 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90468 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90472 | GIR_RootConstrainSelectedInstOperands, |
| 90473 | // GIR_Coverage, 59212, |
| 90474 | GIR_EraseRootFromParent_Done, |
| 90475 | // Label 6088: @230985 |
| 90476 | GIM_Try, /*On fail goto*//*Label 6089*/ GIMT_Encode4(231028), // Rule ID 59213 // |
| 90477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90478 | // (fp_to_sint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 90479 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 90480 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90481 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4), |
| 90484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90485 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90486 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90490 | GIR_RootConstrainSelectedInstOperands, |
| 90491 | // GIR_Coverage, 59213, |
| 90492 | GIR_EraseRootFromParent_Done, |
| 90493 | // Label 6089: @231028 |
| 90494 | GIM_Reject, |
| 90495 | // Label 6087: @231029 |
| 90496 | GIM_Reject, |
| 90497 | // Label 6026: @231030 |
| 90498 | GIM_Try, /*On fail goto*//*Label 6090*/ GIMT_Encode4(231084), // Rule ID 58796 // |
| 90499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90500 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 90501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90503 | // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90504 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 90505 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90506 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_MF2), |
| 90509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90511 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90515 | GIR_RootConstrainSelectedInstOperands, |
| 90516 | // GIR_Coverage, 58796, |
| 90517 | GIR_EraseRootFromParent_Done, |
| 90518 | // Label 6090: @231084 |
| 90519 | GIM_Try, /*On fail goto*//*Label 6091*/ GIMT_Encode4(231138), // Rule ID 58797 // |
| 90520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90521 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 90522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90523 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90524 | // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90525 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 90526 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90527 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_MF2), |
| 90530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90531 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90532 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90536 | GIR_RootConstrainSelectedInstOperands, |
| 90537 | // GIR_Coverage, 58797, |
| 90538 | GIR_EraseRootFromParent_Done, |
| 90539 | // Label 6091: @231138 |
| 90540 | GIM_Try, /*On fail goto*//*Label 6092*/ GIMT_Encode4(231192), // Rule ID 59236 // |
| 90541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 90542 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 90543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90544 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90545 | // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90546 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 90547 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90548 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2), |
| 90551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90552 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90553 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90557 | GIR_RootConstrainSelectedInstOperands, |
| 90558 | // GIR_Coverage, 59236, |
| 90559 | GIR_EraseRootFromParent_Done, |
| 90560 | // Label 6092: @231192 |
| 90561 | GIM_Try, /*On fail goto*//*Label 6093*/ GIMT_Encode4(231246), // Rule ID 59237 // |
| 90562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 90563 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 90564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90566 | // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 90568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2), |
| 90572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90573 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90574 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90578 | GIR_RootConstrainSelectedInstOperands, |
| 90579 | // GIR_Coverage, 59237, |
| 90580 | GIR_EraseRootFromParent_Done, |
| 90581 | // Label 6093: @231246 |
| 90582 | GIM_Reject, |
| 90583 | // Label 6027: @231247 |
| 90584 | GIM_Try, /*On fail goto*//*Label 6094*/ GIMT_Encode4(231301), // Rule ID 58808 // |
| 90585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 90586 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 90587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90589 | // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 90591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M1), |
| 90595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90597 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90601 | GIR_RootConstrainSelectedInstOperands, |
| 90602 | // GIR_Coverage, 58808, |
| 90603 | GIR_EraseRootFromParent_Done, |
| 90604 | // Label 6094: @231301 |
| 90605 | GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(231355), // Rule ID 58809 // |
| 90606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 90607 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 90608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90609 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90610 | // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90611 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 90612 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90613 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M1), |
| 90616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90618 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90622 | GIR_RootConstrainSelectedInstOperands, |
| 90623 | // GIR_Coverage, 58809, |
| 90624 | GIR_EraseRootFromParent_Done, |
| 90625 | // Label 6095: @231355 |
| 90626 | GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(231409), // Rule ID 59028 // |
| 90627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90628 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 90629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90630 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90631 | // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 90633 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90634 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2), |
| 90637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90638 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90639 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90643 | GIR_RootConstrainSelectedInstOperands, |
| 90644 | // GIR_Coverage, 59028, |
| 90645 | GIR_EraseRootFromParent_Done, |
| 90646 | // Label 6096: @231409 |
| 90647 | GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(231463), // Rule ID 59029 // |
| 90648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90649 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 90650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90652 | // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 90654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2), |
| 90658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90660 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90664 | GIR_RootConstrainSelectedInstOperands, |
| 90665 | // GIR_Coverage, 59029, |
| 90666 | GIR_EraseRootFromParent_Done, |
| 90667 | // Label 6097: @231463 |
| 90668 | GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(231517), // Rule ID 59256 // |
| 90669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 90670 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 90671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90673 | // (fp_to_sint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 90675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90677 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M1), |
| 90679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90680 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90681 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90685 | GIR_RootConstrainSelectedInstOperands, |
| 90686 | // GIR_Coverage, 59256, |
| 90687 | GIR_EraseRootFromParent_Done, |
| 90688 | // Label 6098: @231517 |
| 90689 | GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(231571), // Rule ID 59257 // |
| 90690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 90691 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 90692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90693 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90694 | // (fp_to_sint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90695 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 90696 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90697 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M1), |
| 90700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90701 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90702 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90706 | GIR_RootConstrainSelectedInstOperands, |
| 90707 | // GIR_Coverage, 59257, |
| 90708 | GIR_EraseRootFromParent_Done, |
| 90709 | // Label 6099: @231571 |
| 90710 | GIM_Reject, |
| 90711 | // Label 6028: @231572 |
| 90712 | GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(231626), // Rule ID 58840 // |
| 90713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 90714 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 90715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90716 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90717 | // (fp_to_sint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 90718 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 90719 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90720 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M2), |
| 90723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90725 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 90728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90729 | GIR_RootConstrainSelectedInstOperands, |
| 90730 | // GIR_Coverage, 58840, |
| 90731 | GIR_EraseRootFromParent_Done, |
| 90732 | // Label 6100: @231626 |
| 90733 | GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(231680), // Rule ID 58841 // |
| 90734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 90735 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 90736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90737 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90738 | // (fp_to_sint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 90739 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 90740 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90741 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M2), |
| 90744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90745 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90746 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 90749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90750 | GIR_RootConstrainSelectedInstOperands, |
| 90751 | // GIR_Coverage, 58841, |
| 90752 | GIR_EraseRootFromParent_Done, |
| 90753 | // Label 6101: @231680 |
| 90754 | GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(231734), // Rule ID 59048 // |
| 90755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 90756 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 90757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90758 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90759 | // (fp_to_sint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 90761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90762 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M1), |
| 90765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90767 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90771 | GIR_RootConstrainSelectedInstOperands, |
| 90772 | // GIR_Coverage, 59048, |
| 90773 | GIR_EraseRootFromParent_Done, |
| 90774 | // Label 6102: @231734 |
| 90775 | GIM_Try, /*On fail goto*//*Label 6103*/ GIMT_Encode4(231788), // Rule ID 59049 // |
| 90776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 90777 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 90778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90779 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90780 | // (fp_to_sint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90781 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 90782 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90783 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M1), |
| 90786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90787 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90788 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90792 | GIR_RootConstrainSelectedInstOperands, |
| 90793 | // GIR_Coverage, 59049, |
| 90794 | GIR_EraseRootFromParent_Done, |
| 90795 | // Label 6103: @231788 |
| 90796 | GIM_Reject, |
| 90797 | // Label 6029: @231789 |
| 90798 | GIM_Try, /*On fail goto*//*Label 6104*/ GIMT_Encode4(231892), |
| 90799 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 90800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90801 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90802 | GIM_Try, /*On fail goto*//*Label 6105*/ GIMT_Encode4(231848), // Rule ID 59216 // |
| 90803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90804 | // (fp_to_sint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 90805 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 90806 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90807 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2), |
| 90810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90811 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90812 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90816 | GIR_RootConstrainSelectedInstOperands, |
| 90817 | // GIR_Coverage, 59216, |
| 90818 | GIR_EraseRootFromParent_Done, |
| 90819 | // Label 6105: @231848 |
| 90820 | GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(231891), // Rule ID 59217 // |
| 90821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90822 | // (fp_to_sint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 90823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 90824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90826 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2), |
| 90828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90829 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90830 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90834 | GIR_RootConstrainSelectedInstOperands, |
| 90835 | // GIR_Coverage, 59217, |
| 90836 | GIR_EraseRootFromParent_Done, |
| 90837 | // Label 6106: @231891 |
| 90838 | GIM_Reject, |
| 90839 | // Label 6104: @231892 |
| 90840 | GIM_Reject, |
| 90841 | // Label 6030: @231893 |
| 90842 | GIM_Try, /*On fail goto*//*Label 6107*/ GIMT_Encode4(231947), // Rule ID 58804 // |
| 90843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90844 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 90845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90847 | // (fp_to_sint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 90849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M1), |
| 90853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90854 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90855 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90859 | GIR_RootConstrainSelectedInstOperands, |
| 90860 | // GIR_Coverage, 58804, |
| 90861 | GIR_EraseRootFromParent_Done, |
| 90862 | // Label 6107: @231947 |
| 90863 | GIM_Try, /*On fail goto*//*Label 6108*/ GIMT_Encode4(232001), // Rule ID 58805 // |
| 90864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90865 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 90866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90867 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90868 | // (fp_to_sint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90869 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 90870 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90871 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M1), |
| 90874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90875 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90876 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90880 | GIR_RootConstrainSelectedInstOperands, |
| 90881 | // GIR_Coverage, 58805, |
| 90882 | GIR_EraseRootFromParent_Done, |
| 90883 | // Label 6108: @232001 |
| 90884 | GIM_Try, /*On fail goto*//*Label 6109*/ GIMT_Encode4(232055), // Rule ID 59240 // |
| 90885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 90886 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 90887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90889 | // (fp_to_sint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90890 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 90891 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90892 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M1), |
| 90895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90896 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90897 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90901 | GIR_RootConstrainSelectedInstOperands, |
| 90902 | // GIR_Coverage, 59240, |
| 90903 | GIR_EraseRootFromParent_Done, |
| 90904 | // Label 6109: @232055 |
| 90905 | GIM_Try, /*On fail goto*//*Label 6110*/ GIMT_Encode4(232109), // Rule ID 59241 // |
| 90906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 90907 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 90908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90910 | // (fp_to_sint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90911 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 90912 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90913 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90914 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M1), |
| 90916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90917 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90918 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90922 | GIR_RootConstrainSelectedInstOperands, |
| 90923 | // GIR_Coverage, 59241, |
| 90924 | GIR_EraseRootFromParent_Done, |
| 90925 | // Label 6110: @232109 |
| 90926 | GIM_Reject, |
| 90927 | // Label 6031: @232110 |
| 90928 | GIM_Try, /*On fail goto*//*Label 6111*/ GIMT_Encode4(232164), // Rule ID 58828 // |
| 90929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 90930 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 90931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90932 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90933 | // (fp_to_sint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 90934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 90935 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90936 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90937 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M2), |
| 90939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90940 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90941 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90945 | GIR_RootConstrainSelectedInstOperands, |
| 90946 | // GIR_Coverage, 58828, |
| 90947 | GIR_EraseRootFromParent_Done, |
| 90948 | // Label 6111: @232164 |
| 90949 | GIM_Try, /*On fail goto*//*Label 6112*/ GIMT_Encode4(232218), // Rule ID 58829 // |
| 90950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 90951 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 90952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90953 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90954 | // (fp_to_sint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 90955 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 90956 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90957 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M2), |
| 90960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90961 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90962 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 90965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90966 | GIR_RootConstrainSelectedInstOperands, |
| 90967 | // GIR_Coverage, 58829, |
| 90968 | GIR_EraseRootFromParent_Done, |
| 90969 | // Label 6112: @232218 |
| 90970 | GIM_Try, /*On fail goto*//*Label 6113*/ GIMT_Encode4(232272), // Rule ID 59032 // |
| 90971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 90972 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 90973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90974 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90975 | // (fp_to_sint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 90976 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 90977 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90978 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 90979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 90980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M1), |
| 90981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 90982 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 90983 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 90984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 90985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 90986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 90987 | GIR_RootConstrainSelectedInstOperands, |
| 90988 | // GIR_Coverage, 59032, |
| 90989 | GIR_EraseRootFromParent_Done, |
| 90990 | // Label 6113: @232272 |
| 90991 | GIM_Try, /*On fail goto*//*Label 6114*/ GIMT_Encode4(232326), // Rule ID 59033 // |
| 90992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 90993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 90994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 90995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 90996 | // (fp_to_sint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 90997 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 90998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 90999 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91000 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M1), |
| 91002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91003 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91004 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91008 | GIR_RootConstrainSelectedInstOperands, |
| 91009 | // GIR_Coverage, 59033, |
| 91010 | GIR_EraseRootFromParent_Done, |
| 91011 | // Label 6114: @232326 |
| 91012 | GIM_Try, /*On fail goto*//*Label 6115*/ GIMT_Encode4(232380), // Rule ID 59260 // |
| 91013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 91014 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 91015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91017 | // (fp_to_sint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 91018 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 91019 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91020 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91021 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M2), |
| 91023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91024 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91025 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91029 | GIR_RootConstrainSelectedInstOperands, |
| 91030 | // GIR_Coverage, 59260, |
| 91031 | GIR_EraseRootFromParent_Done, |
| 91032 | // Label 6115: @232380 |
| 91033 | GIM_Try, /*On fail goto*//*Label 6116*/ GIMT_Encode4(232434), // Rule ID 59261 // |
| 91034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 91035 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 91036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91037 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91038 | // (fp_to_sint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 91039 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 91040 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91041 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91042 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M2), |
| 91044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91045 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91046 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91050 | GIR_RootConstrainSelectedInstOperands, |
| 91051 | // GIR_Coverage, 59261, |
| 91052 | GIR_EraseRootFromParent_Done, |
| 91053 | // Label 6116: @232434 |
| 91054 | GIM_Reject, |
| 91055 | // Label 6032: @232435 |
| 91056 | GIM_Try, /*On fail goto*//*Label 6117*/ GIMT_Encode4(232489), // Rule ID 58844 // |
| 91057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 91058 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 91059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91060 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91061 | // (fp_to_sint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 91062 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 91063 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91064 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M4), |
| 91067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91068 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91069 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 91072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91073 | GIR_RootConstrainSelectedInstOperands, |
| 91074 | // GIR_Coverage, 58844, |
| 91075 | GIR_EraseRootFromParent_Done, |
| 91076 | // Label 6117: @232489 |
| 91077 | GIM_Try, /*On fail goto*//*Label 6118*/ GIMT_Encode4(232543), // Rule ID 58845 // |
| 91078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 91079 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 91080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91081 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91082 | // (fp_to_sint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 91083 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 91084 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91085 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M4), |
| 91088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91089 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91090 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 91093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91094 | GIR_RootConstrainSelectedInstOperands, |
| 91095 | // GIR_Coverage, 58845, |
| 91096 | GIR_EraseRootFromParent_Done, |
| 91097 | // Label 6118: @232543 |
| 91098 | GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(232597), // Rule ID 59052 // |
| 91099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 91100 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 91101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91102 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91103 | // (fp_to_sint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 91104 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 91105 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91106 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M2), |
| 91109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91110 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91111 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91115 | GIR_RootConstrainSelectedInstOperands, |
| 91116 | // GIR_Coverage, 59052, |
| 91117 | GIR_EraseRootFromParent_Done, |
| 91118 | // Label 6119: @232597 |
| 91119 | GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(232651), // Rule ID 59053 // |
| 91120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 91121 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 91122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91124 | // (fp_to_sint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 91125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 91126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M2), |
| 91130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91136 | GIR_RootConstrainSelectedInstOperands, |
| 91137 | // GIR_Coverage, 59053, |
| 91138 | GIR_EraseRootFromParent_Done, |
| 91139 | // Label 6120: @232651 |
| 91140 | GIM_Reject, |
| 91141 | // Label 6033: @232652 |
| 91142 | GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(232755), |
| 91143 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 91144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 91145 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91146 | GIM_Try, /*On fail goto*//*Label 6122*/ GIMT_Encode4(232711), // Rule ID 59220 // |
| 91147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91148 | // (fp_to_sint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 91149 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 91150 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91151 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M1), |
| 91154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91155 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91156 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91160 | GIR_RootConstrainSelectedInstOperands, |
| 91161 | // GIR_Coverage, 59220, |
| 91162 | GIR_EraseRootFromParent_Done, |
| 91163 | // Label 6122: @232711 |
| 91164 | GIM_Try, /*On fail goto*//*Label 6123*/ GIMT_Encode4(232754), // Rule ID 59221 // |
| 91165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91166 | // (fp_to_sint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 91167 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 91168 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91169 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M1), |
| 91172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91174 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91178 | GIR_RootConstrainSelectedInstOperands, |
| 91179 | // GIR_Coverage, 59221, |
| 91180 | GIR_EraseRootFromParent_Done, |
| 91181 | // Label 6123: @232754 |
| 91182 | GIM_Reject, |
| 91183 | // Label 6121: @232755 |
| 91184 | GIM_Reject, |
| 91185 | // Label 6034: @232756 |
| 91186 | GIM_Try, /*On fail goto*//*Label 6124*/ GIMT_Encode4(232810), // Rule ID 58816 // |
| 91187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91188 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 91189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91190 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91191 | // (fp_to_sint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91192 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 91193 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91194 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M2), |
| 91197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91199 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91203 | GIR_RootConstrainSelectedInstOperands, |
| 91204 | // GIR_Coverage, 58816, |
| 91205 | GIR_EraseRootFromParent_Done, |
| 91206 | // Label 6124: @232810 |
| 91207 | GIM_Try, /*On fail goto*//*Label 6125*/ GIMT_Encode4(232864), // Rule ID 58817 // |
| 91208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91209 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 91210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91211 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91212 | // (fp_to_sint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 91214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M2), |
| 91218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91219 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91220 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91224 | GIR_RootConstrainSelectedInstOperands, |
| 91225 | // GIR_Coverage, 58817, |
| 91226 | GIR_EraseRootFromParent_Done, |
| 91227 | // Label 6125: @232864 |
| 91228 | GIM_Try, /*On fail goto*//*Label 6126*/ GIMT_Encode4(232918), // Rule ID 59244 // |
| 91229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 91230 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 91231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91232 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91233 | // (fp_to_sint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91234 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 91235 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91236 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91237 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M2), |
| 91239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91240 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91241 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91245 | GIR_RootConstrainSelectedInstOperands, |
| 91246 | // GIR_Coverage, 59244, |
| 91247 | GIR_EraseRootFromParent_Done, |
| 91248 | // Label 6126: @232918 |
| 91249 | GIM_Try, /*On fail goto*//*Label 6127*/ GIMT_Encode4(232972), // Rule ID 59245 // |
| 91250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 91251 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 91252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91253 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91254 | // (fp_to_sint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91255 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 91256 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91257 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91258 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M2), |
| 91260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91261 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91262 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91266 | GIR_RootConstrainSelectedInstOperands, |
| 91267 | // GIR_Coverage, 59245, |
| 91268 | GIR_EraseRootFromParent_Done, |
| 91269 | // Label 6127: @232972 |
| 91270 | GIM_Reject, |
| 91271 | // Label 6035: @232973 |
| 91272 | GIM_Try, /*On fail goto*//*Label 6128*/ GIMT_Encode4(233027), // Rule ID 58832 // |
| 91273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 91274 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 91275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91277 | // (fp_to_sint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 91278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 91279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M4), |
| 91283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91289 | GIR_RootConstrainSelectedInstOperands, |
| 91290 | // GIR_Coverage, 58832, |
| 91291 | GIR_EraseRootFromParent_Done, |
| 91292 | // Label 6128: @233027 |
| 91293 | GIM_Try, /*On fail goto*//*Label 6129*/ GIMT_Encode4(233081), // Rule ID 58833 // |
| 91294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 91295 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 91296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91297 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91298 | // (fp_to_sint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 91299 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 91300 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91301 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M4), |
| 91304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91305 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91306 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91310 | GIR_RootConstrainSelectedInstOperands, |
| 91311 | // GIR_Coverage, 58833, |
| 91312 | GIR_EraseRootFromParent_Done, |
| 91313 | // Label 6129: @233081 |
| 91314 | GIM_Try, /*On fail goto*//*Label 6130*/ GIMT_Encode4(233135), // Rule ID 59036 // |
| 91315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91316 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 91317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91318 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91319 | // (fp_to_sint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 91321 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91322 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M2), |
| 91325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91326 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91327 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91331 | GIR_RootConstrainSelectedInstOperands, |
| 91332 | // GIR_Coverage, 59036, |
| 91333 | GIR_EraseRootFromParent_Done, |
| 91334 | // Label 6130: @233135 |
| 91335 | GIM_Try, /*On fail goto*//*Label 6131*/ GIMT_Encode4(233189), // Rule ID 59037 // |
| 91336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91337 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 91338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91339 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91340 | // (fp_to_sint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91341 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 91342 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91343 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M2), |
| 91346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91347 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91348 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91352 | GIR_RootConstrainSelectedInstOperands, |
| 91353 | // GIR_Coverage, 59037, |
| 91354 | GIR_EraseRootFromParent_Done, |
| 91355 | // Label 6131: @233189 |
| 91356 | GIM_Try, /*On fail goto*//*Label 6132*/ GIMT_Encode4(233243), // Rule ID 59264 // |
| 91357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 91358 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 91359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91361 | // (fp_to_sint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 91362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 91363 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91364 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M4), |
| 91367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91368 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91369 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91373 | GIR_RootConstrainSelectedInstOperands, |
| 91374 | // GIR_Coverage, 59264, |
| 91375 | GIR_EraseRootFromParent_Done, |
| 91376 | // Label 6132: @233243 |
| 91377 | GIM_Try, /*On fail goto*//*Label 6133*/ GIMT_Encode4(233297), // Rule ID 59265 // |
| 91378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 91379 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 91380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91382 | // (fp_to_sint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 91383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 91384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M4), |
| 91388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91390 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91394 | GIR_RootConstrainSelectedInstOperands, |
| 91395 | // GIR_Coverage, 59265, |
| 91396 | GIR_EraseRootFromParent_Done, |
| 91397 | // Label 6133: @233297 |
| 91398 | GIM_Reject, |
| 91399 | // Label 6036: @233298 |
| 91400 | GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(233352), // Rule ID 58848 // |
| 91401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 91402 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 91403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91404 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91405 | // (fp_to_sint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 91406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 91407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91408 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M8), |
| 91411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91413 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 91416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91417 | GIR_RootConstrainSelectedInstOperands, |
| 91418 | // GIR_Coverage, 58848, |
| 91419 | GIR_EraseRootFromParent_Done, |
| 91420 | // Label 6134: @233352 |
| 91421 | GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(233406), // Rule ID 58849 // |
| 91422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 91423 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 91424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91425 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91426 | // (fp_to_sint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 91427 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 91428 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91429 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91430 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M8), |
| 91432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91433 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91434 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 91437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91438 | GIR_RootConstrainSelectedInstOperands, |
| 91439 | // GIR_Coverage, 58849, |
| 91440 | GIR_EraseRootFromParent_Done, |
| 91441 | // Label 6135: @233406 |
| 91442 | GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(233460), // Rule ID 59056 // |
| 91443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 91444 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 91445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91446 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91447 | // (fp_to_sint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 91448 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 91449 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91450 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M4), |
| 91453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91454 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91455 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91459 | GIR_RootConstrainSelectedInstOperands, |
| 91460 | // GIR_Coverage, 59056, |
| 91461 | GIR_EraseRootFromParent_Done, |
| 91462 | // Label 6136: @233460 |
| 91463 | GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(233514), // Rule ID 59057 // |
| 91464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 91465 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 91466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91467 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91468 | // (fp_to_sint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 91469 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 91470 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91471 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91472 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M4), |
| 91474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91475 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91476 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91480 | GIR_RootConstrainSelectedInstOperands, |
| 91481 | // GIR_Coverage, 59057, |
| 91482 | GIR_EraseRootFromParent_Done, |
| 91483 | // Label 6137: @233514 |
| 91484 | GIM_Reject, |
| 91485 | // Label 6037: @233515 |
| 91486 | GIM_Try, /*On fail goto*//*Label 6138*/ GIMT_Encode4(233618), |
| 91487 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 91488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 91489 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91490 | GIM_Try, /*On fail goto*//*Label 6139*/ GIMT_Encode4(233574), // Rule ID 59224 // |
| 91491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91492 | // (fp_to_sint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 91493 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 91494 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91495 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M2), |
| 91498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91504 | GIR_RootConstrainSelectedInstOperands, |
| 91505 | // GIR_Coverage, 59224, |
| 91506 | GIR_EraseRootFromParent_Done, |
| 91507 | // Label 6139: @233574 |
| 91508 | GIM_Try, /*On fail goto*//*Label 6140*/ GIMT_Encode4(233617), // Rule ID 59225 // |
| 91509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91510 | // (fp_to_sint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 91511 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 91512 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91513 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M2), |
| 91516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91517 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91518 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91522 | GIR_RootConstrainSelectedInstOperands, |
| 91523 | // GIR_Coverage, 59225, |
| 91524 | GIR_EraseRootFromParent_Done, |
| 91525 | // Label 6140: @233617 |
| 91526 | GIM_Reject, |
| 91527 | // Label 6138: @233618 |
| 91528 | GIM_Reject, |
| 91529 | // Label 6038: @233619 |
| 91530 | GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(233673), // Rule ID 58820 // |
| 91531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91532 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 91533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91534 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91535 | // (fp_to_sint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91536 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 91537 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91538 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91539 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M4), |
| 91541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91542 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91543 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91547 | GIR_RootConstrainSelectedInstOperands, |
| 91548 | // GIR_Coverage, 58820, |
| 91549 | GIR_EraseRootFromParent_Done, |
| 91550 | // Label 6141: @233673 |
| 91551 | GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(233727), // Rule ID 58821 // |
| 91552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91553 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 91554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91555 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91556 | // (fp_to_sint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 91558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M4), |
| 91562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91564 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91568 | GIR_RootConstrainSelectedInstOperands, |
| 91569 | // GIR_Coverage, 58821, |
| 91570 | GIR_EraseRootFromParent_Done, |
| 91571 | // Label 6142: @233727 |
| 91572 | GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(233781), // Rule ID 59248 // |
| 91573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 91574 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 91575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91577 | // (fp_to_sint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91578 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 91579 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91580 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M4), |
| 91583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91585 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91589 | GIR_RootConstrainSelectedInstOperands, |
| 91590 | // GIR_Coverage, 59248, |
| 91591 | GIR_EraseRootFromParent_Done, |
| 91592 | // Label 6143: @233781 |
| 91593 | GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(233835), // Rule ID 59249 // |
| 91594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 91595 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 91596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91597 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91598 | // (fp_to_sint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91599 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 91600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91602 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M4), |
| 91604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91605 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91606 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91610 | GIR_RootConstrainSelectedInstOperands, |
| 91611 | // GIR_Coverage, 59249, |
| 91612 | GIR_EraseRootFromParent_Done, |
| 91613 | // Label 6144: @233835 |
| 91614 | GIM_Reject, |
| 91615 | // Label 6039: @233836 |
| 91616 | GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(233890), // Rule ID 58836 // |
| 91617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 91618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 91619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91620 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91621 | // (fp_to_sint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 91622 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 91623 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91624 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M8), |
| 91627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91629 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91633 | GIR_RootConstrainSelectedInstOperands, |
| 91634 | // GIR_Coverage, 58836, |
| 91635 | GIR_EraseRootFromParent_Done, |
| 91636 | // Label 6145: @233890 |
| 91637 | GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(233944), // Rule ID 58837 // |
| 91638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 91639 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 91640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91641 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91642 | // (fp_to_sint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 91643 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 91644 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91645 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M8), |
| 91648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91649 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91650 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 91653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91654 | GIR_RootConstrainSelectedInstOperands, |
| 91655 | // GIR_Coverage, 58837, |
| 91656 | GIR_EraseRootFromParent_Done, |
| 91657 | // Label 6146: @233944 |
| 91658 | GIM_Try, /*On fail goto*//*Label 6147*/ GIMT_Encode4(233998), // Rule ID 59040 // |
| 91659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91660 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 91661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91662 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91663 | // (fp_to_sint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91664 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 91665 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91666 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91667 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M4), |
| 91669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91671 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91675 | GIR_RootConstrainSelectedInstOperands, |
| 91676 | // GIR_Coverage, 59040, |
| 91677 | GIR_EraseRootFromParent_Done, |
| 91678 | // Label 6147: @233998 |
| 91679 | GIM_Try, /*On fail goto*//*Label 6148*/ GIMT_Encode4(234052), // Rule ID 59041 // |
| 91680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91681 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 91682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91684 | // (fp_to_sint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 91686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_X_F_V_M4), |
| 91690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91691 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91692 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91696 | GIR_RootConstrainSelectedInstOperands, |
| 91697 | // GIR_Coverage, 59041, |
| 91698 | GIR_EraseRootFromParent_Done, |
| 91699 | // Label 6148: @234052 |
| 91700 | GIM_Reject, |
| 91701 | // Label 6040: @234053 |
| 91702 | GIM_Try, /*On fail goto*//*Label 6149*/ GIMT_Encode4(234156), |
| 91703 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 91704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 91705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91706 | GIM_Try, /*On fail goto*//*Label 6150*/ GIMT_Encode4(234112), // Rule ID 59228 // |
| 91707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91708 | // (fp_to_sint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 91709 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 91710 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91711 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M4), |
| 91714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91715 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91716 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91720 | GIR_RootConstrainSelectedInstOperands, |
| 91721 | // GIR_Coverage, 59228, |
| 91722 | GIR_EraseRootFromParent_Done, |
| 91723 | // Label 6150: @234112 |
| 91724 | GIM_Try, /*On fail goto*//*Label 6151*/ GIMT_Encode4(234155), // Rule ID 59229 // |
| 91725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91726 | // (fp_to_sint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 91727 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 91728 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91729 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_X_F_W_M4), |
| 91732 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91733 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91734 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91738 | GIR_RootConstrainSelectedInstOperands, |
| 91739 | // GIR_Coverage, 59229, |
| 91740 | GIR_EraseRootFromParent_Done, |
| 91741 | // Label 6151: @234155 |
| 91742 | GIM_Reject, |
| 91743 | // Label 6149: @234156 |
| 91744 | GIM_Reject, |
| 91745 | // Label 6041: @234157 |
| 91746 | GIM_Try, /*On fail goto*//*Label 6152*/ GIMT_Encode4(234260), |
| 91747 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 91748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 91750 | GIM_Try, /*On fail goto*//*Label 6153*/ GIMT_Encode4(234216), // Rule ID 58824 // |
| 91751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 91752 | // (fp_to_sint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 91753 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 91754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91755 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M8), |
| 91758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91759 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91760 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91764 | GIR_RootConstrainSelectedInstOperands, |
| 91765 | // GIR_Coverage, 58824, |
| 91766 | GIR_EraseRootFromParent_Done, |
| 91767 | // Label 6153: @234216 |
| 91768 | GIM_Try, /*On fail goto*//*Label 6154*/ GIMT_Encode4(234259), // Rule ID 58825 // |
| 91769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 91770 | // (fp_to_sint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 91771 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 91772 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 91773 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91774 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_X_F_V_M8), |
| 91776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91777 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 91778 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 91780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 91781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 91782 | GIR_RootConstrainSelectedInstOperands, |
| 91783 | // GIR_Coverage, 58825, |
| 91784 | GIR_EraseRootFromParent_Done, |
| 91785 | // Label 6154: @234259 |
| 91786 | GIM_Reject, |
| 91787 | // Label 6152: @234260 |
| 91788 | GIM_Reject, |
| 91789 | // Label 6042: @234261 |
| 91790 | GIM_Reject, |
| 91791 | // Label 62: @234262 |
| 91792 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(32), /*)*//*default:*//*Label 6178*/ GIMT_Encode4(239624), |
| 91793 | /*GILLT_s32*//*Label 6155*/ GIMT_Encode4(234389), |
| 91794 | /*GILLT_s64*//*Label 6156*/ GIMT_Encode4(235080), GIMT_Encode4(0), |
| 91795 | /*GILLT_nxv1s8*//*Label 6157*/ GIMT_Encode4(235426), |
| 91796 | /*GILLT_nxv1s16*//*Label 6158*/ GIMT_Encode4(235530), |
| 91797 | /*GILLT_nxv1s32*//*Label 6159*/ GIMT_Encode4(235747), |
| 91798 | /*GILLT_nxv1s64*//*Label 6160*/ GIMT_Encode4(236072), GIMT_Encode4(0), |
| 91799 | /*GILLT_nxv2s8*//*Label 6161*/ GIMT_Encode4(236289), |
| 91800 | /*GILLT_nxv2s16*//*Label 6162*/ GIMT_Encode4(236393), |
| 91801 | /*GILLT_nxv2s32*//*Label 6163*/ GIMT_Encode4(236610), |
| 91802 | /*GILLT_nxv2s64*//*Label 6164*/ GIMT_Encode4(236935), GIMT_Encode4(0), |
| 91803 | /*GILLT_nxv4s8*//*Label 6165*/ GIMT_Encode4(237152), |
| 91804 | /*GILLT_nxv4s16*//*Label 6166*/ GIMT_Encode4(237256), |
| 91805 | /*GILLT_nxv4s32*//*Label 6167*/ GIMT_Encode4(237473), |
| 91806 | /*GILLT_nxv4s64*//*Label 6168*/ GIMT_Encode4(237798), GIMT_Encode4(0), |
| 91807 | /*GILLT_nxv8s8*//*Label 6169*/ GIMT_Encode4(238015), |
| 91808 | /*GILLT_nxv8s16*//*Label 6170*/ GIMT_Encode4(238119), |
| 91809 | /*GILLT_nxv8s32*//*Label 6171*/ GIMT_Encode4(238336), |
| 91810 | /*GILLT_nxv8s64*//*Label 6172*/ GIMT_Encode4(238661), GIMT_Encode4(0), |
| 91811 | /*GILLT_nxv16s8*//*Label 6173*/ GIMT_Encode4(238878), |
| 91812 | /*GILLT_nxv16s16*//*Label 6174*/ GIMT_Encode4(238982), |
| 91813 | /*GILLT_nxv16s32*//*Label 6175*/ GIMT_Encode4(239199), GIMT_Encode4(0), |
| 91814 | /*GILLT_nxv32s8*//*Label 6176*/ GIMT_Encode4(239416), |
| 91815 | /*GILLT_nxv32s16*//*Label 6177*/ GIMT_Encode4(239520), |
| 91816 | // Label 6155: @234389 |
| 91817 | GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(234420), // Rule ID 1527 // |
| 91818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 91819 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 91820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91821 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 91822 | // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_WU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 91823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S), |
| 91824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91825 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91827 | GIR_RootConstrainSelectedInstOperands, |
| 91828 | // GIR_Coverage, 1527, |
| 91829 | GIR_EraseRootFromParent_Done, |
| 91830 | // Label 6179: @234420 |
| 91831 | GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(234451), // Rule ID 1528 // |
| 91832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 91833 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 91834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91835 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 91836 | // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_WU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] }) |
| 91837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S), |
| 91838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91839 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91841 | GIR_RootConstrainSelectedInstOperands, |
| 91842 | // GIR_Coverage, 1528, |
| 91843 | GIR_EraseRootFromParent_Done, |
| 91844 | // Label 6180: @234451 |
| 91845 | GIM_Try, /*On fail goto*//*Label 6181*/ GIMT_Encode4(234482), // Rule ID 1553 // |
| 91846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 91847 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 91848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91849 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 91850 | // (fp_to_uint:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_WU_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 91851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S_INX), |
| 91852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91853 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91855 | GIR_RootConstrainSelectedInstOperands, |
| 91856 | // GIR_Coverage, 1553, |
| 91857 | GIR_EraseRootFromParent_Done, |
| 91858 | // Label 6181: @234482 |
| 91859 | GIM_Try, /*On fail goto*//*Label 6182*/ GIMT_Encode4(234513), // Rule ID 1554 // |
| 91860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 91861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 91862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91863 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 91864 | // (fp_to_uint:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_WU_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] }) |
| 91865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S_INX), |
| 91866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91867 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91869 | GIR_RootConstrainSelectedInstOperands, |
| 91870 | // GIR_Coverage, 1554, |
| 91871 | GIR_EraseRootFromParent_Done, |
| 91872 | // Label 6182: @234513 |
| 91873 | GIM_Try, /*On fail goto*//*Label 6183*/ GIMT_Encode4(234544), // Rule ID 1908 // |
| 91874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 91875 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 91876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91877 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 91878 | // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 91879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_D), |
| 91880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91881 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91883 | GIR_RootConstrainSelectedInstOperands, |
| 91884 | // GIR_Coverage, 1908, |
| 91885 | GIR_EraseRootFromParent_Done, |
| 91886 | // Label 6183: @234544 |
| 91887 | GIM_Try, /*On fail goto*//*Label 6184*/ GIMT_Encode4(234575), // Rule ID 1909 // |
| 91888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 91889 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 91890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 91892 | // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) |
| 91893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_D), |
| 91894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91895 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91897 | GIR_RootConstrainSelectedInstOperands, |
| 91898 | // GIR_Coverage, 1909, |
| 91899 | GIR_EraseRootFromParent_Done, |
| 91900 | // Label 6184: @234575 |
| 91901 | GIM_Try, /*On fail goto*//*Label 6185*/ GIMT_Encode4(234606), // Rule ID 1934 // |
| 91902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 91903 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 91904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91905 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 91906 | // (fp_to_uint:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_WU_D_IN32X:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 91907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_D_IN32X), |
| 91908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91909 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91911 | GIR_RootConstrainSelectedInstOperands, |
| 91912 | // GIR_Coverage, 1934, |
| 91913 | GIR_EraseRootFromParent_Done, |
| 91914 | // Label 6185: @234606 |
| 91915 | GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(234637), // Rule ID 1935 // |
| 91916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 91917 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 91918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91919 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 91920 | // (fp_to_uint:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_WU_D_IN32X:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1, 1:{ *:[i32] }) |
| 91921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_D_IN32X), |
| 91922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91923 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91925 | GIR_RootConstrainSelectedInstOperands, |
| 91926 | // GIR_Coverage, 1935, |
| 91927 | GIR_EraseRootFromParent_Done, |
| 91928 | // Label 6186: @234637 |
| 91929 | GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(234668), // Rule ID 2244 // |
| 91930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 91931 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 91932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 91934 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_WU_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 91935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_H), |
| 91936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91937 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91939 | GIR_RootConstrainSelectedInstOperands, |
| 91940 | // GIR_Coverage, 2244, |
| 91941 | GIR_EraseRootFromParent_Done, |
| 91942 | // Label 6187: @234668 |
| 91943 | GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(234699), // Rule ID 2245 // |
| 91944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 91945 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 91946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91947 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 91948 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_WU_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i32] }) |
| 91949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_H), |
| 91950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91951 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91953 | GIR_RootConstrainSelectedInstOperands, |
| 91954 | // GIR_Coverage, 2245, |
| 91955 | GIR_EraseRootFromParent_Done, |
| 91956 | // Label 6188: @234699 |
| 91957 | GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(234730), // Rule ID 2270 // |
| 91958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 91959 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 91960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91961 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 91962 | // (fp_to_uint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_WU_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 91963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_H_INX), |
| 91964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91965 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91967 | GIR_RootConstrainSelectedInstOperands, |
| 91968 | // GIR_Coverage, 2270, |
| 91969 | GIR_EraseRootFromParent_Done, |
| 91970 | // Label 6189: @234730 |
| 91971 | GIM_Try, /*On fail goto*//*Label 6190*/ GIMT_Encode4(234761), // Rule ID 2271 // |
| 91972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 91973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 91974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 91976 | // (fp_to_uint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_WU_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 1:{ *:[i32] }) |
| 91977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_H_INX), |
| 91978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91979 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 91980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 91981 | GIR_RootConstrainSelectedInstOperands, |
| 91982 | // GIR_Coverage, 2271, |
| 91983 | GIR_EraseRootFromParent_Done, |
| 91984 | // Label 6190: @234761 |
| 91985 | GIM_Try, /*On fail goto*//*Label 6191*/ GIMT_Encode4(234814), // Rule ID 2378 // |
| 91986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0), |
| 91987 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 91988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 91989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 91990 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_WU_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 91991 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 91992 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 91993 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 91994 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 91995 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 91996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 91997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S), |
| 91998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 91999 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92001 | GIR_RootConstrainSelectedInstOperands, |
| 92002 | // GIR_Coverage, 2378, |
| 92003 | GIR_EraseRootFromParent_Done, |
| 92004 | // Label 6191: @234814 |
| 92005 | GIM_Try, /*On fail goto*//*Label 6192*/ GIMT_Encode4(234867), // Rule ID 2379 // |
| 92006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1), |
| 92007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 92010 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_WU_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 1:{ *:[i32] }) |
| 92011 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92012 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 92013 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92014 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92015 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S), |
| 92018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92019 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92021 | GIR_RootConstrainSelectedInstOperands, |
| 92022 | // GIR_Coverage, 2379, |
| 92023 | GIR_EraseRootFromParent_Done, |
| 92024 | // Label 6192: @234867 |
| 92025 | GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(234920), // Rule ID 2402 // |
| 92026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0), |
| 92027 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 92030 | // (fp_to_uint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_WU_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 92031 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 92033 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92035 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S_INX), |
| 92038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92039 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92041 | GIR_RootConstrainSelectedInstOperands, |
| 92042 | // GIR_Coverage, 2402, |
| 92043 | GIR_EraseRootFromParent_Done, |
| 92044 | // Label 6193: @234920 |
| 92045 | GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(234973), // Rule ID 2403 // |
| 92046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1), |
| 92047 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92048 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92049 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 92050 | // (fp_to_uint:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_WU_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 1:{ *:[i32] }) |
| 92051 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92052 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 92053 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92054 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92055 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S_INX), |
| 92058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92061 | GIR_RootConstrainSelectedInstOperands, |
| 92062 | // GIR_Coverage, 2403, |
| 92063 | GIR_EraseRootFromParent_Done, |
| 92064 | // Label 6194: @234973 |
| 92065 | GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(235026), // Rule ID 2472 // |
| 92066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode0), |
| 92067 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92069 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 92070 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[bf16] }:$rs1) => (FCVT_WU_S:{ *:[i32] } (FCVT_S_BF16:{ *:[f32] } ?:{ *:[bf16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 92071 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92072 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_BF16), |
| 92073 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92074 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92075 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92076 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S), |
| 92078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92079 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92081 | GIR_RootConstrainSelectedInstOperands, |
| 92082 | // GIR_Coverage, 2472, |
| 92083 | GIR_EraseRootFromParent_Done, |
| 92084 | // Label 6195: @235026 |
| 92085 | GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(235079), // Rule ID 2473 // |
| 92086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode1), |
| 92087 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92089 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 92090 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[bf16] }:$rs1) => (FCVT_WU_S:{ *:[i32] } (FCVT_S_BF16:{ *:[f32] } ?:{ *:[bf16] }:$rs1, 0:{ *:[i32] }), 1:{ *:[i32] }) |
| 92091 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92092 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_BF16), |
| 92093 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92094 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92095 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_WU_S), |
| 92098 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92099 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92101 | GIR_RootConstrainSelectedInstOperands, |
| 92102 | // GIR_Coverage, 2473, |
| 92103 | GIR_EraseRootFromParent_Done, |
| 92104 | // Label 6196: @235079 |
| 92105 | GIM_Reject, |
| 92106 | // Label 6156: @235080 |
| 92107 | GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(235111), // Rule ID 1582 // |
| 92108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 92109 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 92110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92111 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 92112 | // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_LU_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 92113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_S), |
| 92114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92115 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92117 | GIR_RootConstrainSelectedInstOperands, |
| 92118 | // GIR_Coverage, 1582, |
| 92119 | GIR_EraseRootFromParent_Done, |
| 92120 | // Label 6197: @235111 |
| 92121 | GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(235142), // Rule ID 1610 // |
| 92122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 92123 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 92124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92125 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 92126 | // (fp_to_uint:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_LU_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] }) |
| 92127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_S_INX), |
| 92128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92129 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92131 | GIR_RootConstrainSelectedInstOperands, |
| 92132 | // GIR_Coverage, 1610, |
| 92133 | GIR_EraseRootFromParent_Done, |
| 92134 | // Label 6198: @235142 |
| 92135 | GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(235173), // Rule ID 1969 // |
| 92136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 92137 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 92138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 92140 | // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 92141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_D), |
| 92142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92143 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92145 | GIR_RootConstrainSelectedInstOperands, |
| 92146 | // GIR_Coverage, 1969, |
| 92147 | GIR_EraseRootFromParent_Done, |
| 92148 | // Label 6199: @235173 |
| 92149 | GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(235204), // Rule ID 1997 // |
| 92150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 92151 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 92152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92153 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92154 | // (fp_to_uint:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_LU_D_INX:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1, 1:{ *:[i64] }) |
| 92155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_D_INX), |
| 92156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92157 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92159 | GIR_RootConstrainSelectedInstOperands, |
| 92160 | // GIR_Coverage, 1997, |
| 92161 | GIR_EraseRootFromParent_Done, |
| 92162 | // Label 6200: @235204 |
| 92163 | GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(235235), // Rule ID 2297 // |
| 92164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 92165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 92168 | // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_LU_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 92169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_H), |
| 92170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92171 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92173 | GIR_RootConstrainSelectedInstOperands, |
| 92174 | // GIR_Coverage, 2297, |
| 92175 | GIR_EraseRootFromParent_Done, |
| 92176 | // Label 6201: @235235 |
| 92177 | GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(235266), // Rule ID 2323 // |
| 92178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 92179 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92181 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 92182 | // (fp_to_uint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_LU_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, 1:{ *:[i64] }) |
| 92183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_H_INX), |
| 92184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92185 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92187 | GIR_RootConstrainSelectedInstOperands, |
| 92188 | // GIR_Coverage, 2323, |
| 92189 | GIR_EraseRootFromParent_Done, |
| 92190 | // Label 6202: @235266 |
| 92191 | GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(235319), // Rule ID 2423 // |
| 92192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 92193 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92195 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 92196 | // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_LU_S:{ *:[i64] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 92197 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92198 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 92199 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92200 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92201 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_S), |
| 92204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92205 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92207 | GIR_RootConstrainSelectedInstOperands, |
| 92208 | // GIR_Coverage, 2423, |
| 92209 | GIR_EraseRootFromParent_Done, |
| 92210 | // Label 6203: @235319 |
| 92211 | GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(235372), // Rule ID 2439 // |
| 92212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 92213 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92214 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92215 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 92216 | // (fp_to_uint:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_LU_S_INX:{ *:[i64] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 92217 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92218 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 92219 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92220 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92221 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92222 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_S_INX), |
| 92224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92225 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92227 | GIR_RootConstrainSelectedInstOperands, |
| 92228 | // GIR_Coverage, 2439, |
| 92229 | GIR_EraseRootFromParent_Done, |
| 92230 | // Label 6204: @235372 |
| 92231 | GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(235425), // Rule ID 2485 // |
| 92232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_IsRV64_HwMode0), |
| 92233 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 92234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 92235 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 92236 | // (fp_to_uint:{ *:[i64] } FPR16:{ *:[bf16] }:$rs1) => (FCVT_LU_S:{ *:[i64] } (FCVT_S_BF16:{ *:[f32] } ?:{ *:[bf16] }:$rs1, 0:{ *:[i64] }), 1:{ *:[i64] }) |
| 92237 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 92238 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_BF16), |
| 92239 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92240 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 92241 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 92242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_LU_S), |
| 92244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 92247 | GIR_RootConstrainSelectedInstOperands, |
| 92248 | // GIR_Coverage, 2485, |
| 92249 | GIR_EraseRootFromParent_Done, |
| 92250 | // Label 6205: @235425 |
| 92251 | GIM_Reject, |
| 92252 | // Label 6157: @235426 |
| 92253 | GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(235529), |
| 92254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 92255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92257 | GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(235485), // Rule ID 59268 // |
| 92258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92259 | // (fp_to_uint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 92260 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 92261 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92262 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF8), |
| 92265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92266 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92267 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92271 | GIR_RootConstrainSelectedInstOperands, |
| 92272 | // GIR_Coverage, 59268, |
| 92273 | GIR_EraseRootFromParent_Done, |
| 92274 | // Label 6207: @235485 |
| 92275 | GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(235528), // Rule ID 59269 // |
| 92276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92277 | // (fp_to_uint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 92278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 92279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF8), |
| 92283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92289 | GIR_RootConstrainSelectedInstOperands, |
| 92290 | // GIR_Coverage, 59269, |
| 92291 | GIR_EraseRootFromParent_Done, |
| 92292 | // Label 6208: @235528 |
| 92293 | GIM_Reject, |
| 92294 | // Label 6206: @235529 |
| 92295 | GIM_Reject, |
| 92296 | // Label 6158: @235530 |
| 92297 | GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(235584), // Rule ID 58852 // |
| 92298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92299 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 92300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92301 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92302 | // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 92304 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92305 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_MF4), |
| 92308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92310 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92314 | GIR_RootConstrainSelectedInstOperands, |
| 92315 | // GIR_Coverage, 58852, |
| 92316 | GIR_EraseRootFromParent_Done, |
| 92317 | // Label 6209: @235584 |
| 92318 | GIM_Try, /*On fail goto*//*Label 6210*/ GIMT_Encode4(235638), // Rule ID 58853 // |
| 92319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92320 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 92321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92323 | // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 92324 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 92325 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92326 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92327 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_MF4), |
| 92329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92330 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92331 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92335 | GIR_RootConstrainSelectedInstOperands, |
| 92336 | // GIR_Coverage, 58853, |
| 92337 | GIR_EraseRootFromParent_Done, |
| 92338 | // Label 6210: @235638 |
| 92339 | GIM_Try, /*On fail goto*//*Label 6211*/ GIMT_Encode4(235692), // Rule ID 59292 // |
| 92340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 92341 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 92342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92343 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92344 | // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92345 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 92346 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92347 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92349 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4), |
| 92350 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92351 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92352 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92356 | GIR_RootConstrainSelectedInstOperands, |
| 92357 | // GIR_Coverage, 59292, |
| 92358 | GIR_EraseRootFromParent_Done, |
| 92359 | // Label 6211: @235692 |
| 92360 | GIM_Try, /*On fail goto*//*Label 6212*/ GIMT_Encode4(235746), // Rule ID 59293 // |
| 92361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 92362 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 92363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92364 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92365 | // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 92366 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 92367 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92368 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4), |
| 92371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92372 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92373 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92377 | GIR_RootConstrainSelectedInstOperands, |
| 92378 | // GIR_Coverage, 59293, |
| 92379 | GIR_EraseRootFromParent_Done, |
| 92380 | // Label 6212: @235746 |
| 92381 | GIM_Reject, |
| 92382 | // Label 6159: @235747 |
| 92383 | GIM_Try, /*On fail goto*//*Label 6213*/ GIMT_Encode4(235801), // Rule ID 58860 // |
| 92384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 92385 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 92386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92387 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92388 | // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 92389 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 92390 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92391 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92392 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2), |
| 92394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92395 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92396 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92400 | GIR_RootConstrainSelectedInstOperands, |
| 92401 | // GIR_Coverage, 58860, |
| 92402 | GIR_EraseRootFromParent_Done, |
| 92403 | // Label 6213: @235801 |
| 92404 | GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(235855), // Rule ID 58861 // |
| 92405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 92406 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 92407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92409 | // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 92410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 92411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2), |
| 92415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92416 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92417 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92421 | GIR_RootConstrainSelectedInstOperands, |
| 92422 | // GIR_Coverage, 58861, |
| 92423 | GIR_EraseRootFromParent_Done, |
| 92424 | // Label 6214: @235855 |
| 92425 | GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(235909), // Rule ID 59060 // |
| 92426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92427 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 92428 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92429 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92430 | // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92431 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 92432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92433 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF4), |
| 92436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92438 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92442 | GIR_RootConstrainSelectedInstOperands, |
| 92443 | // GIR_Coverage, 59060, |
| 92444 | GIR_EraseRootFromParent_Done, |
| 92445 | // Label 6215: @235909 |
| 92446 | GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(235963), // Rule ID 59061 // |
| 92447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92448 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 92449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92450 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92451 | // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 92452 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 92453 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92454 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF4), |
| 92457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92458 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92459 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92463 | GIR_RootConstrainSelectedInstOperands, |
| 92464 | // GIR_Coverage, 59061, |
| 92465 | GIR_EraseRootFromParent_Done, |
| 92466 | // Label 6216: @235963 |
| 92467 | GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(236017), // Rule ID 59312 // |
| 92468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 92469 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 92470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92471 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92472 | // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 92473 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 92474 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92475 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2), |
| 92478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92479 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92480 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92484 | GIR_RootConstrainSelectedInstOperands, |
| 92485 | // GIR_Coverage, 59312, |
| 92486 | GIR_EraseRootFromParent_Done, |
| 92487 | // Label 6217: @236017 |
| 92488 | GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(236071), // Rule ID 59313 // |
| 92489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 92490 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 92491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92493 | // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 92494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 92495 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92496 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2), |
| 92499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92500 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92501 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92505 | GIR_RootConstrainSelectedInstOperands, |
| 92506 | // GIR_Coverage, 59313, |
| 92507 | GIR_EraseRootFromParent_Done, |
| 92508 | // Label 6218: @236071 |
| 92509 | GIM_Reject, |
| 92510 | // Label 6160: @236072 |
| 92511 | GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(236126), // Rule ID 58872 // |
| 92512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 92513 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 92514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92515 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92516 | // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 92517 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 92518 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92519 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M1), |
| 92522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92523 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92524 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 92527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92528 | GIR_RootConstrainSelectedInstOperands, |
| 92529 | // GIR_Coverage, 58872, |
| 92530 | GIR_EraseRootFromParent_Done, |
| 92531 | // Label 6219: @236126 |
| 92532 | GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(236180), // Rule ID 58873 // |
| 92533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 92534 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 92535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92537 | // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 92538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 92539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M1), |
| 92543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92545 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 92548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92549 | GIR_RootConstrainSelectedInstOperands, |
| 92550 | // GIR_Coverage, 58873, |
| 92551 | GIR_EraseRootFromParent_Done, |
| 92552 | // Label 6220: @236180 |
| 92553 | GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(236234), // Rule ID 59080 // |
| 92554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 92555 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 92556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92558 | // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 92559 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 92560 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92561 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92562 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2), |
| 92564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92565 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92566 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92570 | GIR_RootConstrainSelectedInstOperands, |
| 92571 | // GIR_Coverage, 59080, |
| 92572 | GIR_EraseRootFromParent_Done, |
| 92573 | // Label 6221: @236234 |
| 92574 | GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(236288), // Rule ID 59081 // |
| 92575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 92576 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 92577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92579 | // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 92580 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 92581 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92582 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2), |
| 92585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92586 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92587 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92591 | GIR_RootConstrainSelectedInstOperands, |
| 92592 | // GIR_Coverage, 59081, |
| 92593 | GIR_EraseRootFromParent_Done, |
| 92594 | // Label 6222: @236288 |
| 92595 | GIM_Reject, |
| 92596 | // Label 6161: @236289 |
| 92597 | GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(236392), |
| 92598 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 92599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92600 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92601 | GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(236348), // Rule ID 59272 // |
| 92602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92603 | // (fp_to_uint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 92604 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 92605 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92606 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4), |
| 92609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92610 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92611 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92615 | GIR_RootConstrainSelectedInstOperands, |
| 92616 | // GIR_Coverage, 59272, |
| 92617 | GIR_EraseRootFromParent_Done, |
| 92618 | // Label 6224: @236348 |
| 92619 | GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(236391), // Rule ID 59273 // |
| 92620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92621 | // (fp_to_uint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 92622 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 92623 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92624 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4), |
| 92627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92629 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92633 | GIR_RootConstrainSelectedInstOperands, |
| 92634 | // GIR_Coverage, 59273, |
| 92635 | GIR_EraseRootFromParent_Done, |
| 92636 | // Label 6225: @236391 |
| 92637 | GIM_Reject, |
| 92638 | // Label 6223: @236392 |
| 92639 | GIM_Reject, |
| 92640 | // Label 6162: @236393 |
| 92641 | GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(236447), // Rule ID 58856 // |
| 92642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92643 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 92644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92645 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92646 | // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92647 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 92648 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2), |
| 92652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92654 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92658 | GIR_RootConstrainSelectedInstOperands, |
| 92659 | // GIR_Coverage, 58856, |
| 92660 | GIR_EraseRootFromParent_Done, |
| 92661 | // Label 6226: @236447 |
| 92662 | GIM_Try, /*On fail goto*//*Label 6227*/ GIMT_Encode4(236501), // Rule ID 58857 // |
| 92663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92664 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 92665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92666 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92667 | // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 92668 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 92669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92670 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2), |
| 92673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92674 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92675 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92679 | GIR_RootConstrainSelectedInstOperands, |
| 92680 | // GIR_Coverage, 58857, |
| 92681 | GIR_EraseRootFromParent_Done, |
| 92682 | // Label 6227: @236501 |
| 92683 | GIM_Try, /*On fail goto*//*Label 6228*/ GIMT_Encode4(236555), // Rule ID 59296 // |
| 92684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 92685 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 92686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92687 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92688 | // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92689 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 92690 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92691 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2), |
| 92694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92695 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92696 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92700 | GIR_RootConstrainSelectedInstOperands, |
| 92701 | // GIR_Coverage, 59296, |
| 92702 | GIR_EraseRootFromParent_Done, |
| 92703 | // Label 6228: @236555 |
| 92704 | GIM_Try, /*On fail goto*//*Label 6229*/ GIMT_Encode4(236609), // Rule ID 59297 // |
| 92705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 92706 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 92707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92708 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92709 | // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 92710 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 92711 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2), |
| 92715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92716 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92717 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92721 | GIR_RootConstrainSelectedInstOperands, |
| 92722 | // GIR_Coverage, 59297, |
| 92723 | GIR_EraseRootFromParent_Done, |
| 92724 | // Label 6229: @236609 |
| 92725 | GIM_Reject, |
| 92726 | // Label 6163: @236610 |
| 92727 | GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(236664), // Rule ID 58868 // |
| 92728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 92729 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 92730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92731 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92732 | // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 92733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 92734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M1), |
| 92738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92739 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92740 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92744 | GIR_RootConstrainSelectedInstOperands, |
| 92745 | // GIR_Coverage, 58868, |
| 92746 | GIR_EraseRootFromParent_Done, |
| 92747 | // Label 6230: @236664 |
| 92748 | GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(236718), // Rule ID 58869 // |
| 92749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 92750 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 92751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92753 | // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 92754 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 92755 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92756 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M1), |
| 92759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92760 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92761 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92765 | GIR_RootConstrainSelectedInstOperands, |
| 92766 | // GIR_Coverage, 58869, |
| 92767 | GIR_EraseRootFromParent_Done, |
| 92768 | // Label 6231: @236718 |
| 92769 | GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(236772), // Rule ID 59064 // |
| 92770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92771 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 92772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92773 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92774 | // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92775 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 92776 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92777 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92778 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2), |
| 92780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92781 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92782 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92786 | GIR_RootConstrainSelectedInstOperands, |
| 92787 | // GIR_Coverage, 59064, |
| 92788 | GIR_EraseRootFromParent_Done, |
| 92789 | // Label 6232: @236772 |
| 92790 | GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(236826), // Rule ID 59065 // |
| 92791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92792 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 92793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92794 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92795 | // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 92796 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 92797 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92798 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2), |
| 92801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92802 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92803 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 92806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92807 | GIR_RootConstrainSelectedInstOperands, |
| 92808 | // GIR_Coverage, 59065, |
| 92809 | GIR_EraseRootFromParent_Done, |
| 92810 | // Label 6233: @236826 |
| 92811 | GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(236880), // Rule ID 59316 // |
| 92812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 92813 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 92814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92816 | // (fp_to_uint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 92817 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 92818 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92819 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1), |
| 92822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92823 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92824 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92828 | GIR_RootConstrainSelectedInstOperands, |
| 92829 | // GIR_Coverage, 59316, |
| 92830 | GIR_EraseRootFromParent_Done, |
| 92831 | // Label 6234: @236880 |
| 92832 | GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(236934), // Rule ID 59317 // |
| 92833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 92834 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 92835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92837 | // (fp_to_uint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 92838 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 92839 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92840 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1), |
| 92843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92844 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92845 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92849 | GIR_RootConstrainSelectedInstOperands, |
| 92850 | // GIR_Coverage, 59317, |
| 92851 | GIR_EraseRootFromParent_Done, |
| 92852 | // Label 6235: @236934 |
| 92853 | GIM_Reject, |
| 92854 | // Label 6164: @236935 |
| 92855 | GIM_Try, /*On fail goto*//*Label 6236*/ GIMT_Encode4(236989), // Rule ID 58900 // |
| 92856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 92857 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 92858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92859 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92860 | // (fp_to_uint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 92861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 92862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92864 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M2), |
| 92866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92868 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 92871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92872 | GIR_RootConstrainSelectedInstOperands, |
| 92873 | // GIR_Coverage, 58900, |
| 92874 | GIR_EraseRootFromParent_Done, |
| 92875 | // Label 6236: @236989 |
| 92876 | GIM_Try, /*On fail goto*//*Label 6237*/ GIMT_Encode4(237043), // Rule ID 58901 // |
| 92877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 92878 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 92879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92880 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92881 | // (fp_to_uint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 92882 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 92883 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92884 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92885 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M2), |
| 92887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92888 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92889 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 92892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92893 | GIR_RootConstrainSelectedInstOperands, |
| 92894 | // GIR_Coverage, 58901, |
| 92895 | GIR_EraseRootFromParent_Done, |
| 92896 | // Label 6237: @237043 |
| 92897 | GIM_Try, /*On fail goto*//*Label 6238*/ GIMT_Encode4(237097), // Rule ID 59084 // |
| 92898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 92899 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 92900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92901 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92902 | // (fp_to_uint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 92903 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 92904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1), |
| 92908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92909 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92910 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92914 | GIR_RootConstrainSelectedInstOperands, |
| 92915 | // GIR_Coverage, 59084, |
| 92916 | GIR_EraseRootFromParent_Done, |
| 92917 | // Label 6238: @237097 |
| 92918 | GIM_Try, /*On fail goto*//*Label 6239*/ GIMT_Encode4(237151), // Rule ID 59085 // |
| 92919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 92920 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 92921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 92922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92923 | // (fp_to_uint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 92924 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 92925 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92926 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1), |
| 92929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92930 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92931 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 92934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92935 | GIR_RootConstrainSelectedInstOperands, |
| 92936 | // GIR_Coverage, 59085, |
| 92937 | GIR_EraseRootFromParent_Done, |
| 92938 | // Label 6239: @237151 |
| 92939 | GIM_Reject, |
| 92940 | // Label 6165: @237152 |
| 92941 | GIM_Try, /*On fail goto*//*Label 6240*/ GIMT_Encode4(237255), |
| 92942 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 92943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92944 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92945 | GIM_Try, /*On fail goto*//*Label 6241*/ GIMT_Encode4(237211), // Rule ID 59276 // |
| 92946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92947 | // (fp_to_uint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 92948 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 92949 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92950 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2), |
| 92953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92954 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92955 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92959 | GIR_RootConstrainSelectedInstOperands, |
| 92960 | // GIR_Coverage, 59276, |
| 92961 | GIR_EraseRootFromParent_Done, |
| 92962 | // Label 6241: @237211 |
| 92963 | GIM_Try, /*On fail goto*//*Label 6242*/ GIMT_Encode4(237254), // Rule ID 59277 // |
| 92964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 92965 | // (fp_to_uint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 92966 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 92967 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92968 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92969 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2), |
| 92971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92972 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92973 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 92975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 92977 | GIR_RootConstrainSelectedInstOperands, |
| 92978 | // GIR_Coverage, 59277, |
| 92979 | GIR_EraseRootFromParent_Done, |
| 92980 | // Label 6242: @237254 |
| 92981 | GIM_Reject, |
| 92982 | // Label 6240: @237255 |
| 92983 | GIM_Reject, |
| 92984 | // Label 6166: @237256 |
| 92985 | GIM_Try, /*On fail goto*//*Label 6243*/ GIMT_Encode4(237310), // Rule ID 58864 // |
| 92986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 92987 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 92988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 92990 | // (fp_to_uint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 92991 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 92992 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 92993 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 92994 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 92995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M1), |
| 92996 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 92997 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 92998 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 92999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93002 | GIR_RootConstrainSelectedInstOperands, |
| 93003 | // GIR_Coverage, 58864, |
| 93004 | GIR_EraseRootFromParent_Done, |
| 93005 | // Label 6243: @237310 |
| 93006 | GIM_Try, /*On fail goto*//*Label 6244*/ GIMT_Encode4(237364), // Rule ID 58865 // |
| 93007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93008 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 93009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93010 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93011 | // (fp_to_uint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93012 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 93013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M1), |
| 93017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93018 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93019 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93023 | GIR_RootConstrainSelectedInstOperands, |
| 93024 | // GIR_Coverage, 58865, |
| 93025 | GIR_EraseRootFromParent_Done, |
| 93026 | // Label 6244: @237364 |
| 93027 | GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(237418), // Rule ID 59300 // |
| 93028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 93029 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 93030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93032 | // (fp_to_uint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93033 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 93034 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93035 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1), |
| 93038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93039 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93040 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93044 | GIR_RootConstrainSelectedInstOperands, |
| 93045 | // GIR_Coverage, 59300, |
| 93046 | GIR_EraseRootFromParent_Done, |
| 93047 | // Label 6245: @237418 |
| 93048 | GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(237472), // Rule ID 59301 // |
| 93049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 93050 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 93051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93052 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93053 | // (fp_to_uint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 93055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1), |
| 93059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93060 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93061 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93065 | GIR_RootConstrainSelectedInstOperands, |
| 93066 | // GIR_Coverage, 59301, |
| 93067 | GIR_EraseRootFromParent_Done, |
| 93068 | // Label 6246: @237472 |
| 93069 | GIM_Reject, |
| 93070 | // Label 6167: @237473 |
| 93071 | GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(237527), // Rule ID 58888 // |
| 93072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 93073 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 93074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93075 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93076 | // (fp_to_uint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93077 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 93078 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93079 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M2), |
| 93082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93083 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93084 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93088 | GIR_RootConstrainSelectedInstOperands, |
| 93089 | // GIR_Coverage, 58888, |
| 93090 | GIR_EraseRootFromParent_Done, |
| 93091 | // Label 6247: @237527 |
| 93092 | GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(237581), // Rule ID 58889 // |
| 93093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 93094 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 93095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93096 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93097 | // (fp_to_uint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93098 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 93099 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93100 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M2), |
| 93103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93104 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93105 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93109 | GIR_RootConstrainSelectedInstOperands, |
| 93110 | // GIR_Coverage, 58889, |
| 93111 | GIR_EraseRootFromParent_Done, |
| 93112 | // Label 6248: @237581 |
| 93113 | GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(237635), // Rule ID 59068 // |
| 93114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93115 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 93116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93117 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93118 | // (fp_to_uint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93119 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 93120 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93121 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1), |
| 93124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93125 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93126 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93130 | GIR_RootConstrainSelectedInstOperands, |
| 93131 | // GIR_Coverage, 59068, |
| 93132 | GIR_EraseRootFromParent_Done, |
| 93133 | // Label 6249: @237635 |
| 93134 | GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(237689), // Rule ID 59069 // |
| 93135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93136 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 93137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93138 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93139 | // (fp_to_uint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93140 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 93141 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93142 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1), |
| 93145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93146 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93147 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93151 | GIR_RootConstrainSelectedInstOperands, |
| 93152 | // GIR_Coverage, 59069, |
| 93153 | GIR_EraseRootFromParent_Done, |
| 93154 | // Label 6250: @237689 |
| 93155 | GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(237743), // Rule ID 59320 // |
| 93156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 93157 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 93158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93159 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93160 | // (fp_to_uint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 93162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2), |
| 93166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93167 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93168 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93172 | GIR_RootConstrainSelectedInstOperands, |
| 93173 | // GIR_Coverage, 59320, |
| 93174 | GIR_EraseRootFromParent_Done, |
| 93175 | // Label 6251: @237743 |
| 93176 | GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(237797), // Rule ID 59321 // |
| 93177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 93178 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 93179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93181 | // (fp_to_uint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93182 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 93183 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93184 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2), |
| 93187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93188 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93189 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93193 | GIR_RootConstrainSelectedInstOperands, |
| 93194 | // GIR_Coverage, 59321, |
| 93195 | GIR_EraseRootFromParent_Done, |
| 93196 | // Label 6252: @237797 |
| 93197 | GIM_Reject, |
| 93198 | // Label 6168: @237798 |
| 93199 | GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(237852), // Rule ID 58904 // |
| 93200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 93201 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 93202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93203 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93204 | // (fp_to_uint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 93205 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 93206 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93207 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M4), |
| 93210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93211 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93212 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 93215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93216 | GIR_RootConstrainSelectedInstOperands, |
| 93217 | // GIR_Coverage, 58904, |
| 93218 | GIR_EraseRootFromParent_Done, |
| 93219 | // Label 6253: @237852 |
| 93220 | GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(237906), // Rule ID 58905 // |
| 93221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 93222 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 93223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93224 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93225 | // (fp_to_uint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 93226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 93227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M4), |
| 93231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93232 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93233 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 93236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93237 | GIR_RootConstrainSelectedInstOperands, |
| 93238 | // GIR_Coverage, 58905, |
| 93239 | GIR_EraseRootFromParent_Done, |
| 93240 | // Label 6254: @237906 |
| 93241 | GIM_Try, /*On fail goto*//*Label 6255*/ GIMT_Encode4(237960), // Rule ID 59088 // |
| 93242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 93243 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 93244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93245 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93246 | // (fp_to_uint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93247 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 93248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93249 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93250 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2), |
| 93252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93253 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93254 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93258 | GIR_RootConstrainSelectedInstOperands, |
| 93259 | // GIR_Coverage, 59088, |
| 93260 | GIR_EraseRootFromParent_Done, |
| 93261 | // Label 6255: @237960 |
| 93262 | GIM_Try, /*On fail goto*//*Label 6256*/ GIMT_Encode4(238014), // Rule ID 59089 // |
| 93263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 93264 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 93265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93266 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93267 | // (fp_to_uint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93268 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 93269 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2), |
| 93273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93274 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93275 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93279 | GIR_RootConstrainSelectedInstOperands, |
| 93280 | // GIR_Coverage, 59089, |
| 93281 | GIR_EraseRootFromParent_Done, |
| 93282 | // Label 6256: @238014 |
| 93283 | GIM_Reject, |
| 93284 | // Label 6169: @238015 |
| 93285 | GIM_Try, /*On fail goto*//*Label 6257*/ GIMT_Encode4(238118), |
| 93286 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 93287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 93288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93289 | GIM_Try, /*On fail goto*//*Label 6258*/ GIMT_Encode4(238074), // Rule ID 59280 // |
| 93290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93291 | // (fp_to_uint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 93292 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 93293 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93294 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93295 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1), |
| 93297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93298 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93299 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93303 | GIR_RootConstrainSelectedInstOperands, |
| 93304 | // GIR_Coverage, 59280, |
| 93305 | GIR_EraseRootFromParent_Done, |
| 93306 | // Label 6258: @238074 |
| 93307 | GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(238117), // Rule ID 59281 // |
| 93308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93309 | // (fp_to_uint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 93310 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 93311 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93312 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1), |
| 93315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93316 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93317 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93321 | GIR_RootConstrainSelectedInstOperands, |
| 93322 | // GIR_Coverage, 59281, |
| 93323 | GIR_EraseRootFromParent_Done, |
| 93324 | // Label 6259: @238117 |
| 93325 | GIM_Reject, |
| 93326 | // Label 6257: @238118 |
| 93327 | GIM_Reject, |
| 93328 | // Label 6170: @238119 |
| 93329 | GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(238173), // Rule ID 58876 // |
| 93330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93331 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 93332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93333 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93334 | // (fp_to_uint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93335 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 93336 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93337 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M2), |
| 93340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93342 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93346 | GIR_RootConstrainSelectedInstOperands, |
| 93347 | // GIR_Coverage, 58876, |
| 93348 | GIR_EraseRootFromParent_Done, |
| 93349 | // Label 6260: @238173 |
| 93350 | GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(238227), // Rule ID 58877 // |
| 93351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93352 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 93353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93354 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93355 | // (fp_to_uint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 93357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M2), |
| 93361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93363 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93367 | GIR_RootConstrainSelectedInstOperands, |
| 93368 | // GIR_Coverage, 58877, |
| 93369 | GIR_EraseRootFromParent_Done, |
| 93370 | // Label 6261: @238227 |
| 93371 | GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(238281), // Rule ID 59304 // |
| 93372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 93373 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 93374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93375 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93376 | // (fp_to_uint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93377 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 93378 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93379 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2), |
| 93382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93383 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93384 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93388 | GIR_RootConstrainSelectedInstOperands, |
| 93389 | // GIR_Coverage, 59304, |
| 93390 | GIR_EraseRootFromParent_Done, |
| 93391 | // Label 6262: @238281 |
| 93392 | GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(238335), // Rule ID 59305 // |
| 93393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 93394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 93395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93396 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93397 | // (fp_to_uint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93398 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 93399 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93400 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2), |
| 93403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93404 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93405 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93409 | GIR_RootConstrainSelectedInstOperands, |
| 93410 | // GIR_Coverage, 59305, |
| 93411 | GIR_EraseRootFromParent_Done, |
| 93412 | // Label 6263: @238335 |
| 93413 | GIM_Reject, |
| 93414 | // Label 6171: @238336 |
| 93415 | GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(238390), // Rule ID 58892 // |
| 93416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 93417 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 93418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93419 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93420 | // (fp_to_uint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93421 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 93422 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93423 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93424 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M4), |
| 93426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93427 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93428 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93432 | GIR_RootConstrainSelectedInstOperands, |
| 93433 | // GIR_Coverage, 58892, |
| 93434 | GIR_EraseRootFromParent_Done, |
| 93435 | // Label 6264: @238390 |
| 93436 | GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(238444), // Rule ID 58893 // |
| 93437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 93438 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 93439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93440 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93441 | // (fp_to_uint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93442 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 93443 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93444 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M4), |
| 93447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93448 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93449 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93453 | GIR_RootConstrainSelectedInstOperands, |
| 93454 | // GIR_Coverage, 58893, |
| 93455 | GIR_EraseRootFromParent_Done, |
| 93456 | // Label 6265: @238444 |
| 93457 | GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(238498), // Rule ID 59072 // |
| 93458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93459 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 93460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93461 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93462 | // (fp_to_uint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93463 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 93464 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93465 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93466 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2), |
| 93468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93469 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93470 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93474 | GIR_RootConstrainSelectedInstOperands, |
| 93475 | // GIR_Coverage, 59072, |
| 93476 | GIR_EraseRootFromParent_Done, |
| 93477 | // Label 6266: @238498 |
| 93478 | GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(238552), // Rule ID 59073 // |
| 93479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 93481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93483 | // (fp_to_uint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 93485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2), |
| 93489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93490 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93491 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93495 | GIR_RootConstrainSelectedInstOperands, |
| 93496 | // GIR_Coverage, 59073, |
| 93497 | GIR_EraseRootFromParent_Done, |
| 93498 | // Label 6267: @238552 |
| 93499 | GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(238606), // Rule ID 59324 // |
| 93500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 93501 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 93502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93504 | // (fp_to_uint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93505 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 93506 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93507 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4), |
| 93510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93511 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93512 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93516 | GIR_RootConstrainSelectedInstOperands, |
| 93517 | // GIR_Coverage, 59324, |
| 93518 | GIR_EraseRootFromParent_Done, |
| 93519 | // Label 6268: @238606 |
| 93520 | GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(238660), // Rule ID 59325 // |
| 93521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 93522 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 93523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93524 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93525 | // (fp_to_uint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93526 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 93527 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93528 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93529 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4), |
| 93531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93532 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93533 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93537 | GIR_RootConstrainSelectedInstOperands, |
| 93538 | // GIR_Coverage, 59325, |
| 93539 | GIR_EraseRootFromParent_Done, |
| 93540 | // Label 6269: @238660 |
| 93541 | GIM_Reject, |
| 93542 | // Label 6172: @238661 |
| 93543 | GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(238715), // Rule ID 58908 // |
| 93544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 93545 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 93546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93547 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93548 | // (fp_to_uint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 93549 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 93550 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93551 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M8), |
| 93554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93555 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93556 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 93559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93560 | GIR_RootConstrainSelectedInstOperands, |
| 93561 | // GIR_Coverage, 58908, |
| 93562 | GIR_EraseRootFromParent_Done, |
| 93563 | // Label 6270: @238715 |
| 93564 | GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(238769), // Rule ID 58909 // |
| 93565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 93566 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 93567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93568 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93569 | // (fp_to_uint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 93570 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 93571 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93572 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93573 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M8), |
| 93575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93576 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93577 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 93580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93581 | GIR_RootConstrainSelectedInstOperands, |
| 93582 | // GIR_Coverage, 58909, |
| 93583 | GIR_EraseRootFromParent_Done, |
| 93584 | // Label 6271: @238769 |
| 93585 | GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(238823), // Rule ID 59092 // |
| 93586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 93587 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 93588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93590 | // (fp_to_uint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93591 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 93592 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93593 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93594 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4), |
| 93596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93597 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93598 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93602 | GIR_RootConstrainSelectedInstOperands, |
| 93603 | // GIR_Coverage, 59092, |
| 93604 | GIR_EraseRootFromParent_Done, |
| 93605 | // Label 6272: @238823 |
| 93606 | GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(238877), // Rule ID 59093 // |
| 93607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 93608 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 93609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93610 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93611 | // (fp_to_uint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93612 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 93613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4), |
| 93617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93618 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93619 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93623 | GIR_RootConstrainSelectedInstOperands, |
| 93624 | // GIR_Coverage, 59093, |
| 93625 | GIR_EraseRootFromParent_Done, |
| 93626 | // Label 6273: @238877 |
| 93627 | GIM_Reject, |
| 93628 | // Label 6173: @238878 |
| 93629 | GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(238981), |
| 93630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 93631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 93632 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93633 | GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(238937), // Rule ID 59284 // |
| 93634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93635 | // (fp_to_uint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 93636 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 93637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93638 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2), |
| 93641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93642 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93643 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93647 | GIR_RootConstrainSelectedInstOperands, |
| 93648 | // GIR_Coverage, 59284, |
| 93649 | GIR_EraseRootFromParent_Done, |
| 93650 | // Label 6275: @238937 |
| 93651 | GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(238980), // Rule ID 59285 // |
| 93652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93653 | // (fp_to_uint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 93654 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 93655 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93656 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2), |
| 93659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93660 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93661 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93665 | GIR_RootConstrainSelectedInstOperands, |
| 93666 | // GIR_Coverage, 59285, |
| 93667 | GIR_EraseRootFromParent_Done, |
| 93668 | // Label 6276: @238980 |
| 93669 | GIM_Reject, |
| 93670 | // Label 6274: @238981 |
| 93671 | GIM_Reject, |
| 93672 | // Label 6174: @238982 |
| 93673 | GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(239036), // Rule ID 58880 // |
| 93674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93675 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 93676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93677 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93678 | // (fp_to_uint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93679 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 93680 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93681 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93682 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M4), |
| 93684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93685 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93686 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93690 | GIR_RootConstrainSelectedInstOperands, |
| 93691 | // GIR_Coverage, 58880, |
| 93692 | GIR_EraseRootFromParent_Done, |
| 93693 | // Label 6277: @239036 |
| 93694 | GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(239090), // Rule ID 58881 // |
| 93695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93696 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 93697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93698 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93699 | // (fp_to_uint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93700 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 93701 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93702 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M4), |
| 93705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93706 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93707 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93711 | GIR_RootConstrainSelectedInstOperands, |
| 93712 | // GIR_Coverage, 58881, |
| 93713 | GIR_EraseRootFromParent_Done, |
| 93714 | // Label 6278: @239090 |
| 93715 | GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(239144), // Rule ID 59308 // |
| 93716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 93717 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 93718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93719 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93720 | // (fp_to_uint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93721 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 93722 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93723 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4), |
| 93726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93727 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93728 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93732 | GIR_RootConstrainSelectedInstOperands, |
| 93733 | // GIR_Coverage, 59308, |
| 93734 | GIR_EraseRootFromParent_Done, |
| 93735 | // Label 6279: @239144 |
| 93736 | GIM_Try, /*On fail goto*//*Label 6280*/ GIMT_Encode4(239198), // Rule ID 59309 // |
| 93737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 93738 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 93739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93741 | // (fp_to_uint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93742 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 93743 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93744 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93745 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4), |
| 93747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93748 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93749 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93753 | GIR_RootConstrainSelectedInstOperands, |
| 93754 | // GIR_Coverage, 59309, |
| 93755 | GIR_EraseRootFromParent_Done, |
| 93756 | // Label 6280: @239198 |
| 93757 | GIM_Reject, |
| 93758 | // Label 6175: @239199 |
| 93759 | GIM_Try, /*On fail goto*//*Label 6281*/ GIMT_Encode4(239253), // Rule ID 58896 // |
| 93760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 93761 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 93762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93763 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93764 | // (fp_to_uint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 93765 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 93766 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93767 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M8), |
| 93770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93771 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93772 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93776 | GIR_RootConstrainSelectedInstOperands, |
| 93777 | // GIR_Coverage, 58896, |
| 93778 | GIR_EraseRootFromParent_Done, |
| 93779 | // Label 6281: @239253 |
| 93780 | GIM_Try, /*On fail goto*//*Label 6282*/ GIMT_Encode4(239307), // Rule ID 58897 // |
| 93781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 93782 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 93783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93784 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93785 | // (fp_to_uint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 93786 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 93787 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93788 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M8), |
| 93791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93792 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93793 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 93796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93797 | GIR_RootConstrainSelectedInstOperands, |
| 93798 | // GIR_Coverage, 58897, |
| 93799 | GIR_EraseRootFromParent_Done, |
| 93800 | // Label 6282: @239307 |
| 93801 | GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(239361), // Rule ID 59076 // |
| 93802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93803 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 93804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93806 | // (fp_to_uint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 93808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4), |
| 93812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93818 | GIR_RootConstrainSelectedInstOperands, |
| 93819 | // GIR_Coverage, 59076, |
| 93820 | GIR_EraseRootFromParent_Done, |
| 93821 | // Label 6283: @239361 |
| 93822 | GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(239415), // Rule ID 59077 // |
| 93823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93824 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 93825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93827 | // (fp_to_uint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1) => (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 93829 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93830 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4), |
| 93833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93835 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93839 | GIR_RootConstrainSelectedInstOperands, |
| 93840 | // GIR_Coverage, 59077, |
| 93841 | GIR_EraseRootFromParent_Done, |
| 93842 | // Label 6284: @239415 |
| 93843 | GIM_Reject, |
| 93844 | // Label 6176: @239416 |
| 93845 | GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(239519), |
| 93846 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 93847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 93848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93849 | GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(239475), // Rule ID 59288 // |
| 93850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93851 | // (fp_to_uint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 93852 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 93853 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93854 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4), |
| 93857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93858 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93859 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93863 | GIR_RootConstrainSelectedInstOperands, |
| 93864 | // GIR_Coverage, 59288, |
| 93865 | GIR_EraseRootFromParent_Done, |
| 93866 | // Label 6286: @239475 |
| 93867 | GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(239518), // Rule ID 59289 // |
| 93868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93869 | // (fp_to_uint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 93870 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 93871 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93872 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93873 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4), |
| 93875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93876 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93877 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93881 | GIR_RootConstrainSelectedInstOperands, |
| 93882 | // GIR_Coverage, 59289, |
| 93883 | GIR_EraseRootFromParent_Done, |
| 93884 | // Label 6287: @239518 |
| 93885 | GIM_Reject, |
| 93886 | // Label 6285: @239519 |
| 93887 | GIM_Reject, |
| 93888 | // Label 6177: @239520 |
| 93889 | GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(239623), |
| 93890 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 93891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93892 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 93893 | GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(239579), // Rule ID 58884 // |
| 93894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 93895 | // (fp_to_uint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 93896 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 93897 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93898 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93899 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M8), |
| 93901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93902 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93903 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93907 | GIR_RootConstrainSelectedInstOperands, |
| 93908 | // GIR_Coverage, 58884, |
| 93909 | GIR_EraseRootFromParent_Done, |
| 93910 | // Label 6289: @239579 |
| 93911 | GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(239622), // Rule ID 58885 // |
| 93912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 93913 | // (fp_to_uint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1) => (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 93914 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 93915 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 93916 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 93917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 93918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_RTZ_XU_F_V_M8), |
| 93919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93920 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 93921 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 93923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 93924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 93925 | GIR_RootConstrainSelectedInstOperands, |
| 93926 | // GIR_Coverage, 58885, |
| 93927 | GIR_EraseRootFromParent_Done, |
| 93928 | // Label 6290: @239622 |
| 93929 | GIM_Reject, |
| 93930 | // Label 6288: @239623 |
| 93931 | GIM_Reject, |
| 93932 | // Label 6178: @239624 |
| 93933 | GIM_Reject, |
| 93934 | // Label 63: @239625 |
| 93935 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 6309*/ GIMT_Encode4(245165), |
| 93936 | /*GILLT_s16*//*Label 6291*/ GIMT_Encode4(239756), |
| 93937 | /*GILLT_s32*//*Label 6292*/ GIMT_Encode4(240420), |
| 93938 | /*GILLT_s64*//*Label 6293*/ GIMT_Encode4(240607), GIMT_Encode4(0), GIMT_Encode4(0), |
| 93939 | /*GILLT_nxv1s16*//*Label 6294*/ GIMT_Encode4(240794), |
| 93940 | /*GILLT_nxv1s32*//*Label 6295*/ GIMT_Encode4(241131), |
| 93941 | /*GILLT_nxv1s64*//*Label 6296*/ GIMT_Encode4(241468), GIMT_Encode4(0), GIMT_Encode4(0), |
| 93942 | /*GILLT_nxv2s16*//*Label 6297*/ GIMT_Encode4(241691), |
| 93943 | /*GILLT_nxv2s32*//*Label 6298*/ GIMT_Encode4(242028), |
| 93944 | /*GILLT_nxv2s64*//*Label 6299*/ GIMT_Encode4(242365), GIMT_Encode4(0), GIMT_Encode4(0), |
| 93945 | /*GILLT_nxv4s16*//*Label 6300*/ GIMT_Encode4(242588), |
| 93946 | /*GILLT_nxv4s32*//*Label 6301*/ GIMT_Encode4(242925), |
| 93947 | /*GILLT_nxv4s64*//*Label 6302*/ GIMT_Encode4(243262), GIMT_Encode4(0), GIMT_Encode4(0), |
| 93948 | /*GILLT_nxv8s16*//*Label 6303*/ GIMT_Encode4(243485), |
| 93949 | /*GILLT_nxv8s32*//*Label 6304*/ GIMT_Encode4(243822), |
| 93950 | /*GILLT_nxv8s64*//*Label 6305*/ GIMT_Encode4(244159), GIMT_Encode4(0), GIMT_Encode4(0), |
| 93951 | /*GILLT_nxv16s16*//*Label 6306*/ GIMT_Encode4(244382), |
| 93952 | /*GILLT_nxv16s32*//*Label 6307*/ GIMT_Encode4(244719), GIMT_Encode4(0), GIMT_Encode4(0), |
| 93953 | /*GILLT_nxv32s16*//*Label 6308*/ GIMT_Encode4(244942), |
| 93954 | // Label 6291: @239756 |
| 93955 | GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(239787), // Rule ID 2258 // |
| 93956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 93957 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 93958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 93959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 93960 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_W:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 93961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_W), |
| 93962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93963 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 93965 | GIR_RootConstrainSelectedInstOperands, |
| 93966 | // GIR_Coverage, 2258, |
| 93967 | GIR_EraseRootFromParent_Done, |
| 93968 | // Label 6310: @239787 |
| 93969 | GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(239818), // Rule ID 2259 // |
| 93970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 93971 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 93972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 93973 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 93974 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_W:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 93975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_W), |
| 93976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93977 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 93979 | GIR_RootConstrainSelectedInstOperands, |
| 93980 | // GIR_Coverage, 2259, |
| 93981 | GIR_EraseRootFromParent_Done, |
| 93982 | // Label 6311: @239818 |
| 93983 | GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(239849), // Rule ID 2284 // |
| 93984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 93985 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 93986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 93987 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 93988 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_W_INX:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 93989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_W_INX), |
| 93990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 93991 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 93992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 93993 | GIR_RootConstrainSelectedInstOperands, |
| 93994 | // GIR_Coverage, 2284, |
| 93995 | GIR_EraseRootFromParent_Done, |
| 93996 | // Label 6312: @239849 |
| 93997 | GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(239880), // Rule ID 2285 // |
| 93998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 93999 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 94001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94002 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_W_INX:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 94003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_W_INX), |
| 94004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94007 | GIR_RootConstrainSelectedInstOperands, |
| 94008 | // GIR_Coverage, 2285, |
| 94009 | GIR_EraseRootFromParent_Done, |
| 94010 | // Label 6313: @239880 |
| 94011 | GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(239911), // Rule ID 2313 // |
| 94012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 94013 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94015 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94016 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_L:{ *:[f16] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 94017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_L), |
| 94018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94019 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94021 | GIR_RootConstrainSelectedInstOperands, |
| 94022 | // GIR_Coverage, 2313, |
| 94023 | GIR_EraseRootFromParent_Done, |
| 94024 | // Label 6314: @239911 |
| 94025 | GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(239942), // Rule ID 2339 // |
| 94026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 94027 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 94029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94030 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_L_INX:{ *:[f16] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 94031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_L_INX), |
| 94032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94033 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94035 | GIR_RootConstrainSelectedInstOperands, |
| 94036 | // GIR_Coverage, 2339, |
| 94037 | GIR_EraseRootFromParent_Done, |
| 94038 | // Label 6315: @239942 |
| 94039 | GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(239995), // Rule ID 2390 // |
| 94040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0), |
| 94041 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94043 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94044 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S:{ *:[f16] } (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 94045 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94046 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W), |
| 94047 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94048 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94049 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 94052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94053 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94055 | GIR_RootConstrainSelectedInstOperands, |
| 94056 | // GIR_Coverage, 2390, |
| 94057 | GIR_EraseRootFromParent_Done, |
| 94058 | // Label 6316: @239995 |
| 94059 | GIM_Try, /*On fail goto*//*Label 6317*/ GIMT_Encode4(240048), // Rule ID 2391 // |
| 94060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1), |
| 94061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94064 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S:{ *:[f16] } (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }), 7:{ *:[i32] }) |
| 94065 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94066 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W), |
| 94067 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94068 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94069 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94070 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 94072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94073 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94075 | GIR_RootConstrainSelectedInstOperands, |
| 94076 | // GIR_Coverage, 2391, |
| 94077 | GIR_EraseRootFromParent_Done, |
| 94078 | // Label 6317: @240048 |
| 94079 | GIM_Try, /*On fail goto*//*Label 6318*/ GIMT_Encode4(240101), // Rule ID 2414 // |
| 94080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0), |
| 94081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 94083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94084 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } (FCVT_S_W_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 94085 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94086 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W_INX), |
| 94087 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94088 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94089 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94090 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 94092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94095 | GIR_RootConstrainSelectedInstOperands, |
| 94096 | // GIR_Coverage, 2414, |
| 94097 | GIR_EraseRootFromParent_Done, |
| 94098 | // Label 6318: @240101 |
| 94099 | GIM_Try, /*On fail goto*//*Label 6319*/ GIMT_Encode4(240154), // Rule ID 2415 // |
| 94100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1), |
| 94101 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 94103 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94104 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } (FCVT_S_W_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }), 7:{ *:[i32] }) |
| 94105 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94106 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W_INX), |
| 94107 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94108 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94109 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 94112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94113 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94115 | GIR_RootConstrainSelectedInstOperands, |
| 94116 | // GIR_Coverage, 2415, |
| 94117 | GIR_EraseRootFromParent_Done, |
| 94118 | // Label 6319: @240154 |
| 94119 | GIM_Try, /*On fail goto*//*Label 6320*/ GIMT_Encode4(240207), // Rule ID 2433 // |
| 94120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 94121 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94124 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_S:{ *:[f16] } (FCVT_S_L:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 94125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_L), |
| 94127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94128 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94129 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 94132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94133 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94135 | GIR_RootConstrainSelectedInstOperands, |
| 94136 | // GIR_Coverage, 2433, |
| 94137 | GIR_EraseRootFromParent_Done, |
| 94138 | // Label 6320: @240207 |
| 94139 | GIM_Try, /*On fail goto*//*Label 6321*/ GIMT_Encode4(240260), // Rule ID 2449 // |
| 94140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 94141 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 94143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94144 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } (FCVT_S_L_INX:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 94145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94146 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_L_INX), |
| 94147 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94148 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94149 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 94152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94153 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94155 | GIR_RootConstrainSelectedInstOperands, |
| 94156 | // GIR_Coverage, 2449, |
| 94157 | GIR_EraseRootFromParent_Done, |
| 94158 | // Label 6321: @240260 |
| 94159 | GIM_Try, /*On fail goto*//*Label 6322*/ GIMT_Encode4(240313), // Rule ID 2476 // |
| 94160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode0), |
| 94161 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94164 | // (sint_to_fp:{ *:[bf16] } GPR:{ *:[i32] }:$rs1) => (FCVT_BF16_S:{ *:[bf16] } (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 94165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W), |
| 94167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94168 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94169 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_BF16_S), |
| 94172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94175 | GIR_RootConstrainSelectedInstOperands, |
| 94176 | // GIR_Coverage, 2476, |
| 94177 | GIR_EraseRootFromParent_Done, |
| 94178 | // Label 6322: @240313 |
| 94179 | GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(240366), // Rule ID 2477 // |
| 94180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode1), |
| 94181 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94183 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94184 | // (sint_to_fp:{ *:[bf16] } GPR:{ *:[i32] }:$rs1) => (FCVT_BF16_S:{ *:[bf16] } (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }), 7:{ *:[i32] }) |
| 94185 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94186 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W), |
| 94187 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94188 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94189 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94190 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_BF16_S), |
| 94192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94193 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94195 | GIR_RootConstrainSelectedInstOperands, |
| 94196 | // GIR_Coverage, 2477, |
| 94197 | GIR_EraseRootFromParent_Done, |
| 94198 | // Label 6323: @240366 |
| 94199 | GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(240419), // Rule ID 2487 // |
| 94200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_IsRV64_HwMode0), |
| 94201 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 94203 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94204 | // (sint_to_fp:{ *:[bf16] } GPR:{ *:[i64] }:$rs1) => (FCVT_BF16_S:{ *:[bf16] } (FCVT_S_L:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 94205 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 94206 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_L), |
| 94207 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94208 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 94209 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 94210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_BF16_S), |
| 94212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94213 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94215 | GIR_RootConstrainSelectedInstOperands, |
| 94216 | // GIR_Coverage, 2487, |
| 94217 | GIR_EraseRootFromParent_Done, |
| 94218 | // Label 6324: @240419 |
| 94219 | GIM_Reject, |
| 94220 | // Label 6292: @240420 |
| 94221 | GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(240451), // Rule ID 1541 // |
| 94222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 94223 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 94225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94226 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 94227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W), |
| 94228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94229 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94231 | GIR_RootConstrainSelectedInstOperands, |
| 94232 | // GIR_Coverage, 1541, |
| 94233 | GIR_EraseRootFromParent_Done, |
| 94234 | // Label 6325: @240451 |
| 94235 | GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(240482), // Rule ID 1542 // |
| 94236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 94237 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 94239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94240 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 94241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W), |
| 94242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94243 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94245 | GIR_RootConstrainSelectedInstOperands, |
| 94246 | // GIR_Coverage, 1542, |
| 94247 | GIR_EraseRootFromParent_Done, |
| 94248 | // Label 6326: @240482 |
| 94249 | GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(240513), // Rule ID 1567 // |
| 94250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 94251 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 94253 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94254 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_W_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 94255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W_INX), |
| 94256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94257 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94259 | GIR_RootConstrainSelectedInstOperands, |
| 94260 | // GIR_Coverage, 1567, |
| 94261 | GIR_EraseRootFromParent_Done, |
| 94262 | // Label 6327: @240513 |
| 94263 | GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(240544), // Rule ID 1568 // |
| 94264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 94265 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 94267 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94268 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_W_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 94269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_W_INX), |
| 94270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94273 | GIR_RootConstrainSelectedInstOperands, |
| 94274 | // GIR_Coverage, 1568, |
| 94275 | GIR_EraseRootFromParent_Done, |
| 94276 | // Label 6328: @240544 |
| 94277 | GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(240575), // Rule ID 1598 // |
| 94278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 94279 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 94281 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94282 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) => (FCVT_S_L:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 94283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_L), |
| 94284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94287 | GIR_RootConstrainSelectedInstOperands, |
| 94288 | // GIR_Coverage, 1598, |
| 94289 | GIR_EraseRootFromParent_Done, |
| 94290 | // Label 6329: @240575 |
| 94291 | GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(240606), // Rule ID 1626 // |
| 94292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 94293 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 94295 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94296 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) => (FCVT_S_L_INX:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 94297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_L_INX), |
| 94298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94299 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94301 | GIR_RootConstrainSelectedInstOperands, |
| 94302 | // GIR_Coverage, 1626, |
| 94303 | GIR_EraseRootFromParent_Done, |
| 94304 | // Label 6330: @240606 |
| 94305 | GIM_Reject, |
| 94306 | // Label 6293: @240607 |
| 94307 | GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(240638), // Rule ID 1922 // |
| 94308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 94309 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 94311 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94312 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i64] }) |
| 94313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_W), |
| 94314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94315 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94317 | GIR_RootConstrainSelectedInstOperands, |
| 94318 | // GIR_Coverage, 1922, |
| 94319 | GIR_EraseRootFromParent_Done, |
| 94320 | // Label 6331: @240638 |
| 94321 | GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(240669), // Rule ID 1923 // |
| 94322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 94323 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 94325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94326 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) |
| 94327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_W), |
| 94328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94329 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94331 | GIR_RootConstrainSelectedInstOperands, |
| 94332 | // GIR_Coverage, 1923, |
| 94333 | GIR_EraseRootFromParent_Done, |
| 94334 | // Label 6332: @240669 |
| 94335 | GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(240700), // Rule ID 1948 // |
| 94336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 94337 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 94339 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94340 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W_IN32X:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i64] }) |
| 94341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_W_IN32X), |
| 94342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94343 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94345 | GIR_RootConstrainSelectedInstOperands, |
| 94346 | // GIR_Coverage, 1948, |
| 94347 | GIR_EraseRootFromParent_Done, |
| 94348 | // Label 6333: @240700 |
| 94349 | GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(240731), // Rule ID 1949 // |
| 94350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 94351 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 94353 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94354 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W_IN32X:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) |
| 94355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_W_IN32X), |
| 94356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94357 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94359 | GIR_RootConstrainSelectedInstOperands, |
| 94360 | // GIR_Coverage, 1949, |
| 94361 | GIR_EraseRootFromParent_Done, |
| 94362 | // Label 6334: @240731 |
| 94363 | GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(240762), // Rule ID 1979 // |
| 94364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 94365 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 94367 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94368 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 94369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_L), |
| 94370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94371 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94373 | GIR_RootConstrainSelectedInstOperands, |
| 94374 | // GIR_Coverage, 1979, |
| 94375 | GIR_EraseRootFromParent_Done, |
| 94376 | // Label 6335: @240762 |
| 94377 | GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(240793), // Rule ID 2007 // |
| 94378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 94379 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 94380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 94382 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_L_INX:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 94383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_L_INX), |
| 94384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94385 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94387 | GIR_RootConstrainSelectedInstOperands, |
| 94388 | // GIR_Coverage, 2007, |
| 94389 | GIR_EraseRootFromParent_Done, |
| 94390 | // Label 6336: @240793 |
| 94391 | GIM_Reject, |
| 94392 | // Label 6294: @240794 |
| 94393 | GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(240851), // Rule ID 46636 // |
| 94394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 94395 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 94396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94397 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94398 | // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFCVT_F_X_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 94399 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 94400 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94401 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_MF4_E16), |
| 94404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94405 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94406 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94411 | GIR_RootConstrainSelectedInstOperands, |
| 94412 | // GIR_Coverage, 46636, |
| 94413 | GIR_EraseRootFromParent_Done, |
| 94414 | // Label 6337: @240851 |
| 94415 | GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(240908), // Rule ID 46637 // |
| 94416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 94417 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 94418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94419 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94420 | // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFCVT_F_X_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 94421 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 94422 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94423 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94424 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_MF4_E16), |
| 94426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94427 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94428 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94433 | GIR_RootConstrainSelectedInstOperands, |
| 94434 | // GIR_Coverage, 46637, |
| 94435 | GIR_EraseRootFromParent_Done, |
| 94436 | // Label 6338: @240908 |
| 94437 | GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(240962), // Rule ID 46644 // |
| 94438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 94439 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 94440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94441 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94442 | // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVFWCVT_F_X_V_MF8_E8:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 94443 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 94444 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94445 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94446 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF8_E8), |
| 94448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94449 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94450 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94454 | GIR_RootConstrainSelectedInstOperands, |
| 94455 | // GIR_Coverage, 46644, |
| 94456 | GIR_EraseRootFromParent_Done, |
| 94457 | // Label 6339: @240962 |
| 94458 | GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(241016), // Rule ID 46645 // |
| 94459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 94460 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 94461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94463 | // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVFWCVT_F_X_V_MF8_E8:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 94464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 94465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF8_E8), |
| 94469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94470 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94471 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94475 | GIR_RootConstrainSelectedInstOperands, |
| 94476 | // GIR_Coverage, 46645, |
| 94477 | GIR_EraseRootFromParent_Done, |
| 94478 | // Label 6340: @241016 |
| 94479 | GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(241073), // Rule ID 46652 // |
| 94480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 94481 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 94482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94483 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94484 | // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFNCVT_F_X_W_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 94485 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 94486 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94487 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94488 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_MF4_E16), |
| 94490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94491 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94492 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94497 | GIR_RootConstrainSelectedInstOperands, |
| 94498 | // GIR_Coverage, 46652, |
| 94499 | GIR_EraseRootFromParent_Done, |
| 94500 | // Label 6341: @241073 |
| 94501 | GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(241130), // Rule ID 46653 // |
| 94502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 94503 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 94504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94506 | // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFNCVT_F_X_W_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 94507 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 94508 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94509 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94510 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_MF4_E16), |
| 94512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94513 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94514 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94519 | GIR_RootConstrainSelectedInstOperands, |
| 94520 | // GIR_Coverage, 46653, |
| 94521 | GIR_EraseRootFromParent_Done, |
| 94522 | // Label 6342: @241130 |
| 94523 | GIM_Reject, |
| 94524 | // Label 6295: @241131 |
| 94525 | GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(241188), // Rule ID 58916 // |
| 94526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 94527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 94528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94529 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94530 | // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFCVT_F_X_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 94531 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 94532 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94533 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94534 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_MF2_E32), |
| 94536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94537 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94538 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94543 | GIR_RootConstrainSelectedInstOperands, |
| 94544 | // GIR_Coverage, 58916, |
| 94545 | GIR_EraseRootFromParent_Done, |
| 94546 | // Label 6343: @241188 |
| 94547 | GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(241245), // Rule ID 58917 // |
| 94548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 94549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 94550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94551 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94552 | // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFCVT_F_X_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 94553 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 94554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94555 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_MF2_E32), |
| 94558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94559 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94565 | GIR_RootConstrainSelectedInstOperands, |
| 94566 | // GIR_Coverage, 58917, |
| 94567 | GIR_EraseRootFromParent_Done, |
| 94568 | // Label 6344: @241245 |
| 94569 | GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(241299), // Rule ID 59116 // |
| 94570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 94571 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 94572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94574 | // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFWCVT_F_X_V_MF4_E16:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 94575 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 94576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94577 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF4_E16), |
| 94580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94581 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94582 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94586 | GIR_RootConstrainSelectedInstOperands, |
| 94587 | // GIR_Coverage, 59116, |
| 94588 | GIR_EraseRootFromParent_Done, |
| 94589 | // Label 6345: @241299 |
| 94590 | GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(241353), // Rule ID 59117 // |
| 94591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 94592 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 94593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94594 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94595 | // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFWCVT_F_X_V_MF4_E16:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 94596 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 94597 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94598 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF4_E16), |
| 94601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94602 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94603 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94607 | GIR_RootConstrainSelectedInstOperands, |
| 94608 | // GIR_Coverage, 59117, |
| 94609 | GIR_EraseRootFromParent_Done, |
| 94610 | // Label 6346: @241353 |
| 94611 | GIM_Try, /*On fail goto*//*Label 6347*/ GIMT_Encode4(241410), // Rule ID 59344 // |
| 94612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 94613 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 94614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94615 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94616 | // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFNCVT_F_X_W_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 94617 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 94618 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94619 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_MF2_E32), |
| 94622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94623 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94624 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94629 | GIR_RootConstrainSelectedInstOperands, |
| 94630 | // GIR_Coverage, 59344, |
| 94631 | GIR_EraseRootFromParent_Done, |
| 94632 | // Label 6347: @241410 |
| 94633 | GIM_Try, /*On fail goto*//*Label 6348*/ GIMT_Encode4(241467), // Rule ID 59345 // |
| 94634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 94635 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 94636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94637 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94638 | // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFNCVT_F_X_W_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 94639 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 94640 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94641 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_MF2_E32), |
| 94644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94646 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94651 | GIR_RootConstrainSelectedInstOperands, |
| 94652 | // GIR_Coverage, 59345, |
| 94653 | GIR_EraseRootFromParent_Done, |
| 94654 | // Label 6348: @241467 |
| 94655 | GIM_Reject, |
| 94656 | // Label 6296: @241468 |
| 94657 | GIM_Try, /*On fail goto*//*Label 6349*/ GIMT_Encode4(241525), // Rule ID 58928 // |
| 94658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 94659 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 94660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94661 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94662 | // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFCVT_F_X_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 94663 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 94664 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94665 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94666 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M1_E64), |
| 94668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94669 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94670 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 94674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94675 | GIR_RootConstrainSelectedInstOperands, |
| 94676 | // GIR_Coverage, 58928, |
| 94677 | GIR_EraseRootFromParent_Done, |
| 94678 | // Label 6349: @241525 |
| 94679 | GIM_Try, /*On fail goto*//*Label 6350*/ GIMT_Encode4(241582), // Rule ID 58929 // |
| 94680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 94681 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 94682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94684 | // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFCVT_F_X_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 94685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 94686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M1_E64), |
| 94690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94691 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94692 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 94696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94697 | GIR_RootConstrainSelectedInstOperands, |
| 94698 | // GIR_Coverage, 58929, |
| 94699 | GIR_EraseRootFromParent_Done, |
| 94700 | // Label 6350: @241582 |
| 94701 | GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(241636), // Rule ID 59136 // |
| 94702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 94703 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 94704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94706 | // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFWCVT_F_X_V_MF2_E32:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 94707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 94708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF2_E32), |
| 94712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94713 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94714 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94718 | GIR_RootConstrainSelectedInstOperands, |
| 94719 | // GIR_Coverage, 59136, |
| 94720 | GIR_EraseRootFromParent_Done, |
| 94721 | // Label 6351: @241636 |
| 94722 | GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(241690), // Rule ID 59137 // |
| 94723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 94724 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 94725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94727 | // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFWCVT_F_X_V_MF2_E32:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 94728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 94729 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94730 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF2_E32), |
| 94733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94734 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94735 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94739 | GIR_RootConstrainSelectedInstOperands, |
| 94740 | // GIR_Coverage, 59137, |
| 94741 | GIR_EraseRootFromParent_Done, |
| 94742 | // Label 6352: @241690 |
| 94743 | GIM_Reject, |
| 94744 | // Label 6297: @241691 |
| 94745 | GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(241748), // Rule ID 58912 // |
| 94746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 94747 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 94748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94750 | // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFCVT_F_X_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 94751 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 94752 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94753 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94754 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_MF2_E16), |
| 94756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94757 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94758 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94763 | GIR_RootConstrainSelectedInstOperands, |
| 94764 | // GIR_Coverage, 58912, |
| 94765 | GIR_EraseRootFromParent_Done, |
| 94766 | // Label 6353: @241748 |
| 94767 | GIM_Try, /*On fail goto*//*Label 6354*/ GIMT_Encode4(241805), // Rule ID 58913 // |
| 94768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 94769 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 94770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94772 | // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFCVT_F_X_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 94773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 94774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_MF2_E16), |
| 94778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94785 | GIR_RootConstrainSelectedInstOperands, |
| 94786 | // GIR_Coverage, 58913, |
| 94787 | GIR_EraseRootFromParent_Done, |
| 94788 | // Label 6354: @241805 |
| 94789 | GIM_Try, /*On fail goto*//*Label 6355*/ GIMT_Encode4(241859), // Rule ID 59096 // |
| 94790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 94791 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 94792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94794 | // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVFWCVT_F_X_V_MF4_E8:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 94795 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 94796 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94797 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF4_E8), |
| 94800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94801 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94802 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94806 | GIR_RootConstrainSelectedInstOperands, |
| 94807 | // GIR_Coverage, 59096, |
| 94808 | GIR_EraseRootFromParent_Done, |
| 94809 | // Label 6355: @241859 |
| 94810 | GIM_Try, /*On fail goto*//*Label 6356*/ GIMT_Encode4(241913), // Rule ID 59097 // |
| 94811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 94812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 94813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94814 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94815 | // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVFWCVT_F_X_V_MF4_E8:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 94816 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 94817 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94818 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94819 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF4_E8), |
| 94821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94822 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94823 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94827 | GIR_RootConstrainSelectedInstOperands, |
| 94828 | // GIR_Coverage, 59097, |
| 94829 | GIR_EraseRootFromParent_Done, |
| 94830 | // Label 6356: @241913 |
| 94831 | GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(241970), // Rule ID 59328 // |
| 94832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 94833 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 94834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94835 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94836 | // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFNCVT_F_X_W_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 94837 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 94838 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94839 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_MF2_E16), |
| 94842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94843 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94844 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94849 | GIR_RootConstrainSelectedInstOperands, |
| 94850 | // GIR_Coverage, 59328, |
| 94851 | GIR_EraseRootFromParent_Done, |
| 94852 | // Label 6357: @241970 |
| 94853 | GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(242027), // Rule ID 59329 // |
| 94854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 94855 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 94856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94858 | // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFNCVT_F_X_W_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 94859 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 94860 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94861 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_MF2_E16), |
| 94864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94865 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94866 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94871 | GIR_RootConstrainSelectedInstOperands, |
| 94872 | // GIR_Coverage, 59329, |
| 94873 | GIR_EraseRootFromParent_Done, |
| 94874 | // Label 6358: @242027 |
| 94875 | GIM_Reject, |
| 94876 | // Label 6298: @242028 |
| 94877 | GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(242085), // Rule ID 58924 // |
| 94878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 94879 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 94880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94882 | // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFCVT_F_X_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 94883 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 94884 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94885 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94886 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M1_E32), |
| 94888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94890 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94895 | GIR_RootConstrainSelectedInstOperands, |
| 94896 | // GIR_Coverage, 58924, |
| 94897 | GIR_EraseRootFromParent_Done, |
| 94898 | // Label 6359: @242085 |
| 94899 | GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(242142), // Rule ID 58925 // |
| 94900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 94901 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 94902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94903 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94904 | // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFCVT_F_X_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 94905 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 94906 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94907 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M1_E32), |
| 94910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94912 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94917 | GIR_RootConstrainSelectedInstOperands, |
| 94918 | // GIR_Coverage, 58925, |
| 94919 | GIR_EraseRootFromParent_Done, |
| 94920 | // Label 6360: @242142 |
| 94921 | GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(242196), // Rule ID 59120 // |
| 94922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 94923 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 94924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94925 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94926 | // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFWCVT_F_X_V_MF2_E16:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 94927 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 94928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF2_E16), |
| 94932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94933 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94934 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94938 | GIR_RootConstrainSelectedInstOperands, |
| 94939 | // GIR_Coverage, 59120, |
| 94940 | GIR_EraseRootFromParent_Done, |
| 94941 | // Label 6361: @242196 |
| 94942 | GIM_Try, /*On fail goto*//*Label 6362*/ GIMT_Encode4(242250), // Rule ID 59121 // |
| 94943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 94944 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 94945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94947 | // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFWCVT_F_X_V_MF2_E16:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 94948 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 94949 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94950 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF2_E16), |
| 94953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94954 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94955 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 94958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94959 | GIR_RootConstrainSelectedInstOperands, |
| 94960 | // GIR_Coverage, 59121, |
| 94961 | GIR_EraseRootFromParent_Done, |
| 94962 | // Label 6362: @242250 |
| 94963 | GIM_Try, /*On fail goto*//*Label 6363*/ GIMT_Encode4(242307), // Rule ID 59348 // |
| 94964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 94965 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 94966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94967 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 94968 | // (sint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFNCVT_F_X_W_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 94969 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 94970 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94971 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94972 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M1_E32), |
| 94974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94975 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94976 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 94978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 94979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 94980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 94981 | GIR_RootConstrainSelectedInstOperands, |
| 94982 | // GIR_Coverage, 59348, |
| 94983 | GIR_EraseRootFromParent_Done, |
| 94984 | // Label 6363: @242307 |
| 94985 | GIM_Try, /*On fail goto*//*Label 6364*/ GIMT_Encode4(242364), // Rule ID 59349 // |
| 94986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 94987 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 94988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 94989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 94990 | // (sint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFNCVT_F_X_W_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 94991 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 94992 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 94993 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 94994 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 94995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M1_E32), |
| 94996 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 94997 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 94998 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 94999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95003 | GIR_RootConstrainSelectedInstOperands, |
| 95004 | // GIR_Coverage, 59349, |
| 95005 | GIR_EraseRootFromParent_Done, |
| 95006 | // Label 6364: @242364 |
| 95007 | GIM_Reject, |
| 95008 | // Label 6299: @242365 |
| 95009 | GIM_Try, /*On fail goto*//*Label 6365*/ GIMT_Encode4(242422), // Rule ID 58956 // |
| 95010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 95011 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 95012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95013 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95014 | // (sint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFCVT_F_X_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 95015 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 95016 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95017 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M2_E64), |
| 95020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95021 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95022 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 95026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95027 | GIR_RootConstrainSelectedInstOperands, |
| 95028 | // GIR_Coverage, 58956, |
| 95029 | GIR_EraseRootFromParent_Done, |
| 95030 | // Label 6365: @242422 |
| 95031 | GIM_Try, /*On fail goto*//*Label 6366*/ GIMT_Encode4(242479), // Rule ID 58957 // |
| 95032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 95033 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 95034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95036 | // (sint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFCVT_F_X_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 95037 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 95038 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95039 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M2_E64), |
| 95042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95043 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95044 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 95048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95049 | GIR_RootConstrainSelectedInstOperands, |
| 95050 | // GIR_Coverage, 58957, |
| 95051 | GIR_EraseRootFromParent_Done, |
| 95052 | // Label 6366: @242479 |
| 95053 | GIM_Try, /*On fail goto*//*Label 6367*/ GIMT_Encode4(242533), // Rule ID 59140 // |
| 95054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 95055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 95056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95057 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95058 | // (sint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFWCVT_F_X_V_M1_E32:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95059 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 95060 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95061 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M1_E32), |
| 95064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95065 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95066 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95070 | GIR_RootConstrainSelectedInstOperands, |
| 95071 | // GIR_Coverage, 59140, |
| 95072 | GIR_EraseRootFromParent_Done, |
| 95073 | // Label 6367: @242533 |
| 95074 | GIM_Try, /*On fail goto*//*Label 6368*/ GIMT_Encode4(242587), // Rule ID 59141 // |
| 95075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 95076 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 95077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95078 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95079 | // (sint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFWCVT_F_X_V_M1_E32:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95080 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 95081 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95082 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M1_E32), |
| 95085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95086 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95087 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95091 | GIR_RootConstrainSelectedInstOperands, |
| 95092 | // GIR_Coverage, 59141, |
| 95093 | GIR_EraseRootFromParent_Done, |
| 95094 | // Label 6368: @242587 |
| 95095 | GIM_Reject, |
| 95096 | // Label 6300: @242588 |
| 95097 | GIM_Try, /*On fail goto*//*Label 6369*/ GIMT_Encode4(242645), // Rule ID 58920 // |
| 95098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95099 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 95100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95101 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95102 | // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFCVT_F_X_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95103 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 95104 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95105 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M1_E16), |
| 95108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95109 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95110 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95115 | GIR_RootConstrainSelectedInstOperands, |
| 95116 | // GIR_Coverage, 58920, |
| 95117 | GIR_EraseRootFromParent_Done, |
| 95118 | // Label 6369: @242645 |
| 95119 | GIM_Try, /*On fail goto*//*Label 6370*/ GIMT_Encode4(242702), // Rule ID 58921 // |
| 95120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95121 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 95122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95124 | // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFCVT_F_X_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 95126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M1_E16), |
| 95130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95137 | GIR_RootConstrainSelectedInstOperands, |
| 95138 | // GIR_Coverage, 58921, |
| 95139 | GIR_EraseRootFromParent_Done, |
| 95140 | // Label 6370: @242702 |
| 95141 | GIM_Try, /*On fail goto*//*Label 6371*/ GIMT_Encode4(242756), // Rule ID 59100 // |
| 95142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95143 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 95144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95145 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95146 | // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVFWCVT_F_X_V_MF2_E8:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 95147 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 95148 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95149 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF2_E8), |
| 95152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95153 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95154 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95158 | GIR_RootConstrainSelectedInstOperands, |
| 95159 | // GIR_Coverage, 59100, |
| 95160 | GIR_EraseRootFromParent_Done, |
| 95161 | // Label 6371: @242756 |
| 95162 | GIM_Try, /*On fail goto*//*Label 6372*/ GIMT_Encode4(242810), // Rule ID 59101 // |
| 95163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95164 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 95165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95167 | // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVFWCVT_F_X_V_MF2_E8:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 95168 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 95169 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95170 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95171 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_MF2_E8), |
| 95173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95174 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95175 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95179 | GIR_RootConstrainSelectedInstOperands, |
| 95180 | // GIR_Coverage, 59101, |
| 95181 | GIR_EraseRootFromParent_Done, |
| 95182 | // Label 6372: @242810 |
| 95183 | GIM_Try, /*On fail goto*//*Label 6373*/ GIMT_Encode4(242867), // Rule ID 59332 // |
| 95184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95185 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 95186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95187 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95188 | // (sint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFNCVT_F_X_W_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95189 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 95190 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95191 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95192 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M1_E16), |
| 95194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95195 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95196 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95201 | GIR_RootConstrainSelectedInstOperands, |
| 95202 | // GIR_Coverage, 59332, |
| 95203 | GIR_EraseRootFromParent_Done, |
| 95204 | // Label 6373: @242867 |
| 95205 | GIM_Try, /*On fail goto*//*Label 6374*/ GIMT_Encode4(242924), // Rule ID 59333 // |
| 95206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95207 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 95208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95210 | // (sint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFNCVT_F_X_W_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95211 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 95212 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95213 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95214 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M1_E16), |
| 95216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95217 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95218 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95223 | GIR_RootConstrainSelectedInstOperands, |
| 95224 | // GIR_Coverage, 59333, |
| 95225 | GIR_EraseRootFromParent_Done, |
| 95226 | // Label 6374: @242924 |
| 95227 | GIM_Reject, |
| 95228 | // Label 6301: @242925 |
| 95229 | GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(242982), // Rule ID 58944 // |
| 95230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 95231 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 95232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95233 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95234 | // (sint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFCVT_F_X_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 95236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M2_E32), |
| 95240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95242 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95247 | GIR_RootConstrainSelectedInstOperands, |
| 95248 | // GIR_Coverage, 58944, |
| 95249 | GIR_EraseRootFromParent_Done, |
| 95250 | // Label 6375: @242982 |
| 95251 | GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(243039), // Rule ID 58945 // |
| 95252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 95253 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 95254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95255 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95256 | // (sint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFCVT_F_X_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95257 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 95258 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95259 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M2_E32), |
| 95262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95263 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95264 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95269 | GIR_RootConstrainSelectedInstOperands, |
| 95270 | // GIR_Coverage, 58945, |
| 95271 | GIR_EraseRootFromParent_Done, |
| 95272 | // Label 6376: @243039 |
| 95273 | GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(243093), // Rule ID 59124 // |
| 95274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 95275 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 95276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95277 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95278 | // (sint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFWCVT_F_X_V_M1_E16:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95279 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 95280 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95281 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95282 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M1_E16), |
| 95284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95285 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95286 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95290 | GIR_RootConstrainSelectedInstOperands, |
| 95291 | // GIR_Coverage, 59124, |
| 95292 | GIR_EraseRootFromParent_Done, |
| 95293 | // Label 6377: @243093 |
| 95294 | GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(243147), // Rule ID 59125 // |
| 95295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 95296 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 95297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95298 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95299 | // (sint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFWCVT_F_X_V_M1_E16:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95300 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 95301 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95302 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M1_E16), |
| 95305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95306 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95307 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95311 | GIR_RootConstrainSelectedInstOperands, |
| 95312 | // GIR_Coverage, 59125, |
| 95313 | GIR_EraseRootFromParent_Done, |
| 95314 | // Label 6378: @243147 |
| 95315 | GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(243204), // Rule ID 59352 // |
| 95316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 95317 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 95318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95319 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95320 | // (sint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFNCVT_F_X_W_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95321 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 95322 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95323 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M2_E32), |
| 95326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95327 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95328 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95333 | GIR_RootConstrainSelectedInstOperands, |
| 95334 | // GIR_Coverage, 59352, |
| 95335 | GIR_EraseRootFromParent_Done, |
| 95336 | // Label 6379: @243204 |
| 95337 | GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(243261), // Rule ID 59353 // |
| 95338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 95339 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 95340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95341 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95342 | // (sint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFNCVT_F_X_W_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95343 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 95344 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95345 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95346 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M2_E32), |
| 95348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95350 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95355 | GIR_RootConstrainSelectedInstOperands, |
| 95356 | // GIR_Coverage, 59353, |
| 95357 | GIR_EraseRootFromParent_Done, |
| 95358 | // Label 6380: @243261 |
| 95359 | GIM_Reject, |
| 95360 | // Label 6302: @243262 |
| 95361 | GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(243319), // Rule ID 58960 // |
| 95362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 95363 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 95364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95365 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95366 | // (sint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFCVT_F_X_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 95367 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 95368 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95369 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M4_E64), |
| 95372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95373 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95374 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 95378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95379 | GIR_RootConstrainSelectedInstOperands, |
| 95380 | // GIR_Coverage, 58960, |
| 95381 | GIR_EraseRootFromParent_Done, |
| 95382 | // Label 6381: @243319 |
| 95383 | GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(243376), // Rule ID 58961 // |
| 95384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 95385 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 95386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95387 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95388 | // (sint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFCVT_F_X_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 95389 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 95390 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95391 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95392 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M4_E64), |
| 95394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95395 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95396 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 95400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95401 | GIR_RootConstrainSelectedInstOperands, |
| 95402 | // GIR_Coverage, 58961, |
| 95403 | GIR_EraseRootFromParent_Done, |
| 95404 | // Label 6382: @243376 |
| 95405 | GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(243430), // Rule ID 59144 // |
| 95406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 95407 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 95408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95409 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95410 | // (sint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFWCVT_F_X_V_M2_E32:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 95412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95413 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M2_E32), |
| 95416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95417 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95418 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95422 | GIR_RootConstrainSelectedInstOperands, |
| 95423 | // GIR_Coverage, 59144, |
| 95424 | GIR_EraseRootFromParent_Done, |
| 95425 | // Label 6383: @243430 |
| 95426 | GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(243484), // Rule ID 59145 // |
| 95427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 95428 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 95429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95430 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95431 | // (sint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFWCVT_F_X_V_M2_E32:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 95433 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95434 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M2_E32), |
| 95437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95438 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95439 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95443 | GIR_RootConstrainSelectedInstOperands, |
| 95444 | // GIR_Coverage, 59145, |
| 95445 | GIR_EraseRootFromParent_Done, |
| 95446 | // Label 6384: @243484 |
| 95447 | GIM_Reject, |
| 95448 | // Label 6303: @243485 |
| 95449 | GIM_Try, /*On fail goto*//*Label 6385*/ GIMT_Encode4(243542), // Rule ID 58932 // |
| 95450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95451 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 95452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95453 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95454 | // (sint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFCVT_F_X_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95455 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 95456 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95457 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M2_E16), |
| 95460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95462 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95467 | GIR_RootConstrainSelectedInstOperands, |
| 95468 | // GIR_Coverage, 58932, |
| 95469 | GIR_EraseRootFromParent_Done, |
| 95470 | // Label 6385: @243542 |
| 95471 | GIM_Try, /*On fail goto*//*Label 6386*/ GIMT_Encode4(243599), // Rule ID 58933 // |
| 95472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95473 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 95474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95475 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95476 | // (sint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFCVT_F_X_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95477 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 95478 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95479 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M2_E16), |
| 95482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95483 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95484 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95489 | GIR_RootConstrainSelectedInstOperands, |
| 95490 | // GIR_Coverage, 58933, |
| 95491 | GIR_EraseRootFromParent_Done, |
| 95492 | // Label 6386: @243599 |
| 95493 | GIM_Try, /*On fail goto*//*Label 6387*/ GIMT_Encode4(243653), // Rule ID 59104 // |
| 95494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95495 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 95496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95497 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95498 | // (sint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVFWCVT_F_X_V_M1_E8:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 95499 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 95500 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95501 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M1_E8), |
| 95504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95505 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95506 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95510 | GIR_RootConstrainSelectedInstOperands, |
| 95511 | // GIR_Coverage, 59104, |
| 95512 | GIR_EraseRootFromParent_Done, |
| 95513 | // Label 6387: @243653 |
| 95514 | GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(243707), // Rule ID 59105 // |
| 95515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95516 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 95517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95518 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 95519 | // (sint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVFWCVT_F_X_V_M1_E8:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 95520 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 95521 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95522 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95523 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M1_E8), |
| 95525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95526 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95527 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95531 | GIR_RootConstrainSelectedInstOperands, |
| 95532 | // GIR_Coverage, 59105, |
| 95533 | GIR_EraseRootFromParent_Done, |
| 95534 | // Label 6388: @243707 |
| 95535 | GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(243764), // Rule ID 59336 // |
| 95536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95537 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 95538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95540 | // (sint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFNCVT_F_X_W_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 95542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M2_E16), |
| 95546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95548 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95553 | GIR_RootConstrainSelectedInstOperands, |
| 95554 | // GIR_Coverage, 59336, |
| 95555 | GIR_EraseRootFromParent_Done, |
| 95556 | // Label 6389: @243764 |
| 95557 | GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(243821), // Rule ID 59337 // |
| 95558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95559 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 95560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95561 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95562 | // (sint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFNCVT_F_X_W_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95563 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 95564 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95565 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M2_E16), |
| 95568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95569 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95570 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95575 | GIR_RootConstrainSelectedInstOperands, |
| 95576 | // GIR_Coverage, 59337, |
| 95577 | GIR_EraseRootFromParent_Done, |
| 95578 | // Label 6390: @243821 |
| 95579 | GIM_Reject, |
| 95580 | // Label 6304: @243822 |
| 95581 | GIM_Try, /*On fail goto*//*Label 6391*/ GIMT_Encode4(243879), // Rule ID 58948 // |
| 95582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 95583 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 95584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95586 | // (sint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFCVT_F_X_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95587 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 95588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95589 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M4_E32), |
| 95592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95593 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95594 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95599 | GIR_RootConstrainSelectedInstOperands, |
| 95600 | // GIR_Coverage, 58948, |
| 95601 | GIR_EraseRootFromParent_Done, |
| 95602 | // Label 6391: @243879 |
| 95603 | GIM_Try, /*On fail goto*//*Label 6392*/ GIMT_Encode4(243936), // Rule ID 58949 // |
| 95604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 95605 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 95606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95607 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95608 | // (sint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFCVT_F_X_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95609 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 95610 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95611 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95612 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M4_E32), |
| 95614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95616 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95621 | GIR_RootConstrainSelectedInstOperands, |
| 95622 | // GIR_Coverage, 58949, |
| 95623 | GIR_EraseRootFromParent_Done, |
| 95624 | // Label 6392: @243936 |
| 95625 | GIM_Try, /*On fail goto*//*Label 6393*/ GIMT_Encode4(243990), // Rule ID 59128 // |
| 95626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 95627 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 95628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95629 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95630 | // (sint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFWCVT_F_X_V_M2_E16:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95631 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 95632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95633 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M2_E16), |
| 95636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95638 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95642 | GIR_RootConstrainSelectedInstOperands, |
| 95643 | // GIR_Coverage, 59128, |
| 95644 | GIR_EraseRootFromParent_Done, |
| 95645 | // Label 6393: @243990 |
| 95646 | GIM_Try, /*On fail goto*//*Label 6394*/ GIMT_Encode4(244044), // Rule ID 59129 // |
| 95647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 95648 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 95649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95650 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95651 | // (sint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFWCVT_F_X_V_M2_E16:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95652 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 95653 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95654 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M2_E16), |
| 95657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95658 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95659 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95663 | GIR_RootConstrainSelectedInstOperands, |
| 95664 | // GIR_Coverage, 59129, |
| 95665 | GIR_EraseRootFromParent_Done, |
| 95666 | // Label 6394: @244044 |
| 95667 | GIM_Try, /*On fail goto*//*Label 6395*/ GIMT_Encode4(244101), // Rule ID 59356 // |
| 95668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 95669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 95670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95672 | // (sint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFNCVT_F_X_W_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95673 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 95674 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95675 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M4_E32), |
| 95678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95679 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95680 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95685 | GIR_RootConstrainSelectedInstOperands, |
| 95686 | // GIR_Coverage, 59356, |
| 95687 | GIR_EraseRootFromParent_Done, |
| 95688 | // Label 6395: @244101 |
| 95689 | GIM_Try, /*On fail goto*//*Label 6396*/ GIMT_Encode4(244158), // Rule ID 59357 // |
| 95690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 95691 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 95692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95693 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95694 | // (sint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFNCVT_F_X_W_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95695 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 95696 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95697 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M4_E32), |
| 95700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95701 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95702 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95707 | GIR_RootConstrainSelectedInstOperands, |
| 95708 | // GIR_Coverage, 59357, |
| 95709 | GIR_EraseRootFromParent_Done, |
| 95710 | // Label 6396: @244158 |
| 95711 | GIM_Reject, |
| 95712 | // Label 6305: @244159 |
| 95713 | GIM_Try, /*On fail goto*//*Label 6397*/ GIMT_Encode4(244216), // Rule ID 58964 // |
| 95714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 95715 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 95716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95718 | // (sint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFCVT_F_X_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 95719 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 95720 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95721 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95722 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M8_E64), |
| 95724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95725 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95726 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 95730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95731 | GIR_RootConstrainSelectedInstOperands, |
| 95732 | // GIR_Coverage, 58964, |
| 95733 | GIR_EraseRootFromParent_Done, |
| 95734 | // Label 6397: @244216 |
| 95735 | GIM_Try, /*On fail goto*//*Label 6398*/ GIMT_Encode4(244273), // Rule ID 58965 // |
| 95736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 95737 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 95738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95739 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95740 | // (sint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFCVT_F_X_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 95741 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 95742 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95743 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M8_E64), |
| 95746 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95747 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95748 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 95752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95753 | GIR_RootConstrainSelectedInstOperands, |
| 95754 | // GIR_Coverage, 58965, |
| 95755 | GIR_EraseRootFromParent_Done, |
| 95756 | // Label 6398: @244273 |
| 95757 | GIM_Try, /*On fail goto*//*Label 6399*/ GIMT_Encode4(244327), // Rule ID 59148 // |
| 95758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 95759 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 95760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95761 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95762 | // (sint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFWCVT_F_X_V_M4_E32:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95763 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 95764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95765 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M4_E32), |
| 95768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95769 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95770 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95774 | GIR_RootConstrainSelectedInstOperands, |
| 95775 | // GIR_Coverage, 59148, |
| 95776 | GIR_EraseRootFromParent_Done, |
| 95777 | // Label 6399: @244327 |
| 95778 | GIM_Try, /*On fail goto*//*Label 6400*/ GIMT_Encode4(244381), // Rule ID 59149 // |
| 95779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 95780 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 95781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95782 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95783 | // (sint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFWCVT_F_X_V_M4_E32:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 95785 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M4_E32), |
| 95789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95790 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95791 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95795 | GIR_RootConstrainSelectedInstOperands, |
| 95796 | // GIR_Coverage, 59149, |
| 95797 | GIR_EraseRootFromParent_Done, |
| 95798 | // Label 6400: @244381 |
| 95799 | GIM_Reject, |
| 95800 | // Label 6306: @244382 |
| 95801 | GIM_Try, /*On fail goto*//*Label 6401*/ GIMT_Encode4(244439), // Rule ID 58936 // |
| 95802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95803 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 95804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95806 | // (sint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFCVT_F_X_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 95808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M4_E16), |
| 95812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95819 | GIR_RootConstrainSelectedInstOperands, |
| 95820 | // GIR_Coverage, 58936, |
| 95821 | GIR_EraseRootFromParent_Done, |
| 95822 | // Label 6401: @244439 |
| 95823 | GIM_Try, /*On fail goto*//*Label 6402*/ GIMT_Encode4(244496), // Rule ID 58937 // |
| 95824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95825 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 95826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95828 | // (sint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFCVT_F_X_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95829 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 95830 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95831 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M4_E16), |
| 95834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95835 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95836 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95841 | GIR_RootConstrainSelectedInstOperands, |
| 95842 | // GIR_Coverage, 58937, |
| 95843 | GIR_EraseRootFromParent_Done, |
| 95844 | // Label 6402: @244496 |
| 95845 | GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(244550), // Rule ID 59108 // |
| 95846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95847 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 95848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95849 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95850 | // (sint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVFWCVT_F_X_V_M2_E8:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 95851 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 95852 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95853 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95854 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M2_E8), |
| 95856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95857 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95858 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95862 | GIR_RootConstrainSelectedInstOperands, |
| 95863 | // GIR_Coverage, 59108, |
| 95864 | GIR_EraseRootFromParent_Done, |
| 95865 | // Label 6403: @244550 |
| 95866 | GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(244604), // Rule ID 59109 // |
| 95867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95868 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 95869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95870 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 95871 | // (sint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVFWCVT_F_X_V_M2_E8:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 95872 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 95873 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95874 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M2_E8), |
| 95877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95878 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95879 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95883 | GIR_RootConstrainSelectedInstOperands, |
| 95884 | // GIR_Coverage, 59109, |
| 95885 | GIR_EraseRootFromParent_Done, |
| 95886 | // Label 6404: @244604 |
| 95887 | GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(244661), // Rule ID 59340 // |
| 95888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 95889 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 95890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95892 | // (sint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFNCVT_F_X_W_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 95894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M4_E16), |
| 95898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95900 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95905 | GIR_RootConstrainSelectedInstOperands, |
| 95906 | // GIR_Coverage, 59340, |
| 95907 | GIR_EraseRootFromParent_Done, |
| 95908 | // Label 6405: @244661 |
| 95909 | GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(244718), // Rule ID 59341 // |
| 95910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 95911 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 95912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95913 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95914 | // (sint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFNCVT_F_X_W_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 95915 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 95916 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95917 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95918 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_X_W_M4_E16), |
| 95920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95921 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95922 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95927 | GIR_RootConstrainSelectedInstOperands, |
| 95928 | // GIR_Coverage, 59341, |
| 95929 | GIR_EraseRootFromParent_Done, |
| 95930 | // Label 6406: @244718 |
| 95931 | GIM_Reject, |
| 95932 | // Label 6307: @244719 |
| 95933 | GIM_Try, /*On fail goto*//*Label 6407*/ GIMT_Encode4(244776), // Rule ID 58952 // |
| 95934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 95935 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 95936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95937 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95938 | // (sint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFCVT_F_X_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 95939 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 95940 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95941 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95942 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M8_E32), |
| 95944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95945 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95946 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95951 | GIR_RootConstrainSelectedInstOperands, |
| 95952 | // GIR_Coverage, 58952, |
| 95953 | GIR_EraseRootFromParent_Done, |
| 95954 | // Label 6407: @244776 |
| 95955 | GIM_Try, /*On fail goto*//*Label 6408*/ GIMT_Encode4(244833), // Rule ID 58953 // |
| 95956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 95957 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 95958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95960 | // (sint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFCVT_F_X_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 95961 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 95962 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95963 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95964 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M8_E32), |
| 95966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95967 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95968 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 95970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 95972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95973 | GIR_RootConstrainSelectedInstOperands, |
| 95974 | // GIR_Coverage, 58953, |
| 95975 | GIR_EraseRootFromParent_Done, |
| 95976 | // Label 6408: @244833 |
| 95977 | GIM_Try, /*On fail goto*//*Label 6409*/ GIMT_Encode4(244887), // Rule ID 59132 // |
| 95978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 95979 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 95980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 95981 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 95982 | // (sint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFWCVT_F_X_V_M4_E16:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 95983 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 95984 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 95985 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 95986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 95987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M4_E16), |
| 95988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 95989 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 95990 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 95991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 95992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 95993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 95994 | GIR_RootConstrainSelectedInstOperands, |
| 95995 | // GIR_Coverage, 59132, |
| 95996 | GIR_EraseRootFromParent_Done, |
| 95997 | // Label 6409: @244887 |
| 95998 | GIM_Try, /*On fail goto*//*Label 6410*/ GIMT_Encode4(244941), // Rule ID 59133 // |
| 95999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 96000 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 96001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96002 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 96003 | // (sint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFWCVT_F_X_V_M4_E16:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 96004 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 96005 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96006 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M4_E16), |
| 96009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96010 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96011 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96015 | GIR_RootConstrainSelectedInstOperands, |
| 96016 | // GIR_Coverage, 59133, |
| 96017 | GIR_EraseRootFromParent_Done, |
| 96018 | // Label 6410: @244941 |
| 96019 | GIM_Reject, |
| 96020 | // Label 6308: @244942 |
| 96021 | GIM_Try, /*On fail goto*//*Label 6411*/ GIMT_Encode4(244999), // Rule ID 58940 // |
| 96022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96023 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 96024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96025 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96026 | // (sint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVFCVT_F_X_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 96027 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 96028 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96029 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M8_E16), |
| 96032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96033 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96034 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96039 | GIR_RootConstrainSelectedInstOperands, |
| 96040 | // GIR_Coverage, 58940, |
| 96041 | GIR_EraseRootFromParent_Done, |
| 96042 | // Label 6411: @244999 |
| 96043 | GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(245056), // Rule ID 58941 // |
| 96044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96045 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 96046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96047 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96048 | // (sint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVFCVT_F_X_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 96049 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 96050 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96051 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96052 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_X_V_M8_E16), |
| 96054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96055 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96056 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96061 | GIR_RootConstrainSelectedInstOperands, |
| 96062 | // GIR_Coverage, 58941, |
| 96063 | GIR_EraseRootFromParent_Done, |
| 96064 | // Label 6412: @245056 |
| 96065 | GIM_Try, /*On fail goto*//*Label 6413*/ GIMT_Encode4(245110), // Rule ID 59112 // |
| 96066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96067 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 96068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96069 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 96070 | // (sint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVFWCVT_F_X_V_M4_E8:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 96071 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 96072 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96073 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M4_E8), |
| 96076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96077 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96078 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96082 | GIR_RootConstrainSelectedInstOperands, |
| 96083 | // GIR_Coverage, 59112, |
| 96084 | GIR_EraseRootFromParent_Done, |
| 96085 | // Label 6413: @245110 |
| 96086 | GIM_Try, /*On fail goto*//*Label 6414*/ GIMT_Encode4(245164), // Rule ID 59113 // |
| 96087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96088 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 96089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 96090 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 96091 | // (sint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVFWCVT_F_X_V_M4_E8:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 96092 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 96093 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96094 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96095 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_X_V_M4_E8), |
| 96097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96098 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96099 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96103 | GIR_RootConstrainSelectedInstOperands, |
| 96104 | // GIR_Coverage, 59113, |
| 96105 | GIR_EraseRootFromParent_Done, |
| 96106 | // Label 6414: @245164 |
| 96107 | GIM_Reject, |
| 96108 | // Label 6309: @245165 |
| 96109 | GIM_Reject, |
| 96110 | // Label 64: @245166 |
| 96111 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 6433*/ GIMT_Encode4(250706), |
| 96112 | /*GILLT_s16*//*Label 6415*/ GIMT_Encode4(245297), |
| 96113 | /*GILLT_s32*//*Label 6416*/ GIMT_Encode4(245961), |
| 96114 | /*GILLT_s64*//*Label 6417*/ GIMT_Encode4(246148), GIMT_Encode4(0), GIMT_Encode4(0), |
| 96115 | /*GILLT_nxv1s16*//*Label 6418*/ GIMT_Encode4(246335), |
| 96116 | /*GILLT_nxv1s32*//*Label 6419*/ GIMT_Encode4(246672), |
| 96117 | /*GILLT_nxv1s64*//*Label 6420*/ GIMT_Encode4(247009), GIMT_Encode4(0), GIMT_Encode4(0), |
| 96118 | /*GILLT_nxv2s16*//*Label 6421*/ GIMT_Encode4(247232), |
| 96119 | /*GILLT_nxv2s32*//*Label 6422*/ GIMT_Encode4(247569), |
| 96120 | /*GILLT_nxv2s64*//*Label 6423*/ GIMT_Encode4(247906), GIMT_Encode4(0), GIMT_Encode4(0), |
| 96121 | /*GILLT_nxv4s16*//*Label 6424*/ GIMT_Encode4(248129), |
| 96122 | /*GILLT_nxv4s32*//*Label 6425*/ GIMT_Encode4(248466), |
| 96123 | /*GILLT_nxv4s64*//*Label 6426*/ GIMT_Encode4(248803), GIMT_Encode4(0), GIMT_Encode4(0), |
| 96124 | /*GILLT_nxv8s16*//*Label 6427*/ GIMT_Encode4(249026), |
| 96125 | /*GILLT_nxv8s32*//*Label 6428*/ GIMT_Encode4(249363), |
| 96126 | /*GILLT_nxv8s64*//*Label 6429*/ GIMT_Encode4(249700), GIMT_Encode4(0), GIMT_Encode4(0), |
| 96127 | /*GILLT_nxv16s16*//*Label 6430*/ GIMT_Encode4(249923), |
| 96128 | /*GILLT_nxv16s32*//*Label 6431*/ GIMT_Encode4(250260), GIMT_Encode4(0), GIMT_Encode4(0), |
| 96129 | /*GILLT_nxv32s16*//*Label 6432*/ GIMT_Encode4(250483), |
| 96130 | // Label 6415: @245297 |
| 96131 | GIM_Try, /*On fail goto*//*Label 6434*/ GIMT_Encode4(245328), // Rule ID 2262 // |
| 96132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 96133 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96136 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_WU:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 96137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_WU), |
| 96138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96139 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96141 | GIR_RootConstrainSelectedInstOperands, |
| 96142 | // GIR_Coverage, 2262, |
| 96143 | GIR_EraseRootFromParent_Done, |
| 96144 | // Label 6434: @245328 |
| 96145 | GIM_Try, /*On fail goto*//*Label 6435*/ GIMT_Encode4(245359), // Rule ID 2263 // |
| 96146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 96147 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96150 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_WU:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 96151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_WU), |
| 96152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96153 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96155 | GIR_RootConstrainSelectedInstOperands, |
| 96156 | // GIR_Coverage, 2263, |
| 96157 | GIR_EraseRootFromParent_Done, |
| 96158 | // Label 6435: @245359 |
| 96159 | GIM_Try, /*On fail goto*//*Label 6436*/ GIMT_Encode4(245390), // Rule ID 2288 // |
| 96160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 96161 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 96163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96164 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_WU_INX:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 96165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_WU_INX), |
| 96166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96167 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96169 | GIR_RootConstrainSelectedInstOperands, |
| 96170 | // GIR_Coverage, 2288, |
| 96171 | GIR_EraseRootFromParent_Done, |
| 96172 | // Label 6436: @245390 |
| 96173 | GIM_Try, /*On fail goto*//*Label 6437*/ GIMT_Encode4(245421), // Rule ID 2289 // |
| 96174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 96175 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 96177 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96178 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_WU_INX:{ *:[f16] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 96179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_WU_INX), |
| 96180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96181 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96183 | GIR_RootConstrainSelectedInstOperands, |
| 96184 | // GIR_Coverage, 2289, |
| 96185 | GIR_EraseRootFromParent_Done, |
| 96186 | // Label 6437: @245421 |
| 96187 | GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(245452), // Rule ID 2315 // |
| 96188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 96189 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96191 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96192 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_LU:{ *:[f16] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 96193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_LU), |
| 96194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96197 | GIR_RootConstrainSelectedInstOperands, |
| 96198 | // GIR_Coverage, 2315, |
| 96199 | GIR_EraseRootFromParent_Done, |
| 96200 | // Label 6438: @245452 |
| 96201 | GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(245483), // Rule ID 2341 // |
| 96202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 96203 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 96205 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96206 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_LU_INX:{ *:[f16] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 96207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_LU_INX), |
| 96208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96209 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96211 | GIR_RootConstrainSelectedInstOperands, |
| 96212 | // GIR_Coverage, 2341, |
| 96213 | GIR_EraseRootFromParent_Done, |
| 96214 | // Label 6439: @245483 |
| 96215 | GIM_Try, /*On fail goto*//*Label 6440*/ GIMT_Encode4(245536), // Rule ID 2394 // |
| 96216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0), |
| 96217 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96219 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96220 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S:{ *:[f16] } (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 96221 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96222 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU), |
| 96223 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96224 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96225 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 96228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96229 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96231 | GIR_RootConstrainSelectedInstOperands, |
| 96232 | // GIR_Coverage, 2394, |
| 96233 | GIR_EraseRootFromParent_Done, |
| 96234 | // Label 6440: @245536 |
| 96235 | GIM_Try, /*On fail goto*//*Label 6441*/ GIMT_Encode4(245589), // Rule ID 2395 // |
| 96236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1), |
| 96237 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96240 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S:{ *:[f16] } (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }), 7:{ *:[i32] }) |
| 96241 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96242 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU), |
| 96243 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96244 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96245 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96246 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 96248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96249 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96251 | GIR_RootConstrainSelectedInstOperands, |
| 96252 | // GIR_Coverage, 2395, |
| 96253 | GIR_EraseRootFromParent_Done, |
| 96254 | // Label 6441: @245589 |
| 96255 | GIM_Try, /*On fail goto*//*Label 6442*/ GIMT_Encode4(245642), // Rule ID 2418 // |
| 96256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0), |
| 96257 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 96259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96260 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } (FCVT_S_WU_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 96261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU_INX), |
| 96263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96264 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96265 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 96268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96269 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96271 | GIR_RootConstrainSelectedInstOperands, |
| 96272 | // GIR_Coverage, 2418, |
| 96273 | GIR_EraseRootFromParent_Done, |
| 96274 | // Label 6442: @245642 |
| 96275 | GIM_Try, /*On fail goto*//*Label 6443*/ GIMT_Encode4(245695), // Rule ID 2419 // |
| 96276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1), |
| 96277 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 96279 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96280 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } (FCVT_S_WU_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }), 7:{ *:[i32] }) |
| 96281 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU_INX), |
| 96283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96284 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96285 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 96288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96289 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96291 | GIR_RootConstrainSelectedInstOperands, |
| 96292 | // GIR_Coverage, 2419, |
| 96293 | GIR_EraseRootFromParent_Done, |
| 96294 | // Label 6443: @245695 |
| 96295 | GIM_Try, /*On fail goto*//*Label 6444*/ GIMT_Encode4(245748), // Rule ID 2435 // |
| 96296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 96297 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96299 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96300 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_S:{ *:[f16] } (FCVT_S_LU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 96301 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96302 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_LU), |
| 96303 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96304 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96305 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 96308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96311 | GIR_RootConstrainSelectedInstOperands, |
| 96312 | // GIR_Coverage, 2435, |
| 96313 | GIR_EraseRootFromParent_Done, |
| 96314 | // Label 6444: @245748 |
| 96315 | GIM_Try, /*On fail goto*//*Label 6445*/ GIMT_Encode4(245801), // Rule ID 2451 // |
| 96316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 96317 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 96319 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96320 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i64] }:$rs1) => (FCVT_H_S_INX:{ *:[f16] } (FCVT_S_LU_INX:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 96321 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96322 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_LU_INX), |
| 96323 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96324 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96325 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 96328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96329 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96331 | GIR_RootConstrainSelectedInstOperands, |
| 96332 | // GIR_Coverage, 2451, |
| 96333 | GIR_EraseRootFromParent_Done, |
| 96334 | // Label 6445: @245801 |
| 96335 | GIM_Try, /*On fail goto*//*Label 6446*/ GIMT_Encode4(245854), // Rule ID 2480 // |
| 96336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode0), |
| 96337 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96339 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96340 | // (uint_to_fp:{ *:[bf16] } GPR:{ *:[i32] }:$rs1) => (FCVT_BF16_S:{ *:[bf16] } (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 96341 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96342 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU), |
| 96343 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96344 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96345 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96346 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_BF16_S), |
| 96348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96351 | GIR_RootConstrainSelectedInstOperands, |
| 96352 | // GIR_Coverage, 2480, |
| 96353 | GIR_EraseRootFromParent_Done, |
| 96354 | // Label 6446: @245854 |
| 96355 | GIM_Try, /*On fail goto*//*Label 6447*/ GIMT_Encode4(245907), // Rule ID 2481 // |
| 96356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_HwMode1), |
| 96357 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96360 | // (uint_to_fp:{ *:[bf16] } GPR:{ *:[i32] }:$rs1) => (FCVT_BF16_S:{ *:[bf16] } (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }), 7:{ *:[i32] }) |
| 96361 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96362 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU), |
| 96363 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96364 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96365 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96366 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_BF16_S), |
| 96368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96369 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96371 | GIR_RootConstrainSelectedInstOperands, |
| 96372 | // GIR_Coverage, 2481, |
| 96373 | GIR_EraseRootFromParent_Done, |
| 96374 | // Label 6447: @245907 |
| 96375 | GIM_Try, /*On fail goto*//*Label 6448*/ GIMT_Encode4(245960), // Rule ID 2489 // |
| 96376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfbfmin_IsRV64_HwMode0), |
| 96377 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 96379 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96380 | // (uint_to_fp:{ *:[bf16] } GPR:{ *:[i64] }:$rs1) => (FCVT_BF16_S:{ *:[bf16] } (FCVT_S_LU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }), 7:{ *:[i64] }) |
| 96381 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 96382 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_LU), |
| 96383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96384 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 96385 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 96386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_BF16_S), |
| 96388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96391 | GIR_RootConstrainSelectedInstOperands, |
| 96392 | // GIR_Coverage, 2489, |
| 96393 | GIR_EraseRootFromParent_Done, |
| 96394 | // Label 6448: @245960 |
| 96395 | GIM_Reject, |
| 96396 | // Label 6416: @245961 |
| 96397 | GIM_Try, /*On fail goto*//*Label 6449*/ GIMT_Encode4(245992), // Rule ID 1545 // |
| 96398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 96399 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 96401 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96402 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 96403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU), |
| 96404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96405 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96407 | GIR_RootConstrainSelectedInstOperands, |
| 96408 | // GIR_Coverage, 1545, |
| 96409 | GIR_EraseRootFromParent_Done, |
| 96410 | // Label 6449: @245992 |
| 96411 | GIM_Try, /*On fail goto*//*Label 6450*/ GIMT_Encode4(246023), // Rule ID 1546 // |
| 96412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 96413 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 96415 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96416 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 96417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU), |
| 96418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96419 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96421 | GIR_RootConstrainSelectedInstOperands, |
| 96422 | // GIR_Coverage, 1546, |
| 96423 | GIR_EraseRootFromParent_Done, |
| 96424 | // Label 6450: @246023 |
| 96425 | GIM_Try, /*On fail goto*//*Label 6451*/ GIMT_Encode4(246054), // Rule ID 1571 // |
| 96426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 96427 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96428 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 96429 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96430 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_WU_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i64] }) |
| 96431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU_INX), |
| 96432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96433 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96435 | GIR_RootConstrainSelectedInstOperands, |
| 96436 | // GIR_Coverage, 1571, |
| 96437 | GIR_EraseRootFromParent_Done, |
| 96438 | // Label 6451: @246054 |
| 96439 | GIM_Try, /*On fail goto*//*Label 6452*/ GIMT_Encode4(246085), // Rule ID 1572 // |
| 96440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 96441 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 96443 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96444 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FCVT_S_WU_INX:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] }) |
| 96445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_WU_INX), |
| 96446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96447 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96449 | GIR_RootConstrainSelectedInstOperands, |
| 96450 | // GIR_Coverage, 1572, |
| 96451 | GIR_EraseRootFromParent_Done, |
| 96452 | // Label 6452: @246085 |
| 96453 | GIM_Try, /*On fail goto*//*Label 6453*/ GIMT_Encode4(246116), // Rule ID 1600 // |
| 96454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 96455 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 96457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96458 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) => (FCVT_S_LU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 96459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_LU), |
| 96460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96461 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96463 | GIR_RootConstrainSelectedInstOperands, |
| 96464 | // GIR_Coverage, 1600, |
| 96465 | GIR_EraseRootFromParent_Done, |
| 96466 | // Label 6453: @246116 |
| 96467 | GIM_Try, /*On fail goto*//*Label 6454*/ GIMT_Encode4(246147), // Rule ID 1628 // |
| 96468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 96469 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 96471 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96472 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) => (FCVT_S_LU_INX:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 96473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_LU_INX), |
| 96474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96475 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96477 | GIR_RootConstrainSelectedInstOperands, |
| 96478 | // GIR_Coverage, 1628, |
| 96479 | GIR_EraseRootFromParent_Done, |
| 96480 | // Label 6454: @246147 |
| 96481 | GIM_Reject, |
| 96482 | // Label 6417: @246148 |
| 96483 | GIM_Try, /*On fail goto*//*Label 6455*/ GIMT_Encode4(246179), // Rule ID 1926 // |
| 96484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 96485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96486 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 96487 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96488 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i64] }) |
| 96489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_WU), |
| 96490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96491 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96493 | GIR_RootConstrainSelectedInstOperands, |
| 96494 | // GIR_Coverage, 1926, |
| 96495 | GIR_EraseRootFromParent_Done, |
| 96496 | // Label 6455: @246179 |
| 96497 | GIM_Try, /*On fail goto*//*Label 6456*/ GIMT_Encode4(246210), // Rule ID 1927 // |
| 96498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 96499 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 96501 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96502 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) |
| 96503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_WU), |
| 96504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96505 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96507 | GIR_RootConstrainSelectedInstOperands, |
| 96508 | // GIR_Coverage, 1927, |
| 96509 | GIR_EraseRootFromParent_Done, |
| 96510 | // Label 6456: @246210 |
| 96511 | GIM_Try, /*On fail goto*//*Label 6457*/ GIMT_Encode4(246241), // Rule ID 1952 // |
| 96512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 96513 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 96515 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96516 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU_IN32X:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i64] }) |
| 96517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_WU_IN32X), |
| 96518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96521 | GIR_RootConstrainSelectedInstOperands, |
| 96522 | // GIR_Coverage, 1952, |
| 96523 | GIR_EraseRootFromParent_Done, |
| 96524 | // Label 6457: @246241 |
| 96525 | GIM_Try, /*On fail goto*//*Label 6458*/ GIMT_Encode4(246272), // Rule ID 1953 // |
| 96526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 96527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 96528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 96529 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96530 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU_IN32X:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) |
| 96531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_WU_IN32X), |
| 96532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96533 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96535 | GIR_RootConstrainSelectedInstOperands, |
| 96536 | // GIR_Coverage, 1953, |
| 96537 | GIR_EraseRootFromParent_Done, |
| 96538 | // Label 6458: @246272 |
| 96539 | GIM_Try, /*On fail goto*//*Label 6459*/ GIMT_Encode4(246303), // Rule ID 1981 // |
| 96540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 96541 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 96543 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96544 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 96545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_LU), |
| 96546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96547 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96549 | GIR_RootConstrainSelectedInstOperands, |
| 96550 | // GIR_Coverage, 1981, |
| 96551 | GIR_EraseRootFromParent_Done, |
| 96552 | // Label 6459: @246303 |
| 96553 | GIM_Try, /*On fail goto*//*Label 6460*/ GIMT_Encode4(246334), // Rule ID 2009 // |
| 96554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 96555 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 96556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 96558 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_LU_INX:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] }) |
| 96559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_LU_INX), |
| 96560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96561 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96563 | GIR_RootConstrainSelectedInstOperands, |
| 96564 | // GIR_Coverage, 2009, |
| 96565 | GIR_EraseRootFromParent_Done, |
| 96566 | // Label 6460: @246334 |
| 96567 | GIM_Reject, |
| 96568 | // Label 6418: @246335 |
| 96569 | GIM_Try, /*On fail goto*//*Label 6461*/ GIMT_Encode4(246392), // Rule ID 58968 // |
| 96570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96571 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 96572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96574 | // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFCVT_F_XU_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 96575 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 96576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96577 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_MF4_E16), |
| 96580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96581 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96582 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96587 | GIR_RootConstrainSelectedInstOperands, |
| 96588 | // GIR_Coverage, 58968, |
| 96589 | GIR_EraseRootFromParent_Done, |
| 96590 | // Label 6461: @246392 |
| 96591 | GIM_Try, /*On fail goto*//*Label 6462*/ GIMT_Encode4(246449), // Rule ID 58969 // |
| 96592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96593 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 96594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96596 | // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFCVT_F_XU_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 96597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 96598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96600 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_MF4_E16), |
| 96602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96604 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96609 | GIR_RootConstrainSelectedInstOperands, |
| 96610 | // GIR_Coverage, 58969, |
| 96611 | GIR_EraseRootFromParent_Done, |
| 96612 | // Label 6462: @246449 |
| 96613 | GIM_Try, /*On fail goto*//*Label 6463*/ GIMT_Encode4(246503), // Rule ID 59152 // |
| 96614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96615 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 96616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96617 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96618 | // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF8_E8:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 96619 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 96620 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96621 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96622 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF8_E8), |
| 96624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96625 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96626 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96630 | GIR_RootConstrainSelectedInstOperands, |
| 96631 | // GIR_Coverage, 59152, |
| 96632 | GIR_EraseRootFromParent_Done, |
| 96633 | // Label 6463: @246503 |
| 96634 | GIM_Try, /*On fail goto*//*Label 6464*/ GIMT_Encode4(246557), // Rule ID 59153 // |
| 96635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 96637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96638 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96639 | // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF8_E8:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 96640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 96641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF8_E8), |
| 96645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96647 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96651 | GIR_RootConstrainSelectedInstOperands, |
| 96652 | // GIR_Coverage, 59153, |
| 96653 | GIR_EraseRootFromParent_Done, |
| 96654 | // Label 6464: @246557 |
| 96655 | GIM_Try, /*On fail goto*//*Label 6465*/ GIMT_Encode4(246614), // Rule ID 59360 // |
| 96656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96657 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 96658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96660 | // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 96661 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 96662 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96663 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_MF4_E16), |
| 96666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96667 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96668 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96673 | GIR_RootConstrainSelectedInstOperands, |
| 96674 | // GIR_Coverage, 59360, |
| 96675 | GIR_EraseRootFromParent_Done, |
| 96676 | // Label 6465: @246614 |
| 96677 | GIM_Try, /*On fail goto*//*Label 6466*/ GIMT_Encode4(246671), // Rule ID 59361 // |
| 96678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96679 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 96680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96681 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96682 | // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 96683 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 96684 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96685 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_MF4_E16), |
| 96688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96689 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96690 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96695 | GIR_RootConstrainSelectedInstOperands, |
| 96696 | // GIR_Coverage, 59361, |
| 96697 | GIR_EraseRootFromParent_Done, |
| 96698 | // Label 6466: @246671 |
| 96699 | GIM_Reject, |
| 96700 | // Label 6419: @246672 |
| 96701 | GIM_Try, /*On fail goto*//*Label 6467*/ GIMT_Encode4(246729), // Rule ID 58976 // |
| 96702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 96703 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 96704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96705 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96706 | // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFCVT_F_XU_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 96707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 96708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_MF2_E32), |
| 96712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96713 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96714 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 96718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96719 | GIR_RootConstrainSelectedInstOperands, |
| 96720 | // GIR_Coverage, 58976, |
| 96721 | GIR_EraseRootFromParent_Done, |
| 96722 | // Label 6467: @246729 |
| 96723 | GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(246786), // Rule ID 58977 // |
| 96724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 96725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 96726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96727 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96728 | // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFCVT_F_XU_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 96729 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 96730 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96731 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96732 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_MF2_E32), |
| 96734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96735 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96736 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 96740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96741 | GIR_RootConstrainSelectedInstOperands, |
| 96742 | // GIR_Coverage, 58977, |
| 96743 | GIR_EraseRootFromParent_Done, |
| 96744 | // Label 6468: @246786 |
| 96745 | GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(246840), // Rule ID 59176 // |
| 96746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 96747 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 96748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96750 | // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF4_E16:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 96751 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 96752 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96753 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96754 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF4_E16), |
| 96756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96757 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96758 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96762 | GIR_RootConstrainSelectedInstOperands, |
| 96763 | // GIR_Coverage, 59176, |
| 96764 | GIR_EraseRootFromParent_Done, |
| 96765 | // Label 6469: @246840 |
| 96766 | GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(246894), // Rule ID 59177 // |
| 96767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 96768 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 96769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96771 | // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF4_E16:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 96772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 96773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96774 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF4_E16), |
| 96777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96778 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96779 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96783 | GIR_RootConstrainSelectedInstOperands, |
| 96784 | // GIR_Coverage, 59177, |
| 96785 | GIR_EraseRootFromParent_Done, |
| 96786 | // Label 6470: @246894 |
| 96787 | GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(246951), // Rule ID 59380 // |
| 96788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 96789 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 96790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96791 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96792 | // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 96793 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 96794 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96795 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96796 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_MF2_E32), |
| 96798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96799 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96800 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 96804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96805 | GIR_RootConstrainSelectedInstOperands, |
| 96806 | // GIR_Coverage, 59380, |
| 96807 | GIR_EraseRootFromParent_Done, |
| 96808 | // Label 6471: @246951 |
| 96809 | GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(247008), // Rule ID 59381 // |
| 96810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 96811 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 96812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96813 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96814 | // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 96815 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 96816 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96817 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_MF2_E32), |
| 96820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96821 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96822 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 96826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96827 | GIR_RootConstrainSelectedInstOperands, |
| 96828 | // GIR_Coverage, 59381, |
| 96829 | GIR_EraseRootFromParent_Done, |
| 96830 | // Label 6472: @247008 |
| 96831 | GIM_Reject, |
| 96832 | // Label 6420: @247009 |
| 96833 | GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(247066), // Rule ID 58988 // |
| 96834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 96835 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 96836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96837 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96838 | // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 96839 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 96840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M1_E64), |
| 96844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96845 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96846 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 96850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96851 | GIR_RootConstrainSelectedInstOperands, |
| 96852 | // GIR_Coverage, 58988, |
| 96853 | GIR_EraseRootFromParent_Done, |
| 96854 | // Label 6473: @247066 |
| 96855 | GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(247123), // Rule ID 58989 // |
| 96856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 96857 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 96858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96859 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96860 | // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 96861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 96862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96864 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M1_E64), |
| 96866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96868 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 96872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96873 | GIR_RootConstrainSelectedInstOperands, |
| 96874 | // GIR_Coverage, 58989, |
| 96875 | GIR_EraseRootFromParent_Done, |
| 96876 | // Label 6474: @247123 |
| 96877 | GIM_Try, /*On fail goto*//*Label 6475*/ GIMT_Encode4(247177), // Rule ID 59196 // |
| 96878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 96879 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 96880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96882 | // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF2_E32:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 96883 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 96884 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96885 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96886 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF2_E32), |
| 96888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96890 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 96893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96894 | GIR_RootConstrainSelectedInstOperands, |
| 96895 | // GIR_Coverage, 59196, |
| 96896 | GIR_EraseRootFromParent_Done, |
| 96897 | // Label 6475: @247177 |
| 96898 | GIM_Try, /*On fail goto*//*Label 6476*/ GIMT_Encode4(247231), // Rule ID 59197 // |
| 96899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 96900 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 96901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96902 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96903 | // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF2_E32:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 96904 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 96905 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96906 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF2_E32), |
| 96909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96910 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96911 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 96914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96915 | GIR_RootConstrainSelectedInstOperands, |
| 96916 | // GIR_Coverage, 59197, |
| 96917 | GIR_EraseRootFromParent_Done, |
| 96918 | // Label 6476: @247231 |
| 96919 | GIM_Reject, |
| 96920 | // Label 6421: @247232 |
| 96921 | GIM_Try, /*On fail goto*//*Label 6477*/ GIMT_Encode4(247289), // Rule ID 58972 // |
| 96922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96923 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 96924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96925 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96926 | // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFCVT_F_XU_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 96927 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 96928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_MF2_E16), |
| 96932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96933 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96934 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96939 | GIR_RootConstrainSelectedInstOperands, |
| 96940 | // GIR_Coverage, 58972, |
| 96941 | GIR_EraseRootFromParent_Done, |
| 96942 | // Label 6477: @247289 |
| 96943 | GIM_Try, /*On fail goto*//*Label 6478*/ GIMT_Encode4(247346), // Rule ID 58973 // |
| 96944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96945 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 96946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96947 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96948 | // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFCVT_F_XU_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 96949 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 96950 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96951 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_MF2_E16), |
| 96954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96955 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96956 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 96958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 96960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96961 | GIR_RootConstrainSelectedInstOperands, |
| 96962 | // GIR_Coverage, 58973, |
| 96963 | GIR_EraseRootFromParent_Done, |
| 96964 | // Label 6478: @247346 |
| 96965 | GIM_Try, /*On fail goto*//*Label 6479*/ GIMT_Encode4(247400), // Rule ID 59156 // |
| 96966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 96967 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 96968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96970 | // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF4_E8:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 96971 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 96972 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96973 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF4_E8), |
| 96976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96977 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96978 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 96979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 96980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 96982 | GIR_RootConstrainSelectedInstOperands, |
| 96983 | // GIR_Coverage, 59156, |
| 96984 | GIR_EraseRootFromParent_Done, |
| 96985 | // Label 6479: @247400 |
| 96986 | GIM_Try, /*On fail goto*//*Label 6480*/ GIMT_Encode4(247454), // Rule ID 59157 // |
| 96987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 96988 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 96989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 96991 | // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF4_E8:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 96992 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 96993 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 96994 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 96995 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 96996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF4_E8), |
| 96997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 96998 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 96999 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97003 | GIR_RootConstrainSelectedInstOperands, |
| 97004 | // GIR_Coverage, 59157, |
| 97005 | GIR_EraseRootFromParent_Done, |
| 97006 | // Label 6480: @247454 |
| 97007 | GIM_Try, /*On fail goto*//*Label 6481*/ GIMT_Encode4(247511), // Rule ID 59364 // |
| 97008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97009 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 97010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97011 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97012 | // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97013 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 97014 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97015 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_MF2_E16), |
| 97018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97019 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97020 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97025 | GIR_RootConstrainSelectedInstOperands, |
| 97026 | // GIR_Coverage, 59364, |
| 97027 | GIR_EraseRootFromParent_Done, |
| 97028 | // Label 6481: @247511 |
| 97029 | GIM_Try, /*On fail goto*//*Label 6482*/ GIMT_Encode4(247568), // Rule ID 59365 // |
| 97030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97031 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 97032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97033 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97034 | // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97035 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 97036 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97037 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97038 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_MF2_E16), |
| 97040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97041 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97042 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97047 | GIR_RootConstrainSelectedInstOperands, |
| 97048 | // GIR_Coverage, 59365, |
| 97049 | GIR_EraseRootFromParent_Done, |
| 97050 | // Label 6482: @247568 |
| 97051 | GIM_Reject, |
| 97052 | // Label 6422: @247569 |
| 97053 | GIM_Try, /*On fail goto*//*Label 6483*/ GIMT_Encode4(247626), // Rule ID 58984 // |
| 97054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 97055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 97056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97057 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97058 | // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97059 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 97060 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97061 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M1_E32), |
| 97064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97065 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97066 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97071 | GIR_RootConstrainSelectedInstOperands, |
| 97072 | // GIR_Coverage, 58984, |
| 97073 | GIR_EraseRootFromParent_Done, |
| 97074 | // Label 6483: @247626 |
| 97075 | GIM_Try, /*On fail goto*//*Label 6484*/ GIMT_Encode4(247683), // Rule ID 58985 // |
| 97076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 97077 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 97078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97080 | // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 97082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M1_E32), |
| 97086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97087 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97088 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97093 | GIR_RootConstrainSelectedInstOperands, |
| 97094 | // GIR_Coverage, 58985, |
| 97095 | GIR_EraseRootFromParent_Done, |
| 97096 | // Label 6484: @247683 |
| 97097 | GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(247737), // Rule ID 59180 // |
| 97098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 97099 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 97100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97101 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97102 | // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF2_E16:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97103 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 97104 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97105 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF2_E16), |
| 97108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97109 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97110 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97114 | GIR_RootConstrainSelectedInstOperands, |
| 97115 | // GIR_Coverage, 59180, |
| 97116 | GIR_EraseRootFromParent_Done, |
| 97117 | // Label 6485: @247737 |
| 97118 | GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(247791), // Rule ID 59181 // |
| 97119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 97120 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 97121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97122 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97123 | // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF2_E16:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97124 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 97125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF2_E16), |
| 97129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97130 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97131 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97135 | GIR_RootConstrainSelectedInstOperands, |
| 97136 | // GIR_Coverage, 59181, |
| 97137 | GIR_EraseRootFromParent_Done, |
| 97138 | // Label 6486: @247791 |
| 97139 | GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(247848), // Rule ID 59384 // |
| 97140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 97141 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 97142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97144 | // (uint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 97146 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97147 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97148 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M1_E32), |
| 97150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97151 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97152 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97157 | GIR_RootConstrainSelectedInstOperands, |
| 97158 | // GIR_Coverage, 59384, |
| 97159 | GIR_EraseRootFromParent_Done, |
| 97160 | // Label 6487: @247848 |
| 97161 | GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(247905), // Rule ID 59385 // |
| 97162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 97163 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 97164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97165 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97166 | // (uint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97167 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 97168 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97169 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M1_E32), |
| 97172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97174 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97179 | GIR_RootConstrainSelectedInstOperands, |
| 97180 | // GIR_Coverage, 59385, |
| 97181 | GIR_EraseRootFromParent_Done, |
| 97182 | // Label 6488: @247905 |
| 97183 | GIM_Reject, |
| 97184 | // Label 6423: @247906 |
| 97185 | GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(247963), // Rule ID 59016 // |
| 97186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 97187 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 97188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97189 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97190 | // (uint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 97191 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 97192 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97193 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M2_E64), |
| 97196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97198 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 97202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97203 | GIR_RootConstrainSelectedInstOperands, |
| 97204 | // GIR_Coverage, 59016, |
| 97205 | GIR_EraseRootFromParent_Done, |
| 97206 | // Label 6489: @247963 |
| 97207 | GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(248020), // Rule ID 59017 // |
| 97208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 97209 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 97210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97211 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97212 | // (uint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 97213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 97214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M2_E64), |
| 97218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97219 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97220 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 97224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97225 | GIR_RootConstrainSelectedInstOperands, |
| 97226 | // GIR_Coverage, 59017, |
| 97227 | GIR_EraseRootFromParent_Done, |
| 97228 | // Label 6490: @248020 |
| 97229 | GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(248074), // Rule ID 59200 // |
| 97230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 97231 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 97232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97233 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97234 | // (uint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_M1_E32:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 97236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M1_E32), |
| 97240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97242 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97246 | GIR_RootConstrainSelectedInstOperands, |
| 97247 | // GIR_Coverage, 59200, |
| 97248 | GIR_EraseRootFromParent_Done, |
| 97249 | // Label 6491: @248074 |
| 97250 | GIM_Try, /*On fail goto*//*Label 6492*/ GIMT_Encode4(248128), // Rule ID 59201 // |
| 97251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 97252 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 97253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97255 | // (uint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_M1_E32:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97256 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 97257 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97258 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97259 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M1_E32), |
| 97261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97262 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97263 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97267 | GIR_RootConstrainSelectedInstOperands, |
| 97268 | // GIR_Coverage, 59201, |
| 97269 | GIR_EraseRootFromParent_Done, |
| 97270 | // Label 6492: @248128 |
| 97271 | GIM_Reject, |
| 97272 | // Label 6424: @248129 |
| 97273 | GIM_Try, /*On fail goto*//*Label 6493*/ GIMT_Encode4(248186), // Rule ID 58980 // |
| 97274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97275 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 97276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97277 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97278 | // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97279 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 97280 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97281 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97282 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M1_E16), |
| 97284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97285 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97286 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97291 | GIR_RootConstrainSelectedInstOperands, |
| 97292 | // GIR_Coverage, 58980, |
| 97293 | GIR_EraseRootFromParent_Done, |
| 97294 | // Label 6493: @248186 |
| 97295 | GIM_Try, /*On fail goto*//*Label 6494*/ GIMT_Encode4(248243), // Rule ID 58981 // |
| 97296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97297 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 97298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97299 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97300 | // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97301 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 97302 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97303 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M1_E16), |
| 97306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97307 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97308 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97313 | GIR_RootConstrainSelectedInstOperands, |
| 97314 | // GIR_Coverage, 58981, |
| 97315 | GIR_EraseRootFromParent_Done, |
| 97316 | // Label 6494: @248243 |
| 97317 | GIM_Try, /*On fail goto*//*Label 6495*/ GIMT_Encode4(248297), // Rule ID 59160 // |
| 97318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97319 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 97320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97321 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97322 | // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF2_E8:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 97323 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 97324 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97325 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF2_E8), |
| 97328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97329 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97330 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97334 | GIR_RootConstrainSelectedInstOperands, |
| 97335 | // GIR_Coverage, 59160, |
| 97336 | GIR_EraseRootFromParent_Done, |
| 97337 | // Label 6495: @248297 |
| 97338 | GIM_Try, /*On fail goto*//*Label 6496*/ GIMT_Encode4(248351), // Rule ID 59161 // |
| 97339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97340 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 97341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97342 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97343 | // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_MF2_E8:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 97344 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 97345 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97346 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_MF2_E8), |
| 97349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97350 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97351 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97355 | GIR_RootConstrainSelectedInstOperands, |
| 97356 | // GIR_Coverage, 59161, |
| 97357 | GIR_EraseRootFromParent_Done, |
| 97358 | // Label 6496: @248351 |
| 97359 | GIM_Try, /*On fail goto*//*Label 6497*/ GIMT_Encode4(248408), // Rule ID 59368 // |
| 97360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97361 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 97362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97363 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97364 | // (uint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 97366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M1_E16), |
| 97370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97371 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97372 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97377 | GIR_RootConstrainSelectedInstOperands, |
| 97378 | // GIR_Coverage, 59368, |
| 97379 | GIR_EraseRootFromParent_Done, |
| 97380 | // Label 6497: @248408 |
| 97381 | GIM_Try, /*On fail goto*//*Label 6498*/ GIMT_Encode4(248465), // Rule ID 59369 // |
| 97382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97383 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 97384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97385 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97386 | // (uint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97387 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 97388 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97389 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M1_E16), |
| 97392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97394 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97399 | GIR_RootConstrainSelectedInstOperands, |
| 97400 | // GIR_Coverage, 59369, |
| 97401 | GIR_EraseRootFromParent_Done, |
| 97402 | // Label 6498: @248465 |
| 97403 | GIM_Reject, |
| 97404 | // Label 6425: @248466 |
| 97405 | GIM_Try, /*On fail goto*//*Label 6499*/ GIMT_Encode4(248523), // Rule ID 59004 // |
| 97406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 97407 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 97408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97409 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97410 | // (uint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 97412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97413 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M2_E32), |
| 97416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97417 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97418 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97423 | GIR_RootConstrainSelectedInstOperands, |
| 97424 | // GIR_Coverage, 59004, |
| 97425 | GIR_EraseRootFromParent_Done, |
| 97426 | // Label 6499: @248523 |
| 97427 | GIM_Try, /*On fail goto*//*Label 6500*/ GIMT_Encode4(248580), // Rule ID 59005 // |
| 97428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 97429 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 97430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97431 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97432 | // (uint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97433 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 97434 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97435 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97436 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M2_E32), |
| 97438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97439 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97440 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97445 | GIR_RootConstrainSelectedInstOperands, |
| 97446 | // GIR_Coverage, 59005, |
| 97447 | GIR_EraseRootFromParent_Done, |
| 97448 | // Label 6500: @248580 |
| 97449 | GIM_Try, /*On fail goto*//*Label 6501*/ GIMT_Encode4(248634), // Rule ID 59184 // |
| 97450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 97451 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 97452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97453 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97454 | // (uint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_M1_E16:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97455 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 97456 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97457 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M1_E16), |
| 97460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97462 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97466 | GIR_RootConstrainSelectedInstOperands, |
| 97467 | // GIR_Coverage, 59184, |
| 97468 | GIR_EraseRootFromParent_Done, |
| 97469 | // Label 6501: @248634 |
| 97470 | GIM_Try, /*On fail goto*//*Label 6502*/ GIMT_Encode4(248688), // Rule ID 59185 // |
| 97471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 97472 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 97473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97474 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97475 | // (uint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_M1_E16:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97476 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 97477 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97478 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M1_E16), |
| 97481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97482 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97483 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97487 | GIR_RootConstrainSelectedInstOperands, |
| 97488 | // GIR_Coverage, 59185, |
| 97489 | GIR_EraseRootFromParent_Done, |
| 97490 | // Label 6502: @248688 |
| 97491 | GIM_Try, /*On fail goto*//*Label 6503*/ GIMT_Encode4(248745), // Rule ID 59388 // |
| 97492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 97493 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 97494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97495 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97496 | // (uint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 97498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97499 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M2_E32), |
| 97502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97504 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97509 | GIR_RootConstrainSelectedInstOperands, |
| 97510 | // GIR_Coverage, 59388, |
| 97511 | GIR_EraseRootFromParent_Done, |
| 97512 | // Label 6503: @248745 |
| 97513 | GIM_Try, /*On fail goto*//*Label 6504*/ GIMT_Encode4(248802), // Rule ID 59389 // |
| 97514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 97515 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 97516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97517 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97518 | // (uint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97519 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 97520 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97521 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97522 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M2_E32), |
| 97524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97525 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97526 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97531 | GIR_RootConstrainSelectedInstOperands, |
| 97532 | // GIR_Coverage, 59389, |
| 97533 | GIR_EraseRootFromParent_Done, |
| 97534 | // Label 6504: @248802 |
| 97535 | GIM_Reject, |
| 97536 | // Label 6426: @248803 |
| 97537 | GIM_Try, /*On fail goto*//*Label 6505*/ GIMT_Encode4(248860), // Rule ID 59020 // |
| 97538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 97539 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 97540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97541 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97542 | // (uint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 97543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 97544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M4_E64), |
| 97548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97550 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 97554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97555 | GIR_RootConstrainSelectedInstOperands, |
| 97556 | // GIR_Coverage, 59020, |
| 97557 | GIR_EraseRootFromParent_Done, |
| 97558 | // Label 6505: @248860 |
| 97559 | GIM_Try, /*On fail goto*//*Label 6506*/ GIMT_Encode4(248917), // Rule ID 59021 // |
| 97560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 97561 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 97562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97563 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97564 | // (uint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 97565 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 97566 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97567 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97568 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M4_E64), |
| 97570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97571 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97572 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 97576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97577 | GIR_RootConstrainSelectedInstOperands, |
| 97578 | // GIR_Coverage, 59021, |
| 97579 | GIR_EraseRootFromParent_Done, |
| 97580 | // Label 6506: @248917 |
| 97581 | GIM_Try, /*On fail goto*//*Label 6507*/ GIMT_Encode4(248971), // Rule ID 59204 // |
| 97582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 97583 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 97584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97586 | // (uint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_M2_E32:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97587 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 97588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97589 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M2_E32), |
| 97592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97593 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97594 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97598 | GIR_RootConstrainSelectedInstOperands, |
| 97599 | // GIR_Coverage, 59204, |
| 97600 | GIR_EraseRootFromParent_Done, |
| 97601 | // Label 6507: @248971 |
| 97602 | GIM_Try, /*On fail goto*//*Label 6508*/ GIMT_Encode4(249025), // Rule ID 59205 // |
| 97603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 97604 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 97605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97606 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97607 | // (uint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_M2_E32:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 97609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M2_E32), |
| 97613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97619 | GIR_RootConstrainSelectedInstOperands, |
| 97620 | // GIR_Coverage, 59205, |
| 97621 | GIR_EraseRootFromParent_Done, |
| 97622 | // Label 6508: @249025 |
| 97623 | GIM_Reject, |
| 97624 | // Label 6427: @249026 |
| 97625 | GIM_Try, /*On fail goto*//*Label 6509*/ GIMT_Encode4(249083), // Rule ID 58992 // |
| 97626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97627 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 97628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97629 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97630 | // (uint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97631 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 97632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97633 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M2_E16), |
| 97636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97638 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97643 | GIR_RootConstrainSelectedInstOperands, |
| 97644 | // GIR_Coverage, 58992, |
| 97645 | GIR_EraseRootFromParent_Done, |
| 97646 | // Label 6509: @249083 |
| 97647 | GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(249140), // Rule ID 58993 // |
| 97648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97649 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 97650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97652 | // (uint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 97654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M2_E16), |
| 97658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97660 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97665 | GIR_RootConstrainSelectedInstOperands, |
| 97666 | // GIR_Coverage, 58993, |
| 97667 | GIR_EraseRootFromParent_Done, |
| 97668 | // Label 6510: @249140 |
| 97669 | GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(249194), // Rule ID 59164 // |
| 97670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97671 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 97672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97673 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97674 | // (uint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_M1_E8:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 97675 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 97676 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97677 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97678 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M1_E8), |
| 97680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97681 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97686 | GIR_RootConstrainSelectedInstOperands, |
| 97687 | // GIR_Coverage, 59164, |
| 97688 | GIR_EraseRootFromParent_Done, |
| 97689 | // Label 6511: @249194 |
| 97690 | GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(249248), // Rule ID 59165 // |
| 97691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97692 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 97693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 97695 | // (uint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_M1_E8:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 97696 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 97697 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M1_E8), |
| 97701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97702 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97707 | GIR_RootConstrainSelectedInstOperands, |
| 97708 | // GIR_Coverage, 59165, |
| 97709 | GIR_EraseRootFromParent_Done, |
| 97710 | // Label 6512: @249248 |
| 97711 | GIM_Try, /*On fail goto*//*Label 6513*/ GIMT_Encode4(249305), // Rule ID 59372 // |
| 97712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97713 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 97714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97716 | // (uint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 97718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97719 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M2_E16), |
| 97722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97729 | GIR_RootConstrainSelectedInstOperands, |
| 97730 | // GIR_Coverage, 59372, |
| 97731 | GIR_EraseRootFromParent_Done, |
| 97732 | // Label 6513: @249305 |
| 97733 | GIM_Try, /*On fail goto*//*Label 6514*/ GIMT_Encode4(249362), // Rule ID 59373 // |
| 97734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 97735 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 97736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97737 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97738 | // (uint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97739 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 97740 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97741 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M2_E16), |
| 97744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97745 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97746 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97751 | GIR_RootConstrainSelectedInstOperands, |
| 97752 | // GIR_Coverage, 59373, |
| 97753 | GIR_EraseRootFromParent_Done, |
| 97754 | // Label 6514: @249362 |
| 97755 | GIM_Reject, |
| 97756 | // Label 6428: @249363 |
| 97757 | GIM_Try, /*On fail goto*//*Label 6515*/ GIMT_Encode4(249420), // Rule ID 59008 // |
| 97758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 97759 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 97760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97761 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97762 | // (uint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97763 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 97764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97765 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M4_E32), |
| 97768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97769 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97770 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97775 | GIR_RootConstrainSelectedInstOperands, |
| 97776 | // GIR_Coverage, 59008, |
| 97777 | GIR_EraseRootFromParent_Done, |
| 97778 | // Label 6515: @249420 |
| 97779 | GIM_Try, /*On fail goto*//*Label 6516*/ GIMT_Encode4(249477), // Rule ID 59009 // |
| 97780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 97781 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 97782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97784 | // (uint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97785 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 97786 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97787 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97788 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M4_E32), |
| 97790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97791 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97792 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97797 | GIR_RootConstrainSelectedInstOperands, |
| 97798 | // GIR_Coverage, 59009, |
| 97799 | GIR_EraseRootFromParent_Done, |
| 97800 | // Label 6516: @249477 |
| 97801 | GIM_Try, /*On fail goto*//*Label 6517*/ GIMT_Encode4(249531), // Rule ID 59188 // |
| 97802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 97803 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 97804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97806 | // (uint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_M2_E16:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 97808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M2_E16), |
| 97812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97818 | GIR_RootConstrainSelectedInstOperands, |
| 97819 | // GIR_Coverage, 59188, |
| 97820 | GIR_EraseRootFromParent_Done, |
| 97821 | // Label 6517: @249531 |
| 97822 | GIM_Try, /*On fail goto*//*Label 6518*/ GIMT_Encode4(249585), // Rule ID 59189 // |
| 97823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 97824 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 97825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 97827 | // (uint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_M2_E16:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 97828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 97829 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97830 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M2_E16), |
| 97833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97835 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97839 | GIR_RootConstrainSelectedInstOperands, |
| 97840 | // GIR_Coverage, 59189, |
| 97841 | GIR_EraseRootFromParent_Done, |
| 97842 | // Label 6518: @249585 |
| 97843 | GIM_Try, /*On fail goto*//*Label 6519*/ GIMT_Encode4(249642), // Rule ID 59392 // |
| 97844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0), |
| 97845 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 97846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97847 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97848 | // (uint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97849 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 97850 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97851 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M4_E32), |
| 97854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97855 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97856 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97861 | GIR_RootConstrainSelectedInstOperands, |
| 97862 | // GIR_Coverage, 59392, |
| 97863 | GIR_EraseRootFromParent_Done, |
| 97864 | // Label 6519: @249642 |
| 97865 | GIM_Try, /*On fail goto*//*Label 6520*/ GIMT_Encode4(249699), // Rule ID 59393 // |
| 97866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1), |
| 97867 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 97868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97870 | // (uint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFNCVT_F_XU_W_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97871 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 97872 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97873 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97874 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M4_E32), |
| 97876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97877 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97878 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97883 | GIR_RootConstrainSelectedInstOperands, |
| 97884 | // GIR_Coverage, 59393, |
| 97885 | GIR_EraseRootFromParent_Done, |
| 97886 | // Label 6520: @249699 |
| 97887 | GIM_Reject, |
| 97888 | // Label 6429: @249700 |
| 97889 | GIM_Try, /*On fail goto*//*Label 6521*/ GIMT_Encode4(249757), // Rule ID 59024 // |
| 97890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0), |
| 97891 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 97892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97893 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97894 | // (uint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 97895 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 97896 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97897 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M8_E64), |
| 97900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97901 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97902 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 97906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97907 | GIR_RootConstrainSelectedInstOperands, |
| 97908 | // GIR_Coverage, 59024, |
| 97909 | GIR_EraseRootFromParent_Done, |
| 97910 | // Label 6521: @249757 |
| 97911 | GIM_Try, /*On fail goto*//*Label 6522*/ GIMT_Encode4(249814), // Rule ID 59025 // |
| 97912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1), |
| 97913 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 97914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97915 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97916 | // (uint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVFCVT_F_XU_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8i64] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 97917 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 97918 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97919 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M8_E64), |
| 97922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97923 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97924 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 97928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97929 | GIR_RootConstrainSelectedInstOperands, |
| 97930 | // GIR_Coverage, 59025, |
| 97931 | GIR_EraseRootFromParent_Done, |
| 97932 | // Label 6522: @249814 |
| 97933 | GIM_Try, /*On fail goto*//*Label 6523*/ GIMT_Encode4(249868), // Rule ID 59208 // |
| 97934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0), |
| 97935 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 97936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97937 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97938 | // (uint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_M4_E32:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 97939 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 97940 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97941 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97942 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M4_E32), |
| 97944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97945 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97946 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97950 | GIR_RootConstrainSelectedInstOperands, |
| 97951 | // GIR_Coverage, 59208, |
| 97952 | GIR_EraseRootFromParent_Done, |
| 97953 | // Label 6523: @249868 |
| 97954 | GIM_Try, /*On fail goto*//*Label 6524*/ GIMT_Encode4(249922), // Rule ID 59209 // |
| 97955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1), |
| 97956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 97957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 97958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97959 | // (uint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVFWCVT_F_XU_V_M4_E32:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 97960 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 97961 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97962 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97963 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M4_E32), |
| 97965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97966 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97967 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 97970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97971 | GIR_RootConstrainSelectedInstOperands, |
| 97972 | // GIR_Coverage, 59209, |
| 97973 | GIR_EraseRootFromParent_Done, |
| 97974 | // Label 6524: @249922 |
| 97975 | GIM_Reject, |
| 97976 | // Label 6430: @249923 |
| 97977 | GIM_Try, /*On fail goto*//*Label 6525*/ GIMT_Encode4(249980), // Rule ID 58996 // |
| 97978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 97979 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 97980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97981 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 97982 | // (uint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 97983 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 97984 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 97985 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 97986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 97987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M4_E16), |
| 97988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 97989 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 97990 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 97991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 97992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 97993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 97994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 97995 | GIR_RootConstrainSelectedInstOperands, |
| 97996 | // GIR_Coverage, 58996, |
| 97997 | GIR_EraseRootFromParent_Done, |
| 97998 | // Label 6525: @249980 |
| 97999 | GIM_Try, /*On fail goto*//*Label 6526*/ GIMT_Encode4(250037), // Rule ID 58997 // |
| 98000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 98001 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 98002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98004 | // (uint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98005 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98006 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98007 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M4_E16), |
| 98010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98011 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98012 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98017 | GIR_RootConstrainSelectedInstOperands, |
| 98018 | // GIR_Coverage, 58997, |
| 98019 | GIR_EraseRootFromParent_Done, |
| 98020 | // Label 6526: @250037 |
| 98021 | GIM_Try, /*On fail goto*//*Label 6527*/ GIMT_Encode4(250091), // Rule ID 59168 // |
| 98022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 98023 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 98024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98025 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98026 | // (uint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_M2_E8:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 98027 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98028 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98029 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M2_E8), |
| 98032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98033 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98034 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98038 | GIR_RootConstrainSelectedInstOperands, |
| 98039 | // GIR_Coverage, 59168, |
| 98040 | GIR_EraseRootFromParent_Done, |
| 98041 | // Label 6527: @250091 |
| 98042 | GIM_Try, /*On fail goto*//*Label 6528*/ GIMT_Encode4(250145), // Rule ID 59169 // |
| 98043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 98044 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 98045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98046 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98047 | // (uint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_M2_E8:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 98048 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98049 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98050 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M2_E8), |
| 98053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98054 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98055 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98059 | GIR_RootConstrainSelectedInstOperands, |
| 98060 | // GIR_Coverage, 59169, |
| 98061 | GIR_EraseRootFromParent_Done, |
| 98062 | // Label 6528: @250145 |
| 98063 | GIM_Try, /*On fail goto*//*Label 6529*/ GIMT_Encode4(250202), // Rule ID 59376 // |
| 98064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 98065 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 98066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98067 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98068 | // (uint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M4_E16), |
| 98074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98076 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98081 | GIR_RootConstrainSelectedInstOperands, |
| 98082 | // GIR_Coverage, 59376, |
| 98083 | GIR_EraseRootFromParent_Done, |
| 98084 | // Label 6529: @250202 |
| 98085 | GIM_Try, /*On fail goto*//*Label 6530*/ GIMT_Encode4(250259), // Rule ID 59377 // |
| 98086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 98087 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 98088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98089 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98090 | // (uint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFNCVT_F_XU_W_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98091 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98092 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98093 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNCVT_F_XU_W_M4_E16), |
| 98096 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98097 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98098 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98103 | GIR_RootConstrainSelectedInstOperands, |
| 98104 | // GIR_Coverage, 59377, |
| 98105 | GIR_EraseRootFromParent_Done, |
| 98106 | // Label 6530: @250259 |
| 98107 | GIM_Reject, |
| 98108 | // Label 6431: @250260 |
| 98109 | GIM_Try, /*On fail goto*//*Label 6531*/ GIMT_Encode4(250317), // Rule ID 59012 // |
| 98110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 98111 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 98112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98114 | // (uint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 98115 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 98116 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98117 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M8_E32), |
| 98120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98121 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98122 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98127 | GIR_RootConstrainSelectedInstOperands, |
| 98128 | // GIR_Coverage, 59012, |
| 98129 | GIR_EraseRootFromParent_Done, |
| 98130 | // Label 6531: @250317 |
| 98131 | GIM_Try, /*On fail goto*//*Label 6532*/ GIMT_Encode4(250374), // Rule ID 59013 // |
| 98132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 98133 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 98134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98136 | // (uint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVFCVT_F_XU_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16i32] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 98137 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 98138 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98139 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98140 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M8_E32), |
| 98142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98143 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98144 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98149 | GIR_RootConstrainSelectedInstOperands, |
| 98150 | // GIR_Coverage, 59013, |
| 98151 | GIR_EraseRootFromParent_Done, |
| 98152 | // Label 6532: @250374 |
| 98153 | GIM_Try, /*On fail goto*//*Label 6533*/ GIMT_Encode4(250428), // Rule ID 59192 // |
| 98154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0), |
| 98155 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 98156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98157 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98158 | // (uint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_M4_E16:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98159 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 98160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M4_E16), |
| 98164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98166 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98170 | GIR_RootConstrainSelectedInstOperands, |
| 98171 | // GIR_Coverage, 59192, |
| 98172 | GIR_EraseRootFromParent_Done, |
| 98173 | // Label 6533: @250428 |
| 98174 | GIM_Try, /*On fail goto*//*Label 6534*/ GIMT_Encode4(250482), // Rule ID 59193 // |
| 98175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1), |
| 98176 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 98177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98179 | // (uint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVFWCVT_F_XU_V_M4_E16:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98180 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 98181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M4_E16), |
| 98185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98187 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98191 | GIR_RootConstrainSelectedInstOperands, |
| 98192 | // GIR_Coverage, 59193, |
| 98193 | GIR_EraseRootFromParent_Done, |
| 98194 | // Label 6534: @250482 |
| 98195 | GIM_Reject, |
| 98196 | // Label 6432: @250483 |
| 98197 | GIM_Try, /*On fail goto*//*Label 6535*/ GIMT_Encode4(250540), // Rule ID 59000 // |
| 98198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 98199 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 98200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98201 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98202 | // (uint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32i16] }:$rs1, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98203 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 98204 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98205 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M8_E16), |
| 98208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98209 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98210 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98215 | GIR_RootConstrainSelectedInstOperands, |
| 98216 | // GIR_Coverage, 59000, |
| 98217 | GIR_EraseRootFromParent_Done, |
| 98218 | // Label 6535: @250540 |
| 98219 | GIM_Try, /*On fail goto*//*Label 6536*/ GIMT_Encode4(250597), // Rule ID 59001 // |
| 98220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 98221 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 98222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98223 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98224 | // (uint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVFCVT_F_XU_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32i16] }:$rs1, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98225 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 98226 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98227 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFCVT_F_XU_V_M8_E16), |
| 98230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98231 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98232 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 98234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98237 | GIR_RootConstrainSelectedInstOperands, |
| 98238 | // GIR_Coverage, 59001, |
| 98239 | GIR_EraseRootFromParent_Done, |
| 98240 | // Label 6536: @250597 |
| 98241 | GIM_Try, /*On fail goto*//*Label 6537*/ GIMT_Encode4(250651), // Rule ID 59172 // |
| 98242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0), |
| 98243 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 98244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98245 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98246 | // (uint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_M4_E8:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 98247 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 98248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98249 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98250 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M4_E8), |
| 98252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98253 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98254 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98258 | GIR_RootConstrainSelectedInstOperands, |
| 98259 | // GIR_Coverage, 59172, |
| 98260 | GIR_EraseRootFromParent_Done, |
| 98261 | // Label 6537: @250651 |
| 98262 | GIM_Try, /*On fail goto*//*Label 6538*/ GIMT_Encode4(250705), // Rule ID 59173 // |
| 98263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1), |
| 98264 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 98265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98266 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98267 | // (uint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVFWCVT_F_XU_V_M4_E8:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 98268 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 98269 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFWCVT_F_XU_V_M4_E8), |
| 98273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98274 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98275 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98279 | GIR_RootConstrainSelectedInstOperands, |
| 98280 | // GIR_Coverage, 59173, |
| 98281 | GIR_EraseRootFromParent_Done, |
| 98282 | // Label 6538: @250705 |
| 98283 | GIM_Reject, |
| 98284 | // Label 6433: @250706 |
| 98285 | GIM_Reject, |
| 98286 | // Label 65: @250707 |
| 98287 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 6557*/ GIMT_Encode4(252677), |
| 98288 | /*GILLT_s16*//*Label 6539*/ GIMT_Encode4(250838), |
| 98289 | /*GILLT_s32*//*Label 6540*/ GIMT_Encode4(250902), |
| 98290 | /*GILLT_s64*//*Label 6541*/ GIMT_Encode4(250966), GIMT_Encode4(0), GIMT_Encode4(0), |
| 98291 | /*GILLT_nxv1s16*//*Label 6542*/ GIMT_Encode4(251057), |
| 98292 | /*GILLT_nxv1s32*//*Label 6543*/ GIMT_Encode4(251165), |
| 98293 | /*GILLT_nxv1s64*//*Label 6544*/ GIMT_Encode4(251273), GIMT_Encode4(0), GIMT_Encode4(0), |
| 98294 | /*GILLT_nxv2s16*//*Label 6545*/ GIMT_Encode4(251381), |
| 98295 | /*GILLT_nxv2s32*//*Label 6546*/ GIMT_Encode4(251489), |
| 98296 | /*GILLT_nxv2s64*//*Label 6547*/ GIMT_Encode4(251597), GIMT_Encode4(0), GIMT_Encode4(0), |
| 98297 | /*GILLT_nxv4s16*//*Label 6548*/ GIMT_Encode4(251705), |
| 98298 | /*GILLT_nxv4s32*//*Label 6549*/ GIMT_Encode4(251813), |
| 98299 | /*GILLT_nxv4s64*//*Label 6550*/ GIMT_Encode4(251921), GIMT_Encode4(0), GIMT_Encode4(0), |
| 98300 | /*GILLT_nxv8s16*//*Label 6551*/ GIMT_Encode4(252029), |
| 98301 | /*GILLT_nxv8s32*//*Label 6552*/ GIMT_Encode4(252137), |
| 98302 | /*GILLT_nxv8s64*//*Label 6553*/ GIMT_Encode4(252245), GIMT_Encode4(0), GIMT_Encode4(0), |
| 98303 | /*GILLT_nxv16s16*//*Label 6554*/ GIMT_Encode4(252353), |
| 98304 | /*GILLT_nxv16s32*//*Label 6555*/ GIMT_Encode4(252461), GIMT_Encode4(0), GIMT_Encode4(0), |
| 98305 | /*GILLT_nxv32s16*//*Label 6556*/ GIMT_Encode4(252569), |
| 98306 | // Label 6539: @250838 |
| 98307 | GIM_Try, /*On fail goto*//*Label 6558*/ GIMT_Encode4(250901), |
| 98308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 98309 | GIM_Try, /*On fail goto*//*Label 6559*/ GIMT_Encode4(250873), // Rule ID 2047 // |
| 98310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh), |
| 98311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 98312 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 98313 | // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FSGNJX_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs1) |
| 98314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_H), |
| 98315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98317 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98318 | GIR_RootConstrainSelectedInstOperands, |
| 98319 | // GIR_Coverage, 2047, |
| 98320 | GIR_EraseRootFromParent_Done, |
| 98321 | // Label 6559: @250873 |
| 98322 | GIM_Try, /*On fail goto*//*Label 6560*/ GIMT_Encode4(250900), // Rule ID 2079 // |
| 98323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx), |
| 98324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 98325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 98326 | // (fabs:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1) => (FSGNJX_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs1) |
| 98327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_H_INX), |
| 98328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98329 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98330 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98331 | GIR_RootConstrainSelectedInstOperands, |
| 98332 | // GIR_Coverage, 2079, |
| 98333 | GIR_EraseRootFromParent_Done, |
| 98334 | // Label 6560: @250900 |
| 98335 | GIM_Reject, |
| 98336 | // Label 6558: @250901 |
| 98337 | GIM_Reject, |
| 98338 | // Label 6540: @250902 |
| 98339 | GIM_Try, /*On fail goto*//*Label 6561*/ GIMT_Encode4(250965), |
| 98340 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 98341 | GIM_Try, /*On fail goto*//*Label 6562*/ GIMT_Encode4(250937), // Rule ID 1359 // |
| 98342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF), |
| 98343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 98344 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 98345 | // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSGNJX_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs1) |
| 98346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_S), |
| 98347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98348 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98349 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98350 | GIR_RootConstrainSelectedInstOperands, |
| 98351 | // GIR_Coverage, 1359, |
| 98352 | GIR_EraseRootFromParent_Done, |
| 98353 | // Label 6562: @250937 |
| 98354 | GIM_Try, /*On fail goto*//*Label 6563*/ GIMT_Encode4(250964), // Rule ID 1367 // |
| 98355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx), |
| 98356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 98357 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 98358 | // (fabs:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1) => (FSGNJX_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs1) |
| 98359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_S_INX), |
| 98360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98361 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98362 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98363 | GIR_RootConstrainSelectedInstOperands, |
| 98364 | // GIR_Coverage, 1367, |
| 98365 | GIR_EraseRootFromParent_Done, |
| 98366 | // Label 6563: @250964 |
| 98367 | GIM_Reject, |
| 98368 | // Label 6561: @250965 |
| 98369 | GIM_Reject, |
| 98370 | // Label 6541: @250966 |
| 98371 | GIM_Try, /*On fail goto*//*Label 6564*/ GIMT_Encode4(251056), |
| 98372 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 98373 | GIM_Try, /*On fail goto*//*Label 6565*/ GIMT_Encode4(251001), // Rule ID 1694 // |
| 98374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD), |
| 98375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 98376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 98377 | // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSGNJX_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1) |
| 98378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_D), |
| 98379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98380 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98381 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98382 | GIR_RootConstrainSelectedInstOperands, |
| 98383 | // GIR_Coverage, 1694, |
| 98384 | GIR_EraseRootFromParent_Done, |
| 98385 | // Label 6565: @251001 |
| 98386 | GIM_Try, /*On fail goto*//*Label 6566*/ GIMT_Encode4(251028), // Rule ID 1726 // |
| 98387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 98388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 98389 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 98390 | // (fabs:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1) => (FSGNJX_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1) |
| 98391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_D_INX), |
| 98392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98393 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98394 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98395 | GIR_RootConstrainSelectedInstOperands, |
| 98396 | // GIR_Coverage, 1726, |
| 98397 | GIR_EraseRootFromParent_Done, |
| 98398 | // Label 6566: @251028 |
| 98399 | GIM_Try, /*On fail goto*//*Label 6567*/ GIMT_Encode4(251055), // Rule ID 1747 // |
| 98400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32), |
| 98401 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 98402 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 98403 | // (fabs:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FSGNJX_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1) |
| 98404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJX_D_IN32X), |
| 98405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98406 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98407 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 98408 | GIR_RootConstrainSelectedInstOperands, |
| 98409 | // GIR_Coverage, 1747, |
| 98410 | GIR_EraseRootFromParent_Done, |
| 98411 | // Label 6567: @251055 |
| 98412 | GIM_Reject, |
| 98413 | // Label 6564: @251056 |
| 98414 | GIM_Reject, |
| 98415 | // Label 6542: @251057 |
| 98416 | GIM_Try, /*On fail goto*//*Label 6568*/ GIMT_Encode4(251164), |
| 98417 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 98418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98419 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98420 | GIM_Try, /*On fail goto*//*Label 6569*/ GIMT_Encode4(251118), // Rule ID 56864 // |
| 98421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 98422 | // (fabs:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs) => (PseudoVFSGNJX_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98423 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 98424 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98425 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_MF4_E16), |
| 98428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98429 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98430 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98431 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98435 | GIR_RootConstrainSelectedInstOperands, |
| 98436 | // GIR_Coverage, 56864, |
| 98437 | GIR_EraseRootFromParent_Done, |
| 98438 | // Label 6569: @251118 |
| 98439 | GIM_Try, /*On fail goto*//*Label 6570*/ GIMT_Encode4(251163), // Rule ID 56865 // |
| 98440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 98441 | // (fabs:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs) => (PseudoVFSGNJX_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98442 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 98443 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98444 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_MF4_E16), |
| 98447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98448 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98449 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98450 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98454 | GIR_RootConstrainSelectedInstOperands, |
| 98455 | // GIR_Coverage, 56865, |
| 98456 | GIR_EraseRootFromParent_Done, |
| 98457 | // Label 6570: @251163 |
| 98458 | GIM_Reject, |
| 98459 | // Label 6568: @251164 |
| 98460 | GIM_Reject, |
| 98461 | // Label 6543: @251165 |
| 98462 | GIM_Try, /*On fail goto*//*Label 6571*/ GIMT_Encode4(251272), |
| 98463 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 98464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98465 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98466 | GIM_Try, /*On fail goto*//*Label 6572*/ GIMT_Encode4(251226), // Rule ID 56904 // |
| 98467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 98468 | // (fabs:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs) => (PseudoVFSGNJX_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 98469 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 98470 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98471 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98472 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_MF2_E32), |
| 98474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98475 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98476 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98477 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98481 | GIR_RootConstrainSelectedInstOperands, |
| 98482 | // GIR_Coverage, 56904, |
| 98483 | GIR_EraseRootFromParent_Done, |
| 98484 | // Label 6572: @251226 |
| 98485 | GIM_Try, /*On fail goto*//*Label 6573*/ GIMT_Encode4(251271), // Rule ID 56905 // |
| 98486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 98487 | // (fabs:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs) => (PseudoVFSGNJX_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 98488 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 98489 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98490 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_MF2_E32), |
| 98493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98494 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98495 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98496 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98500 | GIR_RootConstrainSelectedInstOperands, |
| 98501 | // GIR_Coverage, 56905, |
| 98502 | GIR_EraseRootFromParent_Done, |
| 98503 | // Label 6573: @251271 |
| 98504 | GIM_Reject, |
| 98505 | // Label 6571: @251272 |
| 98506 | GIM_Reject, |
| 98507 | // Label 6544: @251273 |
| 98508 | GIM_Try, /*On fail goto*//*Label 6574*/ GIMT_Encode4(251380), |
| 98509 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 98510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98511 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98512 | GIM_Try, /*On fail goto*//*Label 6575*/ GIMT_Encode4(251334), // Rule ID 56964 // |
| 98513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 98514 | // (fabs:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs) => (PseudoVFSGNJX_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 98515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 98516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M1_E64), |
| 98520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98521 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98522 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98523 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98527 | GIR_RootConstrainSelectedInstOperands, |
| 98528 | // GIR_Coverage, 56964, |
| 98529 | GIR_EraseRootFromParent_Done, |
| 98530 | // Label 6575: @251334 |
| 98531 | GIM_Try, /*On fail goto*//*Label 6576*/ GIMT_Encode4(251379), // Rule ID 56965 // |
| 98532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 98533 | // (fabs:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs) => (PseudoVFSGNJX_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 98534 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 98535 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98536 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98537 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M1_E64), |
| 98539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98540 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98541 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98542 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98546 | GIR_RootConstrainSelectedInstOperands, |
| 98547 | // GIR_Coverage, 56965, |
| 98548 | GIR_EraseRootFromParent_Done, |
| 98549 | // Label 6576: @251379 |
| 98550 | GIM_Reject, |
| 98551 | // Label 6574: @251380 |
| 98552 | GIM_Reject, |
| 98553 | // Label 6545: @251381 |
| 98554 | GIM_Try, /*On fail goto*//*Label 6577*/ GIMT_Encode4(251488), |
| 98555 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 98556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98558 | GIM_Try, /*On fail goto*//*Label 6578*/ GIMT_Encode4(251442), // Rule ID 56884 // |
| 98559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 98560 | // (fabs:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs) => (PseudoVFSGNJX_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98561 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 98562 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98563 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98564 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_MF2_E16), |
| 98566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98567 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98568 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98569 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98573 | GIR_RootConstrainSelectedInstOperands, |
| 98574 | // GIR_Coverage, 56884, |
| 98575 | GIR_EraseRootFromParent_Done, |
| 98576 | // Label 6578: @251442 |
| 98577 | GIM_Try, /*On fail goto*//*Label 6579*/ GIMT_Encode4(251487), // Rule ID 56885 // |
| 98578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 98579 | // (fabs:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs) => (PseudoVFSGNJX_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98580 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 98581 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98582 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_MF2_E16), |
| 98585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98586 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98587 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98588 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98592 | GIR_RootConstrainSelectedInstOperands, |
| 98593 | // GIR_Coverage, 56885, |
| 98594 | GIR_EraseRootFromParent_Done, |
| 98595 | // Label 6579: @251487 |
| 98596 | GIM_Reject, |
| 98597 | // Label 6577: @251488 |
| 98598 | GIM_Reject, |
| 98599 | // Label 6546: @251489 |
| 98600 | GIM_Try, /*On fail goto*//*Label 6580*/ GIMT_Encode4(251596), |
| 98601 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 98602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98603 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98604 | GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(251550), // Rule ID 56944 // |
| 98605 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 98606 | // (fabs:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs) => (PseudoVFSGNJX_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 98607 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 98608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98610 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M1_E32), |
| 98612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98613 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98614 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98619 | GIR_RootConstrainSelectedInstOperands, |
| 98620 | // GIR_Coverage, 56944, |
| 98621 | GIR_EraseRootFromParent_Done, |
| 98622 | // Label 6581: @251550 |
| 98623 | GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(251595), // Rule ID 56945 // |
| 98624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 98625 | // (fabs:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs) => (PseudoVFSGNJX_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 98626 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 98627 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98628 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M1_E32), |
| 98631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98632 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98633 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98634 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98638 | GIR_RootConstrainSelectedInstOperands, |
| 98639 | // GIR_Coverage, 56945, |
| 98640 | GIR_EraseRootFromParent_Done, |
| 98641 | // Label 6582: @251595 |
| 98642 | GIM_Reject, |
| 98643 | // Label 6580: @251596 |
| 98644 | GIM_Reject, |
| 98645 | // Label 6547: @251597 |
| 98646 | GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(251704), |
| 98647 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 98648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98649 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98650 | GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(251658), // Rule ID 57104 // |
| 98651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 98652 | // (fabs:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs) => (PseudoVFSGNJX_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 98653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 98654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M2_E64), |
| 98658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98660 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98661 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98665 | GIR_RootConstrainSelectedInstOperands, |
| 98666 | // GIR_Coverage, 57104, |
| 98667 | GIR_EraseRootFromParent_Done, |
| 98668 | // Label 6584: @251658 |
| 98669 | GIM_Try, /*On fail goto*//*Label 6585*/ GIMT_Encode4(251703), // Rule ID 57105 // |
| 98670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 98671 | // (fabs:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs) => (PseudoVFSGNJX_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 98672 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 98673 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98674 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M2_E64), |
| 98677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98679 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98680 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98684 | GIR_RootConstrainSelectedInstOperands, |
| 98685 | // GIR_Coverage, 57105, |
| 98686 | GIR_EraseRootFromParent_Done, |
| 98687 | // Label 6585: @251703 |
| 98688 | GIM_Reject, |
| 98689 | // Label 6583: @251704 |
| 98690 | GIM_Reject, |
| 98691 | // Label 6548: @251705 |
| 98692 | GIM_Try, /*On fail goto*//*Label 6586*/ GIMT_Encode4(251812), |
| 98693 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 98694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98695 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 98696 | GIM_Try, /*On fail goto*//*Label 6587*/ GIMT_Encode4(251766), // Rule ID 56924 // |
| 98697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 98698 | // (fabs:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs) => (PseudoVFSGNJX_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98699 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 98700 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98701 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98702 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M1_E16), |
| 98704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98705 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98706 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98707 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98711 | GIR_RootConstrainSelectedInstOperands, |
| 98712 | // GIR_Coverage, 56924, |
| 98713 | GIR_EraseRootFromParent_Done, |
| 98714 | // Label 6587: @251766 |
| 98715 | GIM_Try, /*On fail goto*//*Label 6588*/ GIMT_Encode4(251811), // Rule ID 56925 // |
| 98716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 98717 | // (fabs:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs) => (PseudoVFSGNJX_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98718 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 98719 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98720 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M1_E16), |
| 98723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98725 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98726 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98730 | GIR_RootConstrainSelectedInstOperands, |
| 98731 | // GIR_Coverage, 56925, |
| 98732 | GIR_EraseRootFromParent_Done, |
| 98733 | // Label 6588: @251811 |
| 98734 | GIM_Reject, |
| 98735 | // Label 6586: @251812 |
| 98736 | GIM_Reject, |
| 98737 | // Label 6549: @251813 |
| 98738 | GIM_Try, /*On fail goto*//*Label 6589*/ GIMT_Encode4(251920), |
| 98739 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 98740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98741 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98742 | GIM_Try, /*On fail goto*//*Label 6590*/ GIMT_Encode4(251874), // Rule ID 57044 // |
| 98743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 98744 | // (fabs:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs) => (PseudoVFSGNJX_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 98745 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 98746 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98747 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98748 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M2_E32), |
| 98750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98751 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98752 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98753 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98757 | GIR_RootConstrainSelectedInstOperands, |
| 98758 | // GIR_Coverage, 57044, |
| 98759 | GIR_EraseRootFromParent_Done, |
| 98760 | // Label 6590: @251874 |
| 98761 | GIM_Try, /*On fail goto*//*Label 6591*/ GIMT_Encode4(251919), // Rule ID 57045 // |
| 98762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 98763 | // (fabs:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs) => (PseudoVFSGNJX_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 98764 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 98765 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M2_E32), |
| 98769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98771 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98772 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98776 | GIR_RootConstrainSelectedInstOperands, |
| 98777 | // GIR_Coverage, 57045, |
| 98778 | GIR_EraseRootFromParent_Done, |
| 98779 | // Label 6591: @251919 |
| 98780 | GIM_Reject, |
| 98781 | // Label 6589: @251920 |
| 98782 | GIM_Reject, |
| 98783 | // Label 6550: @251921 |
| 98784 | GIM_Try, /*On fail goto*//*Label 6592*/ GIMT_Encode4(252028), |
| 98785 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 98786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98787 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98788 | GIM_Try, /*On fail goto*//*Label 6593*/ GIMT_Encode4(251982), // Rule ID 57124 // |
| 98789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 98790 | // (fabs:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs) => (PseudoVFSGNJX_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 98791 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 98792 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98793 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98794 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M4_E64), |
| 98796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98797 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98798 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98799 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98803 | GIR_RootConstrainSelectedInstOperands, |
| 98804 | // GIR_Coverage, 57124, |
| 98805 | GIR_EraseRootFromParent_Done, |
| 98806 | // Label 6593: @251982 |
| 98807 | GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(252027), // Rule ID 57125 // |
| 98808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 98809 | // (fabs:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs) => (PseudoVFSGNJX_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 98810 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 98811 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98812 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98813 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M4_E64), |
| 98815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98816 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98817 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98818 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98822 | GIR_RootConstrainSelectedInstOperands, |
| 98823 | // GIR_Coverage, 57125, |
| 98824 | GIR_EraseRootFromParent_Done, |
| 98825 | // Label 6594: @252027 |
| 98826 | GIM_Reject, |
| 98827 | // Label 6592: @252028 |
| 98828 | GIM_Reject, |
| 98829 | // Label 6551: @252029 |
| 98830 | GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(252136), |
| 98831 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 98832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 98834 | GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(252090), // Rule ID 56984 // |
| 98835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 98836 | // (fabs:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs) => (PseudoVFSGNJX_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98837 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 98838 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98839 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M2_E16), |
| 98842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98843 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98844 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98845 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98849 | GIR_RootConstrainSelectedInstOperands, |
| 98850 | // GIR_Coverage, 56984, |
| 98851 | GIR_EraseRootFromParent_Done, |
| 98852 | // Label 6596: @252090 |
| 98853 | GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(252135), // Rule ID 56985 // |
| 98854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 98855 | // (fabs:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs) => (PseudoVFSGNJX_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98856 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 98857 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98858 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98859 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M2_E16), |
| 98861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98862 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98863 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98864 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98868 | GIR_RootConstrainSelectedInstOperands, |
| 98869 | // GIR_Coverage, 56985, |
| 98870 | GIR_EraseRootFromParent_Done, |
| 98871 | // Label 6597: @252135 |
| 98872 | GIM_Reject, |
| 98873 | // Label 6595: @252136 |
| 98874 | GIM_Reject, |
| 98875 | // Label 6552: @252137 |
| 98876 | GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(252244), |
| 98877 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 98878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98879 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98880 | GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(252198), // Rule ID 57064 // |
| 98881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 98882 | // (fabs:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs) => (PseudoVFSGNJX_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 98883 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 98884 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98885 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98886 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M4_E32), |
| 98888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98890 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98891 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98895 | GIR_RootConstrainSelectedInstOperands, |
| 98896 | // GIR_Coverage, 57064, |
| 98897 | GIR_EraseRootFromParent_Done, |
| 98898 | // Label 6599: @252198 |
| 98899 | GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(252243), // Rule ID 57065 // |
| 98900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 98901 | // (fabs:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs) => (PseudoVFSGNJX_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 98902 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 98903 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98904 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M4_E32), |
| 98907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98909 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98910 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 98913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98914 | GIR_RootConstrainSelectedInstOperands, |
| 98915 | // GIR_Coverage, 57065, |
| 98916 | GIR_EraseRootFromParent_Done, |
| 98917 | // Label 6600: @252243 |
| 98918 | GIM_Reject, |
| 98919 | // Label 6598: @252244 |
| 98920 | GIM_Reject, |
| 98921 | // Label 6553: @252245 |
| 98922 | GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(252352), |
| 98923 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 98924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98925 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 98926 | GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(252306), // Rule ID 57144 // |
| 98927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 98928 | // (fabs:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs) => (PseudoVFSGNJX_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 98929 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 98930 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98931 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M8_E64), |
| 98934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98935 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98936 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98937 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98941 | GIR_RootConstrainSelectedInstOperands, |
| 98942 | // GIR_Coverage, 57144, |
| 98943 | GIR_EraseRootFromParent_Done, |
| 98944 | // Label 6602: @252306 |
| 98945 | GIM_Try, /*On fail goto*//*Label 6603*/ GIMT_Encode4(252351), // Rule ID 57145 // |
| 98946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 98947 | // (fabs:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs) => (PseudoVFSGNJX_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 98948 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 98949 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98950 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M8_E64), |
| 98953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98954 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98955 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98956 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 98959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98960 | GIR_RootConstrainSelectedInstOperands, |
| 98961 | // GIR_Coverage, 57145, |
| 98962 | GIR_EraseRootFromParent_Done, |
| 98963 | // Label 6603: @252351 |
| 98964 | GIM_Reject, |
| 98965 | // Label 6601: @252352 |
| 98966 | GIM_Reject, |
| 98967 | // Label 6554: @252353 |
| 98968 | GIM_Try, /*On fail goto*//*Label 6604*/ GIMT_Encode4(252460), |
| 98969 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 98970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98971 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 98972 | GIM_Try, /*On fail goto*//*Label 6605*/ GIMT_Encode4(252414), // Rule ID 57004 // |
| 98973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 98974 | // (fabs:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs) => (PseudoVFSGNJX_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 98975 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98976 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98977 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M4_E16), |
| 98980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 98981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 98982 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98983 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 98984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 98985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 98986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 98987 | GIR_RootConstrainSelectedInstOperands, |
| 98988 | // GIR_Coverage, 57004, |
| 98989 | GIR_EraseRootFromParent_Done, |
| 98990 | // Label 6605: @252414 |
| 98991 | GIM_Try, /*On fail goto*//*Label 6606*/ GIMT_Encode4(252459), // Rule ID 57005 // |
| 98992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 98993 | // (fabs:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs) => (PseudoVFSGNJX_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 98994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 98995 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 98996 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 98997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 98998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M4_E16), |
| 98999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99000 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99001 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99002 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99006 | GIR_RootConstrainSelectedInstOperands, |
| 99007 | // GIR_Coverage, 57005, |
| 99008 | GIR_EraseRootFromParent_Done, |
| 99009 | // Label 6606: @252459 |
| 99010 | GIM_Reject, |
| 99011 | // Label 6604: @252460 |
| 99012 | GIM_Reject, |
| 99013 | // Label 6555: @252461 |
| 99014 | GIM_Try, /*On fail goto*//*Label 6607*/ GIMT_Encode4(252568), |
| 99015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 99016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 99017 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 99018 | GIM_Try, /*On fail goto*//*Label 6608*/ GIMT_Encode4(252522), // Rule ID 57084 // |
| 99019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 99020 | // (fabs:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs) => (PseudoVFSGNJX_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 99021 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 99022 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99023 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99024 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M8_E32), |
| 99026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99027 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99028 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99029 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 99032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99033 | GIR_RootConstrainSelectedInstOperands, |
| 99034 | // GIR_Coverage, 57084, |
| 99035 | GIR_EraseRootFromParent_Done, |
| 99036 | // Label 6608: @252522 |
| 99037 | GIM_Try, /*On fail goto*//*Label 6609*/ GIMT_Encode4(252567), // Rule ID 57085 // |
| 99038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 99039 | // (fabs:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs) => (PseudoVFSGNJX_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 99040 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 99041 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99042 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M8_E32), |
| 99045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99046 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99047 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99048 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 99051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99052 | GIR_RootConstrainSelectedInstOperands, |
| 99053 | // GIR_Coverage, 57085, |
| 99054 | GIR_EraseRootFromParent_Done, |
| 99055 | // Label 6609: @252567 |
| 99056 | GIM_Reject, |
| 99057 | // Label 6607: @252568 |
| 99058 | GIM_Reject, |
| 99059 | // Label 6556: @252569 |
| 99060 | GIM_Try, /*On fail goto*//*Label 6610*/ GIMT_Encode4(252676), |
| 99061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 99062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 99063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 99064 | GIM_Try, /*On fail goto*//*Label 6611*/ GIMT_Encode4(252630), // Rule ID 57024 // |
| 99065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 99066 | // (fabs:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs) => (PseudoVFSGNJX_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 99067 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 99068 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99069 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99070 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M8_E16), |
| 99072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99073 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99074 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99075 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99079 | GIR_RootConstrainSelectedInstOperands, |
| 99080 | // GIR_Coverage, 57024, |
| 99081 | GIR_EraseRootFromParent_Done, |
| 99082 | // Label 6611: @252630 |
| 99083 | GIM_Try, /*On fail goto*//*Label 6612*/ GIMT_Encode4(252675), // Rule ID 57025 // |
| 99084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 99085 | // (fabs:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs) => (PseudoVFSGNJX_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 99086 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 99087 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99088 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJX_VV_M8_E16), |
| 99091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99092 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99093 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99094 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 99095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99098 | GIR_RootConstrainSelectedInstOperands, |
| 99099 | // GIR_Coverage, 57025, |
| 99100 | GIR_EraseRootFromParent_Done, |
| 99101 | // Label 6612: @252675 |
| 99102 | GIM_Reject, |
| 99103 | // Label 6610: @252676 |
| 99104 | GIM_Reject, |
| 99105 | // Label 6557: @252677 |
| 99106 | GIM_Reject, |
| 99107 | // Label 66: @252678 |
| 99108 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 6631*/ GIMT_Encode4(258326), |
| 99109 | /*GILLT_s16*//*Label 6613*/ GIMT_Encode4(252809), |
| 99110 | /*GILLT_s32*//*Label 6614*/ GIMT_Encode4(253383), |
| 99111 | /*GILLT_s64*//*Label 6615*/ GIMT_Encode4(253957), GIMT_Encode4(0), GIMT_Encode4(0), |
| 99112 | /*GILLT_nxv1s16*//*Label 6616*/ GIMT_Encode4(254561), |
| 99113 | /*GILLT_nxv1s32*//*Label 6617*/ GIMT_Encode4(254812), |
| 99114 | /*GILLT_nxv1s64*//*Label 6618*/ GIMT_Encode4(255063), GIMT_Encode4(0), GIMT_Encode4(0), |
| 99115 | /*GILLT_nxv2s16*//*Label 6619*/ GIMT_Encode4(255314), |
| 99116 | /*GILLT_nxv2s32*//*Label 6620*/ GIMT_Encode4(255565), |
| 99117 | /*GILLT_nxv2s64*//*Label 6621*/ GIMT_Encode4(255816), GIMT_Encode4(0), GIMT_Encode4(0), |
| 99118 | /*GILLT_nxv4s16*//*Label 6622*/ GIMT_Encode4(256067), |
| 99119 | /*GILLT_nxv4s32*//*Label 6623*/ GIMT_Encode4(256318), |
| 99120 | /*GILLT_nxv4s64*//*Label 6624*/ GIMT_Encode4(256569), GIMT_Encode4(0), GIMT_Encode4(0), |
| 99121 | /*GILLT_nxv8s16*//*Label 6625*/ GIMT_Encode4(256820), |
| 99122 | /*GILLT_nxv8s32*//*Label 6626*/ GIMT_Encode4(257071), |
| 99123 | /*GILLT_nxv8s64*//*Label 6627*/ GIMT_Encode4(257322), GIMT_Encode4(0), GIMT_Encode4(0), |
| 99124 | /*GILLT_nxv16s16*//*Label 6628*/ GIMT_Encode4(257573), |
| 99125 | /*GILLT_nxv16s32*//*Label 6629*/ GIMT_Encode4(257824), GIMT_Encode4(0), GIMT_Encode4(0), |
| 99126 | /*GILLT_nxv32s16*//*Label 6630*/ GIMT_Encode4(258075), |
| 99127 | // Label 6613: @252809 |
| 99128 | GIM_Try, /*On fail goto*//*Label 6632*/ GIMT_Encode4(253382), |
| 99129 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 99130 | GIM_Try, /*On fail goto*//*Label 6633*/ GIMT_Encode4(252847), // Rule ID 2050 // |
| 99131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh), |
| 99132 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99134 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99135 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99136 | // (fcopysign:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSGNJ_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 99137 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H), |
| 99138 | GIR_RootConstrainSelectedInstOperands, |
| 99139 | // GIR_Coverage, 2050, |
| 99140 | GIR_Done, |
| 99141 | // Label 6633: @252847 |
| 99142 | GIM_Try, /*On fail goto*//*Label 6634*/ GIMT_Encode4(252903), // Rule ID 2052 // |
| 99143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 99144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99146 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99147 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99148 | // (fcopysign:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSGNJ_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_S:{ *:[bf16] } ?:{ *:[f32] }:$rs2, 7:{ *:[i64] })) |
| 99149 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99150 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 99151 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99152 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99153 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99154 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H), |
| 99156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99157 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99159 | GIR_RootConstrainSelectedInstOperands, |
| 99160 | // GIR_Coverage, 2052, |
| 99161 | GIR_EraseRootFromParent_Done, |
| 99162 | // Label 6634: @252903 |
| 99163 | GIM_Try, /*On fail goto*//*Label 6635*/ GIMT_Encode4(252959), // Rule ID 2053 // |
| 99164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 99165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99168 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99169 | // (fcopysign:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSGNJ_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_S:{ *:[bf16] } ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })) |
| 99170 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99171 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S), |
| 99172 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99173 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99174 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H), |
| 99177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99178 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99179 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99180 | GIR_RootConstrainSelectedInstOperands, |
| 99181 | // GIR_Coverage, 2053, |
| 99182 | GIR_EraseRootFromParent_Done, |
| 99183 | // Label 6635: @252959 |
| 99184 | GIM_Try, /*On fail goto*//*Label 6636*/ GIMT_Encode4(252989), // Rule ID 2082 // |
| 99185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx), |
| 99186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99190 | // (fcopysign:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSGNJ_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 99191 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H_INX), |
| 99192 | GIR_RootConstrainSelectedInstOperands, |
| 99193 | // GIR_Coverage, 2082, |
| 99194 | GIR_Done, |
| 99195 | // Label 6636: @252989 |
| 99196 | GIM_Try, /*On fail goto*//*Label 6637*/ GIMT_Encode4(253045), // Rule ID 2084 // |
| 99197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 99198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99202 | // (fcopysign:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSGNJ_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_S_INX:{ *:[f16] } ?:{ *:[f32] }:$rs2, 7:{ *:[i64] })) |
| 99203 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99204 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 99205 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99206 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99207 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H_INX), |
| 99210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99211 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99212 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99213 | GIR_RootConstrainSelectedInstOperands, |
| 99214 | // GIR_Coverage, 2084, |
| 99215 | GIR_EraseRootFromParent_Done, |
| 99216 | // Label 6637: @253045 |
| 99217 | GIM_Try, /*On fail goto*//*Label 6638*/ GIMT_Encode4(253101), // Rule ID 2085 // |
| 99218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 99219 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99221 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99222 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99223 | // (fcopysign:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSGNJ_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_S_INX:{ *:[f16] } ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })) |
| 99224 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99225 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_S_INX), |
| 99226 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99227 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99228 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H_INX), |
| 99231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99232 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99233 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99234 | GIR_RootConstrainSelectedInstOperands, |
| 99235 | // GIR_Coverage, 2085, |
| 99236 | GIR_EraseRootFromParent_Done, |
| 99237 | // Label 6638: @253101 |
| 99238 | GIM_Try, /*On fail goto*//*Label 6639*/ GIMT_Encode4(253157), // Rule ID 2350 // |
| 99239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode0), |
| 99240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99242 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99243 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99244 | // (fcopysign:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSGNJ_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_D:{ *:[bf16] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })) |
| 99245 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99246 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D), |
| 99247 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99248 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99249 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99250 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H), |
| 99252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99253 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99254 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99255 | GIR_RootConstrainSelectedInstOperands, |
| 99256 | // GIR_Coverage, 2350, |
| 99257 | GIR_EraseRootFromParent_Done, |
| 99258 | // Label 6639: @253157 |
| 99259 | GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(253213), // Rule ID 2351 // |
| 99260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode1), |
| 99261 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99263 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99265 | // (fcopysign:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSGNJ_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_D:{ *:[bf16] } ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })) |
| 99266 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99267 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D), |
| 99268 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99269 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99270 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H), |
| 99273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99274 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99276 | GIR_RootConstrainSelectedInstOperands, |
| 99277 | // GIR_Coverage, 2351, |
| 99278 | GIR_EraseRootFromParent_Done, |
| 99279 | // Label 6640: @253213 |
| 99280 | GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(253269), // Rule ID 2362 // |
| 99281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode0), |
| 99282 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99284 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99286 | // (fcopysign:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSGNJ_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_D_IN32X:{ *:[f16] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })) |
| 99287 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99288 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D_IN32X), |
| 99289 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99290 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99291 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H_INX), |
| 99294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99296 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99297 | GIR_RootConstrainSelectedInstOperands, |
| 99298 | // GIR_Coverage, 2362, |
| 99299 | GIR_EraseRootFromParent_Done, |
| 99300 | // Label 6641: @253269 |
| 99301 | GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(253325), // Rule ID 2363 // |
| 99302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode1), |
| 99303 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99305 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99306 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99307 | // (fcopysign:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSGNJ_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_D_IN32X:{ *:[f16] } ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })) |
| 99308 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99309 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D_IN32X), |
| 99310 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99311 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99312 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H_INX), |
| 99315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99317 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99318 | GIR_RootConstrainSelectedInstOperands, |
| 99319 | // GIR_Coverage, 2363, |
| 99320 | GIR_EraseRootFromParent_Done, |
| 99321 | // Label 6642: @253325 |
| 99322 | GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(253381), // Rule ID 2370 // |
| 99323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV64_HwMode0), |
| 99324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99326 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99327 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99328 | // (fcopysign:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FSGNJ_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, (FCVT_H_D_INX:{ *:[f16] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })) |
| 99329 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 99330 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_H_D_INX), |
| 99331 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99332 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99333 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99334 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_H_INX), |
| 99336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99337 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99339 | GIR_RootConstrainSelectedInstOperands, |
| 99340 | // GIR_Coverage, 2370, |
| 99341 | GIR_EraseRootFromParent_Done, |
| 99342 | // Label 6643: @253381 |
| 99343 | GIM_Reject, |
| 99344 | // Label 6632: @253382 |
| 99345 | GIM_Reject, |
| 99346 | // Label 6614: @253383 |
| 99347 | GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(253956), |
| 99348 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 99349 | GIM_Try, /*On fail goto*//*Label 6645*/ GIMT_Encode4(253421), // Rule ID 1370 // |
| 99350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF), |
| 99351 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99353 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99354 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99355 | // (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 99356 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S), |
| 99357 | GIR_RootConstrainSelectedInstOperands, |
| 99358 | // GIR_Coverage, 1370, |
| 99359 | GIR_Done, |
| 99360 | // Label 6645: @253421 |
| 99361 | GIM_Try, /*On fail goto*//*Label 6646*/ GIMT_Encode4(253451), // Rule ID 1371 // |
| 99362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx), |
| 99363 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99365 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99366 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99367 | // (fcopysign:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSGNJ_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 99368 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S_INX), |
| 99369 | GIR_RootConstrainSelectedInstOperands, |
| 99370 | // GIR_Coverage, 1371, |
| 99371 | GIR_Done, |
| 99372 | // Label 6646: @253451 |
| 99373 | GIM_Try, /*On fail goto*//*Label 6647*/ GIMT_Encode4(253507), // Rule ID 1701 // |
| 99374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 99375 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99377 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99378 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99379 | // (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })) |
| 99380 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99381 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D), |
| 99382 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99383 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99384 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S), |
| 99387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99388 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99390 | GIR_RootConstrainSelectedInstOperands, |
| 99391 | // GIR_Coverage, 1701, |
| 99392 | GIR_EraseRootFromParent_Done, |
| 99393 | // Label 6647: @253507 |
| 99394 | GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(253563), // Rule ID 1702 // |
| 99395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 99396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99398 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99399 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99400 | // (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })) |
| 99401 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99402 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D), |
| 99403 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99404 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99405 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99406 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S), |
| 99408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99409 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99410 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99411 | GIR_RootConstrainSelectedInstOperands, |
| 99412 | // GIR_Coverage, 1702, |
| 99413 | GIR_EraseRootFromParent_Done, |
| 99414 | // Label 6648: @253563 |
| 99415 | GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(253619), // Rule ID 1731 // |
| 99416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 99417 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99419 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99420 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99421 | // (fcopysign:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FSGNJ_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D_INX:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })) |
| 99422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D_INX), |
| 99424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99425 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99426 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S_INX), |
| 99429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99430 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99431 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99432 | GIR_RootConstrainSelectedInstOperands, |
| 99433 | // GIR_Coverage, 1731, |
| 99434 | GIR_EraseRootFromParent_Done, |
| 99435 | // Label 6649: @253619 |
| 99436 | GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(253675), // Rule ID 1753 // |
| 99437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 99438 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99440 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99442 | // (fcopysign:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSGNJ_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D_IN32X:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })) |
| 99443 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99444 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D_IN32X), |
| 99445 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99446 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99447 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S_INX), |
| 99450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99451 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99452 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99453 | GIR_RootConstrainSelectedInstOperands, |
| 99454 | // GIR_Coverage, 1753, |
| 99455 | GIR_EraseRootFromParent_Done, |
| 99456 | // Label 6650: @253675 |
| 99457 | GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(253731), // Rule ID 1754 // |
| 99458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 99459 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99461 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99462 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99463 | // (fcopysign:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSGNJ_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D_IN32X:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })) |
| 99464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_D_IN32X), |
| 99466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99467 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99468 | GIR_AddImm8, /*InsnID*/1, /*Imm*/7, |
| 99469 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S_INX), |
| 99471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99472 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99473 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99474 | GIR_RootConstrainSelectedInstOperands, |
| 99475 | // GIR_Coverage, 1754, |
| 99476 | GIR_EraseRootFromParent_Done, |
| 99477 | // Label 6651: @253731 |
| 99478 | GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(253787), // Rule ID 2220 // |
| 99479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode0), |
| 99480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99484 | // (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs2, 0:{ *:[i64] })) |
| 99485 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99486 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 99487 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99488 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99489 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S), |
| 99492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99493 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99494 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99495 | GIR_RootConstrainSelectedInstOperands, |
| 99496 | // GIR_Coverage, 2220, |
| 99497 | GIR_EraseRootFromParent_Done, |
| 99498 | // Label 6652: @253787 |
| 99499 | GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(253843), // Rule ID 2221 // |
| 99500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_HwMode1), |
| 99501 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99503 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99504 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99505 | // (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs2, 0:{ *:[i32] })) |
| 99506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99507 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 99508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99509 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99510 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S), |
| 99513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99514 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99515 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99516 | GIR_RootConstrainSelectedInstOperands, |
| 99517 | // GIR_Coverage, 2221, |
| 99518 | GIR_EraseRootFromParent_Done, |
| 99519 | // Label 6653: @253843 |
| 99520 | GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(253899), // Rule ID 2236 // |
| 99521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode0), |
| 99522 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99524 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99525 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99526 | // (fcopysign:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSGNJ_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs2, 0:{ *:[i64] })) |
| 99527 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 99529 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99530 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99531 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S_INX), |
| 99534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99535 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99536 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99537 | GIR_RootConstrainSelectedInstOperands, |
| 99538 | // GIR_Coverage, 2236, |
| 99539 | GIR_EraseRootFromParent_Done, |
| 99540 | // Label 6654: @253899 |
| 99541 | GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(253955), // Rule ID 2237 // |
| 99542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_HwMode1), |
| 99543 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99546 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99547 | // (fcopysign:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSGNJ_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs2, 0:{ *:[i32] })) |
| 99548 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99549 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 99550 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99551 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99552 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_S_INX), |
| 99555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99556 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99557 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99558 | GIR_RootConstrainSelectedInstOperands, |
| 99559 | // GIR_Coverage, 2237, |
| 99560 | GIR_EraseRootFromParent_Done, |
| 99561 | // Label 6655: @253955 |
| 99562 | GIM_Reject, |
| 99563 | // Label 6644: @253956 |
| 99564 | GIM_Reject, |
| 99565 | // Label 6615: @253957 |
| 99566 | GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(254560), |
| 99567 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 99568 | GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(253995), // Rule ID 1697 // |
| 99569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD), |
| 99570 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99572 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99574 | // (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 99575 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D), |
| 99576 | GIR_RootConstrainSelectedInstOperands, |
| 99577 | // GIR_Coverage, 1697, |
| 99578 | GIR_Done, |
| 99579 | // Label 6657: @253995 |
| 99580 | GIM_Try, /*On fail goto*//*Label 6658*/ GIMT_Encode4(254051), // Rule ID 1699 // |
| 99581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 99582 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99586 | // (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_S:{ *:[f64] } ?:{ *:[f32] }:$rs2, 0:{ *:[i64] })) |
| 99587 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S), |
| 99589 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99590 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99591 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D), |
| 99594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99595 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99597 | GIR_RootConstrainSelectedInstOperands, |
| 99598 | // GIR_Coverage, 1699, |
| 99599 | GIR_EraseRootFromParent_Done, |
| 99600 | // Label 6658: @254051 |
| 99601 | GIM_Try, /*On fail goto*//*Label 6659*/ GIMT_Encode4(254107), // Rule ID 1700 // |
| 99602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 99603 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99605 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 99607 | // (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_S:{ *:[f64] } ?:{ *:[f32] }:$rs2, 0:{ *:[i32] })) |
| 99608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S), |
| 99610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99611 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99612 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99613 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D), |
| 99615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99616 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99618 | GIR_RootConstrainSelectedInstOperands, |
| 99619 | // GIR_Coverage, 1700, |
| 99620 | GIR_EraseRootFromParent_Done, |
| 99621 | // Label 6659: @254107 |
| 99622 | GIM_Try, /*On fail goto*//*Label 6660*/ GIMT_Encode4(254137), // Rule ID 1728 // |
| 99623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 99624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99625 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99626 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99627 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99628 | // (fcopysign:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FSGNJ_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 99629 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_INX), |
| 99630 | GIR_RootConstrainSelectedInstOperands, |
| 99631 | // GIR_Coverage, 1728, |
| 99632 | GIR_Done, |
| 99633 | // Label 6660: @254137 |
| 99634 | GIM_Try, /*On fail goto*//*Label 6661*/ GIMT_Encode4(254193), // Rule ID 1730 // |
| 99635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 99636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99638 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99639 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99640 | // (fcopysign:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSGNJ_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs2, 0:{ *:[i64] })) |
| 99641 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99642 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S_INX), |
| 99643 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99644 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99645 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_INX), |
| 99648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99649 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99650 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99651 | GIR_RootConstrainSelectedInstOperands, |
| 99652 | // GIR_Coverage, 1730, |
| 99653 | GIR_EraseRootFromParent_Done, |
| 99654 | // Label 6661: @254193 |
| 99655 | GIM_Try, /*On fail goto*//*Label 6662*/ GIMT_Encode4(254223), // Rule ID 1750 // |
| 99656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32), |
| 99657 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99660 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99661 | // (fcopysign:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSGNJ_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 99662 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_IN32X), |
| 99663 | GIR_RootConstrainSelectedInstOperands, |
| 99664 | // GIR_Coverage, 1750, |
| 99665 | GIR_Done, |
| 99666 | // Label 6662: @254223 |
| 99667 | GIM_Try, /*On fail goto*//*Label 6663*/ GIMT_Encode4(254279), // Rule ID 1752 // |
| 99668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 99669 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 99670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99672 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 99673 | // (fcopysign:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSGNJ_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_S_INX:{ *:[f64] } ?:{ *:[f32] }:$rs2, 0:{ *:[i64] })) |
| 99674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_S_INX), |
| 99676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99677 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99678 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_IN32X), |
| 99681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99683 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99684 | GIR_RootConstrainSelectedInstOperands, |
| 99685 | // GIR_Coverage, 1752, |
| 99686 | GIR_EraseRootFromParent_Done, |
| 99687 | // Label 6663: @254279 |
| 99688 | GIM_Try, /*On fail goto*//*Label 6664*/ GIMT_Encode4(254335), // Rule ID 2352 // |
| 99689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode0), |
| 99690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99694 | // (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_H:{ *:[f64] } ?:{ *:[f16] }:$rs2, 0:{ *:[i64] })) |
| 99695 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99696 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H), |
| 99697 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99698 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99699 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D), |
| 99702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99704 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99705 | GIR_RootConstrainSelectedInstOperands, |
| 99706 | // GIR_Coverage, 2352, |
| 99707 | GIR_EraseRootFromParent_Done, |
| 99708 | // Label 6664: @254335 |
| 99709 | GIM_Try, /*On fail goto*//*Label 6665*/ GIMT_Encode4(254391), // Rule ID 2353 // |
| 99710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode1), |
| 99711 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99713 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 99714 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 99715 | // (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_H:{ *:[f64] } ?:{ *:[f16] }:$rs2, 0:{ *:[i32] })) |
| 99716 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99717 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H), |
| 99718 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99719 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99720 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D), |
| 99723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99725 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99726 | GIR_RootConstrainSelectedInstOperands, |
| 99727 | // GIR_Coverage, 2353, |
| 99728 | GIR_EraseRootFromParent_Done, |
| 99729 | // Label 6665: @254391 |
| 99730 | GIM_Try, /*On fail goto*//*Label 6666*/ GIMT_Encode4(254447), // Rule ID 2364 // |
| 99731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode0), |
| 99732 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99735 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99736 | // (fcopysign:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSGNJ_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_H_IN32X:{ *:[f64] } ?:{ *:[f16] }:$rs2, 0:{ *:[i64] })) |
| 99737 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99738 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H_IN32X), |
| 99739 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99740 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99741 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_IN32X), |
| 99744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99745 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99746 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99747 | GIR_RootConstrainSelectedInstOperands, |
| 99748 | // GIR_Coverage, 2364, |
| 99749 | GIR_EraseRootFromParent_Done, |
| 99750 | // Label 6666: @254447 |
| 99751 | GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(254503), // Rule ID 2365 // |
| 99752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode1), |
| 99753 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99755 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 99756 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99757 | // (fcopysign:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSGNJ_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_H_IN32X:{ *:[f64] } ?:{ *:[f16] }:$rs2, 0:{ *:[i32] })) |
| 99758 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 99759 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H_IN32X), |
| 99760 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99761 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99762 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_IN32X), |
| 99765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99768 | GIR_RootConstrainSelectedInstOperands, |
| 99769 | // GIR_Coverage, 2365, |
| 99770 | GIR_EraseRootFromParent_Done, |
| 99771 | // Label 6667: @254503 |
| 99772 | GIM_Try, /*On fail goto*//*Label 6668*/ GIMT_Encode4(254559), // Rule ID 2371 // |
| 99773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV64_HwMode0), |
| 99774 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 99777 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 99778 | // (fcopysign:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSGNJ_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs2, 0:{ *:[i64] })) |
| 99779 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 99780 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_D_H_INX), |
| 99781 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99782 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs2 |
| 99783 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 99784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSGNJ_D_INX), |
| 99786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99787 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99788 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99789 | GIR_RootConstrainSelectedInstOperands, |
| 99790 | // GIR_Coverage, 2371, |
| 99791 | GIR_EraseRootFromParent_Done, |
| 99792 | // Label 6668: @254559 |
| 99793 | GIM_Reject, |
| 99794 | // Label 6656: @254560 |
| 99795 | GIM_Reject, |
| 99796 | // Label 6616: @254561 |
| 99797 | GIM_Try, /*On fail goto*//*Label 6669*/ GIMT_Encode4(254811), |
| 99798 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 99799 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 99800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99801 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99802 | GIM_Try, /*On fail goto*//*Label 6670*/ GIMT_Encode4(254646), // Rule ID 56874 // |
| 99803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 99804 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99805 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 99806 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 99807 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99808 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99809 | // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFSGNJN_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 99810 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 99811 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99812 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99813 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF4_E16), |
| 99815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99816 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99817 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 99819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99822 | GIR_RootConstrainSelectedInstOperands, |
| 99823 | // GIR_Coverage, 56874, |
| 99824 | GIR_EraseRootFromParent_Done, |
| 99825 | // Label 6670: @254646 |
| 99826 | GIM_Try, /*On fail goto*//*Label 6671*/ GIMT_Encode4(254712), // Rule ID 56875 // |
| 99827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 99828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 99830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 99831 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99832 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99833 | // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFSGNJN_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 99834 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 99835 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99836 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF4_E16), |
| 99839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99840 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99841 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99842 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 99843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99846 | GIR_RootConstrainSelectedInstOperands, |
| 99847 | // GIR_Coverage, 56875, |
| 99848 | GIR_EraseRootFromParent_Done, |
| 99849 | // Label 6671: @254712 |
| 99850 | GIM_Try, /*On fail goto*//*Label 6672*/ GIMT_Encode4(254761), // Rule ID 56868 // |
| 99851 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 99852 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99853 | // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSGNJ_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 99854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 99855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99857 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_MF4_E16), |
| 99859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99860 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99861 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99862 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 99863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99866 | GIR_RootConstrainSelectedInstOperands, |
| 99867 | // GIR_Coverage, 56868, |
| 99868 | GIR_EraseRootFromParent_Done, |
| 99869 | // Label 6672: @254761 |
| 99870 | GIM_Try, /*On fail goto*//*Label 6673*/ GIMT_Encode4(254810), // Rule ID 56869 // |
| 99871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 99872 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99873 | // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSGNJ_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 99874 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 99875 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99876 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_MF4_E16), |
| 99879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99881 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99882 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 99883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 99885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99886 | GIR_RootConstrainSelectedInstOperands, |
| 99887 | // GIR_Coverage, 56869, |
| 99888 | GIR_EraseRootFromParent_Done, |
| 99889 | // Label 6673: @254810 |
| 99890 | GIM_Reject, |
| 99891 | // Label 6669: @254811 |
| 99892 | GIM_Reject, |
| 99893 | // Label 6617: @254812 |
| 99894 | GIM_Try, /*On fail goto*//*Label 6674*/ GIMT_Encode4(255062), |
| 99895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 99896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 99897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99898 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99899 | GIM_Try, /*On fail goto*//*Label 6675*/ GIMT_Encode4(254897), // Rule ID 56914 // |
| 99900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 99901 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99902 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 99903 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 99904 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99905 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99906 | // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFSGNJN_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 99907 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 99908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99909 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99910 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E32), |
| 99912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99913 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 99916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 99918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99919 | GIR_RootConstrainSelectedInstOperands, |
| 99920 | // GIR_Coverage, 56914, |
| 99921 | GIR_EraseRootFromParent_Done, |
| 99922 | // Label 6675: @254897 |
| 99923 | GIM_Try, /*On fail goto*//*Label 6676*/ GIMT_Encode4(254963), // Rule ID 56915 // |
| 99924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 99925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99926 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 99927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 99928 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99929 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99930 | // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFSGNJN_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 99931 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 99932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99933 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E32), |
| 99936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99938 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 99940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 99942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99943 | GIR_RootConstrainSelectedInstOperands, |
| 99944 | // GIR_Coverage, 56915, |
| 99945 | GIR_EraseRootFromParent_Done, |
| 99946 | // Label 6676: @254963 |
| 99947 | GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(255012), // Rule ID 56908 // |
| 99948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 99949 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99950 | // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSGNJ_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 99951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 99952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99953 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_MF2_E32), |
| 99956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99957 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99958 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99959 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 99960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 99962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99963 | GIR_RootConstrainSelectedInstOperands, |
| 99964 | // GIR_Coverage, 56908, |
| 99965 | GIR_EraseRootFromParent_Done, |
| 99966 | // Label 6677: @255012 |
| 99967 | GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(255061), // Rule ID 56909 // |
| 99968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 99969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99970 | // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSGNJ_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 99971 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 99972 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 99973 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 99974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 99975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_MF2_E32), |
| 99976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 99977 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 99978 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 99979 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 99980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 99981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 99982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 99983 | GIR_RootConstrainSelectedInstOperands, |
| 99984 | // GIR_Coverage, 56909, |
| 99985 | GIR_EraseRootFromParent_Done, |
| 99986 | // Label 6678: @255061 |
| 99987 | GIM_Reject, |
| 99988 | // Label 6674: @255062 |
| 99989 | GIM_Reject, |
| 99990 | // Label 6618: @255063 |
| 99991 | GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(255313), |
| 99992 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 99993 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 99994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 99996 | GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(255148), // Rule ID 56974 // |
| 99997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 99998 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99999 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100000 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 100001 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100002 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100003 | // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFSGNJN_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100004 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 100005 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100006 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E64), |
| 100009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100010 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100011 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100016 | GIR_RootConstrainSelectedInstOperands, |
| 100017 | // GIR_Coverage, 56974, |
| 100018 | GIR_EraseRootFromParent_Done, |
| 100019 | // Label 6680: @255148 |
| 100020 | GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(255214), // Rule ID 56975 // |
| 100021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100022 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100023 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100024 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 100025 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100026 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100027 | // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFSGNJN_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 100029 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100030 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E64), |
| 100033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100034 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100035 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100040 | GIR_RootConstrainSelectedInstOperands, |
| 100041 | // GIR_Coverage, 56975, |
| 100042 | GIR_EraseRootFromParent_Done, |
| 100043 | // Label 6681: @255214 |
| 100044 | GIM_Try, /*On fail goto*//*Label 6682*/ GIMT_Encode4(255263), // Rule ID 56968 // |
| 100045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100046 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100047 | // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSGNJ_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100048 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 100049 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100050 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M1_E64), |
| 100053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100054 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100055 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100056 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100060 | GIR_RootConstrainSelectedInstOperands, |
| 100061 | // GIR_Coverage, 56968, |
| 100062 | GIR_EraseRootFromParent_Done, |
| 100063 | // Label 6682: @255263 |
| 100064 | GIM_Try, /*On fail goto*//*Label 6683*/ GIMT_Encode4(255312), // Rule ID 56969 // |
| 100065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100066 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100067 | // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSGNJ_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100068 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 100069 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100070 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M1_E64), |
| 100073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100074 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100075 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100076 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100080 | GIR_RootConstrainSelectedInstOperands, |
| 100081 | // GIR_Coverage, 56969, |
| 100082 | GIR_EraseRootFromParent_Done, |
| 100083 | // Label 6683: @255312 |
| 100084 | GIM_Reject, |
| 100085 | // Label 6679: @255313 |
| 100086 | GIM_Reject, |
| 100087 | // Label 6619: @255314 |
| 100088 | GIM_Try, /*On fail goto*//*Label 6684*/ GIMT_Encode4(255564), |
| 100089 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 100090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 100091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100093 | GIM_Try, /*On fail goto*//*Label 6685*/ GIMT_Encode4(255399), // Rule ID 56894 // |
| 100094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100096 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 100098 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100099 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100100 | // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFSGNJN_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100101 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 100102 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100103 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100104 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E16), |
| 100106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100107 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100108 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100113 | GIR_RootConstrainSelectedInstOperands, |
| 100114 | // GIR_Coverage, 56894, |
| 100115 | GIR_EraseRootFromParent_Done, |
| 100116 | // Label 6685: @255399 |
| 100117 | GIM_Try, /*On fail goto*//*Label 6686*/ GIMT_Encode4(255465), // Rule ID 56895 // |
| 100118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100119 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100120 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100121 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 100122 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100123 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100124 | // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFSGNJN_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 100126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_MF2_E16), |
| 100130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100137 | GIR_RootConstrainSelectedInstOperands, |
| 100138 | // GIR_Coverage, 56895, |
| 100139 | GIR_EraseRootFromParent_Done, |
| 100140 | // Label 6686: @255465 |
| 100141 | GIM_Try, /*On fail goto*//*Label 6687*/ GIMT_Encode4(255514), // Rule ID 56888 // |
| 100142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100143 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100144 | // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSGNJ_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 100146 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100147 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100148 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_MF2_E16), |
| 100150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100151 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100152 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100153 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100157 | GIR_RootConstrainSelectedInstOperands, |
| 100158 | // GIR_Coverage, 56888, |
| 100159 | GIR_EraseRootFromParent_Done, |
| 100160 | // Label 6687: @255514 |
| 100161 | GIM_Try, /*On fail goto*//*Label 6688*/ GIMT_Encode4(255563), // Rule ID 56889 // |
| 100162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100164 | // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSGNJ_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 100166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_MF2_E16), |
| 100170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100171 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100172 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100173 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100177 | GIR_RootConstrainSelectedInstOperands, |
| 100178 | // GIR_Coverage, 56889, |
| 100179 | GIR_EraseRootFromParent_Done, |
| 100180 | // Label 6688: @255563 |
| 100181 | GIM_Reject, |
| 100182 | // Label 6684: @255564 |
| 100183 | GIM_Reject, |
| 100184 | // Label 6620: @255565 |
| 100185 | GIM_Try, /*On fail goto*//*Label 6689*/ GIMT_Encode4(255815), |
| 100186 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 100187 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 100188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100189 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100190 | GIM_Try, /*On fail goto*//*Label 6690*/ GIMT_Encode4(255650), // Rule ID 56954 // |
| 100191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 100192 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100193 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100194 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 100195 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100196 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100197 | // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFSGNJN_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 100198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 100199 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100200 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E32), |
| 100203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100204 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100205 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100210 | GIR_RootConstrainSelectedInstOperands, |
| 100211 | // GIR_Coverage, 56954, |
| 100212 | GIR_EraseRootFromParent_Done, |
| 100213 | // Label 6690: @255650 |
| 100214 | GIM_Try, /*On fail goto*//*Label 6691*/ GIMT_Encode4(255716), // Rule ID 56955 // |
| 100215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 100216 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100217 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100218 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 100219 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100220 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100221 | // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFSGNJN_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 100222 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 100223 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100224 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100225 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E32), |
| 100227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100228 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100229 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100234 | GIR_RootConstrainSelectedInstOperands, |
| 100235 | // GIR_Coverage, 56955, |
| 100236 | GIR_EraseRootFromParent_Done, |
| 100237 | // Label 6691: @255716 |
| 100238 | GIM_Try, /*On fail goto*//*Label 6692*/ GIMT_Encode4(255765), // Rule ID 56948 // |
| 100239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 100240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100241 | // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSGNJ_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 100242 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 100243 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100244 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M1_E32), |
| 100247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100248 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100249 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100250 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100254 | GIR_RootConstrainSelectedInstOperands, |
| 100255 | // GIR_Coverage, 56948, |
| 100256 | GIR_EraseRootFromParent_Done, |
| 100257 | // Label 6692: @255765 |
| 100258 | GIM_Try, /*On fail goto*//*Label 6693*/ GIMT_Encode4(255814), // Rule ID 56949 // |
| 100259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 100260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100261 | // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSGNJ_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 100262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 100263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M1_E32), |
| 100267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100268 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100269 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100270 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100274 | GIR_RootConstrainSelectedInstOperands, |
| 100275 | // GIR_Coverage, 56949, |
| 100276 | GIR_EraseRootFromParent_Done, |
| 100277 | // Label 6693: @255814 |
| 100278 | GIM_Reject, |
| 100279 | // Label 6689: @255815 |
| 100280 | GIM_Reject, |
| 100281 | // Label 6621: @255816 |
| 100282 | GIM_Try, /*On fail goto*//*Label 6694*/ GIMT_Encode4(256066), |
| 100283 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 100284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 100285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100287 | GIM_Try, /*On fail goto*//*Label 6695*/ GIMT_Encode4(255901), // Rule ID 57114 // |
| 100288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100289 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100290 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100291 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 100292 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100293 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100294 | // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFSGNJN_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100295 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 100296 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100297 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E64), |
| 100300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100302 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100307 | GIR_RootConstrainSelectedInstOperands, |
| 100308 | // GIR_Coverage, 57114, |
| 100309 | GIR_EraseRootFromParent_Done, |
| 100310 | // Label 6695: @255901 |
| 100311 | GIM_Try, /*On fail goto*//*Label 6696*/ GIMT_Encode4(255967), // Rule ID 57115 // |
| 100312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 100316 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100317 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100318 | // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFSGNJN_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100319 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 100320 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100321 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E64), |
| 100324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100325 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100326 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100327 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100331 | GIR_RootConstrainSelectedInstOperands, |
| 100332 | // GIR_Coverage, 57115, |
| 100333 | GIR_EraseRootFromParent_Done, |
| 100334 | // Label 6696: @255967 |
| 100335 | GIM_Try, /*On fail goto*//*Label 6697*/ GIMT_Encode4(256016), // Rule ID 57108 // |
| 100336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100338 | // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSGNJ_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100339 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 100340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100341 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M2_E64), |
| 100344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100345 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100346 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100347 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100351 | GIR_RootConstrainSelectedInstOperands, |
| 100352 | // GIR_Coverage, 57108, |
| 100353 | GIR_EraseRootFromParent_Done, |
| 100354 | // Label 6697: @256016 |
| 100355 | GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(256065), // Rule ID 57109 // |
| 100356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100358 | // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSGNJ_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100359 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 100360 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100361 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M2_E64), |
| 100364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100365 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100366 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100367 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100371 | GIR_RootConstrainSelectedInstOperands, |
| 100372 | // GIR_Coverage, 57109, |
| 100373 | GIR_EraseRootFromParent_Done, |
| 100374 | // Label 6698: @256065 |
| 100375 | GIM_Reject, |
| 100376 | // Label 6694: @256066 |
| 100377 | GIM_Reject, |
| 100378 | // Label 6622: @256067 |
| 100379 | GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(256317), |
| 100380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 100381 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 100382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100383 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100384 | GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(256152), // Rule ID 56934 // |
| 100385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100386 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100387 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100388 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 100389 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100390 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100391 | // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFSGNJN_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100392 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 100393 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100394 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100395 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E16), |
| 100397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100398 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100399 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100400 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100404 | GIR_RootConstrainSelectedInstOperands, |
| 100405 | // GIR_Coverage, 56934, |
| 100406 | GIR_EraseRootFromParent_Done, |
| 100407 | // Label 6700: @256152 |
| 100408 | GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(256218), // Rule ID 56935 // |
| 100409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100410 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100411 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100412 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 100413 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100414 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100415 | // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFSGNJN_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100416 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 100417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M1_E16), |
| 100421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100422 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100423 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100428 | GIR_RootConstrainSelectedInstOperands, |
| 100429 | // GIR_Coverage, 56935, |
| 100430 | GIR_EraseRootFromParent_Done, |
| 100431 | // Label 6701: @256218 |
| 100432 | GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(256267), // Rule ID 56928 // |
| 100433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100434 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100435 | // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSGNJ_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100436 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 100437 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100438 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M1_E16), |
| 100441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100443 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100444 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100448 | GIR_RootConstrainSelectedInstOperands, |
| 100449 | // GIR_Coverage, 56928, |
| 100450 | GIR_EraseRootFromParent_Done, |
| 100451 | // Label 6702: @256267 |
| 100452 | GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(256316), // Rule ID 56929 // |
| 100453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100454 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 100455 | // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSGNJ_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 100457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M1_E16), |
| 100461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100463 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100464 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100468 | GIR_RootConstrainSelectedInstOperands, |
| 100469 | // GIR_Coverage, 56929, |
| 100470 | GIR_EraseRootFromParent_Done, |
| 100471 | // Label 6703: @256316 |
| 100472 | GIM_Reject, |
| 100473 | // Label 6699: @256317 |
| 100474 | GIM_Reject, |
| 100475 | // Label 6623: @256318 |
| 100476 | GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(256568), |
| 100477 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 100478 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 100479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100480 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100481 | GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(256403), // Rule ID 57054 // |
| 100482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 100483 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100484 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100485 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 100486 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100487 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100488 | // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFSGNJN_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 100489 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 100490 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100491 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100492 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E32), |
| 100494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100495 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100496 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100501 | GIR_RootConstrainSelectedInstOperands, |
| 100502 | // GIR_Coverage, 57054, |
| 100503 | GIR_EraseRootFromParent_Done, |
| 100504 | // Label 6705: @256403 |
| 100505 | GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(256469), // Rule ID 57055 // |
| 100506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 100507 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100508 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100509 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 100510 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100511 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100512 | // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFSGNJN_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 100513 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 100514 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100515 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E32), |
| 100518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100519 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100520 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100525 | GIR_RootConstrainSelectedInstOperands, |
| 100526 | // GIR_Coverage, 57055, |
| 100527 | GIR_EraseRootFromParent_Done, |
| 100528 | // Label 6706: @256469 |
| 100529 | GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(256518), // Rule ID 57048 // |
| 100530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 100531 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100532 | // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSGNJ_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 100533 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 100534 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100535 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M2_E32), |
| 100538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100539 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100540 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100541 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100545 | GIR_RootConstrainSelectedInstOperands, |
| 100546 | // GIR_Coverage, 57048, |
| 100547 | GIR_EraseRootFromParent_Done, |
| 100548 | // Label 6707: @256518 |
| 100549 | GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(256567), // Rule ID 57049 // |
| 100550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 100551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100552 | // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSGNJ_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 100553 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 100554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100555 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M2_E32), |
| 100558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100559 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100561 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100565 | GIR_RootConstrainSelectedInstOperands, |
| 100566 | // GIR_Coverage, 57049, |
| 100567 | GIR_EraseRootFromParent_Done, |
| 100568 | // Label 6708: @256567 |
| 100569 | GIM_Reject, |
| 100570 | // Label 6704: @256568 |
| 100571 | GIM_Reject, |
| 100572 | // Label 6624: @256569 |
| 100573 | GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(256819), |
| 100574 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 100575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 100576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100577 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100578 | GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(256654), // Rule ID 57134 // |
| 100579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100580 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100581 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100582 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 100583 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100584 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100585 | // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFSGNJN_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 100587 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100588 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100589 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E64), |
| 100591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100592 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100593 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100594 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100598 | GIR_RootConstrainSelectedInstOperands, |
| 100599 | // GIR_Coverage, 57134, |
| 100600 | GIR_EraseRootFromParent_Done, |
| 100601 | // Label 6710: @256654 |
| 100602 | GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(256720), // Rule ID 57135 // |
| 100603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100604 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100605 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100606 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 100607 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100608 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100609 | // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFSGNJN_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100610 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 100611 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100612 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100613 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E64), |
| 100615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100617 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100622 | GIR_RootConstrainSelectedInstOperands, |
| 100623 | // GIR_Coverage, 57135, |
| 100624 | GIR_EraseRootFromParent_Done, |
| 100625 | // Label 6711: @256720 |
| 100626 | GIM_Try, /*On fail goto*//*Label 6712*/ GIMT_Encode4(256769), // Rule ID 57128 // |
| 100627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100628 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100629 | // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSGNJ_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100630 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 100631 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100632 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M4_E64), |
| 100635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100642 | GIR_RootConstrainSelectedInstOperands, |
| 100643 | // GIR_Coverage, 57128, |
| 100644 | GIR_EraseRootFromParent_Done, |
| 100645 | // Label 6712: @256769 |
| 100646 | GIM_Try, /*On fail goto*//*Label 6713*/ GIMT_Encode4(256818), // Rule ID 57129 // |
| 100647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100648 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100649 | // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSGNJ_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 100651 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100652 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M4_E64), |
| 100655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100656 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100657 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100658 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100662 | GIR_RootConstrainSelectedInstOperands, |
| 100663 | // GIR_Coverage, 57129, |
| 100664 | GIR_EraseRootFromParent_Done, |
| 100665 | // Label 6713: @256818 |
| 100666 | GIM_Reject, |
| 100667 | // Label 6709: @256819 |
| 100668 | GIM_Reject, |
| 100669 | // Label 6625: @256820 |
| 100670 | GIM_Try, /*On fail goto*//*Label 6714*/ GIMT_Encode4(257070), |
| 100671 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 100672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 100673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100674 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100675 | GIM_Try, /*On fail goto*//*Label 6715*/ GIMT_Encode4(256905), // Rule ID 56994 // |
| 100676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 100680 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100681 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100682 | // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFSGNJN_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100683 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 100684 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100685 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E16), |
| 100688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100689 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100690 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100691 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100695 | GIR_RootConstrainSelectedInstOperands, |
| 100696 | // GIR_Coverage, 56994, |
| 100697 | GIR_EraseRootFromParent_Done, |
| 100698 | // Label 6715: @256905 |
| 100699 | GIM_Try, /*On fail goto*//*Label 6716*/ GIMT_Encode4(256971), // Rule ID 56995 // |
| 100700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100701 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100702 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100703 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 100704 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100705 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100706 | // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFSGNJN_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 100708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M2_E16), |
| 100712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100713 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100714 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100719 | GIR_RootConstrainSelectedInstOperands, |
| 100720 | // GIR_Coverage, 56995, |
| 100721 | GIR_EraseRootFromParent_Done, |
| 100722 | // Label 6716: @256971 |
| 100723 | GIM_Try, /*On fail goto*//*Label 6717*/ GIMT_Encode4(257020), // Rule ID 56988 // |
| 100724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100726 | // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSGNJ_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100727 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 100728 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100729 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M2_E16), |
| 100732 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100733 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100734 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100735 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100739 | GIR_RootConstrainSelectedInstOperands, |
| 100740 | // GIR_Coverage, 56988, |
| 100741 | GIR_EraseRootFromParent_Done, |
| 100742 | // Label 6717: @257020 |
| 100743 | GIM_Try, /*On fail goto*//*Label 6718*/ GIMT_Encode4(257069), // Rule ID 56989 // |
| 100744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 100746 | // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSGNJ_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100747 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 100748 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100749 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M2_E16), |
| 100752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100753 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100754 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100755 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100759 | GIR_RootConstrainSelectedInstOperands, |
| 100760 | // GIR_Coverage, 56989, |
| 100761 | GIR_EraseRootFromParent_Done, |
| 100762 | // Label 6718: @257069 |
| 100763 | GIM_Reject, |
| 100764 | // Label 6714: @257070 |
| 100765 | GIM_Reject, |
| 100766 | // Label 6626: @257071 |
| 100767 | GIM_Try, /*On fail goto*//*Label 6719*/ GIMT_Encode4(257321), |
| 100768 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 100769 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 100770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100772 | GIM_Try, /*On fail goto*//*Label 6720*/ GIMT_Encode4(257156), // Rule ID 57074 // |
| 100773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 100774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100775 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 100777 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100778 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100779 | // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFSGNJN_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 100780 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 100781 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100782 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E32), |
| 100785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100786 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100787 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100792 | GIR_RootConstrainSelectedInstOperands, |
| 100793 | // GIR_Coverage, 57074, |
| 100794 | GIR_EraseRootFromParent_Done, |
| 100795 | // Label 6720: @257156 |
| 100796 | GIM_Try, /*On fail goto*//*Label 6721*/ GIMT_Encode4(257222), // Rule ID 57075 // |
| 100797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 100798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 100801 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100802 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100803 | // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFSGNJN_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 100804 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 100805 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100806 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E32), |
| 100809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100810 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100811 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100816 | GIR_RootConstrainSelectedInstOperands, |
| 100817 | // GIR_Coverage, 57075, |
| 100818 | GIR_EraseRootFromParent_Done, |
| 100819 | // Label 6721: @257222 |
| 100820 | GIM_Try, /*On fail goto*//*Label 6722*/ GIMT_Encode4(257271), // Rule ID 57068 // |
| 100821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 100822 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100823 | // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSGNJ_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 100824 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 100825 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100826 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M4_E32), |
| 100829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100830 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100831 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100832 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100836 | GIR_RootConstrainSelectedInstOperands, |
| 100837 | // GIR_Coverage, 57068, |
| 100838 | GIR_EraseRootFromParent_Done, |
| 100839 | // Label 6722: @257271 |
| 100840 | GIM_Try, /*On fail goto*//*Label 6723*/ GIMT_Encode4(257320), // Rule ID 57069 // |
| 100841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 100842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100843 | // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSGNJ_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 100844 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 100845 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100846 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M4_E32), |
| 100849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100850 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100851 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100852 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 100855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100856 | GIR_RootConstrainSelectedInstOperands, |
| 100857 | // GIR_Coverage, 57069, |
| 100858 | GIR_EraseRootFromParent_Done, |
| 100859 | // Label 6723: @257320 |
| 100860 | GIM_Reject, |
| 100861 | // Label 6719: @257321 |
| 100862 | GIM_Reject, |
| 100863 | // Label 6627: @257322 |
| 100864 | GIM_Try, /*On fail goto*//*Label 6724*/ GIMT_Encode4(257572), |
| 100865 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 100866 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 100867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 100868 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 100869 | GIM_Try, /*On fail goto*//*Label 6725*/ GIMT_Encode4(257407), // Rule ID 57154 // |
| 100870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100871 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100872 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100873 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 100874 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 100875 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100876 | // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFSGNJN_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100877 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 100878 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100879 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100880 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E64), |
| 100882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100883 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100884 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100889 | GIR_RootConstrainSelectedInstOperands, |
| 100890 | // GIR_Coverage, 57154, |
| 100891 | GIR_EraseRootFromParent_Done, |
| 100892 | // Label 6725: @257407 |
| 100893 | GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(257473), // Rule ID 57155 // |
| 100894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 100898 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 100899 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100900 | // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFSGNJN_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100901 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 100902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E64), |
| 100906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100907 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100913 | GIR_RootConstrainSelectedInstOperands, |
| 100914 | // GIR_Coverage, 57155, |
| 100915 | GIR_EraseRootFromParent_Done, |
| 100916 | // Label 6726: @257473 |
| 100917 | GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(257522), // Rule ID 57148 // |
| 100918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 100919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 100920 | // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSGNJ_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 100921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 100922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100923 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100924 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M8_E64), |
| 100926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100927 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100928 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100929 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100933 | GIR_RootConstrainSelectedInstOperands, |
| 100934 | // GIR_Coverage, 57148, |
| 100935 | GIR_EraseRootFromParent_Done, |
| 100936 | // Label 6727: @257522 |
| 100937 | GIM_Try, /*On fail goto*//*Label 6728*/ GIMT_Encode4(257571), // Rule ID 57149 // |
| 100938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 100939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 100940 | // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSGNJ_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 100941 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 100942 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100943 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100944 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M8_E64), |
| 100946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100947 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100948 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100949 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 100950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 100952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100953 | GIR_RootConstrainSelectedInstOperands, |
| 100954 | // GIR_Coverage, 57149, |
| 100955 | GIR_EraseRootFromParent_Done, |
| 100956 | // Label 6728: @257571 |
| 100957 | GIM_Reject, |
| 100958 | // Label 6724: @257572 |
| 100959 | GIM_Reject, |
| 100960 | // Label 6628: @257573 |
| 100961 | GIM_Try, /*On fail goto*//*Label 6729*/ GIMT_Encode4(257823), |
| 100962 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 100963 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 100964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100965 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100966 | GIM_Try, /*On fail goto*//*Label 6730*/ GIMT_Encode4(257658), // Rule ID 57014 // |
| 100967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 100968 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100969 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100970 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 100971 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100972 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100973 | // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFSGNJN_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 100974 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 100975 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 100976 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 100977 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 100978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E16), |
| 100979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 100980 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 100981 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 100982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 100983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 100984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 100985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 100986 | GIR_RootConstrainSelectedInstOperands, |
| 100987 | // GIR_Coverage, 57014, |
| 100988 | GIR_EraseRootFromParent_Done, |
| 100989 | // Label 6730: @257658 |
| 100990 | GIM_Try, /*On fail goto*//*Label 6731*/ GIMT_Encode4(257724), // Rule ID 57015 // |
| 100991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 100992 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 100993 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 100994 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 100995 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 100996 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 100997 | // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFSGNJN_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 100998 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 100999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101001 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M4_E16), |
| 101003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101004 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101005 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 101007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101010 | GIR_RootConstrainSelectedInstOperands, |
| 101011 | // GIR_Coverage, 57015, |
| 101012 | GIR_EraseRootFromParent_Done, |
| 101013 | // Label 6731: @257724 |
| 101014 | GIM_Try, /*On fail goto*//*Label 6732*/ GIMT_Encode4(257773), // Rule ID 57008 // |
| 101015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101016 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101017 | // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSGNJ_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101018 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 101019 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101020 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101021 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M4_E16), |
| 101023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101024 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101025 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101026 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101030 | GIR_RootConstrainSelectedInstOperands, |
| 101031 | // GIR_Coverage, 57008, |
| 101032 | GIR_EraseRootFromParent_Done, |
| 101033 | // Label 6732: @257773 |
| 101034 | GIM_Try, /*On fail goto*//*Label 6733*/ GIMT_Encode4(257822), // Rule ID 57009 // |
| 101035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101036 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101037 | // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSGNJ_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101038 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 101039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101040 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M4_E16), |
| 101043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101044 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101045 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101046 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101050 | GIR_RootConstrainSelectedInstOperands, |
| 101051 | // GIR_Coverage, 57009, |
| 101052 | GIR_EraseRootFromParent_Done, |
| 101053 | // Label 6733: @257822 |
| 101054 | GIM_Reject, |
| 101055 | // Label 6729: @257823 |
| 101056 | GIM_Reject, |
| 101057 | // Label 6629: @257824 |
| 101058 | GIM_Try, /*On fail goto*//*Label 6734*/ GIMT_Encode4(258074), |
| 101059 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 101060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 101061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101062 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101063 | GIM_Try, /*On fail goto*//*Label 6735*/ GIMT_Encode4(257909), // Rule ID 57094 // |
| 101064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 101065 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 101066 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 101067 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 101068 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101069 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 101070 | // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFSGNJN_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 101071 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 101072 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101073 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E32), |
| 101076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101077 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101078 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 101080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101083 | GIR_RootConstrainSelectedInstOperands, |
| 101084 | // GIR_Coverage, 57094, |
| 101085 | GIR_EraseRootFromParent_Done, |
| 101086 | // Label 6735: @257909 |
| 101087 | GIM_Try, /*On fail goto*//*Label 6736*/ GIMT_Encode4(257975), // Rule ID 57095 // |
| 101088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 101089 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 101090 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 101091 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 101092 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101093 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 101094 | // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFSGNJN_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 101095 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 101096 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101097 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E32), |
| 101100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101101 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101102 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 101104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101107 | GIR_RootConstrainSelectedInstOperands, |
| 101108 | // GIR_Coverage, 57095, |
| 101109 | GIR_EraseRootFromParent_Done, |
| 101110 | // Label 6736: @257975 |
| 101111 | GIM_Try, /*On fail goto*//*Label 6737*/ GIMT_Encode4(258024), // Rule ID 57088 // |
| 101112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 101113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101114 | // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSGNJ_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 101115 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 101116 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101117 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M8_E32), |
| 101120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101121 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101122 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101123 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101127 | GIR_RootConstrainSelectedInstOperands, |
| 101128 | // GIR_Coverage, 57088, |
| 101129 | GIR_EraseRootFromParent_Done, |
| 101130 | // Label 6737: @258024 |
| 101131 | GIM_Try, /*On fail goto*//*Label 6738*/ GIMT_Encode4(258073), // Rule ID 57089 // |
| 101132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 101133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101134 | // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSGNJ_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 101135 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 101136 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101137 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101138 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M8_E32), |
| 101140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101141 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101142 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101143 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101147 | GIR_RootConstrainSelectedInstOperands, |
| 101148 | // GIR_Coverage, 57089, |
| 101149 | GIR_EraseRootFromParent_Done, |
| 101150 | // Label 6738: @258073 |
| 101151 | GIM_Reject, |
| 101152 | // Label 6734: @258074 |
| 101153 | GIM_Reject, |
| 101154 | // Label 6630: @258075 |
| 101155 | GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(258325), |
| 101156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 101157 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 101158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101159 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101160 | GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(258160), // Rule ID 57034 // |
| 101161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 101163 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 101164 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 101165 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101166 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 101167 | // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFSGNJN_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101168 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 101169 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101170 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101171 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E16), |
| 101173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101174 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101175 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 101177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101180 | GIR_RootConstrainSelectedInstOperands, |
| 101181 | // GIR_Coverage, 57034, |
| 101182 | GIR_EraseRootFromParent_Done, |
| 101183 | // Label 6740: @258160 |
| 101184 | GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(258226), // Rule ID 57035 // |
| 101185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101186 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 101187 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 101188 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 101189 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101190 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 101191 | // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFSGNJN_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101192 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 101193 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101194 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJN_VV_M8_E16), |
| 101197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101199 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 101201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101204 | GIR_RootConstrainSelectedInstOperands, |
| 101205 | // GIR_Coverage, 57035, |
| 101206 | GIR_EraseRootFromParent_Done, |
| 101207 | // Label 6741: @258226 |
| 101208 | GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(258275), // Rule ID 57028 // |
| 101209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101211 | // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSGNJ_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101212 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 101213 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101214 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101215 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M8_E16), |
| 101217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101218 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101219 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101220 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101224 | GIR_RootConstrainSelectedInstOperands, |
| 101225 | // GIR_Coverage, 57028, |
| 101226 | GIR_EraseRootFromParent_Done, |
| 101227 | // Label 6742: @258275 |
| 101228 | GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(258324), // Rule ID 57029 // |
| 101229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101230 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101231 | // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSGNJ_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101232 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 101233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSGNJ_VV_M8_E16), |
| 101237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101239 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101240 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101244 | GIR_RootConstrainSelectedInstOperands, |
| 101245 | // GIR_Coverage, 57029, |
| 101246 | GIR_EraseRootFromParent_Done, |
| 101247 | // Label 6743: @258324 |
| 101248 | GIM_Reject, |
| 101249 | // Label 6739: @258325 |
| 101250 | GIM_Reject, |
| 101251 | // Label 6631: @258326 |
| 101252 | GIM_Reject, |
| 101253 | // Label 67: @258327 |
| 101254 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 6762*/ GIMT_Encode4(260411), |
| 101255 | /*GILLT_s16*//*Label 6744*/ GIMT_Encode4(258458), |
| 101256 | /*GILLT_s32*//*Label 6745*/ GIMT_Encode4(258525), |
| 101257 | /*GILLT_s64*//*Label 6746*/ GIMT_Encode4(258592), GIMT_Encode4(0), GIMT_Encode4(0), |
| 101258 | /*GILLT_nxv1s16*//*Label 6747*/ GIMT_Encode4(258686), |
| 101259 | /*GILLT_nxv1s32*//*Label 6748*/ GIMT_Encode4(258801), |
| 101260 | /*GILLT_nxv1s64*//*Label 6749*/ GIMT_Encode4(258916), GIMT_Encode4(0), GIMT_Encode4(0), |
| 101261 | /*GILLT_nxv2s16*//*Label 6750*/ GIMT_Encode4(259031), |
| 101262 | /*GILLT_nxv2s32*//*Label 6751*/ GIMT_Encode4(259146), |
| 101263 | /*GILLT_nxv2s64*//*Label 6752*/ GIMT_Encode4(259261), GIMT_Encode4(0), GIMT_Encode4(0), |
| 101264 | /*GILLT_nxv4s16*//*Label 6753*/ GIMT_Encode4(259376), |
| 101265 | /*GILLT_nxv4s32*//*Label 6754*/ GIMT_Encode4(259491), |
| 101266 | /*GILLT_nxv4s64*//*Label 6755*/ GIMT_Encode4(259606), GIMT_Encode4(0), GIMT_Encode4(0), |
| 101267 | /*GILLT_nxv8s16*//*Label 6756*/ GIMT_Encode4(259721), |
| 101268 | /*GILLT_nxv8s32*//*Label 6757*/ GIMT_Encode4(259836), |
| 101269 | /*GILLT_nxv8s64*//*Label 6758*/ GIMT_Encode4(259951), GIMT_Encode4(0), GIMT_Encode4(0), |
| 101270 | /*GILLT_nxv16s16*//*Label 6759*/ GIMT_Encode4(260066), |
| 101271 | /*GILLT_nxv16s32*//*Label 6760*/ GIMT_Encode4(260181), GIMT_Encode4(0), GIMT_Encode4(0), |
| 101272 | /*GILLT_nxv32s16*//*Label 6761*/ GIMT_Encode4(260296), |
| 101273 | // Label 6744: @258458 |
| 101274 | GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(258524), |
| 101275 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 101276 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 101277 | GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(258496), // Rule ID 2106 // |
| 101278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh), |
| 101279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 101280 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 101281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 101282 | // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMIN_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 101283 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_H), |
| 101284 | GIR_RootConstrainSelectedInstOperands, |
| 101285 | // GIR_Coverage, 2106, |
| 101286 | GIR_Done, |
| 101287 | // Label 6764: @258496 |
| 101288 | GIM_Try, /*On fail goto*//*Label 6765*/ GIMT_Encode4(258523), // Rule ID 2107 // |
| 101289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx), |
| 101290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 101291 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 101292 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 101293 | // (fminnum:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FMIN_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 101294 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_H_INX), |
| 101295 | GIR_RootConstrainSelectedInstOperands, |
| 101296 | // GIR_Coverage, 2107, |
| 101297 | GIR_Done, |
| 101298 | // Label 6765: @258523 |
| 101299 | GIM_Reject, |
| 101300 | // Label 6763: @258524 |
| 101301 | GIM_Reject, |
| 101302 | // Label 6745: @258525 |
| 101303 | GIM_Try, /*On fail goto*//*Label 6766*/ GIMT_Encode4(258591), |
| 101304 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 101305 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 101306 | GIM_Try, /*On fail goto*//*Label 6767*/ GIMT_Encode4(258563), // Rule ID 1414 // |
| 101307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF), |
| 101308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 101309 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 101310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 101311 | // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMIN_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 101312 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_S), |
| 101313 | GIR_RootConstrainSelectedInstOperands, |
| 101314 | // GIR_Coverage, 1414, |
| 101315 | GIR_Done, |
| 101316 | // Label 6767: @258563 |
| 101317 | GIM_Try, /*On fail goto*//*Label 6768*/ GIMT_Encode4(258590), // Rule ID 1415 // |
| 101318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx), |
| 101319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 101320 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 101321 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 101322 | // (fminnum:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FMIN_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 101323 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_S_INX), |
| 101324 | GIR_RootConstrainSelectedInstOperands, |
| 101325 | // GIR_Coverage, 1415, |
| 101326 | GIR_Done, |
| 101327 | // Label 6768: @258590 |
| 101328 | GIM_Reject, |
| 101329 | // Label 6766: @258591 |
| 101330 | GIM_Reject, |
| 101331 | // Label 6746: @258592 |
| 101332 | GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(258685), |
| 101333 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 101334 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 101335 | GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(258630), // Rule ID 1775 // |
| 101336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD), |
| 101337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 101338 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 101339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 101340 | // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMIN_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 101341 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_D), |
| 101342 | GIR_RootConstrainSelectedInstOperands, |
| 101343 | // GIR_Coverage, 1775, |
| 101344 | GIR_Done, |
| 101345 | // Label 6770: @258630 |
| 101346 | GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(258657), // Rule ID 1776 // |
| 101347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32), |
| 101348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 101349 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 101350 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 101351 | // (fminnum:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FMIN_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 101352 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_D_IN32X), |
| 101353 | GIR_RootConstrainSelectedInstOperands, |
| 101354 | // GIR_Coverage, 1776, |
| 101355 | GIR_Done, |
| 101356 | // Label 6771: @258657 |
| 101357 | GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(258684), // Rule ID 1777 // |
| 101358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 101359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 101360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 101361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 101362 | // (fminnum:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FMIN_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 101363 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMIN_D_INX), |
| 101364 | GIR_RootConstrainSelectedInstOperands, |
| 101365 | // GIR_Coverage, 1777, |
| 101366 | GIR_Done, |
| 101367 | // Label 6772: @258684 |
| 101368 | GIM_Reject, |
| 101369 | // Label 6769: @258685 |
| 101370 | GIM_Reject, |
| 101371 | // Label 6747: @258686 |
| 101372 | GIM_Try, /*On fail goto*//*Label 6773*/ GIMT_Encode4(258800), |
| 101373 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 101374 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 101375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101378 | GIM_Try, /*On fail goto*//*Label 6774*/ GIMT_Encode4(258754), // Rule ID 46584 // |
| 101379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101380 | // (fminnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMIN_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101381 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 101382 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_MF4_E16), |
| 101386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101387 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101388 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101389 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101393 | GIR_RootConstrainSelectedInstOperands, |
| 101394 | // GIR_Coverage, 46584, |
| 101395 | GIR_EraseRootFromParent_Done, |
| 101396 | // Label 6774: @258754 |
| 101397 | GIM_Try, /*On fail goto*//*Label 6775*/ GIMT_Encode4(258799), // Rule ID 46585 // |
| 101398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101399 | // (fminnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMIN_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 101401 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101402 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_MF4_E16), |
| 101405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101406 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101407 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101408 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101412 | GIR_RootConstrainSelectedInstOperands, |
| 101413 | // GIR_Coverage, 46585, |
| 101414 | GIR_EraseRootFromParent_Done, |
| 101415 | // Label 6775: @258799 |
| 101416 | GIM_Reject, |
| 101417 | // Label 6773: @258800 |
| 101418 | GIM_Reject, |
| 101419 | // Label 6748: @258801 |
| 101420 | GIM_Try, /*On fail goto*//*Label 6776*/ GIMT_Encode4(258915), |
| 101421 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 101422 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 101423 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101424 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101425 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101426 | GIM_Try, /*On fail goto*//*Label 6777*/ GIMT_Encode4(258869), // Rule ID 57166 // |
| 101427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 101428 | // (fminnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMIN_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 101429 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 101430 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101431 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_MF2_E32), |
| 101434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101435 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101436 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101437 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101441 | GIR_RootConstrainSelectedInstOperands, |
| 101442 | // GIR_Coverage, 57166, |
| 101443 | GIR_EraseRootFromParent_Done, |
| 101444 | // Label 6777: @258869 |
| 101445 | GIM_Try, /*On fail goto*//*Label 6778*/ GIMT_Encode4(258914), // Rule ID 57167 // |
| 101446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 101447 | // (fminnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMIN_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 101448 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 101449 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101450 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_MF2_E32), |
| 101453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101454 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101455 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101456 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101460 | GIR_RootConstrainSelectedInstOperands, |
| 101461 | // GIR_Coverage, 57167, |
| 101462 | GIR_EraseRootFromParent_Done, |
| 101463 | // Label 6778: @258914 |
| 101464 | GIM_Reject, |
| 101465 | // Label 6776: @258915 |
| 101466 | GIM_Reject, |
| 101467 | // Label 6749: @258916 |
| 101468 | GIM_Try, /*On fail goto*//*Label 6779*/ GIMT_Encode4(259030), |
| 101469 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 101470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 101471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101472 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101474 | GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(258984), // Rule ID 57184 // |
| 101475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 101476 | // (fminnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMIN_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 101477 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 101478 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101479 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M1_E64), |
| 101482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101483 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101484 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101485 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101489 | GIR_RootConstrainSelectedInstOperands, |
| 101490 | // GIR_Coverage, 57184, |
| 101491 | GIR_EraseRootFromParent_Done, |
| 101492 | // Label 6780: @258984 |
| 101493 | GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(259029), // Rule ID 57185 // |
| 101494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 101495 | // (fminnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMIN_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 101496 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 101497 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101498 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101499 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M1_E64), |
| 101501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101502 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101503 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101504 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101508 | GIR_RootConstrainSelectedInstOperands, |
| 101509 | // GIR_Coverage, 57185, |
| 101510 | GIR_EraseRootFromParent_Done, |
| 101511 | // Label 6781: @259029 |
| 101512 | GIM_Reject, |
| 101513 | // Label 6779: @259030 |
| 101514 | GIM_Reject, |
| 101515 | // Label 6750: @259031 |
| 101516 | GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(259145), |
| 101517 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 101518 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 101519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101520 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101521 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101522 | GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(259099), // Rule ID 57160 // |
| 101523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101524 | // (fminnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMIN_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101525 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 101526 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101527 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_MF2_E16), |
| 101530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101531 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101532 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101533 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101537 | GIR_RootConstrainSelectedInstOperands, |
| 101538 | // GIR_Coverage, 57160, |
| 101539 | GIR_EraseRootFromParent_Done, |
| 101540 | // Label 6783: @259099 |
| 101541 | GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(259144), // Rule ID 57161 // |
| 101542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101543 | // (fminnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMIN_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101544 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 101545 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101546 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_MF2_E16), |
| 101549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101550 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101551 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101552 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101556 | GIR_RootConstrainSelectedInstOperands, |
| 101557 | // GIR_Coverage, 57161, |
| 101558 | GIR_EraseRootFromParent_Done, |
| 101559 | // Label 6784: @259144 |
| 101560 | GIM_Reject, |
| 101561 | // Label 6782: @259145 |
| 101562 | GIM_Reject, |
| 101563 | // Label 6751: @259146 |
| 101564 | GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(259260), |
| 101565 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 101566 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 101567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101568 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101569 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101570 | GIM_Try, /*On fail goto*//*Label 6786*/ GIMT_Encode4(259214), // Rule ID 57178 // |
| 101571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 101572 | // (fminnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMIN_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 101573 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 101574 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101575 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M1_E32), |
| 101578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101579 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101580 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101581 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101585 | GIR_RootConstrainSelectedInstOperands, |
| 101586 | // GIR_Coverage, 57178, |
| 101587 | GIR_EraseRootFromParent_Done, |
| 101588 | // Label 6786: @259214 |
| 101589 | GIM_Try, /*On fail goto*//*Label 6787*/ GIMT_Encode4(259259), // Rule ID 57179 // |
| 101590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 101591 | // (fminnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMIN_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 101592 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 101593 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101594 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M1_E32), |
| 101597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101598 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101599 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101600 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101604 | GIR_RootConstrainSelectedInstOperands, |
| 101605 | // GIR_Coverage, 57179, |
| 101606 | GIR_EraseRootFromParent_Done, |
| 101607 | // Label 6787: @259259 |
| 101608 | GIM_Reject, |
| 101609 | // Label 6785: @259260 |
| 101610 | GIM_Reject, |
| 101611 | // Label 6752: @259261 |
| 101612 | GIM_Try, /*On fail goto*//*Label 6788*/ GIMT_Encode4(259375), |
| 101613 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 101614 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 101615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101616 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101618 | GIM_Try, /*On fail goto*//*Label 6789*/ GIMT_Encode4(259329), // Rule ID 57226 // |
| 101619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 101620 | // (fminnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMIN_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 101621 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 101622 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101623 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101624 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M2_E64), |
| 101626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101627 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101628 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101629 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101633 | GIR_RootConstrainSelectedInstOperands, |
| 101634 | // GIR_Coverage, 57226, |
| 101635 | GIR_EraseRootFromParent_Done, |
| 101636 | // Label 6789: @259329 |
| 101637 | GIM_Try, /*On fail goto*//*Label 6790*/ GIMT_Encode4(259374), // Rule ID 57227 // |
| 101638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 101639 | // (fminnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMIN_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 101640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 101641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M2_E64), |
| 101645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101647 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101648 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101652 | GIR_RootConstrainSelectedInstOperands, |
| 101653 | // GIR_Coverage, 57227, |
| 101654 | GIR_EraseRootFromParent_Done, |
| 101655 | // Label 6790: @259374 |
| 101656 | GIM_Reject, |
| 101657 | // Label 6788: @259375 |
| 101658 | GIM_Reject, |
| 101659 | // Label 6753: @259376 |
| 101660 | GIM_Try, /*On fail goto*//*Label 6791*/ GIMT_Encode4(259490), |
| 101661 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 101662 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 101663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101664 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101665 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 101666 | GIM_Try, /*On fail goto*//*Label 6792*/ GIMT_Encode4(259444), // Rule ID 57172 // |
| 101667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101668 | // (fminnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMIN_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101669 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 101670 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101671 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101672 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M1_E16), |
| 101674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101675 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101676 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101677 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101681 | GIR_RootConstrainSelectedInstOperands, |
| 101682 | // GIR_Coverage, 57172, |
| 101683 | GIR_EraseRootFromParent_Done, |
| 101684 | // Label 6792: @259444 |
| 101685 | GIM_Try, /*On fail goto*//*Label 6793*/ GIMT_Encode4(259489), // Rule ID 57173 // |
| 101686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101687 | // (fminnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMIN_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101688 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 101689 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101690 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M1_E16), |
| 101693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101694 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101695 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101696 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101700 | GIR_RootConstrainSelectedInstOperands, |
| 101701 | // GIR_Coverage, 57173, |
| 101702 | GIR_EraseRootFromParent_Done, |
| 101703 | // Label 6793: @259489 |
| 101704 | GIM_Reject, |
| 101705 | // Label 6791: @259490 |
| 101706 | GIM_Reject, |
| 101707 | // Label 6754: @259491 |
| 101708 | GIM_Try, /*On fail goto*//*Label 6794*/ GIMT_Encode4(259605), |
| 101709 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 101710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 101711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101714 | GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(259559), // Rule ID 57208 // |
| 101715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 101716 | // (fminnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMIN_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 101717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 101718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101719 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M2_E32), |
| 101722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101725 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101729 | GIR_RootConstrainSelectedInstOperands, |
| 101730 | // GIR_Coverage, 57208, |
| 101731 | GIR_EraseRootFromParent_Done, |
| 101732 | // Label 6795: @259559 |
| 101733 | GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(259604), // Rule ID 57209 // |
| 101734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 101735 | // (fminnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMIN_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 101736 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 101737 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101738 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M2_E32), |
| 101741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101742 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101743 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101744 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101748 | GIR_RootConstrainSelectedInstOperands, |
| 101749 | // GIR_Coverage, 57209, |
| 101750 | GIR_EraseRootFromParent_Done, |
| 101751 | // Label 6796: @259604 |
| 101752 | GIM_Reject, |
| 101753 | // Label 6794: @259605 |
| 101754 | GIM_Reject, |
| 101755 | // Label 6755: @259606 |
| 101756 | GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(259720), |
| 101757 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 101758 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 101759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101760 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101762 | GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(259674), // Rule ID 57232 // |
| 101763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 101764 | // (fminnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMIN_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 101765 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 101766 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101767 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M4_E64), |
| 101770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101771 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101772 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101773 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101777 | GIR_RootConstrainSelectedInstOperands, |
| 101778 | // GIR_Coverage, 57232, |
| 101779 | GIR_EraseRootFromParent_Done, |
| 101780 | // Label 6798: @259674 |
| 101781 | GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(259719), // Rule ID 57233 // |
| 101782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 101783 | // (fminnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMIN_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 101784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 101785 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M4_E64), |
| 101789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101790 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101791 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101792 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101796 | GIR_RootConstrainSelectedInstOperands, |
| 101797 | // GIR_Coverage, 57233, |
| 101798 | GIR_EraseRootFromParent_Done, |
| 101799 | // Label 6799: @259719 |
| 101800 | GIM_Reject, |
| 101801 | // Label 6797: @259720 |
| 101802 | GIM_Reject, |
| 101803 | // Label 6756: @259721 |
| 101804 | GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(259835), |
| 101805 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 101806 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 101807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101808 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101809 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 101810 | GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(259789), // Rule ID 57190 // |
| 101811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101812 | // (fminnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMIN_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101813 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 101814 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101815 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M2_E16), |
| 101818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101819 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101820 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101821 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101825 | GIR_RootConstrainSelectedInstOperands, |
| 101826 | // GIR_Coverage, 57190, |
| 101827 | GIR_EraseRootFromParent_Done, |
| 101828 | // Label 6801: @259789 |
| 101829 | GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(259834), // Rule ID 57191 // |
| 101830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101831 | // (fminnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMIN_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 101833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101834 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101835 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M2_E16), |
| 101837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101838 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101839 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101840 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101844 | GIR_RootConstrainSelectedInstOperands, |
| 101845 | // GIR_Coverage, 57191, |
| 101846 | GIR_EraseRootFromParent_Done, |
| 101847 | // Label 6802: @259834 |
| 101848 | GIM_Reject, |
| 101849 | // Label 6800: @259835 |
| 101850 | GIM_Reject, |
| 101851 | // Label 6757: @259836 |
| 101852 | GIM_Try, /*On fail goto*//*Label 6803*/ GIMT_Encode4(259950), |
| 101853 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 101854 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 101855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101857 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101858 | GIM_Try, /*On fail goto*//*Label 6804*/ GIMT_Encode4(259904), // Rule ID 57214 // |
| 101859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 101860 | // (fminnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMIN_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 101861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 101862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101864 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M4_E32), |
| 101866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101868 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101869 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101873 | GIR_RootConstrainSelectedInstOperands, |
| 101874 | // GIR_Coverage, 57214, |
| 101875 | GIR_EraseRootFromParent_Done, |
| 101876 | // Label 6804: @259904 |
| 101877 | GIM_Try, /*On fail goto*//*Label 6805*/ GIMT_Encode4(259949), // Rule ID 57215 // |
| 101878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 101879 | // (fminnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMIN_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 101880 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 101881 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101882 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101883 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M4_E32), |
| 101885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101886 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101887 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101888 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 101891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101892 | GIR_RootConstrainSelectedInstOperands, |
| 101893 | // GIR_Coverage, 57215, |
| 101894 | GIR_EraseRootFromParent_Done, |
| 101895 | // Label 6805: @259949 |
| 101896 | GIM_Reject, |
| 101897 | // Label 6803: @259950 |
| 101898 | GIM_Reject, |
| 101899 | // Label 6758: @259951 |
| 101900 | GIM_Try, /*On fail goto*//*Label 6806*/ GIMT_Encode4(260065), |
| 101901 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 101902 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 101903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101904 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101905 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 101906 | GIM_Try, /*On fail goto*//*Label 6807*/ GIMT_Encode4(260019), // Rule ID 57238 // |
| 101907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 101908 | // (fminnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMIN_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 101909 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 101910 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101911 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101912 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M8_E64), |
| 101914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101915 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101916 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101917 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101921 | GIR_RootConstrainSelectedInstOperands, |
| 101922 | // GIR_Coverage, 57238, |
| 101923 | GIR_EraseRootFromParent_Done, |
| 101924 | // Label 6807: @260019 |
| 101925 | GIM_Try, /*On fail goto*//*Label 6808*/ GIMT_Encode4(260064), // Rule ID 57239 // |
| 101926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 101927 | // (fminnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMIN_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 101928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 101929 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101930 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M8_E64), |
| 101933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101934 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101935 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101936 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 101939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101940 | GIR_RootConstrainSelectedInstOperands, |
| 101941 | // GIR_Coverage, 57239, |
| 101942 | GIR_EraseRootFromParent_Done, |
| 101943 | // Label 6808: @260064 |
| 101944 | GIM_Reject, |
| 101945 | // Label 6806: @260065 |
| 101946 | GIM_Reject, |
| 101947 | // Label 6759: @260066 |
| 101948 | GIM_Try, /*On fail goto*//*Label 6809*/ GIMT_Encode4(260180), |
| 101949 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 101950 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 101951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101952 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101953 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 101954 | GIM_Try, /*On fail goto*//*Label 6810*/ GIMT_Encode4(260134), // Rule ID 57196 // |
| 101955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 101956 | // (fminnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMIN_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 101957 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 101958 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101959 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M4_E16), |
| 101962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101963 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101964 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101965 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101969 | GIR_RootConstrainSelectedInstOperands, |
| 101970 | // GIR_Coverage, 57196, |
| 101971 | GIR_EraseRootFromParent_Done, |
| 101972 | // Label 6810: @260134 |
| 101973 | GIM_Try, /*On fail goto*//*Label 6811*/ GIMT_Encode4(260179), // Rule ID 57197 // |
| 101974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 101975 | // (fminnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMIN_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 101976 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 101977 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 101978 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 101979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 101980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M4_E16), |
| 101981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 101982 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 101983 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 101984 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 101985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 101986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 101987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 101988 | GIR_RootConstrainSelectedInstOperands, |
| 101989 | // GIR_Coverage, 57197, |
| 101990 | GIR_EraseRootFromParent_Done, |
| 101991 | // Label 6811: @260179 |
| 101992 | GIM_Reject, |
| 101993 | // Label 6809: @260180 |
| 101994 | GIM_Reject, |
| 101995 | // Label 6760: @260181 |
| 101996 | GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(260295), |
| 101997 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 101998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 101999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102000 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102001 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102002 | GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(260249), // Rule ID 57220 // |
| 102003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 102004 | // (fminnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMIN_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 102005 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 102006 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102007 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M8_E32), |
| 102010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102011 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102012 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102013 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102017 | GIR_RootConstrainSelectedInstOperands, |
| 102018 | // GIR_Coverage, 57220, |
| 102019 | GIR_EraseRootFromParent_Done, |
| 102020 | // Label 6813: @260249 |
| 102021 | GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(260294), // Rule ID 57221 // |
| 102022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 102023 | // (fminnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMIN_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 102024 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 102025 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102026 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102027 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M8_E32), |
| 102029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102030 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102031 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102032 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102036 | GIR_RootConstrainSelectedInstOperands, |
| 102037 | // GIR_Coverage, 57221, |
| 102038 | GIR_EraseRootFromParent_Done, |
| 102039 | // Label 6814: @260294 |
| 102040 | GIM_Reject, |
| 102041 | // Label 6812: @260295 |
| 102042 | GIM_Reject, |
| 102043 | // Label 6761: @260296 |
| 102044 | GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(260410), |
| 102045 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 102046 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 102047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102048 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102049 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102050 | GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(260364), // Rule ID 57202 // |
| 102051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102052 | // (fminnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMIN_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102053 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 102054 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102055 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M8_E16), |
| 102058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102060 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102061 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102065 | GIR_RootConstrainSelectedInstOperands, |
| 102066 | // GIR_Coverage, 57202, |
| 102067 | GIR_EraseRootFromParent_Done, |
| 102068 | // Label 6816: @260364 |
| 102069 | GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(260409), // Rule ID 57203 // |
| 102070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102071 | // (fminnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMIN_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102072 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 102073 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102074 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMIN_VV_M8_E16), |
| 102077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102078 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102079 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102080 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102084 | GIR_RootConstrainSelectedInstOperands, |
| 102085 | // GIR_Coverage, 57203, |
| 102086 | GIR_EraseRootFromParent_Done, |
| 102087 | // Label 6817: @260409 |
| 102088 | GIM_Reject, |
| 102089 | // Label 6815: @260410 |
| 102090 | GIM_Reject, |
| 102091 | // Label 6762: @260411 |
| 102092 | GIM_Reject, |
| 102093 | // Label 68: @260412 |
| 102094 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 6836*/ GIMT_Encode4(262496), |
| 102095 | /*GILLT_s16*//*Label 6818*/ GIMT_Encode4(260543), |
| 102096 | /*GILLT_s32*//*Label 6819*/ GIMT_Encode4(260610), |
| 102097 | /*GILLT_s64*//*Label 6820*/ GIMT_Encode4(260677), GIMT_Encode4(0), GIMT_Encode4(0), |
| 102098 | /*GILLT_nxv1s16*//*Label 6821*/ GIMT_Encode4(260771), |
| 102099 | /*GILLT_nxv1s32*//*Label 6822*/ GIMT_Encode4(260886), |
| 102100 | /*GILLT_nxv1s64*//*Label 6823*/ GIMT_Encode4(261001), GIMT_Encode4(0), GIMT_Encode4(0), |
| 102101 | /*GILLT_nxv2s16*//*Label 6824*/ GIMT_Encode4(261116), |
| 102102 | /*GILLT_nxv2s32*//*Label 6825*/ GIMT_Encode4(261231), |
| 102103 | /*GILLT_nxv2s64*//*Label 6826*/ GIMT_Encode4(261346), GIMT_Encode4(0), GIMT_Encode4(0), |
| 102104 | /*GILLT_nxv4s16*//*Label 6827*/ GIMT_Encode4(261461), |
| 102105 | /*GILLT_nxv4s32*//*Label 6828*/ GIMT_Encode4(261576), |
| 102106 | /*GILLT_nxv4s64*//*Label 6829*/ GIMT_Encode4(261691), GIMT_Encode4(0), GIMT_Encode4(0), |
| 102107 | /*GILLT_nxv8s16*//*Label 6830*/ GIMT_Encode4(261806), |
| 102108 | /*GILLT_nxv8s32*//*Label 6831*/ GIMT_Encode4(261921), |
| 102109 | /*GILLT_nxv8s64*//*Label 6832*/ GIMT_Encode4(262036), GIMT_Encode4(0), GIMT_Encode4(0), |
| 102110 | /*GILLT_nxv16s16*//*Label 6833*/ GIMT_Encode4(262151), |
| 102111 | /*GILLT_nxv16s32*//*Label 6834*/ GIMT_Encode4(262266), GIMT_Encode4(0), GIMT_Encode4(0), |
| 102112 | /*GILLT_nxv32s16*//*Label 6835*/ GIMT_Encode4(262381), |
| 102113 | // Label 6818: @260543 |
| 102114 | GIM_Try, /*On fail goto*//*Label 6837*/ GIMT_Encode4(260609), |
| 102115 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 102116 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 102117 | GIM_Try, /*On fail goto*//*Label 6838*/ GIMT_Encode4(260581), // Rule ID 2108 // |
| 102118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh), |
| 102119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102120 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102121 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102122 | // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMAX_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 102123 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_H), |
| 102124 | GIR_RootConstrainSelectedInstOperands, |
| 102125 | // GIR_Coverage, 2108, |
| 102126 | GIR_Done, |
| 102127 | // Label 6838: @260581 |
| 102128 | GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(260608), // Rule ID 2109 // |
| 102129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx), |
| 102130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 102131 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 102132 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 102133 | // (fmaxnum:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FMAX_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 102134 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_H_INX), |
| 102135 | GIR_RootConstrainSelectedInstOperands, |
| 102136 | // GIR_Coverage, 2109, |
| 102137 | GIR_Done, |
| 102138 | // Label 6839: @260608 |
| 102139 | GIM_Reject, |
| 102140 | // Label 6837: @260609 |
| 102141 | GIM_Reject, |
| 102142 | // Label 6819: @260610 |
| 102143 | GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(260676), |
| 102144 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 102145 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 102146 | GIM_Try, /*On fail goto*//*Label 6841*/ GIMT_Encode4(260648), // Rule ID 1416 // |
| 102147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF), |
| 102148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 102149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 102150 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 102151 | // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMAX_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 102152 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_S), |
| 102153 | GIR_RootConstrainSelectedInstOperands, |
| 102154 | // GIR_Coverage, 1416, |
| 102155 | GIR_Done, |
| 102156 | // Label 6841: @260648 |
| 102157 | GIM_Try, /*On fail goto*//*Label 6842*/ GIMT_Encode4(260675), // Rule ID 1417 // |
| 102158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx), |
| 102159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 102160 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 102161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 102162 | // (fmaxnum:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FMAX_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 102163 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_S_INX), |
| 102164 | GIR_RootConstrainSelectedInstOperands, |
| 102165 | // GIR_Coverage, 1417, |
| 102166 | GIR_Done, |
| 102167 | // Label 6842: @260675 |
| 102168 | GIM_Reject, |
| 102169 | // Label 6840: @260676 |
| 102170 | GIM_Reject, |
| 102171 | // Label 6820: @260677 |
| 102172 | GIM_Try, /*On fail goto*//*Label 6843*/ GIMT_Encode4(260770), |
| 102173 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 102174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 102175 | GIM_Try, /*On fail goto*//*Label 6844*/ GIMT_Encode4(260715), // Rule ID 1778 // |
| 102176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD), |
| 102177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 102178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 102179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 102180 | // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMAX_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 102181 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_D), |
| 102182 | GIR_RootConstrainSelectedInstOperands, |
| 102183 | // GIR_Coverage, 1778, |
| 102184 | GIR_Done, |
| 102185 | // Label 6844: @260715 |
| 102186 | GIM_Try, /*On fail goto*//*Label 6845*/ GIMT_Encode4(260742), // Rule ID 1779 // |
| 102187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32), |
| 102188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 102189 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 102190 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 102191 | // (fmaxnum:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FMAX_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 102192 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_D_IN32X), |
| 102193 | GIR_RootConstrainSelectedInstOperands, |
| 102194 | // GIR_Coverage, 1779, |
| 102195 | GIR_Done, |
| 102196 | // Label 6845: @260742 |
| 102197 | GIM_Try, /*On fail goto*//*Label 6846*/ GIMT_Encode4(260769), // Rule ID 1780 // |
| 102198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 102199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 102200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 102201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 102202 | // (fmaxnum:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FMAX_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 102203 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAX_D_INX), |
| 102204 | GIR_RootConstrainSelectedInstOperands, |
| 102205 | // GIR_Coverage, 1780, |
| 102206 | GIR_Done, |
| 102207 | // Label 6846: @260769 |
| 102208 | GIM_Reject, |
| 102209 | // Label 6843: @260770 |
| 102210 | GIM_Reject, |
| 102211 | // Label 6821: @260771 |
| 102212 | GIM_Try, /*On fail goto*//*Label 6847*/ GIMT_Encode4(260885), |
| 102213 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 102214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 102215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102216 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102218 | GIM_Try, /*On fail goto*//*Label 6848*/ GIMT_Encode4(260839), // Rule ID 57244 // |
| 102219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102220 | // (fmaxnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMAX_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102221 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 102222 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102223 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_MF4_E16), |
| 102226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102227 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102228 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102229 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102233 | GIR_RootConstrainSelectedInstOperands, |
| 102234 | // GIR_Coverage, 57244, |
| 102235 | GIR_EraseRootFromParent_Done, |
| 102236 | // Label 6848: @260839 |
| 102237 | GIM_Try, /*On fail goto*//*Label 6849*/ GIMT_Encode4(260884), // Rule ID 57245 // |
| 102238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102239 | // (fmaxnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMAX_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 102241 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102242 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_MF4_E16), |
| 102245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102247 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102248 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102252 | GIR_RootConstrainSelectedInstOperands, |
| 102253 | // GIR_Coverage, 57245, |
| 102254 | GIR_EraseRootFromParent_Done, |
| 102255 | // Label 6849: @260884 |
| 102256 | GIM_Reject, |
| 102257 | // Label 6847: @260885 |
| 102258 | GIM_Reject, |
| 102259 | // Label 6822: @260886 |
| 102260 | GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(261000), |
| 102261 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 102262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 102263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102264 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102266 | GIM_Try, /*On fail goto*//*Label 6851*/ GIMT_Encode4(260954), // Rule ID 57256 // |
| 102267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 102268 | // (fmaxnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMAX_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 102269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 102270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_MF2_E32), |
| 102274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102276 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102277 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102281 | GIR_RootConstrainSelectedInstOperands, |
| 102282 | // GIR_Coverage, 57256, |
| 102283 | GIR_EraseRootFromParent_Done, |
| 102284 | // Label 6851: @260954 |
| 102285 | GIM_Try, /*On fail goto*//*Label 6852*/ GIMT_Encode4(260999), // Rule ID 57257 // |
| 102286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 102287 | // (fmaxnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMAX_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 102288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 102289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_MF2_E32), |
| 102293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102300 | GIR_RootConstrainSelectedInstOperands, |
| 102301 | // GIR_Coverage, 57257, |
| 102302 | GIR_EraseRootFromParent_Done, |
| 102303 | // Label 6852: @260999 |
| 102304 | GIM_Reject, |
| 102305 | // Label 6850: @261000 |
| 102306 | GIM_Reject, |
| 102307 | // Label 6823: @261001 |
| 102308 | GIM_Try, /*On fail goto*//*Label 6853*/ GIMT_Encode4(261115), |
| 102309 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 102310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 102311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102312 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102313 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102314 | GIM_Try, /*On fail goto*//*Label 6854*/ GIMT_Encode4(261069), // Rule ID 57274 // |
| 102315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 102316 | // (fmaxnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMAX_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 102317 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 102318 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102319 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102320 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M1_E64), |
| 102322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102323 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102324 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102325 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102329 | GIR_RootConstrainSelectedInstOperands, |
| 102330 | // GIR_Coverage, 57274, |
| 102331 | GIR_EraseRootFromParent_Done, |
| 102332 | // Label 6854: @261069 |
| 102333 | GIM_Try, /*On fail goto*//*Label 6855*/ GIMT_Encode4(261114), // Rule ID 57275 // |
| 102334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 102335 | // (fmaxnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMAX_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 102336 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 102337 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102338 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M1_E64), |
| 102341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102342 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102343 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102344 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102348 | GIR_RootConstrainSelectedInstOperands, |
| 102349 | // GIR_Coverage, 57275, |
| 102350 | GIR_EraseRootFromParent_Done, |
| 102351 | // Label 6855: @261114 |
| 102352 | GIM_Reject, |
| 102353 | // Label 6853: @261115 |
| 102354 | GIM_Reject, |
| 102355 | // Label 6824: @261116 |
| 102356 | GIM_Try, /*On fail goto*//*Label 6856*/ GIMT_Encode4(261230), |
| 102357 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 102358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 102359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102362 | GIM_Try, /*On fail goto*//*Label 6857*/ GIMT_Encode4(261184), // Rule ID 57250 // |
| 102363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102364 | // (fmaxnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMAX_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 102366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_MF2_E16), |
| 102370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102371 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102372 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102373 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102377 | GIR_RootConstrainSelectedInstOperands, |
| 102378 | // GIR_Coverage, 57250, |
| 102379 | GIR_EraseRootFromParent_Done, |
| 102380 | // Label 6857: @261184 |
| 102381 | GIM_Try, /*On fail goto*//*Label 6858*/ GIMT_Encode4(261229), // Rule ID 57251 // |
| 102382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102383 | // (fmaxnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMAX_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 102385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_MF2_E16), |
| 102389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102390 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102391 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102392 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102396 | GIR_RootConstrainSelectedInstOperands, |
| 102397 | // GIR_Coverage, 57251, |
| 102398 | GIR_EraseRootFromParent_Done, |
| 102399 | // Label 6858: @261229 |
| 102400 | GIM_Reject, |
| 102401 | // Label 6856: @261230 |
| 102402 | GIM_Reject, |
| 102403 | // Label 6825: @261231 |
| 102404 | GIM_Try, /*On fail goto*//*Label 6859*/ GIMT_Encode4(261345), |
| 102405 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 102406 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 102407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102409 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102410 | GIM_Try, /*On fail goto*//*Label 6860*/ GIMT_Encode4(261299), // Rule ID 57268 // |
| 102411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 102412 | // (fmaxnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMAX_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 102413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 102414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102415 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M1_E32), |
| 102418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102419 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102420 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102421 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102425 | GIR_RootConstrainSelectedInstOperands, |
| 102426 | // GIR_Coverage, 57268, |
| 102427 | GIR_EraseRootFromParent_Done, |
| 102428 | // Label 6860: @261299 |
| 102429 | GIM_Try, /*On fail goto*//*Label 6861*/ GIMT_Encode4(261344), // Rule ID 57269 // |
| 102430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 102431 | // (fmaxnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMAX_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 102432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 102433 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102434 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M1_E32), |
| 102437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102438 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102439 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102440 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102444 | GIR_RootConstrainSelectedInstOperands, |
| 102445 | // GIR_Coverage, 57269, |
| 102446 | GIR_EraseRootFromParent_Done, |
| 102447 | // Label 6861: @261344 |
| 102448 | GIM_Reject, |
| 102449 | // Label 6859: @261345 |
| 102450 | GIM_Reject, |
| 102451 | // Label 6826: @261346 |
| 102452 | GIM_Try, /*On fail goto*//*Label 6862*/ GIMT_Encode4(261460), |
| 102453 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 102454 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 102455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102456 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102458 | GIM_Try, /*On fail goto*//*Label 6863*/ GIMT_Encode4(261414), // Rule ID 57316 // |
| 102459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 102460 | // (fmaxnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMAX_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 102461 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 102462 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102463 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M2_E64), |
| 102466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102467 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102468 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102469 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102473 | GIR_RootConstrainSelectedInstOperands, |
| 102474 | // GIR_Coverage, 57316, |
| 102475 | GIR_EraseRootFromParent_Done, |
| 102476 | // Label 6863: @261414 |
| 102477 | GIM_Try, /*On fail goto*//*Label 6864*/ GIMT_Encode4(261459), // Rule ID 57317 // |
| 102478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 102479 | // (fmaxnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMAX_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 102480 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 102481 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102482 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M2_E64), |
| 102485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102486 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102487 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102488 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102492 | GIR_RootConstrainSelectedInstOperands, |
| 102493 | // GIR_Coverage, 57317, |
| 102494 | GIR_EraseRootFromParent_Done, |
| 102495 | // Label 6864: @261459 |
| 102496 | GIM_Reject, |
| 102497 | // Label 6862: @261460 |
| 102498 | GIM_Reject, |
| 102499 | // Label 6827: @261461 |
| 102500 | GIM_Try, /*On fail goto*//*Label 6865*/ GIMT_Encode4(261575), |
| 102501 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 102502 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 102503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102504 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102505 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 102506 | GIM_Try, /*On fail goto*//*Label 6866*/ GIMT_Encode4(261529), // Rule ID 57262 // |
| 102507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102508 | // (fmaxnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMAX_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102509 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 102510 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102511 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M1_E16), |
| 102514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102515 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102516 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102517 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102521 | GIR_RootConstrainSelectedInstOperands, |
| 102522 | // GIR_Coverage, 57262, |
| 102523 | GIR_EraseRootFromParent_Done, |
| 102524 | // Label 6866: @261529 |
| 102525 | GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(261574), // Rule ID 57263 // |
| 102526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102527 | // (fmaxnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMAX_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 102529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M1_E16), |
| 102533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102534 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102535 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102536 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102540 | GIR_RootConstrainSelectedInstOperands, |
| 102541 | // GIR_Coverage, 57263, |
| 102542 | GIR_EraseRootFromParent_Done, |
| 102543 | // Label 6867: @261574 |
| 102544 | GIM_Reject, |
| 102545 | // Label 6865: @261575 |
| 102546 | GIM_Reject, |
| 102547 | // Label 6828: @261576 |
| 102548 | GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(261690), |
| 102549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 102550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 102551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102554 | GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(261644), // Rule ID 57298 // |
| 102555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 102556 | // (fmaxnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMAX_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 102557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 102558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M2_E32), |
| 102562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102564 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102565 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102569 | GIR_RootConstrainSelectedInstOperands, |
| 102570 | // GIR_Coverage, 57298, |
| 102571 | GIR_EraseRootFromParent_Done, |
| 102572 | // Label 6869: @261644 |
| 102573 | GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(261689), // Rule ID 57299 // |
| 102574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 102575 | // (fmaxnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMAX_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 102576 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 102577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102579 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M2_E32), |
| 102581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102582 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102583 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102584 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102588 | GIR_RootConstrainSelectedInstOperands, |
| 102589 | // GIR_Coverage, 57299, |
| 102590 | GIR_EraseRootFromParent_Done, |
| 102591 | // Label 6870: @261689 |
| 102592 | GIM_Reject, |
| 102593 | // Label 6868: @261690 |
| 102594 | GIM_Reject, |
| 102595 | // Label 6829: @261691 |
| 102596 | GIM_Try, /*On fail goto*//*Label 6871*/ GIMT_Encode4(261805), |
| 102597 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 102598 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 102599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102600 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102601 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102602 | GIM_Try, /*On fail goto*//*Label 6872*/ GIMT_Encode4(261759), // Rule ID 57322 // |
| 102603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 102604 | // (fmaxnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMAX_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 102605 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 102606 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102607 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102608 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M4_E64), |
| 102610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102612 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102613 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102617 | GIR_RootConstrainSelectedInstOperands, |
| 102618 | // GIR_Coverage, 57322, |
| 102619 | GIR_EraseRootFromParent_Done, |
| 102620 | // Label 6872: @261759 |
| 102621 | GIM_Try, /*On fail goto*//*Label 6873*/ GIMT_Encode4(261804), // Rule ID 57323 // |
| 102622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 102623 | // (fmaxnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMAX_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 102624 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 102625 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102626 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102627 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M4_E64), |
| 102629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102630 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102631 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102632 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102636 | GIR_RootConstrainSelectedInstOperands, |
| 102637 | // GIR_Coverage, 57323, |
| 102638 | GIR_EraseRootFromParent_Done, |
| 102639 | // Label 6873: @261804 |
| 102640 | GIM_Reject, |
| 102641 | // Label 6871: @261805 |
| 102642 | GIM_Reject, |
| 102643 | // Label 6830: @261806 |
| 102644 | GIM_Try, /*On fail goto*//*Label 6874*/ GIMT_Encode4(261920), |
| 102645 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 102646 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 102647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102649 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 102650 | GIM_Try, /*On fail goto*//*Label 6875*/ GIMT_Encode4(261874), // Rule ID 57280 // |
| 102651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102652 | // (fmaxnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMAX_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 102654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M2_E16), |
| 102658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102660 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102665 | GIR_RootConstrainSelectedInstOperands, |
| 102666 | // GIR_Coverage, 57280, |
| 102667 | GIR_EraseRootFromParent_Done, |
| 102668 | // Label 6875: @261874 |
| 102669 | GIM_Try, /*On fail goto*//*Label 6876*/ GIMT_Encode4(261919), // Rule ID 57281 // |
| 102670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102671 | // (fmaxnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMAX_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102672 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 102673 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102674 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M2_E16), |
| 102677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102679 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102680 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102684 | GIR_RootConstrainSelectedInstOperands, |
| 102685 | // GIR_Coverage, 57281, |
| 102686 | GIR_EraseRootFromParent_Done, |
| 102687 | // Label 6876: @261919 |
| 102688 | GIM_Reject, |
| 102689 | // Label 6874: @261920 |
| 102690 | GIM_Reject, |
| 102691 | // Label 6831: @261921 |
| 102692 | GIM_Try, /*On fail goto*//*Label 6877*/ GIMT_Encode4(262035), |
| 102693 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 102694 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 102695 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102696 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102698 | GIM_Try, /*On fail goto*//*Label 6878*/ GIMT_Encode4(261989), // Rule ID 57304 // |
| 102699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 102700 | // (fmaxnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMAX_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 102701 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 102702 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102703 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102704 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M4_E32), |
| 102706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102707 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102708 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102709 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102713 | GIR_RootConstrainSelectedInstOperands, |
| 102714 | // GIR_Coverage, 57304, |
| 102715 | GIR_EraseRootFromParent_Done, |
| 102716 | // Label 6878: @261989 |
| 102717 | GIM_Try, /*On fail goto*//*Label 6879*/ GIMT_Encode4(262034), // Rule ID 57305 // |
| 102718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 102719 | // (fmaxnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMAX_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 102720 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 102721 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102722 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M4_E32), |
| 102725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102726 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102727 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102728 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102732 | GIR_RootConstrainSelectedInstOperands, |
| 102733 | // GIR_Coverage, 57305, |
| 102734 | GIR_EraseRootFromParent_Done, |
| 102735 | // Label 6879: @262034 |
| 102736 | GIM_Reject, |
| 102737 | // Label 6877: @262035 |
| 102738 | GIM_Reject, |
| 102739 | // Label 6832: @262036 |
| 102740 | GIM_Try, /*On fail goto*//*Label 6880*/ GIMT_Encode4(262150), |
| 102741 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 102742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 102743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102744 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102746 | GIM_Try, /*On fail goto*//*Label 6881*/ GIMT_Encode4(262104), // Rule ID 57328 // |
| 102747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 102748 | // (fmaxnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMAX_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 102749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 102750 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102751 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102752 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M8_E64), |
| 102754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102755 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102756 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102757 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102761 | GIR_RootConstrainSelectedInstOperands, |
| 102762 | // GIR_Coverage, 57328, |
| 102763 | GIR_EraseRootFromParent_Done, |
| 102764 | // Label 6881: @262104 |
| 102765 | GIM_Try, /*On fail goto*//*Label 6882*/ GIMT_Encode4(262149), // Rule ID 57329 // |
| 102766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 102767 | // (fmaxnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMAX_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 102768 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 102769 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102770 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102771 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M8_E64), |
| 102773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102774 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102775 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102776 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 102779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102780 | GIR_RootConstrainSelectedInstOperands, |
| 102781 | // GIR_Coverage, 57329, |
| 102782 | GIR_EraseRootFromParent_Done, |
| 102783 | // Label 6882: @262149 |
| 102784 | GIM_Reject, |
| 102785 | // Label 6880: @262150 |
| 102786 | GIM_Reject, |
| 102787 | // Label 6833: @262151 |
| 102788 | GIM_Try, /*On fail goto*//*Label 6883*/ GIMT_Encode4(262265), |
| 102789 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 102790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 102791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102792 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102793 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 102794 | GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(262219), // Rule ID 57286 // |
| 102795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102796 | // (fmaxnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMAX_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102797 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 102798 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102799 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102800 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M4_E16), |
| 102802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102803 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102804 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102805 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102809 | GIR_RootConstrainSelectedInstOperands, |
| 102810 | // GIR_Coverage, 57286, |
| 102811 | GIR_EraseRootFromParent_Done, |
| 102812 | // Label 6884: @262219 |
| 102813 | GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(262264), // Rule ID 57287 // |
| 102814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102815 | // (fmaxnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMAX_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102816 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 102817 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102818 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102819 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M4_E16), |
| 102821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102822 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102823 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102824 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102828 | GIR_RootConstrainSelectedInstOperands, |
| 102829 | // GIR_Coverage, 57287, |
| 102830 | GIR_EraseRootFromParent_Done, |
| 102831 | // Label 6885: @262264 |
| 102832 | GIM_Reject, |
| 102833 | // Label 6883: @262265 |
| 102834 | GIM_Reject, |
| 102835 | // Label 6834: @262266 |
| 102836 | GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(262380), |
| 102837 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 102838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 102839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102840 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102841 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102842 | GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(262334), // Rule ID 57310 // |
| 102843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 102844 | // (fmaxnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMAX_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 102845 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 102846 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102847 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M8_E32), |
| 102850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102851 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102852 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102853 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102857 | GIR_RootConstrainSelectedInstOperands, |
| 102858 | // GIR_Coverage, 57310, |
| 102859 | GIR_EraseRootFromParent_Done, |
| 102860 | // Label 6887: @262334 |
| 102861 | GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(262379), // Rule ID 57311 // |
| 102862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 102863 | // (fmaxnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMAX_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 102864 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 102865 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102866 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M8_E32), |
| 102869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102870 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102871 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 102875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102876 | GIR_RootConstrainSelectedInstOperands, |
| 102877 | // GIR_Coverage, 57311, |
| 102878 | GIR_EraseRootFromParent_Done, |
| 102879 | // Label 6888: @262379 |
| 102880 | GIM_Reject, |
| 102881 | // Label 6886: @262380 |
| 102882 | GIM_Reject, |
| 102883 | // Label 6835: @262381 |
| 102884 | GIM_Try, /*On fail goto*//*Label 6889*/ GIMT_Encode4(262495), |
| 102885 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 102886 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 102887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 102890 | GIM_Try, /*On fail goto*//*Label 6890*/ GIMT_Encode4(262449), // Rule ID 57292 // |
| 102891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 102892 | // (fmaxnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMAX_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 102893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 102894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M8_E16), |
| 102898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102900 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102901 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102905 | GIR_RootConstrainSelectedInstOperands, |
| 102906 | // GIR_Coverage, 57292, |
| 102907 | GIR_EraseRootFromParent_Done, |
| 102908 | // Label 6890: @262449 |
| 102909 | GIM_Try, /*On fail goto*//*Label 6891*/ GIMT_Encode4(262494), // Rule ID 57293 // |
| 102910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 102911 | // (fmaxnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMAX_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 102912 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 102913 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 102914 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 102915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 102916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMAX_VV_M8_E16), |
| 102917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 102918 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 102919 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 102920 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 102921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 102922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 102923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 102924 | GIR_RootConstrainSelectedInstOperands, |
| 102925 | // GIR_Coverage, 57293, |
| 102926 | GIR_EraseRootFromParent_Done, |
| 102927 | // Label 6891: @262494 |
| 102928 | GIM_Reject, |
| 102929 | // Label 6889: @262495 |
| 102930 | GIM_Reject, |
| 102931 | // Label 6836: @262496 |
| 102932 | GIM_Reject, |
| 102933 | // Label 69: @262497 |
| 102934 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 6895*/ GIMT_Encode4(262622), |
| 102935 | /*GILLT_s16*//*Label 6892*/ GIMT_Encode4(262520), |
| 102936 | /*GILLT_s32*//*Label 6893*/ GIMT_Encode4(262554), |
| 102937 | /*GILLT_s64*//*Label 6894*/ GIMT_Encode4(262588), |
| 102938 | // Label 6892: @262520 |
| 102939 | GIM_Try, /*On fail goto*//*Label 6896*/ GIMT_Encode4(262553), // Rule ID 2564 // |
| 102940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh), |
| 102941 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 102942 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 102943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102944 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102945 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102946 | // (fminimum:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMINM_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 102947 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMINM_H), |
| 102948 | GIR_RootConstrainSelectedInstOperands, |
| 102949 | // GIR_Coverage, 2564, |
| 102950 | GIR_Done, |
| 102951 | // Label 6896: @262553 |
| 102952 | GIM_Reject, |
| 102953 | // Label 6893: @262554 |
| 102954 | GIM_Try, /*On fail goto*//*Label 6897*/ GIMT_Encode4(262587), // Rule ID 2490 // |
| 102955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa), |
| 102956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 102957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 102958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 102959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 102960 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 102961 | // (fminimum:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMINM_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 102962 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMINM_S), |
| 102963 | GIR_RootConstrainSelectedInstOperands, |
| 102964 | // GIR_Coverage, 2490, |
| 102965 | GIR_Done, |
| 102966 | // Label 6897: @262587 |
| 102967 | GIM_Reject, |
| 102968 | // Label 6894: @262588 |
| 102969 | GIM_Try, /*On fail goto*//*Label 6898*/ GIMT_Encode4(262621), // Rule ID 2524 // |
| 102970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa), |
| 102971 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 102972 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 102973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 102974 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 102975 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 102976 | // (fminimum:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMINM_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 102977 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMINM_D), |
| 102978 | GIR_RootConstrainSelectedInstOperands, |
| 102979 | // GIR_Coverage, 2524, |
| 102980 | GIR_Done, |
| 102981 | // Label 6898: @262621 |
| 102982 | GIM_Reject, |
| 102983 | // Label 6895: @262622 |
| 102984 | GIM_Reject, |
| 102985 | // Label 70: @262623 |
| 102986 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 6902*/ GIMT_Encode4(262748), |
| 102987 | /*GILLT_s16*//*Label 6899*/ GIMT_Encode4(262646), |
| 102988 | /*GILLT_s32*//*Label 6900*/ GIMT_Encode4(262680), |
| 102989 | /*GILLT_s64*//*Label 6901*/ GIMT_Encode4(262714), |
| 102990 | // Label 6899: @262646 |
| 102991 | GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(262679), // Rule ID 2565 // |
| 102992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh), |
| 102993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 102994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 102995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102996 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102997 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 102998 | // (fmaximum:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMAXM_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2) |
| 102999 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAXM_H), |
| 103000 | GIR_RootConstrainSelectedInstOperands, |
| 103001 | // GIR_Coverage, 2565, |
| 103002 | GIR_Done, |
| 103003 | // Label 6903: @262679 |
| 103004 | GIM_Reject, |
| 103005 | // Label 6900: @262680 |
| 103006 | GIM_Try, /*On fail goto*//*Label 6904*/ GIMT_Encode4(262713), // Rule ID 2491 // |
| 103007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa), |
| 103008 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 103009 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 103010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 103011 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 103012 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 103013 | // (fmaximum:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMAXM_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2) |
| 103014 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAXM_S), |
| 103015 | GIR_RootConstrainSelectedInstOperands, |
| 103016 | // GIR_Coverage, 2491, |
| 103017 | GIR_Done, |
| 103018 | // Label 6904: @262713 |
| 103019 | GIM_Reject, |
| 103020 | // Label 6901: @262714 |
| 103021 | GIM_Try, /*On fail goto*//*Label 6905*/ GIMT_Encode4(262747), // Rule ID 2525 // |
| 103022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa), |
| 103023 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 103024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 103025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 103026 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 103027 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 103028 | // (fmaximum:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMAXM_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2) |
| 103029 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FMAXM_D), |
| 103030 | GIR_RootConstrainSelectedInstOperands, |
| 103031 | // GIR_Coverage, 2525, |
| 103032 | GIR_Done, |
| 103033 | // Label 6905: @262747 |
| 103034 | GIM_Reject, |
| 103035 | // Label 6902: @262748 |
| 103036 | GIM_Reject, |
| 103037 | // Label 71: @262749 |
| 103038 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 6930*/ GIMT_Encode4(265524), |
| 103039 | /*GILLT_s32*//*Label 6906*/ GIMT_Encode4(262884), |
| 103040 | /*GILLT_s64*//*Label 6907*/ GIMT_Encode4(262939), GIMT_Encode4(0), |
| 103041 | /*GILLT_nxv1s8*//*Label 6908*/ GIMT_Encode4(262994), |
| 103042 | /*GILLT_nxv1s16*//*Label 6909*/ GIMT_Encode4(263109), |
| 103043 | /*GILLT_nxv1s32*//*Label 6910*/ GIMT_Encode4(263224), |
| 103044 | /*GILLT_nxv1s64*//*Label 6911*/ GIMT_Encode4(263339), GIMT_Encode4(0), |
| 103045 | /*GILLT_nxv2s8*//*Label 6912*/ GIMT_Encode4(263454), |
| 103046 | /*GILLT_nxv2s16*//*Label 6913*/ GIMT_Encode4(263569), |
| 103047 | /*GILLT_nxv2s32*//*Label 6914*/ GIMT_Encode4(263684), |
| 103048 | /*GILLT_nxv2s64*//*Label 6915*/ GIMT_Encode4(263799), GIMT_Encode4(0), |
| 103049 | /*GILLT_nxv4s8*//*Label 6916*/ GIMT_Encode4(263914), |
| 103050 | /*GILLT_nxv4s16*//*Label 6917*/ GIMT_Encode4(264029), |
| 103051 | /*GILLT_nxv4s32*//*Label 6918*/ GIMT_Encode4(264144), |
| 103052 | /*GILLT_nxv4s64*//*Label 6919*/ GIMT_Encode4(264259), GIMT_Encode4(0), |
| 103053 | /*GILLT_nxv8s8*//*Label 6920*/ GIMT_Encode4(264374), |
| 103054 | /*GILLT_nxv8s16*//*Label 6921*/ GIMT_Encode4(264489), |
| 103055 | /*GILLT_nxv8s32*//*Label 6922*/ GIMT_Encode4(264604), |
| 103056 | /*GILLT_nxv8s64*//*Label 6923*/ GIMT_Encode4(264719), GIMT_Encode4(0), |
| 103057 | /*GILLT_nxv16s8*//*Label 6924*/ GIMT_Encode4(264834), |
| 103058 | /*GILLT_nxv16s16*//*Label 6925*/ GIMT_Encode4(264949), |
| 103059 | /*GILLT_nxv16s32*//*Label 6926*/ GIMT_Encode4(265064), GIMT_Encode4(0), |
| 103060 | /*GILLT_nxv32s8*//*Label 6927*/ GIMT_Encode4(265179), |
| 103061 | /*GILLT_nxv32s16*//*Label 6928*/ GIMT_Encode4(265294), GIMT_Encode4(0), |
| 103062 | /*GILLT_nxv64s8*//*Label 6929*/ GIMT_Encode4(265409), |
| 103063 | // Label 6906: @262884 |
| 103064 | GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(262938), |
| 103065 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 103066 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 103067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 103068 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 103069 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 103070 | GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(262922), // Rule ID 64980 // |
| 103071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 103072 | // (smin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_MIN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 103073 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MIN), |
| 103074 | GIR_RootConstrainSelectedInstOperands, |
| 103075 | // GIR_Coverage, 64980, |
| 103076 | GIR_Done, |
| 103077 | // Label 6932: @262922 |
| 103078 | GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(262937), // Rule ID 2679 // |
| 103079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 103080 | // (smin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MIN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 103081 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MIN), |
| 103082 | GIR_RootConstrainSelectedInstOperands, |
| 103083 | // GIR_Coverage, 2679, |
| 103084 | GIR_Done, |
| 103085 | // Label 6933: @262937 |
| 103086 | GIM_Reject, |
| 103087 | // Label 6931: @262938 |
| 103088 | GIM_Reject, |
| 103089 | // Label 6907: @262939 |
| 103090 | GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(262993), |
| 103091 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 103092 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 103093 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 103094 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 103095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 103096 | GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(262977), // Rule ID 64979 // |
| 103097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 103098 | // (smin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (CV_MIN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 103099 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MIN), |
| 103100 | GIR_RootConstrainSelectedInstOperands, |
| 103101 | // GIR_Coverage, 64979, |
| 103102 | GIR_Done, |
| 103103 | // Label 6935: @262977 |
| 103104 | GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(262992), // Rule ID 2678 // |
| 103105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 103106 | // (smin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MIN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 103107 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MIN), |
| 103108 | GIR_RootConstrainSelectedInstOperands, |
| 103109 | // GIR_Coverage, 2678, |
| 103110 | GIR_Done, |
| 103111 | // Label 6936: @262992 |
| 103112 | GIM_Reject, |
| 103113 | // Label 6934: @262993 |
| 103114 | GIM_Reject, |
| 103115 | // Label 6908: @262994 |
| 103116 | GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(263108), |
| 103117 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 103118 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 103119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103120 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103121 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103122 | GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(263062), // Rule ID 51216 // |
| 103123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103124 | // (smin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMIN_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 103125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 103126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF8), |
| 103130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103133 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103137 | GIR_RootConstrainSelectedInstOperands, |
| 103138 | // GIR_Coverage, 51216, |
| 103139 | GIR_EraseRootFromParent_Done, |
| 103140 | // Label 6938: @263062 |
| 103141 | GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(263107), // Rule ID 51217 // |
| 103142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103143 | // (smin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMIN_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 103144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 103145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103147 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF8), |
| 103149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103150 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103151 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103152 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103156 | GIR_RootConstrainSelectedInstOperands, |
| 103157 | // GIR_Coverage, 51217, |
| 103158 | GIR_EraseRootFromParent_Done, |
| 103159 | // Label 6939: @263107 |
| 103160 | GIM_Reject, |
| 103161 | // Label 6937: @263108 |
| 103162 | GIM_Reject, |
| 103163 | // Label 6909: @263109 |
| 103164 | GIM_Try, /*On fail goto*//*Label 6940*/ GIMT_Encode4(263223), |
| 103165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 103166 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 103167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103168 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103169 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103170 | GIM_Try, /*On fail goto*//*Label 6941*/ GIMT_Encode4(263177), // Rule ID 51228 // |
| 103171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103172 | // (smin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMIN_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 103173 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 103174 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103175 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF4), |
| 103178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103179 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103180 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103181 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103185 | GIR_RootConstrainSelectedInstOperands, |
| 103186 | // GIR_Coverage, 51228, |
| 103187 | GIR_EraseRootFromParent_Done, |
| 103188 | // Label 6941: @263177 |
| 103189 | GIM_Try, /*On fail goto*//*Label 6942*/ GIMT_Encode4(263222), // Rule ID 51229 // |
| 103190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103191 | // (smin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMIN_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 103192 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 103193 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103194 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF4), |
| 103197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103199 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103200 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103204 | GIR_RootConstrainSelectedInstOperands, |
| 103205 | // GIR_Coverage, 51229, |
| 103206 | GIR_EraseRootFromParent_Done, |
| 103207 | // Label 6942: @263222 |
| 103208 | GIM_Reject, |
| 103209 | // Label 6940: @263223 |
| 103210 | GIM_Reject, |
| 103211 | // Label 6910: @263224 |
| 103212 | GIM_Try, /*On fail goto*//*Label 6943*/ GIMT_Encode4(263338), |
| 103213 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 103214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 103215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103216 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103218 | GIM_Try, /*On fail goto*//*Label 6944*/ GIMT_Encode4(263292), // Rule ID 51236 // |
| 103219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103220 | // (smin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMIN_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 103221 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 103222 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103223 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF2), |
| 103226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103227 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103228 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103229 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103233 | GIR_RootConstrainSelectedInstOperands, |
| 103234 | // GIR_Coverage, 51236, |
| 103235 | GIR_EraseRootFromParent_Done, |
| 103236 | // Label 6944: @263292 |
| 103237 | GIM_Try, /*On fail goto*//*Label 6945*/ GIMT_Encode4(263337), // Rule ID 51237 // |
| 103238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103239 | // (smin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMIN_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 103240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 103241 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103242 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF2), |
| 103245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103247 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103248 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103252 | GIR_RootConstrainSelectedInstOperands, |
| 103253 | // GIR_Coverage, 51237, |
| 103254 | GIR_EraseRootFromParent_Done, |
| 103255 | // Label 6945: @263337 |
| 103256 | GIM_Reject, |
| 103257 | // Label 6943: @263338 |
| 103258 | GIM_Reject, |
| 103259 | // Label 6911: @263339 |
| 103260 | GIM_Try, /*On fail goto*//*Label 6946*/ GIMT_Encode4(263453), |
| 103261 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 103262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 103263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103264 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103266 | GIM_Try, /*On fail goto*//*Label 6947*/ GIMT_Encode4(263407), // Rule ID 51252 // |
| 103267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 103268 | // (smin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 103269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 103270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103276 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103277 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103281 | GIR_RootConstrainSelectedInstOperands, |
| 103282 | // GIR_Coverage, 51252, |
| 103283 | GIR_EraseRootFromParent_Done, |
| 103284 | // Label 6947: @263407 |
| 103285 | GIM_Try, /*On fail goto*//*Label 6948*/ GIMT_Encode4(263452), // Rule ID 51253 // |
| 103286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 103287 | // (smin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 103288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 103289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103300 | GIR_RootConstrainSelectedInstOperands, |
| 103301 | // GIR_Coverage, 51253, |
| 103302 | GIR_EraseRootFromParent_Done, |
| 103303 | // Label 6948: @263452 |
| 103304 | GIM_Reject, |
| 103305 | // Label 6946: @263453 |
| 103306 | GIM_Reject, |
| 103307 | // Label 6912: @263454 |
| 103308 | GIM_Try, /*On fail goto*//*Label 6949*/ GIMT_Encode4(263568), |
| 103309 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 103310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 103311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103312 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103313 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103314 | GIM_Try, /*On fail goto*//*Label 6950*/ GIMT_Encode4(263522), // Rule ID 51220 // |
| 103315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103316 | // (smin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMIN_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 103317 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 103318 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103319 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103320 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF4), |
| 103322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103323 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103324 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103325 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103329 | GIR_RootConstrainSelectedInstOperands, |
| 103330 | // GIR_Coverage, 51220, |
| 103331 | GIR_EraseRootFromParent_Done, |
| 103332 | // Label 6950: @263522 |
| 103333 | GIM_Try, /*On fail goto*//*Label 6951*/ GIMT_Encode4(263567), // Rule ID 51221 // |
| 103334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103335 | // (smin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMIN_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 103336 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 103337 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103338 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF4), |
| 103341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103342 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103343 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103344 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103348 | GIR_RootConstrainSelectedInstOperands, |
| 103349 | // GIR_Coverage, 51221, |
| 103350 | GIR_EraseRootFromParent_Done, |
| 103351 | // Label 6951: @263567 |
| 103352 | GIM_Reject, |
| 103353 | // Label 6949: @263568 |
| 103354 | GIM_Reject, |
| 103355 | // Label 6913: @263569 |
| 103356 | GIM_Try, /*On fail goto*//*Label 6952*/ GIMT_Encode4(263683), |
| 103357 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 103358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 103359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103362 | GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(263637), // Rule ID 51232 // |
| 103363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103364 | // (smin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMIN_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 103365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 103366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF2), |
| 103370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103371 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103372 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103373 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103377 | GIR_RootConstrainSelectedInstOperands, |
| 103378 | // GIR_Coverage, 51232, |
| 103379 | GIR_EraseRootFromParent_Done, |
| 103380 | // Label 6953: @263637 |
| 103381 | GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(263682), // Rule ID 51233 // |
| 103382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103383 | // (smin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMIN_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 103384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 103385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF2), |
| 103389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103390 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103391 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103392 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103396 | GIR_RootConstrainSelectedInstOperands, |
| 103397 | // GIR_Coverage, 51233, |
| 103398 | GIR_EraseRootFromParent_Done, |
| 103399 | // Label 6954: @263682 |
| 103400 | GIM_Reject, |
| 103401 | // Label 6952: @263683 |
| 103402 | GIM_Reject, |
| 103403 | // Label 6914: @263684 |
| 103404 | GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(263798), |
| 103405 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 103406 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 103407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103409 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103410 | GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(263752), // Rule ID 51248 // |
| 103411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103412 | // (smin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 103413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 103414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103415 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103419 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103420 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103421 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103425 | GIR_RootConstrainSelectedInstOperands, |
| 103426 | // GIR_Coverage, 51248, |
| 103427 | GIR_EraseRootFromParent_Done, |
| 103428 | // Label 6956: @263752 |
| 103429 | GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(263797), // Rule ID 51249 // |
| 103430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103431 | // (smin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 103432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 103433 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103434 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103438 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103439 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103440 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103444 | GIR_RootConstrainSelectedInstOperands, |
| 103445 | // GIR_Coverage, 51249, |
| 103446 | GIR_EraseRootFromParent_Done, |
| 103447 | // Label 6957: @263797 |
| 103448 | GIM_Reject, |
| 103449 | // Label 6955: @263798 |
| 103450 | GIM_Reject, |
| 103451 | // Label 6915: @263799 |
| 103452 | GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(263913), |
| 103453 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 103454 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 103455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103456 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103458 | GIM_Try, /*On fail goto*//*Label 6959*/ GIMT_Encode4(263867), // Rule ID 51292 // |
| 103459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 103460 | // (smin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 103461 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 103462 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103463 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103467 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103468 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103469 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103473 | GIR_RootConstrainSelectedInstOperands, |
| 103474 | // GIR_Coverage, 51292, |
| 103475 | GIR_EraseRootFromParent_Done, |
| 103476 | // Label 6959: @263867 |
| 103477 | GIM_Try, /*On fail goto*//*Label 6960*/ GIMT_Encode4(263912), // Rule ID 51293 // |
| 103478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 103479 | // (smin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 103480 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 103481 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103482 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103486 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103487 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103488 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103492 | GIR_RootConstrainSelectedInstOperands, |
| 103493 | // GIR_Coverage, 51293, |
| 103494 | GIR_EraseRootFromParent_Done, |
| 103495 | // Label 6960: @263912 |
| 103496 | GIM_Reject, |
| 103497 | // Label 6958: @263913 |
| 103498 | GIM_Reject, |
| 103499 | // Label 6916: @263914 |
| 103500 | GIM_Try, /*On fail goto*//*Label 6961*/ GIMT_Encode4(264028), |
| 103501 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 103502 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 103503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103504 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103505 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103506 | GIM_Try, /*On fail goto*//*Label 6962*/ GIMT_Encode4(263982), // Rule ID 51224 // |
| 103507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103508 | // (smin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMIN_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 103509 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 103510 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103511 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF2), |
| 103514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103515 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103516 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103517 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103521 | GIR_RootConstrainSelectedInstOperands, |
| 103522 | // GIR_Coverage, 51224, |
| 103523 | GIR_EraseRootFromParent_Done, |
| 103524 | // Label 6962: @263982 |
| 103525 | GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(264027), // Rule ID 51225 // |
| 103526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103527 | // (smin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMIN_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 103528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 103529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_MF2), |
| 103533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103534 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103535 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103536 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103540 | GIR_RootConstrainSelectedInstOperands, |
| 103541 | // GIR_Coverage, 51225, |
| 103542 | GIR_EraseRootFromParent_Done, |
| 103543 | // Label 6963: @264027 |
| 103544 | GIM_Reject, |
| 103545 | // Label 6961: @264028 |
| 103546 | GIM_Reject, |
| 103547 | // Label 6917: @264029 |
| 103548 | GIM_Try, /*On fail goto*//*Label 6964*/ GIMT_Encode4(264143), |
| 103549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 103550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 103551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103554 | GIM_Try, /*On fail goto*//*Label 6965*/ GIMT_Encode4(264097), // Rule ID 51244 // |
| 103555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103556 | // (smin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 103557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 103558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103564 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103565 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103569 | GIR_RootConstrainSelectedInstOperands, |
| 103570 | // GIR_Coverage, 51244, |
| 103571 | GIR_EraseRootFromParent_Done, |
| 103572 | // Label 6965: @264097 |
| 103573 | GIM_Try, /*On fail goto*//*Label 6966*/ GIMT_Encode4(264142), // Rule ID 51245 // |
| 103574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103575 | // (smin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 103576 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 103577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103579 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103582 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103583 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103584 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103588 | GIR_RootConstrainSelectedInstOperands, |
| 103589 | // GIR_Coverage, 51245, |
| 103590 | GIR_EraseRootFromParent_Done, |
| 103591 | // Label 6966: @264142 |
| 103592 | GIM_Reject, |
| 103593 | // Label 6964: @264143 |
| 103594 | GIM_Reject, |
| 103595 | // Label 6918: @264144 |
| 103596 | GIM_Try, /*On fail goto*//*Label 6967*/ GIMT_Encode4(264258), |
| 103597 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 103598 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 103599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103600 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103601 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103602 | GIM_Try, /*On fail goto*//*Label 6968*/ GIMT_Encode4(264212), // Rule ID 51280 // |
| 103603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103604 | // (smin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 103605 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 103606 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103607 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103608 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103612 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103613 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103617 | GIR_RootConstrainSelectedInstOperands, |
| 103618 | // GIR_Coverage, 51280, |
| 103619 | GIR_EraseRootFromParent_Done, |
| 103620 | // Label 6968: @264212 |
| 103621 | GIM_Try, /*On fail goto*//*Label 6969*/ GIMT_Encode4(264257), // Rule ID 51281 // |
| 103622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103623 | // (smin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 103624 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 103625 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103626 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103627 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103630 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103631 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103632 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103636 | GIR_RootConstrainSelectedInstOperands, |
| 103637 | // GIR_Coverage, 51281, |
| 103638 | GIR_EraseRootFromParent_Done, |
| 103639 | // Label 6969: @264257 |
| 103640 | GIM_Reject, |
| 103641 | // Label 6967: @264258 |
| 103642 | GIM_Reject, |
| 103643 | // Label 6919: @264259 |
| 103644 | GIM_Try, /*On fail goto*//*Label 6970*/ GIMT_Encode4(264373), |
| 103645 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 103646 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 103647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103649 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103650 | GIM_Try, /*On fail goto*//*Label 6971*/ GIMT_Encode4(264327), // Rule ID 51296 // |
| 103651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 103652 | // (smin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 103653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 103654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 103658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103660 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103661 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103665 | GIR_RootConstrainSelectedInstOperands, |
| 103666 | // GIR_Coverage, 51296, |
| 103667 | GIR_EraseRootFromParent_Done, |
| 103668 | // Label 6971: @264327 |
| 103669 | GIM_Try, /*On fail goto*//*Label 6972*/ GIMT_Encode4(264372), // Rule ID 51297 // |
| 103670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 103671 | // (smin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 103672 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 103673 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103674 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 103677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103679 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103680 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103684 | GIR_RootConstrainSelectedInstOperands, |
| 103685 | // GIR_Coverage, 51297, |
| 103686 | GIR_EraseRootFromParent_Done, |
| 103687 | // Label 6972: @264372 |
| 103688 | GIM_Reject, |
| 103689 | // Label 6970: @264373 |
| 103690 | GIM_Reject, |
| 103691 | // Label 6920: @264374 |
| 103692 | GIM_Try, /*On fail goto*//*Label 6973*/ GIMT_Encode4(264488), |
| 103693 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 103694 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 103695 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103696 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103697 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 103698 | GIM_Try, /*On fail goto*//*Label 6974*/ GIMT_Encode4(264442), // Rule ID 51240 // |
| 103699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103700 | // (smin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 103701 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 103702 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103703 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103704 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103707 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103708 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103709 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103713 | GIR_RootConstrainSelectedInstOperands, |
| 103714 | // GIR_Coverage, 51240, |
| 103715 | GIR_EraseRootFromParent_Done, |
| 103716 | // Label 6974: @264442 |
| 103717 | GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(264487), // Rule ID 51241 // |
| 103718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103719 | // (smin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMIN_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 103720 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 103721 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103722 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M1), |
| 103725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103726 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103727 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103728 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103732 | GIR_RootConstrainSelectedInstOperands, |
| 103733 | // GIR_Coverage, 51241, |
| 103734 | GIR_EraseRootFromParent_Done, |
| 103735 | // Label 6975: @264487 |
| 103736 | GIM_Reject, |
| 103737 | // Label 6973: @264488 |
| 103738 | GIM_Reject, |
| 103739 | // Label 6921: @264489 |
| 103740 | GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(264603), |
| 103741 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 103742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 103743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103744 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103746 | GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(264557), // Rule ID 51268 // |
| 103747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103748 | // (smin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 103749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 103750 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103751 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103752 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103755 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103756 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103757 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103761 | GIR_RootConstrainSelectedInstOperands, |
| 103762 | // GIR_Coverage, 51268, |
| 103763 | GIR_EraseRootFromParent_Done, |
| 103764 | // Label 6977: @264557 |
| 103765 | GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(264602), // Rule ID 51269 // |
| 103766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103767 | // (smin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 103768 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 103769 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103770 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103771 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103774 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103775 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103776 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103780 | GIR_RootConstrainSelectedInstOperands, |
| 103781 | // GIR_Coverage, 51269, |
| 103782 | GIR_EraseRootFromParent_Done, |
| 103783 | // Label 6978: @264602 |
| 103784 | GIM_Reject, |
| 103785 | // Label 6976: @264603 |
| 103786 | GIM_Reject, |
| 103787 | // Label 6922: @264604 |
| 103788 | GIM_Try, /*On fail goto*//*Label 6979*/ GIMT_Encode4(264718), |
| 103789 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 103790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 103791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103792 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103793 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103794 | GIM_Try, /*On fail goto*//*Label 6980*/ GIMT_Encode4(264672), // Rule ID 51284 // |
| 103795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103796 | // (smin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 103797 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 103798 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103799 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103800 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 103802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103803 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103804 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103805 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103809 | GIR_RootConstrainSelectedInstOperands, |
| 103810 | // GIR_Coverage, 51284, |
| 103811 | GIR_EraseRootFromParent_Done, |
| 103812 | // Label 6980: @264672 |
| 103813 | GIM_Try, /*On fail goto*//*Label 6981*/ GIMT_Encode4(264717), // Rule ID 51285 // |
| 103814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103815 | // (smin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 103816 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 103817 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103818 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103819 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 103821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103822 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103823 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103824 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 103827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103828 | GIR_RootConstrainSelectedInstOperands, |
| 103829 | // GIR_Coverage, 51285, |
| 103830 | GIR_EraseRootFromParent_Done, |
| 103831 | // Label 6981: @264717 |
| 103832 | GIM_Reject, |
| 103833 | // Label 6979: @264718 |
| 103834 | GIM_Reject, |
| 103835 | // Label 6923: @264719 |
| 103836 | GIM_Try, /*On fail goto*//*Label 6982*/ GIMT_Encode4(264833), |
| 103837 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 103838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 103839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 103840 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 103841 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 103842 | GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(264787), // Rule ID 51300 // |
| 103843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 103844 | // (smin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 103845 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 103846 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103847 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 103850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103851 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103852 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103853 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103857 | GIR_RootConstrainSelectedInstOperands, |
| 103858 | // GIR_Coverage, 51300, |
| 103859 | GIR_EraseRootFromParent_Done, |
| 103860 | // Label 6983: @264787 |
| 103861 | GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(264832), // Rule ID 51301 // |
| 103862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 103863 | // (smin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 103864 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 103865 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103866 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 103869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103870 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103871 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 103875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103876 | GIR_RootConstrainSelectedInstOperands, |
| 103877 | // GIR_Coverage, 51301, |
| 103878 | GIR_EraseRootFromParent_Done, |
| 103879 | // Label 6984: @264832 |
| 103880 | GIM_Reject, |
| 103881 | // Label 6982: @264833 |
| 103882 | GIM_Reject, |
| 103883 | // Label 6924: @264834 |
| 103884 | GIM_Try, /*On fail goto*//*Label 6985*/ GIMT_Encode4(264948), |
| 103885 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 103886 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 103887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 103890 | GIM_Try, /*On fail goto*//*Label 6986*/ GIMT_Encode4(264902), // Rule ID 51256 // |
| 103891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103892 | // (smin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 103893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 103894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103900 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103901 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103905 | GIR_RootConstrainSelectedInstOperands, |
| 103906 | // GIR_Coverage, 51256, |
| 103907 | GIR_EraseRootFromParent_Done, |
| 103908 | // Label 6986: @264902 |
| 103909 | GIM_Try, /*On fail goto*//*Label 6987*/ GIMT_Encode4(264947), // Rule ID 51257 // |
| 103910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103911 | // (smin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMIN_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 103912 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 103913 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103914 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M2), |
| 103917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103918 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103919 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103920 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103924 | GIR_RootConstrainSelectedInstOperands, |
| 103925 | // GIR_Coverage, 51257, |
| 103926 | GIR_EraseRootFromParent_Done, |
| 103927 | // Label 6987: @264947 |
| 103928 | GIM_Reject, |
| 103929 | // Label 6985: @264948 |
| 103930 | GIM_Reject, |
| 103931 | // Label 6925: @264949 |
| 103932 | GIM_Try, /*On fail goto*//*Label 6988*/ GIMT_Encode4(265063), |
| 103933 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 103934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 103935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103937 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 103938 | GIM_Try, /*On fail goto*//*Label 6989*/ GIMT_Encode4(265017), // Rule ID 51272 // |
| 103939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103940 | // (smin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 103941 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 103942 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103943 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103944 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 103946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103947 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103948 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103949 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103953 | GIR_RootConstrainSelectedInstOperands, |
| 103954 | // GIR_Coverage, 51272, |
| 103955 | GIR_EraseRootFromParent_Done, |
| 103956 | // Label 6989: @265017 |
| 103957 | GIM_Try, /*On fail goto*//*Label 6990*/ GIMT_Encode4(265062), // Rule ID 51273 // |
| 103958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 103959 | // (smin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 103960 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 103961 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103962 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103963 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 103965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103966 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103967 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103968 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 103971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 103972 | GIR_RootConstrainSelectedInstOperands, |
| 103973 | // GIR_Coverage, 51273, |
| 103974 | GIR_EraseRootFromParent_Done, |
| 103975 | // Label 6990: @265062 |
| 103976 | GIM_Reject, |
| 103977 | // Label 6988: @265063 |
| 103978 | GIM_Reject, |
| 103979 | // Label 6926: @265064 |
| 103980 | GIM_Try, /*On fail goto*//*Label 6991*/ GIMT_Encode4(265178), |
| 103981 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 103982 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 103983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 103984 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 103985 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 103986 | GIM_Try, /*On fail goto*//*Label 6992*/ GIMT_Encode4(265132), // Rule ID 51288 // |
| 103987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 103988 | // (smin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 103989 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 103990 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 103991 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 103992 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 103993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 103994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 103995 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 103996 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 103997 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 103998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 103999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104001 | GIR_RootConstrainSelectedInstOperands, |
| 104002 | // GIR_Coverage, 51288, |
| 104003 | GIR_EraseRootFromParent_Done, |
| 104004 | // Label 6992: @265132 |
| 104005 | GIM_Try, /*On fail goto*//*Label 6993*/ GIMT_Encode4(265177), // Rule ID 51289 // |
| 104006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104007 | // (smin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 104008 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 104009 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104010 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 104013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104014 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104015 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104016 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104020 | GIR_RootConstrainSelectedInstOperands, |
| 104021 | // GIR_Coverage, 51289, |
| 104022 | GIR_EraseRootFromParent_Done, |
| 104023 | // Label 6993: @265177 |
| 104024 | GIM_Reject, |
| 104025 | // Label 6991: @265178 |
| 104026 | GIM_Reject, |
| 104027 | // Label 6927: @265179 |
| 104028 | GIM_Try, /*On fail goto*//*Label 6994*/ GIMT_Encode4(265293), |
| 104029 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 104030 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 104031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104032 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104033 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104034 | GIM_Try, /*On fail goto*//*Label 6995*/ GIMT_Encode4(265247), // Rule ID 51260 // |
| 104035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104036 | // (smin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 104037 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 104038 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104039 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 104042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104043 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104044 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104045 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104049 | GIR_RootConstrainSelectedInstOperands, |
| 104050 | // GIR_Coverage, 51260, |
| 104051 | GIR_EraseRootFromParent_Done, |
| 104052 | // Label 6995: @265247 |
| 104053 | GIM_Try, /*On fail goto*//*Label 6996*/ GIMT_Encode4(265292), // Rule ID 51261 // |
| 104054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104055 | // (smin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMIN_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 104056 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 104057 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104058 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M4), |
| 104061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104063 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104068 | GIR_RootConstrainSelectedInstOperands, |
| 104069 | // GIR_Coverage, 51261, |
| 104070 | GIR_EraseRootFromParent_Done, |
| 104071 | // Label 6996: @265292 |
| 104072 | GIM_Reject, |
| 104073 | // Label 6994: @265293 |
| 104074 | GIM_Reject, |
| 104075 | // Label 6928: @265294 |
| 104076 | GIM_Try, /*On fail goto*//*Label 6997*/ GIMT_Encode4(265408), |
| 104077 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 104078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 104079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104080 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104081 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104082 | GIM_Try, /*On fail goto*//*Label 6998*/ GIMT_Encode4(265362), // Rule ID 51276 // |
| 104083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104084 | // (smin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 104085 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 104086 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104087 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 104090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104091 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104092 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104093 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104097 | GIR_RootConstrainSelectedInstOperands, |
| 104098 | // GIR_Coverage, 51276, |
| 104099 | GIR_EraseRootFromParent_Done, |
| 104100 | // Label 6998: @265362 |
| 104101 | GIM_Try, /*On fail goto*//*Label 6999*/ GIMT_Encode4(265407), // Rule ID 51277 // |
| 104102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104103 | // (smin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 104104 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 104105 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104106 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 104109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104110 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104111 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104112 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104116 | GIR_RootConstrainSelectedInstOperands, |
| 104117 | // GIR_Coverage, 51277, |
| 104118 | GIR_EraseRootFromParent_Done, |
| 104119 | // Label 6999: @265407 |
| 104120 | GIM_Reject, |
| 104121 | // Label 6997: @265408 |
| 104122 | GIM_Reject, |
| 104123 | // Label 6929: @265409 |
| 104124 | GIM_Try, /*On fail goto*//*Label 7000*/ GIMT_Encode4(265523), |
| 104125 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 104126 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 104127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104129 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104130 | GIM_Try, /*On fail goto*//*Label 7001*/ GIMT_Encode4(265477), // Rule ID 51264 // |
| 104131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104132 | // (smin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 104133 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 104134 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104135 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 104138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104139 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104140 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104141 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104145 | GIR_RootConstrainSelectedInstOperands, |
| 104146 | // GIR_Coverage, 51264, |
| 104147 | GIR_EraseRootFromParent_Done, |
| 104148 | // Label 7001: @265477 |
| 104149 | GIM_Try, /*On fail goto*//*Label 7002*/ GIMT_Encode4(265522), // Rule ID 51265 // |
| 104150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104151 | // (smin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMIN_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 104152 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 104153 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104154 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMIN_VV_M8), |
| 104157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104159 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104160 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104164 | GIR_RootConstrainSelectedInstOperands, |
| 104165 | // GIR_Coverage, 51265, |
| 104166 | GIR_EraseRootFromParent_Done, |
| 104167 | // Label 7002: @265522 |
| 104168 | GIM_Reject, |
| 104169 | // Label 7000: @265523 |
| 104170 | GIM_Reject, |
| 104171 | // Label 6930: @265524 |
| 104172 | GIM_Reject, |
| 104173 | // Label 72: @265525 |
| 104174 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7027*/ GIMT_Encode4(268300), |
| 104175 | /*GILLT_s32*//*Label 7003*/ GIMT_Encode4(265660), |
| 104176 | /*GILLT_s64*//*Label 7004*/ GIMT_Encode4(265715), GIMT_Encode4(0), |
| 104177 | /*GILLT_nxv1s8*//*Label 7005*/ GIMT_Encode4(265770), |
| 104178 | /*GILLT_nxv1s16*//*Label 7006*/ GIMT_Encode4(265885), |
| 104179 | /*GILLT_nxv1s32*//*Label 7007*/ GIMT_Encode4(266000), |
| 104180 | /*GILLT_nxv1s64*//*Label 7008*/ GIMT_Encode4(266115), GIMT_Encode4(0), |
| 104181 | /*GILLT_nxv2s8*//*Label 7009*/ GIMT_Encode4(266230), |
| 104182 | /*GILLT_nxv2s16*//*Label 7010*/ GIMT_Encode4(266345), |
| 104183 | /*GILLT_nxv2s32*//*Label 7011*/ GIMT_Encode4(266460), |
| 104184 | /*GILLT_nxv2s64*//*Label 7012*/ GIMT_Encode4(266575), GIMT_Encode4(0), |
| 104185 | /*GILLT_nxv4s8*//*Label 7013*/ GIMT_Encode4(266690), |
| 104186 | /*GILLT_nxv4s16*//*Label 7014*/ GIMT_Encode4(266805), |
| 104187 | /*GILLT_nxv4s32*//*Label 7015*/ GIMT_Encode4(266920), |
| 104188 | /*GILLT_nxv4s64*//*Label 7016*/ GIMT_Encode4(267035), GIMT_Encode4(0), |
| 104189 | /*GILLT_nxv8s8*//*Label 7017*/ GIMT_Encode4(267150), |
| 104190 | /*GILLT_nxv8s16*//*Label 7018*/ GIMT_Encode4(267265), |
| 104191 | /*GILLT_nxv8s32*//*Label 7019*/ GIMT_Encode4(267380), |
| 104192 | /*GILLT_nxv8s64*//*Label 7020*/ GIMT_Encode4(267495), GIMT_Encode4(0), |
| 104193 | /*GILLT_nxv16s8*//*Label 7021*/ GIMT_Encode4(267610), |
| 104194 | /*GILLT_nxv16s16*//*Label 7022*/ GIMT_Encode4(267725), |
| 104195 | /*GILLT_nxv16s32*//*Label 7023*/ GIMT_Encode4(267840), GIMT_Encode4(0), |
| 104196 | /*GILLT_nxv32s8*//*Label 7024*/ GIMT_Encode4(267955), |
| 104197 | /*GILLT_nxv32s16*//*Label 7025*/ GIMT_Encode4(268070), GIMT_Encode4(0), |
| 104198 | /*GILLT_nxv64s8*//*Label 7026*/ GIMT_Encode4(268185), |
| 104199 | // Label 7003: @265660 |
| 104200 | GIM_Try, /*On fail goto*//*Label 7028*/ GIMT_Encode4(265714), |
| 104201 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 104202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 104203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 104204 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 104205 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 104206 | GIM_Try, /*On fail goto*//*Label 7029*/ GIMT_Encode4(265698), // Rule ID 64984 // |
| 104207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 104208 | // (smax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_MAX:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 104209 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MAX), |
| 104210 | GIR_RootConstrainSelectedInstOperands, |
| 104211 | // GIR_Coverage, 64984, |
| 104212 | GIR_Done, |
| 104213 | // Label 7029: @265698 |
| 104214 | GIM_Try, /*On fail goto*//*Label 7030*/ GIMT_Encode4(265713), // Rule ID 2681 // |
| 104215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 104216 | // (smax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MAX:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 104217 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MAX), |
| 104218 | GIR_RootConstrainSelectedInstOperands, |
| 104219 | // GIR_Coverage, 2681, |
| 104220 | GIR_Done, |
| 104221 | // Label 7030: @265713 |
| 104222 | GIM_Reject, |
| 104223 | // Label 7028: @265714 |
| 104224 | GIM_Reject, |
| 104225 | // Label 7004: @265715 |
| 104226 | GIM_Try, /*On fail goto*//*Label 7031*/ GIMT_Encode4(265769), |
| 104227 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 104228 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 104229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 104230 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 104231 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 104232 | GIM_Try, /*On fail goto*//*Label 7032*/ GIMT_Encode4(265753), // Rule ID 64983 // |
| 104233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 104234 | // (smax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (CV_MAX:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 104235 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MAX), |
| 104236 | GIR_RootConstrainSelectedInstOperands, |
| 104237 | // GIR_Coverage, 64983, |
| 104238 | GIR_Done, |
| 104239 | // Label 7032: @265753 |
| 104240 | GIM_Try, /*On fail goto*//*Label 7033*/ GIMT_Encode4(265768), // Rule ID 2680 // |
| 104241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 104242 | // (smax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MAX:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 104243 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MAX), |
| 104244 | GIR_RootConstrainSelectedInstOperands, |
| 104245 | // GIR_Coverage, 2680, |
| 104246 | GIR_Done, |
| 104247 | // Label 7033: @265768 |
| 104248 | GIM_Reject, |
| 104249 | // Label 7031: @265769 |
| 104250 | GIM_Reject, |
| 104251 | // Label 7005: @265770 |
| 104252 | GIM_Try, /*On fail goto*//*Label 7034*/ GIMT_Encode4(265884), |
| 104253 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 104254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 104255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104258 | GIM_Try, /*On fail goto*//*Label 7035*/ GIMT_Encode4(265838), // Rule ID 51392 // |
| 104259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104260 | // (smax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMAX_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 104261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 104262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF8), |
| 104266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104268 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104269 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104273 | GIR_RootConstrainSelectedInstOperands, |
| 104274 | // GIR_Coverage, 51392, |
| 104275 | GIR_EraseRootFromParent_Done, |
| 104276 | // Label 7035: @265838 |
| 104277 | GIM_Try, /*On fail goto*//*Label 7036*/ GIMT_Encode4(265883), // Rule ID 51393 // |
| 104278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104279 | // (smax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMAX_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 104280 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 104281 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104282 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF8), |
| 104285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104286 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104287 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104288 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104292 | GIR_RootConstrainSelectedInstOperands, |
| 104293 | // GIR_Coverage, 51393, |
| 104294 | GIR_EraseRootFromParent_Done, |
| 104295 | // Label 7036: @265883 |
| 104296 | GIM_Reject, |
| 104297 | // Label 7034: @265884 |
| 104298 | GIM_Reject, |
| 104299 | // Label 7006: @265885 |
| 104300 | GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(265999), |
| 104301 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 104302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 104303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104304 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104305 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104306 | GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(265953), // Rule ID 51404 // |
| 104307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104308 | // (smax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMAX_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 104309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 104310 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104311 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF4), |
| 104314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104315 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104317 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104321 | GIR_RootConstrainSelectedInstOperands, |
| 104322 | // GIR_Coverage, 51404, |
| 104323 | GIR_EraseRootFromParent_Done, |
| 104324 | // Label 7038: @265953 |
| 104325 | GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(265998), // Rule ID 51405 // |
| 104326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104327 | // (smax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMAX_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 104328 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 104329 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104330 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF4), |
| 104333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104334 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104335 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104336 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104340 | GIR_RootConstrainSelectedInstOperands, |
| 104341 | // GIR_Coverage, 51405, |
| 104342 | GIR_EraseRootFromParent_Done, |
| 104343 | // Label 7039: @265998 |
| 104344 | GIM_Reject, |
| 104345 | // Label 7037: @265999 |
| 104346 | GIM_Reject, |
| 104347 | // Label 7007: @266000 |
| 104348 | GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(266114), |
| 104349 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 104350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 104351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104352 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104354 | GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(266068), // Rule ID 51412 // |
| 104355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104356 | // (smax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMAX_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 104357 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 104358 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104359 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF2), |
| 104362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104363 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104364 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104365 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104369 | GIR_RootConstrainSelectedInstOperands, |
| 104370 | // GIR_Coverage, 51412, |
| 104371 | GIR_EraseRootFromParent_Done, |
| 104372 | // Label 7041: @266068 |
| 104373 | GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(266113), // Rule ID 51413 // |
| 104374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104375 | // (smax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMAX_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 104376 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 104377 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104378 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF2), |
| 104381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104382 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104383 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104384 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104388 | GIR_RootConstrainSelectedInstOperands, |
| 104389 | // GIR_Coverage, 51413, |
| 104390 | GIR_EraseRootFromParent_Done, |
| 104391 | // Label 7042: @266113 |
| 104392 | GIM_Reject, |
| 104393 | // Label 7040: @266114 |
| 104394 | GIM_Reject, |
| 104395 | // Label 7008: @266115 |
| 104396 | GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(266229), |
| 104397 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 104398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 104399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104400 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104402 | GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(266183), // Rule ID 51428 // |
| 104403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 104404 | // (smax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 104405 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 104406 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104407 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104411 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104412 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104413 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104417 | GIR_RootConstrainSelectedInstOperands, |
| 104418 | // GIR_Coverage, 51428, |
| 104419 | GIR_EraseRootFromParent_Done, |
| 104420 | // Label 7044: @266183 |
| 104421 | GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(266228), // Rule ID 51429 // |
| 104422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 104423 | // (smax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 104424 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 104425 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104431 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104432 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104436 | GIR_RootConstrainSelectedInstOperands, |
| 104437 | // GIR_Coverage, 51429, |
| 104438 | GIR_EraseRootFromParent_Done, |
| 104439 | // Label 7045: @266228 |
| 104440 | GIM_Reject, |
| 104441 | // Label 7043: @266229 |
| 104442 | GIM_Reject, |
| 104443 | // Label 7009: @266230 |
| 104444 | GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(266344), |
| 104445 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 104446 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 104447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104450 | GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(266298), // Rule ID 51396 // |
| 104451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104452 | // (smax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMAX_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 104453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 104454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF4), |
| 104458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104460 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104461 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104465 | GIR_RootConstrainSelectedInstOperands, |
| 104466 | // GIR_Coverage, 51396, |
| 104467 | GIR_EraseRootFromParent_Done, |
| 104468 | // Label 7047: @266298 |
| 104469 | GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(266343), // Rule ID 51397 // |
| 104470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104471 | // (smax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMAX_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 104472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 104473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF4), |
| 104477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104479 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104480 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104484 | GIR_RootConstrainSelectedInstOperands, |
| 104485 | // GIR_Coverage, 51397, |
| 104486 | GIR_EraseRootFromParent_Done, |
| 104487 | // Label 7048: @266343 |
| 104488 | GIM_Reject, |
| 104489 | // Label 7046: @266344 |
| 104490 | GIM_Reject, |
| 104491 | // Label 7010: @266345 |
| 104492 | GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(266459), |
| 104493 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 104494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 104495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104496 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104497 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104498 | GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(266413), // Rule ID 51408 // |
| 104499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104500 | // (smax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMAX_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 104501 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 104502 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104503 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF2), |
| 104506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104507 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104508 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104509 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104513 | GIR_RootConstrainSelectedInstOperands, |
| 104514 | // GIR_Coverage, 51408, |
| 104515 | GIR_EraseRootFromParent_Done, |
| 104516 | // Label 7050: @266413 |
| 104517 | GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(266458), // Rule ID 51409 // |
| 104518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104519 | // (smax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMAX_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 104520 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 104521 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104522 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104523 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF2), |
| 104525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104526 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104527 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104528 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104532 | GIR_RootConstrainSelectedInstOperands, |
| 104533 | // GIR_Coverage, 51409, |
| 104534 | GIR_EraseRootFromParent_Done, |
| 104535 | // Label 7051: @266458 |
| 104536 | GIM_Reject, |
| 104537 | // Label 7049: @266459 |
| 104538 | GIM_Reject, |
| 104539 | // Label 7011: @266460 |
| 104540 | GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(266574), |
| 104541 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 104542 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 104543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104544 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104545 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104546 | GIM_Try, /*On fail goto*//*Label 7053*/ GIMT_Encode4(266528), // Rule ID 51424 // |
| 104547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104548 | // (smax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 104549 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 104550 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104551 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104555 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104556 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104557 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104561 | GIR_RootConstrainSelectedInstOperands, |
| 104562 | // GIR_Coverage, 51424, |
| 104563 | GIR_EraseRootFromParent_Done, |
| 104564 | // Label 7053: @266528 |
| 104565 | GIM_Try, /*On fail goto*//*Label 7054*/ GIMT_Encode4(266573), // Rule ID 51425 // |
| 104566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104567 | // (smax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 104568 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 104569 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104570 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104574 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104575 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104576 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104580 | GIR_RootConstrainSelectedInstOperands, |
| 104581 | // GIR_Coverage, 51425, |
| 104582 | GIR_EraseRootFromParent_Done, |
| 104583 | // Label 7054: @266573 |
| 104584 | GIM_Reject, |
| 104585 | // Label 7052: @266574 |
| 104586 | GIM_Reject, |
| 104587 | // Label 7012: @266575 |
| 104588 | GIM_Try, /*On fail goto*//*Label 7055*/ GIMT_Encode4(266689), |
| 104589 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 104590 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 104591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104592 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104594 | GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(266643), // Rule ID 51468 // |
| 104595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 104596 | // (smax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 104597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 104598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104600 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 104602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104604 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104605 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104609 | GIR_RootConstrainSelectedInstOperands, |
| 104610 | // GIR_Coverage, 51468, |
| 104611 | GIR_EraseRootFromParent_Done, |
| 104612 | // Label 7056: @266643 |
| 104613 | GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(266688), // Rule ID 51469 // |
| 104614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 104615 | // (smax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 104616 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 104617 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104618 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104619 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 104621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104622 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104623 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104624 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104628 | GIR_RootConstrainSelectedInstOperands, |
| 104629 | // GIR_Coverage, 51469, |
| 104630 | GIR_EraseRootFromParent_Done, |
| 104631 | // Label 7057: @266688 |
| 104632 | GIM_Reject, |
| 104633 | // Label 7055: @266689 |
| 104634 | GIM_Reject, |
| 104635 | // Label 7013: @266690 |
| 104636 | GIM_Try, /*On fail goto*//*Label 7058*/ GIMT_Encode4(266804), |
| 104637 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 104638 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 104639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104640 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104641 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104642 | GIM_Try, /*On fail goto*//*Label 7059*/ GIMT_Encode4(266758), // Rule ID 51400 // |
| 104643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104644 | // (smax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMAX_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 104645 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 104646 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104647 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104648 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF2), |
| 104650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104651 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104652 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104653 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104657 | GIR_RootConstrainSelectedInstOperands, |
| 104658 | // GIR_Coverage, 51400, |
| 104659 | GIR_EraseRootFromParent_Done, |
| 104660 | // Label 7059: @266758 |
| 104661 | GIM_Try, /*On fail goto*//*Label 7060*/ GIMT_Encode4(266803), // Rule ID 51401 // |
| 104662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104663 | // (smax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMAX_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 104664 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 104665 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104666 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104667 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_MF2), |
| 104669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104671 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104672 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104676 | GIR_RootConstrainSelectedInstOperands, |
| 104677 | // GIR_Coverage, 51401, |
| 104678 | GIR_EraseRootFromParent_Done, |
| 104679 | // Label 7060: @266803 |
| 104680 | GIM_Reject, |
| 104681 | // Label 7058: @266804 |
| 104682 | GIM_Reject, |
| 104683 | // Label 7014: @266805 |
| 104684 | GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(266919), |
| 104685 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 104686 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 104687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104688 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104689 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104690 | GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(266873), // Rule ID 51420 // |
| 104691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104692 | // (smax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 104693 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 104694 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104695 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104699 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104700 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104701 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104705 | GIR_RootConstrainSelectedInstOperands, |
| 104706 | // GIR_Coverage, 51420, |
| 104707 | GIR_EraseRootFromParent_Done, |
| 104708 | // Label 7062: @266873 |
| 104709 | GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(266918), // Rule ID 51421 // |
| 104710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104711 | // (smax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 104712 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 104713 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104714 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104718 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104719 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104720 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104724 | GIR_RootConstrainSelectedInstOperands, |
| 104725 | // GIR_Coverage, 51421, |
| 104726 | GIR_EraseRootFromParent_Done, |
| 104727 | // Label 7063: @266918 |
| 104728 | GIM_Reject, |
| 104729 | // Label 7061: @266919 |
| 104730 | GIM_Reject, |
| 104731 | // Label 7015: @266920 |
| 104732 | GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(267034), |
| 104733 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 104734 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 104735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104738 | GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(266988), // Rule ID 51456 // |
| 104739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104740 | // (smax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 104741 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 104742 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104743 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 104746 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104747 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104748 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104749 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104753 | GIR_RootConstrainSelectedInstOperands, |
| 104754 | // GIR_Coverage, 51456, |
| 104755 | GIR_EraseRootFromParent_Done, |
| 104756 | // Label 7065: @266988 |
| 104757 | GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(267033), // Rule ID 51457 // |
| 104758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104759 | // (smax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 104760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 104761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104762 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 104765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104767 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104768 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104772 | GIR_RootConstrainSelectedInstOperands, |
| 104773 | // GIR_Coverage, 51457, |
| 104774 | GIR_EraseRootFromParent_Done, |
| 104775 | // Label 7066: @267033 |
| 104776 | GIM_Reject, |
| 104777 | // Label 7064: @267034 |
| 104778 | GIM_Reject, |
| 104779 | // Label 7016: @267035 |
| 104780 | GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(267149), |
| 104781 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 104782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 104783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104784 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104785 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104786 | GIM_Try, /*On fail goto*//*Label 7068*/ GIMT_Encode4(267103), // Rule ID 51472 // |
| 104787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 104788 | // (smax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 104789 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 104790 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104791 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104792 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 104794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104795 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104796 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104797 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104801 | GIR_RootConstrainSelectedInstOperands, |
| 104802 | // GIR_Coverage, 51472, |
| 104803 | GIR_EraseRootFromParent_Done, |
| 104804 | // Label 7068: @267103 |
| 104805 | GIM_Try, /*On fail goto*//*Label 7069*/ GIMT_Encode4(267148), // Rule ID 51473 // |
| 104806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 104807 | // (smax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 104808 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 104809 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104810 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 104813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104814 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104815 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104816 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104820 | GIR_RootConstrainSelectedInstOperands, |
| 104821 | // GIR_Coverage, 51473, |
| 104822 | GIR_EraseRootFromParent_Done, |
| 104823 | // Label 7069: @267148 |
| 104824 | GIM_Reject, |
| 104825 | // Label 7067: @267149 |
| 104826 | GIM_Reject, |
| 104827 | // Label 7017: @267150 |
| 104828 | GIM_Try, /*On fail goto*//*Label 7070*/ GIMT_Encode4(267264), |
| 104829 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 104830 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 104831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104832 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104833 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 104834 | GIM_Try, /*On fail goto*//*Label 7071*/ GIMT_Encode4(267218), // Rule ID 51416 // |
| 104835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104836 | // (smax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 104837 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 104838 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104839 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104843 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104844 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104845 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104849 | GIR_RootConstrainSelectedInstOperands, |
| 104850 | // GIR_Coverage, 51416, |
| 104851 | GIR_EraseRootFromParent_Done, |
| 104852 | // Label 7071: @267218 |
| 104853 | GIM_Try, /*On fail goto*//*Label 7072*/ GIMT_Encode4(267263), // Rule ID 51417 // |
| 104854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104855 | // (smax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMAX_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 104856 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 104857 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104858 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104859 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M1), |
| 104861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104862 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104863 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104864 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104868 | GIR_RootConstrainSelectedInstOperands, |
| 104869 | // GIR_Coverage, 51417, |
| 104870 | GIR_EraseRootFromParent_Done, |
| 104871 | // Label 7072: @267263 |
| 104872 | GIM_Reject, |
| 104873 | // Label 7070: @267264 |
| 104874 | GIM_Reject, |
| 104875 | // Label 7018: @267265 |
| 104876 | GIM_Try, /*On fail goto*//*Label 7073*/ GIMT_Encode4(267379), |
| 104877 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 104878 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 104879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104880 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104881 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 104882 | GIM_Try, /*On fail goto*//*Label 7074*/ GIMT_Encode4(267333), // Rule ID 51444 // |
| 104883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104884 | // (smax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 104885 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 104886 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104887 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 104890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104891 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104892 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104893 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104897 | GIR_RootConstrainSelectedInstOperands, |
| 104898 | // GIR_Coverage, 51444, |
| 104899 | GIR_EraseRootFromParent_Done, |
| 104900 | // Label 7074: @267333 |
| 104901 | GIM_Try, /*On fail goto*//*Label 7075*/ GIMT_Encode4(267378), // Rule ID 51445 // |
| 104902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104903 | // (smax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 104904 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 104905 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104906 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 104909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104910 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104911 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104912 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 104915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104916 | GIR_RootConstrainSelectedInstOperands, |
| 104917 | // GIR_Coverage, 51445, |
| 104918 | GIR_EraseRootFromParent_Done, |
| 104919 | // Label 7075: @267378 |
| 104920 | GIM_Reject, |
| 104921 | // Label 7073: @267379 |
| 104922 | GIM_Reject, |
| 104923 | // Label 7019: @267380 |
| 104924 | GIM_Try, /*On fail goto*//*Label 7076*/ GIMT_Encode4(267494), |
| 104925 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 104926 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 104927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104928 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 104930 | GIM_Try, /*On fail goto*//*Label 7077*/ GIMT_Encode4(267448), // Rule ID 51460 // |
| 104931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 104932 | // (smax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 104933 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 104934 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104935 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104936 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 104938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104940 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104941 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104945 | GIR_RootConstrainSelectedInstOperands, |
| 104946 | // GIR_Coverage, 51460, |
| 104947 | GIR_EraseRootFromParent_Done, |
| 104948 | // Label 7077: @267448 |
| 104949 | GIM_Try, /*On fail goto*//*Label 7078*/ GIMT_Encode4(267493), // Rule ID 51461 // |
| 104950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 104951 | // (smax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 104952 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 104953 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104954 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104955 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 104957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104958 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104959 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104960 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 104963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104964 | GIR_RootConstrainSelectedInstOperands, |
| 104965 | // GIR_Coverage, 51461, |
| 104966 | GIR_EraseRootFromParent_Done, |
| 104967 | // Label 7078: @267493 |
| 104968 | GIM_Reject, |
| 104969 | // Label 7076: @267494 |
| 104970 | GIM_Reject, |
| 104971 | // Label 7020: @267495 |
| 104972 | GIM_Try, /*On fail goto*//*Label 7079*/ GIMT_Encode4(267609), |
| 104973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 104974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 104975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104976 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104977 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 104978 | GIM_Try, /*On fail goto*//*Label 7080*/ GIMT_Encode4(267563), // Rule ID 51476 // |
| 104979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 104980 | // (smax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 104981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 104982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 104983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 104984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 104985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 104986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 104987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 104988 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 104989 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 104990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 104991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 104992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 104993 | GIR_RootConstrainSelectedInstOperands, |
| 104994 | // GIR_Coverage, 51476, |
| 104995 | GIR_EraseRootFromParent_Done, |
| 104996 | // Label 7080: @267563 |
| 104997 | GIM_Try, /*On fail goto*//*Label 7081*/ GIMT_Encode4(267608), // Rule ID 51477 // |
| 104998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 104999 | // (smax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 105000 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 105001 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105002 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105003 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105006 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105007 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105008 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105012 | GIR_RootConstrainSelectedInstOperands, |
| 105013 | // GIR_Coverage, 51477, |
| 105014 | GIR_EraseRootFromParent_Done, |
| 105015 | // Label 7081: @267608 |
| 105016 | GIM_Reject, |
| 105017 | // Label 7079: @267609 |
| 105018 | GIM_Reject, |
| 105019 | // Label 7021: @267610 |
| 105020 | GIM_Try, /*On fail goto*//*Label 7082*/ GIMT_Encode4(267724), |
| 105021 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 105022 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 105023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105024 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105025 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105026 | GIM_Try, /*On fail goto*//*Label 7083*/ GIMT_Encode4(267678), // Rule ID 51432 // |
| 105027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105028 | // (smax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105029 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 105030 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105031 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105032 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 105034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105035 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105036 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105037 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105041 | GIR_RootConstrainSelectedInstOperands, |
| 105042 | // GIR_Coverage, 51432, |
| 105043 | GIR_EraseRootFromParent_Done, |
| 105044 | // Label 7083: @267678 |
| 105045 | GIM_Try, /*On fail goto*//*Label 7084*/ GIMT_Encode4(267723), // Rule ID 51433 // |
| 105046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105047 | // (smax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMAX_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105048 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 105049 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105050 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M2), |
| 105053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105054 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105055 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105056 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105060 | GIR_RootConstrainSelectedInstOperands, |
| 105061 | // GIR_Coverage, 51433, |
| 105062 | GIR_EraseRootFromParent_Done, |
| 105063 | // Label 7084: @267723 |
| 105064 | GIM_Reject, |
| 105065 | // Label 7082: @267724 |
| 105066 | GIM_Reject, |
| 105067 | // Label 7022: @267725 |
| 105068 | GIM_Try, /*On fail goto*//*Label 7085*/ GIMT_Encode4(267839), |
| 105069 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 105070 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 105071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105072 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105073 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105074 | GIM_Try, /*On fail goto*//*Label 7086*/ GIMT_Encode4(267793), // Rule ID 51448 // |
| 105075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105076 | // (smax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 105077 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 105078 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105079 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 105082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105083 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105084 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105085 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105089 | GIR_RootConstrainSelectedInstOperands, |
| 105090 | // GIR_Coverage, 51448, |
| 105091 | GIR_EraseRootFromParent_Done, |
| 105092 | // Label 7086: @267793 |
| 105093 | GIM_Try, /*On fail goto*//*Label 7087*/ GIMT_Encode4(267838), // Rule ID 51449 // |
| 105094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105095 | // (smax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 105096 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 105097 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105098 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105099 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 105101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105102 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105103 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105104 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105108 | GIR_RootConstrainSelectedInstOperands, |
| 105109 | // GIR_Coverage, 51449, |
| 105110 | GIR_EraseRootFromParent_Done, |
| 105111 | // Label 7087: @267838 |
| 105112 | GIM_Reject, |
| 105113 | // Label 7085: @267839 |
| 105114 | GIM_Reject, |
| 105115 | // Label 7023: @267840 |
| 105116 | GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(267954), |
| 105117 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 105118 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 105119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105120 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105121 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105122 | GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(267908), // Rule ID 51464 // |
| 105123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105124 | // (smax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 105125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 105126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105133 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105137 | GIR_RootConstrainSelectedInstOperands, |
| 105138 | // GIR_Coverage, 51464, |
| 105139 | GIR_EraseRootFromParent_Done, |
| 105140 | // Label 7089: @267908 |
| 105141 | GIM_Try, /*On fail goto*//*Label 7090*/ GIMT_Encode4(267953), // Rule ID 51465 // |
| 105142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105143 | // (smax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 105144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 105145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105147 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105150 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105151 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105152 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105156 | GIR_RootConstrainSelectedInstOperands, |
| 105157 | // GIR_Coverage, 51465, |
| 105158 | GIR_EraseRootFromParent_Done, |
| 105159 | // Label 7090: @267953 |
| 105160 | GIM_Reject, |
| 105161 | // Label 7088: @267954 |
| 105162 | GIM_Reject, |
| 105163 | // Label 7024: @267955 |
| 105164 | GIM_Try, /*On fail goto*//*Label 7091*/ GIMT_Encode4(268069), |
| 105165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 105166 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 105167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105168 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105169 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105170 | GIM_Try, /*On fail goto*//*Label 7092*/ GIMT_Encode4(268023), // Rule ID 51436 // |
| 105171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105172 | // (smax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105173 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 105174 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105175 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 105178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105179 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105180 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105181 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105185 | GIR_RootConstrainSelectedInstOperands, |
| 105186 | // GIR_Coverage, 51436, |
| 105187 | GIR_EraseRootFromParent_Done, |
| 105188 | // Label 7092: @268023 |
| 105189 | GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(268068), // Rule ID 51437 // |
| 105190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105191 | // (smax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMAX_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105192 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 105193 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105194 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M4), |
| 105197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105199 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105200 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105204 | GIR_RootConstrainSelectedInstOperands, |
| 105205 | // GIR_Coverage, 51437, |
| 105206 | GIR_EraseRootFromParent_Done, |
| 105207 | // Label 7093: @268068 |
| 105208 | GIM_Reject, |
| 105209 | // Label 7091: @268069 |
| 105210 | GIM_Reject, |
| 105211 | // Label 7025: @268070 |
| 105212 | GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(268184), |
| 105213 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 105214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 105215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105216 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105218 | GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(268138), // Rule ID 51452 // |
| 105219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105220 | // (smax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 105221 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 105222 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105223 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105227 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105228 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105229 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105233 | GIR_RootConstrainSelectedInstOperands, |
| 105234 | // GIR_Coverage, 51452, |
| 105235 | GIR_EraseRootFromParent_Done, |
| 105236 | // Label 7095: @268138 |
| 105237 | GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(268183), // Rule ID 51453 // |
| 105238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105239 | // (smax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 105240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 105241 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105242 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105247 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105248 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105252 | GIR_RootConstrainSelectedInstOperands, |
| 105253 | // GIR_Coverage, 51453, |
| 105254 | GIR_EraseRootFromParent_Done, |
| 105255 | // Label 7096: @268183 |
| 105256 | GIM_Reject, |
| 105257 | // Label 7094: @268184 |
| 105258 | GIM_Reject, |
| 105259 | // Label 7026: @268185 |
| 105260 | GIM_Try, /*On fail goto*//*Label 7097*/ GIMT_Encode4(268299), |
| 105261 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 105262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 105263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105264 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 105266 | GIM_Try, /*On fail goto*//*Label 7098*/ GIMT_Encode4(268253), // Rule ID 51440 // |
| 105267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105268 | // (smax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 105270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105276 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105277 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105281 | GIR_RootConstrainSelectedInstOperands, |
| 105282 | // GIR_Coverage, 51440, |
| 105283 | GIR_EraseRootFromParent_Done, |
| 105284 | // Label 7098: @268253 |
| 105285 | GIM_Try, /*On fail goto*//*Label 7099*/ GIMT_Encode4(268298), // Rule ID 51441 // |
| 105286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105287 | // (smax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMAX_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 105289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAX_VV_M8), |
| 105293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105300 | GIR_RootConstrainSelectedInstOperands, |
| 105301 | // GIR_Coverage, 51441, |
| 105302 | GIR_EraseRootFromParent_Done, |
| 105303 | // Label 7099: @268298 |
| 105304 | GIM_Reject, |
| 105305 | // Label 7097: @268299 |
| 105306 | GIM_Reject, |
| 105307 | // Label 7027: @268300 |
| 105308 | GIM_Reject, |
| 105309 | // Label 73: @268301 |
| 105310 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7124*/ GIMT_Encode4(271076), |
| 105311 | /*GILLT_s32*//*Label 7100*/ GIMT_Encode4(268436), |
| 105312 | /*GILLT_s64*//*Label 7101*/ GIMT_Encode4(268491), GIMT_Encode4(0), |
| 105313 | /*GILLT_nxv1s8*//*Label 7102*/ GIMT_Encode4(268546), |
| 105314 | /*GILLT_nxv1s16*//*Label 7103*/ GIMT_Encode4(268661), |
| 105315 | /*GILLT_nxv1s32*//*Label 7104*/ GIMT_Encode4(268776), |
| 105316 | /*GILLT_nxv1s64*//*Label 7105*/ GIMT_Encode4(268891), GIMT_Encode4(0), |
| 105317 | /*GILLT_nxv2s8*//*Label 7106*/ GIMT_Encode4(269006), |
| 105318 | /*GILLT_nxv2s16*//*Label 7107*/ GIMT_Encode4(269121), |
| 105319 | /*GILLT_nxv2s32*//*Label 7108*/ GIMT_Encode4(269236), |
| 105320 | /*GILLT_nxv2s64*//*Label 7109*/ GIMT_Encode4(269351), GIMT_Encode4(0), |
| 105321 | /*GILLT_nxv4s8*//*Label 7110*/ GIMT_Encode4(269466), |
| 105322 | /*GILLT_nxv4s16*//*Label 7111*/ GIMT_Encode4(269581), |
| 105323 | /*GILLT_nxv4s32*//*Label 7112*/ GIMT_Encode4(269696), |
| 105324 | /*GILLT_nxv4s64*//*Label 7113*/ GIMT_Encode4(269811), GIMT_Encode4(0), |
| 105325 | /*GILLT_nxv8s8*//*Label 7114*/ GIMT_Encode4(269926), |
| 105326 | /*GILLT_nxv8s16*//*Label 7115*/ GIMT_Encode4(270041), |
| 105327 | /*GILLT_nxv8s32*//*Label 7116*/ GIMT_Encode4(270156), |
| 105328 | /*GILLT_nxv8s64*//*Label 7117*/ GIMT_Encode4(270271), GIMT_Encode4(0), |
| 105329 | /*GILLT_nxv16s8*//*Label 7118*/ GIMT_Encode4(270386), |
| 105330 | /*GILLT_nxv16s16*//*Label 7119*/ GIMT_Encode4(270501), |
| 105331 | /*GILLT_nxv16s32*//*Label 7120*/ GIMT_Encode4(270616), GIMT_Encode4(0), |
| 105332 | /*GILLT_nxv32s8*//*Label 7121*/ GIMT_Encode4(270731), |
| 105333 | /*GILLT_nxv32s16*//*Label 7122*/ GIMT_Encode4(270846), GIMT_Encode4(0), |
| 105334 | /*GILLT_nxv64s8*//*Label 7123*/ GIMT_Encode4(270961), |
| 105335 | // Label 7100: @268436 |
| 105336 | GIM_Try, /*On fail goto*//*Label 7125*/ GIMT_Encode4(268490), |
| 105337 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 105338 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 105339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 105340 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 105341 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 105342 | GIM_Try, /*On fail goto*//*Label 7126*/ GIMT_Encode4(268474), // Rule ID 64982 // |
| 105343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 105344 | // (umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_MINU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 105345 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MINU), |
| 105346 | GIR_RootConstrainSelectedInstOperands, |
| 105347 | // GIR_Coverage, 64982, |
| 105348 | GIR_Done, |
| 105349 | // Label 7126: @268474 |
| 105350 | GIM_Try, /*On fail goto*//*Label 7127*/ GIMT_Encode4(268489), // Rule ID 2683 // |
| 105351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 105352 | // (umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MINU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 105353 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MINU), |
| 105354 | GIR_RootConstrainSelectedInstOperands, |
| 105355 | // GIR_Coverage, 2683, |
| 105356 | GIR_Done, |
| 105357 | // Label 7127: @268489 |
| 105358 | GIM_Reject, |
| 105359 | // Label 7125: @268490 |
| 105360 | GIM_Reject, |
| 105361 | // Label 7101: @268491 |
| 105362 | GIM_Try, /*On fail goto*//*Label 7128*/ GIMT_Encode4(268545), |
| 105363 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 105364 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 105365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 105366 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 105367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 105368 | GIM_Try, /*On fail goto*//*Label 7129*/ GIMT_Encode4(268529), // Rule ID 64981 // |
| 105369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 105370 | // (umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (CV_MINU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 105371 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MINU), |
| 105372 | GIR_RootConstrainSelectedInstOperands, |
| 105373 | // GIR_Coverage, 64981, |
| 105374 | GIR_Done, |
| 105375 | // Label 7129: @268529 |
| 105376 | GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(268544), // Rule ID 2682 // |
| 105377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 105378 | // (umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MINU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 105379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MINU), |
| 105380 | GIR_RootConstrainSelectedInstOperands, |
| 105381 | // GIR_Coverage, 2682, |
| 105382 | GIR_Done, |
| 105383 | // Label 7130: @268544 |
| 105384 | GIM_Reject, |
| 105385 | // Label 7128: @268545 |
| 105386 | GIM_Reject, |
| 105387 | // Label 7102: @268546 |
| 105388 | GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(268660), |
| 105389 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 105390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 105391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105394 | GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(268614), // Rule ID 51128 // |
| 105395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105396 | // (umin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMINU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105397 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 105398 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105399 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF8), |
| 105402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105404 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105405 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105409 | GIR_RootConstrainSelectedInstOperands, |
| 105410 | // GIR_Coverage, 51128, |
| 105411 | GIR_EraseRootFromParent_Done, |
| 105412 | // Label 7132: @268614 |
| 105413 | GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(268659), // Rule ID 51129 // |
| 105414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105415 | // (umin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMINU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105416 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 105417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF8), |
| 105421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105422 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105423 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105424 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105428 | GIR_RootConstrainSelectedInstOperands, |
| 105429 | // GIR_Coverage, 51129, |
| 105430 | GIR_EraseRootFromParent_Done, |
| 105431 | // Label 7133: @268659 |
| 105432 | GIM_Reject, |
| 105433 | // Label 7131: @268660 |
| 105434 | GIM_Reject, |
| 105435 | // Label 7103: @268661 |
| 105436 | GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(268775), |
| 105437 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 105438 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 105439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105440 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105442 | GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(268729), // Rule ID 51140 // |
| 105443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105444 | // (umin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMINU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 105445 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 105446 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105447 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF4), |
| 105450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105451 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105452 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105453 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105457 | GIR_RootConstrainSelectedInstOperands, |
| 105458 | // GIR_Coverage, 51140, |
| 105459 | GIR_EraseRootFromParent_Done, |
| 105460 | // Label 7135: @268729 |
| 105461 | GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(268774), // Rule ID 51141 // |
| 105462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105463 | // (umin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMINU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 105464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 105465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF4), |
| 105469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105470 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105471 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105472 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105476 | GIR_RootConstrainSelectedInstOperands, |
| 105477 | // GIR_Coverage, 51141, |
| 105478 | GIR_EraseRootFromParent_Done, |
| 105479 | // Label 7136: @268774 |
| 105480 | GIM_Reject, |
| 105481 | // Label 7134: @268775 |
| 105482 | GIM_Reject, |
| 105483 | // Label 7104: @268776 |
| 105484 | GIM_Try, /*On fail goto*//*Label 7137*/ GIMT_Encode4(268890), |
| 105485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 105486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 105487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105490 | GIM_Try, /*On fail goto*//*Label 7138*/ GIMT_Encode4(268844), // Rule ID 51148 // |
| 105491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105492 | // (umin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMINU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 105493 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 105494 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105495 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF2), |
| 105498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105501 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105505 | GIR_RootConstrainSelectedInstOperands, |
| 105506 | // GIR_Coverage, 51148, |
| 105507 | GIR_EraseRootFromParent_Done, |
| 105508 | // Label 7138: @268844 |
| 105509 | GIM_Try, /*On fail goto*//*Label 7139*/ GIMT_Encode4(268889), // Rule ID 51149 // |
| 105510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105511 | // (umin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMINU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 105512 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 105513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF2), |
| 105517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105518 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105520 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105524 | GIR_RootConstrainSelectedInstOperands, |
| 105525 | // GIR_Coverage, 51149, |
| 105526 | GIR_EraseRootFromParent_Done, |
| 105527 | // Label 7139: @268889 |
| 105528 | GIM_Reject, |
| 105529 | // Label 7137: @268890 |
| 105530 | GIM_Reject, |
| 105531 | // Label 7105: @268891 |
| 105532 | GIM_Try, /*On fail goto*//*Label 7140*/ GIMT_Encode4(269005), |
| 105533 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 105534 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 105535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105538 | GIM_Try, /*On fail goto*//*Label 7141*/ GIMT_Encode4(268959), // Rule ID 51164 // |
| 105539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 105540 | // (umin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 105541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 105542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105548 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105549 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105553 | GIR_RootConstrainSelectedInstOperands, |
| 105554 | // GIR_Coverage, 51164, |
| 105555 | GIR_EraseRootFromParent_Done, |
| 105556 | // Label 7141: @268959 |
| 105557 | GIM_Try, /*On fail goto*//*Label 7142*/ GIMT_Encode4(269004), // Rule ID 51165 // |
| 105558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 105559 | // (umin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 105560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 105561 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105562 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105566 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105567 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105568 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105572 | GIR_RootConstrainSelectedInstOperands, |
| 105573 | // GIR_Coverage, 51165, |
| 105574 | GIR_EraseRootFromParent_Done, |
| 105575 | // Label 7142: @269004 |
| 105576 | GIM_Reject, |
| 105577 | // Label 7140: @269005 |
| 105578 | GIM_Reject, |
| 105579 | // Label 7106: @269006 |
| 105580 | GIM_Try, /*On fail goto*//*Label 7143*/ GIMT_Encode4(269120), |
| 105581 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 105582 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 105583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105586 | GIM_Try, /*On fail goto*//*Label 7144*/ GIMT_Encode4(269074), // Rule ID 51132 // |
| 105587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105588 | // (umin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMINU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105589 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 105590 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105591 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF4), |
| 105594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105595 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105596 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105597 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105601 | GIR_RootConstrainSelectedInstOperands, |
| 105602 | // GIR_Coverage, 51132, |
| 105603 | GIR_EraseRootFromParent_Done, |
| 105604 | // Label 7144: @269074 |
| 105605 | GIM_Try, /*On fail goto*//*Label 7145*/ GIMT_Encode4(269119), // Rule ID 51133 // |
| 105606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105607 | // (umin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMINU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 105609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF4), |
| 105613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105615 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105616 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105620 | GIR_RootConstrainSelectedInstOperands, |
| 105621 | // GIR_Coverage, 51133, |
| 105622 | GIR_EraseRootFromParent_Done, |
| 105623 | // Label 7145: @269119 |
| 105624 | GIM_Reject, |
| 105625 | // Label 7143: @269120 |
| 105626 | GIM_Reject, |
| 105627 | // Label 7107: @269121 |
| 105628 | GIM_Try, /*On fail goto*//*Label 7146*/ GIMT_Encode4(269235), |
| 105629 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 105630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 105631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105632 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105634 | GIM_Try, /*On fail goto*//*Label 7147*/ GIMT_Encode4(269189), // Rule ID 51144 // |
| 105635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105636 | // (umin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMINU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 105637 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 105638 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105639 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF2), |
| 105642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105643 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105644 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105645 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105649 | GIR_RootConstrainSelectedInstOperands, |
| 105650 | // GIR_Coverage, 51144, |
| 105651 | GIR_EraseRootFromParent_Done, |
| 105652 | // Label 7147: @269189 |
| 105653 | GIM_Try, /*On fail goto*//*Label 7148*/ GIMT_Encode4(269234), // Rule ID 51145 // |
| 105654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105655 | // (umin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMINU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 105656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 105657 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105658 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF2), |
| 105661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105663 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105664 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105668 | GIR_RootConstrainSelectedInstOperands, |
| 105669 | // GIR_Coverage, 51145, |
| 105670 | GIR_EraseRootFromParent_Done, |
| 105671 | // Label 7148: @269234 |
| 105672 | GIM_Reject, |
| 105673 | // Label 7146: @269235 |
| 105674 | GIM_Reject, |
| 105675 | // Label 7108: @269236 |
| 105676 | GIM_Try, /*On fail goto*//*Label 7149*/ GIMT_Encode4(269350), |
| 105677 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 105678 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 105679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105682 | GIM_Try, /*On fail goto*//*Label 7150*/ GIMT_Encode4(269304), // Rule ID 51160 // |
| 105683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105684 | // (umin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 105685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 105686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105691 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105692 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105693 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105697 | GIR_RootConstrainSelectedInstOperands, |
| 105698 | // GIR_Coverage, 51160, |
| 105699 | GIR_EraseRootFromParent_Done, |
| 105700 | // Label 7150: @269304 |
| 105701 | GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(269349), // Rule ID 51161 // |
| 105702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105703 | // (umin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 105704 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 105705 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105706 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105710 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105711 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105712 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105716 | GIR_RootConstrainSelectedInstOperands, |
| 105717 | // GIR_Coverage, 51161, |
| 105718 | GIR_EraseRootFromParent_Done, |
| 105719 | // Label 7151: @269349 |
| 105720 | GIM_Reject, |
| 105721 | // Label 7149: @269350 |
| 105722 | GIM_Reject, |
| 105723 | // Label 7109: @269351 |
| 105724 | GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(269465), |
| 105725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 105726 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 105727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105730 | GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(269419), // Rule ID 51204 // |
| 105731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 105732 | // (umin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 105733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 105734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 105738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105739 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105740 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105741 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105745 | GIR_RootConstrainSelectedInstOperands, |
| 105746 | // GIR_Coverage, 51204, |
| 105747 | GIR_EraseRootFromParent_Done, |
| 105748 | // Label 7153: @269419 |
| 105749 | GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(269464), // Rule ID 51205 // |
| 105750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 105751 | // (umin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 105752 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 105753 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105754 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 105757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105758 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105759 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105760 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105764 | GIR_RootConstrainSelectedInstOperands, |
| 105765 | // GIR_Coverage, 51205, |
| 105766 | GIR_EraseRootFromParent_Done, |
| 105767 | // Label 7154: @269464 |
| 105768 | GIM_Reject, |
| 105769 | // Label 7152: @269465 |
| 105770 | GIM_Reject, |
| 105771 | // Label 7110: @269466 |
| 105772 | GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(269580), |
| 105773 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 105774 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 105775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105777 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105778 | GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(269534), // Rule ID 51136 // |
| 105779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105780 | // (umin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMINU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105781 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 105782 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105783 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF2), |
| 105786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105787 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105788 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105789 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105793 | GIR_RootConstrainSelectedInstOperands, |
| 105794 | // GIR_Coverage, 51136, |
| 105795 | GIR_EraseRootFromParent_Done, |
| 105796 | // Label 7156: @269534 |
| 105797 | GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(269579), // Rule ID 51137 // |
| 105798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105799 | // (umin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMINU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105800 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 105801 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105802 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_MF2), |
| 105805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105806 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105807 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105808 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105812 | GIR_RootConstrainSelectedInstOperands, |
| 105813 | // GIR_Coverage, 51137, |
| 105814 | GIR_EraseRootFromParent_Done, |
| 105815 | // Label 7157: @269579 |
| 105816 | GIM_Reject, |
| 105817 | // Label 7155: @269580 |
| 105818 | GIM_Reject, |
| 105819 | // Label 7111: @269581 |
| 105820 | GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(269695), |
| 105821 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 105822 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 105823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105825 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105826 | GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(269649), // Rule ID 51156 // |
| 105827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105828 | // (umin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 105829 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 105830 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105831 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105835 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105836 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105837 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105841 | GIR_RootConstrainSelectedInstOperands, |
| 105842 | // GIR_Coverage, 51156, |
| 105843 | GIR_EraseRootFromParent_Done, |
| 105844 | // Label 7159: @269649 |
| 105845 | GIM_Try, /*On fail goto*//*Label 7160*/ GIMT_Encode4(269694), // Rule ID 51157 // |
| 105846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105847 | // (umin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 105848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 105849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105854 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105855 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105856 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 105859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105860 | GIR_RootConstrainSelectedInstOperands, |
| 105861 | // GIR_Coverage, 51157, |
| 105862 | GIR_EraseRootFromParent_Done, |
| 105863 | // Label 7160: @269694 |
| 105864 | GIM_Reject, |
| 105865 | // Label 7158: @269695 |
| 105866 | GIM_Reject, |
| 105867 | // Label 7112: @269696 |
| 105868 | GIM_Try, /*On fail goto*//*Label 7161*/ GIMT_Encode4(269810), |
| 105869 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 105870 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 105871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 105874 | GIM_Try, /*On fail goto*//*Label 7162*/ GIMT_Encode4(269764), // Rule ID 51192 // |
| 105875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105876 | // (umin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 105877 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 105878 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105879 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105880 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 105882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105883 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105884 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105885 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105889 | GIR_RootConstrainSelectedInstOperands, |
| 105890 | // GIR_Coverage, 51192, |
| 105891 | GIR_EraseRootFromParent_Done, |
| 105892 | // Label 7162: @269764 |
| 105893 | GIM_Try, /*On fail goto*//*Label 7163*/ GIMT_Encode4(269809), // Rule ID 51193 // |
| 105894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105895 | // (umin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 105896 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 105897 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105898 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105899 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 105901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105902 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105903 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105904 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 105907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105908 | GIR_RootConstrainSelectedInstOperands, |
| 105909 | // GIR_Coverage, 51193, |
| 105910 | GIR_EraseRootFromParent_Done, |
| 105911 | // Label 7163: @269809 |
| 105912 | GIM_Reject, |
| 105913 | // Label 7161: @269810 |
| 105914 | GIM_Reject, |
| 105915 | // Label 7113: @269811 |
| 105916 | GIM_Try, /*On fail goto*//*Label 7164*/ GIMT_Encode4(269925), |
| 105917 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 105918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 105919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105920 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105921 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 105922 | GIM_Try, /*On fail goto*//*Label 7165*/ GIMT_Encode4(269879), // Rule ID 51208 // |
| 105923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 105924 | // (umin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 105925 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 105926 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105927 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105928 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 105930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105931 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105932 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105933 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105937 | GIR_RootConstrainSelectedInstOperands, |
| 105938 | // GIR_Coverage, 51208, |
| 105939 | GIR_EraseRootFromParent_Done, |
| 105940 | // Label 7165: @269879 |
| 105941 | GIM_Try, /*On fail goto*//*Label 7166*/ GIMT_Encode4(269924), // Rule ID 51209 // |
| 105942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 105943 | // (umin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 105944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 105945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 105949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105950 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105951 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105952 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 105955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105956 | GIR_RootConstrainSelectedInstOperands, |
| 105957 | // GIR_Coverage, 51209, |
| 105958 | GIR_EraseRootFromParent_Done, |
| 105959 | // Label 7166: @269924 |
| 105960 | GIM_Reject, |
| 105961 | // Label 7164: @269925 |
| 105962 | GIM_Reject, |
| 105963 | // Label 7114: @269926 |
| 105964 | GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(270040), |
| 105965 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 105966 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 105967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105968 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 105970 | GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(269994), // Rule ID 51152 // |
| 105971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 105972 | // (umin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 105973 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 105974 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105975 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105979 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105980 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 105981 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 105982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 105983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 105985 | GIR_RootConstrainSelectedInstOperands, |
| 105986 | // GIR_Coverage, 51152, |
| 105987 | GIR_EraseRootFromParent_Done, |
| 105988 | // Label 7168: @269994 |
| 105989 | GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(270039), // Rule ID 51153 // |
| 105990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 105991 | // (umin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMINU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 105992 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 105993 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 105994 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 105995 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 105996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M1), |
| 105997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 105998 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 105999 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106000 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106004 | GIR_RootConstrainSelectedInstOperands, |
| 106005 | // GIR_Coverage, 51153, |
| 106006 | GIR_EraseRootFromParent_Done, |
| 106007 | // Label 7169: @270039 |
| 106008 | GIM_Reject, |
| 106009 | // Label 7167: @270040 |
| 106010 | GIM_Reject, |
| 106011 | // Label 7115: @270041 |
| 106012 | GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(270155), |
| 106013 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 106014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 106015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106017 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106018 | GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(270109), // Rule ID 51180 // |
| 106019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106020 | // (umin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 106021 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 106022 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106023 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106024 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 106026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106027 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106028 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106029 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106033 | GIR_RootConstrainSelectedInstOperands, |
| 106034 | // GIR_Coverage, 51180, |
| 106035 | GIR_EraseRootFromParent_Done, |
| 106036 | // Label 7171: @270109 |
| 106037 | GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(270154), // Rule ID 51181 // |
| 106038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106039 | // (umin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 106040 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 106041 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106042 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 106045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106046 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106047 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106048 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106052 | GIR_RootConstrainSelectedInstOperands, |
| 106053 | // GIR_Coverage, 51181, |
| 106054 | GIR_EraseRootFromParent_Done, |
| 106055 | // Label 7172: @270154 |
| 106056 | GIM_Reject, |
| 106057 | // Label 7170: @270155 |
| 106058 | GIM_Reject, |
| 106059 | // Label 7116: @270156 |
| 106060 | GIM_Try, /*On fail goto*//*Label 7173*/ GIMT_Encode4(270270), |
| 106061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 106062 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 106063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106064 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106066 | GIM_Try, /*On fail goto*//*Label 7174*/ GIMT_Encode4(270224), // Rule ID 51196 // |
| 106067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106068 | // (umin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 106069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 106070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 106074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106076 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106077 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106081 | GIR_RootConstrainSelectedInstOperands, |
| 106082 | // GIR_Coverage, 51196, |
| 106083 | GIR_EraseRootFromParent_Done, |
| 106084 | // Label 7174: @270224 |
| 106085 | GIM_Try, /*On fail goto*//*Label 7175*/ GIMT_Encode4(270269), // Rule ID 51197 // |
| 106086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106087 | // (umin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 106088 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 106089 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106090 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 106093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106095 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106096 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106100 | GIR_RootConstrainSelectedInstOperands, |
| 106101 | // GIR_Coverage, 51197, |
| 106102 | GIR_EraseRootFromParent_Done, |
| 106103 | // Label 7175: @270269 |
| 106104 | GIM_Reject, |
| 106105 | // Label 7173: @270270 |
| 106106 | GIM_Reject, |
| 106107 | // Label 7117: @270271 |
| 106108 | GIM_Try, /*On fail goto*//*Label 7176*/ GIMT_Encode4(270385), |
| 106109 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 106110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 106111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106112 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106114 | GIM_Try, /*On fail goto*//*Label 7177*/ GIMT_Encode4(270339), // Rule ID 51212 // |
| 106115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 106116 | // (umin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 106117 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 106118 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106119 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106123 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106124 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106125 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 106128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106129 | GIR_RootConstrainSelectedInstOperands, |
| 106130 | // GIR_Coverage, 51212, |
| 106131 | GIR_EraseRootFromParent_Done, |
| 106132 | // Label 7177: @270339 |
| 106133 | GIM_Try, /*On fail goto*//*Label 7178*/ GIMT_Encode4(270384), // Rule ID 51213 // |
| 106134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 106135 | // (umin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 106136 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 106137 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106138 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106143 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106144 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 106147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106148 | GIR_RootConstrainSelectedInstOperands, |
| 106149 | // GIR_Coverage, 51213, |
| 106150 | GIR_EraseRootFromParent_Done, |
| 106151 | // Label 7178: @270384 |
| 106152 | GIM_Reject, |
| 106153 | // Label 7176: @270385 |
| 106154 | GIM_Reject, |
| 106155 | // Label 7118: @270386 |
| 106156 | GIM_Try, /*On fail goto*//*Label 7179*/ GIMT_Encode4(270500), |
| 106157 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 106158 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 106159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106160 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106162 | GIM_Try, /*On fail goto*//*Label 7180*/ GIMT_Encode4(270454), // Rule ID 51168 // |
| 106163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106164 | // (umin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 106165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 106166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 106170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106171 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106172 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106173 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106177 | GIR_RootConstrainSelectedInstOperands, |
| 106178 | // GIR_Coverage, 51168, |
| 106179 | GIR_EraseRootFromParent_Done, |
| 106180 | // Label 7180: @270454 |
| 106181 | GIM_Try, /*On fail goto*//*Label 7181*/ GIMT_Encode4(270499), // Rule ID 51169 // |
| 106182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106183 | // (umin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMINU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 106184 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 106185 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106186 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M2), |
| 106189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106190 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106191 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106192 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106196 | GIR_RootConstrainSelectedInstOperands, |
| 106197 | // GIR_Coverage, 51169, |
| 106198 | GIR_EraseRootFromParent_Done, |
| 106199 | // Label 7181: @270499 |
| 106200 | GIM_Reject, |
| 106201 | // Label 7179: @270500 |
| 106202 | GIM_Reject, |
| 106203 | // Label 7119: @270501 |
| 106204 | GIM_Try, /*On fail goto*//*Label 7182*/ GIMT_Encode4(270615), |
| 106205 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 106206 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 106207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106208 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106209 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106210 | GIM_Try, /*On fail goto*//*Label 7183*/ GIMT_Encode4(270569), // Rule ID 51184 // |
| 106211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106212 | // (umin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 106213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 106214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 106218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106219 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106220 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106221 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106225 | GIR_RootConstrainSelectedInstOperands, |
| 106226 | // GIR_Coverage, 51184, |
| 106227 | GIR_EraseRootFromParent_Done, |
| 106228 | // Label 7183: @270569 |
| 106229 | GIM_Try, /*On fail goto*//*Label 7184*/ GIMT_Encode4(270614), // Rule ID 51185 // |
| 106230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106231 | // (umin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 106232 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 106233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 106237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106239 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106240 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106244 | GIR_RootConstrainSelectedInstOperands, |
| 106245 | // GIR_Coverage, 51185, |
| 106246 | GIR_EraseRootFromParent_Done, |
| 106247 | // Label 7184: @270614 |
| 106248 | GIM_Reject, |
| 106249 | // Label 7182: @270615 |
| 106250 | GIM_Reject, |
| 106251 | // Label 7120: @270616 |
| 106252 | GIM_Try, /*On fail goto*//*Label 7185*/ GIMT_Encode4(270730), |
| 106253 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 106254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 106255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106258 | GIM_Try, /*On fail goto*//*Label 7186*/ GIMT_Encode4(270684), // Rule ID 51200 // |
| 106259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106260 | // (umin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 106261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 106262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106268 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106269 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106273 | GIR_RootConstrainSelectedInstOperands, |
| 106274 | // GIR_Coverage, 51200, |
| 106275 | GIR_EraseRootFromParent_Done, |
| 106276 | // Label 7186: @270684 |
| 106277 | GIM_Try, /*On fail goto*//*Label 7187*/ GIMT_Encode4(270729), // Rule ID 51201 // |
| 106278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106279 | // (umin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 106280 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 106281 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106282 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106286 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106287 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106288 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106292 | GIR_RootConstrainSelectedInstOperands, |
| 106293 | // GIR_Coverage, 51201, |
| 106294 | GIR_EraseRootFromParent_Done, |
| 106295 | // Label 7187: @270729 |
| 106296 | GIM_Reject, |
| 106297 | // Label 7185: @270730 |
| 106298 | GIM_Reject, |
| 106299 | // Label 7121: @270731 |
| 106300 | GIM_Try, /*On fail goto*//*Label 7188*/ GIMT_Encode4(270845), |
| 106301 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 106302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 106303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106304 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106305 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 106306 | GIM_Try, /*On fail goto*//*Label 7189*/ GIMT_Encode4(270799), // Rule ID 51172 // |
| 106307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106308 | // (umin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 106309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 106310 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106311 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 106314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106315 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106316 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106317 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106321 | GIR_RootConstrainSelectedInstOperands, |
| 106322 | // GIR_Coverage, 51172, |
| 106323 | GIR_EraseRootFromParent_Done, |
| 106324 | // Label 7189: @270799 |
| 106325 | GIM_Try, /*On fail goto*//*Label 7190*/ GIMT_Encode4(270844), // Rule ID 51173 // |
| 106326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106327 | // (umin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMINU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 106328 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 106329 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106330 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M4), |
| 106333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106334 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106335 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106336 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106340 | GIR_RootConstrainSelectedInstOperands, |
| 106341 | // GIR_Coverage, 51173, |
| 106342 | GIR_EraseRootFromParent_Done, |
| 106343 | // Label 7190: @270844 |
| 106344 | GIM_Reject, |
| 106345 | // Label 7188: @270845 |
| 106346 | GIM_Reject, |
| 106347 | // Label 7122: @270846 |
| 106348 | GIM_Try, /*On fail goto*//*Label 7191*/ GIMT_Encode4(270960), |
| 106349 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 106350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 106351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106352 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106354 | GIM_Try, /*On fail goto*//*Label 7192*/ GIMT_Encode4(270914), // Rule ID 51188 // |
| 106355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106356 | // (umin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 106357 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 106358 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106359 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106363 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106364 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106365 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106369 | GIR_RootConstrainSelectedInstOperands, |
| 106370 | // GIR_Coverage, 51188, |
| 106371 | GIR_EraseRootFromParent_Done, |
| 106372 | // Label 7192: @270914 |
| 106373 | GIM_Try, /*On fail goto*//*Label 7193*/ GIMT_Encode4(270959), // Rule ID 51189 // |
| 106374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106375 | // (umin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 106376 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 106377 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106378 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106382 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106383 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106384 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106388 | GIR_RootConstrainSelectedInstOperands, |
| 106389 | // GIR_Coverage, 51189, |
| 106390 | GIR_EraseRootFromParent_Done, |
| 106391 | // Label 7193: @270959 |
| 106392 | GIM_Reject, |
| 106393 | // Label 7191: @270960 |
| 106394 | GIM_Reject, |
| 106395 | // Label 7123: @270961 |
| 106396 | GIM_Try, /*On fail goto*//*Label 7194*/ GIMT_Encode4(271075), |
| 106397 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 106398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 106399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106400 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 106402 | GIM_Try, /*On fail goto*//*Label 7195*/ GIMT_Encode4(271029), // Rule ID 51176 // |
| 106403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106404 | // (umin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 106405 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 106406 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106407 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106411 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106412 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106413 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106417 | GIR_RootConstrainSelectedInstOperands, |
| 106418 | // GIR_Coverage, 51176, |
| 106419 | GIR_EraseRootFromParent_Done, |
| 106420 | // Label 7195: @271029 |
| 106421 | GIM_Try, /*On fail goto*//*Label 7196*/ GIMT_Encode4(271074), // Rule ID 51177 // |
| 106422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106423 | // (umin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMINU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 106424 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 106425 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMINU_VV_M8), |
| 106429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106431 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106432 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106436 | GIR_RootConstrainSelectedInstOperands, |
| 106437 | // GIR_Coverage, 51177, |
| 106438 | GIR_EraseRootFromParent_Done, |
| 106439 | // Label 7196: @271074 |
| 106440 | GIM_Reject, |
| 106441 | // Label 7194: @271075 |
| 106442 | GIM_Reject, |
| 106443 | // Label 7124: @271076 |
| 106444 | GIM_Reject, |
| 106445 | // Label 74: @271077 |
| 106446 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7221*/ GIMT_Encode4(273852), |
| 106447 | /*GILLT_s32*//*Label 7197*/ GIMT_Encode4(271212), |
| 106448 | /*GILLT_s64*//*Label 7198*/ GIMT_Encode4(271267), GIMT_Encode4(0), |
| 106449 | /*GILLT_nxv1s8*//*Label 7199*/ GIMT_Encode4(271322), |
| 106450 | /*GILLT_nxv1s16*//*Label 7200*/ GIMT_Encode4(271437), |
| 106451 | /*GILLT_nxv1s32*//*Label 7201*/ GIMT_Encode4(271552), |
| 106452 | /*GILLT_nxv1s64*//*Label 7202*/ GIMT_Encode4(271667), GIMT_Encode4(0), |
| 106453 | /*GILLT_nxv2s8*//*Label 7203*/ GIMT_Encode4(271782), |
| 106454 | /*GILLT_nxv2s16*//*Label 7204*/ GIMT_Encode4(271897), |
| 106455 | /*GILLT_nxv2s32*//*Label 7205*/ GIMT_Encode4(272012), |
| 106456 | /*GILLT_nxv2s64*//*Label 7206*/ GIMT_Encode4(272127), GIMT_Encode4(0), |
| 106457 | /*GILLT_nxv4s8*//*Label 7207*/ GIMT_Encode4(272242), |
| 106458 | /*GILLT_nxv4s16*//*Label 7208*/ GIMT_Encode4(272357), |
| 106459 | /*GILLT_nxv4s32*//*Label 7209*/ GIMT_Encode4(272472), |
| 106460 | /*GILLT_nxv4s64*//*Label 7210*/ GIMT_Encode4(272587), GIMT_Encode4(0), |
| 106461 | /*GILLT_nxv8s8*//*Label 7211*/ GIMT_Encode4(272702), |
| 106462 | /*GILLT_nxv8s16*//*Label 7212*/ GIMT_Encode4(272817), |
| 106463 | /*GILLT_nxv8s32*//*Label 7213*/ GIMT_Encode4(272932), |
| 106464 | /*GILLT_nxv8s64*//*Label 7214*/ GIMT_Encode4(273047), GIMT_Encode4(0), |
| 106465 | /*GILLT_nxv16s8*//*Label 7215*/ GIMT_Encode4(273162), |
| 106466 | /*GILLT_nxv16s16*//*Label 7216*/ GIMT_Encode4(273277), |
| 106467 | /*GILLT_nxv16s32*//*Label 7217*/ GIMT_Encode4(273392), GIMT_Encode4(0), |
| 106468 | /*GILLT_nxv32s8*//*Label 7218*/ GIMT_Encode4(273507), |
| 106469 | /*GILLT_nxv32s16*//*Label 7219*/ GIMT_Encode4(273622), GIMT_Encode4(0), |
| 106470 | /*GILLT_nxv64s8*//*Label 7220*/ GIMT_Encode4(273737), |
| 106471 | // Label 7197: @271212 |
| 106472 | GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(271266), |
| 106473 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 106474 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 106475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 106476 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 106477 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 106478 | GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(271250), // Rule ID 64986 // |
| 106479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 106480 | // (umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (CV_MAXU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 106481 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MAXU), |
| 106482 | GIR_RootConstrainSelectedInstOperands, |
| 106483 | // GIR_Coverage, 64986, |
| 106484 | GIR_Done, |
| 106485 | // Label 7223: @271250 |
| 106486 | GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(271265), // Rule ID 2685 // |
| 106487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 106488 | // (umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MAXU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) |
| 106489 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MAXU), |
| 106490 | GIR_RootConstrainSelectedInstOperands, |
| 106491 | // GIR_Coverage, 2685, |
| 106492 | GIR_Done, |
| 106493 | // Label 7224: @271265 |
| 106494 | GIM_Reject, |
| 106495 | // Label 7222: @271266 |
| 106496 | GIM_Reject, |
| 106497 | // Label 7198: @271267 |
| 106498 | GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(271321), |
| 106499 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 106500 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 106501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 106502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 106503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 106504 | GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(271305), // Rule ID 64985 // |
| 106505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 106506 | // (umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (CV_MAXU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 106507 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_MAXU), |
| 106508 | GIR_RootConstrainSelectedInstOperands, |
| 106509 | // GIR_Coverage, 64985, |
| 106510 | GIR_Done, |
| 106511 | // Label 7226: @271305 |
| 106512 | GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(271320), // Rule ID 2684 // |
| 106513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 106514 | // (umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MAXU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) |
| 106515 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MAXU), |
| 106516 | GIR_RootConstrainSelectedInstOperands, |
| 106517 | // GIR_Coverage, 2684, |
| 106518 | GIR_Done, |
| 106519 | // Label 7227: @271320 |
| 106520 | GIM_Reject, |
| 106521 | // Label 7225: @271321 |
| 106522 | GIM_Reject, |
| 106523 | // Label 7199: @271322 |
| 106524 | GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(271436), |
| 106525 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 106526 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, |
| 106527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106528 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106530 | GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(271390), // Rule ID 51304 // |
| 106531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106532 | // (umax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMAXU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 106533 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 106534 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106535 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF8), |
| 106538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106539 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106540 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106541 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106545 | GIR_RootConstrainSelectedInstOperands, |
| 106546 | // GIR_Coverage, 51304, |
| 106547 | GIR_EraseRootFromParent_Done, |
| 106548 | // Label 7229: @271390 |
| 106549 | GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(271435), // Rule ID 51305 // |
| 106550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106551 | // (umax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMAXU_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 106552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 106553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106554 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF8), |
| 106557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106558 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106559 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106560 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106564 | GIR_RootConstrainSelectedInstOperands, |
| 106565 | // GIR_Coverage, 51305, |
| 106566 | GIR_EraseRootFromParent_Done, |
| 106567 | // Label 7230: @271435 |
| 106568 | GIM_Reject, |
| 106569 | // Label 7228: @271436 |
| 106570 | GIM_Reject, |
| 106571 | // Label 7200: @271437 |
| 106572 | GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(271551), |
| 106573 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 106574 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 106575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106578 | GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(271505), // Rule ID 51316 // |
| 106579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106580 | // (umax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMAXU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 106581 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 106582 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106583 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF4), |
| 106586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106587 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106588 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106589 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106593 | GIR_RootConstrainSelectedInstOperands, |
| 106594 | // GIR_Coverage, 51316, |
| 106595 | GIR_EraseRootFromParent_Done, |
| 106596 | // Label 7232: @271505 |
| 106597 | GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(271550), // Rule ID 51317 // |
| 106598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106599 | // (umax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMAXU_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 106600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 106601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106602 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF4), |
| 106605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106606 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106607 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106608 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106612 | GIR_RootConstrainSelectedInstOperands, |
| 106613 | // GIR_Coverage, 51317, |
| 106614 | GIR_EraseRootFromParent_Done, |
| 106615 | // Label 7233: @271550 |
| 106616 | GIM_Reject, |
| 106617 | // Label 7231: @271551 |
| 106618 | GIM_Reject, |
| 106619 | // Label 7201: @271552 |
| 106620 | GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(271666), |
| 106621 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 106622 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 106623 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106624 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106625 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106626 | GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(271620), // Rule ID 51324 // |
| 106627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106628 | // (umax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMAXU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 106629 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 106630 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106631 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF2), |
| 106634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106635 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106636 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106637 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106641 | GIR_RootConstrainSelectedInstOperands, |
| 106642 | // GIR_Coverage, 51324, |
| 106643 | GIR_EraseRootFromParent_Done, |
| 106644 | // Label 7235: @271620 |
| 106645 | GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(271665), // Rule ID 51325 // |
| 106646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106647 | // (umax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMAXU_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 106648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 106649 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF2), |
| 106653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106654 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106655 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106656 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106660 | GIR_RootConstrainSelectedInstOperands, |
| 106661 | // GIR_Coverage, 51325, |
| 106662 | GIR_EraseRootFromParent_Done, |
| 106663 | // Label 7236: @271665 |
| 106664 | GIM_Reject, |
| 106665 | // Label 7234: @271666 |
| 106666 | GIM_Reject, |
| 106667 | // Label 7202: @271667 |
| 106668 | GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(271781), |
| 106669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 106670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 106671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106674 | GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(271735), // Rule ID 51340 // |
| 106675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 106676 | // (umax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 106677 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 106678 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106679 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 106682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106683 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106684 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106685 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 106688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106689 | GIR_RootConstrainSelectedInstOperands, |
| 106690 | // GIR_Coverage, 51340, |
| 106691 | GIR_EraseRootFromParent_Done, |
| 106692 | // Label 7238: @271735 |
| 106693 | GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(271780), // Rule ID 51341 // |
| 106694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 106695 | // (umax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 106696 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 106697 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 106701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106702 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106703 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106704 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 106707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106708 | GIR_RootConstrainSelectedInstOperands, |
| 106709 | // GIR_Coverage, 51341, |
| 106710 | GIR_EraseRootFromParent_Done, |
| 106711 | // Label 7239: @271780 |
| 106712 | GIM_Reject, |
| 106713 | // Label 7237: @271781 |
| 106714 | GIM_Reject, |
| 106715 | // Label 7203: @271782 |
| 106716 | GIM_Try, /*On fail goto*//*Label 7240*/ GIMT_Encode4(271896), |
| 106717 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 106718 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, |
| 106719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106720 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106721 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106722 | GIM_Try, /*On fail goto*//*Label 7241*/ GIMT_Encode4(271850), // Rule ID 51308 // |
| 106723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106724 | // (umax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMAXU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 106725 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 106726 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106727 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF4), |
| 106730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106731 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106732 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106733 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106737 | GIR_RootConstrainSelectedInstOperands, |
| 106738 | // GIR_Coverage, 51308, |
| 106739 | GIR_EraseRootFromParent_Done, |
| 106740 | // Label 7241: @271850 |
| 106741 | GIM_Try, /*On fail goto*//*Label 7242*/ GIMT_Encode4(271895), // Rule ID 51309 // |
| 106742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106743 | // (umax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMAXU_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 106744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 106745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106747 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF4), |
| 106749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106750 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106752 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106756 | GIR_RootConstrainSelectedInstOperands, |
| 106757 | // GIR_Coverage, 51309, |
| 106758 | GIR_EraseRootFromParent_Done, |
| 106759 | // Label 7242: @271895 |
| 106760 | GIM_Reject, |
| 106761 | // Label 7240: @271896 |
| 106762 | GIM_Reject, |
| 106763 | // Label 7204: @271897 |
| 106764 | GIM_Try, /*On fail goto*//*Label 7243*/ GIMT_Encode4(272011), |
| 106765 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 106766 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 106767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106768 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106770 | GIM_Try, /*On fail goto*//*Label 7244*/ GIMT_Encode4(271965), // Rule ID 51320 // |
| 106771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106772 | // (umax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMAXU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 106773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 106774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF2), |
| 106778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106781 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106785 | GIR_RootConstrainSelectedInstOperands, |
| 106786 | // GIR_Coverage, 51320, |
| 106787 | GIR_EraseRootFromParent_Done, |
| 106788 | // Label 7244: @271965 |
| 106789 | GIM_Try, /*On fail goto*//*Label 7245*/ GIMT_Encode4(272010), // Rule ID 51321 // |
| 106790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106791 | // (umax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMAXU_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 106792 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 106793 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106794 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF2), |
| 106797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106798 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106799 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106800 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106804 | GIR_RootConstrainSelectedInstOperands, |
| 106805 | // GIR_Coverage, 51321, |
| 106806 | GIR_EraseRootFromParent_Done, |
| 106807 | // Label 7245: @272010 |
| 106808 | GIM_Reject, |
| 106809 | // Label 7243: @272011 |
| 106810 | GIM_Reject, |
| 106811 | // Label 7205: @272012 |
| 106812 | GIM_Try, /*On fail goto*//*Label 7246*/ GIMT_Encode4(272126), |
| 106813 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 106814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 106815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106816 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106817 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106818 | GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(272080), // Rule ID 51336 // |
| 106819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106820 | // (umax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 106821 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 106822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 106826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106827 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106828 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106829 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106833 | GIR_RootConstrainSelectedInstOperands, |
| 106834 | // GIR_Coverage, 51336, |
| 106835 | GIR_EraseRootFromParent_Done, |
| 106836 | // Label 7247: @272080 |
| 106837 | GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(272125), // Rule ID 51337 // |
| 106838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106839 | // (umax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 106840 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 106841 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106842 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 106845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106846 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106847 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106848 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 106851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106852 | GIR_RootConstrainSelectedInstOperands, |
| 106853 | // GIR_Coverage, 51337, |
| 106854 | GIR_EraseRootFromParent_Done, |
| 106855 | // Label 7248: @272125 |
| 106856 | GIM_Reject, |
| 106857 | // Label 7246: @272126 |
| 106858 | GIM_Reject, |
| 106859 | // Label 7206: @272127 |
| 106860 | GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(272241), |
| 106861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 106862 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 106863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106864 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 106866 | GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(272195), // Rule ID 51380 // |
| 106867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 106868 | // (umax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 106869 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 106870 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106871 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 106874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106875 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106876 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106877 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 106880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106881 | GIR_RootConstrainSelectedInstOperands, |
| 106882 | // GIR_Coverage, 51380, |
| 106883 | GIR_EraseRootFromParent_Done, |
| 106884 | // Label 7250: @272195 |
| 106885 | GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(272240), // Rule ID 51381 // |
| 106886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 106887 | // (umax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 106888 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 106889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106891 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 106893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106894 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106895 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106896 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 106899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106900 | GIR_RootConstrainSelectedInstOperands, |
| 106901 | // GIR_Coverage, 51381, |
| 106902 | GIR_EraseRootFromParent_Done, |
| 106903 | // Label 7251: @272240 |
| 106904 | GIM_Reject, |
| 106905 | // Label 7249: @272241 |
| 106906 | GIM_Reject, |
| 106907 | // Label 7207: @272242 |
| 106908 | GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(272356), |
| 106909 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 106910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, |
| 106911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106912 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106913 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106914 | GIM_Try, /*On fail goto*//*Label 7253*/ GIMT_Encode4(272310), // Rule ID 51312 // |
| 106915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106916 | // (umax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMAXU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 106917 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 106918 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106919 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF2), |
| 106922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106923 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106924 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106925 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106929 | GIR_RootConstrainSelectedInstOperands, |
| 106930 | // GIR_Coverage, 51312, |
| 106931 | GIR_EraseRootFromParent_Done, |
| 106932 | // Label 7253: @272310 |
| 106933 | GIM_Try, /*On fail goto*//*Label 7254*/ GIMT_Encode4(272355), // Rule ID 51313 // |
| 106934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106935 | // (umax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMAXU_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 106936 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 106937 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106938 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_MF2), |
| 106941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106942 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106943 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106944 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106948 | GIR_RootConstrainSelectedInstOperands, |
| 106949 | // GIR_Coverage, 51313, |
| 106950 | GIR_EraseRootFromParent_Done, |
| 106951 | // Label 7254: @272355 |
| 106952 | GIM_Reject, |
| 106953 | // Label 7252: @272356 |
| 106954 | GIM_Reject, |
| 106955 | // Label 7208: @272357 |
| 106956 | GIM_Try, /*On fail goto*//*Label 7255*/ GIMT_Encode4(272471), |
| 106957 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 106958 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 106959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 106962 | GIM_Try, /*On fail goto*//*Label 7256*/ GIMT_Encode4(272425), // Rule ID 51332 // |
| 106963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 106964 | // (umax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 106965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 106966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 106970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106971 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106973 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106977 | GIR_RootConstrainSelectedInstOperands, |
| 106978 | // GIR_Coverage, 51332, |
| 106979 | GIR_EraseRootFromParent_Done, |
| 106980 | // Label 7256: @272425 |
| 106981 | GIM_Try, /*On fail goto*//*Label 7257*/ GIMT_Encode4(272470), // Rule ID 51333 // |
| 106982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 106983 | // (umax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 106984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 106985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 106986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 106987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 106988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 106989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 106990 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 106991 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 106992 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 106993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 106994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 106995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 106996 | GIR_RootConstrainSelectedInstOperands, |
| 106997 | // GIR_Coverage, 51333, |
| 106998 | GIR_EraseRootFromParent_Done, |
| 106999 | // Label 7257: @272470 |
| 107000 | GIM_Reject, |
| 107001 | // Label 7255: @272471 |
| 107002 | GIM_Reject, |
| 107003 | // Label 7209: @272472 |
| 107004 | GIM_Try, /*On fail goto*//*Label 7258*/ GIMT_Encode4(272586), |
| 107005 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 107006 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 107007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107008 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107009 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107010 | GIM_Try, /*On fail goto*//*Label 7259*/ GIMT_Encode4(272540), // Rule ID 51368 // |
| 107011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107012 | // (umax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 107013 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 107014 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107015 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 107018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107019 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107020 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107021 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 107024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107025 | GIR_RootConstrainSelectedInstOperands, |
| 107026 | // GIR_Coverage, 51368, |
| 107027 | GIR_EraseRootFromParent_Done, |
| 107028 | // Label 7259: @272540 |
| 107029 | GIM_Try, /*On fail goto*//*Label 7260*/ GIMT_Encode4(272585), // Rule ID 51369 // |
| 107030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107031 | // (umax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 107032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 107033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 107037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107038 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107039 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107040 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 107043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107044 | GIR_RootConstrainSelectedInstOperands, |
| 107045 | // GIR_Coverage, 51369, |
| 107046 | GIR_EraseRootFromParent_Done, |
| 107047 | // Label 7260: @272585 |
| 107048 | GIM_Reject, |
| 107049 | // Label 7258: @272586 |
| 107050 | GIM_Reject, |
| 107051 | // Label 7210: @272587 |
| 107052 | GIM_Try, /*On fail goto*//*Label 7261*/ GIMT_Encode4(272701), |
| 107053 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 107054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 107055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107056 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107057 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107058 | GIM_Try, /*On fail goto*//*Label 7262*/ GIMT_Encode4(272655), // Rule ID 51384 // |
| 107059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 107060 | // (umax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 107061 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 107062 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107063 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107064 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107067 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107069 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 107072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107073 | GIR_RootConstrainSelectedInstOperands, |
| 107074 | // GIR_Coverage, 51384, |
| 107075 | GIR_EraseRootFromParent_Done, |
| 107076 | // Label 7262: @272655 |
| 107077 | GIM_Try, /*On fail goto*//*Label 7263*/ GIMT_Encode4(272700), // Rule ID 51385 // |
| 107078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 107079 | // (umax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 107080 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 107081 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107082 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107086 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107087 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 107091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107092 | GIR_RootConstrainSelectedInstOperands, |
| 107093 | // GIR_Coverage, 51385, |
| 107094 | GIR_EraseRootFromParent_Done, |
| 107095 | // Label 7263: @272700 |
| 107096 | GIM_Reject, |
| 107097 | // Label 7261: @272701 |
| 107098 | GIM_Reject, |
| 107099 | // Label 7211: @272702 |
| 107100 | GIM_Try, /*On fail goto*//*Label 7264*/ GIMT_Encode4(272816), |
| 107101 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 107102 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, |
| 107103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 107104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 107105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 107106 | GIM_Try, /*On fail goto*//*Label 7265*/ GIMT_Encode4(272770), // Rule ID 51328 // |
| 107107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107108 | // (umax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 107109 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 107110 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107111 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 107114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107115 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107116 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107117 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107121 | GIR_RootConstrainSelectedInstOperands, |
| 107122 | // GIR_Coverage, 51328, |
| 107123 | GIR_EraseRootFromParent_Done, |
| 107124 | // Label 7265: @272770 |
| 107125 | GIM_Try, /*On fail goto*//*Label 7266*/ GIMT_Encode4(272815), // Rule ID 51329 // |
| 107126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107127 | // (umax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMAXU_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 107128 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 107129 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107130 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M1), |
| 107133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107134 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107135 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107136 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107140 | GIR_RootConstrainSelectedInstOperands, |
| 107141 | // GIR_Coverage, 51329, |
| 107142 | GIR_EraseRootFromParent_Done, |
| 107143 | // Label 7266: @272815 |
| 107144 | GIM_Reject, |
| 107145 | // Label 7264: @272816 |
| 107146 | GIM_Reject, |
| 107147 | // Label 7212: @272817 |
| 107148 | GIM_Try, /*On fail goto*//*Label 7267*/ GIMT_Encode4(272931), |
| 107149 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 107150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 107151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107152 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107153 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107154 | GIM_Try, /*On fail goto*//*Label 7268*/ GIMT_Encode4(272885), // Rule ID 51356 // |
| 107155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107156 | // (umax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 107157 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 107158 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107159 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 107162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107163 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107164 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107165 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107169 | GIR_RootConstrainSelectedInstOperands, |
| 107170 | // GIR_Coverage, 51356, |
| 107171 | GIR_EraseRootFromParent_Done, |
| 107172 | // Label 7268: @272885 |
| 107173 | GIM_Try, /*On fail goto*//*Label 7269*/ GIMT_Encode4(272930), // Rule ID 51357 // |
| 107174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107175 | // (umax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 107176 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 107177 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107178 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 107181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107182 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107183 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107184 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107188 | GIR_RootConstrainSelectedInstOperands, |
| 107189 | // GIR_Coverage, 51357, |
| 107190 | GIR_EraseRootFromParent_Done, |
| 107191 | // Label 7269: @272930 |
| 107192 | GIM_Reject, |
| 107193 | // Label 7267: @272931 |
| 107194 | GIM_Reject, |
| 107195 | // Label 7213: @272932 |
| 107196 | GIM_Try, /*On fail goto*//*Label 7270*/ GIMT_Encode4(273046), |
| 107197 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 107198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 107199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107202 | GIM_Try, /*On fail goto*//*Label 7271*/ GIMT_Encode4(273000), // Rule ID 51372 // |
| 107203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107204 | // (umax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 107205 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 107206 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107207 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107211 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107212 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107213 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 107216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107217 | GIR_RootConstrainSelectedInstOperands, |
| 107218 | // GIR_Coverage, 51372, |
| 107219 | GIR_EraseRootFromParent_Done, |
| 107220 | // Label 7271: @273000 |
| 107221 | GIM_Try, /*On fail goto*//*Label 7272*/ GIMT_Encode4(273045), // Rule ID 51373 // |
| 107222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107223 | // (umax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 107224 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 107225 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107226 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107227 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107230 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107231 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107232 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 107235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107236 | GIR_RootConstrainSelectedInstOperands, |
| 107237 | // GIR_Coverage, 51373, |
| 107238 | GIR_EraseRootFromParent_Done, |
| 107239 | // Label 7272: @273045 |
| 107240 | GIM_Reject, |
| 107241 | // Label 7270: @273046 |
| 107242 | GIM_Reject, |
| 107243 | // Label 7214: @273047 |
| 107244 | GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(273161), |
| 107245 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 107246 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 107247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107248 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107249 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107250 | GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(273115), // Rule ID 51388 // |
| 107251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), |
| 107252 | // (umax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 107253 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 107254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107255 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107260 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107261 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 107264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107265 | GIR_RootConstrainSelectedInstOperands, |
| 107266 | // GIR_Coverage, 51388, |
| 107267 | GIR_EraseRootFromParent_Done, |
| 107268 | // Label 7274: @273115 |
| 107269 | GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(273160), // Rule ID 51389 // |
| 107270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), |
| 107271 | // (umax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 107272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 107273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107278 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107279 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107280 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 107283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107284 | GIR_RootConstrainSelectedInstOperands, |
| 107285 | // GIR_Coverage, 51389, |
| 107286 | GIR_EraseRootFromParent_Done, |
| 107287 | // Label 7275: @273160 |
| 107288 | GIM_Reject, |
| 107289 | // Label 7273: @273161 |
| 107290 | GIM_Reject, |
| 107291 | // Label 7215: @273162 |
| 107292 | GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(273276), |
| 107293 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 107294 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, |
| 107295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107296 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107297 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 107298 | GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(273230), // Rule ID 51344 // |
| 107299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107300 | // (umax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 107301 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 107302 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107303 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 107306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107307 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107308 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107309 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107313 | GIR_RootConstrainSelectedInstOperands, |
| 107314 | // GIR_Coverage, 51344, |
| 107315 | GIR_EraseRootFromParent_Done, |
| 107316 | // Label 7277: @273230 |
| 107317 | GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(273275), // Rule ID 51345 // |
| 107318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107319 | // (umax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMAXU_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 107320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 107321 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107322 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M2), |
| 107325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107326 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107327 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107332 | GIR_RootConstrainSelectedInstOperands, |
| 107333 | // GIR_Coverage, 51345, |
| 107334 | GIR_EraseRootFromParent_Done, |
| 107335 | // Label 7278: @273275 |
| 107336 | GIM_Reject, |
| 107337 | // Label 7276: @273276 |
| 107338 | GIM_Reject, |
| 107339 | // Label 7216: @273277 |
| 107340 | GIM_Try, /*On fail goto*//*Label 7279*/ GIMT_Encode4(273391), |
| 107341 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 107342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 107343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107344 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107346 | GIM_Try, /*On fail goto*//*Label 7280*/ GIMT_Encode4(273345), // Rule ID 51360 // |
| 107347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107348 | // (umax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 107349 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 107350 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107351 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107355 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107356 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107357 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107361 | GIR_RootConstrainSelectedInstOperands, |
| 107362 | // GIR_Coverage, 51360, |
| 107363 | GIR_EraseRootFromParent_Done, |
| 107364 | // Label 7280: @273345 |
| 107365 | GIM_Try, /*On fail goto*//*Label 7281*/ GIMT_Encode4(273390), // Rule ID 51361 // |
| 107366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107367 | // (umax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 107368 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 107369 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107370 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107374 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107375 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107376 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107380 | GIR_RootConstrainSelectedInstOperands, |
| 107381 | // GIR_Coverage, 51361, |
| 107382 | GIR_EraseRootFromParent_Done, |
| 107383 | // Label 7281: @273390 |
| 107384 | GIM_Reject, |
| 107385 | // Label 7279: @273391 |
| 107386 | GIM_Reject, |
| 107387 | // Label 7217: @273392 |
| 107388 | GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(273506), |
| 107389 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 107390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 107391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107394 | GIM_Try, /*On fail goto*//*Label 7283*/ GIMT_Encode4(273460), // Rule ID 51376 // |
| 107395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107396 | // (umax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 107397 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 107398 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107399 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107404 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107405 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 107408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107409 | GIR_RootConstrainSelectedInstOperands, |
| 107410 | // GIR_Coverage, 51376, |
| 107411 | GIR_EraseRootFromParent_Done, |
| 107412 | // Label 7283: @273460 |
| 107413 | GIM_Try, /*On fail goto*//*Label 7284*/ GIMT_Encode4(273505), // Rule ID 51377 // |
| 107414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107415 | // (umax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 107416 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 107417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107422 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107423 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107424 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 107427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107428 | GIR_RootConstrainSelectedInstOperands, |
| 107429 | // GIR_Coverage, 51377, |
| 107430 | GIR_EraseRootFromParent_Done, |
| 107431 | // Label 7284: @273505 |
| 107432 | GIM_Reject, |
| 107433 | // Label 7282: @273506 |
| 107434 | GIM_Reject, |
| 107435 | // Label 7218: @273507 |
| 107436 | GIM_Try, /*On fail goto*//*Label 7285*/ GIMT_Encode4(273621), |
| 107437 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 107438 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, |
| 107439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107440 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107441 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 107442 | GIM_Try, /*On fail goto*//*Label 7286*/ GIMT_Encode4(273575), // Rule ID 51348 // |
| 107443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107444 | // (umax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 107445 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 107446 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107447 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107451 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107452 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107453 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107457 | GIR_RootConstrainSelectedInstOperands, |
| 107458 | // GIR_Coverage, 51348, |
| 107459 | GIR_EraseRootFromParent_Done, |
| 107460 | // Label 7286: @273575 |
| 107461 | GIM_Try, /*On fail goto*//*Label 7287*/ GIMT_Encode4(273620), // Rule ID 51349 // |
| 107462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107463 | // (umax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMAXU_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 107464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 107465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M4), |
| 107469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107470 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107471 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107472 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107476 | GIR_RootConstrainSelectedInstOperands, |
| 107477 | // GIR_Coverage, 51349, |
| 107478 | GIR_EraseRootFromParent_Done, |
| 107479 | // Label 7287: @273620 |
| 107480 | GIM_Reject, |
| 107481 | // Label 7285: @273621 |
| 107482 | GIM_Reject, |
| 107483 | // Label 7219: @273622 |
| 107484 | GIM_Try, /*On fail goto*//*Label 7288*/ GIMT_Encode4(273736), |
| 107485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 107486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 107487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107490 | GIM_Try, /*On fail goto*//*Label 7289*/ GIMT_Encode4(273690), // Rule ID 51364 // |
| 107491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107492 | // (umax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 107493 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 107494 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107495 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107500 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107501 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107505 | GIR_RootConstrainSelectedInstOperands, |
| 107506 | // GIR_Coverage, 51364, |
| 107507 | GIR_EraseRootFromParent_Done, |
| 107508 | // Label 7289: @273690 |
| 107509 | GIM_Try, /*On fail goto*//*Label 7290*/ GIMT_Encode4(273735), // Rule ID 51365 // |
| 107510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107511 | // (umax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 107512 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 107513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107518 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107520 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107524 | GIR_RootConstrainSelectedInstOperands, |
| 107525 | // GIR_Coverage, 51365, |
| 107526 | GIR_EraseRootFromParent_Done, |
| 107527 | // Label 7290: @273735 |
| 107528 | GIM_Reject, |
| 107529 | // Label 7288: @273736 |
| 107530 | GIM_Reject, |
| 107531 | // Label 7220: @273737 |
| 107532 | GIM_Try, /*On fail goto*//*Label 7291*/ GIMT_Encode4(273851), |
| 107533 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 107534 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, |
| 107535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 107538 | GIM_Try, /*On fail goto*//*Label 7292*/ GIMT_Encode4(273805), // Rule ID 51352 // |
| 107539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 107540 | // (umax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 107541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 107542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107548 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107549 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107553 | GIR_RootConstrainSelectedInstOperands, |
| 107554 | // GIR_Coverage, 51352, |
| 107555 | GIR_EraseRootFromParent_Done, |
| 107556 | // Label 7292: @273805 |
| 107557 | GIM_Try, /*On fail goto*//*Label 7293*/ GIMT_Encode4(273850), // Rule ID 51353 // |
| 107558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 107559 | // (umax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMAXU_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 107560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 107561 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 107562 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAXU_VV_M8), |
| 107565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107566 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107567 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107568 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 107569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 107570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 107572 | GIR_RootConstrainSelectedInstOperands, |
| 107573 | // GIR_Coverage, 51353, |
| 107574 | GIR_EraseRootFromParent_Done, |
| 107575 | // Label 7293: @273850 |
| 107576 | GIM_Reject, |
| 107577 | // Label 7291: @273851 |
| 107578 | GIM_Reject, |
| 107579 | // Label 7221: @273852 |
| 107580 | GIM_Reject, |
| 107581 | // Label 75: @273853 |
| 107582 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 7296*/ GIMT_Encode4(274010), |
| 107583 | /*GILLT_s32*//*Label 7294*/ GIMT_Encode4(273872), |
| 107584 | /*GILLT_s64*//*Label 7295*/ GIMT_Encode4(273941), |
| 107585 | // Label 7294: @273872 |
| 107586 | GIM_Try, /*On fail goto*//*Label 7297*/ GIMT_Encode4(273940), |
| 107587 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107590 | GIM_Try, /*On fail goto*//*Label 7298*/ GIMT_Encode4(273903), // Rule ID 64974 // |
| 107591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), |
| 107592 | // (abs:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CV_ABS:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 107593 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_ABS), |
| 107594 | GIR_RootConstrainSelectedInstOperands, |
| 107595 | // GIR_Coverage, 64974, |
| 107596 | GIR_Done, |
| 107597 | // Label 7298: @273903 |
| 107598 | GIM_Try, /*On fail goto*//*Label 7299*/ GIMT_Encode4(273939), // Rule ID 64911 // |
| 107599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShortForwardBranchOpt_HwMode1), |
| 107600 | // (abs:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (PseudoCCSUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, X0:{ *:[i32] }, 2:{ *:[i32] }, GPR:{ *:[i32] }:$rs1, X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1) |
| 107601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCCSUB), |
| 107602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 107603 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107604 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 107605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 107606 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107607 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 107608 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107609 | GIR_RootConstrainSelectedInstOperands, |
| 107610 | // GIR_Coverage, 64911, |
| 107611 | GIR_EraseRootFromParent_Done, |
| 107612 | // Label 7299: @273939 |
| 107613 | GIM_Reject, |
| 107614 | // Label 7297: @273940 |
| 107615 | GIM_Reject, |
| 107616 | // Label 7295: @273941 |
| 107617 | GIM_Try, /*On fail goto*//*Label 7300*/ GIMT_Encode4(274009), |
| 107618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107620 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107621 | GIM_Try, /*On fail goto*//*Label 7301*/ GIMT_Encode4(273972), // Rule ID 64973 // |
| 107622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), |
| 107623 | // (abs:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CV_ABS:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 107624 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_ABS), |
| 107625 | GIR_RootConstrainSelectedInstOperands, |
| 107626 | // GIR_Coverage, 64973, |
| 107627 | GIR_Done, |
| 107628 | // Label 7301: @273972 |
| 107629 | GIM_Try, /*On fail goto*//*Label 7302*/ GIMT_Encode4(274008), // Rule ID 64910 // |
| 107630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShortForwardBranchOpt_HwMode0), |
| 107631 | // (abs:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (PseudoCCSUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, X0:{ *:[i64] }, 2:{ *:[i64] }, GPR:{ *:[i64] }:$rs1, X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1) |
| 107632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoCCSUB), |
| 107633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 107634 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107635 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 107636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 107637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107638 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 107639 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107640 | GIR_RootConstrainSelectedInstOperands, |
| 107641 | // GIR_Coverage, 64910, |
| 107642 | GIR_EraseRootFromParent_Done, |
| 107643 | // Label 7302: @274008 |
| 107644 | GIM_Reject, |
| 107645 | // Label 7300: @274009 |
| 107646 | GIM_Reject, |
| 107647 | // Label 7296: @274010 |
| 107648 | GIM_Reject, |
| 107649 | // Label 76: @274011 |
| 107650 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 7305*/ GIMT_Encode4(274908), |
| 107651 | /*GILLT_s32*//*Label 7303*/ GIMT_Encode4(274030), |
| 107652 | /*GILLT_s64*//*Label 7304*/ GIMT_Encode4(274615), |
| 107653 | // Label 7303: @274030 |
| 107654 | GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(274061), // Rule ID 1537 // |
| 107655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 107656 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107658 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 107659 | // (lround:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 4:{ *:[i64] }) |
| 107660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 107661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107662 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107664 | GIR_RootConstrainSelectedInstOperands, |
| 107665 | // GIR_Coverage, 1537, |
| 107666 | GIR_EraseRootFromParent_Done, |
| 107667 | // Label 7306: @274061 |
| 107668 | GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(274092), // Rule ID 1538 // |
| 107669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 107670 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 107673 | // (lround:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 4:{ *:[i32] }) |
| 107674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 107675 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107676 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107678 | GIR_RootConstrainSelectedInstOperands, |
| 107679 | // GIR_Coverage, 1538, |
| 107680 | GIR_EraseRootFromParent_Done, |
| 107681 | // Label 7307: @274092 |
| 107682 | GIM_Try, /*On fail goto*//*Label 7308*/ GIMT_Encode4(274123), // Rule ID 1563 // |
| 107683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 107684 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 107687 | // (lround:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 4:{ *:[i64] }) |
| 107688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 107689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107690 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107692 | GIR_RootConstrainSelectedInstOperands, |
| 107693 | // GIR_Coverage, 1563, |
| 107694 | GIR_EraseRootFromParent_Done, |
| 107695 | // Label 7308: @274123 |
| 107696 | GIM_Try, /*On fail goto*//*Label 7309*/ GIMT_Encode4(274154), // Rule ID 1564 // |
| 107697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 107698 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107700 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 107701 | // (lround:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1, 4:{ *:[i32] }) |
| 107702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 107703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107704 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107706 | GIR_RootConstrainSelectedInstOperands, |
| 107707 | // GIR_Coverage, 1564, |
| 107708 | GIR_EraseRootFromParent_Done, |
| 107709 | // Label 7309: @274154 |
| 107710 | GIM_Try, /*On fail goto*//*Label 7310*/ GIMT_Encode4(274185), // Rule ID 1918 // |
| 107711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 107712 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 107715 | // (lround:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 107716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D), |
| 107717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107718 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107720 | GIR_RootConstrainSelectedInstOperands, |
| 107721 | // GIR_Coverage, 1918, |
| 107722 | GIR_EraseRootFromParent_Done, |
| 107723 | // Label 7310: @274185 |
| 107724 | GIM_Try, /*On fail goto*//*Label 7311*/ GIMT_Encode4(274216), // Rule ID 1919 // |
| 107725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 107726 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 107729 | // (lround:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, 4:{ *:[i32] }) |
| 107730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D), |
| 107731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107732 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107734 | GIR_RootConstrainSelectedInstOperands, |
| 107735 | // GIR_Coverage, 1919, |
| 107736 | GIR_EraseRootFromParent_Done, |
| 107737 | // Label 7311: @274216 |
| 107738 | GIM_Try, /*On fail goto*//*Label 7312*/ GIMT_Encode4(274247), // Rule ID 1944 // |
| 107739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 107740 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107742 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 107743 | // (lround:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_W_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 107744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D_IN32X), |
| 107745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107746 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107748 | GIR_RootConstrainSelectedInstOperands, |
| 107749 | // GIR_Coverage, 1944, |
| 107750 | GIR_EraseRootFromParent_Done, |
| 107751 | // Label 7312: @274247 |
| 107752 | GIM_Try, /*On fail goto*//*Label 7313*/ GIMT_Encode4(274278), // Rule ID 1945 // |
| 107753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 107754 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 107757 | // (lround:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCVT_W_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1, 4:{ *:[i32] }) |
| 107758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_D_IN32X), |
| 107759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107760 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107762 | GIR_RootConstrainSelectedInstOperands, |
| 107763 | // GIR_Coverage, 1945, |
| 107764 | GIR_EraseRootFromParent_Done, |
| 107765 | // Label 7313: @274278 |
| 107766 | GIM_Try, /*On fail goto*//*Label 7314*/ GIMT_Encode4(274309), // Rule ID 2254 // |
| 107767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 107768 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 107771 | // (lround:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 107772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H), |
| 107773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107774 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107776 | GIR_RootConstrainSelectedInstOperands, |
| 107777 | // GIR_Coverage, 2254, |
| 107778 | GIR_EraseRootFromParent_Done, |
| 107779 | // Label 7314: @274309 |
| 107780 | GIM_Try, /*On fail goto*//*Label 7315*/ GIMT_Encode4(274340), // Rule ID 2255 // |
| 107781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 107782 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107784 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 107785 | // (lround:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_H:{ *:[i32] } ?:{ *:[f16] }:$rs1, 4:{ *:[i32] }) |
| 107786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H), |
| 107787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107788 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107790 | GIR_RootConstrainSelectedInstOperands, |
| 107791 | // GIR_Coverage, 2255, |
| 107792 | GIR_EraseRootFromParent_Done, |
| 107793 | // Label 7315: @274340 |
| 107794 | GIM_Try, /*On fail goto*//*Label 7316*/ GIMT_Encode4(274371), // Rule ID 2280 // |
| 107795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 107796 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 107799 | // (lround:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 107800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H_INX), |
| 107801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107802 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107804 | GIR_RootConstrainSelectedInstOperands, |
| 107805 | // GIR_Coverage, 2280, |
| 107806 | GIR_EraseRootFromParent_Done, |
| 107807 | // Label 7316: @274371 |
| 107808 | GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(274402), // Rule ID 2281 // |
| 107809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 107810 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107812 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 107813 | // (lround:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1, 4:{ *:[i32] }) |
| 107814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_H_INX), |
| 107815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107816 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107818 | GIR_RootConstrainSelectedInstOperands, |
| 107819 | // GIR_Coverage, 2281, |
| 107820 | GIR_EraseRootFromParent_Done, |
| 107821 | // Label 7317: @274402 |
| 107822 | GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(274455), // Rule ID 2386 // |
| 107823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode0), |
| 107824 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 107827 | // (lround:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 4:{ *:[i64] }) |
| 107828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 107829 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 107830 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107831 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 107832 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 107833 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 107835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107836 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107838 | GIR_RootConstrainSelectedInstOperands, |
| 107839 | // GIR_Coverage, 2386, |
| 107840 | GIR_EraseRootFromParent_Done, |
| 107841 | // Label 7318: @274455 |
| 107842 | GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(274508), // Rule ID 2387 // |
| 107843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_NoStdExtZfh_HwMode1), |
| 107844 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 107847 | // (lround:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCVT_W_S:{ *:[i32] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 4:{ *:[i32] }) |
| 107848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 107849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 107850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107851 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 107852 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 107853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S), |
| 107855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107856 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107858 | GIR_RootConstrainSelectedInstOperands, |
| 107859 | // GIR_Coverage, 2387, |
| 107860 | GIR_EraseRootFromParent_Done, |
| 107861 | // Label 7319: @274508 |
| 107862 | GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(274561), // Rule ID 2410 // |
| 107863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode0), |
| 107864 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107866 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 107867 | // (lround:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 4:{ *:[i64] }) |
| 107868 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 107869 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 107870 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107871 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 107872 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 107873 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 107875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107876 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107878 | GIR_RootConstrainSelectedInstOperands, |
| 107879 | // GIR_Coverage, 2410, |
| 107880 | GIR_EraseRootFromParent_Done, |
| 107881 | // Label 7320: @274561 |
| 107882 | GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(274614), // Rule ID 2411 // |
| 107883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_NoStdExtZhinx_HwMode1), |
| 107884 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 107887 | // (lround:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_W_S_INX:{ *:[i32] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i32] }), 4:{ *:[i32] }) |
| 107888 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 107889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 107890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107891 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 107892 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 107893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 107894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_W_S_INX), |
| 107895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107896 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 107897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107898 | GIR_RootConstrainSelectedInstOperands, |
| 107899 | // GIR_Coverage, 2411, |
| 107900 | GIR_EraseRootFromParent_Done, |
| 107901 | // Label 7321: @274614 |
| 107902 | GIM_Reject, |
| 107903 | // Label 7304: @274615 |
| 107904 | GIM_Try, /*On fail goto*//*Label 7322*/ GIMT_Encode4(274646), // Rule ID 1590 // |
| 107905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 107906 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107908 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 107909 | // (lround:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_L_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 4:{ *:[i64] }) |
| 107910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 107911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107912 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107914 | GIR_RootConstrainSelectedInstOperands, |
| 107915 | // GIR_Coverage, 1590, |
| 107916 | GIR_EraseRootFromParent_Done, |
| 107917 | // Label 7322: @274646 |
| 107918 | GIM_Try, /*On fail goto*//*Label 7323*/ GIMT_Encode4(274677), // Rule ID 1618 // |
| 107919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 107920 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 107921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 107923 | // (lround:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 107924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 107925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107926 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 107928 | GIR_RootConstrainSelectedInstOperands, |
| 107929 | // GIR_Coverage, 1618, |
| 107930 | GIR_EraseRootFromParent_Done, |
| 107931 | // Label 7323: @274677 |
| 107932 | GIM_Try, /*On fail goto*//*Label 7324*/ GIMT_Encode4(274708), // Rule ID 1975 // |
| 107933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 107934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 107937 | // (lround:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 107938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D), |
| 107939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107940 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107942 | GIR_RootConstrainSelectedInstOperands, |
| 107943 | // GIR_Coverage, 1975, |
| 107944 | GIR_EraseRootFromParent_Done, |
| 107945 | // Label 7324: @274708 |
| 107946 | GIM_Try, /*On fail goto*//*Label 7325*/ GIMT_Encode4(274739), // Rule ID 2003 // |
| 107947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 107948 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 107949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107950 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107951 | // (lround:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_L_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 107952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D_INX), |
| 107953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107954 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107956 | GIR_RootConstrainSelectedInstOperands, |
| 107957 | // GIR_Coverage, 2003, |
| 107958 | GIR_EraseRootFromParent_Done, |
| 107959 | // Label 7325: @274739 |
| 107960 | GIM_Try, /*On fail goto*//*Label 7326*/ GIMT_Encode4(274770), // Rule ID 2305 // |
| 107961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 107962 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107964 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 107965 | // (lround:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 107966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H), |
| 107967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107968 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107970 | GIR_RootConstrainSelectedInstOperands, |
| 107971 | // GIR_Coverage, 2305, |
| 107972 | GIR_EraseRootFromParent_Done, |
| 107973 | // Label 7326: @274770 |
| 107974 | GIM_Try, /*On fail goto*//*Label 7327*/ GIMT_Encode4(274801), // Rule ID 2331 // |
| 107975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 107976 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 107979 | // (lround:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 107980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H_INX), |
| 107981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 107982 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 107983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 107984 | GIR_RootConstrainSelectedInstOperands, |
| 107985 | // GIR_Coverage, 2331, |
| 107986 | GIR_EraseRootFromParent_Done, |
| 107987 | // Label 7327: @274801 |
| 107988 | GIM_Try, /*On fail goto*//*Label 7328*/ GIMT_Encode4(274854), // Rule ID 2429 // |
| 107989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 107990 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 107991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 107992 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 107993 | // (lround:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_S:{ *:[i64] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 4:{ *:[i64] }) |
| 107994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 107995 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 107996 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 107997 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 107998 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 107999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 108001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108002 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108004 | GIR_RootConstrainSelectedInstOperands, |
| 108005 | // GIR_Coverage, 2429, |
| 108006 | GIR_EraseRootFromParent_Done, |
| 108007 | // Label 7328: @274854 |
| 108008 | GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(274907), // Rule ID 2445 // |
| 108009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 108010 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 108011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108012 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 108013 | // (lround:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 4:{ *:[i64] }) |
| 108014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 108015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 108016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108017 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 108018 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 108019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 108021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108022 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108024 | GIR_RootConstrainSelectedInstOperands, |
| 108025 | // GIR_Coverage, 2445, |
| 108026 | GIR_EraseRootFromParent_Done, |
| 108027 | // Label 7329: @274907 |
| 108028 | GIM_Reject, |
| 108029 | // Label 7305: @274908 |
| 108030 | GIM_Reject, |
| 108031 | // Label 77: @274909 |
| 108032 | GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(275210), |
| 108033 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 108034 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 7334*/ GIMT_Encode4(275209), |
| 108035 | /*GILLT_s16*//*Label 7331*/ GIMT_Encode4(274940), |
| 108036 | /*GILLT_s32*//*Label 7332*/ GIMT_Encode4(275091), |
| 108037 | /*GILLT_s64*//*Label 7333*/ GIMT_Encode4(275150), |
| 108038 | // Label 7331: @274940 |
| 108039 | GIM_Try, /*On fail goto*//*Label 7335*/ GIMT_Encode4(275090), |
| 108040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108041 | GIM_Try, /*On fail goto*//*Label 7336*/ GIMT_Encode4(274973), // Rule ID 2307 // |
| 108042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_IsRV64_HwMode0), |
| 108043 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 108044 | // (llround:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_H:{ *:[i64] } ?:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 108045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H), |
| 108046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108047 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108049 | GIR_RootConstrainSelectedInstOperands, |
| 108050 | // GIR_Coverage, 2307, |
| 108051 | GIR_EraseRootFromParent_Done, |
| 108052 | // Label 7336: @274973 |
| 108053 | GIM_Try, /*On fail goto*//*Label 7337*/ GIMT_Encode4(274997), // Rule ID 2333 // |
| 108054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_IsRV64_HwMode0), |
| 108055 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 108056 | // (llround:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1, 4:{ *:[i64] }) |
| 108057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_H_INX), |
| 108058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108059 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108061 | GIR_RootConstrainSelectedInstOperands, |
| 108062 | // GIR_Coverage, 2333, |
| 108063 | GIR_EraseRootFromParent_Done, |
| 108064 | // Label 7337: @274997 |
| 108065 | GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(275043), // Rule ID 2431 // |
| 108066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfhmin_IsRV64_NoStdExtZfh_HwMode0), |
| 108067 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 108068 | // (llround:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCVT_L_S:{ *:[i64] } (FCVT_S_H:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 4:{ *:[i64] }) |
| 108069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 108070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H), |
| 108071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108072 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 108073 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 108074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 108076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108077 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108079 | GIR_RootConstrainSelectedInstOperands, |
| 108080 | // GIR_Coverage, 2431, |
| 108081 | GIR_EraseRootFromParent_Done, |
| 108082 | // Label 7338: @275043 |
| 108083 | GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(275089), // Rule ID 2447 // |
| 108084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinxmin_IsRV64_NoStdExtZhinx_HwMode0), |
| 108085 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 108086 | // (llround:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } (FCVT_S_H_INX:{ *:[f32] } ?:{ *:[f16] }:$rs1, 0:{ *:[i64] }), 4:{ *:[i64] }) |
| 108087 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 108088 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::FCVT_S_H_INX), |
| 108089 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108090 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 |
| 108091 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 108092 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 108094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108095 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108097 | GIR_RootConstrainSelectedInstOperands, |
| 108098 | // GIR_Coverage, 2447, |
| 108099 | GIR_EraseRootFromParent_Done, |
| 108100 | // Label 7339: @275089 |
| 108101 | GIM_Reject, |
| 108102 | // Label 7335: @275090 |
| 108103 | GIM_Reject, |
| 108104 | // Label 7332: @275091 |
| 108105 | GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(275149), |
| 108106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108107 | GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(275124), // Rule ID 1592 // |
| 108108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_IsRV64_HwMode0), |
| 108109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 108110 | // (llround:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_L_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 4:{ *:[i64] }) |
| 108111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S), |
| 108112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108113 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108115 | GIR_RootConstrainSelectedInstOperands, |
| 108116 | // GIR_Coverage, 1592, |
| 108117 | GIR_EraseRootFromParent_Done, |
| 108118 | // Label 7341: @275124 |
| 108119 | GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(275148), // Rule ID 1620 // |
| 108120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_IsRV64_HwMode0), |
| 108121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 108122 | // (llround:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCVT_L_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 108123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_S_INX), |
| 108124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108125 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 108127 | GIR_RootConstrainSelectedInstOperands, |
| 108128 | // GIR_Coverage, 1620, |
| 108129 | GIR_EraseRootFromParent_Done, |
| 108130 | // Label 7342: @275148 |
| 108131 | GIM_Reject, |
| 108132 | // Label 7340: @275149 |
| 108133 | GIM_Reject, |
| 108134 | // Label 7333: @275150 |
| 108135 | GIM_Try, /*On fail goto*//*Label 7343*/ GIMT_Encode4(275208), |
| 108136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108137 | GIM_Try, /*On fail goto*//*Label 7344*/ GIMT_Encode4(275183), // Rule ID 1977 // |
| 108138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_IsRV64_HwMode0), |
| 108139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 108140 | // (llround:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 108141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D), |
| 108142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108143 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108145 | GIR_RootConstrainSelectedInstOperands, |
| 108146 | // GIR_Coverage, 1977, |
| 108147 | GIR_EraseRootFromParent_Done, |
| 108148 | // Label 7344: @275183 |
| 108149 | GIM_Try, /*On fail goto*//*Label 7345*/ GIMT_Encode4(275207), // Rule ID 2005 // |
| 108150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 108151 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108152 | // (llround:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCVT_L_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1, 4:{ *:[i64] }) |
| 108153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FCVT_L_D_INX), |
| 108154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108157 | GIR_RootConstrainSelectedInstOperands, |
| 108158 | // GIR_Coverage, 2005, |
| 108159 | GIR_EraseRootFromParent_Done, |
| 108160 | // Label 7345: @275207 |
| 108161 | GIM_Reject, |
| 108162 | // Label 7343: @275208 |
| 108163 | GIM_Reject, |
| 108164 | // Label 7334: @275209 |
| 108165 | GIM_Reject, |
| 108166 | // Label 7330: @275210 |
| 108167 | GIM_Reject, |
| 108168 | // Label 78: @275211 |
| 108169 | GIM_Try, /*On fail goto*//*Label 7346*/ GIMT_Encode4(275226), // Rule ID 2 // |
| 108170 | // MIs[0] imm20 |
| 108171 | GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 108172 | // (br (bb:{ *:[Other] }):$imm20) => (PseudoBR (bb:{ *:[Other] }):$imm20) |
| 108173 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::PseudoBR), |
| 108174 | GIR_RootConstrainSelectedInstOperands, |
| 108175 | // GIR_Coverage, 2, |
| 108176 | GIR_Done, |
| 108177 | // Label 7346: @275226 |
| 108178 | GIM_Reject, |
| 108179 | // Label 79: @275227 |
| 108180 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7371*/ GIMT_Encode4(277776), |
| 108181 | /*GILLT_s32*//*Label 7347*/ GIMT_Encode4(275362), |
| 108182 | /*GILLT_s64*//*Label 7348*/ GIMT_Encode4(275440), GIMT_Encode4(0), |
| 108183 | /*GILLT_nxv1s8*//*Label 7349*/ GIMT_Encode4(275488), |
| 108184 | /*GILLT_nxv1s16*//*Label 7350*/ GIMT_Encode4(275592), |
| 108185 | /*GILLT_nxv1s32*//*Label 7351*/ GIMT_Encode4(275696), |
| 108186 | /*GILLT_nxv1s64*//*Label 7352*/ GIMT_Encode4(275800), GIMT_Encode4(0), |
| 108187 | /*GILLT_nxv2s8*//*Label 7353*/ GIMT_Encode4(275904), |
| 108188 | /*GILLT_nxv2s16*//*Label 7354*/ GIMT_Encode4(276008), |
| 108189 | /*GILLT_nxv2s32*//*Label 7355*/ GIMT_Encode4(276112), |
| 108190 | /*GILLT_nxv2s64*//*Label 7356*/ GIMT_Encode4(276216), GIMT_Encode4(0), |
| 108191 | /*GILLT_nxv4s8*//*Label 7357*/ GIMT_Encode4(276320), |
| 108192 | /*GILLT_nxv4s16*//*Label 7358*/ GIMT_Encode4(276424), |
| 108193 | /*GILLT_nxv4s32*//*Label 7359*/ GIMT_Encode4(276528), |
| 108194 | /*GILLT_nxv4s64*//*Label 7360*/ GIMT_Encode4(276632), GIMT_Encode4(0), |
| 108195 | /*GILLT_nxv8s8*//*Label 7361*/ GIMT_Encode4(276736), |
| 108196 | /*GILLT_nxv8s16*//*Label 7362*/ GIMT_Encode4(276840), |
| 108197 | /*GILLT_nxv8s32*//*Label 7363*/ GIMT_Encode4(276944), |
| 108198 | /*GILLT_nxv8s64*//*Label 7364*/ GIMT_Encode4(277048), GIMT_Encode4(0), |
| 108199 | /*GILLT_nxv16s8*//*Label 7365*/ GIMT_Encode4(277152), |
| 108200 | /*GILLT_nxv16s16*//*Label 7366*/ GIMT_Encode4(277256), |
| 108201 | /*GILLT_nxv16s32*//*Label 7367*/ GIMT_Encode4(277360), GIMT_Encode4(0), |
| 108202 | /*GILLT_nxv32s8*//*Label 7368*/ GIMT_Encode4(277464), |
| 108203 | /*GILLT_nxv32s16*//*Label 7369*/ GIMT_Encode4(277568), GIMT_Encode4(0), |
| 108204 | /*GILLT_nxv64s8*//*Label 7370*/ GIMT_Encode4(277672), |
| 108205 | // Label 7347: @275362 |
| 108206 | GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(275439), |
| 108207 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 108208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108209 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108210 | GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(275393), // Rule ID 2667 // |
| 108211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 108212 | // (cttz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CTZ:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 108213 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CTZ), |
| 108214 | GIR_RootConstrainSelectedInstOperands, |
| 108215 | // GIR_Coverage, 2667, |
| 108216 | GIR_Done, |
| 108217 | // Label 7373: @275393 |
| 108218 | GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(275408), // Rule ID 2795 // |
| 108219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), |
| 108220 | // (cttz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CTZW:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 108221 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CTZW), |
| 108222 | GIR_RootConstrainSelectedInstOperands, |
| 108223 | // GIR_Coverage, 2795, |
| 108224 | GIR_Done, |
| 108225 | // Label 7374: @275408 |
| 108226 | GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(275423), // Rule ID 2796 // |
| 108227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode1), |
| 108228 | // (cttz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CTZW:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 108229 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CTZW), |
| 108230 | GIR_RootConstrainSelectedInstOperands, |
| 108231 | // GIR_Coverage, 2796, |
| 108232 | GIR_Done, |
| 108233 | // Label 7375: @275423 |
| 108234 | GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(275438), // Rule ID 64957 // |
| 108235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 108236 | // (cttz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CV_FF1:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 108237 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_FF1), |
| 108238 | GIR_RootConstrainSelectedInstOperands, |
| 108239 | // GIR_Coverage, 64957, |
| 108240 | GIR_Done, |
| 108241 | // Label 7376: @275438 |
| 108242 | GIM_Reject, |
| 108243 | // Label 7372: @275439 |
| 108244 | GIM_Reject, |
| 108245 | // Label 7348: @275440 |
| 108246 | GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(275487), |
| 108247 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 108248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108249 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 108250 | GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(275471), // Rule ID 2666 // |
| 108251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 108252 | // (cttz:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CTZ:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 108253 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CTZ), |
| 108254 | GIR_RootConstrainSelectedInstOperands, |
| 108255 | // GIR_Coverage, 2666, |
| 108256 | GIR_Done, |
| 108257 | // Label 7378: @275471 |
| 108258 | GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(275486), // Rule ID 64956 // |
| 108259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0), |
| 108260 | // (cttz:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CV_FF1:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 108261 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_FF1), |
| 108262 | GIR_RootConstrainSelectedInstOperands, |
| 108263 | // GIR_Coverage, 64956, |
| 108264 | GIR_Done, |
| 108265 | // Label 7379: @275486 |
| 108266 | GIM_Reject, |
| 108267 | // Label 7377: @275487 |
| 108268 | GIM_Reject, |
| 108269 | // Label 7349: @275488 |
| 108270 | GIM_Try, /*On fail goto*//*Label 7380*/ GIMT_Encode4(275591), |
| 108271 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 108272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108274 | GIM_Try, /*On fail goto*//*Label 7381*/ GIMT_Encode4(275547), // Rule ID 59672 // |
| 108275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108276 | // (cttz:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVCTZ_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 108277 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 108278 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108279 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF8), |
| 108282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108283 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108284 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108288 | GIR_RootConstrainSelectedInstOperands, |
| 108289 | // GIR_Coverage, 59672, |
| 108290 | GIR_EraseRootFromParent_Done, |
| 108291 | // Label 7381: @275547 |
| 108292 | GIM_Try, /*On fail goto*//*Label 7382*/ GIMT_Encode4(275590), // Rule ID 59673 // |
| 108293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108294 | // (cttz:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVCTZ_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 108295 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 108296 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108297 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF8), |
| 108300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108302 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108306 | GIR_RootConstrainSelectedInstOperands, |
| 108307 | // GIR_Coverage, 59673, |
| 108308 | GIR_EraseRootFromParent_Done, |
| 108309 | // Label 7382: @275590 |
| 108310 | GIM_Reject, |
| 108311 | // Label 7380: @275591 |
| 108312 | GIM_Reject, |
| 108313 | // Label 7350: @275592 |
| 108314 | GIM_Try, /*On fail goto*//*Label 7383*/ GIMT_Encode4(275695), |
| 108315 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 108316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108318 | GIM_Try, /*On fail goto*//*Label 7384*/ GIMT_Encode4(275651), // Rule ID 59678 // |
| 108319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108320 | // (cttz:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVCTZ_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 108321 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 108322 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108323 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF4), |
| 108326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108327 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108328 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108332 | GIR_RootConstrainSelectedInstOperands, |
| 108333 | // GIR_Coverage, 59678, |
| 108334 | GIR_EraseRootFromParent_Done, |
| 108335 | // Label 7384: @275651 |
| 108336 | GIM_Try, /*On fail goto*//*Label 7385*/ GIMT_Encode4(275694), // Rule ID 59679 // |
| 108337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108338 | // (cttz:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVCTZ_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 108339 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 108340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108341 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF4), |
| 108344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108345 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108346 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108350 | GIR_RootConstrainSelectedInstOperands, |
| 108351 | // GIR_Coverage, 59679, |
| 108352 | GIR_EraseRootFromParent_Done, |
| 108353 | // Label 7385: @275694 |
| 108354 | GIM_Reject, |
| 108355 | // Label 7383: @275695 |
| 108356 | GIM_Reject, |
| 108357 | // Label 7351: @275696 |
| 108358 | GIM_Try, /*On fail goto*//*Label 7386*/ GIMT_Encode4(275799), |
| 108359 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 108360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108361 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108362 | GIM_Try, /*On fail goto*//*Label 7387*/ GIMT_Encode4(275755), // Rule ID 59682 // |
| 108363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108364 | // (cttz:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVCTZ_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 108365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 108366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF2), |
| 108370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108371 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108372 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108376 | GIR_RootConstrainSelectedInstOperands, |
| 108377 | // GIR_Coverage, 59682, |
| 108378 | GIR_EraseRootFromParent_Done, |
| 108379 | // Label 7387: @275755 |
| 108380 | GIM_Try, /*On fail goto*//*Label 7388*/ GIMT_Encode4(275798), // Rule ID 59683 // |
| 108381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108382 | // (cttz:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVCTZ_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 108383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 108384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF2), |
| 108388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108390 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108394 | GIR_RootConstrainSelectedInstOperands, |
| 108395 | // GIR_Coverage, 59683, |
| 108396 | GIR_EraseRootFromParent_Done, |
| 108397 | // Label 7388: @275798 |
| 108398 | GIM_Reject, |
| 108399 | // Label 7386: @275799 |
| 108400 | GIM_Reject, |
| 108401 | // Label 7352: @275800 |
| 108402 | GIM_Try, /*On fail goto*//*Label 7389*/ GIMT_Encode4(275903), |
| 108403 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 108404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108405 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108406 | GIM_Try, /*On fail goto*//*Label 7390*/ GIMT_Encode4(275859), // Rule ID 59690 // |
| 108407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 108408 | // (cttz:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 108409 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 108410 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108411 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108415 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108416 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108420 | GIR_RootConstrainSelectedInstOperands, |
| 108421 | // GIR_Coverage, 59690, |
| 108422 | GIR_EraseRootFromParent_Done, |
| 108423 | // Label 7390: @275859 |
| 108424 | GIM_Try, /*On fail goto*//*Label 7391*/ GIMT_Encode4(275902), // Rule ID 59691 // |
| 108425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 108426 | // (cttz:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 108427 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 108428 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108429 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108430 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108433 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108434 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108438 | GIR_RootConstrainSelectedInstOperands, |
| 108439 | // GIR_Coverage, 59691, |
| 108440 | GIR_EraseRootFromParent_Done, |
| 108441 | // Label 7391: @275902 |
| 108442 | GIM_Reject, |
| 108443 | // Label 7389: @275903 |
| 108444 | GIM_Reject, |
| 108445 | // Label 7353: @275904 |
| 108446 | GIM_Try, /*On fail goto*//*Label 7392*/ GIMT_Encode4(276007), |
| 108447 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 108448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108450 | GIM_Try, /*On fail goto*//*Label 7393*/ GIMT_Encode4(275963), // Rule ID 59674 // |
| 108451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108452 | // (cttz:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVCTZ_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 108453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 108454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF4), |
| 108458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108460 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108464 | GIR_RootConstrainSelectedInstOperands, |
| 108465 | // GIR_Coverage, 59674, |
| 108466 | GIR_EraseRootFromParent_Done, |
| 108467 | // Label 7393: @275963 |
| 108468 | GIM_Try, /*On fail goto*//*Label 7394*/ GIMT_Encode4(276006), // Rule ID 59675 // |
| 108469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108470 | // (cttz:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVCTZ_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 108471 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 108472 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108473 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108474 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF4), |
| 108476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108477 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108478 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108482 | GIR_RootConstrainSelectedInstOperands, |
| 108483 | // GIR_Coverage, 59675, |
| 108484 | GIR_EraseRootFromParent_Done, |
| 108485 | // Label 7394: @276006 |
| 108486 | GIM_Reject, |
| 108487 | // Label 7392: @276007 |
| 108488 | GIM_Reject, |
| 108489 | // Label 7354: @276008 |
| 108490 | GIM_Try, /*On fail goto*//*Label 7395*/ GIMT_Encode4(276111), |
| 108491 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 108492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108494 | GIM_Try, /*On fail goto*//*Label 7396*/ GIMT_Encode4(276067), // Rule ID 59680 // |
| 108495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108496 | // (cttz:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVCTZ_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 108497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 108498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108499 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF2), |
| 108502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108504 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108508 | GIR_RootConstrainSelectedInstOperands, |
| 108509 | // GIR_Coverage, 59680, |
| 108510 | GIR_EraseRootFromParent_Done, |
| 108511 | // Label 7396: @276067 |
| 108512 | GIM_Try, /*On fail goto*//*Label 7397*/ GIMT_Encode4(276110), // Rule ID 59681 // |
| 108513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108514 | // (cttz:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVCTZ_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 108515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 108516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF2), |
| 108520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108521 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108522 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108526 | GIR_RootConstrainSelectedInstOperands, |
| 108527 | // GIR_Coverage, 59681, |
| 108528 | GIR_EraseRootFromParent_Done, |
| 108529 | // Label 7397: @276110 |
| 108530 | GIM_Reject, |
| 108531 | // Label 7395: @276111 |
| 108532 | GIM_Reject, |
| 108533 | // Label 7355: @276112 |
| 108534 | GIM_Try, /*On fail goto*//*Label 7398*/ GIMT_Encode4(276215), |
| 108535 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 108536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108537 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108538 | GIM_Try, /*On fail goto*//*Label 7399*/ GIMT_Encode4(276171), // Rule ID 59688 // |
| 108539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108540 | // (cttz:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 108541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 108542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108548 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108552 | GIR_RootConstrainSelectedInstOperands, |
| 108553 | // GIR_Coverage, 59688, |
| 108554 | GIR_EraseRootFromParent_Done, |
| 108555 | // Label 7399: @276171 |
| 108556 | GIM_Try, /*On fail goto*//*Label 7400*/ GIMT_Encode4(276214), // Rule ID 59689 // |
| 108557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108558 | // (cttz:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 108559 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 108560 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108561 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108562 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108565 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108566 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108570 | GIR_RootConstrainSelectedInstOperands, |
| 108571 | // GIR_Coverage, 59689, |
| 108572 | GIR_EraseRootFromParent_Done, |
| 108573 | // Label 7400: @276214 |
| 108574 | GIM_Reject, |
| 108575 | // Label 7398: @276215 |
| 108576 | GIM_Reject, |
| 108577 | // Label 7356: @276216 |
| 108578 | GIM_Try, /*On fail goto*//*Label 7401*/ GIMT_Encode4(276319), |
| 108579 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 108580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108582 | GIM_Try, /*On fail goto*//*Label 7402*/ GIMT_Encode4(276275), // Rule ID 59710 // |
| 108583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 108584 | // (cttz:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 108585 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 108586 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108587 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108588 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108591 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108592 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108596 | GIR_RootConstrainSelectedInstOperands, |
| 108597 | // GIR_Coverage, 59710, |
| 108598 | GIR_EraseRootFromParent_Done, |
| 108599 | // Label 7402: @276275 |
| 108600 | GIM_Try, /*On fail goto*//*Label 7403*/ GIMT_Encode4(276318), // Rule ID 59711 // |
| 108601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 108602 | // (cttz:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 108603 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 108604 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108605 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108609 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108610 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108614 | GIR_RootConstrainSelectedInstOperands, |
| 108615 | // GIR_Coverage, 59711, |
| 108616 | GIR_EraseRootFromParent_Done, |
| 108617 | // Label 7403: @276318 |
| 108618 | GIM_Reject, |
| 108619 | // Label 7401: @276319 |
| 108620 | GIM_Reject, |
| 108621 | // Label 7357: @276320 |
| 108622 | GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(276423), |
| 108623 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 108624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108626 | GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(276379), // Rule ID 59676 // |
| 108627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108628 | // (cttz:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVCTZ_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 108629 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 108630 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108631 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF2), |
| 108634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108635 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108636 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108640 | GIR_RootConstrainSelectedInstOperands, |
| 108641 | // GIR_Coverage, 59676, |
| 108642 | GIR_EraseRootFromParent_Done, |
| 108643 | // Label 7405: @276379 |
| 108644 | GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(276422), // Rule ID 59677 // |
| 108645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108646 | // (cttz:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVCTZ_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 108647 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 108648 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_MF2), |
| 108652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108654 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108658 | GIR_RootConstrainSelectedInstOperands, |
| 108659 | // GIR_Coverage, 59677, |
| 108660 | GIR_EraseRootFromParent_Done, |
| 108661 | // Label 7406: @276422 |
| 108662 | GIM_Reject, |
| 108663 | // Label 7404: @276423 |
| 108664 | GIM_Reject, |
| 108665 | // Label 7358: @276424 |
| 108666 | GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(276527), |
| 108667 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 108668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108669 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108670 | GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(276483), // Rule ID 59686 // |
| 108671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108672 | // (cttz:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 108673 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 108674 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108675 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108679 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108680 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108684 | GIR_RootConstrainSelectedInstOperands, |
| 108685 | // GIR_Coverage, 59686, |
| 108686 | GIR_EraseRootFromParent_Done, |
| 108687 | // Label 7408: @276483 |
| 108688 | GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(276526), // Rule ID 59687 // |
| 108689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108690 | // (cttz:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 108691 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 108692 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108693 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108697 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108698 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108702 | GIR_RootConstrainSelectedInstOperands, |
| 108703 | // GIR_Coverage, 59687, |
| 108704 | GIR_EraseRootFromParent_Done, |
| 108705 | // Label 7409: @276526 |
| 108706 | GIM_Reject, |
| 108707 | // Label 7407: @276527 |
| 108708 | GIM_Reject, |
| 108709 | // Label 7359: @276528 |
| 108710 | GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(276631), |
| 108711 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 108712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108713 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108714 | GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(276587), // Rule ID 59704 // |
| 108715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108716 | // (cttz:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 108717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 108718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108719 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108728 | GIR_RootConstrainSelectedInstOperands, |
| 108729 | // GIR_Coverage, 59704, |
| 108730 | GIR_EraseRootFromParent_Done, |
| 108731 | // Label 7411: @276587 |
| 108732 | GIM_Try, /*On fail goto*//*Label 7412*/ GIMT_Encode4(276630), // Rule ID 59705 // |
| 108733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108734 | // (cttz:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 108735 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 108736 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108737 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108742 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108746 | GIR_RootConstrainSelectedInstOperands, |
| 108747 | // GIR_Coverage, 59705, |
| 108748 | GIR_EraseRootFromParent_Done, |
| 108749 | // Label 7412: @276630 |
| 108750 | GIM_Reject, |
| 108751 | // Label 7410: @276631 |
| 108752 | GIM_Reject, |
| 108753 | // Label 7360: @276632 |
| 108754 | GIM_Try, /*On fail goto*//*Label 7413*/ GIMT_Encode4(276735), |
| 108755 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 108756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 108757 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 108758 | GIM_Try, /*On fail goto*//*Label 7414*/ GIMT_Encode4(276691), // Rule ID 59712 // |
| 108759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 108760 | // (cttz:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 108761 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 108762 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108763 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 108766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108768 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108772 | GIR_RootConstrainSelectedInstOperands, |
| 108773 | // GIR_Coverage, 59712, |
| 108774 | GIR_EraseRootFromParent_Done, |
| 108775 | // Label 7414: @276691 |
| 108776 | GIM_Try, /*On fail goto*//*Label 7415*/ GIMT_Encode4(276734), // Rule ID 59713 // |
| 108777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 108778 | // (cttz:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 108779 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 108780 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108781 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108782 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 108784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108785 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108786 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108790 | GIR_RootConstrainSelectedInstOperands, |
| 108791 | // GIR_Coverage, 59713, |
| 108792 | GIR_EraseRootFromParent_Done, |
| 108793 | // Label 7415: @276734 |
| 108794 | GIM_Reject, |
| 108795 | // Label 7413: @276735 |
| 108796 | GIM_Reject, |
| 108797 | // Label 7361: @276736 |
| 108798 | GIM_Try, /*On fail goto*//*Label 7416*/ GIMT_Encode4(276839), |
| 108799 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 108800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108801 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 108802 | GIM_Try, /*On fail goto*//*Label 7417*/ GIMT_Encode4(276795), // Rule ID 59684 // |
| 108803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108804 | // (cttz:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 108805 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 108806 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108807 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108811 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108812 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108816 | GIR_RootConstrainSelectedInstOperands, |
| 108817 | // GIR_Coverage, 59684, |
| 108818 | GIR_EraseRootFromParent_Done, |
| 108819 | // Label 7417: @276795 |
| 108820 | GIM_Try, /*On fail goto*//*Label 7418*/ GIMT_Encode4(276838), // Rule ID 59685 // |
| 108821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108822 | // (cttz:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVCTZ_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 108823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 108824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108826 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M1), |
| 108828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108829 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108830 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108834 | GIR_RootConstrainSelectedInstOperands, |
| 108835 | // GIR_Coverage, 59685, |
| 108836 | GIR_EraseRootFromParent_Done, |
| 108837 | // Label 7418: @276838 |
| 108838 | GIM_Reject, |
| 108839 | // Label 7416: @276839 |
| 108840 | GIM_Reject, |
| 108841 | // Label 7362: @276840 |
| 108842 | GIM_Try, /*On fail goto*//*Label 7419*/ GIMT_Encode4(276943), |
| 108843 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 108844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108845 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108846 | GIM_Try, /*On fail goto*//*Label 7420*/ GIMT_Encode4(276899), // Rule ID 59698 // |
| 108847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108848 | // (cttz:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 108849 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 108850 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108851 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108855 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108856 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108860 | GIR_RootConstrainSelectedInstOperands, |
| 108861 | // GIR_Coverage, 59698, |
| 108862 | GIR_EraseRootFromParent_Done, |
| 108863 | // Label 7420: @276899 |
| 108864 | GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(276942), // Rule ID 59699 // |
| 108865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108866 | // (cttz:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 108867 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 108868 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108869 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108873 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108874 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 108877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108878 | GIR_RootConstrainSelectedInstOperands, |
| 108879 | // GIR_Coverage, 59699, |
| 108880 | GIR_EraseRootFromParent_Done, |
| 108881 | // Label 7421: @276942 |
| 108882 | GIM_Reject, |
| 108883 | // Label 7419: @276943 |
| 108884 | GIM_Reject, |
| 108885 | // Label 7363: @276944 |
| 108886 | GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(277047), |
| 108887 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 108888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 108889 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 108890 | GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(277003), // Rule ID 59706 // |
| 108891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108892 | // (cttz:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 108893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 108894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 108898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108900 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108904 | GIR_RootConstrainSelectedInstOperands, |
| 108905 | // GIR_Coverage, 59706, |
| 108906 | GIR_EraseRootFromParent_Done, |
| 108907 | // Label 7423: @277003 |
| 108908 | GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(277046), // Rule ID 59707 // |
| 108909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108910 | // (cttz:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 108911 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 108912 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108913 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108914 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 108916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108917 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108918 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 108921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108922 | GIR_RootConstrainSelectedInstOperands, |
| 108923 | // GIR_Coverage, 59707, |
| 108924 | GIR_EraseRootFromParent_Done, |
| 108925 | // Label 7424: @277046 |
| 108926 | GIM_Reject, |
| 108927 | // Label 7422: @277047 |
| 108928 | GIM_Reject, |
| 108929 | // Label 7364: @277048 |
| 108930 | GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(277151), |
| 108931 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 108932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 108933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 108934 | GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(277107), // Rule ID 59714 // |
| 108935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 108936 | // (cttz:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 108937 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 108938 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108939 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108940 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 108942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108943 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108944 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108948 | GIR_RootConstrainSelectedInstOperands, |
| 108949 | // GIR_Coverage, 59714, |
| 108950 | GIR_EraseRootFromParent_Done, |
| 108951 | // Label 7426: @277107 |
| 108952 | GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(277150), // Rule ID 59715 // |
| 108953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 108954 | // (cttz:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 108955 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 108956 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108957 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 108960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108961 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108962 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 108965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108966 | GIR_RootConstrainSelectedInstOperands, |
| 108967 | // GIR_Coverage, 59715, |
| 108968 | GIR_EraseRootFromParent_Done, |
| 108969 | // Label 7427: @277150 |
| 108970 | GIM_Reject, |
| 108971 | // Label 7425: @277151 |
| 108972 | GIM_Reject, |
| 108973 | // Label 7365: @277152 |
| 108974 | GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(277255), |
| 108975 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 108976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108977 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 108978 | GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(277211), // Rule ID 59692 // |
| 108979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 108980 | // (cttz:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 108981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 108982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 108983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 108984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 108985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 108986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 108987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 108988 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 108989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 108990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 108992 | GIR_RootConstrainSelectedInstOperands, |
| 108993 | // GIR_Coverage, 59692, |
| 108994 | GIR_EraseRootFromParent_Done, |
| 108995 | // Label 7429: @277211 |
| 108996 | GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(277254), // Rule ID 59693 // |
| 108997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 108998 | // (cttz:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVCTZ_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 108999 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 109000 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M2), |
| 109004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109006 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109010 | GIR_RootConstrainSelectedInstOperands, |
| 109011 | // GIR_Coverage, 59693, |
| 109012 | GIR_EraseRootFromParent_Done, |
| 109013 | // Label 7430: @277254 |
| 109014 | GIM_Reject, |
| 109015 | // Label 7428: @277255 |
| 109016 | GIM_Reject, |
| 109017 | // Label 7366: @277256 |
| 109018 | GIM_Try, /*On fail goto*//*Label 7431*/ GIMT_Encode4(277359), |
| 109019 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 109020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 109021 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 109022 | GIM_Try, /*On fail goto*//*Label 7432*/ GIMT_Encode4(277315), // Rule ID 59700 // |
| 109023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109024 | // (cttz:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 109025 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 109026 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109027 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 109030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109031 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109032 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109036 | GIR_RootConstrainSelectedInstOperands, |
| 109037 | // GIR_Coverage, 59700, |
| 109038 | GIR_EraseRootFromParent_Done, |
| 109039 | // Label 7432: @277315 |
| 109040 | GIM_Try, /*On fail goto*//*Label 7433*/ GIMT_Encode4(277358), // Rule ID 59701 // |
| 109041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109042 | // (cttz:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 109043 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 109044 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109045 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109046 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 109048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109049 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109050 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109054 | GIR_RootConstrainSelectedInstOperands, |
| 109055 | // GIR_Coverage, 59701, |
| 109056 | GIR_EraseRootFromParent_Done, |
| 109057 | // Label 7433: @277358 |
| 109058 | GIM_Reject, |
| 109059 | // Label 7431: @277359 |
| 109060 | GIM_Reject, |
| 109061 | // Label 7367: @277360 |
| 109062 | GIM_Try, /*On fail goto*//*Label 7434*/ GIMT_Encode4(277463), |
| 109063 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 109064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 109065 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 109066 | GIM_Try, /*On fail goto*//*Label 7435*/ GIMT_Encode4(277419), // Rule ID 59708 // |
| 109067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109068 | // (cttz:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 109069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 109070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 109074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109076 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109080 | GIR_RootConstrainSelectedInstOperands, |
| 109081 | // GIR_Coverage, 59708, |
| 109082 | GIR_EraseRootFromParent_Done, |
| 109083 | // Label 7435: @277419 |
| 109084 | GIM_Try, /*On fail goto*//*Label 7436*/ GIMT_Encode4(277462), // Rule ID 59709 // |
| 109085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109086 | // (cttz:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 109087 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 109088 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109089 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109090 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 109092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109094 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109098 | GIR_RootConstrainSelectedInstOperands, |
| 109099 | // GIR_Coverage, 59709, |
| 109100 | GIR_EraseRootFromParent_Done, |
| 109101 | // Label 7436: @277462 |
| 109102 | GIM_Reject, |
| 109103 | // Label 7434: @277463 |
| 109104 | GIM_Reject, |
| 109105 | // Label 7368: @277464 |
| 109106 | GIM_Try, /*On fail goto*//*Label 7437*/ GIMT_Encode4(277567), |
| 109107 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 109108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 109109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 109110 | GIM_Try, /*On fail goto*//*Label 7438*/ GIMT_Encode4(277523), // Rule ID 59694 // |
| 109111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109112 | // (cttz:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 109113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 109114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 109118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109119 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109120 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109124 | GIR_RootConstrainSelectedInstOperands, |
| 109125 | // GIR_Coverage, 59694, |
| 109126 | GIR_EraseRootFromParent_Done, |
| 109127 | // Label 7438: @277523 |
| 109128 | GIM_Try, /*On fail goto*//*Label 7439*/ GIMT_Encode4(277566), // Rule ID 59695 // |
| 109129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109130 | // (cttz:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVCTZ_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 109131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 109132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M4), |
| 109136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109138 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109142 | GIR_RootConstrainSelectedInstOperands, |
| 109143 | // GIR_Coverage, 59695, |
| 109144 | GIR_EraseRootFromParent_Done, |
| 109145 | // Label 7439: @277566 |
| 109146 | GIM_Reject, |
| 109147 | // Label 7437: @277567 |
| 109148 | GIM_Reject, |
| 109149 | // Label 7369: @277568 |
| 109150 | GIM_Try, /*On fail goto*//*Label 7440*/ GIMT_Encode4(277671), |
| 109151 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 109152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 109153 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 109154 | GIM_Try, /*On fail goto*//*Label 7441*/ GIMT_Encode4(277627), // Rule ID 59702 // |
| 109155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109156 | // (cttz:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 109157 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 109158 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109159 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 109162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109163 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109164 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109168 | GIR_RootConstrainSelectedInstOperands, |
| 109169 | // GIR_Coverage, 59702, |
| 109170 | GIR_EraseRootFromParent_Done, |
| 109171 | // Label 7441: @277627 |
| 109172 | GIM_Try, /*On fail goto*//*Label 7442*/ GIMT_Encode4(277670), // Rule ID 59703 // |
| 109173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109174 | // (cttz:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 109175 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 109176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 109180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109181 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109182 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109186 | GIR_RootConstrainSelectedInstOperands, |
| 109187 | // GIR_Coverage, 59703, |
| 109188 | GIR_EraseRootFromParent_Done, |
| 109189 | // Label 7442: @277670 |
| 109190 | GIM_Reject, |
| 109191 | // Label 7440: @277671 |
| 109192 | GIM_Reject, |
| 109193 | // Label 7370: @277672 |
| 109194 | GIM_Try, /*On fail goto*//*Label 7443*/ GIMT_Encode4(277775), |
| 109195 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 109196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 109197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 109198 | GIM_Try, /*On fail goto*//*Label 7444*/ GIMT_Encode4(277731), // Rule ID 59696 // |
| 109199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109200 | // (cttz:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 109201 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 109202 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109203 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109204 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 109206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109208 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109212 | GIR_RootConstrainSelectedInstOperands, |
| 109213 | // GIR_Coverage, 59696, |
| 109214 | GIR_EraseRootFromParent_Done, |
| 109215 | // Label 7444: @277731 |
| 109216 | GIM_Try, /*On fail goto*//*Label 7445*/ GIMT_Encode4(277774), // Rule ID 59697 // |
| 109217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109218 | // (cttz:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVCTZ_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 109219 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 109220 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109221 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109222 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCTZ_V_M8), |
| 109224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109225 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109226 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109230 | GIR_RootConstrainSelectedInstOperands, |
| 109231 | // GIR_Coverage, 59697, |
| 109232 | GIR_EraseRootFromParent_Done, |
| 109233 | // Label 7445: @277774 |
| 109234 | GIM_Reject, |
| 109235 | // Label 7443: @277775 |
| 109236 | GIM_Reject, |
| 109237 | // Label 7371: @277776 |
| 109238 | GIM_Reject, |
| 109239 | // Label 80: @277777 |
| 109240 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7470*/ GIMT_Encode4(280472), |
| 109241 | /*GILLT_s32*//*Label 7446*/ GIMT_Encode4(277912), |
| 109242 | /*GILLT_s64*//*Label 7447*/ GIMT_Encode4(278067), GIMT_Encode4(0), |
| 109243 | /*GILLT_nxv1s8*//*Label 7448*/ GIMT_Encode4(278184), |
| 109244 | /*GILLT_nxv1s16*//*Label 7449*/ GIMT_Encode4(278288), |
| 109245 | /*GILLT_nxv1s32*//*Label 7450*/ GIMT_Encode4(278392), |
| 109246 | /*GILLT_nxv1s64*//*Label 7451*/ GIMT_Encode4(278496), GIMT_Encode4(0), |
| 109247 | /*GILLT_nxv2s8*//*Label 7452*/ GIMT_Encode4(278600), |
| 109248 | /*GILLT_nxv2s16*//*Label 7453*/ GIMT_Encode4(278704), |
| 109249 | /*GILLT_nxv2s32*//*Label 7454*/ GIMT_Encode4(278808), |
| 109250 | /*GILLT_nxv2s64*//*Label 7455*/ GIMT_Encode4(278912), GIMT_Encode4(0), |
| 109251 | /*GILLT_nxv4s8*//*Label 7456*/ GIMT_Encode4(279016), |
| 109252 | /*GILLT_nxv4s16*//*Label 7457*/ GIMT_Encode4(279120), |
| 109253 | /*GILLT_nxv4s32*//*Label 7458*/ GIMT_Encode4(279224), |
| 109254 | /*GILLT_nxv4s64*//*Label 7459*/ GIMT_Encode4(279328), GIMT_Encode4(0), |
| 109255 | /*GILLT_nxv8s8*//*Label 7460*/ GIMT_Encode4(279432), |
| 109256 | /*GILLT_nxv8s16*//*Label 7461*/ GIMT_Encode4(279536), |
| 109257 | /*GILLT_nxv8s32*//*Label 7462*/ GIMT_Encode4(279640), |
| 109258 | /*GILLT_nxv8s64*//*Label 7463*/ GIMT_Encode4(279744), GIMT_Encode4(0), |
| 109259 | /*GILLT_nxv16s8*//*Label 7464*/ GIMT_Encode4(279848), |
| 109260 | /*GILLT_nxv16s16*//*Label 7465*/ GIMT_Encode4(279952), |
| 109261 | /*GILLT_nxv16s32*//*Label 7466*/ GIMT_Encode4(280056), GIMT_Encode4(0), |
| 109262 | /*GILLT_nxv32s8*//*Label 7467*/ GIMT_Encode4(280160), |
| 109263 | /*GILLT_nxv32s16*//*Label 7468*/ GIMT_Encode4(280264), GIMT_Encode4(0), |
| 109264 | /*GILLT_nxv64s8*//*Label 7469*/ GIMT_Encode4(280368), |
| 109265 | // Label 7446: @277912 |
| 109266 | GIM_Try, /*On fail goto*//*Label 7471*/ GIMT_Encode4(278066), |
| 109267 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 109268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109269 | GIM_Try, /*On fail goto*//*Label 7472*/ GIMT_Encode4(277970), // Rule ID 63028 // |
| 109270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode1), |
| 109271 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109272 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 109273 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109274 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109275 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109276 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 109277 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 109278 | // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] })) => (TH_FF0:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 109279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_FF0), |
| 109280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 109282 | GIR_RootConstrainSelectedInstOperands, |
| 109283 | // GIR_Coverage, 63028, |
| 109284 | GIR_EraseRootFromParent_Done, |
| 109285 | // Label 7472: @277970 |
| 109286 | GIM_Try, /*On fail goto*//*Label 7473*/ GIMT_Encode4(277989), // Rule ID 2665 // |
| 109287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 109288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109289 | // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 109290 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CLZ), |
| 109291 | GIR_RootConstrainSelectedInstOperands, |
| 109292 | // GIR_Coverage, 2665, |
| 109293 | GIR_Done, |
| 109294 | // Label 7473: @277989 |
| 109295 | GIM_Try, /*On fail goto*//*Label 7474*/ GIMT_Encode4(278008), // Rule ID 2793 // |
| 109296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), |
| 109297 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109298 | // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CLZW:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 109299 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CLZW), |
| 109300 | GIR_RootConstrainSelectedInstOperands, |
| 109301 | // GIR_Coverage, 2793, |
| 109302 | GIR_Done, |
| 109303 | // Label 7474: @278008 |
| 109304 | GIM_Try, /*On fail goto*//*Label 7475*/ GIMT_Encode4(278027), // Rule ID 2794 // |
| 109305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode1), |
| 109306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109307 | // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CLZW:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 109308 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CLZW), |
| 109309 | GIR_RootConstrainSelectedInstOperands, |
| 109310 | // GIR_Coverage, 2794, |
| 109311 | GIR_Done, |
| 109312 | // Label 7475: @278027 |
| 109313 | GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(278046), // Rule ID 63026 // |
| 109314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode1), |
| 109315 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109316 | // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (TH_FF1:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 109317 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::TH_FF1), |
| 109318 | GIR_RootConstrainSelectedInstOperands, |
| 109319 | // GIR_Coverage, 63026, |
| 109320 | GIR_Done, |
| 109321 | // Label 7476: @278046 |
| 109322 | GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(278065), // Rule ID 64959 // |
| 109323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 109324 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109325 | // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CV_FL1:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 109326 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_FL1), |
| 109327 | GIR_RootConstrainSelectedInstOperands, |
| 109328 | // GIR_Coverage, 64959, |
| 109329 | GIR_Done, |
| 109330 | // Label 7477: @278065 |
| 109331 | GIM_Reject, |
| 109332 | // Label 7471: @278066 |
| 109333 | GIM_Reject, |
| 109334 | // Label 7447: @278067 |
| 109335 | GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(278183), |
| 109336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 109337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109338 | GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(278125), // Rule ID 63027 // |
| 109339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode0), |
| 109340 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109341 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 109342 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 109343 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 109344 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109345 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 109346 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 109347 | // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] })) => (TH_FF0:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 109348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_FF0), |
| 109349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109350 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 109351 | GIR_RootConstrainSelectedInstOperands, |
| 109352 | // GIR_Coverage, 63027, |
| 109353 | GIR_EraseRootFromParent_Done, |
| 109354 | // Label 7479: @278125 |
| 109355 | GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(278144), // Rule ID 2664 // |
| 109356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 109357 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109358 | // (ctlz:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CLZ:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 109359 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CLZ), |
| 109360 | GIR_RootConstrainSelectedInstOperands, |
| 109361 | // GIR_Coverage, 2664, |
| 109362 | GIR_Done, |
| 109363 | // Label 7480: @278144 |
| 109364 | GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(278163), // Rule ID 63025 // |
| 109365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode0), |
| 109366 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109367 | // (ctlz:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (TH_FF1:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 109368 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::TH_FF1), |
| 109369 | GIR_RootConstrainSelectedInstOperands, |
| 109370 | // GIR_Coverage, 63025, |
| 109371 | GIR_Done, |
| 109372 | // Label 7481: @278163 |
| 109373 | GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(278182), // Rule ID 64958 // |
| 109374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0), |
| 109375 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 109376 | // (ctlz:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CV_FL1:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 109377 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_FL1), |
| 109378 | GIR_RootConstrainSelectedInstOperands, |
| 109379 | // GIR_Coverage, 64958, |
| 109380 | GIR_Done, |
| 109381 | // Label 7482: @278182 |
| 109382 | GIM_Reject, |
| 109383 | // Label 7478: @278183 |
| 109384 | GIM_Reject, |
| 109385 | // Label 7448: @278184 |
| 109386 | GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(278287), |
| 109387 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 109388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109389 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109390 | GIM_Try, /*On fail goto*//*Label 7484*/ GIMT_Encode4(278243), // Rule ID 59628 // |
| 109391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109392 | // (ctlz:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVCLZ_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 109393 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 109394 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109395 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF8), |
| 109398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109399 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109400 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109404 | GIR_RootConstrainSelectedInstOperands, |
| 109405 | // GIR_Coverage, 59628, |
| 109406 | GIR_EraseRootFromParent_Done, |
| 109407 | // Label 7484: @278243 |
| 109408 | GIM_Try, /*On fail goto*//*Label 7485*/ GIMT_Encode4(278286), // Rule ID 59629 // |
| 109409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109410 | // (ctlz:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVCLZ_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 109411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 109412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109413 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF8), |
| 109416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109417 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109418 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109422 | GIR_RootConstrainSelectedInstOperands, |
| 109423 | // GIR_Coverage, 59629, |
| 109424 | GIR_EraseRootFromParent_Done, |
| 109425 | // Label 7485: @278286 |
| 109426 | GIM_Reject, |
| 109427 | // Label 7483: @278287 |
| 109428 | GIM_Reject, |
| 109429 | // Label 7449: @278288 |
| 109430 | GIM_Try, /*On fail goto*//*Label 7486*/ GIMT_Encode4(278391), |
| 109431 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 109432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109433 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109434 | GIM_Try, /*On fail goto*//*Label 7487*/ GIMT_Encode4(278347), // Rule ID 59634 // |
| 109435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109436 | // (ctlz:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVCLZ_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 109437 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 109438 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109439 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109440 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF4), |
| 109442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109443 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109444 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109448 | GIR_RootConstrainSelectedInstOperands, |
| 109449 | // GIR_Coverage, 59634, |
| 109450 | GIR_EraseRootFromParent_Done, |
| 109451 | // Label 7487: @278347 |
| 109452 | GIM_Try, /*On fail goto*//*Label 7488*/ GIMT_Encode4(278390), // Rule ID 59635 // |
| 109453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109454 | // (ctlz:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVCLZ_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 109455 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 109456 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109457 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF4), |
| 109460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109462 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109466 | GIR_RootConstrainSelectedInstOperands, |
| 109467 | // GIR_Coverage, 59635, |
| 109468 | GIR_EraseRootFromParent_Done, |
| 109469 | // Label 7488: @278390 |
| 109470 | GIM_Reject, |
| 109471 | // Label 7486: @278391 |
| 109472 | GIM_Reject, |
| 109473 | // Label 7450: @278392 |
| 109474 | GIM_Try, /*On fail goto*//*Label 7489*/ GIMT_Encode4(278495), |
| 109475 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 109476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109477 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109478 | GIM_Try, /*On fail goto*//*Label 7490*/ GIMT_Encode4(278451), // Rule ID 59638 // |
| 109479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109480 | // (ctlz:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVCLZ_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 109481 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 109482 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109483 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF2), |
| 109486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109487 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109488 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109492 | GIR_RootConstrainSelectedInstOperands, |
| 109493 | // GIR_Coverage, 59638, |
| 109494 | GIR_EraseRootFromParent_Done, |
| 109495 | // Label 7490: @278451 |
| 109496 | GIM_Try, /*On fail goto*//*Label 7491*/ GIMT_Encode4(278494), // Rule ID 59639 // |
| 109497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109498 | // (ctlz:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVCLZ_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 109499 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 109500 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109501 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF2), |
| 109504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109505 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109506 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109510 | GIR_RootConstrainSelectedInstOperands, |
| 109511 | // GIR_Coverage, 59639, |
| 109512 | GIR_EraseRootFromParent_Done, |
| 109513 | // Label 7491: @278494 |
| 109514 | GIM_Reject, |
| 109515 | // Label 7489: @278495 |
| 109516 | GIM_Reject, |
| 109517 | // Label 7451: @278496 |
| 109518 | GIM_Try, /*On fail goto*//*Label 7492*/ GIMT_Encode4(278599), |
| 109519 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 109520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109521 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109522 | GIM_Try, /*On fail goto*//*Label 7493*/ GIMT_Encode4(278555), // Rule ID 59646 // |
| 109523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 109524 | // (ctlz:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 109525 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 109526 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109527 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109531 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109532 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 109535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109536 | GIR_RootConstrainSelectedInstOperands, |
| 109537 | // GIR_Coverage, 59646, |
| 109538 | GIR_EraseRootFromParent_Done, |
| 109539 | // Label 7493: @278555 |
| 109540 | GIM_Try, /*On fail goto*//*Label 7494*/ GIMT_Encode4(278598), // Rule ID 59647 // |
| 109541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 109542 | // (ctlz:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 109543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 109544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109550 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 109553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109554 | GIR_RootConstrainSelectedInstOperands, |
| 109555 | // GIR_Coverage, 59647, |
| 109556 | GIR_EraseRootFromParent_Done, |
| 109557 | // Label 7494: @278598 |
| 109558 | GIM_Reject, |
| 109559 | // Label 7492: @278599 |
| 109560 | GIM_Reject, |
| 109561 | // Label 7452: @278600 |
| 109562 | GIM_Try, /*On fail goto*//*Label 7495*/ GIMT_Encode4(278703), |
| 109563 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 109564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109566 | GIM_Try, /*On fail goto*//*Label 7496*/ GIMT_Encode4(278659), // Rule ID 59630 // |
| 109567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109568 | // (ctlz:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVCLZ_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 109569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 109570 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109571 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF4), |
| 109574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109575 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109576 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109580 | GIR_RootConstrainSelectedInstOperands, |
| 109581 | // GIR_Coverage, 59630, |
| 109582 | GIR_EraseRootFromParent_Done, |
| 109583 | // Label 7496: @278659 |
| 109584 | GIM_Try, /*On fail goto*//*Label 7497*/ GIMT_Encode4(278702), // Rule ID 59631 // |
| 109585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109586 | // (ctlz:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVCLZ_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 109587 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 109588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109589 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF4), |
| 109592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109593 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109594 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109598 | GIR_RootConstrainSelectedInstOperands, |
| 109599 | // GIR_Coverage, 59631, |
| 109600 | GIR_EraseRootFromParent_Done, |
| 109601 | // Label 7497: @278702 |
| 109602 | GIM_Reject, |
| 109603 | // Label 7495: @278703 |
| 109604 | GIM_Reject, |
| 109605 | // Label 7453: @278704 |
| 109606 | GIM_Try, /*On fail goto*//*Label 7498*/ GIMT_Encode4(278807), |
| 109607 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 109608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109609 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109610 | GIM_Try, /*On fail goto*//*Label 7499*/ GIMT_Encode4(278763), // Rule ID 59636 // |
| 109611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109612 | // (ctlz:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVCLZ_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 109613 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 109614 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109615 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF2), |
| 109618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109619 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109620 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109624 | GIR_RootConstrainSelectedInstOperands, |
| 109625 | // GIR_Coverage, 59636, |
| 109626 | GIR_EraseRootFromParent_Done, |
| 109627 | // Label 7499: @278763 |
| 109628 | GIM_Try, /*On fail goto*//*Label 7500*/ GIMT_Encode4(278806), // Rule ID 59637 // |
| 109629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109630 | // (ctlz:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVCLZ_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 109631 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 109632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109633 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF2), |
| 109636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109638 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109642 | GIR_RootConstrainSelectedInstOperands, |
| 109643 | // GIR_Coverage, 59637, |
| 109644 | GIR_EraseRootFromParent_Done, |
| 109645 | // Label 7500: @278806 |
| 109646 | GIM_Reject, |
| 109647 | // Label 7498: @278807 |
| 109648 | GIM_Reject, |
| 109649 | // Label 7454: @278808 |
| 109650 | GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(278911), |
| 109651 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 109652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109653 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109654 | GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(278867), // Rule ID 59644 // |
| 109655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109656 | // (ctlz:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 109657 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 109658 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109659 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109664 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109668 | GIR_RootConstrainSelectedInstOperands, |
| 109669 | // GIR_Coverage, 59644, |
| 109670 | GIR_EraseRootFromParent_Done, |
| 109671 | // Label 7502: @278867 |
| 109672 | GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(278910), // Rule ID 59645 // |
| 109673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109674 | // (ctlz:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 109675 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 109676 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109677 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109678 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109681 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109686 | GIR_RootConstrainSelectedInstOperands, |
| 109687 | // GIR_Coverage, 59645, |
| 109688 | GIR_EraseRootFromParent_Done, |
| 109689 | // Label 7503: @278910 |
| 109690 | GIM_Reject, |
| 109691 | // Label 7501: @278911 |
| 109692 | GIM_Reject, |
| 109693 | // Label 7455: @278912 |
| 109694 | GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(279015), |
| 109695 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 109696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 109697 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 109698 | GIM_Try, /*On fail goto*//*Label 7505*/ GIMT_Encode4(278971), // Rule ID 59666 // |
| 109699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 109700 | // (ctlz:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 109701 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 109702 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109703 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109704 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 109706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109707 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109708 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 109711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109712 | GIR_RootConstrainSelectedInstOperands, |
| 109713 | // GIR_Coverage, 59666, |
| 109714 | GIR_EraseRootFromParent_Done, |
| 109715 | // Label 7505: @278971 |
| 109716 | GIM_Try, /*On fail goto*//*Label 7506*/ GIMT_Encode4(279014), // Rule ID 59667 // |
| 109717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 109718 | // (ctlz:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 109719 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 109720 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109721 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109722 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 109724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109725 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109726 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 109729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109730 | GIR_RootConstrainSelectedInstOperands, |
| 109731 | // GIR_Coverage, 59667, |
| 109732 | GIR_EraseRootFromParent_Done, |
| 109733 | // Label 7506: @279014 |
| 109734 | GIM_Reject, |
| 109735 | // Label 7504: @279015 |
| 109736 | GIM_Reject, |
| 109737 | // Label 7456: @279016 |
| 109738 | GIM_Try, /*On fail goto*//*Label 7507*/ GIMT_Encode4(279119), |
| 109739 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 109740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109741 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109742 | GIM_Try, /*On fail goto*//*Label 7508*/ GIMT_Encode4(279075), // Rule ID 59632 // |
| 109743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109744 | // (ctlz:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVCLZ_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 109745 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 109746 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109747 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109748 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF2), |
| 109750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109751 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109752 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109756 | GIR_RootConstrainSelectedInstOperands, |
| 109757 | // GIR_Coverage, 59632, |
| 109758 | GIR_EraseRootFromParent_Done, |
| 109759 | // Label 7508: @279075 |
| 109760 | GIM_Try, /*On fail goto*//*Label 7509*/ GIMT_Encode4(279118), // Rule ID 59633 // |
| 109761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109762 | // (ctlz:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVCLZ_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 109763 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 109764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109765 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_MF2), |
| 109768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109769 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109770 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109774 | GIR_RootConstrainSelectedInstOperands, |
| 109775 | // GIR_Coverage, 59633, |
| 109776 | GIR_EraseRootFromParent_Done, |
| 109777 | // Label 7509: @279118 |
| 109778 | GIM_Reject, |
| 109779 | // Label 7507: @279119 |
| 109780 | GIM_Reject, |
| 109781 | // Label 7457: @279120 |
| 109782 | GIM_Try, /*On fail goto*//*Label 7510*/ GIMT_Encode4(279223), |
| 109783 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 109784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109785 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109786 | GIM_Try, /*On fail goto*//*Label 7511*/ GIMT_Encode4(279179), // Rule ID 59642 // |
| 109787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109788 | // (ctlz:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 109789 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 109790 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109791 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109792 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109795 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109796 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109800 | GIR_RootConstrainSelectedInstOperands, |
| 109801 | // GIR_Coverage, 59642, |
| 109802 | GIR_EraseRootFromParent_Done, |
| 109803 | // Label 7511: @279179 |
| 109804 | GIM_Try, /*On fail goto*//*Label 7512*/ GIMT_Encode4(279222), // Rule ID 59643 // |
| 109805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109806 | // (ctlz:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 109807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 109808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109814 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109818 | GIR_RootConstrainSelectedInstOperands, |
| 109819 | // GIR_Coverage, 59643, |
| 109820 | GIR_EraseRootFromParent_Done, |
| 109821 | // Label 7512: @279222 |
| 109822 | GIM_Reject, |
| 109823 | // Label 7510: @279223 |
| 109824 | GIM_Reject, |
| 109825 | // Label 7458: @279224 |
| 109826 | GIM_Try, /*On fail goto*//*Label 7513*/ GIMT_Encode4(279327), |
| 109827 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 109828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 109829 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 109830 | GIM_Try, /*On fail goto*//*Label 7514*/ GIMT_Encode4(279283), // Rule ID 59660 // |
| 109831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109832 | // (ctlz:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 109833 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 109834 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109835 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 109838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109839 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109840 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109844 | GIR_RootConstrainSelectedInstOperands, |
| 109845 | // GIR_Coverage, 59660, |
| 109846 | GIR_EraseRootFromParent_Done, |
| 109847 | // Label 7514: @279283 |
| 109848 | GIM_Try, /*On fail goto*//*Label 7515*/ GIMT_Encode4(279326), // Rule ID 59661 // |
| 109849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109850 | // (ctlz:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 109851 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 109852 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109853 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109854 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 109856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109857 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109858 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 109861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109862 | GIR_RootConstrainSelectedInstOperands, |
| 109863 | // GIR_Coverage, 59661, |
| 109864 | GIR_EraseRootFromParent_Done, |
| 109865 | // Label 7515: @279326 |
| 109866 | GIM_Reject, |
| 109867 | // Label 7513: @279327 |
| 109868 | GIM_Reject, |
| 109869 | // Label 7459: @279328 |
| 109870 | GIM_Try, /*On fail goto*//*Label 7516*/ GIMT_Encode4(279431), |
| 109871 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 109872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 109873 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 109874 | GIM_Try, /*On fail goto*//*Label 7517*/ GIMT_Encode4(279387), // Rule ID 59668 // |
| 109875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 109876 | // (ctlz:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 109877 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 109878 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109879 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109880 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 109882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109883 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109884 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 109887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109888 | GIR_RootConstrainSelectedInstOperands, |
| 109889 | // GIR_Coverage, 59668, |
| 109890 | GIR_EraseRootFromParent_Done, |
| 109891 | // Label 7517: @279387 |
| 109892 | GIM_Try, /*On fail goto*//*Label 7518*/ GIMT_Encode4(279430), // Rule ID 59669 // |
| 109893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 109894 | // (ctlz:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 109895 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 109896 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109897 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 109900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109901 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109902 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 109905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109906 | GIR_RootConstrainSelectedInstOperands, |
| 109907 | // GIR_Coverage, 59669, |
| 109908 | GIR_EraseRootFromParent_Done, |
| 109909 | // Label 7518: @279430 |
| 109910 | GIM_Reject, |
| 109911 | // Label 7516: @279431 |
| 109912 | GIM_Reject, |
| 109913 | // Label 7460: @279432 |
| 109914 | GIM_Try, /*On fail goto*//*Label 7519*/ GIMT_Encode4(279535), |
| 109915 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 109916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109917 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 109918 | GIM_Try, /*On fail goto*//*Label 7520*/ GIMT_Encode4(279491), // Rule ID 59640 // |
| 109919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109920 | // (ctlz:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 109921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 109922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109923 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109924 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109927 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109928 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109932 | GIR_RootConstrainSelectedInstOperands, |
| 109933 | // GIR_Coverage, 59640, |
| 109934 | GIR_EraseRootFromParent_Done, |
| 109935 | // Label 7520: @279491 |
| 109936 | GIM_Try, /*On fail goto*//*Label 7521*/ GIMT_Encode4(279534), // Rule ID 59641 // |
| 109937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109938 | // (ctlz:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVCLZ_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 109939 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 109940 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109941 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109942 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M1), |
| 109944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109945 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109946 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109950 | GIR_RootConstrainSelectedInstOperands, |
| 109951 | // GIR_Coverage, 59641, |
| 109952 | GIR_EraseRootFromParent_Done, |
| 109953 | // Label 7521: @279534 |
| 109954 | GIM_Reject, |
| 109955 | // Label 7519: @279535 |
| 109956 | GIM_Reject, |
| 109957 | // Label 7461: @279536 |
| 109958 | GIM_Try, /*On fail goto*//*Label 7522*/ GIMT_Encode4(279639), |
| 109959 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 109960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 109961 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 109962 | GIM_Try, /*On fail goto*//*Label 7523*/ GIMT_Encode4(279595), // Rule ID 59654 // |
| 109963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 109964 | // (ctlz:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 109965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 109966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 109970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109971 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109972 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109976 | GIR_RootConstrainSelectedInstOperands, |
| 109977 | // GIR_Coverage, 59654, |
| 109978 | GIR_EraseRootFromParent_Done, |
| 109979 | // Label 7523: @279595 |
| 109980 | GIM_Try, /*On fail goto*//*Label 7524*/ GIMT_Encode4(279638), // Rule ID 59655 // |
| 109981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 109982 | // (ctlz:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 109983 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 109984 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 109985 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 109986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 109987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 109988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 109989 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 109990 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 109991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 109992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 109993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 109994 | GIR_RootConstrainSelectedInstOperands, |
| 109995 | // GIR_Coverage, 59655, |
| 109996 | GIR_EraseRootFromParent_Done, |
| 109997 | // Label 7524: @279638 |
| 109998 | GIM_Reject, |
| 109999 | // Label 7522: @279639 |
| 110000 | GIM_Reject, |
| 110001 | // Label 7462: @279640 |
| 110002 | GIM_Try, /*On fail goto*//*Label 7525*/ GIMT_Encode4(279743), |
| 110003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 110004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110005 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110006 | GIM_Try, /*On fail goto*//*Label 7526*/ GIMT_Encode4(279699), // Rule ID 59662 // |
| 110007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110008 | // (ctlz:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 110009 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 110010 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110011 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110012 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 110014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110015 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110016 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110020 | GIR_RootConstrainSelectedInstOperands, |
| 110021 | // GIR_Coverage, 59662, |
| 110022 | GIR_EraseRootFromParent_Done, |
| 110023 | // Label 7526: @279699 |
| 110024 | GIM_Try, /*On fail goto*//*Label 7527*/ GIMT_Encode4(279742), // Rule ID 59663 // |
| 110025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110026 | // (ctlz:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 110027 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 110028 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110029 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 110032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110033 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110034 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110038 | GIR_RootConstrainSelectedInstOperands, |
| 110039 | // GIR_Coverage, 59663, |
| 110040 | GIR_EraseRootFromParent_Done, |
| 110041 | // Label 7527: @279742 |
| 110042 | GIM_Reject, |
| 110043 | // Label 7525: @279743 |
| 110044 | GIM_Reject, |
| 110045 | // Label 7463: @279744 |
| 110046 | GIM_Try, /*On fail goto*//*Label 7528*/ GIMT_Encode4(279847), |
| 110047 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 110048 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110049 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110050 | GIM_Try, /*On fail goto*//*Label 7529*/ GIMT_Encode4(279803), // Rule ID 59670 // |
| 110051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 110052 | // (ctlz:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 110053 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 110054 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110055 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110059 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110060 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110064 | GIR_RootConstrainSelectedInstOperands, |
| 110065 | // GIR_Coverage, 59670, |
| 110066 | GIR_EraseRootFromParent_Done, |
| 110067 | // Label 7529: @279803 |
| 110068 | GIM_Try, /*On fail goto*//*Label 7530*/ GIMT_Encode4(279846), // Rule ID 59671 // |
| 110069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 110070 | // (ctlz:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 110071 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 110072 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110073 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110077 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110078 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110082 | GIR_RootConstrainSelectedInstOperands, |
| 110083 | // GIR_Coverage, 59671, |
| 110084 | GIR_EraseRootFromParent_Done, |
| 110085 | // Label 7530: @279846 |
| 110086 | GIM_Reject, |
| 110087 | // Label 7528: @279847 |
| 110088 | GIM_Reject, |
| 110089 | // Label 7464: @279848 |
| 110090 | GIM_Try, /*On fail goto*//*Label 7531*/ GIMT_Encode4(279951), |
| 110091 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 110092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 110093 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 110094 | GIM_Try, /*On fail goto*//*Label 7532*/ GIMT_Encode4(279907), // Rule ID 59648 // |
| 110095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110096 | // (ctlz:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110097 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 110098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110099 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 110102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110104 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110108 | GIR_RootConstrainSelectedInstOperands, |
| 110109 | // GIR_Coverage, 59648, |
| 110110 | GIR_EraseRootFromParent_Done, |
| 110111 | // Label 7532: @279907 |
| 110112 | GIM_Try, /*On fail goto*//*Label 7533*/ GIMT_Encode4(279950), // Rule ID 59649 // |
| 110113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110114 | // (ctlz:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVCLZ_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110115 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 110116 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110117 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M2), |
| 110120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110121 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110122 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110126 | GIR_RootConstrainSelectedInstOperands, |
| 110127 | // GIR_Coverage, 59649, |
| 110128 | GIR_EraseRootFromParent_Done, |
| 110129 | // Label 7533: @279950 |
| 110130 | GIM_Reject, |
| 110131 | // Label 7531: @279951 |
| 110132 | GIM_Reject, |
| 110133 | // Label 7465: @279952 |
| 110134 | GIM_Try, /*On fail goto*//*Label 7534*/ GIMT_Encode4(280055), |
| 110135 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 110136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110138 | GIM_Try, /*On fail goto*//*Label 7535*/ GIMT_Encode4(280011), // Rule ID 59656 // |
| 110139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110140 | // (ctlz:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 110141 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 110142 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110143 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110144 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 110146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110147 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110148 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110152 | GIR_RootConstrainSelectedInstOperands, |
| 110153 | // GIR_Coverage, 59656, |
| 110154 | GIR_EraseRootFromParent_Done, |
| 110155 | // Label 7535: @280011 |
| 110156 | GIM_Try, /*On fail goto*//*Label 7536*/ GIMT_Encode4(280054), // Rule ID 59657 // |
| 110157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110158 | // (ctlz:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 110159 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 110160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 110164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110166 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110170 | GIR_RootConstrainSelectedInstOperands, |
| 110171 | // GIR_Coverage, 59657, |
| 110172 | GIR_EraseRootFromParent_Done, |
| 110173 | // Label 7536: @280054 |
| 110174 | GIM_Reject, |
| 110175 | // Label 7534: @280055 |
| 110176 | GIM_Reject, |
| 110177 | // Label 7466: @280056 |
| 110178 | GIM_Try, /*On fail goto*//*Label 7537*/ GIMT_Encode4(280159), |
| 110179 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 110180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110181 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110182 | GIM_Try, /*On fail goto*//*Label 7538*/ GIMT_Encode4(280115), // Rule ID 59664 // |
| 110183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110184 | // (ctlz:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 110185 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 110186 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110187 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110191 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110192 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110196 | GIR_RootConstrainSelectedInstOperands, |
| 110197 | // GIR_Coverage, 59664, |
| 110198 | GIR_EraseRootFromParent_Done, |
| 110199 | // Label 7538: @280115 |
| 110200 | GIM_Try, /*On fail goto*//*Label 7539*/ GIMT_Encode4(280158), // Rule ID 59665 // |
| 110201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110202 | // (ctlz:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 110203 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 110204 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110205 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110209 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110210 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110214 | GIR_RootConstrainSelectedInstOperands, |
| 110215 | // GIR_Coverage, 59665, |
| 110216 | GIR_EraseRootFromParent_Done, |
| 110217 | // Label 7539: @280158 |
| 110218 | GIM_Reject, |
| 110219 | // Label 7537: @280159 |
| 110220 | GIM_Reject, |
| 110221 | // Label 7467: @280160 |
| 110222 | GIM_Try, /*On fail goto*//*Label 7540*/ GIMT_Encode4(280263), |
| 110223 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 110224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110226 | GIM_Try, /*On fail goto*//*Label 7541*/ GIMT_Encode4(280219), // Rule ID 59650 // |
| 110227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110228 | // (ctlz:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110229 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 110230 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110231 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110232 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 110234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110235 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110236 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110240 | GIR_RootConstrainSelectedInstOperands, |
| 110241 | // GIR_Coverage, 59650, |
| 110242 | GIR_EraseRootFromParent_Done, |
| 110243 | // Label 7541: @280219 |
| 110244 | GIM_Try, /*On fail goto*//*Label 7542*/ GIMT_Encode4(280262), // Rule ID 59651 // |
| 110245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110246 | // (ctlz:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVCLZ_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110247 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 110248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110249 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110250 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M4), |
| 110252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110253 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110254 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110258 | GIR_RootConstrainSelectedInstOperands, |
| 110259 | // GIR_Coverage, 59651, |
| 110260 | GIR_EraseRootFromParent_Done, |
| 110261 | // Label 7542: @280262 |
| 110262 | GIM_Reject, |
| 110263 | // Label 7540: @280263 |
| 110264 | GIM_Reject, |
| 110265 | // Label 7468: @280264 |
| 110266 | GIM_Try, /*On fail goto*//*Label 7543*/ GIMT_Encode4(280367), |
| 110267 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 110268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110269 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110270 | GIM_Try, /*On fail goto*//*Label 7544*/ GIMT_Encode4(280323), // Rule ID 59658 // |
| 110271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110272 | // (ctlz:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 110273 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 110274 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110275 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110279 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110280 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110284 | GIR_RootConstrainSelectedInstOperands, |
| 110285 | // GIR_Coverage, 59658, |
| 110286 | GIR_EraseRootFromParent_Done, |
| 110287 | // Label 7544: @280323 |
| 110288 | GIM_Try, /*On fail goto*//*Label 7545*/ GIMT_Encode4(280366), // Rule ID 59659 // |
| 110289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110290 | // (ctlz:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 110291 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 110292 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110293 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110294 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110298 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110302 | GIR_RootConstrainSelectedInstOperands, |
| 110303 | // GIR_Coverage, 59659, |
| 110304 | GIR_EraseRootFromParent_Done, |
| 110305 | // Label 7545: @280366 |
| 110306 | GIM_Reject, |
| 110307 | // Label 7543: @280367 |
| 110308 | GIM_Reject, |
| 110309 | // Label 7469: @280368 |
| 110310 | GIM_Try, /*On fail goto*//*Label 7546*/ GIMT_Encode4(280471), |
| 110311 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 110312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110313 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 110314 | GIM_Try, /*On fail goto*//*Label 7547*/ GIMT_Encode4(280427), // Rule ID 59652 // |
| 110315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110316 | // (ctlz:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110317 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 110318 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110319 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110320 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110323 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110324 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110328 | GIR_RootConstrainSelectedInstOperands, |
| 110329 | // GIR_Coverage, 59652, |
| 110330 | GIR_EraseRootFromParent_Done, |
| 110331 | // Label 7547: @280427 |
| 110332 | GIM_Try, /*On fail goto*//*Label 7548*/ GIMT_Encode4(280470), // Rule ID 59653 // |
| 110333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110334 | // (ctlz:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVCLZ_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110335 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 110336 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110337 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCLZ_V_M8), |
| 110340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110342 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110346 | GIR_RootConstrainSelectedInstOperands, |
| 110347 | // GIR_Coverage, 59653, |
| 110348 | GIR_EraseRootFromParent_Done, |
| 110349 | // Label 7548: @280470 |
| 110350 | GIM_Reject, |
| 110351 | // Label 7546: @280471 |
| 110352 | GIM_Reject, |
| 110353 | // Label 7470: @280472 |
| 110354 | GIM_Reject, |
| 110355 | // Label 81: @280473 |
| 110356 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7573*/ GIMT_Encode4(283022), |
| 110357 | /*GILLT_s32*//*Label 7549*/ GIMT_Encode4(280608), |
| 110358 | /*GILLT_s64*//*Label 7550*/ GIMT_Encode4(280686), GIMT_Encode4(0), |
| 110359 | /*GILLT_nxv1s8*//*Label 7551*/ GIMT_Encode4(280734), |
| 110360 | /*GILLT_nxv1s16*//*Label 7552*/ GIMT_Encode4(280838), |
| 110361 | /*GILLT_nxv1s32*//*Label 7553*/ GIMT_Encode4(280942), |
| 110362 | /*GILLT_nxv1s64*//*Label 7554*/ GIMT_Encode4(281046), GIMT_Encode4(0), |
| 110363 | /*GILLT_nxv2s8*//*Label 7555*/ GIMT_Encode4(281150), |
| 110364 | /*GILLT_nxv2s16*//*Label 7556*/ GIMT_Encode4(281254), |
| 110365 | /*GILLT_nxv2s32*//*Label 7557*/ GIMT_Encode4(281358), |
| 110366 | /*GILLT_nxv2s64*//*Label 7558*/ GIMT_Encode4(281462), GIMT_Encode4(0), |
| 110367 | /*GILLT_nxv4s8*//*Label 7559*/ GIMT_Encode4(281566), |
| 110368 | /*GILLT_nxv4s16*//*Label 7560*/ GIMT_Encode4(281670), |
| 110369 | /*GILLT_nxv4s32*//*Label 7561*/ GIMT_Encode4(281774), |
| 110370 | /*GILLT_nxv4s64*//*Label 7562*/ GIMT_Encode4(281878), GIMT_Encode4(0), |
| 110371 | /*GILLT_nxv8s8*//*Label 7563*/ GIMT_Encode4(281982), |
| 110372 | /*GILLT_nxv8s16*//*Label 7564*/ GIMT_Encode4(282086), |
| 110373 | /*GILLT_nxv8s32*//*Label 7565*/ GIMT_Encode4(282190), |
| 110374 | /*GILLT_nxv8s64*//*Label 7566*/ GIMT_Encode4(282294), GIMT_Encode4(0), |
| 110375 | /*GILLT_nxv16s8*//*Label 7567*/ GIMT_Encode4(282398), |
| 110376 | /*GILLT_nxv16s16*//*Label 7568*/ GIMT_Encode4(282502), |
| 110377 | /*GILLT_nxv16s32*//*Label 7569*/ GIMT_Encode4(282606), GIMT_Encode4(0), |
| 110378 | /*GILLT_nxv32s8*//*Label 7570*/ GIMT_Encode4(282710), |
| 110379 | /*GILLT_nxv32s16*//*Label 7571*/ GIMT_Encode4(282814), GIMT_Encode4(0), |
| 110380 | /*GILLT_nxv64s8*//*Label 7572*/ GIMT_Encode4(282918), |
| 110381 | // Label 7549: @280608 |
| 110382 | GIM_Try, /*On fail goto*//*Label 7574*/ GIMT_Encode4(280685), |
| 110383 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 110384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 110385 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 110386 | GIM_Try, /*On fail goto*//*Label 7575*/ GIMT_Encode4(280639), // Rule ID 2669 // |
| 110387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode1), |
| 110388 | // (ctpop:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CPOP:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 110389 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CPOP), |
| 110390 | GIR_RootConstrainSelectedInstOperands, |
| 110391 | // GIR_Coverage, 2669, |
| 110392 | GIR_Done, |
| 110393 | // Label 7575: @280639 |
| 110394 | GIM_Try, /*On fail goto*//*Label 7576*/ GIMT_Encode4(280654), // Rule ID 2797 // |
| 110395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), |
| 110396 | // (ctpop:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CPOPW:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 110397 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CPOPW), |
| 110398 | GIR_RootConstrainSelectedInstOperands, |
| 110399 | // GIR_Coverage, 2797, |
| 110400 | GIR_Done, |
| 110401 | // Label 7576: @280654 |
| 110402 | GIM_Try, /*On fail goto*//*Label 7577*/ GIMT_Encode4(280669), // Rule ID 2798 // |
| 110403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode1), |
| 110404 | // (ctpop:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CPOPW:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 110405 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CPOPW), |
| 110406 | GIR_RootConstrainSelectedInstOperands, |
| 110407 | // GIR_Coverage, 2798, |
| 110408 | GIR_Done, |
| 110409 | // Label 7577: @280669 |
| 110410 | GIM_Try, /*On fail goto*//*Label 7578*/ GIMT_Encode4(280684), // Rule ID 64962 // |
| 110411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 110412 | // (ctpop:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (CV_CNT:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 110413 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_CNT), |
| 110414 | GIR_RootConstrainSelectedInstOperands, |
| 110415 | // GIR_Coverage, 64962, |
| 110416 | GIR_Done, |
| 110417 | // Label 7578: @280684 |
| 110418 | GIM_Reject, |
| 110419 | // Label 7574: @280685 |
| 110420 | GIM_Reject, |
| 110421 | // Label 7550: @280686 |
| 110422 | GIM_Try, /*On fail goto*//*Label 7579*/ GIMT_Encode4(280733), |
| 110423 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 110424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 110425 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 110426 | GIM_Try, /*On fail goto*//*Label 7580*/ GIMT_Encode4(280717), // Rule ID 2668 // |
| 110427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_HwMode0), |
| 110428 | // (ctpop:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CPOP:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 110429 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CPOP), |
| 110430 | GIR_RootConstrainSelectedInstOperands, |
| 110431 | // GIR_Coverage, 2668, |
| 110432 | GIR_Done, |
| 110433 | // Label 7580: @280717 |
| 110434 | GIM_Try, /*On fail goto*//*Label 7581*/ GIMT_Encode4(280732), // Rule ID 64961 // |
| 110435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0), |
| 110436 | // (ctpop:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (CV_CNT:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 110437 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::CV_CNT), |
| 110438 | GIR_RootConstrainSelectedInstOperands, |
| 110439 | // GIR_Coverage, 64961, |
| 110440 | GIR_Done, |
| 110441 | // Label 7581: @280732 |
| 110442 | GIM_Reject, |
| 110443 | // Label 7579: @280733 |
| 110444 | GIM_Reject, |
| 110445 | // Label 7551: @280734 |
| 110446 | GIM_Try, /*On fail goto*//*Label 7582*/ GIMT_Encode4(280837), |
| 110447 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 110448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110450 | GIM_Try, /*On fail goto*//*Label 7583*/ GIMT_Encode4(280793), // Rule ID 59716 // |
| 110451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110452 | // (ctpop:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVCPOP_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 110454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF8), |
| 110458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110460 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110464 | GIR_RootConstrainSelectedInstOperands, |
| 110465 | // GIR_Coverage, 59716, |
| 110466 | GIR_EraseRootFromParent_Done, |
| 110467 | // Label 7583: @280793 |
| 110468 | GIM_Try, /*On fail goto*//*Label 7584*/ GIMT_Encode4(280836), // Rule ID 59717 // |
| 110469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110470 | // (ctpop:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVCPOP_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110471 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 110472 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110473 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110474 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF8), |
| 110476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110477 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110478 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110482 | GIR_RootConstrainSelectedInstOperands, |
| 110483 | // GIR_Coverage, 59717, |
| 110484 | GIR_EraseRootFromParent_Done, |
| 110485 | // Label 7584: @280836 |
| 110486 | GIM_Reject, |
| 110487 | // Label 7582: @280837 |
| 110488 | GIM_Reject, |
| 110489 | // Label 7552: @280838 |
| 110490 | GIM_Try, /*On fail goto*//*Label 7585*/ GIMT_Encode4(280941), |
| 110491 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 110492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110494 | GIM_Try, /*On fail goto*//*Label 7586*/ GIMT_Encode4(280897), // Rule ID 59722 // |
| 110495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110496 | // (ctpop:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVCPOP_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 110497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 110498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110499 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF4), |
| 110502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110503 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110504 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110508 | GIR_RootConstrainSelectedInstOperands, |
| 110509 | // GIR_Coverage, 59722, |
| 110510 | GIR_EraseRootFromParent_Done, |
| 110511 | // Label 7586: @280897 |
| 110512 | GIM_Try, /*On fail goto*//*Label 7587*/ GIMT_Encode4(280940), // Rule ID 59723 // |
| 110513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110514 | // (ctpop:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVCPOP_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 110515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 110516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF4), |
| 110520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110521 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110522 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110526 | GIR_RootConstrainSelectedInstOperands, |
| 110527 | // GIR_Coverage, 59723, |
| 110528 | GIR_EraseRootFromParent_Done, |
| 110529 | // Label 7587: @280940 |
| 110530 | GIM_Reject, |
| 110531 | // Label 7585: @280941 |
| 110532 | GIM_Reject, |
| 110533 | // Label 7553: @280942 |
| 110534 | GIM_Try, /*On fail goto*//*Label 7588*/ GIMT_Encode4(281045), |
| 110535 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 110536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110537 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110538 | GIM_Try, /*On fail goto*//*Label 7589*/ GIMT_Encode4(281001), // Rule ID 59726 // |
| 110539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110540 | // (ctpop:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVCPOP_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 110541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 110542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF2), |
| 110546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110548 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110552 | GIR_RootConstrainSelectedInstOperands, |
| 110553 | // GIR_Coverage, 59726, |
| 110554 | GIR_EraseRootFromParent_Done, |
| 110555 | // Label 7589: @281001 |
| 110556 | GIM_Try, /*On fail goto*//*Label 7590*/ GIMT_Encode4(281044), // Rule ID 59727 // |
| 110557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110558 | // (ctpop:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVCPOP_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 110559 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 110560 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110561 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110562 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF2), |
| 110564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110565 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110566 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110570 | GIR_RootConstrainSelectedInstOperands, |
| 110571 | // GIR_Coverage, 59727, |
| 110572 | GIR_EraseRootFromParent_Done, |
| 110573 | // Label 7590: @281044 |
| 110574 | GIM_Reject, |
| 110575 | // Label 7588: @281045 |
| 110576 | GIM_Reject, |
| 110577 | // Label 7554: @281046 |
| 110578 | GIM_Try, /*On fail goto*//*Label 7591*/ GIMT_Encode4(281149), |
| 110579 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 110580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110582 | GIM_Try, /*On fail goto*//*Label 7592*/ GIMT_Encode4(281105), // Rule ID 59734 // |
| 110583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 110584 | // (ctpop:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 110585 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 110586 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110587 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110588 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110591 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110592 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110596 | GIR_RootConstrainSelectedInstOperands, |
| 110597 | // GIR_Coverage, 59734, |
| 110598 | GIR_EraseRootFromParent_Done, |
| 110599 | // Label 7592: @281105 |
| 110600 | GIM_Try, /*On fail goto*//*Label 7593*/ GIMT_Encode4(281148), // Rule ID 59735 // |
| 110601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 110602 | // (ctpop:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 110603 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 110604 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110605 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110609 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110610 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110614 | GIR_RootConstrainSelectedInstOperands, |
| 110615 | // GIR_Coverage, 59735, |
| 110616 | GIR_EraseRootFromParent_Done, |
| 110617 | // Label 7593: @281148 |
| 110618 | GIM_Reject, |
| 110619 | // Label 7591: @281149 |
| 110620 | GIM_Reject, |
| 110621 | // Label 7555: @281150 |
| 110622 | GIM_Try, /*On fail goto*//*Label 7594*/ GIMT_Encode4(281253), |
| 110623 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 110624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110626 | GIM_Try, /*On fail goto*//*Label 7595*/ GIMT_Encode4(281209), // Rule ID 59718 // |
| 110627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110628 | // (ctpop:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVCPOP_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110629 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 110630 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110631 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF4), |
| 110634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110635 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110636 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110640 | GIR_RootConstrainSelectedInstOperands, |
| 110641 | // GIR_Coverage, 59718, |
| 110642 | GIR_EraseRootFromParent_Done, |
| 110643 | // Label 7595: @281209 |
| 110644 | GIM_Try, /*On fail goto*//*Label 7596*/ GIMT_Encode4(281252), // Rule ID 59719 // |
| 110645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110646 | // (ctpop:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVCPOP_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110647 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 110648 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF4), |
| 110652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110654 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110658 | GIR_RootConstrainSelectedInstOperands, |
| 110659 | // GIR_Coverage, 59719, |
| 110660 | GIR_EraseRootFromParent_Done, |
| 110661 | // Label 7596: @281252 |
| 110662 | GIM_Reject, |
| 110663 | // Label 7594: @281253 |
| 110664 | GIM_Reject, |
| 110665 | // Label 7556: @281254 |
| 110666 | GIM_Try, /*On fail goto*//*Label 7597*/ GIMT_Encode4(281357), |
| 110667 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 110668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110669 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110670 | GIM_Try, /*On fail goto*//*Label 7598*/ GIMT_Encode4(281313), // Rule ID 59724 // |
| 110671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110672 | // (ctpop:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVCPOP_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 110673 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 110674 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110675 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF2), |
| 110678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110679 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110680 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110684 | GIR_RootConstrainSelectedInstOperands, |
| 110685 | // GIR_Coverage, 59724, |
| 110686 | GIR_EraseRootFromParent_Done, |
| 110687 | // Label 7598: @281313 |
| 110688 | GIM_Try, /*On fail goto*//*Label 7599*/ GIMT_Encode4(281356), // Rule ID 59725 // |
| 110689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110690 | // (ctpop:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVCPOP_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 110691 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 110692 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110693 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF2), |
| 110696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110697 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110698 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110702 | GIR_RootConstrainSelectedInstOperands, |
| 110703 | // GIR_Coverage, 59725, |
| 110704 | GIR_EraseRootFromParent_Done, |
| 110705 | // Label 7599: @281356 |
| 110706 | GIM_Reject, |
| 110707 | // Label 7597: @281357 |
| 110708 | GIM_Reject, |
| 110709 | // Label 7557: @281358 |
| 110710 | GIM_Try, /*On fail goto*//*Label 7600*/ GIMT_Encode4(281461), |
| 110711 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 110712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110713 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110714 | GIM_Try, /*On fail goto*//*Label 7601*/ GIMT_Encode4(281417), // Rule ID 59732 // |
| 110715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110716 | // (ctpop:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 110717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 110718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110719 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110728 | GIR_RootConstrainSelectedInstOperands, |
| 110729 | // GIR_Coverage, 59732, |
| 110730 | GIR_EraseRootFromParent_Done, |
| 110731 | // Label 7601: @281417 |
| 110732 | GIM_Try, /*On fail goto*//*Label 7602*/ GIMT_Encode4(281460), // Rule ID 59733 // |
| 110733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110734 | // (ctpop:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 110735 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 110736 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110737 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110742 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110746 | GIR_RootConstrainSelectedInstOperands, |
| 110747 | // GIR_Coverage, 59733, |
| 110748 | GIR_EraseRootFromParent_Done, |
| 110749 | // Label 7602: @281460 |
| 110750 | GIM_Reject, |
| 110751 | // Label 7600: @281461 |
| 110752 | GIM_Reject, |
| 110753 | // Label 7558: @281462 |
| 110754 | GIM_Try, /*On fail goto*//*Label 7603*/ GIMT_Encode4(281565), |
| 110755 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 110756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 110757 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 110758 | GIM_Try, /*On fail goto*//*Label 7604*/ GIMT_Encode4(281521), // Rule ID 59754 // |
| 110759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 110760 | // (ctpop:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 110761 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 110762 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110763 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 110766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110768 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110772 | GIR_RootConstrainSelectedInstOperands, |
| 110773 | // GIR_Coverage, 59754, |
| 110774 | GIR_EraseRootFromParent_Done, |
| 110775 | // Label 7604: @281521 |
| 110776 | GIM_Try, /*On fail goto*//*Label 7605*/ GIMT_Encode4(281564), // Rule ID 59755 // |
| 110777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 110778 | // (ctpop:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 110779 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 110780 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110781 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110782 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 110784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110785 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110786 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110790 | GIR_RootConstrainSelectedInstOperands, |
| 110791 | // GIR_Coverage, 59755, |
| 110792 | GIR_EraseRootFromParent_Done, |
| 110793 | // Label 7605: @281564 |
| 110794 | GIM_Reject, |
| 110795 | // Label 7603: @281565 |
| 110796 | GIM_Reject, |
| 110797 | // Label 7559: @281566 |
| 110798 | GIM_Try, /*On fail goto*//*Label 7606*/ GIMT_Encode4(281669), |
| 110799 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 110800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110801 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110802 | GIM_Try, /*On fail goto*//*Label 7607*/ GIMT_Encode4(281625), // Rule ID 59720 // |
| 110803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110804 | // (ctpop:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVCPOP_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110805 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 110806 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110807 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF2), |
| 110810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110811 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110812 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110816 | GIR_RootConstrainSelectedInstOperands, |
| 110817 | // GIR_Coverage, 59720, |
| 110818 | GIR_EraseRootFromParent_Done, |
| 110819 | // Label 7607: @281625 |
| 110820 | GIM_Try, /*On fail goto*//*Label 7608*/ GIMT_Encode4(281668), // Rule ID 59721 // |
| 110821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110822 | // (ctpop:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVCPOP_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 110824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110826 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_MF2), |
| 110828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110829 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110830 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110834 | GIR_RootConstrainSelectedInstOperands, |
| 110835 | // GIR_Coverage, 59721, |
| 110836 | GIR_EraseRootFromParent_Done, |
| 110837 | // Label 7608: @281668 |
| 110838 | GIM_Reject, |
| 110839 | // Label 7606: @281669 |
| 110840 | GIM_Reject, |
| 110841 | // Label 7560: @281670 |
| 110842 | GIM_Try, /*On fail goto*//*Label 7609*/ GIMT_Encode4(281773), |
| 110843 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 110844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110845 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110846 | GIM_Try, /*On fail goto*//*Label 7610*/ GIMT_Encode4(281729), // Rule ID 59730 // |
| 110847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110848 | // (ctpop:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 110849 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 110850 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110851 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110855 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110856 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110860 | GIR_RootConstrainSelectedInstOperands, |
| 110861 | // GIR_Coverage, 59730, |
| 110862 | GIR_EraseRootFromParent_Done, |
| 110863 | // Label 7610: @281729 |
| 110864 | GIM_Try, /*On fail goto*//*Label 7611*/ GIMT_Encode4(281772), // Rule ID 59731 // |
| 110865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110866 | // (ctpop:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 110867 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 110868 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110869 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110873 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110874 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 110877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110878 | GIR_RootConstrainSelectedInstOperands, |
| 110879 | // GIR_Coverage, 59731, |
| 110880 | GIR_EraseRootFromParent_Done, |
| 110881 | // Label 7611: @281772 |
| 110882 | GIM_Reject, |
| 110883 | // Label 7609: @281773 |
| 110884 | GIM_Reject, |
| 110885 | // Label 7561: @281774 |
| 110886 | GIM_Try, /*On fail goto*//*Label 7612*/ GIMT_Encode4(281877), |
| 110887 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 110888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 110889 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 110890 | GIM_Try, /*On fail goto*//*Label 7613*/ GIMT_Encode4(281833), // Rule ID 59748 // |
| 110891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110892 | // (ctpop:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 110893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 110894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 110898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110900 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110904 | GIR_RootConstrainSelectedInstOperands, |
| 110905 | // GIR_Coverage, 59748, |
| 110906 | GIR_EraseRootFromParent_Done, |
| 110907 | // Label 7613: @281833 |
| 110908 | GIM_Try, /*On fail goto*//*Label 7614*/ GIMT_Encode4(281876), // Rule ID 59749 // |
| 110909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110910 | // (ctpop:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 110911 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 110912 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110913 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110914 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 110916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110917 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110918 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 110921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110922 | GIR_RootConstrainSelectedInstOperands, |
| 110923 | // GIR_Coverage, 59749, |
| 110924 | GIR_EraseRootFromParent_Done, |
| 110925 | // Label 7614: @281876 |
| 110926 | GIM_Reject, |
| 110927 | // Label 7612: @281877 |
| 110928 | GIM_Reject, |
| 110929 | // Label 7562: @281878 |
| 110930 | GIM_Try, /*On fail goto*//*Label 7615*/ GIMT_Encode4(281981), |
| 110931 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 110932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 110934 | GIM_Try, /*On fail goto*//*Label 7616*/ GIMT_Encode4(281937), // Rule ID 59756 // |
| 110935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 110936 | // (ctpop:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 110937 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 110938 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110939 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110940 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 110942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110943 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110944 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110948 | GIR_RootConstrainSelectedInstOperands, |
| 110949 | // GIR_Coverage, 59756, |
| 110950 | GIR_EraseRootFromParent_Done, |
| 110951 | // Label 7616: @281937 |
| 110952 | GIM_Try, /*On fail goto*//*Label 7617*/ GIMT_Encode4(281980), // Rule ID 59757 // |
| 110953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 110954 | // (ctpop:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 110955 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 110956 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110957 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 110960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110961 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110962 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 110965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110966 | GIR_RootConstrainSelectedInstOperands, |
| 110967 | // GIR_Coverage, 59757, |
| 110968 | GIR_EraseRootFromParent_Done, |
| 110969 | // Label 7617: @281980 |
| 110970 | GIM_Reject, |
| 110971 | // Label 7615: @281981 |
| 110972 | GIM_Reject, |
| 110973 | // Label 7563: @281982 |
| 110974 | GIM_Try, /*On fail goto*//*Label 7618*/ GIMT_Encode4(282085), |
| 110975 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 110976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110977 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 110978 | GIM_Try, /*On fail goto*//*Label 7619*/ GIMT_Encode4(282041), // Rule ID 59728 // |
| 110979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 110980 | // (ctpop:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 110981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 110982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 110983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 110984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 110985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 110986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 110987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 110988 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 110989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 110990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 110992 | GIR_RootConstrainSelectedInstOperands, |
| 110993 | // GIR_Coverage, 59728, |
| 110994 | GIR_EraseRootFromParent_Done, |
| 110995 | // Label 7619: @282041 |
| 110996 | GIM_Try, /*On fail goto*//*Label 7620*/ GIMT_Encode4(282084), // Rule ID 59729 // |
| 110997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 110998 | // (ctpop:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVCPOP_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 110999 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 111000 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M1), |
| 111004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111006 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111010 | GIR_RootConstrainSelectedInstOperands, |
| 111011 | // GIR_Coverage, 59729, |
| 111012 | GIR_EraseRootFromParent_Done, |
| 111013 | // Label 7620: @282084 |
| 111014 | GIM_Reject, |
| 111015 | // Label 7618: @282085 |
| 111016 | GIM_Reject, |
| 111017 | // Label 7564: @282086 |
| 111018 | GIM_Try, /*On fail goto*//*Label 7621*/ GIMT_Encode4(282189), |
| 111019 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 111020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111021 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111022 | GIM_Try, /*On fail goto*//*Label 7622*/ GIMT_Encode4(282145), // Rule ID 59742 // |
| 111023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111024 | // (ctpop:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 111025 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 111026 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111027 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 111030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111031 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111032 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111036 | GIR_RootConstrainSelectedInstOperands, |
| 111037 | // GIR_Coverage, 59742, |
| 111038 | GIR_EraseRootFromParent_Done, |
| 111039 | // Label 7622: @282145 |
| 111040 | GIM_Try, /*On fail goto*//*Label 7623*/ GIMT_Encode4(282188), // Rule ID 59743 // |
| 111041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111042 | // (ctpop:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 111043 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 111044 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111045 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111046 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 111048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111049 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111050 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111054 | GIR_RootConstrainSelectedInstOperands, |
| 111055 | // GIR_Coverage, 59743, |
| 111056 | GIR_EraseRootFromParent_Done, |
| 111057 | // Label 7623: @282188 |
| 111058 | GIM_Reject, |
| 111059 | // Label 7621: @282189 |
| 111060 | GIM_Reject, |
| 111061 | // Label 7565: @282190 |
| 111062 | GIM_Try, /*On fail goto*//*Label 7624*/ GIMT_Encode4(282293), |
| 111063 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 111064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111065 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111066 | GIM_Try, /*On fail goto*//*Label 7625*/ GIMT_Encode4(282249), // Rule ID 59750 // |
| 111067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111068 | // (ctpop:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 111069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 111070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 111074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111076 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111080 | GIR_RootConstrainSelectedInstOperands, |
| 111081 | // GIR_Coverage, 59750, |
| 111082 | GIR_EraseRootFromParent_Done, |
| 111083 | // Label 7625: @282249 |
| 111084 | GIM_Try, /*On fail goto*//*Label 7626*/ GIMT_Encode4(282292), // Rule ID 59751 // |
| 111085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111086 | // (ctpop:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 111087 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 111088 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111089 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111090 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 111092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111094 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111098 | GIR_RootConstrainSelectedInstOperands, |
| 111099 | // GIR_Coverage, 59751, |
| 111100 | GIR_EraseRootFromParent_Done, |
| 111101 | // Label 7626: @282292 |
| 111102 | GIM_Reject, |
| 111103 | // Label 7624: @282293 |
| 111104 | GIM_Reject, |
| 111105 | // Label 7566: @282294 |
| 111106 | GIM_Try, /*On fail goto*//*Label 7627*/ GIMT_Encode4(282397), |
| 111107 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 111108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111110 | GIM_Try, /*On fail goto*//*Label 7628*/ GIMT_Encode4(282353), // Rule ID 59758 // |
| 111111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 111112 | // (ctpop:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 111113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 111114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111119 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111120 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111124 | GIR_RootConstrainSelectedInstOperands, |
| 111125 | // GIR_Coverage, 59758, |
| 111126 | GIR_EraseRootFromParent_Done, |
| 111127 | // Label 7628: @282353 |
| 111128 | GIM_Try, /*On fail goto*//*Label 7629*/ GIMT_Encode4(282396), // Rule ID 59759 // |
| 111129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 111130 | // (ctpop:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 111131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 111132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111138 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111142 | GIR_RootConstrainSelectedInstOperands, |
| 111143 | // GIR_Coverage, 59759, |
| 111144 | GIR_EraseRootFromParent_Done, |
| 111145 | // Label 7629: @282396 |
| 111146 | GIM_Reject, |
| 111147 | // Label 7627: @282397 |
| 111148 | GIM_Reject, |
| 111149 | // Label 7567: @282398 |
| 111150 | GIM_Try, /*On fail goto*//*Label 7630*/ GIMT_Encode4(282501), |
| 111151 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 111152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111153 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111154 | GIM_Try, /*On fail goto*//*Label 7631*/ GIMT_Encode4(282457), // Rule ID 59736 // |
| 111155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111156 | // (ctpop:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 111157 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 111158 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111159 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 111162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111163 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111164 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111168 | GIR_RootConstrainSelectedInstOperands, |
| 111169 | // GIR_Coverage, 59736, |
| 111170 | GIR_EraseRootFromParent_Done, |
| 111171 | // Label 7631: @282457 |
| 111172 | GIM_Try, /*On fail goto*//*Label 7632*/ GIMT_Encode4(282500), // Rule ID 59737 // |
| 111173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111174 | // (ctpop:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVCPOP_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 111175 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 111176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M2), |
| 111180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111181 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111182 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111186 | GIR_RootConstrainSelectedInstOperands, |
| 111187 | // GIR_Coverage, 59737, |
| 111188 | GIR_EraseRootFromParent_Done, |
| 111189 | // Label 7632: @282500 |
| 111190 | GIM_Reject, |
| 111191 | // Label 7630: @282501 |
| 111192 | GIM_Reject, |
| 111193 | // Label 7568: @282502 |
| 111194 | GIM_Try, /*On fail goto*//*Label 7633*/ GIMT_Encode4(282605), |
| 111195 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 111196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111198 | GIM_Try, /*On fail goto*//*Label 7634*/ GIMT_Encode4(282561), // Rule ID 59744 // |
| 111199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111200 | // (ctpop:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 111201 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 111202 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111203 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111204 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 111206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111208 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111212 | GIR_RootConstrainSelectedInstOperands, |
| 111213 | // GIR_Coverage, 59744, |
| 111214 | GIR_EraseRootFromParent_Done, |
| 111215 | // Label 7634: @282561 |
| 111216 | GIM_Try, /*On fail goto*//*Label 7635*/ GIMT_Encode4(282604), // Rule ID 59745 // |
| 111217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111218 | // (ctpop:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 111219 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 111220 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111221 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111222 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 111224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111225 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111226 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111230 | GIR_RootConstrainSelectedInstOperands, |
| 111231 | // GIR_Coverage, 59745, |
| 111232 | GIR_EraseRootFromParent_Done, |
| 111233 | // Label 7635: @282604 |
| 111234 | GIM_Reject, |
| 111235 | // Label 7633: @282605 |
| 111236 | GIM_Reject, |
| 111237 | // Label 7569: @282606 |
| 111238 | GIM_Try, /*On fail goto*//*Label 7636*/ GIMT_Encode4(282709), |
| 111239 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 111240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111241 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111242 | GIM_Try, /*On fail goto*//*Label 7637*/ GIMT_Encode4(282665), // Rule ID 59752 // |
| 111243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111244 | // (ctpop:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 111245 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 111246 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111247 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111248 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111251 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111252 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111256 | GIR_RootConstrainSelectedInstOperands, |
| 111257 | // GIR_Coverage, 59752, |
| 111258 | GIR_EraseRootFromParent_Done, |
| 111259 | // Label 7637: @282665 |
| 111260 | GIM_Try, /*On fail goto*//*Label 7638*/ GIMT_Encode4(282708), // Rule ID 59753 // |
| 111261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111262 | // (ctpop:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 111263 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 111264 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111265 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111269 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111270 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111274 | GIR_RootConstrainSelectedInstOperands, |
| 111275 | // GIR_Coverage, 59753, |
| 111276 | GIR_EraseRootFromParent_Done, |
| 111277 | // Label 7638: @282708 |
| 111278 | GIM_Reject, |
| 111279 | // Label 7636: @282709 |
| 111280 | GIM_Reject, |
| 111281 | // Label 7570: @282710 |
| 111282 | GIM_Try, /*On fail goto*//*Label 7639*/ GIMT_Encode4(282813), |
| 111283 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 111284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111285 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111286 | GIM_Try, /*On fail goto*//*Label 7640*/ GIMT_Encode4(282769), // Rule ID 59738 // |
| 111287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111288 | // (ctpop:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 111289 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 111290 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111291 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 111294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111295 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111296 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111300 | GIR_RootConstrainSelectedInstOperands, |
| 111301 | // GIR_Coverage, 59738, |
| 111302 | GIR_EraseRootFromParent_Done, |
| 111303 | // Label 7640: @282769 |
| 111304 | GIM_Try, /*On fail goto*//*Label 7641*/ GIMT_Encode4(282812), // Rule ID 59739 // |
| 111305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111306 | // (ctpop:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVCPOP_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 111307 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 111308 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111309 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111310 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M4), |
| 111312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111313 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111314 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111318 | GIR_RootConstrainSelectedInstOperands, |
| 111319 | // GIR_Coverage, 59739, |
| 111320 | GIR_EraseRootFromParent_Done, |
| 111321 | // Label 7641: @282812 |
| 111322 | GIM_Reject, |
| 111323 | // Label 7639: @282813 |
| 111324 | GIM_Reject, |
| 111325 | // Label 7571: @282814 |
| 111326 | GIM_Try, /*On fail goto*//*Label 7642*/ GIMT_Encode4(282917), |
| 111327 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 111328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111329 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111330 | GIM_Try, /*On fail goto*//*Label 7643*/ GIMT_Encode4(282873), // Rule ID 59746 // |
| 111331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111332 | // (ctpop:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 111333 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 111334 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111335 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111339 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111340 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111344 | GIR_RootConstrainSelectedInstOperands, |
| 111345 | // GIR_Coverage, 59746, |
| 111346 | GIR_EraseRootFromParent_Done, |
| 111347 | // Label 7643: @282873 |
| 111348 | GIM_Try, /*On fail goto*//*Label 7644*/ GIMT_Encode4(282916), // Rule ID 59747 // |
| 111349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111350 | // (ctpop:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 111351 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 111352 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111353 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111354 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111357 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111358 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111362 | GIR_RootConstrainSelectedInstOperands, |
| 111363 | // GIR_Coverage, 59747, |
| 111364 | GIR_EraseRootFromParent_Done, |
| 111365 | // Label 7644: @282916 |
| 111366 | GIM_Reject, |
| 111367 | // Label 7642: @282917 |
| 111368 | GIM_Reject, |
| 111369 | // Label 7572: @282918 |
| 111370 | GIM_Try, /*On fail goto*//*Label 7645*/ GIMT_Encode4(283021), |
| 111371 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 111372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111373 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 111374 | GIM_Try, /*On fail goto*//*Label 7646*/ GIMT_Encode4(282977), // Rule ID 59740 // |
| 111375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 111376 | // (ctpop:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 111377 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 111378 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111379 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111383 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111384 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111388 | GIR_RootConstrainSelectedInstOperands, |
| 111389 | // GIR_Coverage, 59740, |
| 111390 | GIR_EraseRootFromParent_Done, |
| 111391 | // Label 7646: @282977 |
| 111392 | GIM_Try, /*On fail goto*//*Label 7647*/ GIMT_Encode4(283020), // Rule ID 59741 // |
| 111393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 111394 | // (ctpop:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVCPOP_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 111395 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 111396 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111397 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111398 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVCPOP_V_M8), |
| 111400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111401 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111402 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111406 | GIR_RootConstrainSelectedInstOperands, |
| 111407 | // GIR_Coverage, 59741, |
| 111408 | GIR_EraseRootFromParent_Done, |
| 111409 | // Label 7647: @283020 |
| 111410 | GIM_Reject, |
| 111411 | // Label 7645: @283021 |
| 111412 | GIM_Reject, |
| 111413 | // Label 7573: @283022 |
| 111414 | GIM_Reject, |
| 111415 | // Label 82: @283023 |
| 111416 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7672*/ GIMT_Encode4(285557), |
| 111417 | /*GILLT_s32*//*Label 7648*/ GIMT_Encode4(283158), |
| 111418 | /*GILLT_s64*//*Label 7649*/ GIMT_Encode4(283221), GIMT_Encode4(0), |
| 111419 | /*GILLT_nxv1s8*//*Label 7650*/ GIMT_Encode4(283269), |
| 111420 | /*GILLT_nxv1s16*//*Label 7651*/ GIMT_Encode4(283373), |
| 111421 | /*GILLT_nxv1s32*//*Label 7652*/ GIMT_Encode4(283477), |
| 111422 | /*GILLT_nxv1s64*//*Label 7653*/ GIMT_Encode4(283581), GIMT_Encode4(0), |
| 111423 | /*GILLT_nxv2s8*//*Label 7654*/ GIMT_Encode4(283685), |
| 111424 | /*GILLT_nxv2s16*//*Label 7655*/ GIMT_Encode4(283789), |
| 111425 | /*GILLT_nxv2s32*//*Label 7656*/ GIMT_Encode4(283893), |
| 111426 | /*GILLT_nxv2s64*//*Label 7657*/ GIMT_Encode4(283997), GIMT_Encode4(0), |
| 111427 | /*GILLT_nxv4s8*//*Label 7658*/ GIMT_Encode4(284101), |
| 111428 | /*GILLT_nxv4s16*//*Label 7659*/ GIMT_Encode4(284205), |
| 111429 | /*GILLT_nxv4s32*//*Label 7660*/ GIMT_Encode4(284309), |
| 111430 | /*GILLT_nxv4s64*//*Label 7661*/ GIMT_Encode4(284413), GIMT_Encode4(0), |
| 111431 | /*GILLT_nxv8s8*//*Label 7662*/ GIMT_Encode4(284517), |
| 111432 | /*GILLT_nxv8s16*//*Label 7663*/ GIMT_Encode4(284621), |
| 111433 | /*GILLT_nxv8s32*//*Label 7664*/ GIMT_Encode4(284725), |
| 111434 | /*GILLT_nxv8s64*//*Label 7665*/ GIMT_Encode4(284829), GIMT_Encode4(0), |
| 111435 | /*GILLT_nxv16s8*//*Label 7666*/ GIMT_Encode4(284933), |
| 111436 | /*GILLT_nxv16s16*//*Label 7667*/ GIMT_Encode4(285037), |
| 111437 | /*GILLT_nxv16s32*//*Label 7668*/ GIMT_Encode4(285141), GIMT_Encode4(0), |
| 111438 | /*GILLT_nxv32s8*//*Label 7669*/ GIMT_Encode4(285245), |
| 111439 | /*GILLT_nxv32s16*//*Label 7670*/ GIMT_Encode4(285349), GIMT_Encode4(0), |
| 111440 | /*GILLT_nxv64s8*//*Label 7671*/ GIMT_Encode4(285453), |
| 111441 | // Label 7648: @283158 |
| 111442 | GIM_Try, /*On fail goto*//*Label 7673*/ GIMT_Encode4(283220), |
| 111443 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 111444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 111445 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 111446 | GIM_Try, /*On fail goto*//*Label 7674*/ GIMT_Encode4(283189), // Rule ID 2686 // |
| 111447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV32_HwMode0), |
| 111448 | // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (REV8_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 111449 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REV8_RV32), |
| 111450 | GIR_RootConstrainSelectedInstOperands, |
| 111451 | // GIR_Coverage, 2686, |
| 111452 | GIR_Done, |
| 111453 | // Label 7674: @283189 |
| 111454 | GIM_Try, /*On fail goto*//*Label 7675*/ GIMT_Encode4(283204), // Rule ID 2687 // |
| 111455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV32_HwMode1), |
| 111456 | // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (REV8_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 111457 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REV8_RV32), |
| 111458 | GIR_RootConstrainSelectedInstOperands, |
| 111459 | // GIR_Coverage, 2687, |
| 111460 | GIR_Done, |
| 111461 | // Label 7675: @283204 |
| 111462 | GIM_Try, /*On fail goto*//*Label 7676*/ GIMT_Encode4(283219), // Rule ID 63030 // |
| 111463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode1), |
| 111464 | // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$rs1) => (TH_REV:{ *:[i32] } GPR:{ *:[i32] }:$rs1) |
| 111465 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::TH_REV), |
| 111466 | GIR_RootConstrainSelectedInstOperands, |
| 111467 | // GIR_Coverage, 63030, |
| 111468 | GIR_Done, |
| 111469 | // Label 7676: @283219 |
| 111470 | GIM_Reject, |
| 111471 | // Label 7673: @283220 |
| 111472 | GIM_Reject, |
| 111473 | // Label 7649: @283221 |
| 111474 | GIM_Try, /*On fail goto*//*Label 7677*/ GIMT_Encode4(283268), |
| 111475 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 111476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 111477 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 111478 | GIM_Try, /*On fail goto*//*Label 7678*/ GIMT_Encode4(283252), // Rule ID 2688 // |
| 111479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), |
| 111480 | // (bswap:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (REV8_RV64:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 111481 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REV8_RV64), |
| 111482 | GIR_RootConstrainSelectedInstOperands, |
| 111483 | // GIR_Coverage, 2688, |
| 111484 | GIR_Done, |
| 111485 | // Label 7678: @283252 |
| 111486 | GIM_Try, /*On fail goto*//*Label 7679*/ GIMT_Encode4(283267), // Rule ID 63029 // |
| 111487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBb_HwMode0), |
| 111488 | // (bswap:{ *:[i64] } GPR:{ *:[i64] }:$rs1) => (TH_REV:{ *:[i64] } GPR:{ *:[i64] }:$rs1) |
| 111489 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::TH_REV), |
| 111490 | GIR_RootConstrainSelectedInstOperands, |
| 111491 | // GIR_Coverage, 63029, |
| 111492 | GIR_Done, |
| 111493 | // Label 7679: @283267 |
| 111494 | GIM_Reject, |
| 111495 | // Label 7677: @283268 |
| 111496 | GIM_Reject, |
| 111497 | // Label 7650: @283269 |
| 111498 | GIM_Try, /*On fail goto*//*Label 7680*/ GIMT_Encode4(283372), |
| 111499 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 111500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111501 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111502 | GIM_Try, /*On fail goto*//*Label 7681*/ GIMT_Encode4(283328), // Rule ID 59584 // |
| 111503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111504 | // (bswap:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVREV8_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 111505 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 111506 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111507 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF8), |
| 111510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111511 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111512 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111516 | GIR_RootConstrainSelectedInstOperands, |
| 111517 | // GIR_Coverage, 59584, |
| 111518 | GIR_EraseRootFromParent_Done, |
| 111519 | // Label 7681: @283328 |
| 111520 | GIM_Try, /*On fail goto*//*Label 7682*/ GIMT_Encode4(283371), // Rule ID 59585 // |
| 111521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111522 | // (bswap:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVREV8_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 111523 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 111524 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111525 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111526 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF8), |
| 111528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111529 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111530 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111534 | GIR_RootConstrainSelectedInstOperands, |
| 111535 | // GIR_Coverage, 59585, |
| 111536 | GIR_EraseRootFromParent_Done, |
| 111537 | // Label 7682: @283371 |
| 111538 | GIM_Reject, |
| 111539 | // Label 7680: @283372 |
| 111540 | GIM_Reject, |
| 111541 | // Label 7651: @283373 |
| 111542 | GIM_Try, /*On fail goto*//*Label 7683*/ GIMT_Encode4(283476), |
| 111543 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 111544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111546 | GIM_Try, /*On fail goto*//*Label 7684*/ GIMT_Encode4(283432), // Rule ID 59590 // |
| 111547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111548 | // (bswap:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVREV8_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 111549 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 111550 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111551 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF4), |
| 111554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111555 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111556 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111560 | GIR_RootConstrainSelectedInstOperands, |
| 111561 | // GIR_Coverage, 59590, |
| 111562 | GIR_EraseRootFromParent_Done, |
| 111563 | // Label 7684: @283432 |
| 111564 | GIM_Try, /*On fail goto*//*Label 7685*/ GIMT_Encode4(283475), // Rule ID 59591 // |
| 111565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111566 | // (bswap:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVREV8_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 111567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 111568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF4), |
| 111572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111573 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111574 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111578 | GIR_RootConstrainSelectedInstOperands, |
| 111579 | // GIR_Coverage, 59591, |
| 111580 | GIR_EraseRootFromParent_Done, |
| 111581 | // Label 7685: @283475 |
| 111582 | GIM_Reject, |
| 111583 | // Label 7683: @283476 |
| 111584 | GIM_Reject, |
| 111585 | // Label 7652: @283477 |
| 111586 | GIM_Try, /*On fail goto*//*Label 7686*/ GIMT_Encode4(283580), |
| 111587 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 111588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111590 | GIM_Try, /*On fail goto*//*Label 7687*/ GIMT_Encode4(283536), // Rule ID 59594 // |
| 111591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111592 | // (bswap:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVREV8_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 111593 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 111594 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111595 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111596 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF2), |
| 111598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111599 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111600 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111604 | GIR_RootConstrainSelectedInstOperands, |
| 111605 | // GIR_Coverage, 59594, |
| 111606 | GIR_EraseRootFromParent_Done, |
| 111607 | // Label 7687: @283536 |
| 111608 | GIM_Try, /*On fail goto*//*Label 7688*/ GIMT_Encode4(283579), // Rule ID 59595 // |
| 111609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111610 | // (bswap:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVREV8_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 111611 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 111612 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111613 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF2), |
| 111616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111618 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111622 | GIR_RootConstrainSelectedInstOperands, |
| 111623 | // GIR_Coverage, 59595, |
| 111624 | GIR_EraseRootFromParent_Done, |
| 111625 | // Label 7688: @283579 |
| 111626 | GIM_Reject, |
| 111627 | // Label 7686: @283580 |
| 111628 | GIM_Reject, |
| 111629 | // Label 7653: @283581 |
| 111630 | GIM_Try, /*On fail goto*//*Label 7689*/ GIMT_Encode4(283684), |
| 111631 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 111632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111634 | GIM_Try, /*On fail goto*//*Label 7690*/ GIMT_Encode4(283640), // Rule ID 59602 // |
| 111635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode0), |
| 111636 | // (bswap:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 111637 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 111638 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111639 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 111642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111643 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111644 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111648 | GIR_RootConstrainSelectedInstOperands, |
| 111649 | // GIR_Coverage, 59602, |
| 111650 | GIR_EraseRootFromParent_Done, |
| 111651 | // Label 7690: @283640 |
| 111652 | GIM_Try, /*On fail goto*//*Label 7691*/ GIMT_Encode4(283683), // Rule ID 59603 // |
| 111653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode1), |
| 111654 | // (bswap:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 111655 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 111656 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111657 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111658 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 111660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111661 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111662 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111666 | GIR_RootConstrainSelectedInstOperands, |
| 111667 | // GIR_Coverage, 59603, |
| 111668 | GIR_EraseRootFromParent_Done, |
| 111669 | // Label 7691: @283683 |
| 111670 | GIM_Reject, |
| 111671 | // Label 7689: @283684 |
| 111672 | GIM_Reject, |
| 111673 | // Label 7654: @283685 |
| 111674 | GIM_Try, /*On fail goto*//*Label 7692*/ GIMT_Encode4(283788), |
| 111675 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 111676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111677 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111678 | GIM_Try, /*On fail goto*//*Label 7693*/ GIMT_Encode4(283744), // Rule ID 59586 // |
| 111679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111680 | // (bswap:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVREV8_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 111681 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 111682 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111683 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF4), |
| 111686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111687 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111688 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111692 | GIR_RootConstrainSelectedInstOperands, |
| 111693 | // GIR_Coverage, 59586, |
| 111694 | GIR_EraseRootFromParent_Done, |
| 111695 | // Label 7693: @283744 |
| 111696 | GIM_Try, /*On fail goto*//*Label 7694*/ GIMT_Encode4(283787), // Rule ID 59587 // |
| 111697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111698 | // (bswap:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVREV8_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 111699 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 111700 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111701 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111702 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF4), |
| 111704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111705 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111706 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111710 | GIR_RootConstrainSelectedInstOperands, |
| 111711 | // GIR_Coverage, 59587, |
| 111712 | GIR_EraseRootFromParent_Done, |
| 111713 | // Label 7694: @283787 |
| 111714 | GIM_Reject, |
| 111715 | // Label 7692: @283788 |
| 111716 | GIM_Reject, |
| 111717 | // Label 7655: @283789 |
| 111718 | GIM_Try, /*On fail goto*//*Label 7695*/ GIMT_Encode4(283892), |
| 111719 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 111720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111721 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111722 | GIM_Try, /*On fail goto*//*Label 7696*/ GIMT_Encode4(283848), // Rule ID 59592 // |
| 111723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111724 | // (bswap:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVREV8_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 111725 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 111726 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111727 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF2), |
| 111730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111731 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111732 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111736 | GIR_RootConstrainSelectedInstOperands, |
| 111737 | // GIR_Coverage, 59592, |
| 111738 | GIR_EraseRootFromParent_Done, |
| 111739 | // Label 7696: @283848 |
| 111740 | GIM_Try, /*On fail goto*//*Label 7697*/ GIMT_Encode4(283891), // Rule ID 59593 // |
| 111741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111742 | // (bswap:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVREV8_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 111743 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 111744 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111745 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111746 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF2), |
| 111748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111749 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111750 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111754 | GIR_RootConstrainSelectedInstOperands, |
| 111755 | // GIR_Coverage, 59593, |
| 111756 | GIR_EraseRootFromParent_Done, |
| 111757 | // Label 7697: @283891 |
| 111758 | GIM_Reject, |
| 111759 | // Label 7695: @283892 |
| 111760 | GIM_Reject, |
| 111761 | // Label 7656: @283893 |
| 111762 | GIM_Try, /*On fail goto*//*Label 7698*/ GIMT_Encode4(283996), |
| 111763 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 111764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111765 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111766 | GIM_Try, /*On fail goto*//*Label 7699*/ GIMT_Encode4(283952), // Rule ID 59600 // |
| 111767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111768 | // (bswap:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 111769 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 111770 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111771 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111772 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 111774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111775 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111776 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111780 | GIR_RootConstrainSelectedInstOperands, |
| 111781 | // GIR_Coverage, 59600, |
| 111782 | GIR_EraseRootFromParent_Done, |
| 111783 | // Label 7699: @283952 |
| 111784 | GIM_Try, /*On fail goto*//*Label 7700*/ GIMT_Encode4(283995), // Rule ID 59601 // |
| 111785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111786 | // (bswap:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 111787 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 111788 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111789 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111790 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 111792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111793 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111794 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111798 | GIR_RootConstrainSelectedInstOperands, |
| 111799 | // GIR_Coverage, 59601, |
| 111800 | GIR_EraseRootFromParent_Done, |
| 111801 | // Label 7700: @283995 |
| 111802 | GIM_Reject, |
| 111803 | // Label 7698: @283996 |
| 111804 | GIM_Reject, |
| 111805 | // Label 7657: @283997 |
| 111806 | GIM_Try, /*On fail goto*//*Label 7701*/ GIMT_Encode4(284100), |
| 111807 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 111808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111809 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111810 | GIM_Try, /*On fail goto*//*Label 7702*/ GIMT_Encode4(284056), // Rule ID 59622 // |
| 111811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode0), |
| 111812 | // (bswap:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 111813 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 111814 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111815 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 111818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111819 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111820 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111824 | GIR_RootConstrainSelectedInstOperands, |
| 111825 | // GIR_Coverage, 59622, |
| 111826 | GIR_EraseRootFromParent_Done, |
| 111827 | // Label 7702: @284056 |
| 111828 | GIM_Try, /*On fail goto*//*Label 7703*/ GIMT_Encode4(284099), // Rule ID 59623 // |
| 111829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode1), |
| 111830 | // (bswap:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 111831 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 111832 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111833 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111834 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 111836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111837 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111838 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111842 | GIR_RootConstrainSelectedInstOperands, |
| 111843 | // GIR_Coverage, 59623, |
| 111844 | GIR_EraseRootFromParent_Done, |
| 111845 | // Label 7703: @284099 |
| 111846 | GIM_Reject, |
| 111847 | // Label 7701: @284100 |
| 111848 | GIM_Reject, |
| 111849 | // Label 7658: @284101 |
| 111850 | GIM_Try, /*On fail goto*//*Label 7704*/ GIMT_Encode4(284204), |
| 111851 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 111852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111853 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111854 | GIM_Try, /*On fail goto*//*Label 7705*/ GIMT_Encode4(284160), // Rule ID 59588 // |
| 111855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111856 | // (bswap:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVREV8_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 111857 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 111858 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111859 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111860 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF2), |
| 111862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111863 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111864 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111868 | GIR_RootConstrainSelectedInstOperands, |
| 111869 | // GIR_Coverage, 59588, |
| 111870 | GIR_EraseRootFromParent_Done, |
| 111871 | // Label 7705: @284160 |
| 111872 | GIM_Try, /*On fail goto*//*Label 7706*/ GIMT_Encode4(284203), // Rule ID 59589 // |
| 111873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111874 | // (bswap:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVREV8_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 111875 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 111876 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111877 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111878 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_MF2), |
| 111880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111881 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111882 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111886 | GIR_RootConstrainSelectedInstOperands, |
| 111887 | // GIR_Coverage, 59589, |
| 111888 | GIR_EraseRootFromParent_Done, |
| 111889 | // Label 7706: @284203 |
| 111890 | GIM_Reject, |
| 111891 | // Label 7704: @284204 |
| 111892 | GIM_Reject, |
| 111893 | // Label 7659: @284205 |
| 111894 | GIM_Try, /*On fail goto*//*Label 7707*/ GIMT_Encode4(284308), |
| 111895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 111896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111897 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 111898 | GIM_Try, /*On fail goto*//*Label 7708*/ GIMT_Encode4(284264), // Rule ID 59598 // |
| 111899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111900 | // (bswap:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 111901 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 111902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 111906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111907 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111912 | GIR_RootConstrainSelectedInstOperands, |
| 111913 | // GIR_Coverage, 59598, |
| 111914 | GIR_EraseRootFromParent_Done, |
| 111915 | // Label 7708: @284264 |
| 111916 | GIM_Try, /*On fail goto*//*Label 7709*/ GIMT_Encode4(284307), // Rule ID 59599 // |
| 111917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111918 | // (bswap:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 111919 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 111920 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111922 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 111924 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111925 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111926 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 111929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111930 | GIR_RootConstrainSelectedInstOperands, |
| 111931 | // GIR_Coverage, 59599, |
| 111932 | GIR_EraseRootFromParent_Done, |
| 111933 | // Label 7709: @284307 |
| 111934 | GIM_Reject, |
| 111935 | // Label 7707: @284308 |
| 111936 | GIM_Reject, |
| 111937 | // Label 7660: @284309 |
| 111938 | GIM_Try, /*On fail goto*//*Label 7710*/ GIMT_Encode4(284412), |
| 111939 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 111940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111941 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 111942 | GIM_Try, /*On fail goto*//*Label 7711*/ GIMT_Encode4(284368), // Rule ID 59616 // |
| 111943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 111944 | // (bswap:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 111945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 111946 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111947 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 111950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111951 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111952 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111956 | GIR_RootConstrainSelectedInstOperands, |
| 111957 | // GIR_Coverage, 59616, |
| 111958 | GIR_EraseRootFromParent_Done, |
| 111959 | // Label 7711: @284368 |
| 111960 | GIM_Try, /*On fail goto*//*Label 7712*/ GIMT_Encode4(284411), // Rule ID 59617 // |
| 111961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 111962 | // (bswap:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 111963 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 111964 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111965 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111966 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 111968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111969 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111970 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 111973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 111974 | GIR_RootConstrainSelectedInstOperands, |
| 111975 | // GIR_Coverage, 59617, |
| 111976 | GIR_EraseRootFromParent_Done, |
| 111977 | // Label 7712: @284411 |
| 111978 | GIM_Reject, |
| 111979 | // Label 7710: @284412 |
| 111980 | GIM_Reject, |
| 111981 | // Label 7661: @284413 |
| 111982 | GIM_Try, /*On fail goto*//*Label 7713*/ GIMT_Encode4(284516), |
| 111983 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 111984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111985 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 111986 | GIM_Try, /*On fail goto*//*Label 7714*/ GIMT_Encode4(284472), // Rule ID 59624 // |
| 111987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode0), |
| 111988 | // (bswap:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 111989 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 111990 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 111991 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 111992 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 111993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 111994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 111995 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 111996 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 111997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 111998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 111999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112000 | GIR_RootConstrainSelectedInstOperands, |
| 112001 | // GIR_Coverage, 59624, |
| 112002 | GIR_EraseRootFromParent_Done, |
| 112003 | // Label 7714: @284472 |
| 112004 | GIM_Try, /*On fail goto*//*Label 7715*/ GIMT_Encode4(284515), // Rule ID 59625 // |
| 112005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode1), |
| 112006 | // (bswap:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 112007 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 112008 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112009 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112013 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112014 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112018 | GIR_RootConstrainSelectedInstOperands, |
| 112019 | // GIR_Coverage, 59625, |
| 112020 | GIR_EraseRootFromParent_Done, |
| 112021 | // Label 7715: @284515 |
| 112022 | GIM_Reject, |
| 112023 | // Label 7713: @284516 |
| 112024 | GIM_Reject, |
| 112025 | // Label 7662: @284517 |
| 112026 | GIM_Try, /*On fail goto*//*Label 7716*/ GIMT_Encode4(284620), |
| 112027 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 112028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112030 | GIM_Try, /*On fail goto*//*Label 7717*/ GIMT_Encode4(284576), // Rule ID 59596 // |
| 112031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112032 | // (bswap:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112033 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 112034 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112035 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 112038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112039 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112040 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112044 | GIR_RootConstrainSelectedInstOperands, |
| 112045 | // GIR_Coverage, 59596, |
| 112046 | GIR_EraseRootFromParent_Done, |
| 112047 | // Label 7717: @284576 |
| 112048 | GIM_Try, /*On fail goto*//*Label 7718*/ GIMT_Encode4(284619), // Rule ID 59597 // |
| 112049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112050 | // (bswap:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVREV8_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112051 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 112052 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112053 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M1), |
| 112056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112057 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112058 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112062 | GIR_RootConstrainSelectedInstOperands, |
| 112063 | // GIR_Coverage, 59597, |
| 112064 | GIR_EraseRootFromParent_Done, |
| 112065 | // Label 7718: @284619 |
| 112066 | GIM_Reject, |
| 112067 | // Label 7716: @284620 |
| 112068 | GIM_Reject, |
| 112069 | // Label 7663: @284621 |
| 112070 | GIM_Try, /*On fail goto*//*Label 7719*/ GIMT_Encode4(284724), |
| 112071 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 112072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112073 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112074 | GIM_Try, /*On fail goto*//*Label 7720*/ GIMT_Encode4(284680), // Rule ID 59610 // |
| 112075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112076 | // (bswap:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 112077 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 112078 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112079 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 112082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112083 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112084 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112088 | GIR_RootConstrainSelectedInstOperands, |
| 112089 | // GIR_Coverage, 59610, |
| 112090 | GIR_EraseRootFromParent_Done, |
| 112091 | // Label 7720: @284680 |
| 112092 | GIM_Try, /*On fail goto*//*Label 7721*/ GIMT_Encode4(284723), // Rule ID 59611 // |
| 112093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112094 | // (bswap:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 112095 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 112096 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112097 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 112100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112101 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112102 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112106 | GIR_RootConstrainSelectedInstOperands, |
| 112107 | // GIR_Coverage, 59611, |
| 112108 | GIR_EraseRootFromParent_Done, |
| 112109 | // Label 7721: @284723 |
| 112110 | GIM_Reject, |
| 112111 | // Label 7719: @284724 |
| 112112 | GIM_Reject, |
| 112113 | // Label 7664: @284725 |
| 112114 | GIM_Try, /*On fail goto*//*Label 7722*/ GIMT_Encode4(284828), |
| 112115 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 112116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 112117 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 112118 | GIM_Try, /*On fail goto*//*Label 7723*/ GIMT_Encode4(284784), // Rule ID 59618 // |
| 112119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112120 | // (bswap:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 112121 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 112122 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112123 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112124 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112126 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112127 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112128 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112132 | GIR_RootConstrainSelectedInstOperands, |
| 112133 | // GIR_Coverage, 59618, |
| 112134 | GIR_EraseRootFromParent_Done, |
| 112135 | // Label 7723: @284784 |
| 112136 | GIM_Try, /*On fail goto*//*Label 7724*/ GIMT_Encode4(284827), // Rule ID 59619 // |
| 112137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112138 | // (bswap:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 112139 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 112140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112145 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112146 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112150 | GIR_RootConstrainSelectedInstOperands, |
| 112151 | // GIR_Coverage, 59619, |
| 112152 | GIR_EraseRootFromParent_Done, |
| 112153 | // Label 7724: @284827 |
| 112154 | GIM_Reject, |
| 112155 | // Label 7722: @284828 |
| 112156 | GIM_Reject, |
| 112157 | // Label 7665: @284829 |
| 112158 | GIM_Try, /*On fail goto*//*Label 7725*/ GIMT_Encode4(284932), |
| 112159 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 112160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112161 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112162 | GIM_Try, /*On fail goto*//*Label 7726*/ GIMT_Encode4(284888), // Rule ID 59626 // |
| 112163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode0), |
| 112164 | // (bswap:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 112165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 112166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112171 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112172 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112176 | GIR_RootConstrainSelectedInstOperands, |
| 112177 | // GIR_Coverage, 59626, |
| 112178 | GIR_EraseRootFromParent_Done, |
| 112179 | // Label 7726: @284888 |
| 112180 | GIM_Try, /*On fail goto*//*Label 7727*/ GIMT_Encode4(284931), // Rule ID 59627 // |
| 112181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode1), |
| 112182 | // (bswap:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 112183 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 112184 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112185 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112189 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112190 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112194 | GIR_RootConstrainSelectedInstOperands, |
| 112195 | // GIR_Coverage, 59627, |
| 112196 | GIR_EraseRootFromParent_Done, |
| 112197 | // Label 7727: @284931 |
| 112198 | GIM_Reject, |
| 112199 | // Label 7725: @284932 |
| 112200 | GIM_Reject, |
| 112201 | // Label 7666: @284933 |
| 112202 | GIM_Try, /*On fail goto*//*Label 7728*/ GIMT_Encode4(285036), |
| 112203 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 112204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112205 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112206 | GIM_Try, /*On fail goto*//*Label 7729*/ GIMT_Encode4(284992), // Rule ID 59604 // |
| 112207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112208 | // (bswap:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112209 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 112210 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112211 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112212 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 112214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112215 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112216 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112220 | GIR_RootConstrainSelectedInstOperands, |
| 112221 | // GIR_Coverage, 59604, |
| 112222 | GIR_EraseRootFromParent_Done, |
| 112223 | // Label 7729: @284992 |
| 112224 | GIM_Try, /*On fail goto*//*Label 7730*/ GIMT_Encode4(285035), // Rule ID 59605 // |
| 112225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112226 | // (bswap:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVREV8_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112227 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 112228 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112229 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M2), |
| 112232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112233 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112234 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112238 | GIR_RootConstrainSelectedInstOperands, |
| 112239 | // GIR_Coverage, 59605, |
| 112240 | GIR_EraseRootFromParent_Done, |
| 112241 | // Label 7730: @285035 |
| 112242 | GIM_Reject, |
| 112243 | // Label 7728: @285036 |
| 112244 | GIM_Reject, |
| 112245 | // Label 7667: @285037 |
| 112246 | GIM_Try, /*On fail goto*//*Label 7731*/ GIMT_Encode4(285140), |
| 112247 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 112248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 112249 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 112250 | GIM_Try, /*On fail goto*//*Label 7732*/ GIMT_Encode4(285096), // Rule ID 59612 // |
| 112251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112252 | // (bswap:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 112253 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 112254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112255 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112260 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112264 | GIR_RootConstrainSelectedInstOperands, |
| 112265 | // GIR_Coverage, 59612, |
| 112266 | GIR_EraseRootFromParent_Done, |
| 112267 | // Label 7732: @285096 |
| 112268 | GIM_Try, /*On fail goto*//*Label 7733*/ GIMT_Encode4(285139), // Rule ID 59613 // |
| 112269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112270 | // (bswap:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 112271 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 112272 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112273 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112274 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112277 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112278 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112282 | GIR_RootConstrainSelectedInstOperands, |
| 112283 | // GIR_Coverage, 59613, |
| 112284 | GIR_EraseRootFromParent_Done, |
| 112285 | // Label 7733: @285139 |
| 112286 | GIM_Reject, |
| 112287 | // Label 7731: @285140 |
| 112288 | GIM_Reject, |
| 112289 | // Label 7668: @285141 |
| 112290 | GIM_Try, /*On fail goto*//*Label 7734*/ GIMT_Encode4(285244), |
| 112291 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 112292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112293 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112294 | GIM_Try, /*On fail goto*//*Label 7735*/ GIMT_Encode4(285200), // Rule ID 59620 // |
| 112295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112296 | // (bswap:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 112297 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 112298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112299 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112300 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112303 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112304 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112308 | GIR_RootConstrainSelectedInstOperands, |
| 112309 | // GIR_Coverage, 59620, |
| 112310 | GIR_EraseRootFromParent_Done, |
| 112311 | // Label 7735: @285200 |
| 112312 | GIM_Try, /*On fail goto*//*Label 7736*/ GIMT_Encode4(285243), // Rule ID 59621 // |
| 112313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112314 | // (bswap:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 112315 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 112316 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112317 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112321 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112322 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112326 | GIR_RootConstrainSelectedInstOperands, |
| 112327 | // GIR_Coverage, 59621, |
| 112328 | GIR_EraseRootFromParent_Done, |
| 112329 | // Label 7736: @285243 |
| 112330 | GIM_Reject, |
| 112331 | // Label 7734: @285244 |
| 112332 | GIM_Reject, |
| 112333 | // Label 7669: @285245 |
| 112334 | GIM_Try, /*On fail goto*//*Label 7737*/ GIMT_Encode4(285348), |
| 112335 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 112336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 112337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 112338 | GIM_Try, /*On fail goto*//*Label 7738*/ GIMT_Encode4(285304), // Rule ID 59606 // |
| 112339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112340 | // (bswap:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112341 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 112342 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112343 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112347 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112348 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112352 | GIR_RootConstrainSelectedInstOperands, |
| 112353 | // GIR_Coverage, 59606, |
| 112354 | GIR_EraseRootFromParent_Done, |
| 112355 | // Label 7738: @285304 |
| 112356 | GIM_Try, /*On fail goto*//*Label 7739*/ GIMT_Encode4(285347), // Rule ID 59607 // |
| 112357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112358 | // (bswap:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVREV8_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112359 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 112360 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112361 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M4), |
| 112364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112365 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112366 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112370 | GIR_RootConstrainSelectedInstOperands, |
| 112371 | // GIR_Coverage, 59607, |
| 112372 | GIR_EraseRootFromParent_Done, |
| 112373 | // Label 7739: @285347 |
| 112374 | GIM_Reject, |
| 112375 | // Label 7737: @285348 |
| 112376 | GIM_Reject, |
| 112377 | // Label 7670: @285349 |
| 112378 | GIM_Try, /*On fail goto*//*Label 7740*/ GIMT_Encode4(285452), |
| 112379 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 112380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112382 | GIM_Try, /*On fail goto*//*Label 7741*/ GIMT_Encode4(285408), // Rule ID 59614 // |
| 112383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112384 | // (bswap:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 112385 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 112386 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112391 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112392 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112396 | GIR_RootConstrainSelectedInstOperands, |
| 112397 | // GIR_Coverage, 59614, |
| 112398 | GIR_EraseRootFromParent_Done, |
| 112399 | // Label 7741: @285408 |
| 112400 | GIM_Try, /*On fail goto*//*Label 7742*/ GIMT_Encode4(285451), // Rule ID 59615 // |
| 112401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112402 | // (bswap:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 112403 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 112404 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112405 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112406 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112409 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112410 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112414 | GIR_RootConstrainSelectedInstOperands, |
| 112415 | // GIR_Coverage, 59615, |
| 112416 | GIR_EraseRootFromParent_Done, |
| 112417 | // Label 7742: @285451 |
| 112418 | GIM_Reject, |
| 112419 | // Label 7740: @285452 |
| 112420 | GIM_Reject, |
| 112421 | // Label 7671: @285453 |
| 112422 | GIM_Try, /*On fail goto*//*Label 7743*/ GIMT_Encode4(285556), |
| 112423 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 112424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112425 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 112426 | GIM_Try, /*On fail goto*//*Label 7744*/ GIMT_Encode4(285512), // Rule ID 59608 // |
| 112427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0), |
| 112428 | // (bswap:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112429 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 112430 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112431 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112435 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112436 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112440 | GIR_RootConstrainSelectedInstOperands, |
| 112441 | // GIR_Coverage, 59608, |
| 112442 | GIR_EraseRootFromParent_Done, |
| 112443 | // Label 7744: @285512 |
| 112444 | GIM_Try, /*On fail goto*//*Label 7745*/ GIMT_Encode4(285555), // Rule ID 59609 // |
| 112445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1), |
| 112446 | // (bswap:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVREV8_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 112448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112449 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112450 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREV8_V_M8), |
| 112452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112453 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112454 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112458 | GIR_RootConstrainSelectedInstOperands, |
| 112459 | // GIR_Coverage, 59609, |
| 112460 | GIR_EraseRootFromParent_Done, |
| 112461 | // Label 7745: @285555 |
| 112462 | GIM_Reject, |
| 112463 | // Label 7743: @285556 |
| 112464 | GIM_Reject, |
| 112465 | // Label 7672: @285557 |
| 112466 | GIM_Reject, |
| 112467 | // Label 83: @285558 |
| 112468 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 7770*/ GIMT_Encode4(288051), |
| 112469 | /*GILLT_s32*//*Label 7746*/ GIMT_Encode4(285693), |
| 112470 | /*GILLT_s64*//*Label 7747*/ GIMT_Encode4(285728), GIMT_Encode4(0), |
| 112471 | /*GILLT_nxv1s8*//*Label 7748*/ GIMT_Encode4(285763), |
| 112472 | /*GILLT_nxv1s16*//*Label 7749*/ GIMT_Encode4(285867), |
| 112473 | /*GILLT_nxv1s32*//*Label 7750*/ GIMT_Encode4(285971), |
| 112474 | /*GILLT_nxv1s64*//*Label 7751*/ GIMT_Encode4(286075), GIMT_Encode4(0), |
| 112475 | /*GILLT_nxv2s8*//*Label 7752*/ GIMT_Encode4(286179), |
| 112476 | /*GILLT_nxv2s16*//*Label 7753*/ GIMT_Encode4(286283), |
| 112477 | /*GILLT_nxv2s32*//*Label 7754*/ GIMT_Encode4(286387), |
| 112478 | /*GILLT_nxv2s64*//*Label 7755*/ GIMT_Encode4(286491), GIMT_Encode4(0), |
| 112479 | /*GILLT_nxv4s8*//*Label 7756*/ GIMT_Encode4(286595), |
| 112480 | /*GILLT_nxv4s16*//*Label 7757*/ GIMT_Encode4(286699), |
| 112481 | /*GILLT_nxv4s32*//*Label 7758*/ GIMT_Encode4(286803), |
| 112482 | /*GILLT_nxv4s64*//*Label 7759*/ GIMT_Encode4(286907), GIMT_Encode4(0), |
| 112483 | /*GILLT_nxv8s8*//*Label 7760*/ GIMT_Encode4(287011), |
| 112484 | /*GILLT_nxv8s16*//*Label 7761*/ GIMT_Encode4(287115), |
| 112485 | /*GILLT_nxv8s32*//*Label 7762*/ GIMT_Encode4(287219), |
| 112486 | /*GILLT_nxv8s64*//*Label 7763*/ GIMT_Encode4(287323), GIMT_Encode4(0), |
| 112487 | /*GILLT_nxv16s8*//*Label 7764*/ GIMT_Encode4(287427), |
| 112488 | /*GILLT_nxv16s16*//*Label 7765*/ GIMT_Encode4(287531), |
| 112489 | /*GILLT_nxv16s32*//*Label 7766*/ GIMT_Encode4(287635), GIMT_Encode4(0), |
| 112490 | /*GILLT_nxv32s8*//*Label 7767*/ GIMT_Encode4(287739), |
| 112491 | /*GILLT_nxv32s16*//*Label 7768*/ GIMT_Encode4(287843), GIMT_Encode4(0), |
| 112492 | /*GILLT_nxv64s8*//*Label 7769*/ GIMT_Encode4(287947), |
| 112493 | // Label 7746: @285693 |
| 112494 | GIM_Try, /*On fail goto*//*Label 7771*/ GIMT_Encode4(285727), // Rule ID 64967 // |
| 112495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1), |
| 112496 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 112497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 112498 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 112499 | // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$rs) => (CV_BITREV:{ *:[i32] } GPR:{ *:[i32] }:$rs, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 112500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_BITREV), |
| 112501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112502 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 112503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112505 | GIR_RootConstrainSelectedInstOperands, |
| 112506 | // GIR_Coverage, 64967, |
| 112507 | GIR_EraseRootFromParent_Done, |
| 112508 | // Label 7771: @285727 |
| 112509 | GIM_Reject, |
| 112510 | // Label 7747: @285728 |
| 112511 | GIM_Try, /*On fail goto*//*Label 7772*/ GIMT_Encode4(285762), // Rule ID 64966 // |
| 112512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0), |
| 112513 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 112514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 112515 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 112516 | // (bitreverse:{ *:[i64] } GPR:{ *:[i64] }:$rs) => (CV_BITREV:{ *:[i64] } GPR:{ *:[i64] }:$rs, 0:{ *:[i64] }, 0:{ *:[i64] }) |
| 112517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_BITREV), |
| 112518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 112520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112522 | GIR_RootConstrainSelectedInstOperands, |
| 112523 | // GIR_Coverage, 64966, |
| 112524 | GIR_EraseRootFromParent_Done, |
| 112525 | // Label 7772: @285762 |
| 112526 | GIM_Reject, |
| 112527 | // Label 7748: @285763 |
| 112528 | GIM_Try, /*On fail goto*//*Label 7773*/ GIMT_Encode4(285866), |
| 112529 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, |
| 112530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112531 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112532 | GIM_Try, /*On fail goto*//*Label 7774*/ GIMT_Encode4(285822), // Rule ID 59452 // |
| 112533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112534 | // (bitreverse:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVBREV_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112535 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 112536 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112537 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112538 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF8), |
| 112540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112541 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112542 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112546 | GIR_RootConstrainSelectedInstOperands, |
| 112547 | // GIR_Coverage, 59452, |
| 112548 | GIR_EraseRootFromParent_Done, |
| 112549 | // Label 7774: @285822 |
| 112550 | GIM_Try, /*On fail goto*//*Label 7775*/ GIMT_Encode4(285865), // Rule ID 59453 // |
| 112551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112552 | // (bitreverse:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1) => (PseudoVBREV_V_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112553 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, |
| 112554 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112555 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF8), |
| 112558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112559 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112560 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112564 | GIR_RootConstrainSelectedInstOperands, |
| 112565 | // GIR_Coverage, 59453, |
| 112566 | GIR_EraseRootFromParent_Done, |
| 112567 | // Label 7775: @285865 |
| 112568 | GIM_Reject, |
| 112569 | // Label 7773: @285866 |
| 112570 | GIM_Reject, |
| 112571 | // Label 7749: @285867 |
| 112572 | GIM_Try, /*On fail goto*//*Label 7776*/ GIMT_Encode4(285970), |
| 112573 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 112574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112575 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112576 | GIM_Try, /*On fail goto*//*Label 7777*/ GIMT_Encode4(285926), // Rule ID 59546 // |
| 112577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112578 | // (bitreverse:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVBREV_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 112579 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 112580 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112581 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112582 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF4), |
| 112584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112585 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112586 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112590 | GIR_RootConstrainSelectedInstOperands, |
| 112591 | // GIR_Coverage, 59546, |
| 112592 | GIR_EraseRootFromParent_Done, |
| 112593 | // Label 7777: @285926 |
| 112594 | GIM_Try, /*On fail goto*//*Label 7778*/ GIMT_Encode4(285969), // Rule ID 59547 // |
| 112595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112596 | // (bitreverse:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1) => (PseudoVBREV_V_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 112597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 112598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112600 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF4), |
| 112602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112604 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112608 | GIR_RootConstrainSelectedInstOperands, |
| 112609 | // GIR_Coverage, 59547, |
| 112610 | GIR_EraseRootFromParent_Done, |
| 112611 | // Label 7778: @285969 |
| 112612 | GIM_Reject, |
| 112613 | // Label 7776: @285970 |
| 112614 | GIM_Reject, |
| 112615 | // Label 7750: @285971 |
| 112616 | GIM_Try, /*On fail goto*//*Label 7779*/ GIMT_Encode4(286074), |
| 112617 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 112618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112619 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112620 | GIM_Try, /*On fail goto*//*Label 7780*/ GIMT_Encode4(286030), // Rule ID 59550 // |
| 112621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112622 | // (bitreverse:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVBREV_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 112623 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 112624 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112625 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF2), |
| 112628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112629 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112630 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112634 | GIR_RootConstrainSelectedInstOperands, |
| 112635 | // GIR_Coverage, 59550, |
| 112636 | GIR_EraseRootFromParent_Done, |
| 112637 | // Label 7780: @286030 |
| 112638 | GIM_Try, /*On fail goto*//*Label 7781*/ GIMT_Encode4(286073), // Rule ID 59551 // |
| 112639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112640 | // (bitreverse:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1) => (PseudoVBREV_V_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 112641 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 112642 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112643 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112644 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF2), |
| 112646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112647 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112648 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112652 | GIR_RootConstrainSelectedInstOperands, |
| 112653 | // GIR_Coverage, 59551, |
| 112654 | GIR_EraseRootFromParent_Done, |
| 112655 | // Label 7781: @286073 |
| 112656 | GIM_Reject, |
| 112657 | // Label 7779: @286074 |
| 112658 | GIM_Reject, |
| 112659 | // Label 7751: @286075 |
| 112660 | GIM_Try, /*On fail goto*//*Label 7782*/ GIMT_Encode4(286178), |
| 112661 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 112662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112664 | GIM_Try, /*On fail goto*//*Label 7783*/ GIMT_Encode4(286134), // Rule ID 59558 // |
| 112665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 112666 | // (bitreverse:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 112667 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 112668 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112669 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112670 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 112672 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112673 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112674 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112678 | GIR_RootConstrainSelectedInstOperands, |
| 112679 | // GIR_Coverage, 59558, |
| 112680 | GIR_EraseRootFromParent_Done, |
| 112681 | // Label 7783: @286134 |
| 112682 | GIM_Try, /*On fail goto*//*Label 7784*/ GIMT_Encode4(286177), // Rule ID 59559 // |
| 112683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 112684 | // (bitreverse:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 112685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 112686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 112690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112691 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112692 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112696 | GIR_RootConstrainSelectedInstOperands, |
| 112697 | // GIR_Coverage, 59559, |
| 112698 | GIR_EraseRootFromParent_Done, |
| 112699 | // Label 7784: @286177 |
| 112700 | GIM_Reject, |
| 112701 | // Label 7782: @286178 |
| 112702 | GIM_Reject, |
| 112703 | // Label 7752: @286179 |
| 112704 | GIM_Try, /*On fail goto*//*Label 7785*/ GIMT_Encode4(286282), |
| 112705 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, |
| 112706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112708 | GIM_Try, /*On fail goto*//*Label 7786*/ GIMT_Encode4(286238), // Rule ID 59542 // |
| 112709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112710 | // (bitreverse:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVBREV_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112711 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 112712 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112713 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112714 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF4), |
| 112716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112717 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112718 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112722 | GIR_RootConstrainSelectedInstOperands, |
| 112723 | // GIR_Coverage, 59542, |
| 112724 | GIR_EraseRootFromParent_Done, |
| 112725 | // Label 7786: @286238 |
| 112726 | GIM_Try, /*On fail goto*//*Label 7787*/ GIMT_Encode4(286281), // Rule ID 59543 // |
| 112727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112728 | // (bitreverse:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1) => (PseudoVBREV_V_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112729 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, |
| 112730 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112731 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112732 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF4), |
| 112734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112735 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112736 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112740 | GIR_RootConstrainSelectedInstOperands, |
| 112741 | // GIR_Coverage, 59543, |
| 112742 | GIR_EraseRootFromParent_Done, |
| 112743 | // Label 7787: @286281 |
| 112744 | GIM_Reject, |
| 112745 | // Label 7785: @286282 |
| 112746 | GIM_Reject, |
| 112747 | // Label 7753: @286283 |
| 112748 | GIM_Try, /*On fail goto*//*Label 7788*/ GIMT_Encode4(286386), |
| 112749 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 112750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112752 | GIM_Try, /*On fail goto*//*Label 7789*/ GIMT_Encode4(286342), // Rule ID 59548 // |
| 112753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112754 | // (bitreverse:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVBREV_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 112755 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 112756 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112757 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF2), |
| 112760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112761 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112762 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112766 | GIR_RootConstrainSelectedInstOperands, |
| 112767 | // GIR_Coverage, 59548, |
| 112768 | GIR_EraseRootFromParent_Done, |
| 112769 | // Label 7789: @286342 |
| 112770 | GIM_Try, /*On fail goto*//*Label 7790*/ GIMT_Encode4(286385), // Rule ID 59549 // |
| 112771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112772 | // (bitreverse:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1) => (PseudoVBREV_V_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 112773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 112774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF2), |
| 112778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112784 | GIR_RootConstrainSelectedInstOperands, |
| 112785 | // GIR_Coverage, 59549, |
| 112786 | GIR_EraseRootFromParent_Done, |
| 112787 | // Label 7790: @286385 |
| 112788 | GIM_Reject, |
| 112789 | // Label 7788: @286386 |
| 112790 | GIM_Reject, |
| 112791 | // Label 7754: @286387 |
| 112792 | GIM_Try, /*On fail goto*//*Label 7791*/ GIMT_Encode4(286490), |
| 112793 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 112794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112795 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112796 | GIM_Try, /*On fail goto*//*Label 7792*/ GIMT_Encode4(286446), // Rule ID 59556 // |
| 112797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112798 | // (bitreverse:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 112799 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 112800 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112801 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112802 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112803 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 112804 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112805 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112806 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112810 | GIR_RootConstrainSelectedInstOperands, |
| 112811 | // GIR_Coverage, 59556, |
| 112812 | GIR_EraseRootFromParent_Done, |
| 112813 | // Label 7792: @286446 |
| 112814 | GIM_Try, /*On fail goto*//*Label 7793*/ GIMT_Encode4(286489), // Rule ID 59557 // |
| 112815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112816 | // (bitreverse:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 112817 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 112818 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112819 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 112822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112823 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112824 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112828 | GIR_RootConstrainSelectedInstOperands, |
| 112829 | // GIR_Coverage, 59557, |
| 112830 | GIR_EraseRootFromParent_Done, |
| 112831 | // Label 7793: @286489 |
| 112832 | GIM_Reject, |
| 112833 | // Label 7791: @286490 |
| 112834 | GIM_Reject, |
| 112835 | // Label 7755: @286491 |
| 112836 | GIM_Try, /*On fail goto*//*Label 7794*/ GIMT_Encode4(286594), |
| 112837 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 112838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112839 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112840 | GIM_Try, /*On fail goto*//*Label 7795*/ GIMT_Encode4(286550), // Rule ID 59578 // |
| 112841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 112842 | // (bitreverse:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 112843 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 112844 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112845 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 112848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112849 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112850 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112854 | GIR_RootConstrainSelectedInstOperands, |
| 112855 | // GIR_Coverage, 59578, |
| 112856 | GIR_EraseRootFromParent_Done, |
| 112857 | // Label 7795: @286550 |
| 112858 | GIM_Try, /*On fail goto*//*Label 7796*/ GIMT_Encode4(286593), // Rule ID 59579 // |
| 112859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 112860 | // (bitreverse:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 112861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 112862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112864 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 112866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112868 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 112871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112872 | GIR_RootConstrainSelectedInstOperands, |
| 112873 | // GIR_Coverage, 59579, |
| 112874 | GIR_EraseRootFromParent_Done, |
| 112875 | // Label 7796: @286593 |
| 112876 | GIM_Reject, |
| 112877 | // Label 7794: @286594 |
| 112878 | GIM_Reject, |
| 112879 | // Label 7756: @286595 |
| 112880 | GIM_Try, /*On fail goto*//*Label 7797*/ GIMT_Encode4(286698), |
| 112881 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, |
| 112882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112883 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112884 | GIM_Try, /*On fail goto*//*Label 7798*/ GIMT_Encode4(286654), // Rule ID 59544 // |
| 112885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112886 | // (bitreverse:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVBREV_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 112887 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 112888 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112889 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF2), |
| 112892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112893 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112894 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112898 | GIR_RootConstrainSelectedInstOperands, |
| 112899 | // GIR_Coverage, 59544, |
| 112900 | GIR_EraseRootFromParent_Done, |
| 112901 | // Label 7798: @286654 |
| 112902 | GIM_Try, /*On fail goto*//*Label 7799*/ GIMT_Encode4(286697), // Rule ID 59545 // |
| 112903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112904 | // (bitreverse:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1) => (PseudoVBREV_V_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 112905 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, |
| 112906 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112907 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_MF2), |
| 112910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112912 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112916 | GIR_RootConstrainSelectedInstOperands, |
| 112917 | // GIR_Coverage, 59545, |
| 112918 | GIR_EraseRootFromParent_Done, |
| 112919 | // Label 7799: @286697 |
| 112920 | GIM_Reject, |
| 112921 | // Label 7797: @286698 |
| 112922 | GIM_Reject, |
| 112923 | // Label 7757: @286699 |
| 112924 | GIM_Try, /*On fail goto*//*Label 7800*/ GIMT_Encode4(286802), |
| 112925 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 112926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112927 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 112928 | GIM_Try, /*On fail goto*//*Label 7801*/ GIMT_Encode4(286758), // Rule ID 59554 // |
| 112929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112930 | // (bitreverse:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 112931 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 112932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112933 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 112936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112938 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112942 | GIR_RootConstrainSelectedInstOperands, |
| 112943 | // GIR_Coverage, 59554, |
| 112944 | GIR_EraseRootFromParent_Done, |
| 112945 | // Label 7801: @286758 |
| 112946 | GIM_Try, /*On fail goto*//*Label 7802*/ GIMT_Encode4(286801), // Rule ID 59555 // |
| 112947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112948 | // (bitreverse:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 112949 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 112950 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112951 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 112954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112955 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112956 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 112959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112960 | GIR_RootConstrainSelectedInstOperands, |
| 112961 | // GIR_Coverage, 59555, |
| 112962 | GIR_EraseRootFromParent_Done, |
| 112963 | // Label 7802: @286801 |
| 112964 | GIM_Reject, |
| 112965 | // Label 7800: @286802 |
| 112966 | GIM_Reject, |
| 112967 | // Label 7758: @286803 |
| 112968 | GIM_Try, /*On fail goto*//*Label 7803*/ GIMT_Encode4(286906), |
| 112969 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 112970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112971 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 112972 | GIM_Try, /*On fail goto*//*Label 7804*/ GIMT_Encode4(286862), // Rule ID 59572 // |
| 112973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 112974 | // (bitreverse:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 112975 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 112976 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112977 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 112980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 112982 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 112983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 112984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 112985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 112986 | GIR_RootConstrainSelectedInstOperands, |
| 112987 | // GIR_Coverage, 59572, |
| 112988 | GIR_EraseRootFromParent_Done, |
| 112989 | // Label 7804: @286862 |
| 112990 | GIM_Try, /*On fail goto*//*Label 7805*/ GIMT_Encode4(286905), // Rule ID 59573 // |
| 112991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 112992 | // (bitreverse:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 112993 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 112994 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 112995 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 112996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 112997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 112998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 112999 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113000 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113004 | GIR_RootConstrainSelectedInstOperands, |
| 113005 | // GIR_Coverage, 59573, |
| 113006 | GIR_EraseRootFromParent_Done, |
| 113007 | // Label 7805: @286905 |
| 113008 | GIM_Reject, |
| 113009 | // Label 7803: @286906 |
| 113010 | GIM_Reject, |
| 113011 | // Label 7759: @286907 |
| 113012 | GIM_Try, /*On fail goto*//*Label 7806*/ GIMT_Encode4(287010), |
| 113013 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 113014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113015 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113016 | GIM_Try, /*On fail goto*//*Label 7807*/ GIMT_Encode4(286966), // Rule ID 59580 // |
| 113017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 113018 | // (bitreverse:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 113019 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 113020 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113021 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113022 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113025 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113026 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 113029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113030 | GIR_RootConstrainSelectedInstOperands, |
| 113031 | // GIR_Coverage, 59580, |
| 113032 | GIR_EraseRootFromParent_Done, |
| 113033 | // Label 7807: @286966 |
| 113034 | GIM_Try, /*On fail goto*//*Label 7808*/ GIMT_Encode4(287009), // Rule ID 59581 // |
| 113035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 113036 | // (bitreverse:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 113037 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 113038 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113039 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113043 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113044 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 113047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113048 | GIR_RootConstrainSelectedInstOperands, |
| 113049 | // GIR_Coverage, 59581, |
| 113050 | GIR_EraseRootFromParent_Done, |
| 113051 | // Label 7808: @287009 |
| 113052 | GIM_Reject, |
| 113053 | // Label 7806: @287010 |
| 113054 | GIM_Reject, |
| 113055 | // Label 7760: @287011 |
| 113056 | GIM_Try, /*On fail goto*//*Label 7809*/ GIMT_Encode4(287114), |
| 113057 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, |
| 113058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113059 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113060 | GIM_Try, /*On fail goto*//*Label 7810*/ GIMT_Encode4(287070), // Rule ID 59552 // |
| 113061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113062 | // (bitreverse:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 113063 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 113064 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113065 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113066 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 113068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113069 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113070 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113074 | GIR_RootConstrainSelectedInstOperands, |
| 113075 | // GIR_Coverage, 59552, |
| 113076 | GIR_EraseRootFromParent_Done, |
| 113077 | // Label 7810: @287070 |
| 113078 | GIM_Try, /*On fail goto*//*Label 7811*/ GIMT_Encode4(287113), // Rule ID 59553 // |
| 113079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113080 | // (bitreverse:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1) => (PseudoVBREV_V_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 113081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, |
| 113082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M1), |
| 113086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113087 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113088 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113092 | GIR_RootConstrainSelectedInstOperands, |
| 113093 | // GIR_Coverage, 59553, |
| 113094 | GIR_EraseRootFromParent_Done, |
| 113095 | // Label 7811: @287113 |
| 113096 | GIM_Reject, |
| 113097 | // Label 7809: @287114 |
| 113098 | GIM_Reject, |
| 113099 | // Label 7761: @287115 |
| 113100 | GIM_Try, /*On fail goto*//*Label 7812*/ GIMT_Encode4(287218), |
| 113101 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 113102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 113103 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 113104 | GIM_Try, /*On fail goto*//*Label 7813*/ GIMT_Encode4(287174), // Rule ID 59566 // |
| 113105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113106 | // (bitreverse:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 113107 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 113108 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113109 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 113112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113113 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113114 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113118 | GIR_RootConstrainSelectedInstOperands, |
| 113119 | // GIR_Coverage, 59566, |
| 113120 | GIR_EraseRootFromParent_Done, |
| 113121 | // Label 7813: @287174 |
| 113122 | GIM_Try, /*On fail goto*//*Label 7814*/ GIMT_Encode4(287217), // Rule ID 59567 // |
| 113123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113124 | // (bitreverse:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 113125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 113126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 113130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113131 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113132 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113136 | GIR_RootConstrainSelectedInstOperands, |
| 113137 | // GIR_Coverage, 59567, |
| 113138 | GIR_EraseRootFromParent_Done, |
| 113139 | // Label 7814: @287217 |
| 113140 | GIM_Reject, |
| 113141 | // Label 7812: @287218 |
| 113142 | GIM_Reject, |
| 113143 | // Label 7762: @287219 |
| 113144 | GIM_Try, /*On fail goto*//*Label 7815*/ GIMT_Encode4(287322), |
| 113145 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 113146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113147 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113148 | GIM_Try, /*On fail goto*//*Label 7816*/ GIMT_Encode4(287278), // Rule ID 59574 // |
| 113149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113150 | // (bitreverse:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 113151 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 113152 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113153 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113154 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113157 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113158 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113162 | GIR_RootConstrainSelectedInstOperands, |
| 113163 | // GIR_Coverage, 59574, |
| 113164 | GIR_EraseRootFromParent_Done, |
| 113165 | // Label 7816: @287278 |
| 113166 | GIM_Try, /*On fail goto*//*Label 7817*/ GIMT_Encode4(287321), // Rule ID 59575 // |
| 113167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113168 | // (bitreverse:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 113169 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 113170 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113171 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113175 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113176 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113180 | GIR_RootConstrainSelectedInstOperands, |
| 113181 | // GIR_Coverage, 59575, |
| 113182 | GIR_EraseRootFromParent_Done, |
| 113183 | // Label 7817: @287321 |
| 113184 | GIM_Reject, |
| 113185 | // Label 7815: @287322 |
| 113186 | GIM_Reject, |
| 113187 | // Label 7763: @287323 |
| 113188 | GIM_Try, /*On fail goto*//*Label 7818*/ GIMT_Encode4(287426), |
| 113189 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 113190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113191 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113192 | GIM_Try, /*On fail goto*//*Label 7819*/ GIMT_Encode4(287382), // Rule ID 59582 // |
| 113193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0), |
| 113194 | // (bitreverse:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 113195 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 113196 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113197 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113198 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113201 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113202 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 113205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113206 | GIR_RootConstrainSelectedInstOperands, |
| 113207 | // GIR_Coverage, 59582, |
| 113208 | GIR_EraseRootFromParent_Done, |
| 113209 | // Label 7819: @287382 |
| 113210 | GIM_Try, /*On fail goto*//*Label 7820*/ GIMT_Encode4(287425), // Rule ID 59583 // |
| 113211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1), |
| 113212 | // (bitreverse:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 113213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 113214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113219 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113220 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 113223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113224 | GIR_RootConstrainSelectedInstOperands, |
| 113225 | // GIR_Coverage, 59583, |
| 113226 | GIR_EraseRootFromParent_Done, |
| 113227 | // Label 7820: @287425 |
| 113228 | GIM_Reject, |
| 113229 | // Label 7818: @287426 |
| 113230 | GIM_Reject, |
| 113231 | // Label 7764: @287427 |
| 113232 | GIM_Try, /*On fail goto*//*Label 7821*/ GIMT_Encode4(287530), |
| 113233 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, |
| 113234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 113235 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 113236 | GIM_Try, /*On fail goto*//*Label 7822*/ GIMT_Encode4(287486), // Rule ID 59560 // |
| 113237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113238 | // (bitreverse:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 113239 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 113240 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113241 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 113244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113246 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113250 | GIR_RootConstrainSelectedInstOperands, |
| 113251 | // GIR_Coverage, 59560, |
| 113252 | GIR_EraseRootFromParent_Done, |
| 113253 | // Label 7822: @287486 |
| 113254 | GIM_Try, /*On fail goto*//*Label 7823*/ GIMT_Encode4(287529), // Rule ID 59561 // |
| 113255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113256 | // (bitreverse:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1) => (PseudoVBREV_V_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 113257 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, |
| 113258 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113259 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M2), |
| 113262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113263 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113264 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113268 | GIR_RootConstrainSelectedInstOperands, |
| 113269 | // GIR_Coverage, 59561, |
| 113270 | GIR_EraseRootFromParent_Done, |
| 113271 | // Label 7823: @287529 |
| 113272 | GIM_Reject, |
| 113273 | // Label 7821: @287530 |
| 113274 | GIM_Reject, |
| 113275 | // Label 7765: @287531 |
| 113276 | GIM_Try, /*On fail goto*//*Label 7824*/ GIMT_Encode4(287634), |
| 113277 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 113278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113279 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113280 | GIM_Try, /*On fail goto*//*Label 7825*/ GIMT_Encode4(287590), // Rule ID 59568 // |
| 113281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113282 | // (bitreverse:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 113283 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 113284 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113285 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113289 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113290 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113294 | GIR_RootConstrainSelectedInstOperands, |
| 113295 | // GIR_Coverage, 59568, |
| 113296 | GIR_EraseRootFromParent_Done, |
| 113297 | // Label 7825: @287590 |
| 113298 | GIM_Try, /*On fail goto*//*Label 7826*/ GIMT_Encode4(287633), // Rule ID 59569 // |
| 113299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113300 | // (bitreverse:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 113301 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 113302 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113303 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113307 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113308 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113312 | GIR_RootConstrainSelectedInstOperands, |
| 113313 | // GIR_Coverage, 59569, |
| 113314 | GIR_EraseRootFromParent_Done, |
| 113315 | // Label 7826: @287633 |
| 113316 | GIM_Reject, |
| 113317 | // Label 7824: @287634 |
| 113318 | GIM_Reject, |
| 113319 | // Label 7766: @287635 |
| 113320 | GIM_Try, /*On fail goto*//*Label 7827*/ GIMT_Encode4(287738), |
| 113321 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 113322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113323 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113324 | GIM_Try, /*On fail goto*//*Label 7828*/ GIMT_Encode4(287694), // Rule ID 59576 // |
| 113325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113326 | // (bitreverse:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 113327 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 113328 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113329 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113330 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113333 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113334 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113338 | GIR_RootConstrainSelectedInstOperands, |
| 113339 | // GIR_Coverage, 59576, |
| 113340 | GIR_EraseRootFromParent_Done, |
| 113341 | // Label 7828: @287694 |
| 113342 | GIM_Try, /*On fail goto*//*Label 7829*/ GIMT_Encode4(287737), // Rule ID 59577 // |
| 113343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113344 | // (bitreverse:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 113345 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 113346 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113347 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113349 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113350 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113351 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113352 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113356 | GIR_RootConstrainSelectedInstOperands, |
| 113357 | // GIR_Coverage, 59577, |
| 113358 | GIR_EraseRootFromParent_Done, |
| 113359 | // Label 7829: @287737 |
| 113360 | GIM_Reject, |
| 113361 | // Label 7827: @287738 |
| 113362 | GIM_Reject, |
| 113363 | // Label 7767: @287739 |
| 113364 | GIM_Try, /*On fail goto*//*Label 7830*/ GIMT_Encode4(287842), |
| 113365 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, |
| 113366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113367 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 113368 | GIM_Try, /*On fail goto*//*Label 7831*/ GIMT_Encode4(287798), // Rule ID 59562 // |
| 113369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113370 | // (bitreverse:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 113371 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 113372 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113373 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113377 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113378 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113382 | GIR_RootConstrainSelectedInstOperands, |
| 113383 | // GIR_Coverage, 59562, |
| 113384 | GIR_EraseRootFromParent_Done, |
| 113385 | // Label 7831: @287798 |
| 113386 | GIM_Try, /*On fail goto*//*Label 7832*/ GIMT_Encode4(287841), // Rule ID 59563 // |
| 113387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113388 | // (bitreverse:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1) => (PseudoVBREV_V_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 113389 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, |
| 113390 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113391 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113392 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M4), |
| 113394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113395 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113396 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113400 | GIR_RootConstrainSelectedInstOperands, |
| 113401 | // GIR_Coverage, 59563, |
| 113402 | GIR_EraseRootFromParent_Done, |
| 113403 | // Label 7832: @287841 |
| 113404 | GIM_Reject, |
| 113405 | // Label 7830: @287842 |
| 113406 | GIM_Reject, |
| 113407 | // Label 7768: @287843 |
| 113408 | GIM_Try, /*On fail goto*//*Label 7833*/ GIMT_Encode4(287946), |
| 113409 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 113410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113411 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113412 | GIM_Try, /*On fail goto*//*Label 7834*/ GIMT_Encode4(287902), // Rule ID 59570 // |
| 113413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113414 | // (bitreverse:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 113415 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 113416 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113417 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113418 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113421 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113422 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113426 | GIR_RootConstrainSelectedInstOperands, |
| 113427 | // GIR_Coverage, 59570, |
| 113428 | GIR_EraseRootFromParent_Done, |
| 113429 | // Label 7834: @287902 |
| 113430 | GIM_Try, /*On fail goto*//*Label 7835*/ GIMT_Encode4(287945), // Rule ID 59571 // |
| 113431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113432 | // (bitreverse:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 113433 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 113434 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113435 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113436 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113439 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113440 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113444 | GIR_RootConstrainSelectedInstOperands, |
| 113445 | // GIR_Coverage, 59571, |
| 113446 | GIR_EraseRootFromParent_Done, |
| 113447 | // Label 7835: @287945 |
| 113448 | GIM_Reject, |
| 113449 | // Label 7833: @287946 |
| 113450 | GIM_Reject, |
| 113451 | // Label 7769: @287947 |
| 113452 | GIM_Try, /*On fail goto*//*Label 7836*/ GIMT_Encode4(288050), |
| 113453 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, |
| 113454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113455 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 113456 | GIM_Try, /*On fail goto*//*Label 7837*/ GIMT_Encode4(288006), // Rule ID 59564 // |
| 113457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0), |
| 113458 | // (bitreverse:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) |
| 113459 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 113460 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113461 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113465 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113466 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113470 | GIR_RootConstrainSelectedInstOperands, |
| 113471 | // GIR_Coverage, 59564, |
| 113472 | GIR_EraseRootFromParent_Done, |
| 113473 | // Label 7837: @288006 |
| 113474 | GIM_Try, /*On fail goto*//*Label 7838*/ GIMT_Encode4(288049), // Rule ID 59565 // |
| 113475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1), |
| 113476 | // (bitreverse:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1) => (PseudoVBREV_V_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) |
| 113477 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, |
| 113478 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113479 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVBREV_V_M8), |
| 113482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113483 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113484 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113488 | GIR_RootConstrainSelectedInstOperands, |
| 113489 | // GIR_Coverage, 59565, |
| 113490 | GIR_EraseRootFromParent_Done, |
| 113491 | // Label 7838: @288049 |
| 113492 | GIM_Reject, |
| 113493 | // Label 7836: @288050 |
| 113494 | GIM_Reject, |
| 113495 | // Label 7770: @288051 |
| 113496 | GIM_Reject, |
| 113497 | // Label 84: @288052 |
| 113498 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 7842*/ GIMT_Encode4(288249), |
| 113499 | /*GILLT_s16*//*Label 7839*/ GIMT_Encode4(288075), |
| 113500 | /*GILLT_s32*//*Label 7840*/ GIMT_Encode4(288133), |
| 113501 | /*GILLT_s64*//*Label 7841*/ GIMT_Encode4(288191), |
| 113502 | // Label 7839: @288075 |
| 113503 | GIM_Try, /*On fail goto*//*Label 7843*/ GIMT_Encode4(288132), |
| 113504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 113505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 113506 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 113507 | GIM_Try, /*On fail goto*//*Label 7844*/ GIMT_Encode4(288111), // Rule ID 2588 // |
| 113508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 113509 | // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 3:{ *:[i64] }) |
| 113510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 113511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113512 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113514 | GIR_RootConstrainSelectedInstOperands, |
| 113515 | // GIR_Coverage, 2588, |
| 113516 | GIR_EraseRootFromParent_Done, |
| 113517 | // Label 7844: @288111 |
| 113518 | GIM_Try, /*On fail goto*//*Label 7845*/ GIMT_Encode4(288131), // Rule ID 2589 // |
| 113519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 113520 | // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 3:{ *:[i32] }) |
| 113521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 113522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113523 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113525 | GIR_RootConstrainSelectedInstOperands, |
| 113526 | // GIR_Coverage, 2589, |
| 113527 | GIR_EraseRootFromParent_Done, |
| 113528 | // Label 7845: @288131 |
| 113529 | GIM_Reject, |
| 113530 | // Label 7843: @288132 |
| 113531 | GIM_Reject, |
| 113532 | // Label 7840: @288133 |
| 113533 | GIM_Try, /*On fail goto*//*Label 7846*/ GIMT_Encode4(288190), |
| 113534 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 113535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 113536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 113537 | GIM_Try, /*On fail goto*//*Label 7847*/ GIMT_Encode4(288169), // Rule ID 2510 // |
| 113538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode0), |
| 113539 | // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 3:{ *:[i64] }) |
| 113540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 113541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113542 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113544 | GIR_RootConstrainSelectedInstOperands, |
| 113545 | // GIR_Coverage, 2510, |
| 113546 | GIR_EraseRootFromParent_Done, |
| 113547 | // Label 7847: @288169 |
| 113548 | GIM_Try, /*On fail goto*//*Label 7848*/ GIMT_Encode4(288189), // Rule ID 2511 // |
| 113549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode1), |
| 113550 | // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 3:{ *:[i32] }) |
| 113551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 113552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113553 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113555 | GIR_RootConstrainSelectedInstOperands, |
| 113556 | // GIR_Coverage, 2511, |
| 113557 | GIR_EraseRootFromParent_Done, |
| 113558 | // Label 7848: @288189 |
| 113559 | GIM_Reject, |
| 113560 | // Label 7846: @288190 |
| 113561 | GIM_Reject, |
| 113562 | // Label 7841: @288191 |
| 113563 | GIM_Try, /*On fail goto*//*Label 7849*/ GIMT_Encode4(288248), |
| 113564 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 113565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 113566 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 113567 | GIM_Try, /*On fail goto*//*Label 7850*/ GIMT_Encode4(288227), // Rule ID 2548 // |
| 113568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 113569 | // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 3:{ *:[i64] }) |
| 113570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 113571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113572 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113574 | GIR_RootConstrainSelectedInstOperands, |
| 113575 | // GIR_Coverage, 2548, |
| 113576 | GIR_EraseRootFromParent_Done, |
| 113577 | // Label 7850: @288227 |
| 113578 | GIM_Try, /*On fail goto*//*Label 7851*/ GIMT_Encode4(288247), // Rule ID 2549 // |
| 113579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 113580 | // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 3:{ *:[i32] }) |
| 113581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 113582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113583 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113585 | GIR_RootConstrainSelectedInstOperands, |
| 113586 | // GIR_Coverage, 2549, |
| 113587 | GIR_EraseRootFromParent_Done, |
| 113588 | // Label 7851: @288247 |
| 113589 | GIM_Reject, |
| 113590 | // Label 7849: @288248 |
| 113591 | GIM_Reject, |
| 113592 | // Label 7842: @288249 |
| 113593 | GIM_Reject, |
| 113594 | // Label 85: @288250 |
| 113595 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 7870*/ GIMT_Encode4(290425), |
| 113596 | /*GILLT_s16*//*Label 7852*/ GIMT_Encode4(288381), |
| 113597 | /*GILLT_s32*//*Label 7853*/ GIMT_Encode4(288503), |
| 113598 | /*GILLT_s64*//*Label 7854*/ GIMT_Encode4(288625), GIMT_Encode4(0), GIMT_Encode4(0), |
| 113599 | /*GILLT_nxv1s16*//*Label 7855*/ GIMT_Encode4(288775), |
| 113600 | /*GILLT_nxv1s32*//*Label 7856*/ GIMT_Encode4(288885), |
| 113601 | /*GILLT_nxv1s64*//*Label 7857*/ GIMT_Encode4(288995), GIMT_Encode4(0), GIMT_Encode4(0), |
| 113602 | /*GILLT_nxv2s16*//*Label 7858*/ GIMT_Encode4(289105), |
| 113603 | /*GILLT_nxv2s32*//*Label 7859*/ GIMT_Encode4(289215), |
| 113604 | /*GILLT_nxv2s64*//*Label 7860*/ GIMT_Encode4(289325), GIMT_Encode4(0), GIMT_Encode4(0), |
| 113605 | /*GILLT_nxv4s16*//*Label 7861*/ GIMT_Encode4(289435), |
| 113606 | /*GILLT_nxv4s32*//*Label 7862*/ GIMT_Encode4(289545), |
| 113607 | /*GILLT_nxv4s64*//*Label 7863*/ GIMT_Encode4(289655), GIMT_Encode4(0), GIMT_Encode4(0), |
| 113608 | /*GILLT_nxv8s16*//*Label 7864*/ GIMT_Encode4(289765), |
| 113609 | /*GILLT_nxv8s32*//*Label 7865*/ GIMT_Encode4(289875), |
| 113610 | /*GILLT_nxv8s64*//*Label 7866*/ GIMT_Encode4(289985), GIMT_Encode4(0), GIMT_Encode4(0), |
| 113611 | /*GILLT_nxv16s16*//*Label 7867*/ GIMT_Encode4(290095), |
| 113612 | /*GILLT_nxv16s32*//*Label 7868*/ GIMT_Encode4(290205), GIMT_Encode4(0), GIMT_Encode4(0), |
| 113613 | /*GILLT_nxv32s16*//*Label 7869*/ GIMT_Encode4(290315), |
| 113614 | // Label 7852: @288381 |
| 113615 | GIM_Try, /*On fail goto*//*Label 7871*/ GIMT_Encode4(288502), |
| 113616 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 113617 | GIM_Try, /*On fail goto*//*Label 7872*/ GIMT_Encode4(288417), // Rule ID 2044 // |
| 113618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 113619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 113620 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 113621 | // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 113622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H), |
| 113623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113624 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113626 | GIR_RootConstrainSelectedInstOperands, |
| 113627 | // GIR_Coverage, 2044, |
| 113628 | GIR_EraseRootFromParent_Done, |
| 113629 | // Label 7872: @288417 |
| 113630 | GIM_Try, /*On fail goto*//*Label 7873*/ GIMT_Encode4(288445), // Rule ID 2045 // |
| 113631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 113632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 113633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 113634 | // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 113635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H), |
| 113636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113639 | GIR_RootConstrainSelectedInstOperands, |
| 113640 | // GIR_Coverage, 2045, |
| 113641 | GIR_EraseRootFromParent_Done, |
| 113642 | // Label 7873: @288445 |
| 113643 | GIM_Try, /*On fail goto*//*Label 7874*/ GIMT_Encode4(288473), // Rule ID 2076 // |
| 113644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 113645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 113646 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 113647 | // (fsqrt:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1) => (FSQRT_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 113648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H_INX), |
| 113649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113650 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113652 | GIR_RootConstrainSelectedInstOperands, |
| 113653 | // GIR_Coverage, 2076, |
| 113654 | GIR_EraseRootFromParent_Done, |
| 113655 | // Label 7874: @288473 |
| 113656 | GIM_Try, /*On fail goto*//*Label 7875*/ GIMT_Encode4(288501), // Rule ID 2077 // |
| 113657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 113658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 113659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 113660 | // (fsqrt:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1) => (FSQRT_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 113661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H_INX), |
| 113662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113663 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113665 | GIR_RootConstrainSelectedInstOperands, |
| 113666 | // GIR_Coverage, 2077, |
| 113667 | GIR_EraseRootFromParent_Done, |
| 113668 | // Label 7875: @288501 |
| 113669 | GIM_Reject, |
| 113670 | // Label 7871: @288502 |
| 113671 | GIM_Reject, |
| 113672 | // Label 7853: @288503 |
| 113673 | GIM_Try, /*On fail goto*//*Label 7876*/ GIMT_Encode4(288624), |
| 113674 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 113675 | GIM_Try, /*On fail goto*//*Label 7877*/ GIMT_Encode4(288539), // Rule ID 1356 // |
| 113676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 113677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 113678 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 113679 | // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 113680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S), |
| 113681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113684 | GIR_RootConstrainSelectedInstOperands, |
| 113685 | // GIR_Coverage, 1356, |
| 113686 | GIR_EraseRootFromParent_Done, |
| 113687 | // Label 7877: @288539 |
| 113688 | GIM_Try, /*On fail goto*//*Label 7878*/ GIMT_Encode4(288567), // Rule ID 1357 // |
| 113689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 113690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 113691 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 113692 | // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 113693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S), |
| 113694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113695 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113697 | GIR_RootConstrainSelectedInstOperands, |
| 113698 | // GIR_Coverage, 1357, |
| 113699 | GIR_EraseRootFromParent_Done, |
| 113700 | // Label 7878: @288567 |
| 113701 | GIM_Try, /*On fail goto*//*Label 7879*/ GIMT_Encode4(288595), // Rule ID 1364 // |
| 113702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 113703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 113704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 113705 | // (fsqrt:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1) => (FSQRT_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 113706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S_INX), |
| 113707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113708 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113710 | GIR_RootConstrainSelectedInstOperands, |
| 113711 | // GIR_Coverage, 1364, |
| 113712 | GIR_EraseRootFromParent_Done, |
| 113713 | // Label 7879: @288595 |
| 113714 | GIM_Try, /*On fail goto*//*Label 7880*/ GIMT_Encode4(288623), // Rule ID 1365 // |
| 113715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 113716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 113717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 113718 | // (fsqrt:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1) => (FSQRT_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 113719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S_INX), |
| 113720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113721 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113723 | GIR_RootConstrainSelectedInstOperands, |
| 113724 | // GIR_Coverage, 1365, |
| 113725 | GIR_EraseRootFromParent_Done, |
| 113726 | // Label 7880: @288623 |
| 113727 | GIM_Reject, |
| 113728 | // Label 7876: @288624 |
| 113729 | GIM_Reject, |
| 113730 | // Label 7854: @288625 |
| 113731 | GIM_Try, /*On fail goto*//*Label 7881*/ GIMT_Encode4(288774), |
| 113732 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 113733 | GIM_Try, /*On fail goto*//*Label 7882*/ GIMT_Encode4(288661), // Rule ID 1691 // |
| 113734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 113735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 113736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 113737 | // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 113738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D), |
| 113739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113740 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113742 | GIR_RootConstrainSelectedInstOperands, |
| 113743 | // GIR_Coverage, 1691, |
| 113744 | GIR_EraseRootFromParent_Done, |
| 113745 | // Label 7882: @288661 |
| 113746 | GIM_Try, /*On fail goto*//*Label 7883*/ GIMT_Encode4(288689), // Rule ID 1692 // |
| 113747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 113748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 113749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 113750 | // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 113751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D), |
| 113752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113753 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113755 | GIR_RootConstrainSelectedInstOperands, |
| 113756 | // GIR_Coverage, 1692, |
| 113757 | GIR_EraseRootFromParent_Done, |
| 113758 | // Label 7883: @288689 |
| 113759 | GIM_Try, /*On fail goto*//*Label 7884*/ GIMT_Encode4(288717), // Rule ID 1724 // |
| 113760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 113761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 113762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 113763 | // (fsqrt:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1) => (FSQRT_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 113764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D_INX), |
| 113765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113768 | GIR_RootConstrainSelectedInstOperands, |
| 113769 | // GIR_Coverage, 1724, |
| 113770 | GIR_EraseRootFromParent_Done, |
| 113771 | // Label 7884: @288717 |
| 113772 | GIM_Try, /*On fail goto*//*Label 7885*/ GIMT_Encode4(288745), // Rule ID 1744 // |
| 113773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 113774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 113775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 113776 | // (fsqrt:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FSQRT_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 113777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D_IN32X), |
| 113778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113779 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113781 | GIR_RootConstrainSelectedInstOperands, |
| 113782 | // GIR_Coverage, 1744, |
| 113783 | GIR_EraseRootFromParent_Done, |
| 113784 | // Label 7885: @288745 |
| 113785 | GIM_Try, /*On fail goto*//*Label 7886*/ GIMT_Encode4(288773), // Rule ID 1745 // |
| 113786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 113787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 113788 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 113789 | // (fsqrt:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FSQRT_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 113790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D_IN32X), |
| 113791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113792 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 113793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113794 | GIR_RootConstrainSelectedInstOperands, |
| 113795 | // GIR_Coverage, 1745, |
| 113796 | GIR_EraseRootFromParent_Done, |
| 113797 | // Label 7886: @288773 |
| 113798 | GIM_Reject, |
| 113799 | // Label 7881: @288774 |
| 113800 | GIM_Reject, |
| 113801 | // Label 7855: @288775 |
| 113802 | GIM_Try, /*On fail goto*//*Label 7887*/ GIMT_Encode4(288884), |
| 113803 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 113804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113806 | GIM_Try, /*On fail goto*//*Label 7888*/ GIMT_Encode4(288837), // Rule ID 56862 // |
| 113807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 113808 | // (fsqrt:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSQRT_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 113809 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 113810 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113811 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113812 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF4_E16), |
| 113814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113815 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113816 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113821 | GIR_RootConstrainSelectedInstOperands, |
| 113822 | // GIR_Coverage, 56862, |
| 113823 | GIR_EraseRootFromParent_Done, |
| 113824 | // Label 7888: @288837 |
| 113825 | GIM_Try, /*On fail goto*//*Label 7889*/ GIMT_Encode4(288883), // Rule ID 56863 // |
| 113826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 113827 | // (fsqrt:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSQRT_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 113828 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 113829 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113830 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF4_E16), |
| 113833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113835 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113840 | GIR_RootConstrainSelectedInstOperands, |
| 113841 | // GIR_Coverage, 56863, |
| 113842 | GIR_EraseRootFromParent_Done, |
| 113843 | // Label 7889: @288883 |
| 113844 | GIM_Reject, |
| 113845 | // Label 7887: @288884 |
| 113846 | GIM_Reject, |
| 113847 | // Label 7856: @288885 |
| 113848 | GIM_Try, /*On fail goto*//*Label 7890*/ GIMT_Encode4(288994), |
| 113849 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 113850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113851 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113852 | GIM_Try, /*On fail goto*//*Label 7891*/ GIMT_Encode4(288947), // Rule ID 56902 // |
| 113853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 113854 | // (fsqrt:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSQRT_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 113855 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 113856 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113857 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E32), |
| 113860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113861 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113862 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113867 | GIR_RootConstrainSelectedInstOperands, |
| 113868 | // GIR_Coverage, 56902, |
| 113869 | GIR_EraseRootFromParent_Done, |
| 113870 | // Label 7891: @288947 |
| 113871 | GIM_Try, /*On fail goto*//*Label 7892*/ GIMT_Encode4(288993), // Rule ID 56903 // |
| 113872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 113873 | // (fsqrt:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSQRT_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 113874 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 113875 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113876 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E32), |
| 113879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113881 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 113885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113886 | GIR_RootConstrainSelectedInstOperands, |
| 113887 | // GIR_Coverage, 56903, |
| 113888 | GIR_EraseRootFromParent_Done, |
| 113889 | // Label 7892: @288993 |
| 113890 | GIM_Reject, |
| 113891 | // Label 7890: @288994 |
| 113892 | GIM_Reject, |
| 113893 | // Label 7857: @288995 |
| 113894 | GIM_Try, /*On fail goto*//*Label 7893*/ GIMT_Encode4(289104), |
| 113895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 113896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113897 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113898 | GIM_Try, /*On fail goto*//*Label 7894*/ GIMT_Encode4(289057), // Rule ID 56962 // |
| 113899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 113900 | // (fsqrt:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSQRT_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 113901 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 113902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E64), |
| 113906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113907 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 113912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113913 | GIR_RootConstrainSelectedInstOperands, |
| 113914 | // GIR_Coverage, 56962, |
| 113915 | GIR_EraseRootFromParent_Done, |
| 113916 | // Label 7894: @289057 |
| 113917 | GIM_Try, /*On fail goto*//*Label 7895*/ GIMT_Encode4(289103), // Rule ID 56963 // |
| 113918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 113919 | // (fsqrt:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSQRT_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 113920 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 113921 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113922 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113923 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E64), |
| 113925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113926 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113927 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 113931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113932 | GIR_RootConstrainSelectedInstOperands, |
| 113933 | // GIR_Coverage, 56963, |
| 113934 | GIR_EraseRootFromParent_Done, |
| 113935 | // Label 7895: @289103 |
| 113936 | GIM_Reject, |
| 113937 | // Label 7893: @289104 |
| 113938 | GIM_Reject, |
| 113939 | // Label 7858: @289105 |
| 113940 | GIM_Try, /*On fail goto*//*Label 7896*/ GIMT_Encode4(289214), |
| 113941 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 113942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113943 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113944 | GIM_Try, /*On fail goto*//*Label 7897*/ GIMT_Encode4(289167), // Rule ID 56882 // |
| 113945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 113946 | // (fsqrt:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSQRT_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 113947 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 113948 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113949 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E16), |
| 113952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113953 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113954 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113959 | GIR_RootConstrainSelectedInstOperands, |
| 113960 | // GIR_Coverage, 56882, |
| 113961 | GIR_EraseRootFromParent_Done, |
| 113962 | // Label 7897: @289167 |
| 113963 | GIM_Try, /*On fail goto*//*Label 7898*/ GIMT_Encode4(289213), // Rule ID 56883 // |
| 113964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 113965 | // (fsqrt:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSQRT_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 113966 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 113967 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113968 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113969 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E16), |
| 113971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113972 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 113973 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 113974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 113975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 113976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 113977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 113978 | GIR_RootConstrainSelectedInstOperands, |
| 113979 | // GIR_Coverage, 56883, |
| 113980 | GIR_EraseRootFromParent_Done, |
| 113981 | // Label 7898: @289213 |
| 113982 | GIM_Reject, |
| 113983 | // Label 7896: @289214 |
| 113984 | GIM_Reject, |
| 113985 | // Label 7859: @289215 |
| 113986 | GIM_Try, /*On fail goto*//*Label 7899*/ GIMT_Encode4(289324), |
| 113987 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 113988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 113990 | GIM_Try, /*On fail goto*//*Label 7900*/ GIMT_Encode4(289277), // Rule ID 56942 // |
| 113991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 113992 | // (fsqrt:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSQRT_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 113993 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 113994 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 113995 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 113996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 113997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E32), |
| 113998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 113999 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114000 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114005 | GIR_RootConstrainSelectedInstOperands, |
| 114006 | // GIR_Coverage, 56942, |
| 114007 | GIR_EraseRootFromParent_Done, |
| 114008 | // Label 7900: @289277 |
| 114009 | GIM_Try, /*On fail goto*//*Label 7901*/ GIMT_Encode4(289323), // Rule ID 56943 // |
| 114010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 114011 | // (fsqrt:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSQRT_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 114012 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 114013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E32), |
| 114017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114018 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114019 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114024 | GIR_RootConstrainSelectedInstOperands, |
| 114025 | // GIR_Coverage, 56943, |
| 114026 | GIR_EraseRootFromParent_Done, |
| 114027 | // Label 7901: @289323 |
| 114028 | GIM_Reject, |
| 114029 | // Label 7899: @289324 |
| 114030 | GIM_Reject, |
| 114031 | // Label 7860: @289325 |
| 114032 | GIM_Try, /*On fail goto*//*Label 7902*/ GIMT_Encode4(289434), |
| 114033 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 114034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 114035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 114036 | GIM_Try, /*On fail goto*//*Label 7903*/ GIMT_Encode4(289387), // Rule ID 57102 // |
| 114037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 114038 | // (fsqrt:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSQRT_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 114039 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 114040 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114041 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114042 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E64), |
| 114044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114045 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114046 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 114050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114051 | GIR_RootConstrainSelectedInstOperands, |
| 114052 | // GIR_Coverage, 57102, |
| 114053 | GIR_EraseRootFromParent_Done, |
| 114054 | // Label 7903: @289387 |
| 114055 | GIM_Try, /*On fail goto*//*Label 7904*/ GIMT_Encode4(289433), // Rule ID 57103 // |
| 114056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 114057 | // (fsqrt:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSQRT_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 114058 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 114059 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114060 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E64), |
| 114063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114064 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114065 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 114069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114070 | GIR_RootConstrainSelectedInstOperands, |
| 114071 | // GIR_Coverage, 57103, |
| 114072 | GIR_EraseRootFromParent_Done, |
| 114073 | // Label 7904: @289433 |
| 114074 | GIM_Reject, |
| 114075 | // Label 7902: @289434 |
| 114076 | GIM_Reject, |
| 114077 | // Label 7861: @289435 |
| 114078 | GIM_Try, /*On fail goto*//*Label 7905*/ GIMT_Encode4(289544), |
| 114079 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 114080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 114081 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 114082 | GIM_Try, /*On fail goto*//*Label 7906*/ GIMT_Encode4(289497), // Rule ID 56922 // |
| 114083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 114084 | // (fsqrt:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSQRT_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 114085 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 114086 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114087 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E16), |
| 114090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114091 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114092 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114097 | GIR_RootConstrainSelectedInstOperands, |
| 114098 | // GIR_Coverage, 56922, |
| 114099 | GIR_EraseRootFromParent_Done, |
| 114100 | // Label 7906: @289497 |
| 114101 | GIM_Try, /*On fail goto*//*Label 7907*/ GIMT_Encode4(289543), // Rule ID 56923 // |
| 114102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 114103 | // (fsqrt:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSQRT_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 114104 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 114105 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114106 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E16), |
| 114109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114110 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114111 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114116 | GIR_RootConstrainSelectedInstOperands, |
| 114117 | // GIR_Coverage, 56923, |
| 114118 | GIR_EraseRootFromParent_Done, |
| 114119 | // Label 7907: @289543 |
| 114120 | GIM_Reject, |
| 114121 | // Label 7905: @289544 |
| 114122 | GIM_Reject, |
| 114123 | // Label 7862: @289545 |
| 114124 | GIM_Try, /*On fail goto*//*Label 7908*/ GIMT_Encode4(289654), |
| 114125 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 114126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 114127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 114128 | GIM_Try, /*On fail goto*//*Label 7909*/ GIMT_Encode4(289607), // Rule ID 57042 // |
| 114129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 114130 | // (fsqrt:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSQRT_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 114131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 114132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E32), |
| 114136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114137 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114138 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114143 | GIR_RootConstrainSelectedInstOperands, |
| 114144 | // GIR_Coverage, 57042, |
| 114145 | GIR_EraseRootFromParent_Done, |
| 114146 | // Label 7909: @289607 |
| 114147 | GIM_Try, /*On fail goto*//*Label 7910*/ GIMT_Encode4(289653), // Rule ID 57043 // |
| 114148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 114149 | // (fsqrt:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSQRT_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 114150 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 114151 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114152 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E32), |
| 114155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114156 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114157 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114162 | GIR_RootConstrainSelectedInstOperands, |
| 114163 | // GIR_Coverage, 57043, |
| 114164 | GIR_EraseRootFromParent_Done, |
| 114165 | // Label 7910: @289653 |
| 114166 | GIM_Reject, |
| 114167 | // Label 7908: @289654 |
| 114168 | GIM_Reject, |
| 114169 | // Label 7863: @289655 |
| 114170 | GIM_Try, /*On fail goto*//*Label 7911*/ GIMT_Encode4(289764), |
| 114171 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 114172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 114173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 114174 | GIM_Try, /*On fail goto*//*Label 7912*/ GIMT_Encode4(289717), // Rule ID 57122 // |
| 114175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 114176 | // (fsqrt:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSQRT_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 114177 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 114178 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114179 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114180 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E64), |
| 114182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114183 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114184 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 114188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114189 | GIR_RootConstrainSelectedInstOperands, |
| 114190 | // GIR_Coverage, 57122, |
| 114191 | GIR_EraseRootFromParent_Done, |
| 114192 | // Label 7912: @289717 |
| 114193 | GIM_Try, /*On fail goto*//*Label 7913*/ GIMT_Encode4(289763), // Rule ID 57123 // |
| 114194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 114195 | // (fsqrt:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSQRT_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 114196 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 114197 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114198 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114199 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E64), |
| 114201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114202 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114203 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 114207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114208 | GIR_RootConstrainSelectedInstOperands, |
| 114209 | // GIR_Coverage, 57123, |
| 114210 | GIR_EraseRootFromParent_Done, |
| 114211 | // Label 7913: @289763 |
| 114212 | GIM_Reject, |
| 114213 | // Label 7911: @289764 |
| 114214 | GIM_Reject, |
| 114215 | // Label 7864: @289765 |
| 114216 | GIM_Try, /*On fail goto*//*Label 7914*/ GIMT_Encode4(289874), |
| 114217 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 114218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 114219 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 114220 | GIM_Try, /*On fail goto*//*Label 7915*/ GIMT_Encode4(289827), // Rule ID 56982 // |
| 114221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 114222 | // (fsqrt:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSQRT_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 114223 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 114224 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114225 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E16), |
| 114228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114229 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114230 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114235 | GIR_RootConstrainSelectedInstOperands, |
| 114236 | // GIR_Coverage, 56982, |
| 114237 | GIR_EraseRootFromParent_Done, |
| 114238 | // Label 7915: @289827 |
| 114239 | GIM_Try, /*On fail goto*//*Label 7916*/ GIMT_Encode4(289873), // Rule ID 56983 // |
| 114240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 114241 | // (fsqrt:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSQRT_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 114242 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 114243 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114244 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E16), |
| 114247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114248 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114249 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114254 | GIR_RootConstrainSelectedInstOperands, |
| 114255 | // GIR_Coverage, 56983, |
| 114256 | GIR_EraseRootFromParent_Done, |
| 114257 | // Label 7916: @289873 |
| 114258 | GIM_Reject, |
| 114259 | // Label 7914: @289874 |
| 114260 | GIM_Reject, |
| 114261 | // Label 7865: @289875 |
| 114262 | GIM_Try, /*On fail goto*//*Label 7917*/ GIMT_Encode4(289984), |
| 114263 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 114264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 114265 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 114266 | GIM_Try, /*On fail goto*//*Label 7918*/ GIMT_Encode4(289937), // Rule ID 57062 // |
| 114267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 114268 | // (fsqrt:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSQRT_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 114269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 114270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E32), |
| 114274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114276 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114281 | GIR_RootConstrainSelectedInstOperands, |
| 114282 | // GIR_Coverage, 57062, |
| 114283 | GIR_EraseRootFromParent_Done, |
| 114284 | // Label 7918: @289937 |
| 114285 | GIM_Try, /*On fail goto*//*Label 7919*/ GIMT_Encode4(289983), // Rule ID 57063 // |
| 114286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 114287 | // (fsqrt:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSQRT_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 114288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 114289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E32), |
| 114293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114300 | GIR_RootConstrainSelectedInstOperands, |
| 114301 | // GIR_Coverage, 57063, |
| 114302 | GIR_EraseRootFromParent_Done, |
| 114303 | // Label 7919: @289983 |
| 114304 | GIM_Reject, |
| 114305 | // Label 7917: @289984 |
| 114306 | GIM_Reject, |
| 114307 | // Label 7866: @289985 |
| 114308 | GIM_Try, /*On fail goto*//*Label 7920*/ GIMT_Encode4(290094), |
| 114309 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 114310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 114311 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 114312 | GIM_Try, /*On fail goto*//*Label 7921*/ GIMT_Encode4(290047), // Rule ID 57142 // |
| 114313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 114314 | // (fsqrt:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSQRT_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 114315 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 114316 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114317 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E64), |
| 114320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114321 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114322 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 114326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114327 | GIR_RootConstrainSelectedInstOperands, |
| 114328 | // GIR_Coverage, 57142, |
| 114329 | GIR_EraseRootFromParent_Done, |
| 114330 | // Label 7921: @290047 |
| 114331 | GIM_Try, /*On fail goto*//*Label 7922*/ GIMT_Encode4(290093), // Rule ID 57143 // |
| 114332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 114333 | // (fsqrt:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSQRT_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 114334 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 114335 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114336 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E64), |
| 114339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114340 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114341 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 114345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114346 | GIR_RootConstrainSelectedInstOperands, |
| 114347 | // GIR_Coverage, 57143, |
| 114348 | GIR_EraseRootFromParent_Done, |
| 114349 | // Label 7922: @290093 |
| 114350 | GIM_Reject, |
| 114351 | // Label 7920: @290094 |
| 114352 | GIM_Reject, |
| 114353 | // Label 7867: @290095 |
| 114354 | GIM_Try, /*On fail goto*//*Label 7923*/ GIMT_Encode4(290204), |
| 114355 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 114356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 114357 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 114358 | GIM_Try, /*On fail goto*//*Label 7924*/ GIMT_Encode4(290157), // Rule ID 57002 // |
| 114359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 114360 | // (fsqrt:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSQRT_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 114361 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 114362 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114363 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E16), |
| 114366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114367 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114368 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114373 | GIR_RootConstrainSelectedInstOperands, |
| 114374 | // GIR_Coverage, 57002, |
| 114375 | GIR_EraseRootFromParent_Done, |
| 114376 | // Label 7924: @290157 |
| 114377 | GIM_Try, /*On fail goto*//*Label 7925*/ GIMT_Encode4(290203), // Rule ID 57003 // |
| 114378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 114379 | // (fsqrt:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSQRT_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 114380 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 114381 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114382 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E16), |
| 114385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114386 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114387 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114392 | GIR_RootConstrainSelectedInstOperands, |
| 114393 | // GIR_Coverage, 57003, |
| 114394 | GIR_EraseRootFromParent_Done, |
| 114395 | // Label 7925: @290203 |
| 114396 | GIM_Reject, |
| 114397 | // Label 7923: @290204 |
| 114398 | GIM_Reject, |
| 114399 | // Label 7868: @290205 |
| 114400 | GIM_Try, /*On fail goto*//*Label 7926*/ GIMT_Encode4(290314), |
| 114401 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 114402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 114403 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 114404 | GIM_Try, /*On fail goto*//*Label 7927*/ GIMT_Encode4(290267), // Rule ID 57082 // |
| 114405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 114406 | // (fsqrt:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSQRT_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 114407 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 114408 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114409 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E32), |
| 114412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114413 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114414 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114419 | GIR_RootConstrainSelectedInstOperands, |
| 114420 | // GIR_Coverage, 57082, |
| 114421 | GIR_EraseRootFromParent_Done, |
| 114422 | // Label 7927: @290267 |
| 114423 | GIM_Try, /*On fail goto*//*Label 7928*/ GIMT_Encode4(290313), // Rule ID 57083 // |
| 114424 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 114425 | // (fsqrt:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSQRT_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 114426 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 114427 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114428 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E32), |
| 114431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114432 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114433 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 114437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114438 | GIR_RootConstrainSelectedInstOperands, |
| 114439 | // GIR_Coverage, 57083, |
| 114440 | GIR_EraseRootFromParent_Done, |
| 114441 | // Label 7928: @290313 |
| 114442 | GIM_Reject, |
| 114443 | // Label 7926: @290314 |
| 114444 | GIM_Reject, |
| 114445 | // Label 7869: @290315 |
| 114446 | GIM_Try, /*On fail goto*//*Label 7929*/ GIMT_Encode4(290424), |
| 114447 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 114448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 114449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 114450 | GIM_Try, /*On fail goto*//*Label 7930*/ GIMT_Encode4(290377), // Rule ID 57022 // |
| 114451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 114452 | // (fsqrt:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSQRT_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 114453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 114454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E16), |
| 114458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114459 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114460 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114465 | GIR_RootConstrainSelectedInstOperands, |
| 114466 | // GIR_Coverage, 57022, |
| 114467 | GIR_EraseRootFromParent_Done, |
| 114468 | // Label 7930: @290377 |
| 114469 | GIM_Try, /*On fail goto*//*Label 7931*/ GIMT_Encode4(290423), // Rule ID 57023 // |
| 114470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 114471 | // (fsqrt:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSQRT_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 114472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 114473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 114474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 114475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 114476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E16), |
| 114477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 114479 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 114480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 114482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 114483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 114484 | GIR_RootConstrainSelectedInstOperands, |
| 114485 | // GIR_Coverage, 57023, |
| 114486 | GIR_EraseRootFromParent_Done, |
| 114487 | // Label 7931: @290423 |
| 114488 | GIM_Reject, |
| 114489 | // Label 7929: @290424 |
| 114490 | GIM_Reject, |
| 114491 | // Label 7870: @290425 |
| 114492 | GIM_Reject, |
| 114493 | // Label 86: @290426 |
| 114494 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 7935*/ GIMT_Encode4(290623), |
| 114495 | /*GILLT_s16*//*Label 7932*/ GIMT_Encode4(290449), |
| 114496 | /*GILLT_s32*//*Label 7933*/ GIMT_Encode4(290507), |
| 114497 | /*GILLT_s64*//*Label 7934*/ GIMT_Encode4(290565), |
| 114498 | // Label 7932: @290449 |
| 114499 | GIM_Try, /*On fail goto*//*Label 7936*/ GIMT_Encode4(290506), |
| 114500 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 114501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114503 | GIM_Try, /*On fail goto*//*Label 7937*/ GIMT_Encode4(290485), // Rule ID 2584 // |
| 114504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 114505 | // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 2:{ *:[i64] }) |
| 114506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 114507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114508 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 114510 | GIR_RootConstrainSelectedInstOperands, |
| 114511 | // GIR_Coverage, 2584, |
| 114512 | GIR_EraseRootFromParent_Done, |
| 114513 | // Label 7937: @290485 |
| 114514 | GIM_Try, /*On fail goto*//*Label 7938*/ GIMT_Encode4(290505), // Rule ID 2585 // |
| 114515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 114516 | // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 2:{ *:[i32] }) |
| 114517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 114518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114519 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 114521 | GIR_RootConstrainSelectedInstOperands, |
| 114522 | // GIR_Coverage, 2585, |
| 114523 | GIR_EraseRootFromParent_Done, |
| 114524 | // Label 7938: @290505 |
| 114525 | GIM_Reject, |
| 114526 | // Label 7936: @290506 |
| 114527 | GIM_Reject, |
| 114528 | // Label 7933: @290507 |
| 114529 | GIM_Try, /*On fail goto*//*Label 7939*/ GIMT_Encode4(290564), |
| 114530 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 114531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114532 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114533 | GIM_Try, /*On fail goto*//*Label 7940*/ GIMT_Encode4(290543), // Rule ID 2506 // |
| 114534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode0), |
| 114535 | // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 2:{ *:[i64] }) |
| 114536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 114537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114538 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 114540 | GIR_RootConstrainSelectedInstOperands, |
| 114541 | // GIR_Coverage, 2506, |
| 114542 | GIR_EraseRootFromParent_Done, |
| 114543 | // Label 7940: @290543 |
| 114544 | GIM_Try, /*On fail goto*//*Label 7941*/ GIMT_Encode4(290563), // Rule ID 2507 // |
| 114545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode1), |
| 114546 | // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 2:{ *:[i32] }) |
| 114547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 114548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114549 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 114551 | GIR_RootConstrainSelectedInstOperands, |
| 114552 | // GIR_Coverage, 2507, |
| 114553 | GIR_EraseRootFromParent_Done, |
| 114554 | // Label 7941: @290563 |
| 114555 | GIM_Reject, |
| 114556 | // Label 7939: @290564 |
| 114557 | GIM_Reject, |
| 114558 | // Label 7934: @290565 |
| 114559 | GIM_Try, /*On fail goto*//*Label 7942*/ GIMT_Encode4(290622), |
| 114560 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 114561 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114562 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114563 | GIM_Try, /*On fail goto*//*Label 7943*/ GIMT_Encode4(290601), // Rule ID 2544 // |
| 114564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 114565 | // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 2:{ *:[i64] }) |
| 114566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 114567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114568 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 114570 | GIR_RootConstrainSelectedInstOperands, |
| 114571 | // GIR_Coverage, 2544, |
| 114572 | GIR_EraseRootFromParent_Done, |
| 114573 | // Label 7943: @290601 |
| 114574 | GIM_Try, /*On fail goto*//*Label 7944*/ GIMT_Encode4(290621), // Rule ID 2545 // |
| 114575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 114576 | // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 2:{ *:[i32] }) |
| 114577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 114578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114579 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 114581 | GIR_RootConstrainSelectedInstOperands, |
| 114582 | // GIR_Coverage, 2545, |
| 114583 | GIR_EraseRootFromParent_Done, |
| 114584 | // Label 7944: @290621 |
| 114585 | GIM_Reject, |
| 114586 | // Label 7942: @290622 |
| 114587 | GIM_Reject, |
| 114588 | // Label 7935: @290623 |
| 114589 | GIM_Reject, |
| 114590 | // Label 87: @290624 |
| 114591 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 7948*/ GIMT_Encode4(290821), |
| 114592 | /*GILLT_s16*//*Label 7945*/ GIMT_Encode4(290647), |
| 114593 | /*GILLT_s32*//*Label 7946*/ GIMT_Encode4(290705), |
| 114594 | /*GILLT_s64*//*Label 7947*/ GIMT_Encode4(290763), |
| 114595 | // Label 7945: @290647 |
| 114596 | GIM_Try, /*On fail goto*//*Label 7949*/ GIMT_Encode4(290704), |
| 114597 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 114598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114599 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114600 | GIM_Try, /*On fail goto*//*Label 7950*/ GIMT_Encode4(290683), // Rule ID 2568 // |
| 114601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 114602 | // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUNDNX_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 114603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUNDNX_H), |
| 114604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114605 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114607 | GIR_RootConstrainSelectedInstOperands, |
| 114608 | // GIR_Coverage, 2568, |
| 114609 | GIR_EraseRootFromParent_Done, |
| 114610 | // Label 7950: @290683 |
| 114611 | GIM_Try, /*On fail goto*//*Label 7951*/ GIMT_Encode4(290703), // Rule ID 2569 // |
| 114612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 114613 | // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUNDNX_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 114614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUNDNX_H), |
| 114615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114616 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114618 | GIR_RootConstrainSelectedInstOperands, |
| 114619 | // GIR_Coverage, 2569, |
| 114620 | GIR_EraseRootFromParent_Done, |
| 114621 | // Label 7951: @290703 |
| 114622 | GIM_Reject, |
| 114623 | // Label 7949: @290704 |
| 114624 | GIM_Reject, |
| 114625 | // Label 7946: @290705 |
| 114626 | GIM_Try, /*On fail goto*//*Label 7952*/ GIMT_Encode4(290762), |
| 114627 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 114628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114629 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114630 | GIM_Try, /*On fail goto*//*Label 7953*/ GIMT_Encode4(290741), // Rule ID 2494 // |
| 114631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode0), |
| 114632 | // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUNDNX_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 114633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUNDNX_S), |
| 114634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114635 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114637 | GIR_RootConstrainSelectedInstOperands, |
| 114638 | // GIR_Coverage, 2494, |
| 114639 | GIR_EraseRootFromParent_Done, |
| 114640 | // Label 7953: @290741 |
| 114641 | GIM_Try, /*On fail goto*//*Label 7954*/ GIMT_Encode4(290761), // Rule ID 2495 // |
| 114642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode1), |
| 114643 | // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUNDNX_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 114644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUNDNX_S), |
| 114645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114646 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114648 | GIR_RootConstrainSelectedInstOperands, |
| 114649 | // GIR_Coverage, 2495, |
| 114650 | GIR_EraseRootFromParent_Done, |
| 114651 | // Label 7954: @290761 |
| 114652 | GIM_Reject, |
| 114653 | // Label 7952: @290762 |
| 114654 | GIM_Reject, |
| 114655 | // Label 7947: @290763 |
| 114656 | GIM_Try, /*On fail goto*//*Label 7955*/ GIMT_Encode4(290820), |
| 114657 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 114658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114660 | GIM_Try, /*On fail goto*//*Label 7956*/ GIMT_Encode4(290799), // Rule ID 2528 // |
| 114661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 114662 | // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUNDNX_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 114663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUNDNX_D), |
| 114664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114665 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114667 | GIR_RootConstrainSelectedInstOperands, |
| 114668 | // GIR_Coverage, 2528, |
| 114669 | GIR_EraseRootFromParent_Done, |
| 114670 | // Label 7956: @290799 |
| 114671 | GIM_Try, /*On fail goto*//*Label 7957*/ GIMT_Encode4(290819), // Rule ID 2529 // |
| 114672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 114673 | // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUNDNX_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 114674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUNDNX_D), |
| 114675 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114676 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114678 | GIR_RootConstrainSelectedInstOperands, |
| 114679 | // GIR_Coverage, 2529, |
| 114680 | GIR_EraseRootFromParent_Done, |
| 114681 | // Label 7957: @290819 |
| 114682 | GIM_Reject, |
| 114683 | // Label 7955: @290820 |
| 114684 | GIM_Reject, |
| 114685 | // Label 7948: @290821 |
| 114686 | GIM_Reject, |
| 114687 | // Label 88: @290822 |
| 114688 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(5), /*)*//*default:*//*Label 7961*/ GIMT_Encode4(291019), |
| 114689 | /*GILLT_s16*//*Label 7958*/ GIMT_Encode4(290845), |
| 114690 | /*GILLT_s32*//*Label 7959*/ GIMT_Encode4(290903), |
| 114691 | /*GILLT_s64*//*Label 7960*/ GIMT_Encode4(290961), |
| 114692 | // Label 7958: @290845 |
| 114693 | GIM_Try, /*On fail goto*//*Label 7962*/ GIMT_Encode4(290902), |
| 114694 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 114695 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114696 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114697 | GIM_Try, /*On fail goto*//*Label 7963*/ GIMT_Encode4(290881), // Rule ID 2572 // |
| 114698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0), |
| 114699 | // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 114700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 114701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114702 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114704 | GIR_RootConstrainSelectedInstOperands, |
| 114705 | // GIR_Coverage, 2572, |
| 114706 | GIR_EraseRootFromParent_Done, |
| 114707 | // Label 7963: @290881 |
| 114708 | GIM_Try, /*On fail goto*//*Label 7964*/ GIMT_Encode4(290901), // Rule ID 2573 // |
| 114709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1), |
| 114710 | // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FROUND_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 114711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_H), |
| 114712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114713 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114715 | GIR_RootConstrainSelectedInstOperands, |
| 114716 | // GIR_Coverage, 2573, |
| 114717 | GIR_EraseRootFromParent_Done, |
| 114718 | // Label 7964: @290901 |
| 114719 | GIM_Reject, |
| 114720 | // Label 7962: @290902 |
| 114721 | GIM_Reject, |
| 114722 | // Label 7959: @290903 |
| 114723 | GIM_Try, /*On fail goto*//*Label 7965*/ GIMT_Encode4(290960), |
| 114724 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 114725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114727 | GIM_Try, /*On fail goto*//*Label 7966*/ GIMT_Encode4(290939), // Rule ID 2498 // |
| 114728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode0), |
| 114729 | // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 114730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 114731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114732 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114734 | GIR_RootConstrainSelectedInstOperands, |
| 114735 | // GIR_Coverage, 2498, |
| 114736 | GIR_EraseRootFromParent_Done, |
| 114737 | // Label 7966: @290939 |
| 114738 | GIM_Try, /*On fail goto*//*Label 7967*/ GIMT_Encode4(290959), // Rule ID 2499 // |
| 114739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfa_HwMode1), |
| 114740 | // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FROUND_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 114741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_S), |
| 114742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114743 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114745 | GIR_RootConstrainSelectedInstOperands, |
| 114746 | // GIR_Coverage, 2499, |
| 114747 | GIR_EraseRootFromParent_Done, |
| 114748 | // Label 7967: @290959 |
| 114749 | GIM_Reject, |
| 114750 | // Label 7965: @290960 |
| 114751 | GIM_Reject, |
| 114752 | // Label 7960: @290961 |
| 114753 | GIM_Try, /*On fail goto*//*Label 7968*/ GIMT_Encode4(291018), |
| 114754 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 114755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114757 | GIM_Try, /*On fail goto*//*Label 7969*/ GIMT_Encode4(290997), // Rule ID 2532 // |
| 114758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode0), |
| 114759 | // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 114760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 114761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114762 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114764 | GIR_RootConstrainSelectedInstOperands, |
| 114765 | // GIR_Coverage, 2532, |
| 114766 | GIR_EraseRootFromParent_Done, |
| 114767 | // Label 7969: @290997 |
| 114768 | GIM_Try, /*On fail goto*//*Label 7970*/ GIMT_Encode4(291017), // Rule ID 2533 // |
| 114769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HasStdExtZfa_HwMode1), |
| 114770 | // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FROUND_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 114771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FROUND_D), |
| 114772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114773 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114775 | GIR_RootConstrainSelectedInstOperands, |
| 114776 | // GIR_Coverage, 2533, |
| 114777 | GIR_EraseRootFromParent_Done, |
| 114778 | // Label 7970: @291017 |
| 114779 | GIM_Reject, |
| 114780 | // Label 7968: @291018 |
| 114781 | GIM_Reject, |
| 114782 | // Label 7961: @291019 |
| 114783 | GIM_Reject, |
| 114784 | // Label 89: @291020 |
| 114785 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 7989*/ GIMT_Encode4(293447), |
| 114786 | /*GILLT_s16*//*Label 7971*/ GIMT_Encode4(291151), |
| 114787 | /*GILLT_s32*//*Label 7972*/ GIMT_Encode4(291300), |
| 114788 | /*GILLT_s64*//*Label 7973*/ GIMT_Encode4(291449), GIMT_Encode4(0), GIMT_Encode4(0), |
| 114789 | /*GILLT_nxv1s16*//*Label 7974*/ GIMT_Encode4(291632), |
| 114790 | /*GILLT_nxv1s32*//*Label 7975*/ GIMT_Encode4(291753), |
| 114791 | /*GILLT_nxv1s64*//*Label 7976*/ GIMT_Encode4(291874), GIMT_Encode4(0), GIMT_Encode4(0), |
| 114792 | /*GILLT_nxv2s16*//*Label 7977*/ GIMT_Encode4(291995), |
| 114793 | /*GILLT_nxv2s32*//*Label 7978*/ GIMT_Encode4(292116), |
| 114794 | /*GILLT_nxv2s64*//*Label 7979*/ GIMT_Encode4(292237), GIMT_Encode4(0), GIMT_Encode4(0), |
| 114795 | /*GILLT_nxv4s16*//*Label 7980*/ GIMT_Encode4(292358), |
| 114796 | /*GILLT_nxv4s32*//*Label 7981*/ GIMT_Encode4(292479), |
| 114797 | /*GILLT_nxv4s64*//*Label 7982*/ GIMT_Encode4(292600), GIMT_Encode4(0), GIMT_Encode4(0), |
| 114798 | /*GILLT_nxv8s16*//*Label 7983*/ GIMT_Encode4(292721), |
| 114799 | /*GILLT_nxv8s32*//*Label 7984*/ GIMT_Encode4(292842), |
| 114800 | /*GILLT_nxv8s64*//*Label 7985*/ GIMT_Encode4(292963), GIMT_Encode4(0), GIMT_Encode4(0), |
| 114801 | /*GILLT_nxv16s16*//*Label 7986*/ GIMT_Encode4(293084), |
| 114802 | /*GILLT_nxv16s32*//*Label 7987*/ GIMT_Encode4(293205), GIMT_Encode4(0), GIMT_Encode4(0), |
| 114803 | /*GILLT_nxv32s16*//*Label 7988*/ GIMT_Encode4(293326), |
| 114804 | // Label 7971: @291151 |
| 114805 | GIM_Try, /*On fail goto*//*Label 7990*/ GIMT_Encode4(291299), |
| 114806 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 114807 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 114808 | GIM_Try, /*On fail goto*//*Label 7991*/ GIMT_Encode4(291196), // Rule ID 2010 // |
| 114809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 114810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114812 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114813 | // (strict_fadd:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 114814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H), |
| 114815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114816 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114817 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114819 | GIR_RootConstrainSelectedInstOperands, |
| 114820 | // GIR_Coverage, 2010, |
| 114821 | GIR_EraseRootFromParent_Done, |
| 114822 | // Label 7991: @291196 |
| 114823 | GIM_Try, /*On fail goto*//*Label 7992*/ GIMT_Encode4(291230), // Rule ID 2011 // |
| 114824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 114825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 114828 | // (strict_fadd:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 114829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H), |
| 114830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114831 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114832 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114834 | GIR_RootConstrainSelectedInstOperands, |
| 114835 | // GIR_Coverage, 2011, |
| 114836 | GIR_EraseRootFromParent_Done, |
| 114837 | // Label 7992: @291230 |
| 114838 | GIM_Try, /*On fail goto*//*Label 7993*/ GIMT_Encode4(291264), // Rule ID 2014 // |
| 114839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 114840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 114841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 114842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 114843 | // (strict_fadd:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 114844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H_INX), |
| 114845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114846 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114847 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114849 | GIR_RootConstrainSelectedInstOperands, |
| 114850 | // GIR_Coverage, 2014, |
| 114851 | GIR_EraseRootFromParent_Done, |
| 114852 | // Label 7993: @291264 |
| 114853 | GIM_Try, /*On fail goto*//*Label 7994*/ GIMT_Encode4(291298), // Rule ID 2015 // |
| 114854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 114855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 114856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 114857 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 114858 | // (strict_fadd:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 114859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_H_INX), |
| 114860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114861 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114862 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114864 | GIR_RootConstrainSelectedInstOperands, |
| 114865 | // GIR_Coverage, 2015, |
| 114866 | GIR_EraseRootFromParent_Done, |
| 114867 | // Label 7994: @291298 |
| 114868 | GIM_Reject, |
| 114869 | // Label 7990: @291299 |
| 114870 | GIM_Reject, |
| 114871 | // Label 7972: @291300 |
| 114872 | GIM_Try, /*On fail goto*//*Label 7995*/ GIMT_Encode4(291448), |
| 114873 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 114874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 114875 | GIM_Try, /*On fail goto*//*Label 7996*/ GIMT_Encode4(291345), // Rule ID 1322 // |
| 114876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 114877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114880 | // (strict_fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 114881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S), |
| 114882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114883 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114884 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114886 | GIR_RootConstrainSelectedInstOperands, |
| 114887 | // GIR_Coverage, 1322, |
| 114888 | GIR_EraseRootFromParent_Done, |
| 114889 | // Label 7996: @291345 |
| 114890 | GIM_Try, /*On fail goto*//*Label 7997*/ GIMT_Encode4(291379), // Rule ID 1323 // |
| 114891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 114892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114893 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114894 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 114895 | // (strict_fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 114896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S), |
| 114897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114898 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114899 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114901 | GIR_RootConstrainSelectedInstOperands, |
| 114902 | // GIR_Coverage, 1323, |
| 114903 | GIR_EraseRootFromParent_Done, |
| 114904 | // Label 7997: @291379 |
| 114905 | GIM_Try, /*On fail goto*//*Label 7998*/ GIMT_Encode4(291413), // Rule ID 1326 // |
| 114906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 114907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 114908 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 114909 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 114910 | // (strict_fadd:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 114911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S_INX), |
| 114912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114913 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114914 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114916 | GIR_RootConstrainSelectedInstOperands, |
| 114917 | // GIR_Coverage, 1326, |
| 114918 | GIR_EraseRootFromParent_Done, |
| 114919 | // Label 7998: @291413 |
| 114920 | GIM_Try, /*On fail goto*//*Label 7999*/ GIMT_Encode4(291447), // Rule ID 1327 // |
| 114921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 114922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 114923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 114924 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 114925 | // (strict_fadd:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 114926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_S_INX), |
| 114927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114928 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114929 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114931 | GIR_RootConstrainSelectedInstOperands, |
| 114932 | // GIR_Coverage, 1327, |
| 114933 | GIR_EraseRootFromParent_Done, |
| 114934 | // Label 7999: @291447 |
| 114935 | GIM_Reject, |
| 114936 | // Label 7995: @291448 |
| 114937 | GIM_Reject, |
| 114938 | // Label 7973: @291449 |
| 114939 | GIM_Try, /*On fail goto*//*Label 8000*/ GIMT_Encode4(291631), |
| 114940 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 114941 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 114942 | GIM_Try, /*On fail goto*//*Label 8001*/ GIMT_Encode4(291494), // Rule ID 1649 // |
| 114943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 114944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114945 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114946 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114947 | // (strict_fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 114948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D), |
| 114949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114950 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114951 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114953 | GIR_RootConstrainSelectedInstOperands, |
| 114954 | // GIR_Coverage, 1649, |
| 114955 | GIR_EraseRootFromParent_Done, |
| 114956 | // Label 8001: @291494 |
| 114957 | GIM_Try, /*On fail goto*//*Label 8002*/ GIMT_Encode4(291528), // Rule ID 1650 // |
| 114958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 114959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 114962 | // (strict_fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 114963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D), |
| 114964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114965 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114966 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114968 | GIR_RootConstrainSelectedInstOperands, |
| 114969 | // GIR_Coverage, 1650, |
| 114970 | GIR_EraseRootFromParent_Done, |
| 114971 | // Label 8002: @291528 |
| 114972 | GIM_Try, /*On fail goto*//*Label 8003*/ GIMT_Encode4(291562), // Rule ID 1653 // |
| 114973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 114974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 114975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 114976 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 114977 | // (strict_fadd:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 114978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D_IN32X), |
| 114979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114980 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114981 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114983 | GIR_RootConstrainSelectedInstOperands, |
| 114984 | // GIR_Coverage, 1653, |
| 114985 | GIR_EraseRootFromParent_Done, |
| 114986 | // Label 8003: @291562 |
| 114987 | GIM_Try, /*On fail goto*//*Label 8004*/ GIMT_Encode4(291596), // Rule ID 1654 // |
| 114988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 114989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 114990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 114991 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 114992 | // (strict_fadd:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 114993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D_IN32X), |
| 114994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 114995 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 114996 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 114997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 114998 | GIR_RootConstrainSelectedInstOperands, |
| 114999 | // GIR_Coverage, 1654, |
| 115000 | GIR_EraseRootFromParent_Done, |
| 115001 | // Label 8004: @291596 |
| 115002 | GIM_Try, /*On fail goto*//*Label 8005*/ GIMT_Encode4(291630), // Rule ID 1657 // |
| 115003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 115004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 115005 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 115006 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 115007 | // (strict_fadd:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FADD_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 115008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FADD_D_INX), |
| 115009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115010 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115011 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115013 | GIR_RootConstrainSelectedInstOperands, |
| 115014 | // GIR_Coverage, 1657, |
| 115015 | GIR_EraseRootFromParent_Done, |
| 115016 | // Label 8005: @291630 |
| 115017 | GIM_Reject, |
| 115018 | // Label 8000: @291631 |
| 115019 | GIM_Reject, |
| 115020 | // Label 7974: @291632 |
| 115021 | GIM_Try, /*On fail goto*//*Label 8006*/ GIMT_Encode4(291752), |
| 115022 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 115023 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 115024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115025 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115026 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115027 | GIM_Try, /*On fail goto*//*Label 8007*/ GIMT_Encode4(291703), // Rule ID 46590 // |
| 115028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 115029 | // (strict_fadd:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFADD_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 115030 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 115031 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115032 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115033 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF4_E16), |
| 115035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115036 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115037 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115038 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115043 | GIR_RootConstrainSelectedInstOperands, |
| 115044 | // GIR_Coverage, 46590, |
| 115045 | GIR_EraseRootFromParent_Done, |
| 115046 | // Label 8007: @291703 |
| 115047 | GIM_Try, /*On fail goto*//*Label 8008*/ GIMT_Encode4(291751), // Rule ID 46591 // |
| 115048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 115049 | // (strict_fadd:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFADD_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 115050 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 115051 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115052 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF4_E16), |
| 115055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115056 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115057 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115058 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115063 | GIR_RootConstrainSelectedInstOperands, |
| 115064 | // GIR_Coverage, 46591, |
| 115065 | GIR_EraseRootFromParent_Done, |
| 115066 | // Label 8008: @291751 |
| 115067 | GIM_Reject, |
| 115068 | // Label 8006: @291752 |
| 115069 | GIM_Reject, |
| 115070 | // Label 7975: @291753 |
| 115071 | GIM_Try, /*On fail goto*//*Label 8009*/ GIMT_Encode4(291873), |
| 115072 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 115073 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 115074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115075 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115076 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115077 | GIM_Try, /*On fail goto*//*Label 8010*/ GIMT_Encode4(291824), // Rule ID 53922 // |
| 115078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 115079 | // (strict_fadd:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFADD_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 115080 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 115081 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115082 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E32), |
| 115085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115086 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115087 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115088 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115093 | GIR_RootConstrainSelectedInstOperands, |
| 115094 | // GIR_Coverage, 53922, |
| 115095 | GIR_EraseRootFromParent_Done, |
| 115096 | // Label 8010: @291824 |
| 115097 | GIM_Try, /*On fail goto*//*Label 8011*/ GIMT_Encode4(291872), // Rule ID 53923 // |
| 115098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 115099 | // (strict_fadd:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFADD_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 115100 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 115101 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115102 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E32), |
| 115105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115106 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115107 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115108 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115113 | GIR_RootConstrainSelectedInstOperands, |
| 115114 | // GIR_Coverage, 53923, |
| 115115 | GIR_EraseRootFromParent_Done, |
| 115116 | // Label 8011: @291872 |
| 115117 | GIM_Reject, |
| 115118 | // Label 8009: @291873 |
| 115119 | GIM_Reject, |
| 115120 | // Label 7976: @291874 |
| 115121 | GIM_Try, /*On fail goto*//*Label 8012*/ GIMT_Encode4(291994), |
| 115122 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 115123 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 115124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115125 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115126 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115127 | GIM_Try, /*On fail goto*//*Label 8013*/ GIMT_Encode4(291945), // Rule ID 53958 // |
| 115128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 115129 | // (strict_fadd:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFADD_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 115130 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 115131 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115132 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115133 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E64), |
| 115135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115136 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115137 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115138 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115143 | GIR_RootConstrainSelectedInstOperands, |
| 115144 | // GIR_Coverage, 53958, |
| 115145 | GIR_EraseRootFromParent_Done, |
| 115146 | // Label 8013: @291945 |
| 115147 | GIM_Try, /*On fail goto*//*Label 8014*/ GIMT_Encode4(291993), // Rule ID 53959 // |
| 115148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 115149 | // (strict_fadd:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFADD_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 115150 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 115151 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115152 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E64), |
| 115155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115156 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115157 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115158 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115163 | GIR_RootConstrainSelectedInstOperands, |
| 115164 | // GIR_Coverage, 53959, |
| 115165 | GIR_EraseRootFromParent_Done, |
| 115166 | // Label 8014: @291993 |
| 115167 | GIM_Reject, |
| 115168 | // Label 8012: @291994 |
| 115169 | GIM_Reject, |
| 115170 | // Label 7977: @291995 |
| 115171 | GIM_Try, /*On fail goto*//*Label 8015*/ GIMT_Encode4(292115), |
| 115172 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 115173 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 115174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115175 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115176 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115177 | GIM_Try, /*On fail goto*//*Label 8016*/ GIMT_Encode4(292066), // Rule ID 53910 // |
| 115178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 115179 | // (strict_fadd:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFADD_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 115180 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 115181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E16), |
| 115185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115187 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115188 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115193 | GIR_RootConstrainSelectedInstOperands, |
| 115194 | // GIR_Coverage, 53910, |
| 115195 | GIR_EraseRootFromParent_Done, |
| 115196 | // Label 8016: @292066 |
| 115197 | GIM_Try, /*On fail goto*//*Label 8017*/ GIMT_Encode4(292114), // Rule ID 53911 // |
| 115198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 115199 | // (strict_fadd:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFADD_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 115200 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 115201 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115202 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_MF2_E16), |
| 115205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115206 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115207 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115208 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115213 | GIR_RootConstrainSelectedInstOperands, |
| 115214 | // GIR_Coverage, 53911, |
| 115215 | GIR_EraseRootFromParent_Done, |
| 115216 | // Label 8017: @292114 |
| 115217 | GIM_Reject, |
| 115218 | // Label 8015: @292115 |
| 115219 | GIM_Reject, |
| 115220 | // Label 7978: @292116 |
| 115221 | GIM_Try, /*On fail goto*//*Label 8018*/ GIMT_Encode4(292236), |
| 115222 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 115223 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 115224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115226 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115227 | GIM_Try, /*On fail goto*//*Label 8019*/ GIMT_Encode4(292187), // Rule ID 53946 // |
| 115228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 115229 | // (strict_fadd:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFADD_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 115230 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 115231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115233 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E32), |
| 115235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115236 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115237 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115238 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115243 | GIR_RootConstrainSelectedInstOperands, |
| 115244 | // GIR_Coverage, 53946, |
| 115245 | GIR_EraseRootFromParent_Done, |
| 115246 | // Label 8019: @292187 |
| 115247 | GIM_Try, /*On fail goto*//*Label 8020*/ GIMT_Encode4(292235), // Rule ID 53947 // |
| 115248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 115249 | // (strict_fadd:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFADD_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 115250 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 115251 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115252 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E32), |
| 115255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115256 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115257 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115258 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115263 | GIR_RootConstrainSelectedInstOperands, |
| 115264 | // GIR_Coverage, 53947, |
| 115265 | GIR_EraseRootFromParent_Done, |
| 115266 | // Label 8020: @292235 |
| 115267 | GIM_Reject, |
| 115268 | // Label 8018: @292236 |
| 115269 | GIM_Reject, |
| 115270 | // Label 7979: @292237 |
| 115271 | GIM_Try, /*On fail goto*//*Label 8021*/ GIMT_Encode4(292357), |
| 115272 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 115273 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 115274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115275 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115276 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115277 | GIM_Try, /*On fail goto*//*Label 8022*/ GIMT_Encode4(292308), // Rule ID 54042 // |
| 115278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 115279 | // (strict_fadd:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFADD_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 115280 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 115281 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115282 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E64), |
| 115285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115286 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115287 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115288 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115293 | GIR_RootConstrainSelectedInstOperands, |
| 115294 | // GIR_Coverage, 54042, |
| 115295 | GIR_EraseRootFromParent_Done, |
| 115296 | // Label 8022: @292308 |
| 115297 | GIM_Try, /*On fail goto*//*Label 8023*/ GIMT_Encode4(292356), // Rule ID 54043 // |
| 115298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 115299 | // (strict_fadd:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFADD_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 115300 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 115301 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115302 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E64), |
| 115305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115306 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115307 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115308 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115313 | GIR_RootConstrainSelectedInstOperands, |
| 115314 | // GIR_Coverage, 54043, |
| 115315 | GIR_EraseRootFromParent_Done, |
| 115316 | // Label 8023: @292356 |
| 115317 | GIM_Reject, |
| 115318 | // Label 8021: @292357 |
| 115319 | GIM_Reject, |
| 115320 | // Label 7980: @292358 |
| 115321 | GIM_Try, /*On fail goto*//*Label 8024*/ GIMT_Encode4(292478), |
| 115322 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 115323 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 115324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115326 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 115327 | GIM_Try, /*On fail goto*//*Label 8025*/ GIMT_Encode4(292429), // Rule ID 53934 // |
| 115328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 115329 | // (strict_fadd:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFADD_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 115330 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 115331 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115332 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115333 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E16), |
| 115335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115336 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115337 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115338 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115343 | GIR_RootConstrainSelectedInstOperands, |
| 115344 | // GIR_Coverage, 53934, |
| 115345 | GIR_EraseRootFromParent_Done, |
| 115346 | // Label 8025: @292429 |
| 115347 | GIM_Try, /*On fail goto*//*Label 8026*/ GIMT_Encode4(292477), // Rule ID 53935 // |
| 115348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 115349 | // (strict_fadd:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFADD_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 115350 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 115351 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115352 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M1_E16), |
| 115355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115356 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115357 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115358 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115363 | GIR_RootConstrainSelectedInstOperands, |
| 115364 | // GIR_Coverage, 53935, |
| 115365 | GIR_EraseRootFromParent_Done, |
| 115366 | // Label 8026: @292477 |
| 115367 | GIM_Reject, |
| 115368 | // Label 8024: @292478 |
| 115369 | GIM_Reject, |
| 115370 | // Label 7981: @292479 |
| 115371 | GIM_Try, /*On fail goto*//*Label 8027*/ GIMT_Encode4(292599), |
| 115372 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 115373 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 115374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115375 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115377 | GIM_Try, /*On fail goto*//*Label 8028*/ GIMT_Encode4(292550), // Rule ID 54006 // |
| 115378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 115379 | // (strict_fadd:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFADD_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 115380 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 115381 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115382 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E32), |
| 115385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115386 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115387 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115388 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115393 | GIR_RootConstrainSelectedInstOperands, |
| 115394 | // GIR_Coverage, 54006, |
| 115395 | GIR_EraseRootFromParent_Done, |
| 115396 | // Label 8028: @292550 |
| 115397 | GIM_Try, /*On fail goto*//*Label 8029*/ GIMT_Encode4(292598), // Rule ID 54007 // |
| 115398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 115399 | // (strict_fadd:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFADD_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 115400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 115401 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115402 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E32), |
| 115405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115406 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115407 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115408 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115413 | GIR_RootConstrainSelectedInstOperands, |
| 115414 | // GIR_Coverage, 54007, |
| 115415 | GIR_EraseRootFromParent_Done, |
| 115416 | // Label 8029: @292598 |
| 115417 | GIM_Reject, |
| 115418 | // Label 8027: @292599 |
| 115419 | GIM_Reject, |
| 115420 | // Label 7982: @292600 |
| 115421 | GIM_Try, /*On fail goto*//*Label 8030*/ GIMT_Encode4(292720), |
| 115422 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 115423 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 115424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115425 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115426 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115427 | GIM_Try, /*On fail goto*//*Label 8031*/ GIMT_Encode4(292671), // Rule ID 54054 // |
| 115428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 115429 | // (strict_fadd:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFADD_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 115430 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 115431 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115432 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E64), |
| 115435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115436 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115437 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115438 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115443 | GIR_RootConstrainSelectedInstOperands, |
| 115444 | // GIR_Coverage, 54054, |
| 115445 | GIR_EraseRootFromParent_Done, |
| 115446 | // Label 8031: @292671 |
| 115447 | GIM_Try, /*On fail goto*//*Label 8032*/ GIMT_Encode4(292719), // Rule ID 54055 // |
| 115448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 115449 | // (strict_fadd:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFADD_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 115450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 115451 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115452 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E64), |
| 115455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115456 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115457 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115458 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115463 | GIR_RootConstrainSelectedInstOperands, |
| 115464 | // GIR_Coverage, 54055, |
| 115465 | GIR_EraseRootFromParent_Done, |
| 115466 | // Label 8032: @292719 |
| 115467 | GIM_Reject, |
| 115468 | // Label 8030: @292720 |
| 115469 | GIM_Reject, |
| 115470 | // Label 7983: @292721 |
| 115471 | GIM_Try, /*On fail goto*//*Label 8033*/ GIMT_Encode4(292841), |
| 115472 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 115473 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 115474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115475 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115476 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 115477 | GIM_Try, /*On fail goto*//*Label 8034*/ GIMT_Encode4(292792), // Rule ID 53970 // |
| 115478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 115479 | // (strict_fadd:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFADD_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 115480 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 115481 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115482 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E16), |
| 115485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115486 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115487 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115488 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115493 | GIR_RootConstrainSelectedInstOperands, |
| 115494 | // GIR_Coverage, 53970, |
| 115495 | GIR_EraseRootFromParent_Done, |
| 115496 | // Label 8034: @292792 |
| 115497 | GIM_Try, /*On fail goto*//*Label 8035*/ GIMT_Encode4(292840), // Rule ID 53971 // |
| 115498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 115499 | // (strict_fadd:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFADD_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 115500 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 115501 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115502 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115503 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M2_E16), |
| 115505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115506 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115507 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115508 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115513 | GIR_RootConstrainSelectedInstOperands, |
| 115514 | // GIR_Coverage, 53971, |
| 115515 | GIR_EraseRootFromParent_Done, |
| 115516 | // Label 8035: @292840 |
| 115517 | GIM_Reject, |
| 115518 | // Label 8033: @292841 |
| 115519 | GIM_Reject, |
| 115520 | // Label 7984: @292842 |
| 115521 | GIM_Try, /*On fail goto*//*Label 8036*/ GIMT_Encode4(292962), |
| 115522 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 115523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 115524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115525 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115526 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115527 | GIM_Try, /*On fail goto*//*Label 8037*/ GIMT_Encode4(292913), // Rule ID 54018 // |
| 115528 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 115529 | // (strict_fadd:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFADD_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 115530 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 115531 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115532 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115533 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E32), |
| 115535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115536 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115537 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115538 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115543 | GIR_RootConstrainSelectedInstOperands, |
| 115544 | // GIR_Coverage, 54018, |
| 115545 | GIR_EraseRootFromParent_Done, |
| 115546 | // Label 8037: @292913 |
| 115547 | GIM_Try, /*On fail goto*//*Label 8038*/ GIMT_Encode4(292961), // Rule ID 54019 // |
| 115548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 115549 | // (strict_fadd:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFADD_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 115550 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 115551 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115552 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E32), |
| 115555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115556 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115557 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115558 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115563 | GIR_RootConstrainSelectedInstOperands, |
| 115564 | // GIR_Coverage, 54019, |
| 115565 | GIR_EraseRootFromParent_Done, |
| 115566 | // Label 8038: @292961 |
| 115567 | GIM_Reject, |
| 115568 | // Label 8036: @292962 |
| 115569 | GIM_Reject, |
| 115570 | // Label 7985: @292963 |
| 115571 | GIM_Try, /*On fail goto*//*Label 8039*/ GIMT_Encode4(293083), |
| 115572 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 115573 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 115574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115575 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115576 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115577 | GIM_Try, /*On fail goto*//*Label 8040*/ GIMT_Encode4(293034), // Rule ID 54066 // |
| 115578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 115579 | // (strict_fadd:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFADD_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 115580 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 115581 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115582 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E64), |
| 115585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115586 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115587 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115588 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115593 | GIR_RootConstrainSelectedInstOperands, |
| 115594 | // GIR_Coverage, 54066, |
| 115595 | GIR_EraseRootFromParent_Done, |
| 115596 | // Label 8040: @293034 |
| 115597 | GIM_Try, /*On fail goto*//*Label 8041*/ GIMT_Encode4(293082), // Rule ID 54067 // |
| 115598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 115599 | // (strict_fadd:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFADD_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 115600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 115601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115602 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E64), |
| 115605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115606 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115607 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115608 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 115612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115613 | GIR_RootConstrainSelectedInstOperands, |
| 115614 | // GIR_Coverage, 54067, |
| 115615 | GIR_EraseRootFromParent_Done, |
| 115616 | // Label 8041: @293082 |
| 115617 | GIM_Reject, |
| 115618 | // Label 8039: @293083 |
| 115619 | GIM_Reject, |
| 115620 | // Label 7986: @293084 |
| 115621 | GIM_Try, /*On fail goto*//*Label 8042*/ GIMT_Encode4(293204), |
| 115622 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 115623 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 115624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115626 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 115627 | GIM_Try, /*On fail goto*//*Label 8043*/ GIMT_Encode4(293155), // Rule ID 53982 // |
| 115628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 115629 | // (strict_fadd:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFADD_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 115630 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 115631 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115632 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E16), |
| 115635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115637 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115638 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115643 | GIR_RootConstrainSelectedInstOperands, |
| 115644 | // GIR_Coverage, 53982, |
| 115645 | GIR_EraseRootFromParent_Done, |
| 115646 | // Label 8043: @293155 |
| 115647 | GIM_Try, /*On fail goto*//*Label 8044*/ GIMT_Encode4(293203), // Rule ID 53983 // |
| 115648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 115649 | // (strict_fadd:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFADD_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 115650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 115651 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115652 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M4_E16), |
| 115655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115656 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115657 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115658 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115663 | GIR_RootConstrainSelectedInstOperands, |
| 115664 | // GIR_Coverage, 53983, |
| 115665 | GIR_EraseRootFromParent_Done, |
| 115666 | // Label 8044: @293203 |
| 115667 | GIM_Reject, |
| 115668 | // Label 8042: @293204 |
| 115669 | GIM_Reject, |
| 115670 | // Label 7987: @293205 |
| 115671 | GIM_Try, /*On fail goto*//*Label 8045*/ GIMT_Encode4(293325), |
| 115672 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 115673 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 115674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115675 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115676 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115677 | GIM_Try, /*On fail goto*//*Label 8046*/ GIMT_Encode4(293276), // Rule ID 54030 // |
| 115678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 115679 | // (strict_fadd:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFADD_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 115680 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 115681 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115682 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115683 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E32), |
| 115685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115686 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115687 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115688 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115693 | GIR_RootConstrainSelectedInstOperands, |
| 115694 | // GIR_Coverage, 54030, |
| 115695 | GIR_EraseRootFromParent_Done, |
| 115696 | // Label 8046: @293276 |
| 115697 | GIM_Try, /*On fail goto*//*Label 8047*/ GIMT_Encode4(293324), // Rule ID 54031 // |
| 115698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 115699 | // (strict_fadd:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFADD_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 115700 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 115701 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115702 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E32), |
| 115705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115706 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115707 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115708 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 115712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115713 | GIR_RootConstrainSelectedInstOperands, |
| 115714 | // GIR_Coverage, 54031, |
| 115715 | GIR_EraseRootFromParent_Done, |
| 115716 | // Label 8047: @293324 |
| 115717 | GIM_Reject, |
| 115718 | // Label 8045: @293325 |
| 115719 | GIM_Reject, |
| 115720 | // Label 7988: @293326 |
| 115721 | GIM_Try, /*On fail goto*//*Label 8048*/ GIMT_Encode4(293446), |
| 115722 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 115723 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 115724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115725 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115726 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 115727 | GIM_Try, /*On fail goto*//*Label 8049*/ GIMT_Encode4(293397), // Rule ID 53994 // |
| 115728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 115729 | // (strict_fadd:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFADD_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 115730 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 115731 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115732 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E16), |
| 115735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115736 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115737 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115738 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115743 | GIR_RootConstrainSelectedInstOperands, |
| 115744 | // GIR_Coverage, 53994, |
| 115745 | GIR_EraseRootFromParent_Done, |
| 115746 | // Label 8049: @293397 |
| 115747 | GIM_Try, /*On fail goto*//*Label 8050*/ GIMT_Encode4(293445), // Rule ID 53995 // |
| 115748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 115749 | // (strict_fadd:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFADD_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 115750 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 115751 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 115752 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 115753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 115754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFADD_VV_M8_E16), |
| 115755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115756 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 115757 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115758 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 115761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 115762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 115763 | GIR_RootConstrainSelectedInstOperands, |
| 115764 | // GIR_Coverage, 53995, |
| 115765 | GIR_EraseRootFromParent_Done, |
| 115766 | // Label 8050: @293445 |
| 115767 | GIM_Reject, |
| 115768 | // Label 8048: @293446 |
| 115769 | GIM_Reject, |
| 115770 | // Label 7989: @293447 |
| 115771 | GIM_Reject, |
| 115772 | // Label 90: @293448 |
| 115773 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 8069*/ GIMT_Encode4(295875), |
| 115774 | /*GILLT_s16*//*Label 8051*/ GIMT_Encode4(293579), |
| 115775 | /*GILLT_s32*//*Label 8052*/ GIMT_Encode4(293728), |
| 115776 | /*GILLT_s64*//*Label 8053*/ GIMT_Encode4(293877), GIMT_Encode4(0), GIMT_Encode4(0), |
| 115777 | /*GILLT_nxv1s16*//*Label 8054*/ GIMT_Encode4(294060), |
| 115778 | /*GILLT_nxv1s32*//*Label 8055*/ GIMT_Encode4(294181), |
| 115779 | /*GILLT_nxv1s64*//*Label 8056*/ GIMT_Encode4(294302), GIMT_Encode4(0), GIMT_Encode4(0), |
| 115780 | /*GILLT_nxv2s16*//*Label 8057*/ GIMT_Encode4(294423), |
| 115781 | /*GILLT_nxv2s32*//*Label 8058*/ GIMT_Encode4(294544), |
| 115782 | /*GILLT_nxv2s64*//*Label 8059*/ GIMT_Encode4(294665), GIMT_Encode4(0), GIMT_Encode4(0), |
| 115783 | /*GILLT_nxv4s16*//*Label 8060*/ GIMT_Encode4(294786), |
| 115784 | /*GILLT_nxv4s32*//*Label 8061*/ GIMT_Encode4(294907), |
| 115785 | /*GILLT_nxv4s64*//*Label 8062*/ GIMT_Encode4(295028), GIMT_Encode4(0), GIMT_Encode4(0), |
| 115786 | /*GILLT_nxv8s16*//*Label 8063*/ GIMT_Encode4(295149), |
| 115787 | /*GILLT_nxv8s32*//*Label 8064*/ GIMT_Encode4(295270), |
| 115788 | /*GILLT_nxv8s64*//*Label 8065*/ GIMT_Encode4(295391), GIMT_Encode4(0), GIMT_Encode4(0), |
| 115789 | /*GILLT_nxv16s16*//*Label 8066*/ GIMT_Encode4(295512), |
| 115790 | /*GILLT_nxv16s32*//*Label 8067*/ GIMT_Encode4(295633), GIMT_Encode4(0), GIMT_Encode4(0), |
| 115791 | /*GILLT_nxv32s16*//*Label 8068*/ GIMT_Encode4(295754), |
| 115792 | // Label 8051: @293579 |
| 115793 | GIM_Try, /*On fail goto*//*Label 8070*/ GIMT_Encode4(293727), |
| 115794 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 115795 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 115796 | GIM_Try, /*On fail goto*//*Label 8071*/ GIMT_Encode4(293624), // Rule ID 2018 // |
| 115797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 115798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 115799 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 115800 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 115801 | // (strict_fsub:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSUB_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 115802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H), |
| 115803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115804 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115805 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115807 | GIR_RootConstrainSelectedInstOperands, |
| 115808 | // GIR_Coverage, 2018, |
| 115809 | GIR_EraseRootFromParent_Done, |
| 115810 | // Label 8071: @293624 |
| 115811 | GIM_Try, /*On fail goto*//*Label 8072*/ GIMT_Encode4(293658), // Rule ID 2019 // |
| 115812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 115813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 115814 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 115815 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 115816 | // (strict_fsub:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FSUB_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 115817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H), |
| 115818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115819 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115820 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115822 | GIR_RootConstrainSelectedInstOperands, |
| 115823 | // GIR_Coverage, 2019, |
| 115824 | GIR_EraseRootFromParent_Done, |
| 115825 | // Label 8072: @293658 |
| 115826 | GIM_Try, /*On fail goto*//*Label 8073*/ GIMT_Encode4(293692), // Rule ID 2022 // |
| 115827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 115828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 115829 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 115830 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 115831 | // (strict_fsub:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSUB_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 115832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H_INX), |
| 115833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115834 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115835 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115837 | GIR_RootConstrainSelectedInstOperands, |
| 115838 | // GIR_Coverage, 2022, |
| 115839 | GIR_EraseRootFromParent_Done, |
| 115840 | // Label 8073: @293692 |
| 115841 | GIM_Try, /*On fail goto*//*Label 8074*/ GIMT_Encode4(293726), // Rule ID 2023 // |
| 115842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 115843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 115844 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 115845 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 115846 | // (strict_fsub:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FSUB_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 115847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_H_INX), |
| 115848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115849 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115850 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115852 | GIR_RootConstrainSelectedInstOperands, |
| 115853 | // GIR_Coverage, 2023, |
| 115854 | GIR_EraseRootFromParent_Done, |
| 115855 | // Label 8074: @293726 |
| 115856 | GIM_Reject, |
| 115857 | // Label 8070: @293727 |
| 115858 | GIM_Reject, |
| 115859 | // Label 8052: @293728 |
| 115860 | GIM_Try, /*On fail goto*//*Label 8075*/ GIMT_Encode4(293876), |
| 115861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 115862 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 115863 | GIM_Try, /*On fail goto*//*Label 8076*/ GIMT_Encode4(293773), // Rule ID 1330 // |
| 115864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 115865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 115866 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 115867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 115868 | // (strict_fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 115869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S), |
| 115870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115871 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115872 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115874 | GIR_RootConstrainSelectedInstOperands, |
| 115875 | // GIR_Coverage, 1330, |
| 115876 | GIR_EraseRootFromParent_Done, |
| 115877 | // Label 8076: @293773 |
| 115878 | GIM_Try, /*On fail goto*//*Label 8077*/ GIMT_Encode4(293807), // Rule ID 1331 // |
| 115879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 115880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 115881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 115882 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 115883 | // (strict_fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 115884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S), |
| 115885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115886 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115887 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115889 | GIR_RootConstrainSelectedInstOperands, |
| 115890 | // GIR_Coverage, 1331, |
| 115891 | GIR_EraseRootFromParent_Done, |
| 115892 | // Label 8077: @293807 |
| 115893 | GIM_Try, /*On fail goto*//*Label 8078*/ GIMT_Encode4(293841), // Rule ID 1334 // |
| 115894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 115895 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 115896 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 115897 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 115898 | // (strict_fsub:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSUB_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 115899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S_INX), |
| 115900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115901 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115902 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115904 | GIR_RootConstrainSelectedInstOperands, |
| 115905 | // GIR_Coverage, 1334, |
| 115906 | GIR_EraseRootFromParent_Done, |
| 115907 | // Label 8078: @293841 |
| 115908 | GIM_Try, /*On fail goto*//*Label 8079*/ GIMT_Encode4(293875), // Rule ID 1335 // |
| 115909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 115910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 115911 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 115912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 115913 | // (strict_fsub:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FSUB_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 115914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_S_INX), |
| 115915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115916 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115917 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115919 | GIR_RootConstrainSelectedInstOperands, |
| 115920 | // GIR_Coverage, 1335, |
| 115921 | GIR_EraseRootFromParent_Done, |
| 115922 | // Label 8079: @293875 |
| 115923 | GIM_Reject, |
| 115924 | // Label 8075: @293876 |
| 115925 | GIM_Reject, |
| 115926 | // Label 8053: @293877 |
| 115927 | GIM_Try, /*On fail goto*//*Label 8080*/ GIMT_Encode4(294059), |
| 115928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 115929 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 115930 | GIM_Try, /*On fail goto*//*Label 8081*/ GIMT_Encode4(293922), // Rule ID 1659 // |
| 115931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 115932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 115933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 115934 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 115935 | // (strict_fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 115936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D), |
| 115937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115938 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115939 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115941 | GIR_RootConstrainSelectedInstOperands, |
| 115942 | // GIR_Coverage, 1659, |
| 115943 | GIR_EraseRootFromParent_Done, |
| 115944 | // Label 8081: @293922 |
| 115945 | GIM_Try, /*On fail goto*//*Label 8082*/ GIMT_Encode4(293956), // Rule ID 1660 // |
| 115946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 115947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 115948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 115949 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 115950 | // (strict_fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 115951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D), |
| 115952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115953 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115954 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115956 | GIR_RootConstrainSelectedInstOperands, |
| 115957 | // GIR_Coverage, 1660, |
| 115958 | GIR_EraseRootFromParent_Done, |
| 115959 | // Label 8082: @293956 |
| 115960 | GIM_Try, /*On fail goto*//*Label 8083*/ GIMT_Encode4(293990), // Rule ID 1663 // |
| 115961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 115962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 115963 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 115964 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 115965 | // (strict_fsub:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSUB_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 115966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D_IN32X), |
| 115967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115968 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115969 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115971 | GIR_RootConstrainSelectedInstOperands, |
| 115972 | // GIR_Coverage, 1663, |
| 115973 | GIR_EraseRootFromParent_Done, |
| 115974 | // Label 8083: @293990 |
| 115975 | GIM_Try, /*On fail goto*//*Label 8084*/ GIMT_Encode4(294024), // Rule ID 1664 // |
| 115976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 115977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 115978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 115979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 115980 | // (strict_fsub:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FSUB_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 115981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D_IN32X), |
| 115982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115983 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115984 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 115985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 115986 | GIR_RootConstrainSelectedInstOperands, |
| 115987 | // GIR_Coverage, 1664, |
| 115988 | GIR_EraseRootFromParent_Done, |
| 115989 | // Label 8084: @294024 |
| 115990 | GIM_Try, /*On fail goto*//*Label 8085*/ GIMT_Encode4(294058), // Rule ID 1667 // |
| 115991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 115992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 115993 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 115994 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 115995 | // (strict_fsub:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FSUB_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 115996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSUB_D_INX), |
| 115997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 115998 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 115999 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116001 | GIR_RootConstrainSelectedInstOperands, |
| 116002 | // GIR_Coverage, 1667, |
| 116003 | GIR_EraseRootFromParent_Done, |
| 116004 | // Label 8085: @294058 |
| 116005 | GIM_Reject, |
| 116006 | // Label 8080: @294059 |
| 116007 | GIM_Reject, |
| 116008 | // Label 8054: @294060 |
| 116009 | GIM_Try, /*On fail goto*//*Label 8086*/ GIMT_Encode4(294180), |
| 116010 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 116011 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 116012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116013 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116014 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116015 | GIM_Try, /*On fail goto*//*Label 8087*/ GIMT_Encode4(294131), // Rule ID 54078 // |
| 116016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 116017 | // (strict_fsub:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSUB_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 116018 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 116019 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116020 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116021 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF4_E16), |
| 116023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116024 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116025 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116026 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116031 | GIR_RootConstrainSelectedInstOperands, |
| 116032 | // GIR_Coverage, 54078, |
| 116033 | GIR_EraseRootFromParent_Done, |
| 116034 | // Label 8087: @294131 |
| 116035 | GIM_Try, /*On fail goto*//*Label 8088*/ GIMT_Encode4(294179), // Rule ID 54079 // |
| 116036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 116037 | // (strict_fsub:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSUB_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 116038 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 116039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116040 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF4_E16), |
| 116043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116044 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116045 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116046 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116051 | GIR_RootConstrainSelectedInstOperands, |
| 116052 | // GIR_Coverage, 54079, |
| 116053 | GIR_EraseRootFromParent_Done, |
| 116054 | // Label 8088: @294179 |
| 116055 | GIM_Reject, |
| 116056 | // Label 8086: @294180 |
| 116057 | GIM_Reject, |
| 116058 | // Label 8055: @294181 |
| 116059 | GIM_Try, /*On fail goto*//*Label 8089*/ GIMT_Encode4(294301), |
| 116060 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 116061 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 116062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116064 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116065 | GIM_Try, /*On fail goto*//*Label 8090*/ GIMT_Encode4(294252), // Rule ID 54102 // |
| 116066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 116067 | // (strict_fsub:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSUB_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 116068 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 116069 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116070 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E32), |
| 116073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116074 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116075 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116076 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116081 | GIR_RootConstrainSelectedInstOperands, |
| 116082 | // GIR_Coverage, 54102, |
| 116083 | GIR_EraseRootFromParent_Done, |
| 116084 | // Label 8090: @294252 |
| 116085 | GIM_Try, /*On fail goto*//*Label 8091*/ GIMT_Encode4(294300), // Rule ID 54103 // |
| 116086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 116087 | // (strict_fsub:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSUB_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 116088 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 116089 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116090 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E32), |
| 116093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116095 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116096 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116101 | GIR_RootConstrainSelectedInstOperands, |
| 116102 | // GIR_Coverage, 54103, |
| 116103 | GIR_EraseRootFromParent_Done, |
| 116104 | // Label 8091: @294300 |
| 116105 | GIM_Reject, |
| 116106 | // Label 8089: @294301 |
| 116107 | GIM_Reject, |
| 116108 | // Label 8056: @294302 |
| 116109 | GIM_Try, /*On fail goto*//*Label 8092*/ GIMT_Encode4(294422), |
| 116110 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 116111 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 116112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116114 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116115 | GIM_Try, /*On fail goto*//*Label 8093*/ GIMT_Encode4(294373), // Rule ID 54138 // |
| 116116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 116117 | // (strict_fsub:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSUB_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 116118 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 116119 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116120 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E64), |
| 116123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116124 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116125 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116126 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116131 | GIR_RootConstrainSelectedInstOperands, |
| 116132 | // GIR_Coverage, 54138, |
| 116133 | GIR_EraseRootFromParent_Done, |
| 116134 | // Label 8093: @294373 |
| 116135 | GIM_Try, /*On fail goto*//*Label 8094*/ GIMT_Encode4(294421), // Rule ID 54139 // |
| 116136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 116137 | // (strict_fsub:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSUB_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 116138 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 116139 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116140 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116141 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E64), |
| 116143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116144 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116145 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116146 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116151 | GIR_RootConstrainSelectedInstOperands, |
| 116152 | // GIR_Coverage, 54139, |
| 116153 | GIR_EraseRootFromParent_Done, |
| 116154 | // Label 8094: @294421 |
| 116155 | GIM_Reject, |
| 116156 | // Label 8092: @294422 |
| 116157 | GIM_Reject, |
| 116158 | // Label 8057: @294423 |
| 116159 | GIM_Try, /*On fail goto*//*Label 8095*/ GIMT_Encode4(294543), |
| 116160 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 116161 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 116162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116164 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116165 | GIM_Try, /*On fail goto*//*Label 8096*/ GIMT_Encode4(294494), // Rule ID 54090 // |
| 116166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 116167 | // (strict_fsub:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSUB_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 116168 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 116169 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116170 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116171 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E16), |
| 116173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116174 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116175 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116176 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116181 | GIR_RootConstrainSelectedInstOperands, |
| 116182 | // GIR_Coverage, 54090, |
| 116183 | GIR_EraseRootFromParent_Done, |
| 116184 | // Label 8096: @294494 |
| 116185 | GIM_Try, /*On fail goto*//*Label 8097*/ GIMT_Encode4(294542), // Rule ID 54091 // |
| 116186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 116187 | // (strict_fsub:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSUB_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 116188 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 116189 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116190 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_MF2_E16), |
| 116193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116194 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116195 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116196 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116201 | GIR_RootConstrainSelectedInstOperands, |
| 116202 | // GIR_Coverage, 54091, |
| 116203 | GIR_EraseRootFromParent_Done, |
| 116204 | // Label 8097: @294542 |
| 116205 | GIM_Reject, |
| 116206 | // Label 8095: @294543 |
| 116207 | GIM_Reject, |
| 116208 | // Label 8058: @294544 |
| 116209 | GIM_Try, /*On fail goto*//*Label 8098*/ GIMT_Encode4(294664), |
| 116210 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 116211 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 116212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116213 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116215 | GIM_Try, /*On fail goto*//*Label 8099*/ GIMT_Encode4(294615), // Rule ID 54126 // |
| 116216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 116217 | // (strict_fsub:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSUB_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 116218 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 116219 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116220 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E32), |
| 116223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116224 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116225 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116226 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116231 | GIR_RootConstrainSelectedInstOperands, |
| 116232 | // GIR_Coverage, 54126, |
| 116233 | GIR_EraseRootFromParent_Done, |
| 116234 | // Label 8099: @294615 |
| 116235 | GIM_Try, /*On fail goto*//*Label 8100*/ GIMT_Encode4(294663), // Rule ID 54127 // |
| 116236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 116237 | // (strict_fsub:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSUB_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 116238 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 116239 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116240 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E32), |
| 116243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116244 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116245 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116246 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116251 | GIR_RootConstrainSelectedInstOperands, |
| 116252 | // GIR_Coverage, 54127, |
| 116253 | GIR_EraseRootFromParent_Done, |
| 116254 | // Label 8100: @294663 |
| 116255 | GIM_Reject, |
| 116256 | // Label 8098: @294664 |
| 116257 | GIM_Reject, |
| 116258 | // Label 8059: @294665 |
| 116259 | GIM_Try, /*On fail goto*//*Label 8101*/ GIMT_Encode4(294785), |
| 116260 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 116261 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 116262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116263 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116265 | GIM_Try, /*On fail goto*//*Label 8102*/ GIMT_Encode4(294736), // Rule ID 54222 // |
| 116266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 116267 | // (strict_fsub:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSUB_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 116268 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 116269 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E64), |
| 116273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116274 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116275 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116276 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116281 | GIR_RootConstrainSelectedInstOperands, |
| 116282 | // GIR_Coverage, 54222, |
| 116283 | GIR_EraseRootFromParent_Done, |
| 116284 | // Label 8102: @294736 |
| 116285 | GIM_Try, /*On fail goto*//*Label 8103*/ GIMT_Encode4(294784), // Rule ID 54223 // |
| 116286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 116287 | // (strict_fsub:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSUB_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 116288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 116289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E64), |
| 116293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116295 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116296 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116301 | GIR_RootConstrainSelectedInstOperands, |
| 116302 | // GIR_Coverage, 54223, |
| 116303 | GIR_EraseRootFromParent_Done, |
| 116304 | // Label 8103: @294784 |
| 116305 | GIM_Reject, |
| 116306 | // Label 8101: @294785 |
| 116307 | GIM_Reject, |
| 116308 | // Label 8060: @294786 |
| 116309 | GIM_Try, /*On fail goto*//*Label 8104*/ GIMT_Encode4(294906), |
| 116310 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 116311 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 116312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116313 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116314 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 116315 | GIM_Try, /*On fail goto*//*Label 8105*/ GIMT_Encode4(294857), // Rule ID 54114 // |
| 116316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 116317 | // (strict_fsub:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSUB_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 116318 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 116319 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116320 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E16), |
| 116323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116324 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116325 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116326 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116331 | GIR_RootConstrainSelectedInstOperands, |
| 116332 | // GIR_Coverage, 54114, |
| 116333 | GIR_EraseRootFromParent_Done, |
| 116334 | // Label 8105: @294857 |
| 116335 | GIM_Try, /*On fail goto*//*Label 8106*/ GIMT_Encode4(294905), // Rule ID 54115 // |
| 116336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 116337 | // (strict_fsub:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSUB_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 116338 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 116339 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116340 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116341 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M1_E16), |
| 116343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116344 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116345 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116346 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116351 | GIR_RootConstrainSelectedInstOperands, |
| 116352 | // GIR_Coverage, 54115, |
| 116353 | GIR_EraseRootFromParent_Done, |
| 116354 | // Label 8106: @294905 |
| 116355 | GIM_Reject, |
| 116356 | // Label 8104: @294906 |
| 116357 | GIM_Reject, |
| 116358 | // Label 8061: @294907 |
| 116359 | GIM_Try, /*On fail goto*//*Label 8107*/ GIMT_Encode4(295027), |
| 116360 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 116361 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 116362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116363 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116364 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116365 | GIM_Try, /*On fail goto*//*Label 8108*/ GIMT_Encode4(294978), // Rule ID 54186 // |
| 116366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 116367 | // (strict_fsub:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSUB_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 116368 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 116369 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116370 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E32), |
| 116373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116374 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116375 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116376 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116381 | GIR_RootConstrainSelectedInstOperands, |
| 116382 | // GIR_Coverage, 54186, |
| 116383 | GIR_EraseRootFromParent_Done, |
| 116384 | // Label 8108: @294978 |
| 116385 | GIM_Try, /*On fail goto*//*Label 8109*/ GIMT_Encode4(295026), // Rule ID 54187 // |
| 116386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 116387 | // (strict_fsub:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSUB_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 116388 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 116389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E32), |
| 116393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116394 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116395 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116396 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116401 | GIR_RootConstrainSelectedInstOperands, |
| 116402 | // GIR_Coverage, 54187, |
| 116403 | GIR_EraseRootFromParent_Done, |
| 116404 | // Label 8109: @295026 |
| 116405 | GIM_Reject, |
| 116406 | // Label 8107: @295027 |
| 116407 | GIM_Reject, |
| 116408 | // Label 8062: @295028 |
| 116409 | GIM_Try, /*On fail goto*//*Label 8110*/ GIMT_Encode4(295148), |
| 116410 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 116411 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 116412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116413 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116414 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116415 | GIM_Try, /*On fail goto*//*Label 8111*/ GIMT_Encode4(295099), // Rule ID 54234 // |
| 116416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 116417 | // (strict_fsub:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSUB_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 116418 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 116419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E64), |
| 116423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116424 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116425 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116426 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116431 | GIR_RootConstrainSelectedInstOperands, |
| 116432 | // GIR_Coverage, 54234, |
| 116433 | GIR_EraseRootFromParent_Done, |
| 116434 | // Label 8111: @295099 |
| 116435 | GIM_Try, /*On fail goto*//*Label 8112*/ GIMT_Encode4(295147), // Rule ID 54235 // |
| 116436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 116437 | // (strict_fsub:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSUB_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 116438 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 116439 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116440 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116441 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E64), |
| 116443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116444 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116445 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116446 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116451 | GIR_RootConstrainSelectedInstOperands, |
| 116452 | // GIR_Coverage, 54235, |
| 116453 | GIR_EraseRootFromParent_Done, |
| 116454 | // Label 8112: @295147 |
| 116455 | GIM_Reject, |
| 116456 | // Label 8110: @295148 |
| 116457 | GIM_Reject, |
| 116458 | // Label 8063: @295149 |
| 116459 | GIM_Try, /*On fail goto*//*Label 8113*/ GIMT_Encode4(295269), |
| 116460 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 116461 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 116462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116463 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116464 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 116465 | GIM_Try, /*On fail goto*//*Label 8114*/ GIMT_Encode4(295220), // Rule ID 54150 // |
| 116466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 116467 | // (strict_fsub:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSUB_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 116468 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 116469 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116470 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E16), |
| 116473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116474 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116475 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116476 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116481 | GIR_RootConstrainSelectedInstOperands, |
| 116482 | // GIR_Coverage, 54150, |
| 116483 | GIR_EraseRootFromParent_Done, |
| 116484 | // Label 8114: @295220 |
| 116485 | GIM_Try, /*On fail goto*//*Label 8115*/ GIMT_Encode4(295268), // Rule ID 54151 // |
| 116486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 116487 | // (strict_fsub:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSUB_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 116488 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 116489 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116490 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M2_E16), |
| 116493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116494 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116495 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116496 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116501 | GIR_RootConstrainSelectedInstOperands, |
| 116502 | // GIR_Coverage, 54151, |
| 116503 | GIR_EraseRootFromParent_Done, |
| 116504 | // Label 8115: @295268 |
| 116505 | GIM_Reject, |
| 116506 | // Label 8113: @295269 |
| 116507 | GIM_Reject, |
| 116508 | // Label 8064: @295270 |
| 116509 | GIM_Try, /*On fail goto*//*Label 8116*/ GIMT_Encode4(295390), |
| 116510 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 116511 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 116512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116513 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116514 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116515 | GIM_Try, /*On fail goto*//*Label 8117*/ GIMT_Encode4(295341), // Rule ID 54198 // |
| 116516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 116517 | // (strict_fsub:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSUB_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 116518 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 116519 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116520 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116521 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E32), |
| 116523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116524 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116525 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116526 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116531 | GIR_RootConstrainSelectedInstOperands, |
| 116532 | // GIR_Coverage, 54198, |
| 116533 | GIR_EraseRootFromParent_Done, |
| 116534 | // Label 8117: @295341 |
| 116535 | GIM_Try, /*On fail goto*//*Label 8118*/ GIMT_Encode4(295389), // Rule ID 54199 // |
| 116536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 116537 | // (strict_fsub:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSUB_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 116538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 116539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E32), |
| 116543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116545 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116546 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116551 | GIR_RootConstrainSelectedInstOperands, |
| 116552 | // GIR_Coverage, 54199, |
| 116553 | GIR_EraseRootFromParent_Done, |
| 116554 | // Label 8118: @295389 |
| 116555 | GIM_Reject, |
| 116556 | // Label 8116: @295390 |
| 116557 | GIM_Reject, |
| 116558 | // Label 8065: @295391 |
| 116559 | GIM_Try, /*On fail goto*//*Label 8119*/ GIMT_Encode4(295511), |
| 116560 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 116561 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 116562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116563 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116564 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116565 | GIM_Try, /*On fail goto*//*Label 8120*/ GIMT_Encode4(295462), // Rule ID 54246 // |
| 116566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 116567 | // (strict_fsub:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSUB_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 116568 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 116569 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116570 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E64), |
| 116573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116574 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116575 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116576 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116581 | GIR_RootConstrainSelectedInstOperands, |
| 116582 | // GIR_Coverage, 54246, |
| 116583 | GIR_EraseRootFromParent_Done, |
| 116584 | // Label 8120: @295462 |
| 116585 | GIM_Try, /*On fail goto*//*Label 8121*/ GIMT_Encode4(295510), // Rule ID 54247 // |
| 116586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 116587 | // (strict_fsub:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSUB_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 116588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 116589 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116590 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E64), |
| 116593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116595 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116596 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 116600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116601 | GIR_RootConstrainSelectedInstOperands, |
| 116602 | // GIR_Coverage, 54247, |
| 116603 | GIR_EraseRootFromParent_Done, |
| 116604 | // Label 8121: @295510 |
| 116605 | GIM_Reject, |
| 116606 | // Label 8119: @295511 |
| 116607 | GIM_Reject, |
| 116608 | // Label 8066: @295512 |
| 116609 | GIM_Try, /*On fail goto*//*Label 8122*/ GIMT_Encode4(295632), |
| 116610 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 116611 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 116612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116613 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116614 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 116615 | GIM_Try, /*On fail goto*//*Label 8123*/ GIMT_Encode4(295583), // Rule ID 54162 // |
| 116616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 116617 | // (strict_fsub:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSUB_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 116618 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 116619 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116620 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E16), |
| 116623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116624 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116625 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116626 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116631 | GIR_RootConstrainSelectedInstOperands, |
| 116632 | // GIR_Coverage, 54162, |
| 116633 | GIR_EraseRootFromParent_Done, |
| 116634 | // Label 8123: @295583 |
| 116635 | GIM_Try, /*On fail goto*//*Label 8124*/ GIMT_Encode4(295631), // Rule ID 54163 // |
| 116636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 116637 | // (strict_fsub:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSUB_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 116638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 116639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M4_E16), |
| 116643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116645 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116646 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116651 | GIR_RootConstrainSelectedInstOperands, |
| 116652 | // GIR_Coverage, 54163, |
| 116653 | GIR_EraseRootFromParent_Done, |
| 116654 | // Label 8124: @295631 |
| 116655 | GIM_Reject, |
| 116656 | // Label 8122: @295632 |
| 116657 | GIM_Reject, |
| 116658 | // Label 8067: @295633 |
| 116659 | GIM_Try, /*On fail goto*//*Label 8125*/ GIMT_Encode4(295753), |
| 116660 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 116661 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 116662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116664 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116665 | GIM_Try, /*On fail goto*//*Label 8126*/ GIMT_Encode4(295704), // Rule ID 54210 // |
| 116666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 116667 | // (strict_fsub:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSUB_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 116668 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 116669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116670 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E32), |
| 116673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116674 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116675 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116676 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116681 | GIR_RootConstrainSelectedInstOperands, |
| 116682 | // GIR_Coverage, 54210, |
| 116683 | GIR_EraseRootFromParent_Done, |
| 116684 | // Label 8126: @295704 |
| 116685 | GIM_Try, /*On fail goto*//*Label 8127*/ GIMT_Encode4(295752), // Rule ID 54211 // |
| 116686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 116687 | // (strict_fsub:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSUB_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 116688 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 116689 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116690 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E32), |
| 116693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116694 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116695 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116696 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 116700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116701 | GIR_RootConstrainSelectedInstOperands, |
| 116702 | // GIR_Coverage, 54211, |
| 116703 | GIR_EraseRootFromParent_Done, |
| 116704 | // Label 8127: @295752 |
| 116705 | GIM_Reject, |
| 116706 | // Label 8125: @295753 |
| 116707 | GIM_Reject, |
| 116708 | // Label 8068: @295754 |
| 116709 | GIM_Try, /*On fail goto*//*Label 8128*/ GIMT_Encode4(295874), |
| 116710 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 116711 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 116712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116713 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116714 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 116715 | GIM_Try, /*On fail goto*//*Label 8129*/ GIMT_Encode4(295825), // Rule ID 54174 // |
| 116716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 116717 | // (strict_fsub:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSUB_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 116718 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 116719 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116720 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E16), |
| 116723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116725 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116726 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116731 | GIR_RootConstrainSelectedInstOperands, |
| 116732 | // GIR_Coverage, 54174, |
| 116733 | GIR_EraseRootFromParent_Done, |
| 116734 | // Label 8129: @295825 |
| 116735 | GIM_Try, /*On fail goto*//*Label 8130*/ GIMT_Encode4(295873), // Rule ID 54175 // |
| 116736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 116737 | // (strict_fsub:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSUB_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 116738 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 116739 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 116740 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 116741 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 116742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSUB_VV_M8_E16), |
| 116743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116744 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 116745 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116746 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 116749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 116750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 116751 | GIR_RootConstrainSelectedInstOperands, |
| 116752 | // GIR_Coverage, 54175, |
| 116753 | GIR_EraseRootFromParent_Done, |
| 116754 | // Label 8130: @295873 |
| 116755 | GIM_Reject, |
| 116756 | // Label 8128: @295874 |
| 116757 | GIM_Reject, |
| 116758 | // Label 8069: @295875 |
| 116759 | GIM_Reject, |
| 116760 | // Label 91: @295876 |
| 116761 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 8149*/ GIMT_Encode4(298303), |
| 116762 | /*GILLT_s16*//*Label 8131*/ GIMT_Encode4(296007), |
| 116763 | /*GILLT_s32*//*Label 8132*/ GIMT_Encode4(296156), |
| 116764 | /*GILLT_s64*//*Label 8133*/ GIMT_Encode4(296305), GIMT_Encode4(0), GIMT_Encode4(0), |
| 116765 | /*GILLT_nxv1s16*//*Label 8134*/ GIMT_Encode4(296488), |
| 116766 | /*GILLT_nxv1s32*//*Label 8135*/ GIMT_Encode4(296609), |
| 116767 | /*GILLT_nxv1s64*//*Label 8136*/ GIMT_Encode4(296730), GIMT_Encode4(0), GIMT_Encode4(0), |
| 116768 | /*GILLT_nxv2s16*//*Label 8137*/ GIMT_Encode4(296851), |
| 116769 | /*GILLT_nxv2s32*//*Label 8138*/ GIMT_Encode4(296972), |
| 116770 | /*GILLT_nxv2s64*//*Label 8139*/ GIMT_Encode4(297093), GIMT_Encode4(0), GIMT_Encode4(0), |
| 116771 | /*GILLT_nxv4s16*//*Label 8140*/ GIMT_Encode4(297214), |
| 116772 | /*GILLT_nxv4s32*//*Label 8141*/ GIMT_Encode4(297335), |
| 116773 | /*GILLT_nxv4s64*//*Label 8142*/ GIMT_Encode4(297456), GIMT_Encode4(0), GIMT_Encode4(0), |
| 116774 | /*GILLT_nxv8s16*//*Label 8143*/ GIMT_Encode4(297577), |
| 116775 | /*GILLT_nxv8s32*//*Label 8144*/ GIMT_Encode4(297698), |
| 116776 | /*GILLT_nxv8s64*//*Label 8145*/ GIMT_Encode4(297819), GIMT_Encode4(0), GIMT_Encode4(0), |
| 116777 | /*GILLT_nxv16s16*//*Label 8146*/ GIMT_Encode4(297940), |
| 116778 | /*GILLT_nxv16s32*//*Label 8147*/ GIMT_Encode4(298061), GIMT_Encode4(0), GIMT_Encode4(0), |
| 116779 | /*GILLT_nxv32s16*//*Label 8148*/ GIMT_Encode4(298182), |
| 116780 | // Label 8131: @296007 |
| 116781 | GIM_Try, /*On fail goto*//*Label 8150*/ GIMT_Encode4(296155), |
| 116782 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 116783 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 116784 | GIM_Try, /*On fail goto*//*Label 8151*/ GIMT_Encode4(296052), // Rule ID 2026 // |
| 116785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 116786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 116787 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 116788 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 116789 | // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMUL_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 116790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H), |
| 116791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116792 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116793 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116795 | GIR_RootConstrainSelectedInstOperands, |
| 116796 | // GIR_Coverage, 2026, |
| 116797 | GIR_EraseRootFromParent_Done, |
| 116798 | // Label 8151: @296052 |
| 116799 | GIM_Try, /*On fail goto*//*Label 8152*/ GIMT_Encode4(296086), // Rule ID 2027 // |
| 116800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 116801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 116802 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 116803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 116804 | // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FMUL_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 116805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H), |
| 116806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116807 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116808 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116810 | GIR_RootConstrainSelectedInstOperands, |
| 116811 | // GIR_Coverage, 2027, |
| 116812 | GIR_EraseRootFromParent_Done, |
| 116813 | // Label 8152: @296086 |
| 116814 | GIM_Try, /*On fail goto*//*Label 8153*/ GIMT_Encode4(296120), // Rule ID 2030 // |
| 116815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 116816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 116817 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 116818 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 116819 | // (strict_fmul:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FMUL_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 116820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H_INX), |
| 116821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116822 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116823 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116825 | GIR_RootConstrainSelectedInstOperands, |
| 116826 | // GIR_Coverage, 2030, |
| 116827 | GIR_EraseRootFromParent_Done, |
| 116828 | // Label 8153: @296120 |
| 116829 | GIM_Try, /*On fail goto*//*Label 8154*/ GIMT_Encode4(296154), // Rule ID 2031 // |
| 116830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 116831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 116832 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 116833 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 116834 | // (strict_fmul:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FMUL_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 116835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_H_INX), |
| 116836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116837 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116838 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116840 | GIR_RootConstrainSelectedInstOperands, |
| 116841 | // GIR_Coverage, 2031, |
| 116842 | GIR_EraseRootFromParent_Done, |
| 116843 | // Label 8154: @296154 |
| 116844 | GIM_Reject, |
| 116845 | // Label 8150: @296155 |
| 116846 | GIM_Reject, |
| 116847 | // Label 8132: @296156 |
| 116848 | GIM_Try, /*On fail goto*//*Label 8155*/ GIMT_Encode4(296304), |
| 116849 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 116850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 116851 | GIM_Try, /*On fail goto*//*Label 8156*/ GIMT_Encode4(296201), // Rule ID 1338 // |
| 116852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 116853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 116854 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 116855 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 116856 | // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 116857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S), |
| 116858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116859 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116860 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116862 | GIR_RootConstrainSelectedInstOperands, |
| 116863 | // GIR_Coverage, 1338, |
| 116864 | GIR_EraseRootFromParent_Done, |
| 116865 | // Label 8156: @296201 |
| 116866 | GIM_Try, /*On fail goto*//*Label 8157*/ GIMT_Encode4(296235), // Rule ID 1339 // |
| 116867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 116868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 116869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 116870 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 116871 | // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 116872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S), |
| 116873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116874 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116875 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116877 | GIR_RootConstrainSelectedInstOperands, |
| 116878 | // GIR_Coverage, 1339, |
| 116879 | GIR_EraseRootFromParent_Done, |
| 116880 | // Label 8157: @296235 |
| 116881 | GIM_Try, /*On fail goto*//*Label 8158*/ GIMT_Encode4(296269), // Rule ID 1342 // |
| 116882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 116883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 116884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 116885 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 116886 | // (strict_fmul:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FMUL_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 116887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S_INX), |
| 116888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116889 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116890 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116892 | GIR_RootConstrainSelectedInstOperands, |
| 116893 | // GIR_Coverage, 1342, |
| 116894 | GIR_EraseRootFromParent_Done, |
| 116895 | // Label 8158: @296269 |
| 116896 | GIM_Try, /*On fail goto*//*Label 8159*/ GIMT_Encode4(296303), // Rule ID 1343 // |
| 116897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 116898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 116899 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 116900 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 116901 | // (strict_fmul:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FMUL_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 116902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_S_INX), |
| 116903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116904 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116905 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116907 | GIR_RootConstrainSelectedInstOperands, |
| 116908 | // GIR_Coverage, 1343, |
| 116909 | GIR_EraseRootFromParent_Done, |
| 116910 | // Label 8159: @296303 |
| 116911 | GIM_Reject, |
| 116912 | // Label 8155: @296304 |
| 116913 | GIM_Reject, |
| 116914 | // Label 8133: @296305 |
| 116915 | GIM_Try, /*On fail goto*//*Label 8160*/ GIMT_Encode4(296487), |
| 116916 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 116917 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 116918 | GIM_Try, /*On fail goto*//*Label 8161*/ GIMT_Encode4(296350), // Rule ID 1669 // |
| 116919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 116920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 116921 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 116922 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 116923 | // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 116924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D), |
| 116925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116926 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116927 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116929 | GIR_RootConstrainSelectedInstOperands, |
| 116930 | // GIR_Coverage, 1669, |
| 116931 | GIR_EraseRootFromParent_Done, |
| 116932 | // Label 8161: @296350 |
| 116933 | GIM_Try, /*On fail goto*//*Label 8162*/ GIMT_Encode4(296384), // Rule ID 1670 // |
| 116934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 116935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 116936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 116937 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 116938 | // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 116939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D), |
| 116940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116941 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116942 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116944 | GIR_RootConstrainSelectedInstOperands, |
| 116945 | // GIR_Coverage, 1670, |
| 116946 | GIR_EraseRootFromParent_Done, |
| 116947 | // Label 8162: @296384 |
| 116948 | GIM_Try, /*On fail goto*//*Label 8163*/ GIMT_Encode4(296418), // Rule ID 1673 // |
| 116949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 116950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 116951 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 116952 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 116953 | // (strict_fmul:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FMUL_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 116954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D_IN32X), |
| 116955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116956 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116957 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116959 | GIR_RootConstrainSelectedInstOperands, |
| 116960 | // GIR_Coverage, 1673, |
| 116961 | GIR_EraseRootFromParent_Done, |
| 116962 | // Label 8163: @296418 |
| 116963 | GIM_Try, /*On fail goto*//*Label 8164*/ GIMT_Encode4(296452), // Rule ID 1674 // |
| 116964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 116965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 116966 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 116967 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 116968 | // (strict_fmul:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FMUL_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 116969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D_IN32X), |
| 116970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116971 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116972 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116974 | GIR_RootConstrainSelectedInstOperands, |
| 116975 | // GIR_Coverage, 1674, |
| 116976 | GIR_EraseRootFromParent_Done, |
| 116977 | // Label 8164: @296452 |
| 116978 | GIM_Try, /*On fail goto*//*Label 8165*/ GIMT_Encode4(296486), // Rule ID 1677 // |
| 116979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 116980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 116981 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 116982 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 116983 | // (strict_fmul:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FMUL_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 116984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMUL_D_INX), |
| 116985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 116986 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 116987 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 116988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 116989 | GIR_RootConstrainSelectedInstOperands, |
| 116990 | // GIR_Coverage, 1677, |
| 116991 | GIR_EraseRootFromParent_Done, |
| 116992 | // Label 8165: @296486 |
| 116993 | GIM_Reject, |
| 116994 | // Label 8160: @296487 |
| 116995 | GIM_Reject, |
| 116996 | // Label 8134: @296488 |
| 116997 | GIM_Try, /*On fail goto*//*Label 8166*/ GIMT_Encode4(296608), |
| 116998 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 116999 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 117000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117002 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117003 | GIM_Try, /*On fail goto*//*Label 8167*/ GIMT_Encode4(296559), // Rule ID 54846 // |
| 117004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117005 | // (strict_fmul:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMUL_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117006 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 117007 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117008 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117009 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF4_E16), |
| 117011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117012 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117013 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117014 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117019 | GIR_RootConstrainSelectedInstOperands, |
| 117020 | // GIR_Coverage, 54846, |
| 117021 | GIR_EraseRootFromParent_Done, |
| 117022 | // Label 8167: @296559 |
| 117023 | GIM_Try, /*On fail goto*//*Label 8168*/ GIMT_Encode4(296607), // Rule ID 54847 // |
| 117024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 117025 | // (strict_fmul:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMUL_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 117026 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 117027 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117028 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF4_E16), |
| 117031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117032 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117033 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117034 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117039 | GIR_RootConstrainSelectedInstOperands, |
| 117040 | // GIR_Coverage, 54847, |
| 117041 | GIR_EraseRootFromParent_Done, |
| 117042 | // Label 8168: @296607 |
| 117043 | GIM_Reject, |
| 117044 | // Label 8166: @296608 |
| 117045 | GIM_Reject, |
| 117046 | // Label 8135: @296609 |
| 117047 | GIM_Try, /*On fail goto*//*Label 8169*/ GIMT_Encode4(296729), |
| 117048 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 117049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 117050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117051 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117052 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117053 | GIM_Try, /*On fail goto*//*Label 8170*/ GIMT_Encode4(296680), // Rule ID 54870 // |
| 117054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 117055 | // (strict_fmul:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMUL_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 117056 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 117057 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117058 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E32), |
| 117061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117063 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117064 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117069 | GIR_RootConstrainSelectedInstOperands, |
| 117070 | // GIR_Coverage, 54870, |
| 117071 | GIR_EraseRootFromParent_Done, |
| 117072 | // Label 8170: @296680 |
| 117073 | GIM_Try, /*On fail goto*//*Label 8171*/ GIMT_Encode4(296728), // Rule ID 54871 // |
| 117074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 117075 | // (strict_fmul:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMUL_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 117076 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 117077 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117078 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E32), |
| 117081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117082 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117083 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117084 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117089 | GIR_RootConstrainSelectedInstOperands, |
| 117090 | // GIR_Coverage, 54871, |
| 117091 | GIR_EraseRootFromParent_Done, |
| 117092 | // Label 8171: @296728 |
| 117093 | GIM_Reject, |
| 117094 | // Label 8169: @296729 |
| 117095 | GIM_Reject, |
| 117096 | // Label 8136: @296730 |
| 117097 | GIM_Try, /*On fail goto*//*Label 8172*/ GIMT_Encode4(296850), |
| 117098 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 117099 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 117100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117101 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117102 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117103 | GIM_Try, /*On fail goto*//*Label 8173*/ GIMT_Encode4(296801), // Rule ID 54906 // |
| 117104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 117105 | // (strict_fmul:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMUL_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 117106 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 117107 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117108 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E64), |
| 117111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117112 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117113 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117114 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117119 | GIR_RootConstrainSelectedInstOperands, |
| 117120 | // GIR_Coverage, 54906, |
| 117121 | GIR_EraseRootFromParent_Done, |
| 117122 | // Label 8173: @296801 |
| 117123 | GIM_Try, /*On fail goto*//*Label 8174*/ GIMT_Encode4(296849), // Rule ID 54907 // |
| 117124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 117125 | // (strict_fmul:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMUL_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 117126 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 117127 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117128 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117129 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E64), |
| 117131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117132 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117133 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117134 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117139 | GIR_RootConstrainSelectedInstOperands, |
| 117140 | // GIR_Coverage, 54907, |
| 117141 | GIR_EraseRootFromParent_Done, |
| 117142 | // Label 8174: @296849 |
| 117143 | GIM_Reject, |
| 117144 | // Label 8172: @296850 |
| 117145 | GIM_Reject, |
| 117146 | // Label 8137: @296851 |
| 117147 | GIM_Try, /*On fail goto*//*Label 8175*/ GIMT_Encode4(296971), |
| 117148 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 117149 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 117150 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117151 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117152 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117153 | GIM_Try, /*On fail goto*//*Label 8176*/ GIMT_Encode4(296922), // Rule ID 54858 // |
| 117154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117155 | // (strict_fmul:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMUL_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117156 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 117157 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117158 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E16), |
| 117161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117162 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117163 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117164 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117169 | GIR_RootConstrainSelectedInstOperands, |
| 117170 | // GIR_Coverage, 54858, |
| 117171 | GIR_EraseRootFromParent_Done, |
| 117172 | // Label 8176: @296922 |
| 117173 | GIM_Try, /*On fail goto*//*Label 8177*/ GIMT_Encode4(296970), // Rule ID 54859 // |
| 117174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 117175 | // (strict_fmul:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMUL_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 117176 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 117177 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117178 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_MF2_E16), |
| 117181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117182 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117183 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117184 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117189 | GIR_RootConstrainSelectedInstOperands, |
| 117190 | // GIR_Coverage, 54859, |
| 117191 | GIR_EraseRootFromParent_Done, |
| 117192 | // Label 8177: @296970 |
| 117193 | GIM_Reject, |
| 117194 | // Label 8175: @296971 |
| 117195 | GIM_Reject, |
| 117196 | // Label 8138: @296972 |
| 117197 | GIM_Try, /*On fail goto*//*Label 8178*/ GIMT_Encode4(297092), |
| 117198 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 117199 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 117200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117201 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117202 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117203 | GIM_Try, /*On fail goto*//*Label 8179*/ GIMT_Encode4(297043), // Rule ID 54894 // |
| 117204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 117205 | // (strict_fmul:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMUL_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 117206 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 117207 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117208 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117209 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E32), |
| 117211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117212 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117213 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117214 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117219 | GIR_RootConstrainSelectedInstOperands, |
| 117220 | // GIR_Coverage, 54894, |
| 117221 | GIR_EraseRootFromParent_Done, |
| 117222 | // Label 8179: @297043 |
| 117223 | GIM_Try, /*On fail goto*//*Label 8180*/ GIMT_Encode4(297091), // Rule ID 54895 // |
| 117224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 117225 | // (strict_fmul:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMUL_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 117226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 117227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E32), |
| 117231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117232 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117233 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117234 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117239 | GIR_RootConstrainSelectedInstOperands, |
| 117240 | // GIR_Coverage, 54895, |
| 117241 | GIR_EraseRootFromParent_Done, |
| 117242 | // Label 8180: @297091 |
| 117243 | GIM_Reject, |
| 117244 | // Label 8178: @297092 |
| 117245 | GIM_Reject, |
| 117246 | // Label 8139: @297093 |
| 117247 | GIM_Try, /*On fail goto*//*Label 8181*/ GIMT_Encode4(297213), |
| 117248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 117249 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 117250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117251 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117252 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117253 | GIM_Try, /*On fail goto*//*Label 8182*/ GIMT_Encode4(297164), // Rule ID 54990 // |
| 117254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 117255 | // (strict_fmul:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMUL_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 117256 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 117257 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117258 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117259 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E64), |
| 117261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117262 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117263 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117264 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117269 | GIR_RootConstrainSelectedInstOperands, |
| 117270 | // GIR_Coverage, 54990, |
| 117271 | GIR_EraseRootFromParent_Done, |
| 117272 | // Label 8182: @297164 |
| 117273 | GIM_Try, /*On fail goto*//*Label 8183*/ GIMT_Encode4(297212), // Rule ID 54991 // |
| 117274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 117275 | // (strict_fmul:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMUL_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 117276 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 117277 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117278 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117279 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E64), |
| 117281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117282 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117283 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117284 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117289 | GIR_RootConstrainSelectedInstOperands, |
| 117290 | // GIR_Coverage, 54991, |
| 117291 | GIR_EraseRootFromParent_Done, |
| 117292 | // Label 8183: @297212 |
| 117293 | GIM_Reject, |
| 117294 | // Label 8181: @297213 |
| 117295 | GIM_Reject, |
| 117296 | // Label 8140: @297214 |
| 117297 | GIM_Try, /*On fail goto*//*Label 8184*/ GIMT_Encode4(297334), |
| 117298 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 117299 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 117300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117301 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117302 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117303 | GIM_Try, /*On fail goto*//*Label 8185*/ GIMT_Encode4(297285), // Rule ID 54882 // |
| 117304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117305 | // (strict_fmul:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMUL_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117306 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 117307 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117308 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117309 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E16), |
| 117311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117312 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117313 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117314 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117319 | GIR_RootConstrainSelectedInstOperands, |
| 117320 | // GIR_Coverage, 54882, |
| 117321 | GIR_EraseRootFromParent_Done, |
| 117322 | // Label 8185: @297285 |
| 117323 | GIM_Try, /*On fail goto*//*Label 8186*/ GIMT_Encode4(297333), // Rule ID 54883 // |
| 117324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 117325 | // (strict_fmul:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMUL_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 117326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 117327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M1_E16), |
| 117331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117332 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117333 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117334 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117339 | GIR_RootConstrainSelectedInstOperands, |
| 117340 | // GIR_Coverage, 54883, |
| 117341 | GIR_EraseRootFromParent_Done, |
| 117342 | // Label 8186: @297333 |
| 117343 | GIM_Reject, |
| 117344 | // Label 8184: @297334 |
| 117345 | GIM_Reject, |
| 117346 | // Label 8141: @297335 |
| 117347 | GIM_Try, /*On fail goto*//*Label 8187*/ GIMT_Encode4(297455), |
| 117348 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 117349 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 117350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117351 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117352 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117353 | GIM_Try, /*On fail goto*//*Label 8188*/ GIMT_Encode4(297406), // Rule ID 54954 // |
| 117354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 117355 | // (strict_fmul:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMUL_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 117356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 117357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E32), |
| 117361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117363 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117364 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117369 | GIR_RootConstrainSelectedInstOperands, |
| 117370 | // GIR_Coverage, 54954, |
| 117371 | GIR_EraseRootFromParent_Done, |
| 117372 | // Label 8188: @297406 |
| 117373 | GIM_Try, /*On fail goto*//*Label 8189*/ GIMT_Encode4(297454), // Rule ID 54955 // |
| 117374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 117375 | // (strict_fmul:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMUL_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 117376 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 117377 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117378 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E32), |
| 117381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117382 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117383 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117384 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117389 | GIR_RootConstrainSelectedInstOperands, |
| 117390 | // GIR_Coverage, 54955, |
| 117391 | GIR_EraseRootFromParent_Done, |
| 117392 | // Label 8189: @297454 |
| 117393 | GIM_Reject, |
| 117394 | // Label 8187: @297455 |
| 117395 | GIM_Reject, |
| 117396 | // Label 8142: @297456 |
| 117397 | GIM_Try, /*On fail goto*//*Label 8190*/ GIMT_Encode4(297576), |
| 117398 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 117399 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 117400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117401 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117402 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117403 | GIM_Try, /*On fail goto*//*Label 8191*/ GIMT_Encode4(297527), // Rule ID 55002 // |
| 117404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 117405 | // (strict_fmul:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMUL_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 117406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 117407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117408 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E64), |
| 117411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117413 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117414 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117419 | GIR_RootConstrainSelectedInstOperands, |
| 117420 | // GIR_Coverage, 55002, |
| 117421 | GIR_EraseRootFromParent_Done, |
| 117422 | // Label 8191: @297527 |
| 117423 | GIM_Try, /*On fail goto*//*Label 8192*/ GIMT_Encode4(297575), // Rule ID 55003 // |
| 117424 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 117425 | // (strict_fmul:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMUL_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 117426 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 117427 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117428 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E64), |
| 117431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117432 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117433 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117434 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117439 | GIR_RootConstrainSelectedInstOperands, |
| 117440 | // GIR_Coverage, 55003, |
| 117441 | GIR_EraseRootFromParent_Done, |
| 117442 | // Label 8192: @297575 |
| 117443 | GIM_Reject, |
| 117444 | // Label 8190: @297576 |
| 117445 | GIM_Reject, |
| 117446 | // Label 8143: @297577 |
| 117447 | GIM_Try, /*On fail goto*//*Label 8193*/ GIMT_Encode4(297697), |
| 117448 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 117449 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 117450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117451 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117452 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 117453 | GIM_Try, /*On fail goto*//*Label 8194*/ GIMT_Encode4(297648), // Rule ID 54918 // |
| 117454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117455 | // (strict_fmul:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMUL_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 117457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E16), |
| 117461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117463 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117464 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117469 | GIR_RootConstrainSelectedInstOperands, |
| 117470 | // GIR_Coverage, 54918, |
| 117471 | GIR_EraseRootFromParent_Done, |
| 117472 | // Label 8194: @297648 |
| 117473 | GIM_Try, /*On fail goto*//*Label 8195*/ GIMT_Encode4(297696), // Rule ID 54919 // |
| 117474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 117475 | // (strict_fmul:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMUL_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 117476 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 117477 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117478 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M2_E16), |
| 117481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117482 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117483 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117484 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117489 | GIR_RootConstrainSelectedInstOperands, |
| 117490 | // GIR_Coverage, 54919, |
| 117491 | GIR_EraseRootFromParent_Done, |
| 117492 | // Label 8195: @297696 |
| 117493 | GIM_Reject, |
| 117494 | // Label 8193: @297697 |
| 117495 | GIM_Reject, |
| 117496 | // Label 8144: @297698 |
| 117497 | GIM_Try, /*On fail goto*//*Label 8196*/ GIMT_Encode4(297818), |
| 117498 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 117499 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 117500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117501 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117502 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117503 | GIM_Try, /*On fail goto*//*Label 8197*/ GIMT_Encode4(297769), // Rule ID 54966 // |
| 117504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 117505 | // (strict_fmul:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMUL_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 117506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 117507 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E32), |
| 117511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117513 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117514 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117519 | GIR_RootConstrainSelectedInstOperands, |
| 117520 | // GIR_Coverage, 54966, |
| 117521 | GIR_EraseRootFromParent_Done, |
| 117522 | // Label 8197: @297769 |
| 117523 | GIM_Try, /*On fail goto*//*Label 8198*/ GIMT_Encode4(297817), // Rule ID 54967 // |
| 117524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 117525 | // (strict_fmul:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMUL_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 117526 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 117527 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117528 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117529 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E32), |
| 117531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117532 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117533 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117534 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117539 | GIR_RootConstrainSelectedInstOperands, |
| 117540 | // GIR_Coverage, 54967, |
| 117541 | GIR_EraseRootFromParent_Done, |
| 117542 | // Label 8198: @297817 |
| 117543 | GIM_Reject, |
| 117544 | // Label 8196: @297818 |
| 117545 | GIM_Reject, |
| 117546 | // Label 8145: @297819 |
| 117547 | GIM_Try, /*On fail goto*//*Label 8199*/ GIMT_Encode4(297939), |
| 117548 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 117549 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 117550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117551 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117552 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117553 | GIM_Try, /*On fail goto*//*Label 8200*/ GIMT_Encode4(297890), // Rule ID 55014 // |
| 117554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 117555 | // (strict_fmul:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMUL_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 117556 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 117557 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E64), |
| 117561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117562 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117563 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117564 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117569 | GIR_RootConstrainSelectedInstOperands, |
| 117570 | // GIR_Coverage, 55014, |
| 117571 | GIR_EraseRootFromParent_Done, |
| 117572 | // Label 8200: @297890 |
| 117573 | GIM_Try, /*On fail goto*//*Label 8201*/ GIMT_Encode4(297938), // Rule ID 55015 // |
| 117574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 117575 | // (strict_fmul:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMUL_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 117576 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 117577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117579 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E64), |
| 117581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117582 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117583 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117584 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 117588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117589 | GIR_RootConstrainSelectedInstOperands, |
| 117590 | // GIR_Coverage, 55015, |
| 117591 | GIR_EraseRootFromParent_Done, |
| 117592 | // Label 8201: @297938 |
| 117593 | GIM_Reject, |
| 117594 | // Label 8199: @297939 |
| 117595 | GIM_Reject, |
| 117596 | // Label 8146: @297940 |
| 117597 | GIM_Try, /*On fail goto*//*Label 8202*/ GIMT_Encode4(298060), |
| 117598 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 117599 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 117600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117601 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117602 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 117603 | GIM_Try, /*On fail goto*//*Label 8203*/ GIMT_Encode4(298011), // Rule ID 54930 // |
| 117604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117605 | // (strict_fmul:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMUL_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117606 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 117607 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117608 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E16), |
| 117611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117613 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117614 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117619 | GIR_RootConstrainSelectedInstOperands, |
| 117620 | // GIR_Coverage, 54930, |
| 117621 | GIR_EraseRootFromParent_Done, |
| 117622 | // Label 8203: @298011 |
| 117623 | GIM_Try, /*On fail goto*//*Label 8204*/ GIMT_Encode4(298059), // Rule ID 54931 // |
| 117624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 117625 | // (strict_fmul:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMUL_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 117626 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 117627 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117628 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M4_E16), |
| 117631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117632 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117633 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117634 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117639 | GIR_RootConstrainSelectedInstOperands, |
| 117640 | // GIR_Coverage, 54931, |
| 117641 | GIR_EraseRootFromParent_Done, |
| 117642 | // Label 8204: @298059 |
| 117643 | GIM_Reject, |
| 117644 | // Label 8202: @298060 |
| 117645 | GIM_Reject, |
| 117646 | // Label 8147: @298061 |
| 117647 | GIM_Try, /*On fail goto*//*Label 8205*/ GIMT_Encode4(298181), |
| 117648 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 117649 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 117650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117652 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117653 | GIM_Try, /*On fail goto*//*Label 8206*/ GIMT_Encode4(298132), // Rule ID 54978 // |
| 117654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 117655 | // (strict_fmul:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMUL_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 117656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 117657 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117658 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E32), |
| 117661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117663 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117664 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117669 | GIR_RootConstrainSelectedInstOperands, |
| 117670 | // GIR_Coverage, 54978, |
| 117671 | GIR_EraseRootFromParent_Done, |
| 117672 | // Label 8206: @298132 |
| 117673 | GIM_Try, /*On fail goto*//*Label 8207*/ GIMT_Encode4(298180), // Rule ID 54979 // |
| 117674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 117675 | // (strict_fmul:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMUL_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 117676 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 117677 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117678 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E32), |
| 117681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117682 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117683 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117684 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 117688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117689 | GIR_RootConstrainSelectedInstOperands, |
| 117690 | // GIR_Coverage, 54979, |
| 117691 | GIR_EraseRootFromParent_Done, |
| 117692 | // Label 8207: @298180 |
| 117693 | GIM_Reject, |
| 117694 | // Label 8205: @298181 |
| 117695 | GIM_Reject, |
| 117696 | // Label 8148: @298182 |
| 117697 | GIM_Try, /*On fail goto*//*Label 8208*/ GIMT_Encode4(298302), |
| 117698 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 117699 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 117700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117701 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117702 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 117703 | GIM_Try, /*On fail goto*//*Label 8209*/ GIMT_Encode4(298253), // Rule ID 54942 // |
| 117704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117705 | // (strict_fmul:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMUL_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 117707 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117708 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E16), |
| 117711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117713 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117714 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117719 | GIR_RootConstrainSelectedInstOperands, |
| 117720 | // GIR_Coverage, 54942, |
| 117721 | GIR_EraseRootFromParent_Done, |
| 117722 | // Label 8209: @298253 |
| 117723 | GIM_Try, /*On fail goto*//*Label 8210*/ GIMT_Encode4(298301), // Rule ID 54943 // |
| 117724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 117725 | // (strict_fmul:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMUL_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 117726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 117727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMUL_VV_M8_E16), |
| 117731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117732 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 117733 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117734 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 117737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 117738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 117739 | GIR_RootConstrainSelectedInstOperands, |
| 117740 | // GIR_Coverage, 54943, |
| 117741 | GIR_EraseRootFromParent_Done, |
| 117742 | // Label 8210: @298301 |
| 117743 | GIM_Reject, |
| 117744 | // Label 8208: @298302 |
| 117745 | GIM_Reject, |
| 117746 | // Label 8149: @298303 |
| 117747 | GIM_Reject, |
| 117748 | // Label 92: @298304 |
| 117749 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 8229*/ GIMT_Encode4(300731), |
| 117750 | /*GILLT_s16*//*Label 8211*/ GIMT_Encode4(298435), |
| 117751 | /*GILLT_s32*//*Label 8212*/ GIMT_Encode4(298584), |
| 117752 | /*GILLT_s64*//*Label 8213*/ GIMT_Encode4(298733), GIMT_Encode4(0), GIMT_Encode4(0), |
| 117753 | /*GILLT_nxv1s16*//*Label 8214*/ GIMT_Encode4(298916), |
| 117754 | /*GILLT_nxv1s32*//*Label 8215*/ GIMT_Encode4(299037), |
| 117755 | /*GILLT_nxv1s64*//*Label 8216*/ GIMT_Encode4(299158), GIMT_Encode4(0), GIMT_Encode4(0), |
| 117756 | /*GILLT_nxv2s16*//*Label 8217*/ GIMT_Encode4(299279), |
| 117757 | /*GILLT_nxv2s32*//*Label 8218*/ GIMT_Encode4(299400), |
| 117758 | /*GILLT_nxv2s64*//*Label 8219*/ GIMT_Encode4(299521), GIMT_Encode4(0), GIMT_Encode4(0), |
| 117759 | /*GILLT_nxv4s16*//*Label 8220*/ GIMT_Encode4(299642), |
| 117760 | /*GILLT_nxv4s32*//*Label 8221*/ GIMT_Encode4(299763), |
| 117761 | /*GILLT_nxv4s64*//*Label 8222*/ GIMT_Encode4(299884), GIMT_Encode4(0), GIMT_Encode4(0), |
| 117762 | /*GILLT_nxv8s16*//*Label 8223*/ GIMT_Encode4(300005), |
| 117763 | /*GILLT_nxv8s32*//*Label 8224*/ GIMT_Encode4(300126), |
| 117764 | /*GILLT_nxv8s64*//*Label 8225*/ GIMT_Encode4(300247), GIMT_Encode4(0), GIMT_Encode4(0), |
| 117765 | /*GILLT_nxv16s16*//*Label 8226*/ GIMT_Encode4(300368), |
| 117766 | /*GILLT_nxv16s32*//*Label 8227*/ GIMT_Encode4(300489), GIMT_Encode4(0), GIMT_Encode4(0), |
| 117767 | /*GILLT_nxv32s16*//*Label 8228*/ GIMT_Encode4(300610), |
| 117768 | // Label 8211: @298435 |
| 117769 | GIM_Try, /*On fail goto*//*Label 8230*/ GIMT_Encode4(298583), |
| 117770 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 117771 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 117772 | GIM_Try, /*On fail goto*//*Label 8231*/ GIMT_Encode4(298480), // Rule ID 2034 // |
| 117773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 117774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 117775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 117776 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 117777 | // (strict_fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FDIV_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 117778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H), |
| 117779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117780 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117781 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117783 | GIR_RootConstrainSelectedInstOperands, |
| 117784 | // GIR_Coverage, 2034, |
| 117785 | GIR_EraseRootFromParent_Done, |
| 117786 | // Label 8231: @298480 |
| 117787 | GIM_Try, /*On fail goto*//*Label 8232*/ GIMT_Encode4(298514), // Rule ID 2035 // |
| 117788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 117789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 117790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 117791 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 117792 | // (strict_fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2) => (FDIV_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 117793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H), |
| 117794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117795 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117796 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117798 | GIR_RootConstrainSelectedInstOperands, |
| 117799 | // GIR_Coverage, 2035, |
| 117800 | GIR_EraseRootFromParent_Done, |
| 117801 | // Label 8232: @298514 |
| 117802 | GIM_Try, /*On fail goto*//*Label 8233*/ GIMT_Encode4(298548), // Rule ID 2038 // |
| 117803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 117804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 117805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 117806 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 117807 | // (strict_fdiv:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FDIV_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i64] }) |
| 117808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H_INX), |
| 117809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117810 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117811 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117813 | GIR_RootConstrainSelectedInstOperands, |
| 117814 | // GIR_Coverage, 2038, |
| 117815 | GIR_EraseRootFromParent_Done, |
| 117816 | // Label 8233: @298548 |
| 117817 | GIM_Try, /*On fail goto*//*Label 8234*/ GIMT_Encode4(298582), // Rule ID 2039 // |
| 117818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 117819 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 117820 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 117821 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 117822 | // (strict_fdiv:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2) => (FDIV_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, 7:{ *:[i32] }) |
| 117823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_H_INX), |
| 117824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117825 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117826 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117828 | GIR_RootConstrainSelectedInstOperands, |
| 117829 | // GIR_Coverage, 2039, |
| 117830 | GIR_EraseRootFromParent_Done, |
| 117831 | // Label 8234: @298582 |
| 117832 | GIM_Reject, |
| 117833 | // Label 8230: @298583 |
| 117834 | GIM_Reject, |
| 117835 | // Label 8212: @298584 |
| 117836 | GIM_Try, /*On fail goto*//*Label 8235*/ GIMT_Encode4(298732), |
| 117837 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 117838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 117839 | GIM_Try, /*On fail goto*//*Label 8236*/ GIMT_Encode4(298629), // Rule ID 1346 // |
| 117840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 117841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 117842 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 117843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 117844 | // (strict_fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 117845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S), |
| 117846 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117847 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117848 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117850 | GIR_RootConstrainSelectedInstOperands, |
| 117851 | // GIR_Coverage, 1346, |
| 117852 | GIR_EraseRootFromParent_Done, |
| 117853 | // Label 8236: @298629 |
| 117854 | GIM_Try, /*On fail goto*//*Label 8237*/ GIMT_Encode4(298663), // Rule ID 1347 // |
| 117855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 117856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 117857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 117858 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 117859 | // (strict_fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) => (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 117860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S), |
| 117861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117862 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117863 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117865 | GIR_RootConstrainSelectedInstOperands, |
| 117866 | // GIR_Coverage, 1347, |
| 117867 | GIR_EraseRootFromParent_Done, |
| 117868 | // Label 8237: @298663 |
| 117869 | GIM_Try, /*On fail goto*//*Label 8238*/ GIMT_Encode4(298697), // Rule ID 1350 // |
| 117870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 117871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 117872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 117873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 117874 | // (strict_fdiv:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FDIV_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] }) |
| 117875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S_INX), |
| 117876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117877 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117878 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117880 | GIR_RootConstrainSelectedInstOperands, |
| 117881 | // GIR_Coverage, 1350, |
| 117882 | GIR_EraseRootFromParent_Done, |
| 117883 | // Label 8238: @298697 |
| 117884 | GIM_Try, /*On fail goto*//*Label 8239*/ GIMT_Encode4(298731), // Rule ID 1351 // |
| 117885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 117886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 117887 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 117888 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 117889 | // (strict_fdiv:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2) => (FDIV_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] }) |
| 117890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_S_INX), |
| 117891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117892 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117893 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117895 | GIR_RootConstrainSelectedInstOperands, |
| 117896 | // GIR_Coverage, 1351, |
| 117897 | GIR_EraseRootFromParent_Done, |
| 117898 | // Label 8239: @298731 |
| 117899 | GIM_Reject, |
| 117900 | // Label 8235: @298732 |
| 117901 | GIM_Reject, |
| 117902 | // Label 8213: @298733 |
| 117903 | GIM_Try, /*On fail goto*//*Label 8240*/ GIMT_Encode4(298915), |
| 117904 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 117905 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 117906 | GIM_Try, /*On fail goto*//*Label 8241*/ GIMT_Encode4(298778), // Rule ID 1679 // |
| 117907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 117908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 117909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 117910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 117911 | // (strict_fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 117912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D), |
| 117913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117914 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117915 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117917 | GIR_RootConstrainSelectedInstOperands, |
| 117918 | // GIR_Coverage, 1679, |
| 117919 | GIR_EraseRootFromParent_Done, |
| 117920 | // Label 8241: @298778 |
| 117921 | GIM_Try, /*On fail goto*//*Label 8242*/ GIMT_Encode4(298812), // Rule ID 1680 // |
| 117922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 117923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 117924 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 117925 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 117926 | // (strict_fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) => (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 117927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D), |
| 117928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117929 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117930 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117932 | GIR_RootConstrainSelectedInstOperands, |
| 117933 | // GIR_Coverage, 1680, |
| 117934 | GIR_EraseRootFromParent_Done, |
| 117935 | // Label 8242: @298812 |
| 117936 | GIM_Try, /*On fail goto*//*Label 8243*/ GIMT_Encode4(298846), // Rule ID 1683 // |
| 117937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 117938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 117939 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 117940 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 117941 | // (strict_fdiv:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FDIV_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 117942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D_IN32X), |
| 117943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117944 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117945 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117947 | GIR_RootConstrainSelectedInstOperands, |
| 117948 | // GIR_Coverage, 1683, |
| 117949 | GIR_EraseRootFromParent_Done, |
| 117950 | // Label 8243: @298846 |
| 117951 | GIM_Try, /*On fail goto*//*Label 8244*/ GIMT_Encode4(298880), // Rule ID 1684 // |
| 117952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 117953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 117954 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 117955 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 117956 | // (strict_fdiv:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2) => (FDIV_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }) |
| 117957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D_IN32X), |
| 117958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117959 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117960 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117962 | GIR_RootConstrainSelectedInstOperands, |
| 117963 | // GIR_Coverage, 1684, |
| 117964 | GIR_EraseRootFromParent_Done, |
| 117965 | // Label 8244: @298880 |
| 117966 | GIM_Try, /*On fail goto*//*Label 8245*/ GIMT_Encode4(298914), // Rule ID 1687 // |
| 117967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 117968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 117969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 117970 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 117971 | // (strict_fdiv:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2) => (FDIV_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }) |
| 117972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FDIV_D_INX), |
| 117973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 117974 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 117975 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 117976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 117977 | GIR_RootConstrainSelectedInstOperands, |
| 117978 | // GIR_Coverage, 1687, |
| 117979 | GIR_EraseRootFromParent_Done, |
| 117980 | // Label 8245: @298914 |
| 117981 | GIM_Reject, |
| 117982 | // Label 8240: @298915 |
| 117983 | GIM_Reject, |
| 117984 | // Label 8214: @298916 |
| 117985 | GIM_Try, /*On fail goto*//*Label 8246*/ GIMT_Encode4(299036), |
| 117986 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 117987 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 117988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117990 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 117991 | GIM_Try, /*On fail goto*//*Label 8247*/ GIMT_Encode4(298987), // Rule ID 55026 // |
| 117992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 117993 | // (strict_fdiv:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFDIV_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 117994 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 117995 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 117996 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 117997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 117998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF4_E16), |
| 117999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118000 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118001 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118002 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118007 | GIR_RootConstrainSelectedInstOperands, |
| 118008 | // GIR_Coverage, 55026, |
| 118009 | GIR_EraseRootFromParent_Done, |
| 118010 | // Label 8247: @298987 |
| 118011 | GIM_Try, /*On fail goto*//*Label 8248*/ GIMT_Encode4(299035), // Rule ID 55027 // |
| 118012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 118013 | // (strict_fdiv:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFDIV_VV_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 118014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 118015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118017 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF4_E16), |
| 118019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118020 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118021 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118022 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118027 | GIR_RootConstrainSelectedInstOperands, |
| 118028 | // GIR_Coverage, 55027, |
| 118029 | GIR_EraseRootFromParent_Done, |
| 118030 | // Label 8248: @299035 |
| 118031 | GIM_Reject, |
| 118032 | // Label 8246: @299036 |
| 118033 | GIM_Reject, |
| 118034 | // Label 8215: @299037 |
| 118035 | GIM_Try, /*On fail goto*//*Label 8249*/ GIMT_Encode4(299157), |
| 118036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 118037 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 118038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118040 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118041 | GIM_Try, /*On fail goto*//*Label 8250*/ GIMT_Encode4(299108), // Rule ID 55050 // |
| 118042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 118043 | // (strict_fdiv:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFDIV_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 118044 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 118045 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118046 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E32), |
| 118049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118050 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118051 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118052 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118057 | GIR_RootConstrainSelectedInstOperands, |
| 118058 | // GIR_Coverage, 55050, |
| 118059 | GIR_EraseRootFromParent_Done, |
| 118060 | // Label 8250: @299108 |
| 118061 | GIM_Try, /*On fail goto*//*Label 8251*/ GIMT_Encode4(299156), // Rule ID 55051 // |
| 118062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 118063 | // (strict_fdiv:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFDIV_VV_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 118064 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 118065 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118066 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E32), |
| 118069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118070 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118071 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118072 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118077 | GIR_RootConstrainSelectedInstOperands, |
| 118078 | // GIR_Coverage, 55051, |
| 118079 | GIR_EraseRootFromParent_Done, |
| 118080 | // Label 8251: @299156 |
| 118081 | GIM_Reject, |
| 118082 | // Label 8249: @299157 |
| 118083 | GIM_Reject, |
| 118084 | // Label 8216: @299158 |
| 118085 | GIM_Try, /*On fail goto*//*Label 8252*/ GIMT_Encode4(299278), |
| 118086 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 118087 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 118088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118089 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118090 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118091 | GIM_Try, /*On fail goto*//*Label 8253*/ GIMT_Encode4(299229), // Rule ID 55086 // |
| 118092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 118093 | // (strict_fdiv:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFDIV_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 118094 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 118095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E64), |
| 118099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118100 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118101 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118102 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118107 | GIR_RootConstrainSelectedInstOperands, |
| 118108 | // GIR_Coverage, 55086, |
| 118109 | GIR_EraseRootFromParent_Done, |
| 118110 | // Label 8253: @299229 |
| 118111 | GIM_Try, /*On fail goto*//*Label 8254*/ GIMT_Encode4(299277), // Rule ID 55087 // |
| 118112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 118113 | // (strict_fdiv:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFDIV_VV_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 118114 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 118115 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118116 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E64), |
| 118119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118120 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118121 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118122 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118127 | GIR_RootConstrainSelectedInstOperands, |
| 118128 | // GIR_Coverage, 55087, |
| 118129 | GIR_EraseRootFromParent_Done, |
| 118130 | // Label 8254: @299277 |
| 118131 | GIM_Reject, |
| 118132 | // Label 8252: @299278 |
| 118133 | GIM_Reject, |
| 118134 | // Label 8217: @299279 |
| 118135 | GIM_Try, /*On fail goto*//*Label 8255*/ GIMT_Encode4(299399), |
| 118136 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 118137 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 118138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118140 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118141 | GIM_Try, /*On fail goto*//*Label 8256*/ GIMT_Encode4(299350), // Rule ID 55038 // |
| 118142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 118143 | // (strict_fdiv:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFDIV_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 118144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 118145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118147 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E16), |
| 118149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118150 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118151 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118152 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118157 | GIR_RootConstrainSelectedInstOperands, |
| 118158 | // GIR_Coverage, 55038, |
| 118159 | GIR_EraseRootFromParent_Done, |
| 118160 | // Label 8256: @299350 |
| 118161 | GIM_Try, /*On fail goto*//*Label 8257*/ GIMT_Encode4(299398), // Rule ID 55039 // |
| 118162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 118163 | // (strict_fdiv:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFDIV_VV_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 118164 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 118165 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118166 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_MF2_E16), |
| 118169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118170 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118171 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118172 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118177 | GIR_RootConstrainSelectedInstOperands, |
| 118178 | // GIR_Coverage, 55039, |
| 118179 | GIR_EraseRootFromParent_Done, |
| 118180 | // Label 8257: @299398 |
| 118181 | GIM_Reject, |
| 118182 | // Label 8255: @299399 |
| 118183 | GIM_Reject, |
| 118184 | // Label 8218: @299400 |
| 118185 | GIM_Try, /*On fail goto*//*Label 8258*/ GIMT_Encode4(299520), |
| 118186 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 118187 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 118188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118189 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118190 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118191 | GIM_Try, /*On fail goto*//*Label 8259*/ GIMT_Encode4(299471), // Rule ID 55074 // |
| 118192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 118193 | // (strict_fdiv:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFDIV_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 118194 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 118195 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118196 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118197 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E32), |
| 118199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118200 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118201 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118202 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118207 | GIR_RootConstrainSelectedInstOperands, |
| 118208 | // GIR_Coverage, 55074, |
| 118209 | GIR_EraseRootFromParent_Done, |
| 118210 | // Label 8259: @299471 |
| 118211 | GIM_Try, /*On fail goto*//*Label 8260*/ GIMT_Encode4(299519), // Rule ID 55075 // |
| 118212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 118213 | // (strict_fdiv:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFDIV_VV_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 118214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 118215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E32), |
| 118219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118220 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118221 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118222 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118227 | GIR_RootConstrainSelectedInstOperands, |
| 118228 | // GIR_Coverage, 55075, |
| 118229 | GIR_EraseRootFromParent_Done, |
| 118230 | // Label 8260: @299519 |
| 118231 | GIM_Reject, |
| 118232 | // Label 8258: @299520 |
| 118233 | GIM_Reject, |
| 118234 | // Label 8219: @299521 |
| 118235 | GIM_Try, /*On fail goto*//*Label 8261*/ GIMT_Encode4(299641), |
| 118236 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 118237 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 118238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118241 | GIM_Try, /*On fail goto*//*Label 8262*/ GIMT_Encode4(299592), // Rule ID 55170 // |
| 118242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 118243 | // (strict_fdiv:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFDIV_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 118244 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 118245 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118246 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E64), |
| 118249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118250 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118251 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118252 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118257 | GIR_RootConstrainSelectedInstOperands, |
| 118258 | // GIR_Coverage, 55170, |
| 118259 | GIR_EraseRootFromParent_Done, |
| 118260 | // Label 8262: @299592 |
| 118261 | GIM_Try, /*On fail goto*//*Label 8263*/ GIMT_Encode4(299640), // Rule ID 55171 // |
| 118262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 118263 | // (strict_fdiv:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFDIV_VV_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 118264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 118265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E64), |
| 118269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118270 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118271 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118272 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118277 | GIR_RootConstrainSelectedInstOperands, |
| 118278 | // GIR_Coverage, 55171, |
| 118279 | GIR_EraseRootFromParent_Done, |
| 118280 | // Label 8263: @299640 |
| 118281 | GIM_Reject, |
| 118282 | // Label 8261: @299641 |
| 118283 | GIM_Reject, |
| 118284 | // Label 8220: @299642 |
| 118285 | GIM_Try, /*On fail goto*//*Label 8264*/ GIMT_Encode4(299762), |
| 118286 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 118287 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 118288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118289 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118290 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 118291 | GIM_Try, /*On fail goto*//*Label 8265*/ GIMT_Encode4(299713), // Rule ID 55062 // |
| 118292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 118293 | // (strict_fdiv:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFDIV_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 118294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 118295 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118296 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E16), |
| 118299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118300 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118301 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118302 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118307 | GIR_RootConstrainSelectedInstOperands, |
| 118308 | // GIR_Coverage, 55062, |
| 118309 | GIR_EraseRootFromParent_Done, |
| 118310 | // Label 8265: @299713 |
| 118311 | GIM_Try, /*On fail goto*//*Label 8266*/ GIMT_Encode4(299761), // Rule ID 55063 // |
| 118312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 118313 | // (strict_fdiv:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFDIV_VV_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 118314 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 118315 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118316 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118317 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M1_E16), |
| 118319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118320 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118321 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118322 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118327 | GIR_RootConstrainSelectedInstOperands, |
| 118328 | // GIR_Coverage, 55063, |
| 118329 | GIR_EraseRootFromParent_Done, |
| 118330 | // Label 8266: @299761 |
| 118331 | GIM_Reject, |
| 118332 | // Label 8264: @299762 |
| 118333 | GIM_Reject, |
| 118334 | // Label 8221: @299763 |
| 118335 | GIM_Try, /*On fail goto*//*Label 8267*/ GIMT_Encode4(299883), |
| 118336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 118337 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 118338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118339 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118340 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118341 | GIM_Try, /*On fail goto*//*Label 8268*/ GIMT_Encode4(299834), // Rule ID 55134 // |
| 118342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 118343 | // (strict_fdiv:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFDIV_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 118344 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 118345 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118346 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E32), |
| 118349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118350 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118351 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118352 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118357 | GIR_RootConstrainSelectedInstOperands, |
| 118358 | // GIR_Coverage, 55134, |
| 118359 | GIR_EraseRootFromParent_Done, |
| 118360 | // Label 8268: @299834 |
| 118361 | GIM_Try, /*On fail goto*//*Label 8269*/ GIMT_Encode4(299882), // Rule ID 55135 // |
| 118362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 118363 | // (strict_fdiv:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFDIV_VV_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 118364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 118365 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118366 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E32), |
| 118369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118371 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118372 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118377 | GIR_RootConstrainSelectedInstOperands, |
| 118378 | // GIR_Coverage, 55135, |
| 118379 | GIR_EraseRootFromParent_Done, |
| 118380 | // Label 8269: @299882 |
| 118381 | GIM_Reject, |
| 118382 | // Label 8267: @299883 |
| 118383 | GIM_Reject, |
| 118384 | // Label 8222: @299884 |
| 118385 | GIM_Try, /*On fail goto*//*Label 8270*/ GIMT_Encode4(300004), |
| 118386 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 118387 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 118388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118389 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118390 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118391 | GIM_Try, /*On fail goto*//*Label 8271*/ GIMT_Encode4(299955), // Rule ID 55182 // |
| 118392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 118393 | // (strict_fdiv:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFDIV_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 118394 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 118395 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118396 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E64), |
| 118399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118400 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118401 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118402 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118407 | GIR_RootConstrainSelectedInstOperands, |
| 118408 | // GIR_Coverage, 55182, |
| 118409 | GIR_EraseRootFromParent_Done, |
| 118410 | // Label 8271: @299955 |
| 118411 | GIM_Try, /*On fail goto*//*Label 8272*/ GIMT_Encode4(300003), // Rule ID 55183 // |
| 118412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 118413 | // (strict_fdiv:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFDIV_VV_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 118414 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 118415 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118416 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118417 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E64), |
| 118419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118420 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118421 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118422 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118427 | GIR_RootConstrainSelectedInstOperands, |
| 118428 | // GIR_Coverage, 55183, |
| 118429 | GIR_EraseRootFromParent_Done, |
| 118430 | // Label 8272: @300003 |
| 118431 | GIM_Reject, |
| 118432 | // Label 8270: @300004 |
| 118433 | GIM_Reject, |
| 118434 | // Label 8223: @300005 |
| 118435 | GIM_Try, /*On fail goto*//*Label 8273*/ GIMT_Encode4(300125), |
| 118436 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 118437 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 118438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118439 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118440 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 118441 | GIM_Try, /*On fail goto*//*Label 8274*/ GIMT_Encode4(300076), // Rule ID 55098 // |
| 118442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 118443 | // (strict_fdiv:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFDIV_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 118444 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 118445 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118446 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E16), |
| 118449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118450 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118451 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118452 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118457 | GIR_RootConstrainSelectedInstOperands, |
| 118458 | // GIR_Coverage, 55098, |
| 118459 | GIR_EraseRootFromParent_Done, |
| 118460 | // Label 8274: @300076 |
| 118461 | GIM_Try, /*On fail goto*//*Label 8275*/ GIMT_Encode4(300124), // Rule ID 55099 // |
| 118462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 118463 | // (strict_fdiv:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFDIV_VV_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 118464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 118465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M2_E16), |
| 118469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118470 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118471 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118472 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118477 | GIR_RootConstrainSelectedInstOperands, |
| 118478 | // GIR_Coverage, 55099, |
| 118479 | GIR_EraseRootFromParent_Done, |
| 118480 | // Label 8275: @300124 |
| 118481 | GIM_Reject, |
| 118482 | // Label 8273: @300125 |
| 118483 | GIM_Reject, |
| 118484 | // Label 8224: @300126 |
| 118485 | GIM_Try, /*On fail goto*//*Label 8276*/ GIMT_Encode4(300246), |
| 118486 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 118487 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 118488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118489 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118490 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118491 | GIM_Try, /*On fail goto*//*Label 8277*/ GIMT_Encode4(300197), // Rule ID 55146 // |
| 118492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 118493 | // (strict_fdiv:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFDIV_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 118494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 118495 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118496 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E32), |
| 118499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118500 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118501 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118502 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118507 | GIR_RootConstrainSelectedInstOperands, |
| 118508 | // GIR_Coverage, 55146, |
| 118509 | GIR_EraseRootFromParent_Done, |
| 118510 | // Label 8277: @300197 |
| 118511 | GIM_Try, /*On fail goto*//*Label 8278*/ GIMT_Encode4(300245), // Rule ID 55147 // |
| 118512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 118513 | // (strict_fdiv:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFDIV_VV_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 118514 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 118515 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118516 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118517 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E32), |
| 118519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118520 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118521 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118522 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118527 | GIR_RootConstrainSelectedInstOperands, |
| 118528 | // GIR_Coverage, 55147, |
| 118529 | GIR_EraseRootFromParent_Done, |
| 118530 | // Label 8278: @300245 |
| 118531 | GIM_Reject, |
| 118532 | // Label 8276: @300246 |
| 118533 | GIM_Reject, |
| 118534 | // Label 8225: @300247 |
| 118535 | GIM_Try, /*On fail goto*//*Label 8279*/ GIMT_Encode4(300367), |
| 118536 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 118537 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 118538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118540 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118541 | GIM_Try, /*On fail goto*//*Label 8280*/ GIMT_Encode4(300318), // Rule ID 55194 // |
| 118542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 118543 | // (strict_fdiv:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFDIV_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 118544 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 118545 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118546 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E64), |
| 118549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118550 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118551 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118552 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118557 | GIR_RootConstrainSelectedInstOperands, |
| 118558 | // GIR_Coverage, 55194, |
| 118559 | GIR_EraseRootFromParent_Done, |
| 118560 | // Label 8280: @300318 |
| 118561 | GIM_Try, /*On fail goto*//*Label 8281*/ GIMT_Encode4(300366), // Rule ID 55195 // |
| 118562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 118563 | // (strict_fdiv:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFDIV_VV_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 118564 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 118565 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118566 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E64), |
| 118569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118570 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118571 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118572 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 118576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118577 | GIR_RootConstrainSelectedInstOperands, |
| 118578 | // GIR_Coverage, 55195, |
| 118579 | GIR_EraseRootFromParent_Done, |
| 118580 | // Label 8281: @300366 |
| 118581 | GIM_Reject, |
| 118582 | // Label 8279: @300367 |
| 118583 | GIM_Reject, |
| 118584 | // Label 8226: @300368 |
| 118585 | GIM_Try, /*On fail goto*//*Label 8282*/ GIMT_Encode4(300488), |
| 118586 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 118587 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 118588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118590 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 118591 | GIM_Try, /*On fail goto*//*Label 8283*/ GIMT_Encode4(300439), // Rule ID 55110 // |
| 118592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 118593 | // (strict_fdiv:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFDIV_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 118594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 118595 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118596 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E16), |
| 118599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118600 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118601 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118602 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118607 | GIR_RootConstrainSelectedInstOperands, |
| 118608 | // GIR_Coverage, 55110, |
| 118609 | GIR_EraseRootFromParent_Done, |
| 118610 | // Label 8283: @300439 |
| 118611 | GIM_Try, /*On fail goto*//*Label 8284*/ GIMT_Encode4(300487), // Rule ID 55111 // |
| 118612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 118613 | // (strict_fdiv:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFDIV_VV_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 118614 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 118615 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118616 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M4_E16), |
| 118619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118621 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118622 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118627 | GIR_RootConstrainSelectedInstOperands, |
| 118628 | // GIR_Coverage, 55111, |
| 118629 | GIR_EraseRootFromParent_Done, |
| 118630 | // Label 8284: @300487 |
| 118631 | GIM_Reject, |
| 118632 | // Label 8282: @300488 |
| 118633 | GIM_Reject, |
| 118634 | // Label 8227: @300489 |
| 118635 | GIM_Try, /*On fail goto*//*Label 8285*/ GIMT_Encode4(300609), |
| 118636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 118637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 118638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118639 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118640 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118641 | GIM_Try, /*On fail goto*//*Label 8286*/ GIMT_Encode4(300560), // Rule ID 55158 // |
| 118642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 118643 | // (strict_fdiv:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFDIV_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 118644 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 118645 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118646 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118647 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E32), |
| 118649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118650 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118651 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118652 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118657 | GIR_RootConstrainSelectedInstOperands, |
| 118658 | // GIR_Coverage, 55158, |
| 118659 | GIR_EraseRootFromParent_Done, |
| 118660 | // Label 8286: @300560 |
| 118661 | GIM_Try, /*On fail goto*//*Label 8287*/ GIMT_Encode4(300608), // Rule ID 55159 // |
| 118662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 118663 | // (strict_fdiv:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFDIV_VV_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 118664 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 118665 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118666 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118667 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E32), |
| 118669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118671 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118672 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 118676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118677 | GIR_RootConstrainSelectedInstOperands, |
| 118678 | // GIR_Coverage, 55159, |
| 118679 | GIR_EraseRootFromParent_Done, |
| 118680 | // Label 8287: @300608 |
| 118681 | GIM_Reject, |
| 118682 | // Label 8285: @300609 |
| 118683 | GIM_Reject, |
| 118684 | // Label 8228: @300610 |
| 118685 | GIM_Try, /*On fail goto*//*Label 8288*/ GIMT_Encode4(300730), |
| 118686 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 118687 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 118688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118689 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118690 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 118691 | GIM_Try, /*On fail goto*//*Label 8289*/ GIMT_Encode4(300681), // Rule ID 55122 // |
| 118692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 118693 | // (strict_fdiv:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFDIV_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 118694 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 118695 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118696 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118697 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E16), |
| 118699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118700 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118701 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118702 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118707 | GIR_RootConstrainSelectedInstOperands, |
| 118708 | // GIR_Coverage, 55122, |
| 118709 | GIR_EraseRootFromParent_Done, |
| 118710 | // Label 8289: @300681 |
| 118711 | GIM_Try, /*On fail goto*//*Label 8290*/ GIMT_Encode4(300729), // Rule ID 55123 // |
| 118712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 118713 | // (strict_fdiv:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFDIV_VV_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 118714 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 118715 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 118716 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 118717 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 118718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFDIV_VV_M8_E16), |
| 118719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 118721 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 118722 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 118725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 118726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 118727 | GIR_RootConstrainSelectedInstOperands, |
| 118728 | // GIR_Coverage, 55123, |
| 118729 | GIR_EraseRootFromParent_Done, |
| 118730 | // Label 8290: @300729 |
| 118731 | GIM_Reject, |
| 118732 | // Label 8288: @300730 |
| 118733 | GIM_Reject, |
| 118734 | // Label 8229: @300731 |
| 118735 | GIM_Reject, |
| 118736 | // Label 93: @300732 |
| 118737 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 8309*/ GIMT_Encode4(317376), |
| 118738 | /*GILLT_s16*//*Label 8291*/ GIMT_Encode4(300863), |
| 118739 | /*GILLT_s32*//*Label 8292*/ GIMT_Encode4(302299), |
| 118740 | /*GILLT_s64*//*Label 8293*/ GIMT_Encode4(303735), GIMT_Encode4(0), GIMT_Encode4(0), |
| 118741 | /*GILLT_nxv1s16*//*Label 8294*/ GIMT_Encode4(305526), |
| 118742 | /*GILLT_nxv1s32*//*Label 8295*/ GIMT_Encode4(306316), |
| 118743 | /*GILLT_nxv1s64*//*Label 8296*/ GIMT_Encode4(307106), GIMT_Encode4(0), GIMT_Encode4(0), |
| 118744 | /*GILLT_nxv2s16*//*Label 8297*/ GIMT_Encode4(307896), |
| 118745 | /*GILLT_nxv2s32*//*Label 8298*/ GIMT_Encode4(308686), |
| 118746 | /*GILLT_nxv2s64*//*Label 8299*/ GIMT_Encode4(309476), GIMT_Encode4(0), GIMT_Encode4(0), |
| 118747 | /*GILLT_nxv4s16*//*Label 8300*/ GIMT_Encode4(310266), |
| 118748 | /*GILLT_nxv4s32*//*Label 8301*/ GIMT_Encode4(311056), |
| 118749 | /*GILLT_nxv4s64*//*Label 8302*/ GIMT_Encode4(311846), GIMT_Encode4(0), GIMT_Encode4(0), |
| 118750 | /*GILLT_nxv8s16*//*Label 8303*/ GIMT_Encode4(312636), |
| 118751 | /*GILLT_nxv8s32*//*Label 8304*/ GIMT_Encode4(313426), |
| 118752 | /*GILLT_nxv8s64*//*Label 8305*/ GIMT_Encode4(314216), GIMT_Encode4(0), GIMT_Encode4(0), |
| 118753 | /*GILLT_nxv16s16*//*Label 8306*/ GIMT_Encode4(315006), |
| 118754 | /*GILLT_nxv16s32*//*Label 8307*/ GIMT_Encode4(315796), GIMT_Encode4(0), GIMT_Encode4(0), |
| 118755 | /*GILLT_nxv32s16*//*Label 8308*/ GIMT_Encode4(316586), |
| 118756 | // Label 8291: @300863 |
| 118757 | GIM_Try, /*On fail goto*//*Label 8310*/ GIMT_Encode4(302298), |
| 118758 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 118759 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 118760 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 118761 | GIM_Try, /*On fail goto*//*Label 8311*/ GIMT_Encode4(300949), // Rule ID 2066 // |
| 118762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 118763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118764 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118765 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118766 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118767 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118768 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118769 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118770 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118771 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118772 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118773 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118774 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 118775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 118776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118778 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118781 | GIR_RootConstrainSelectedInstOperands, |
| 118782 | // GIR_Coverage, 2066, |
| 118783 | GIR_EraseRootFromParent_Done, |
| 118784 | // Label 8311: @300949 |
| 118785 | GIM_Try, /*On fail goto*//*Label 8312*/ GIMT_Encode4(301021), // Rule ID 2067 // |
| 118786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 118787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118789 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118790 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118791 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118792 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118793 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118794 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118795 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118796 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118797 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118798 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 118799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 118800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118802 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118805 | GIR_RootConstrainSelectedInstOperands, |
| 118806 | // GIR_Coverage, 2067, |
| 118807 | GIR_EraseRootFromParent_Done, |
| 118808 | // Label 8312: @301021 |
| 118809 | GIM_Try, /*On fail goto*//*Label 8313*/ GIMT_Encode4(301093), // Rule ID 2098 // |
| 118810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 118811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118813 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118815 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118816 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118817 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118818 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118819 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118820 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118821 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118822 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 118823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 118824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118826 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118829 | GIR_RootConstrainSelectedInstOperands, |
| 118830 | // GIR_Coverage, 2098, |
| 118831 | GIR_EraseRootFromParent_Done, |
| 118832 | // Label 8313: @301093 |
| 118833 | GIM_Try, /*On fail goto*//*Label 8314*/ GIMT_Encode4(301165), // Rule ID 2099 // |
| 118834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 118835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118837 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118838 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118839 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118840 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118841 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118842 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118843 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118844 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118845 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118846 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 118847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 118848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118850 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118853 | GIR_RootConstrainSelectedInstOperands, |
| 118854 | // GIR_Coverage, 2099, |
| 118855 | GIR_EraseRootFromParent_Done, |
| 118856 | // Label 8314: @301165 |
| 118857 | GIM_Try, /*On fail goto*//*Label 8315*/ GIMT_Encode4(301237), // Rule ID 65179 // |
| 118858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 118859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118860 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118861 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 118862 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118863 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118864 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118865 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118866 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118867 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118868 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118869 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118870 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 118871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 118872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118874 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 118875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118877 | GIR_RootConstrainSelectedInstOperands, |
| 118878 | // GIR_Coverage, 65179, |
| 118879 | GIR_EraseRootFromParent_Done, |
| 118880 | // Label 8315: @301237 |
| 118881 | GIM_Try, /*On fail goto*//*Label 8316*/ GIMT_Encode4(301309), // Rule ID 65180 // |
| 118882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 118883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118885 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 118886 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118887 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118888 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118889 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118890 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118891 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118892 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118893 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118894 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 118895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H), |
| 118896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118897 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118898 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 118899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118901 | GIR_RootConstrainSelectedInstOperands, |
| 118902 | // GIR_Coverage, 65180, |
| 118903 | GIR_EraseRootFromParent_Done, |
| 118904 | // Label 8316: @301309 |
| 118905 | GIM_Try, /*On fail goto*//*Label 8317*/ GIMT_Encode4(301381), // Rule ID 65187 // |
| 118906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 118907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118908 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118909 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 118910 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118911 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118912 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118913 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118914 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118915 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118916 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118917 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118918 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 118919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 118920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118922 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 118923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118925 | GIR_RootConstrainSelectedInstOperands, |
| 118926 | // GIR_Coverage, 65187, |
| 118927 | GIR_EraseRootFromParent_Done, |
| 118928 | // Label 8317: @301381 |
| 118929 | GIM_Try, /*On fail goto*//*Label 8318*/ GIMT_Encode4(301453), // Rule ID 65188 // |
| 118930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 118931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118932 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 118934 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118935 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118936 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118937 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 118938 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118939 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 118940 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118941 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 118942 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FNMADD_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 118943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_H_INX), |
| 118944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118946 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 118947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 118948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118949 | GIR_RootConstrainSelectedInstOperands, |
| 118950 | // GIR_Coverage, 65188, |
| 118951 | GIR_EraseRootFromParent_Done, |
| 118952 | // Label 8318: @301453 |
| 118953 | GIM_Try, /*On fail goto*//*Label 8319*/ GIMT_Encode4(301510), // Rule ID 2062 // |
| 118954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 118955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118956 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118957 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118958 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118959 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118960 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118961 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118962 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 118963 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 118964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 118965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118967 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118968 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 118969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118970 | GIR_RootConstrainSelectedInstOperands, |
| 118971 | // GIR_Coverage, 2062, |
| 118972 | GIR_EraseRootFromParent_Done, |
| 118973 | // Label 8319: @301510 |
| 118974 | GIM_Try, /*On fail goto*//*Label 8320*/ GIMT_Encode4(301567), // Rule ID 2063 // |
| 118975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 118976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118977 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118978 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 118979 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 118980 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118982 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 118983 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 118984 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 118985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 118986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 118987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 118988 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 118989 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 118990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 118991 | GIR_RootConstrainSelectedInstOperands, |
| 118992 | // GIR_Coverage, 2063, |
| 118993 | GIR_EraseRootFromParent_Done, |
| 118994 | // Label 8320: @301567 |
| 118995 | GIM_Try, /*On fail goto*//*Label 8321*/ GIMT_Encode4(301624), // Rule ID 2094 // |
| 118996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 118997 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 118998 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118999 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119000 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119001 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119002 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119003 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119004 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119005 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 119007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119009 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119010 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119012 | GIR_RootConstrainSelectedInstOperands, |
| 119013 | // GIR_Coverage, 2094, |
| 119014 | GIR_EraseRootFromParent_Done, |
| 119015 | // Label 8321: @301624 |
| 119016 | GIM_Try, /*On fail goto*//*Label 8322*/ GIMT_Encode4(301681), // Rule ID 2095 // |
| 119017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 119018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119019 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119020 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119021 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119022 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119023 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119024 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119025 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119026 | // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 119028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119030 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119031 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119033 | GIR_RootConstrainSelectedInstOperands, |
| 119034 | // GIR_Coverage, 2095, |
| 119035 | GIR_EraseRootFromParent_Done, |
| 119036 | // Label 8322: @301681 |
| 119037 | GIM_Try, /*On fail goto*//*Label 8323*/ GIMT_Encode4(301738), // Rule ID 65175 // |
| 119038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 119039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119040 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119041 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119042 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119043 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119044 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119045 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119046 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119047 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 119049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119051 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119052 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119054 | GIR_RootConstrainSelectedInstOperands, |
| 119055 | // GIR_Coverage, 65175, |
| 119056 | GIR_EraseRootFromParent_Done, |
| 119057 | // Label 8323: @301738 |
| 119058 | GIM_Try, /*On fail goto*//*Label 8324*/ GIMT_Encode4(301795), // Rule ID 65176 // |
| 119059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 119060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119061 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119062 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119063 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119064 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119065 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119066 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119067 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119068 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3) => (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H), |
| 119070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119072 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119073 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119075 | GIR_RootConstrainSelectedInstOperands, |
| 119076 | // GIR_Coverage, 65176, |
| 119077 | GIR_EraseRootFromParent_Done, |
| 119078 | // Label 8324: @301795 |
| 119079 | GIM_Try, /*On fail goto*//*Label 8325*/ GIMT_Encode4(301852), // Rule ID 65183 // |
| 119080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 119081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119082 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119083 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119084 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119085 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119086 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119087 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119088 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119089 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 119091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119093 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119094 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119096 | GIR_RootConstrainSelectedInstOperands, |
| 119097 | // GIR_Coverage, 65183, |
| 119098 | GIR_EraseRootFromParent_Done, |
| 119099 | // Label 8325: @301852 |
| 119100 | GIM_Try, /*On fail goto*//*Label 8326*/ GIMT_Encode4(301909), // Rule ID 65184 // |
| 119101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 119102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119103 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119104 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119105 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119106 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119107 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119108 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119109 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119110 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1), FPR16INX:{ *:[f16] }:$rs3) => (FNMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_H_INX), |
| 119112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119114 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119115 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119117 | GIR_RootConstrainSelectedInstOperands, |
| 119118 | // GIR_Coverage, 65184, |
| 119119 | GIR_EraseRootFromParent_Done, |
| 119120 | // Label 8326: @301909 |
| 119121 | GIM_Try, /*On fail goto*//*Label 8327*/ GIMT_Encode4(301966), // Rule ID 2058 // |
| 119122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 119123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119124 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119125 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119126 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119127 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119128 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119129 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119130 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119131 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H), |
| 119133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119134 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119135 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119138 | GIR_RootConstrainSelectedInstOperands, |
| 119139 | // GIR_Coverage, 2058, |
| 119140 | GIR_EraseRootFromParent_Done, |
| 119141 | // Label 8327: @301966 |
| 119142 | GIM_Try, /*On fail goto*//*Label 8328*/ GIMT_Encode4(302023), // Rule ID 2059 // |
| 119143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 119144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119145 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119146 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119148 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119149 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119150 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119151 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119152 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3)) => (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H), |
| 119154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119155 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119156 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119159 | GIR_RootConstrainSelectedInstOperands, |
| 119160 | // GIR_Coverage, 2059, |
| 119161 | GIR_EraseRootFromParent_Done, |
| 119162 | // Label 8328: @302023 |
| 119163 | GIM_Try, /*On fail goto*//*Label 8329*/ GIMT_Encode4(302080), // Rule ID 2090 // |
| 119164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 119165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119167 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119170 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119171 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119172 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119173 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H_INX), |
| 119175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119176 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119177 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119180 | GIR_RootConstrainSelectedInstOperands, |
| 119181 | // GIR_Coverage, 2090, |
| 119182 | GIR_EraseRootFromParent_Done, |
| 119183 | // Label 8329: @302080 |
| 119184 | GIM_Try, /*On fail goto*//*Label 8330*/ GIMT_Encode4(302137), // Rule ID 2091 // |
| 119185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 119186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119187 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119188 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119189 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119190 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119191 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119192 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119193 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119194 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs3)) => (FMSUB_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_H_INX), |
| 119196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119197 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119198 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119201 | GIR_RootConstrainSelectedInstOperands, |
| 119202 | // GIR_Coverage, 2091, |
| 119203 | GIR_EraseRootFromParent_Done, |
| 119204 | // Label 8330: @302137 |
| 119205 | GIM_Try, /*On fail goto*//*Label 8331*/ GIMT_Encode4(302177), // Rule ID 2054 // |
| 119206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 119207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119208 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119209 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119210 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119211 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FMADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H), |
| 119213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119214 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119215 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119216 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119218 | GIR_RootConstrainSelectedInstOperands, |
| 119219 | // GIR_Coverage, 2054, |
| 119220 | GIR_EraseRootFromParent_Done, |
| 119221 | // Label 8331: @302177 |
| 119222 | GIM_Try, /*On fail goto*//*Label 8332*/ GIMT_Encode4(302217), // Rule ID 2055 // |
| 119223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 119224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119226 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119227 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 119228 | // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3) => (FMADD_H:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H), |
| 119230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119231 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119232 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119233 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119235 | GIR_RootConstrainSelectedInstOperands, |
| 119236 | // GIR_Coverage, 2055, |
| 119237 | GIR_EraseRootFromParent_Done, |
| 119238 | // Label 8332: @302217 |
| 119239 | GIM_Try, /*On fail goto*//*Label 8333*/ GIMT_Encode4(302257), // Rule ID 2086 // |
| 119240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 119241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119242 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119243 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119244 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119245 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FMADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i64] }) |
| 119246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H_INX), |
| 119247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119248 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119249 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119250 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119252 | GIR_RootConstrainSelectedInstOperands, |
| 119253 | // GIR_Coverage, 2086, |
| 119254 | GIR_EraseRootFromParent_Done, |
| 119255 | // Label 8333: @302257 |
| 119256 | GIM_Try, /*On fail goto*//*Label 8334*/ GIMT_Encode4(302297), // Rule ID 2087 // |
| 119257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 119258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119261 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 119262 | // (strict_fma:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, FPR16INX:{ *:[f16] }:$rs2, FPR16INX:{ *:[f16] }:$rs3) => (FMADD_H_INX:{ *:[f16] } ?:{ *:[f16] }:$rs1, ?:{ *:[f16] }:$rs2, ?:{ *:[f16] }:$rs3, 7:{ *:[i32] }) |
| 119263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_H_INX), |
| 119264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119265 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119266 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119267 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119269 | GIR_RootConstrainSelectedInstOperands, |
| 119270 | // GIR_Coverage, 2087, |
| 119271 | GIR_EraseRootFromParent_Done, |
| 119272 | // Label 8334: @302297 |
| 119273 | GIM_Reject, |
| 119274 | // Label 8310: @302298 |
| 119275 | GIM_Reject, |
| 119276 | // Label 8292: @302299 |
| 119277 | GIM_Try, /*On fail goto*//*Label 8335*/ GIMT_Encode4(303734), |
| 119278 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 119279 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 119280 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 119281 | GIM_Try, /*On fail goto*//*Label 8336*/ GIMT_Encode4(302385), // Rule ID 1385 // |
| 119282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 119283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119286 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119287 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119288 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119289 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119290 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119291 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119292 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119293 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119294 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 119296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119298 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119301 | GIR_RootConstrainSelectedInstOperands, |
| 119302 | // GIR_Coverage, 1385, |
| 119303 | GIR_EraseRootFromParent_Done, |
| 119304 | // Label 8336: @302385 |
| 119305 | GIM_Try, /*On fail goto*//*Label 8337*/ GIMT_Encode4(302457), // Rule ID 1386 // |
| 119306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 119307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119309 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119310 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119311 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119312 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119313 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119314 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119315 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119316 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119317 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119318 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 119320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119322 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119325 | GIR_RootConstrainSelectedInstOperands, |
| 119326 | // GIR_Coverage, 1386, |
| 119327 | GIR_EraseRootFromParent_Done, |
| 119328 | // Label 8337: @302457 |
| 119329 | GIM_Try, /*On fail goto*//*Label 8338*/ GIMT_Encode4(302529), // Rule ID 1406 // |
| 119330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 119331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119335 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119336 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119337 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119338 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119339 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119340 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119341 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119342 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 119344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119346 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119349 | GIR_RootConstrainSelectedInstOperands, |
| 119350 | // GIR_Coverage, 1406, |
| 119351 | GIR_EraseRootFromParent_Done, |
| 119352 | // Label 8338: @302529 |
| 119353 | GIM_Try, /*On fail goto*//*Label 8339*/ GIMT_Encode4(302601), // Rule ID 1407 // |
| 119354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 119355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119359 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119361 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119362 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119363 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119364 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119365 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119366 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 119368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119370 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119373 | GIR_RootConstrainSelectedInstOperands, |
| 119374 | // GIR_Coverage, 1407, |
| 119375 | GIR_EraseRootFromParent_Done, |
| 119376 | // Label 8339: @302601 |
| 119377 | GIM_Try, /*On fail goto*//*Label 8340*/ GIMT_Encode4(302673), // Rule ID 65143 // |
| 119378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 119379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119380 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119381 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119382 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119383 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119384 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119385 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119386 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119387 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119388 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119389 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119390 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 119392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119394 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119397 | GIR_RootConstrainSelectedInstOperands, |
| 119398 | // GIR_Coverage, 65143, |
| 119399 | GIR_EraseRootFromParent_Done, |
| 119400 | // Label 8340: @302673 |
| 119401 | GIM_Try, /*On fail goto*//*Label 8341*/ GIMT_Encode4(302745), // Rule ID 65144 // |
| 119402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 119403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119404 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119405 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119406 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119407 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119408 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119409 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119410 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119411 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119412 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119413 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119414 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S), |
| 119416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119418 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119421 | GIR_RootConstrainSelectedInstOperands, |
| 119422 | // GIR_Coverage, 65144, |
| 119423 | GIR_EraseRootFromParent_Done, |
| 119424 | // Label 8341: @302745 |
| 119425 | GIM_Try, /*On fail goto*//*Label 8342*/ GIMT_Encode4(302817), // Rule ID 65151 // |
| 119426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 119427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119429 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119430 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119431 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119432 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119433 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119434 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119435 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119436 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119437 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119438 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 119440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119442 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119445 | GIR_RootConstrainSelectedInstOperands, |
| 119446 | // GIR_Coverage, 65151, |
| 119447 | GIR_EraseRootFromParent_Done, |
| 119448 | // Label 8342: @302817 |
| 119449 | GIM_Try, /*On fail goto*//*Label 8343*/ GIMT_Encode4(302889), // Rule ID 65152 // |
| 119450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 119451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119452 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119453 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119454 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119455 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119456 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119457 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119458 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119459 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119460 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119461 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119462 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FNMADD_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_S_INX), |
| 119464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119466 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119469 | GIR_RootConstrainSelectedInstOperands, |
| 119470 | // GIR_Coverage, 65152, |
| 119471 | GIR_EraseRootFromParent_Done, |
| 119472 | // Label 8343: @302889 |
| 119473 | GIM_Try, /*On fail goto*//*Label 8344*/ GIMT_Encode4(302946), // Rule ID 1381 // |
| 119474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 119475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119476 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119477 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119478 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119479 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119480 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119481 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119482 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119483 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 119485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119487 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119488 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119490 | GIR_RootConstrainSelectedInstOperands, |
| 119491 | // GIR_Coverage, 1381, |
| 119492 | GIR_EraseRootFromParent_Done, |
| 119493 | // Label 8344: @302946 |
| 119494 | GIM_Try, /*On fail goto*//*Label 8345*/ GIMT_Encode4(303003), // Rule ID 1382 // |
| 119495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 119496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119497 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119498 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119499 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119500 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119501 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119502 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119503 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119504 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 119506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119508 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119509 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119511 | GIR_RootConstrainSelectedInstOperands, |
| 119512 | // GIR_Coverage, 1382, |
| 119513 | GIR_EraseRootFromParent_Done, |
| 119514 | // Label 8345: @303003 |
| 119515 | GIM_Try, /*On fail goto*//*Label 8346*/ GIMT_Encode4(303060), // Rule ID 1402 // |
| 119516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 119517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119518 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119519 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119520 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119521 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119522 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119523 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119524 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119525 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 119527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119529 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119530 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119532 | GIR_RootConstrainSelectedInstOperands, |
| 119533 | // GIR_Coverage, 1402, |
| 119534 | GIR_EraseRootFromParent_Done, |
| 119535 | // Label 8346: @303060 |
| 119536 | GIM_Try, /*On fail goto*//*Label 8347*/ GIMT_Encode4(303117), // Rule ID 1403 // |
| 119537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 119538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119539 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119540 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119541 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119542 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119543 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119544 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119545 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119546 | // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 119548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119550 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119551 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119553 | GIR_RootConstrainSelectedInstOperands, |
| 119554 | // GIR_Coverage, 1403, |
| 119555 | GIR_EraseRootFromParent_Done, |
| 119556 | // Label 8347: @303117 |
| 119557 | GIM_Try, /*On fail goto*//*Label 8348*/ GIMT_Encode4(303174), // Rule ID 65139 // |
| 119558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 119559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119560 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119561 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119562 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119563 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119564 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119565 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119566 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119567 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 119569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119570 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119571 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119572 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119574 | GIR_RootConstrainSelectedInstOperands, |
| 119575 | // GIR_Coverage, 65139, |
| 119576 | GIR_EraseRootFromParent_Done, |
| 119577 | // Label 8348: @303174 |
| 119578 | GIM_Try, /*On fail goto*//*Label 8349*/ GIMT_Encode4(303231), // Rule ID 65140 // |
| 119579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 119580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119582 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119583 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119584 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119585 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119586 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119587 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119588 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S), |
| 119590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119592 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119593 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119595 | GIR_RootConstrainSelectedInstOperands, |
| 119596 | // GIR_Coverage, 65140, |
| 119597 | GIR_EraseRootFromParent_Done, |
| 119598 | // Label 8349: @303231 |
| 119599 | GIM_Try, /*On fail goto*//*Label 8350*/ GIMT_Encode4(303288), // Rule ID 65147 // |
| 119600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 119601 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119602 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119603 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119605 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119606 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119607 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119608 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119609 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 119611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119613 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119614 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119616 | GIR_RootConstrainSelectedInstOperands, |
| 119617 | // GIR_Coverage, 65147, |
| 119618 | GIR_EraseRootFromParent_Done, |
| 119619 | // Label 8350: @303288 |
| 119620 | GIM_Try, /*On fail goto*//*Label 8351*/ GIMT_Encode4(303345), // Rule ID 65148 // |
| 119621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 119622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119624 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119625 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119626 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119627 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119628 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119629 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119630 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1), FPR32INX:{ *:[f32] }:$rs3) => (FNMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_S_INX), |
| 119632 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119634 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119635 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119637 | GIR_RootConstrainSelectedInstOperands, |
| 119638 | // GIR_Coverage, 65148, |
| 119639 | GIR_EraseRootFromParent_Done, |
| 119640 | // Label 8351: @303345 |
| 119641 | GIM_Try, /*On fail goto*//*Label 8352*/ GIMT_Encode4(303402), // Rule ID 1377 // |
| 119642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 119643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119644 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119645 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119647 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119648 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119649 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119650 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119651 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S), |
| 119653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119654 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119655 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119658 | GIR_RootConstrainSelectedInstOperands, |
| 119659 | // GIR_Coverage, 1377, |
| 119660 | GIR_EraseRootFromParent_Done, |
| 119661 | // Label 8352: @303402 |
| 119662 | GIM_Try, /*On fail goto*//*Label 8353*/ GIMT_Encode4(303459), // Rule ID 1378 // |
| 119663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 119664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119665 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119666 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119667 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119668 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119669 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119670 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119671 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119672 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S), |
| 119674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119675 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119676 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119677 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119679 | GIR_RootConstrainSelectedInstOperands, |
| 119680 | // GIR_Coverage, 1378, |
| 119681 | GIR_EraseRootFromParent_Done, |
| 119682 | // Label 8353: @303459 |
| 119683 | GIM_Try, /*On fail goto*//*Label 8354*/ GIMT_Encode4(303516), // Rule ID 1398 // |
| 119684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 119685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119688 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119689 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119690 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119691 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119692 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119693 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S_INX), |
| 119695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119696 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119697 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119700 | GIR_RootConstrainSelectedInstOperands, |
| 119701 | // GIR_Coverage, 1398, |
| 119702 | GIR_EraseRootFromParent_Done, |
| 119703 | // Label 8354: @303516 |
| 119704 | GIM_Try, /*On fail goto*//*Label 8355*/ GIMT_Encode4(303573), // Rule ID 1399 // |
| 119705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 119706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119708 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 119710 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119711 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119712 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119713 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119714 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs3)) => (FMSUB_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_S_INX), |
| 119716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119717 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119718 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 119720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119721 | GIR_RootConstrainSelectedInstOperands, |
| 119722 | // GIR_Coverage, 1399, |
| 119723 | GIR_EraseRootFromParent_Done, |
| 119724 | // Label 8355: @303573 |
| 119725 | GIM_Try, /*On fail goto*//*Label 8356*/ GIMT_Encode4(303613), // Rule ID 1373 // |
| 119726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 119727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119730 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119731 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S), |
| 119733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119734 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119735 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119736 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119738 | GIR_RootConstrainSelectedInstOperands, |
| 119739 | // GIR_Coverage, 1373, |
| 119740 | GIR_EraseRootFromParent_Done, |
| 119741 | // Label 8356: @303613 |
| 119742 | GIM_Try, /*On fail goto*//*Label 8357*/ GIMT_Encode4(303653), // Rule ID 1374 // |
| 119743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 119744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119745 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119746 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119747 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 119748 | // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S), |
| 119750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119751 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119752 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119753 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119755 | GIR_RootConstrainSelectedInstOperands, |
| 119756 | // GIR_Coverage, 1374, |
| 119757 | GIR_EraseRootFromParent_Done, |
| 119758 | // Label 8357: @303653 |
| 119759 | GIM_Try, /*On fail goto*//*Label 8358*/ GIMT_Encode4(303693), // Rule ID 1394 // |
| 119760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 119761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119763 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119764 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119765 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FMADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i64] }) |
| 119766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S_INX), |
| 119767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119768 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119769 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119770 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119772 | GIR_RootConstrainSelectedInstOperands, |
| 119773 | // GIR_Coverage, 1394, |
| 119774 | GIR_EraseRootFromParent_Done, |
| 119775 | // Label 8358: @303693 |
| 119776 | GIM_Try, /*On fail goto*//*Label 8359*/ GIMT_Encode4(303733), // Rule ID 1395 // |
| 119777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 119778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119779 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119780 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119781 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 119782 | // (strict_fma:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, FPR32INX:{ *:[f32] }:$rs2, FPR32INX:{ *:[f32] }:$rs3) => (FMADD_S_INX:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i32] }) |
| 119783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_S_INX), |
| 119784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119785 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 119786 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119787 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 119788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119789 | GIR_RootConstrainSelectedInstOperands, |
| 119790 | // GIR_Coverage, 1395, |
| 119791 | GIR_EraseRootFromParent_Done, |
| 119792 | // Label 8359: @303733 |
| 119793 | GIM_Reject, |
| 119794 | // Label 8335: @303734 |
| 119795 | GIM_Reject, |
| 119796 | // Label 8293: @303735 |
| 119797 | GIM_Try, /*On fail goto*//*Label 8360*/ GIMT_Encode4(305525), |
| 119798 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 119799 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 119800 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 119801 | GIM_Try, /*On fail goto*//*Label 8361*/ GIMT_Encode4(303821), // Rule ID 1715 // |
| 119802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 119803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119804 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119805 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119806 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119807 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119808 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119809 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119810 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119811 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119812 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119813 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119814 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 119815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 119816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119817 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119818 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119821 | GIR_RootConstrainSelectedInstOperands, |
| 119822 | // GIR_Coverage, 1715, |
| 119823 | GIR_EraseRootFromParent_Done, |
| 119824 | // Label 8361: @303821 |
| 119825 | GIM_Try, /*On fail goto*//*Label 8362*/ GIMT_Encode4(303893), // Rule ID 1716 // |
| 119826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 119827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119831 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119833 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119834 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119835 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119836 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119837 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119838 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 119839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 119840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119841 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119842 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119845 | GIR_RootConstrainSelectedInstOperands, |
| 119846 | // GIR_Coverage, 1716, |
| 119847 | GIR_EraseRootFromParent_Done, |
| 119848 | // Label 8362: @303893 |
| 119849 | GIM_Try, /*On fail goto*//*Label 8363*/ GIMT_Encode4(303965), // Rule ID 1738 // |
| 119850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 119851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119852 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119853 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119854 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119855 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119856 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119857 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119858 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119859 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119860 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119861 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119862 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs3)) => (FNMADD_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 119863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_INX), |
| 119864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119866 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119869 | GIR_RootConstrainSelectedInstOperands, |
| 119870 | // GIR_Coverage, 1738, |
| 119871 | GIR_EraseRootFromParent_Done, |
| 119872 | // Label 8363: @303965 |
| 119873 | GIM_Try, /*On fail goto*//*Label 8364*/ GIMT_Encode4(304037), // Rule ID 1767 // |
| 119874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 119875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119878 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119879 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119880 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119881 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119882 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119883 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119884 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119885 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119886 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 119887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 119888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119889 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119890 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119893 | GIR_RootConstrainSelectedInstOperands, |
| 119894 | // GIR_Coverage, 1767, |
| 119895 | GIR_EraseRootFromParent_Done, |
| 119896 | // Label 8364: @304037 |
| 119897 | GIM_Try, /*On fail goto*//*Label 8365*/ GIMT_Encode4(304109), // Rule ID 1768 // |
| 119898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 119899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119900 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119901 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119902 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119903 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119904 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119905 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119906 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119907 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119908 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119909 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119910 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 119911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 119912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119914 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 119915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119917 | GIR_RootConstrainSelectedInstOperands, |
| 119918 | // GIR_Coverage, 1768, |
| 119919 | GIR_EraseRootFromParent_Done, |
| 119920 | // Label 8365: @304109 |
| 119921 | GIM_Try, /*On fail goto*//*Label 8366*/ GIMT_Encode4(304181), // Rule ID 65159 // |
| 119922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 119923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119924 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119926 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119928 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119929 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119930 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119931 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119932 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119933 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119934 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 119935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 119936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119938 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119941 | GIR_RootConstrainSelectedInstOperands, |
| 119942 | // GIR_Coverage, 65159, |
| 119943 | GIR_EraseRootFromParent_Done, |
| 119944 | // Label 8366: @304181 |
| 119945 | GIM_Try, /*On fail goto*//*Label 8367*/ GIMT_Encode4(304253), // Rule ID 65160 // |
| 119946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 119947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119950 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119951 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119952 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119953 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119954 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119955 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119956 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 119957 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119958 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 119959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D), |
| 119960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119962 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119965 | GIR_RootConstrainSelectedInstOperands, |
| 119966 | // GIR_Coverage, 65160, |
| 119967 | GIR_EraseRootFromParent_Done, |
| 119968 | // Label 8367: @304253 |
| 119969 | GIM_Try, /*On fail goto*//*Label 8368*/ GIMT_Encode4(304325), // Rule ID 65165 // |
| 119970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 119971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119972 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119973 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119974 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119975 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 119976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119977 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 119978 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119979 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 119980 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 119981 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119982 | // (strict_fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs3)) => (FNMADD_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 119983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_INX), |
| 119984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 119985 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 119986 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 119987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 119988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 119989 | GIR_RootConstrainSelectedInstOperands, |
| 119990 | // GIR_Coverage, 65165, |
| 119991 | GIR_EraseRootFromParent_Done, |
| 119992 | // Label 8368: @304325 |
| 119993 | GIM_Try, /*On fail goto*//*Label 8369*/ GIMT_Encode4(304397), // Rule ID 65171 // |
| 119994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 119995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119996 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 119997 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119998 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 119999 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120000 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120001 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120002 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120003 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 120004 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120005 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120006 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 120008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120010 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 120012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120013 | GIR_RootConstrainSelectedInstOperands, |
| 120014 | // GIR_Coverage, 65171, |
| 120015 | GIR_EraseRootFromParent_Done, |
| 120016 | // Label 8369: @304397 |
| 120017 | GIM_Try, /*On fail goto*//*Label 8370*/ GIMT_Encode4(304469), // Rule ID 65172 // |
| 120018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 120019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120020 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120021 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120022 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120023 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120024 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120025 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120026 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120027 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 120028 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120029 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120030 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FNMADD_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMADD_D_IN32X), |
| 120032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120034 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 |
| 120036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120037 | GIR_RootConstrainSelectedInstOperands, |
| 120038 | // GIR_Coverage, 65172, |
| 120039 | GIR_EraseRootFromParent_Done, |
| 120040 | // Label 8370: @304469 |
| 120041 | GIM_Try, /*On fail goto*//*Label 8371*/ GIMT_Encode4(304526), // Rule ID 1711 // |
| 120042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 120043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120044 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120045 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120046 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120047 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120048 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120049 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120050 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120051 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 120053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120055 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120056 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120058 | GIR_RootConstrainSelectedInstOperands, |
| 120059 | // GIR_Coverage, 1711, |
| 120060 | GIR_EraseRootFromParent_Done, |
| 120061 | // Label 8371: @304526 |
| 120062 | GIM_Try, /*On fail goto*//*Label 8372*/ GIMT_Encode4(304583), // Rule ID 1712 // |
| 120063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 120064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120065 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120066 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120067 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120068 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120069 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120070 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120071 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120072 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 120074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120076 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120077 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120079 | GIR_RootConstrainSelectedInstOperands, |
| 120080 | // GIR_Coverage, 1712, |
| 120081 | GIR_EraseRootFromParent_Done, |
| 120082 | // Label 8372: @304583 |
| 120083 | GIM_Try, /*On fail goto*//*Label 8373*/ GIMT_Encode4(304640), // Rule ID 1736 // |
| 120084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 120085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120086 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120087 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120088 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120089 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120090 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120091 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120092 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120093 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3) => (FNMSUB_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_INX), |
| 120095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120097 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120098 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120100 | GIR_RootConstrainSelectedInstOperands, |
| 120101 | // GIR_Coverage, 1736, |
| 120102 | GIR_EraseRootFromParent_Done, |
| 120103 | // Label 8373: @304640 |
| 120104 | GIM_Try, /*On fail goto*//*Label 8374*/ GIMT_Encode4(304697), // Rule ID 1763 // |
| 120105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 120106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120107 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120108 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120109 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120110 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120111 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120112 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120113 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120114 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 120116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120118 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120119 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120121 | GIR_RootConstrainSelectedInstOperands, |
| 120122 | // GIR_Coverage, 1763, |
| 120123 | GIR_EraseRootFromParent_Done, |
| 120124 | // Label 8374: @304697 |
| 120125 | GIM_Try, /*On fail goto*//*Label 8375*/ GIMT_Encode4(304754), // Rule ID 1764 // |
| 120126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 120127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120128 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120129 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120130 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120131 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120132 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120133 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120134 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120135 | // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 120137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120139 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120140 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120142 | GIR_RootConstrainSelectedInstOperands, |
| 120143 | // GIR_Coverage, 1764, |
| 120144 | GIR_EraseRootFromParent_Done, |
| 120145 | // Label 8375: @304754 |
| 120146 | GIM_Try, /*On fail goto*//*Label 8376*/ GIMT_Encode4(304811), // Rule ID 65155 // |
| 120147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 120148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120150 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120151 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120152 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120153 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120154 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120155 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120156 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 120158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120159 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120161 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120163 | GIR_RootConstrainSelectedInstOperands, |
| 120164 | // GIR_Coverage, 65155, |
| 120165 | GIR_EraseRootFromParent_Done, |
| 120166 | // Label 8376: @304811 |
| 120167 | GIM_Try, /*On fail goto*//*Label 8377*/ GIMT_Encode4(304868), // Rule ID 65156 // |
| 120168 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 120169 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120170 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120171 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120172 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120173 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120174 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120175 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120176 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120177 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D), |
| 120179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120181 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120182 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120184 | GIR_RootConstrainSelectedInstOperands, |
| 120185 | // GIR_Coverage, 65156, |
| 120186 | GIR_EraseRootFromParent_Done, |
| 120187 | // Label 8377: @304868 |
| 120188 | GIM_Try, /*On fail goto*//*Label 8378*/ GIMT_Encode4(304925), // Rule ID 65163 // |
| 120189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 120190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120191 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120192 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120193 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120194 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120195 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120196 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120197 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120198 | // (strict_fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1), FPR64INX:{ *:[f64] }:$rs3) => (FNMSUB_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_INX), |
| 120200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120202 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120203 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120205 | GIR_RootConstrainSelectedInstOperands, |
| 120206 | // GIR_Coverage, 65163, |
| 120207 | GIR_EraseRootFromParent_Done, |
| 120208 | // Label 8378: @304925 |
| 120209 | GIM_Try, /*On fail goto*//*Label 8379*/ GIMT_Encode4(304982), // Rule ID 65167 // |
| 120210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 120211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120213 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120214 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120215 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120216 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120217 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120218 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120219 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 120221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120223 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120224 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120226 | GIR_RootConstrainSelectedInstOperands, |
| 120227 | // GIR_Coverage, 65167, |
| 120228 | GIR_EraseRootFromParent_Done, |
| 120229 | // Label 8379: @304982 |
| 120230 | GIM_Try, /*On fail goto*//*Label 8380*/ GIMT_Encode4(305039), // Rule ID 65168 // |
| 120231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 120232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120233 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120234 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120235 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120236 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120237 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120238 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120239 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120240 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1), FPR64IN32X:{ *:[f64] }:$rs3) => (FNMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FNMSUB_D_IN32X), |
| 120242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120244 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 120245 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120247 | GIR_RootConstrainSelectedInstOperands, |
| 120248 | // GIR_Coverage, 65168, |
| 120249 | GIR_EraseRootFromParent_Done, |
| 120250 | // Label 8380: @305039 |
| 120251 | GIM_Try, /*On fail goto*//*Label 8381*/ GIMT_Encode4(305096), // Rule ID 1707 // |
| 120252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 120253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120256 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120257 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120258 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120259 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120260 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120261 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D), |
| 120263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120264 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120265 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 120267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120268 | GIR_RootConstrainSelectedInstOperands, |
| 120269 | // GIR_Coverage, 1707, |
| 120270 | GIR_EraseRootFromParent_Done, |
| 120271 | // Label 8381: @305096 |
| 120272 | GIM_Try, /*On fail goto*//*Label 8382*/ GIMT_Encode4(305153), // Rule ID 1708 // |
| 120273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 120274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120275 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120276 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120277 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120278 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120279 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120280 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120281 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120282 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D), |
| 120284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120285 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120286 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 120288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120289 | GIR_RootConstrainSelectedInstOperands, |
| 120290 | // GIR_Coverage, 1708, |
| 120291 | GIR_EraseRootFromParent_Done, |
| 120292 | // Label 8382: @305153 |
| 120293 | GIM_Try, /*On fail goto*//*Label 8383*/ GIMT_Encode4(305210), // Rule ID 1734 // |
| 120294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 120295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120296 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120297 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120298 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120299 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120300 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120301 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120302 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120303 | // (strict_fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs3)) => (FMSUB_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D_INX), |
| 120305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120306 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120307 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 120309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120310 | GIR_RootConstrainSelectedInstOperands, |
| 120311 | // GIR_Coverage, 1734, |
| 120312 | GIR_EraseRootFromParent_Done, |
| 120313 | // Label 8383: @305210 |
| 120314 | GIM_Try, /*On fail goto*//*Label 8384*/ GIMT_Encode4(305267), // Rule ID 1759 // |
| 120315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 120316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120320 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120322 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120323 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120324 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D_IN32X), |
| 120326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120327 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120328 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 120330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120331 | GIR_RootConstrainSelectedInstOperands, |
| 120332 | // GIR_Coverage, 1759, |
| 120333 | GIR_EraseRootFromParent_Done, |
| 120334 | // Label 8384: @305267 |
| 120335 | GIM_Try, /*On fail goto*//*Label 8385*/ GIMT_Encode4(305324), // Rule ID 1760 // |
| 120336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 120337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120338 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120340 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120341 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120342 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 120343 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120344 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120345 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs3)) => (FMSUB_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMSUB_D_IN32X), |
| 120347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120348 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120349 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120350 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 |
| 120351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120352 | GIR_RootConstrainSelectedInstOperands, |
| 120353 | // GIR_Coverage, 1760, |
| 120354 | GIR_EraseRootFromParent_Done, |
| 120355 | // Label 8385: @305324 |
| 120356 | GIM_Try, /*On fail goto*//*Label 8386*/ GIMT_Encode4(305364), // Rule ID 1703 // |
| 120357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 120358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120361 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120362 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D), |
| 120364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120365 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120366 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120367 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120369 | GIR_RootConstrainSelectedInstOperands, |
| 120370 | // GIR_Coverage, 1703, |
| 120371 | GIR_EraseRootFromParent_Done, |
| 120372 | // Label 8386: @305364 |
| 120373 | GIM_Try, /*On fail goto*//*Label 8387*/ GIMT_Encode4(305404), // Rule ID 1704 // |
| 120374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 120375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120378 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 120379 | // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D), |
| 120381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120382 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120383 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120384 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120386 | GIR_RootConstrainSelectedInstOperands, |
| 120387 | // GIR_Coverage, 1704, |
| 120388 | GIR_EraseRootFromParent_Done, |
| 120389 | // Label 8387: @305404 |
| 120390 | GIM_Try, /*On fail goto*//*Label 8388*/ GIMT_Encode4(305444), // Rule ID 1732 // |
| 120391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 120392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120394 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120395 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 120396 | // (strict_fma:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, FPR64INX:{ *:[f64] }:$rs2, FPR64INX:{ *:[f64] }:$rs3) => (FMADD_D_INX:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D_INX), |
| 120398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120399 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120400 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120401 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120403 | GIR_RootConstrainSelectedInstOperands, |
| 120404 | // GIR_Coverage, 1732, |
| 120405 | GIR_EraseRootFromParent_Done, |
| 120406 | // Label 8388: @305444 |
| 120407 | GIM_Try, /*On fail goto*//*Label 8389*/ GIMT_Encode4(305484), // Rule ID 1755 // |
| 120408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 120409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120410 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120411 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120412 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120413 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FMADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] }) |
| 120414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D_IN32X), |
| 120415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120416 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120417 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120418 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120420 | GIR_RootConstrainSelectedInstOperands, |
| 120421 | // GIR_Coverage, 1755, |
| 120422 | GIR_EraseRootFromParent_Done, |
| 120423 | // Label 8389: @305484 |
| 120424 | GIM_Try, /*On fail goto*//*Label 8390*/ GIMT_Encode4(305524), // Rule ID 1756 // |
| 120425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 120426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120427 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120428 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120429 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 120430 | // (strict_fma:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, FPR64IN32X:{ *:[f64] }:$rs2, FPR64IN32X:{ *:[f64] }:$rs3) => (FMADD_D_IN32X:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i32] }) |
| 120431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FMADD_D_IN32X), |
| 120432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120433 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120434 | GIR_RootToRootCopy, /*OpIdx*/2, // rs2 |
| 120435 | GIR_RootToRootCopy, /*OpIdx*/3, // rs3 |
| 120436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120437 | GIR_RootConstrainSelectedInstOperands, |
| 120438 | // GIR_Coverage, 1756, |
| 120439 | GIR_EraseRootFromParent_Done, |
| 120440 | // Label 8390: @305524 |
| 120441 | GIM_Reject, |
| 120442 | // Label 8360: @305525 |
| 120443 | GIM_Reject, |
| 120444 | // Label 8294: @305526 |
| 120445 | GIM_Try, /*On fail goto*//*Label 8391*/ GIMT_Encode4(306315), |
| 120446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120447 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, |
| 120448 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s16, |
| 120449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120450 | GIM_Try, /*On fail goto*//*Label 8392*/ GIMT_Encode4(305621), // Rule ID 55460 // |
| 120451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 120452 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120453 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120454 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120455 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120456 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120457 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120458 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120459 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120460 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120461 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120462 | // (strict_fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 120463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 120464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120465 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120472 | GIR_RootConstrainSelectedInstOperands, |
| 120473 | // GIR_Coverage, 55460, |
| 120474 | GIR_EraseRootFromParent_Done, |
| 120475 | // Label 8392: @305621 |
| 120476 | GIM_Try, /*On fail goto*//*Label 8393*/ GIMT_Encode4(305698), // Rule ID 55461 // |
| 120477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 120478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120479 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120480 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120481 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120482 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120483 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120484 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120485 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120486 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120487 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120488 | // (strict_fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 120489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 120490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120491 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120498 | GIR_RootConstrainSelectedInstOperands, |
| 120499 | // GIR_Coverage, 55461, |
| 120500 | GIR_EraseRootFromParent_Done, |
| 120501 | // Label 8393: @305698 |
| 120502 | GIM_Try, /*On fail goto*//*Label 8394*/ GIMT_Encode4(305775), // Rule ID 71994 // |
| 120503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 120504 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120505 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120506 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120507 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120508 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120509 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120510 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120511 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120512 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120513 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120514 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 120515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 120516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120517 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120524 | GIR_RootConstrainSelectedInstOperands, |
| 120525 | // GIR_Coverage, 71994, |
| 120526 | GIR_EraseRootFromParent_Done, |
| 120527 | // Label 8394: @305775 |
| 120528 | GIM_Try, /*On fail goto*//*Label 8395*/ GIMT_Encode4(305852), // Rule ID 71995 // |
| 120529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 120530 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120531 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120532 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120533 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120534 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120535 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120536 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120537 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120538 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120539 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120540 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFNMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 120541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF4_E16), |
| 120542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120543 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120544 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120550 | GIR_RootConstrainSelectedInstOperands, |
| 120551 | // GIR_Coverage, 71995, |
| 120552 | GIR_EraseRootFromParent_Done, |
| 120553 | // Label 8395: @305852 |
| 120554 | GIM_Try, /*On fail goto*//*Label 8396*/ GIMT_Encode4(305914), // Rule ID 55464 // |
| 120555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 120556 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120557 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120558 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120559 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120560 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120561 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120562 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120563 | // (strict_fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 120564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 120565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120566 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120568 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120573 | GIR_RootConstrainSelectedInstOperands, |
| 120574 | // GIR_Coverage, 55464, |
| 120575 | GIR_EraseRootFromParent_Done, |
| 120576 | // Label 8396: @305914 |
| 120577 | GIM_Try, /*On fail goto*//*Label 8397*/ GIMT_Encode4(305976), // Rule ID 55465 // |
| 120578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 120579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120580 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120581 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120582 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120583 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120584 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120585 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120586 | // (strict_fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 120587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 120588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120589 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120590 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120591 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120596 | GIR_RootConstrainSelectedInstOperands, |
| 120597 | // GIR_Coverage, 55465, |
| 120598 | GIR_EraseRootFromParent_Done, |
| 120599 | // Label 8397: @305976 |
| 120600 | GIM_Try, /*On fail goto*//*Label 8398*/ GIMT_Encode4(306038), // Rule ID 71998 // |
| 120601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 120602 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120603 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120605 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120606 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120607 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120608 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120609 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 120610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 120611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120612 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120614 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120619 | GIR_RootConstrainSelectedInstOperands, |
| 120620 | // GIR_Coverage, 71998, |
| 120621 | GIR_EraseRootFromParent_Done, |
| 120622 | // Label 8398: @306038 |
| 120623 | GIM_Try, /*On fail goto*//*Label 8399*/ GIMT_Encode4(306100), // Rule ID 71999 // |
| 120624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 120625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120626 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120627 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120628 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120629 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120630 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120631 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120632 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFNMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 120633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF4_E16), |
| 120634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120635 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120637 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120642 | GIR_RootConstrainSelectedInstOperands, |
| 120643 | // GIR_Coverage, 71999, |
| 120644 | GIR_EraseRootFromParent_Done, |
| 120645 | // Label 8399: @306100 |
| 120646 | GIM_Try, /*On fail goto*//*Label 8400*/ GIMT_Encode4(306162), // Rule ID 55456 // |
| 120647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 120648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120649 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120650 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120651 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120652 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120653 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120654 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120655 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 120656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF4_E16), |
| 120657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120658 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120659 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 120661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120665 | GIR_RootConstrainSelectedInstOperands, |
| 120666 | // GIR_Coverage, 55456, |
| 120667 | GIR_EraseRootFromParent_Done, |
| 120668 | // Label 8400: @306162 |
| 120669 | GIM_Try, /*On fail goto*//*Label 8401*/ GIMT_Encode4(306224), // Rule ID 55457 // |
| 120670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 120671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120672 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120674 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 120676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120677 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120678 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)) => (PseudoVFMSUB_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 120679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF4_E16), |
| 120680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120681 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 120684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120688 | GIR_RootConstrainSelectedInstOperands, |
| 120689 | // GIR_Coverage, 55457, |
| 120690 | GIR_EraseRootFromParent_Done, |
| 120691 | // Label 8401: @306224 |
| 120692 | GIM_Try, /*On fail goto*//*Label 8402*/ GIMT_Encode4(306269), // Rule ID 55452 // |
| 120693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 120694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120696 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120697 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 120698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF4_E16), |
| 120699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120700 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120701 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120702 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120707 | GIR_RootConstrainSelectedInstOperands, |
| 120708 | // GIR_Coverage, 55452, |
| 120709 | GIR_EraseRootFromParent_Done, |
| 120710 | // Label 8402: @306269 |
| 120711 | GIM_Try, /*On fail goto*//*Label 8403*/ GIMT_Encode4(306314), // Rule ID 55453 // |
| 120712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 120713 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120714 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120715 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120716 | // (strict_fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFMADD_VV_MF4_E16:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 120717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF4_E16), |
| 120718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120719 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120720 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120721 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 120725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120726 | GIR_RootConstrainSelectedInstOperands, |
| 120727 | // GIR_Coverage, 55453, |
| 120728 | GIR_EraseRootFromParent_Done, |
| 120729 | // Label 8403: @306314 |
| 120730 | GIM_Reject, |
| 120731 | // Label 8391: @306315 |
| 120732 | GIM_Reject, |
| 120733 | // Label 8295: @306316 |
| 120734 | GIM_Try, /*On fail goto*//*Label 8404*/ GIMT_Encode4(307105), |
| 120735 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, |
| 120737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s32, |
| 120738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120739 | GIM_Try, /*On fail goto*//*Label 8405*/ GIMT_Encode4(306411), // Rule ID 55588 // |
| 120740 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 120741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120742 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120743 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120746 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120747 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120748 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120749 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120750 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120751 | // (strict_fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 120752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 120753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120754 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120761 | GIR_RootConstrainSelectedInstOperands, |
| 120762 | // GIR_Coverage, 55588, |
| 120763 | GIR_EraseRootFromParent_Done, |
| 120764 | // Label 8405: @306411 |
| 120765 | GIM_Try, /*On fail goto*//*Label 8406*/ GIMT_Encode4(306488), // Rule ID 55589 // |
| 120766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 120767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120768 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120769 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120770 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120771 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120772 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120773 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120774 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120775 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120776 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120777 | // (strict_fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 120778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 120779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120780 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120787 | GIR_RootConstrainSelectedInstOperands, |
| 120788 | // GIR_Coverage, 55589, |
| 120789 | GIR_EraseRootFromParent_Done, |
| 120790 | // Label 8406: @306488 |
| 120791 | GIM_Try, /*On fail goto*//*Label 8407*/ GIMT_Encode4(306565), // Rule ID 72106 // |
| 120792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 120793 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120794 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120795 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120796 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120797 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120798 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120799 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120800 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120801 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120802 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120803 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 120804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 120805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120806 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120808 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120813 | GIR_RootConstrainSelectedInstOperands, |
| 120814 | // GIR_Coverage, 72106, |
| 120815 | GIR_EraseRootFromParent_Done, |
| 120816 | // Label 8407: @306565 |
| 120817 | GIM_Try, /*On fail goto*//*Label 8408*/ GIMT_Encode4(306642), // Rule ID 72107 // |
| 120818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 120819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120820 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120821 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120822 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120823 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120824 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 120825 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120826 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120827 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120828 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 120829 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 120830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E32), |
| 120831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120832 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 120835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120839 | GIR_RootConstrainSelectedInstOperands, |
| 120840 | // GIR_Coverage, 72107, |
| 120841 | GIR_EraseRootFromParent_Done, |
| 120842 | // Label 8408: @306642 |
| 120843 | GIM_Try, /*On fail goto*//*Label 8409*/ GIMT_Encode4(306704), // Rule ID 55592 // |
| 120844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 120845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120846 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120848 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120849 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120850 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120851 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120852 | // (strict_fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 120853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 120854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120855 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120857 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120862 | GIR_RootConstrainSelectedInstOperands, |
| 120863 | // GIR_Coverage, 55592, |
| 120864 | GIR_EraseRootFromParent_Done, |
| 120865 | // Label 8409: @306704 |
| 120866 | GIM_Try, /*On fail goto*//*Label 8410*/ GIMT_Encode4(306766), // Rule ID 55593 // |
| 120867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 120868 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120869 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120870 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120871 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120872 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120873 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120874 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120875 | // (strict_fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 120876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 120877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120878 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120880 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120885 | GIR_RootConstrainSelectedInstOperands, |
| 120886 | // GIR_Coverage, 55593, |
| 120887 | GIR_EraseRootFromParent_Done, |
| 120888 | // Label 8410: @306766 |
| 120889 | GIM_Try, /*On fail goto*//*Label 8411*/ GIMT_Encode4(306828), // Rule ID 72110 // |
| 120890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 120891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120892 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120893 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120894 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120895 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120896 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120897 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120898 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 120899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 120900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120901 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120903 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120908 | GIR_RootConstrainSelectedInstOperands, |
| 120909 | // GIR_Coverage, 72110, |
| 120910 | GIR_EraseRootFromParent_Done, |
| 120911 | // Label 8411: @306828 |
| 120912 | GIM_Try, /*On fail goto*//*Label 8412*/ GIMT_Encode4(306890), // Rule ID 72111 // |
| 120913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 120914 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120915 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 120916 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120917 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120918 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120919 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120920 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120921 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 120922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E32), |
| 120923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120924 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 120925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 120926 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120931 | GIR_RootConstrainSelectedInstOperands, |
| 120932 | // GIR_Coverage, 72111, |
| 120933 | GIR_EraseRootFromParent_Done, |
| 120934 | // Label 8412: @306890 |
| 120935 | GIM_Try, /*On fail goto*//*Label 8413*/ GIMT_Encode4(306952), // Rule ID 55584 // |
| 120936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 120937 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120938 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120939 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120940 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120941 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120942 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120943 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120944 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 120945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E32), |
| 120946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120947 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120948 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 120950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120954 | GIR_RootConstrainSelectedInstOperands, |
| 120955 | // GIR_Coverage, 55584, |
| 120956 | GIR_EraseRootFromParent_Done, |
| 120957 | // Label 8413: @306952 |
| 120958 | GIM_Try, /*On fail goto*//*Label 8414*/ GIMT_Encode4(307014), // Rule ID 55585 // |
| 120959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 120960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120962 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 120963 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 120964 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 120965 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120966 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 120967 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 120968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E32), |
| 120969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120970 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120971 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 120973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120977 | GIR_RootConstrainSelectedInstOperands, |
| 120978 | // GIR_Coverage, 55585, |
| 120979 | GIR_EraseRootFromParent_Done, |
| 120980 | // Label 8414: @307014 |
| 120981 | GIM_Try, /*On fail goto*//*Label 8415*/ GIMT_Encode4(307059), // Rule ID 55580 // |
| 120982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 120983 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120985 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 120986 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 120987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E32), |
| 120988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 120989 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 120990 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 120991 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 120992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 120993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 120994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 120995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 120996 | GIR_RootConstrainSelectedInstOperands, |
| 120997 | // GIR_Coverage, 55580, |
| 120998 | GIR_EraseRootFromParent_Done, |
| 120999 | // Label 8415: @307059 |
| 121000 | GIM_Try, /*On fail goto*//*Label 8416*/ GIMT_Encode4(307104), // Rule ID 55581 // |
| 121001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121002 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121003 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121004 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121005 | // (strict_fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFMADD_VV_MF2_E32:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E32), |
| 121007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121008 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121009 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121010 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121015 | GIR_RootConstrainSelectedInstOperands, |
| 121016 | // GIR_Coverage, 55581, |
| 121017 | GIR_EraseRootFromParent_Done, |
| 121018 | // Label 8416: @307104 |
| 121019 | GIM_Reject, |
| 121020 | // Label 8404: @307105 |
| 121021 | GIM_Reject, |
| 121022 | // Label 8296: @307106 |
| 121023 | GIM_Try, /*On fail goto*//*Label 8417*/ GIMT_Encode4(307895), |
| 121024 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121025 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, |
| 121026 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s64, |
| 121027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121028 | GIM_Try, /*On fail goto*//*Label 8418*/ GIMT_Encode4(307201), // Rule ID 55780 // |
| 121029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121030 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121031 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121032 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121033 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121034 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121035 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121036 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121037 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121038 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121039 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121040 | // (strict_fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 121042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121043 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121050 | GIR_RootConstrainSelectedInstOperands, |
| 121051 | // GIR_Coverage, 55780, |
| 121052 | GIR_EraseRootFromParent_Done, |
| 121053 | // Label 8418: @307201 |
| 121054 | GIM_Try, /*On fail goto*//*Label 8419*/ GIMT_Encode4(307278), // Rule ID 55781 // |
| 121055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121056 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121057 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121058 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121059 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121060 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121061 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121062 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121063 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121064 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121065 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121066 | // (strict_fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 121068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121069 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121076 | GIR_RootConstrainSelectedInstOperands, |
| 121077 | // GIR_Coverage, 55781, |
| 121078 | GIR_EraseRootFromParent_Done, |
| 121079 | // Label 8419: @307278 |
| 121080 | GIM_Try, /*On fail goto*//*Label 8420*/ GIMT_Encode4(307355), // Rule ID 72274 // |
| 121081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121082 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121083 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121084 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121085 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121086 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121087 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121088 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121089 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121090 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121091 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121092 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 121094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121095 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121097 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121102 | GIR_RootConstrainSelectedInstOperands, |
| 121103 | // GIR_Coverage, 72274, |
| 121104 | GIR_EraseRootFromParent_Done, |
| 121105 | // Label 8420: @307355 |
| 121106 | GIM_Try, /*On fail goto*//*Label 8421*/ GIMT_Encode4(307432), // Rule ID 72275 // |
| 121107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121109 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121110 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121111 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121112 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121113 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121114 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121115 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121116 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121117 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121118 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFNMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E64), |
| 121120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121121 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121123 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121128 | GIR_RootConstrainSelectedInstOperands, |
| 121129 | // GIR_Coverage, 72275, |
| 121130 | GIR_EraseRootFromParent_Done, |
| 121131 | // Label 8421: @307432 |
| 121132 | GIM_Try, /*On fail goto*//*Label 8422*/ GIMT_Encode4(307494), // Rule ID 55784 // |
| 121133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121134 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121135 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121136 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121137 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121138 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121139 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121140 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121141 | // (strict_fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 121143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121144 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121146 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121151 | GIR_RootConstrainSelectedInstOperands, |
| 121152 | // GIR_Coverage, 55784, |
| 121153 | GIR_EraseRootFromParent_Done, |
| 121154 | // Label 8422: @307494 |
| 121155 | GIM_Try, /*On fail goto*//*Label 8423*/ GIMT_Encode4(307556), // Rule ID 55785 // |
| 121156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121157 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121158 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121159 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121160 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121162 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121163 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121164 | // (strict_fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 121166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121167 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121168 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121169 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121174 | GIR_RootConstrainSelectedInstOperands, |
| 121175 | // GIR_Coverage, 55785, |
| 121176 | GIR_EraseRootFromParent_Done, |
| 121177 | // Label 8423: @307556 |
| 121178 | GIM_Try, /*On fail goto*//*Label 8424*/ GIMT_Encode4(307618), // Rule ID 72278 // |
| 121179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121181 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121182 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121184 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121185 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121186 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121187 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 121189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121190 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121192 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121197 | GIR_RootConstrainSelectedInstOperands, |
| 121198 | // GIR_Coverage, 72278, |
| 121199 | GIR_EraseRootFromParent_Done, |
| 121200 | // Label 8424: @307618 |
| 121201 | GIM_Try, /*On fail goto*//*Label 8425*/ GIMT_Encode4(307680), // Rule ID 72279 // |
| 121202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121203 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121204 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121205 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121206 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121207 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121208 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121209 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121210 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFNMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E64), |
| 121212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121213 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121215 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121220 | GIR_RootConstrainSelectedInstOperands, |
| 121221 | // GIR_Coverage, 72279, |
| 121222 | GIR_EraseRootFromParent_Done, |
| 121223 | // Label 8425: @307680 |
| 121224 | GIM_Try, /*On fail goto*//*Label 8426*/ GIMT_Encode4(307742), // Rule ID 55776 // |
| 121225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121226 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121227 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121228 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 121229 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121230 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121231 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121232 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121233 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E64), |
| 121235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121236 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121237 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 121239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121243 | GIR_RootConstrainSelectedInstOperands, |
| 121244 | // GIR_Coverage, 55776, |
| 121245 | GIR_EraseRootFromParent_Done, |
| 121246 | // Label 8426: @307742 |
| 121247 | GIM_Try, /*On fail goto*//*Label 8427*/ GIMT_Encode4(307804), // Rule ID 55777 // |
| 121248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121249 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121250 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 121252 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121253 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 121254 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121255 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121256 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)) => (PseudoVFMSUB_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E64), |
| 121258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121259 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121260 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 121262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121266 | GIR_RootConstrainSelectedInstOperands, |
| 121267 | // GIR_Coverage, 55777, |
| 121268 | GIR_EraseRootFromParent_Done, |
| 121269 | // Label 8427: @307804 |
| 121270 | GIM_Try, /*On fail goto*//*Label 8428*/ GIMT_Encode4(307849), // Rule ID 55772 // |
| 121271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121275 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E64), |
| 121277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121278 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121279 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121280 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121285 | GIR_RootConstrainSelectedInstOperands, |
| 121286 | // GIR_Coverage, 55772, |
| 121287 | GIR_EraseRootFromParent_Done, |
| 121288 | // Label 8428: @307849 |
| 121289 | GIM_Try, /*On fail goto*//*Label 8429*/ GIMT_Encode4(307894), // Rule ID 55773 // |
| 121290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121291 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121292 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121293 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121294 | // (strict_fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFMADD_VV_M1_E64:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E64), |
| 121296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121297 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121298 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121299 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121304 | GIR_RootConstrainSelectedInstOperands, |
| 121305 | // GIR_Coverage, 55773, |
| 121306 | GIR_EraseRootFromParent_Done, |
| 121307 | // Label 8429: @307894 |
| 121308 | GIM_Reject, |
| 121309 | // Label 8417: @307895 |
| 121310 | GIM_Reject, |
| 121311 | // Label 8297: @307896 |
| 121312 | GIM_Try, /*On fail goto*//*Label 8430*/ GIMT_Encode4(308685), |
| 121313 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121314 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, |
| 121315 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16, |
| 121316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121317 | GIM_Try, /*On fail goto*//*Label 8431*/ GIMT_Encode4(307991), // Rule ID 55524 // |
| 121318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 121319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121320 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121322 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121324 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121325 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121326 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121327 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121328 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121329 | // (strict_fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 121330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 121331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121332 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121339 | GIR_RootConstrainSelectedInstOperands, |
| 121340 | // GIR_Coverage, 55524, |
| 121341 | GIR_EraseRootFromParent_Done, |
| 121342 | // Label 8431: @307991 |
| 121343 | GIM_Try, /*On fail goto*//*Label 8432*/ GIMT_Encode4(308068), // Rule ID 55525 // |
| 121344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 121345 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121346 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121347 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121348 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121349 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121350 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121351 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121352 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121353 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121354 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121355 | // (strict_fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 121356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 121357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121358 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121365 | GIR_RootConstrainSelectedInstOperands, |
| 121366 | // GIR_Coverage, 55525, |
| 121367 | GIR_EraseRootFromParent_Done, |
| 121368 | // Label 8432: @308068 |
| 121369 | GIM_Try, /*On fail goto*//*Label 8433*/ GIMT_Encode4(308145), // Rule ID 72050 // |
| 121370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 121371 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121372 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121373 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121374 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121375 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121376 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121377 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121378 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121379 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121380 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121381 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 121382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 121383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121384 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121391 | GIR_RootConstrainSelectedInstOperands, |
| 121392 | // GIR_Coverage, 72050, |
| 121393 | GIR_EraseRootFromParent_Done, |
| 121394 | // Label 8433: @308145 |
| 121395 | GIM_Try, /*On fail goto*//*Label 8434*/ GIMT_Encode4(308222), // Rule ID 72051 // |
| 121396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 121397 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121398 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121399 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121400 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121401 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121402 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121403 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121404 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121405 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121406 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121407 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFNMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 121408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_MF2_E16), |
| 121409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121410 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121417 | GIR_RootConstrainSelectedInstOperands, |
| 121418 | // GIR_Coverage, 72051, |
| 121419 | GIR_EraseRootFromParent_Done, |
| 121420 | // Label 8434: @308222 |
| 121421 | GIM_Try, /*On fail goto*//*Label 8435*/ GIMT_Encode4(308284), // Rule ID 55528 // |
| 121422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 121423 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121424 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121425 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121426 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121427 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121428 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121429 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121430 | // (strict_fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 121431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 121432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121433 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121435 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121440 | GIR_RootConstrainSelectedInstOperands, |
| 121441 | // GIR_Coverage, 55528, |
| 121442 | GIR_EraseRootFromParent_Done, |
| 121443 | // Label 8435: @308284 |
| 121444 | GIM_Try, /*On fail goto*//*Label 8436*/ GIMT_Encode4(308346), // Rule ID 55529 // |
| 121445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 121446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121449 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121450 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121451 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121452 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121453 | // (strict_fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 121454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 121455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121456 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121458 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121463 | GIR_RootConstrainSelectedInstOperands, |
| 121464 | // GIR_Coverage, 55529, |
| 121465 | GIR_EraseRootFromParent_Done, |
| 121466 | // Label 8436: @308346 |
| 121467 | GIM_Try, /*On fail goto*//*Label 8437*/ GIMT_Encode4(308408), // Rule ID 72054 // |
| 121468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 121469 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121470 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121471 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121472 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121473 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121475 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121476 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 121477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 121478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121479 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121481 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121486 | GIR_RootConstrainSelectedInstOperands, |
| 121487 | // GIR_Coverage, 72054, |
| 121488 | GIR_EraseRootFromParent_Done, |
| 121489 | // Label 8437: @308408 |
| 121490 | GIM_Try, /*On fail goto*//*Label 8438*/ GIMT_Encode4(308470), // Rule ID 72055 // |
| 121491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 121492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121493 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121494 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121495 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121496 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121497 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121498 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121499 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFNMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 121500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_MF2_E16), |
| 121501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121502 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121504 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121509 | GIR_RootConstrainSelectedInstOperands, |
| 121510 | // GIR_Coverage, 72055, |
| 121511 | GIR_EraseRootFromParent_Done, |
| 121512 | // Label 8438: @308470 |
| 121513 | GIM_Try, /*On fail goto*//*Label 8439*/ GIMT_Encode4(308532), // Rule ID 55520 // |
| 121514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 121515 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121516 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121517 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 121518 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121519 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121520 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121521 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121522 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 121523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E16), |
| 121524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121525 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121526 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 121528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121532 | GIR_RootConstrainSelectedInstOperands, |
| 121533 | // GIR_Coverage, 55520, |
| 121534 | GIR_EraseRootFromParent_Done, |
| 121535 | // Label 8439: @308532 |
| 121536 | GIM_Try, /*On fail goto*//*Label 8440*/ GIMT_Encode4(308594), // Rule ID 55521 // |
| 121537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 121538 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121540 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 121541 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121542 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 121543 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121544 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121545 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)) => (PseudoVFMSUB_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 121546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_MF2_E16), |
| 121547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121548 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121549 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 121551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121555 | GIR_RootConstrainSelectedInstOperands, |
| 121556 | // GIR_Coverage, 55521, |
| 121557 | GIR_EraseRootFromParent_Done, |
| 121558 | // Label 8440: @308594 |
| 121559 | GIM_Try, /*On fail goto*//*Label 8441*/ GIMT_Encode4(308639), // Rule ID 55516 // |
| 121560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 121561 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121563 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121564 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 121565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E16), |
| 121566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121567 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121568 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121569 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121574 | GIR_RootConstrainSelectedInstOperands, |
| 121575 | // GIR_Coverage, 55516, |
| 121576 | GIR_EraseRootFromParent_Done, |
| 121577 | // Label 8441: @308639 |
| 121578 | GIM_Try, /*On fail goto*//*Label 8442*/ GIMT_Encode4(308684), // Rule ID 55517 // |
| 121579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 121580 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121582 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121583 | // (strict_fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFMADD_VV_MF2_E16:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 121584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_MF2_E16), |
| 121585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121586 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121587 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121588 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 121592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121593 | GIR_RootConstrainSelectedInstOperands, |
| 121594 | // GIR_Coverage, 55517, |
| 121595 | GIR_EraseRootFromParent_Done, |
| 121596 | // Label 8442: @308684 |
| 121597 | GIM_Reject, |
| 121598 | // Label 8430: @308685 |
| 121599 | GIM_Reject, |
| 121600 | // Label 8298: @308686 |
| 121601 | GIM_Try, /*On fail goto*//*Label 8443*/ GIMT_Encode4(309475), |
| 121602 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121603 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, |
| 121604 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32, |
| 121605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121606 | GIM_Try, /*On fail goto*//*Label 8444*/ GIMT_Encode4(308781), // Rule ID 55716 // |
| 121607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 121608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121609 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121611 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121612 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121613 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121614 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121615 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121616 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121617 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121618 | // (strict_fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 121619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 121620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121621 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121628 | GIR_RootConstrainSelectedInstOperands, |
| 121629 | // GIR_Coverage, 55716, |
| 121630 | GIR_EraseRootFromParent_Done, |
| 121631 | // Label 8444: @308781 |
| 121632 | GIM_Try, /*On fail goto*//*Label 8445*/ GIMT_Encode4(308858), // Rule ID 55717 // |
| 121633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121634 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121635 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121636 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121637 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121638 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121639 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121640 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121641 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121642 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121643 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121644 | // (strict_fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 121646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121647 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121649 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121654 | GIR_RootConstrainSelectedInstOperands, |
| 121655 | // GIR_Coverage, 55717, |
| 121656 | GIR_EraseRootFromParent_Done, |
| 121657 | // Label 8445: @308858 |
| 121658 | GIM_Try, /*On fail goto*//*Label 8446*/ GIMT_Encode4(308935), // Rule ID 72218 // |
| 121659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 121660 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121661 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121662 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121663 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121664 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121665 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121666 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121667 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121668 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121669 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121670 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 121671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 121672 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121673 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121674 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121680 | GIR_RootConstrainSelectedInstOperands, |
| 121681 | // GIR_Coverage, 72218, |
| 121682 | GIR_EraseRootFromParent_Done, |
| 121683 | // Label 8446: @308935 |
| 121684 | GIM_Try, /*On fail goto*//*Label 8447*/ GIMT_Encode4(309012), // Rule ID 72219 // |
| 121685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121687 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121688 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121689 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121690 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121691 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121692 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121693 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121694 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121695 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121696 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFNMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E32), |
| 121698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121699 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121706 | GIR_RootConstrainSelectedInstOperands, |
| 121707 | // GIR_Coverage, 72219, |
| 121708 | GIR_EraseRootFromParent_Done, |
| 121709 | // Label 8447: @309012 |
| 121710 | GIM_Try, /*On fail goto*//*Label 8448*/ GIMT_Encode4(309074), // Rule ID 55720 // |
| 121711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 121712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121713 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121715 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121716 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121717 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121718 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121719 | // (strict_fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 121720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 121721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121722 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121723 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121724 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121729 | GIR_RootConstrainSelectedInstOperands, |
| 121730 | // GIR_Coverage, 55720, |
| 121731 | GIR_EraseRootFromParent_Done, |
| 121732 | // Label 8448: @309074 |
| 121733 | GIM_Try, /*On fail goto*//*Label 8449*/ GIMT_Encode4(309136), // Rule ID 55721 // |
| 121734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121735 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121736 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121737 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121738 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121739 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121740 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121741 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121742 | // (strict_fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 121744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121745 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121747 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121752 | GIR_RootConstrainSelectedInstOperands, |
| 121753 | // GIR_Coverage, 55721, |
| 121754 | GIR_EraseRootFromParent_Done, |
| 121755 | // Label 8449: @309136 |
| 121756 | GIM_Try, /*On fail goto*//*Label 8450*/ GIMT_Encode4(309198), // Rule ID 72222 // |
| 121757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 121758 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121759 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121760 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121761 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121762 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121763 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121764 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121765 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 121766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 121767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121768 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121769 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121770 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121775 | GIR_RootConstrainSelectedInstOperands, |
| 121776 | // GIR_Coverage, 72222, |
| 121777 | GIR_EraseRootFromParent_Done, |
| 121778 | // Label 8450: @309198 |
| 121779 | GIM_Try, /*On fail goto*//*Label 8451*/ GIMT_Encode4(309260), // Rule ID 72223 // |
| 121780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121782 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121783 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121784 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121785 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121786 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121787 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121788 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFNMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E32), |
| 121790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121791 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121793 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121798 | GIR_RootConstrainSelectedInstOperands, |
| 121799 | // GIR_Coverage, 72223, |
| 121800 | GIR_EraseRootFromParent_Done, |
| 121801 | // Label 8451: @309260 |
| 121802 | GIM_Try, /*On fail goto*//*Label 8452*/ GIMT_Encode4(309322), // Rule ID 55712 // |
| 121803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 121804 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121806 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 121807 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121808 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121809 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121810 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121811 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 121812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E32), |
| 121813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121814 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121815 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 121817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121821 | GIR_RootConstrainSelectedInstOperands, |
| 121822 | // GIR_Coverage, 55712, |
| 121823 | GIR_EraseRootFromParent_Done, |
| 121824 | // Label 8452: @309322 |
| 121825 | GIM_Try, /*On fail goto*//*Label 8453*/ GIMT_Encode4(309384), // Rule ID 55713 // |
| 121826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121828 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121829 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 121830 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121831 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 121832 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121833 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 121834 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)) => (PseudoVFMSUB_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E32), |
| 121836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121837 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121838 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 121840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121844 | GIR_RootConstrainSelectedInstOperands, |
| 121845 | // GIR_Coverage, 55713, |
| 121846 | GIR_EraseRootFromParent_Done, |
| 121847 | // Label 8453: @309384 |
| 121848 | GIM_Try, /*On fail goto*//*Label 8454*/ GIMT_Encode4(309429), // Rule ID 55708 // |
| 121849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 121850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121851 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121852 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121853 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 121854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E32), |
| 121855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121856 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121857 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121858 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121863 | GIR_RootConstrainSelectedInstOperands, |
| 121864 | // GIR_Coverage, 55708, |
| 121865 | GIR_EraseRootFromParent_Done, |
| 121866 | // Label 8454: @309429 |
| 121867 | GIM_Try, /*On fail goto*//*Label 8455*/ GIMT_Encode4(309474), // Rule ID 55709 // |
| 121868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 121869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121870 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121871 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 121872 | // (strict_fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFMADD_VV_M1_E32:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 121873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E32), |
| 121874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121875 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121876 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 121877 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 121878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 121881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121882 | GIR_RootConstrainSelectedInstOperands, |
| 121883 | // GIR_Coverage, 55709, |
| 121884 | GIR_EraseRootFromParent_Done, |
| 121885 | // Label 8455: @309474 |
| 121886 | GIM_Reject, |
| 121887 | // Label 8443: @309475 |
| 121888 | GIM_Reject, |
| 121889 | // Label 8299: @309476 |
| 121890 | GIM_Try, /*On fail goto*//*Label 8456*/ GIMT_Encode4(310265), |
| 121891 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, |
| 121893 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64, |
| 121894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121895 | GIM_Try, /*On fail goto*//*Label 8457*/ GIMT_Encode4(309571), // Rule ID 56228 // |
| 121896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121897 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121898 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121899 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121900 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121901 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121902 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121903 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121904 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121905 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121906 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121907 | // (strict_fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 121909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121910 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121917 | GIR_RootConstrainSelectedInstOperands, |
| 121918 | // GIR_Coverage, 56228, |
| 121919 | GIR_EraseRootFromParent_Done, |
| 121920 | // Label 8457: @309571 |
| 121921 | GIM_Try, /*On fail goto*//*Label 8458*/ GIMT_Encode4(309648), // Rule ID 56229 // |
| 121922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121923 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121924 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121925 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121926 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121928 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121929 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121930 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121931 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121932 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121933 | // (strict_fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 121935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121936 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 121937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121943 | GIR_RootConstrainSelectedInstOperands, |
| 121944 | // GIR_Coverage, 56229, |
| 121945 | GIR_EraseRootFromParent_Done, |
| 121946 | // Label 8458: @309648 |
| 121947 | GIM_Try, /*On fail goto*//*Label 8459*/ GIMT_Encode4(309725), // Rule ID 72666 // |
| 121948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 121949 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121951 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121952 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121953 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121954 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121955 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121956 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121957 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121958 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121959 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 121960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 121961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121962 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121969 | GIR_RootConstrainSelectedInstOperands, |
| 121970 | // GIR_Coverage, 72666, |
| 121971 | GIR_EraseRootFromParent_Done, |
| 121972 | // Label 8459: @309725 |
| 121973 | GIM_Try, /*On fail goto*//*Label 8460*/ GIMT_Encode4(309802), // Rule ID 72667 // |
| 121974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 121975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 121977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121979 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121980 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 121981 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 121982 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 121983 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 121984 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 121985 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFNMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 121986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E64), |
| 121987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 121988 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 121989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 121990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 121991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 121992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 121993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 121994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 121995 | GIR_RootConstrainSelectedInstOperands, |
| 121996 | // GIR_Coverage, 72667, |
| 121997 | GIR_EraseRootFromParent_Done, |
| 121998 | // Label 8460: @309802 |
| 121999 | GIM_Try, /*On fail goto*//*Label 8461*/ GIMT_Encode4(309864), // Rule ID 56232 // |
| 122000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122001 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122002 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122003 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 122004 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122006 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122007 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122008 | // (strict_fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 122010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122011 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122013 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122018 | GIR_RootConstrainSelectedInstOperands, |
| 122019 | // GIR_Coverage, 56232, |
| 122020 | GIR_EraseRootFromParent_Done, |
| 122021 | // Label 8461: @309864 |
| 122022 | GIM_Try, /*On fail goto*//*Label 8462*/ GIMT_Encode4(309926), // Rule ID 56233 // |
| 122023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122025 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122026 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 122027 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122028 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122029 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122030 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122031 | // (strict_fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 122033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122034 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122036 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122041 | GIR_RootConstrainSelectedInstOperands, |
| 122042 | // GIR_Coverage, 56233, |
| 122043 | GIR_EraseRootFromParent_Done, |
| 122044 | // Label 8462: @309926 |
| 122045 | GIM_Try, /*On fail goto*//*Label 8463*/ GIMT_Encode4(309988), // Rule ID 72670 // |
| 122046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122047 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122048 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122049 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122050 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 122051 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122052 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122053 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122054 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 122056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122057 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122059 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122064 | GIR_RootConstrainSelectedInstOperands, |
| 122065 | // GIR_Coverage, 72670, |
| 122066 | GIR_EraseRootFromParent_Done, |
| 122067 | // Label 8463: @309988 |
| 122068 | GIM_Try, /*On fail goto*//*Label 8464*/ GIMT_Encode4(310050), // Rule ID 72671 // |
| 122069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122072 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 122074 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122075 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122076 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122077 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFNMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E64), |
| 122079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122080 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122082 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122087 | GIR_RootConstrainSelectedInstOperands, |
| 122088 | // GIR_Coverage, 72671, |
| 122089 | GIR_EraseRootFromParent_Done, |
| 122090 | // Label 8464: @310050 |
| 122091 | GIM_Try, /*On fail goto*//*Label 8465*/ GIMT_Encode4(310112), // Rule ID 56224 // |
| 122092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122093 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122094 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122096 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 122098 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122099 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122100 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E64), |
| 122102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122103 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122104 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122110 | GIR_RootConstrainSelectedInstOperands, |
| 122111 | // GIR_Coverage, 56224, |
| 122112 | GIR_EraseRootFromParent_Done, |
| 122113 | // Label 8465: @310112 |
| 122114 | GIM_Try, /*On fail goto*//*Label 8466*/ GIMT_Encode4(310174), // Rule ID 56225 // |
| 122115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122117 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122118 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122119 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122120 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 122121 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122122 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122123 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)) => (PseudoVFMSUB_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E64), |
| 122125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122126 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122127 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122133 | GIR_RootConstrainSelectedInstOperands, |
| 122134 | // GIR_Coverage, 56225, |
| 122135 | GIR_EraseRootFromParent_Done, |
| 122136 | // Label 8466: @310174 |
| 122137 | GIM_Try, /*On fail goto*//*Label 8467*/ GIMT_Encode4(310219), // Rule ID 56220 // |
| 122138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122140 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122141 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122142 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E64), |
| 122144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122145 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122146 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122147 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122152 | GIR_RootConstrainSelectedInstOperands, |
| 122153 | // GIR_Coverage, 56220, |
| 122154 | GIR_EraseRootFromParent_Done, |
| 122155 | // Label 8467: @310219 |
| 122156 | GIM_Try, /*On fail goto*//*Label 8468*/ GIMT_Encode4(310264), // Rule ID 56221 // |
| 122157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122160 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122161 | // (strict_fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFMADD_VV_M2_E64:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E64), |
| 122163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122164 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122165 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122166 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122171 | GIR_RootConstrainSelectedInstOperands, |
| 122172 | // GIR_Coverage, 56221, |
| 122173 | GIR_EraseRootFromParent_Done, |
| 122174 | // Label 8468: @310264 |
| 122175 | GIM_Reject, |
| 122176 | // Label 8456: @310265 |
| 122177 | GIM_Reject, |
| 122178 | // Label 8300: @310266 |
| 122179 | GIM_Try, /*On fail goto*//*Label 8469*/ GIMT_Encode4(311055), |
| 122180 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122181 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, |
| 122182 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16, |
| 122183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122184 | GIM_Try, /*On fail goto*//*Label 8470*/ GIMT_Encode4(310361), // Rule ID 55652 // |
| 122185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 122186 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122187 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122188 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122189 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122190 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122191 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122192 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122193 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122194 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122195 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122196 | // (strict_fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 122197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 122198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122199 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122206 | GIR_RootConstrainSelectedInstOperands, |
| 122207 | // GIR_Coverage, 55652, |
| 122208 | GIR_EraseRootFromParent_Done, |
| 122209 | // Label 8470: @310361 |
| 122210 | GIM_Try, /*On fail goto*//*Label 8471*/ GIMT_Encode4(310438), // Rule ID 55653 // |
| 122211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 122212 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122213 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122214 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122215 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122216 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122217 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122218 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122219 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122220 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122221 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122222 | // (strict_fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 122223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 122224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122225 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122226 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122227 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122232 | GIR_RootConstrainSelectedInstOperands, |
| 122233 | // GIR_Coverage, 55653, |
| 122234 | GIR_EraseRootFromParent_Done, |
| 122235 | // Label 8471: @310438 |
| 122236 | GIM_Try, /*On fail goto*//*Label 8472*/ GIMT_Encode4(310515), // Rule ID 72162 // |
| 122237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 122238 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122239 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122240 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122241 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122242 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122243 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122244 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122245 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122246 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122247 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122248 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 122249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 122250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122251 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122258 | GIR_RootConstrainSelectedInstOperands, |
| 122259 | // GIR_Coverage, 72162, |
| 122260 | GIR_EraseRootFromParent_Done, |
| 122261 | // Label 8472: @310515 |
| 122262 | GIM_Try, /*On fail goto*//*Label 8473*/ GIMT_Encode4(310592), // Rule ID 72163 // |
| 122263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 122264 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122265 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122266 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122267 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122268 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122269 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122270 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122271 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122272 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122273 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122274 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFNMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 122275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M1_E16), |
| 122276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122277 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122284 | GIR_RootConstrainSelectedInstOperands, |
| 122285 | // GIR_Coverage, 72163, |
| 122286 | GIR_EraseRootFromParent_Done, |
| 122287 | // Label 8473: @310592 |
| 122288 | GIM_Try, /*On fail goto*//*Label 8474*/ GIMT_Encode4(310654), // Rule ID 55656 // |
| 122289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 122290 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122291 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122292 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122293 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122294 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122295 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122296 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122297 | // (strict_fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 122298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 122299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122300 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122302 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122307 | GIR_RootConstrainSelectedInstOperands, |
| 122308 | // GIR_Coverage, 55656, |
| 122309 | GIR_EraseRootFromParent_Done, |
| 122310 | // Label 8474: @310654 |
| 122311 | GIM_Try, /*On fail goto*//*Label 8475*/ GIMT_Encode4(310716), // Rule ID 55657 // |
| 122312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 122313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122316 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122318 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122319 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122320 | // (strict_fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 122321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 122322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122323 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122325 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122330 | GIR_RootConstrainSelectedInstOperands, |
| 122331 | // GIR_Coverage, 55657, |
| 122332 | GIR_EraseRootFromParent_Done, |
| 122333 | // Label 8475: @310716 |
| 122334 | GIM_Try, /*On fail goto*//*Label 8476*/ GIMT_Encode4(310778), // Rule ID 72166 // |
| 122335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 122336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122337 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122338 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122339 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122340 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122341 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122342 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122343 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 122344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 122345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122346 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122348 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122353 | GIR_RootConstrainSelectedInstOperands, |
| 122354 | // GIR_Coverage, 72166, |
| 122355 | GIR_EraseRootFromParent_Done, |
| 122356 | // Label 8476: @310778 |
| 122357 | GIM_Try, /*On fail goto*//*Label 8477*/ GIMT_Encode4(310840), // Rule ID 72167 // |
| 122358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 122359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122360 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122361 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122362 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122363 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122364 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122365 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122366 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFNMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 122367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M1_E16), |
| 122368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122369 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122371 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122376 | GIR_RootConstrainSelectedInstOperands, |
| 122377 | // GIR_Coverage, 72167, |
| 122378 | GIR_EraseRootFromParent_Done, |
| 122379 | // Label 8477: @310840 |
| 122380 | GIM_Try, /*On fail goto*//*Label 8478*/ GIMT_Encode4(310902), // Rule ID 55648 // |
| 122381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 122382 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122383 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122384 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122385 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122386 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122387 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122388 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122389 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 122390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E16), |
| 122391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122392 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122393 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122399 | GIR_RootConstrainSelectedInstOperands, |
| 122400 | // GIR_Coverage, 55648, |
| 122401 | GIR_EraseRootFromParent_Done, |
| 122402 | // Label 8478: @310902 |
| 122403 | GIM_Try, /*On fail goto*//*Label 8479*/ GIMT_Encode4(310964), // Rule ID 55649 // |
| 122404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 122405 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122406 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122408 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 122410 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122411 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122412 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)) => (PseudoVFMSUB_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 122413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M1_E16), |
| 122414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122415 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122416 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122422 | GIR_RootConstrainSelectedInstOperands, |
| 122423 | // GIR_Coverage, 55649, |
| 122424 | GIR_EraseRootFromParent_Done, |
| 122425 | // Label 8479: @310964 |
| 122426 | GIM_Try, /*On fail goto*//*Label 8480*/ GIMT_Encode4(311009), // Rule ID 55644 // |
| 122427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 122428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122430 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122431 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 122432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E16), |
| 122433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122434 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122435 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122436 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122441 | GIR_RootConstrainSelectedInstOperands, |
| 122442 | // GIR_Coverage, 55644, |
| 122443 | GIR_EraseRootFromParent_Done, |
| 122444 | // Label 8480: @311009 |
| 122445 | GIM_Try, /*On fail goto*//*Label 8481*/ GIMT_Encode4(311054), // Rule ID 55645 // |
| 122446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 122447 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122448 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122449 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 122450 | // (strict_fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFMADD_VV_M1_E16:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 122451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M1_E16), |
| 122452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122453 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122454 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122455 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 122459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122460 | GIR_RootConstrainSelectedInstOperands, |
| 122461 | // GIR_Coverage, 55645, |
| 122462 | GIR_EraseRootFromParent_Done, |
| 122463 | // Label 8481: @311054 |
| 122464 | GIM_Reject, |
| 122465 | // Label 8469: @311055 |
| 122466 | GIM_Reject, |
| 122467 | // Label 8301: @311056 |
| 122468 | GIM_Try, /*On fail goto*//*Label 8482*/ GIMT_Encode4(311845), |
| 122469 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, |
| 122471 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32, |
| 122472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122473 | GIM_Try, /*On fail goto*//*Label 8483*/ GIMT_Encode4(311151), // Rule ID 56036 // |
| 122474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 122475 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122476 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122477 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122478 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122479 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122480 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122481 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122482 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122483 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122484 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122485 | // (strict_fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 122486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 122487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122488 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122489 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122490 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122495 | GIR_RootConstrainSelectedInstOperands, |
| 122496 | // GIR_Coverage, 56036, |
| 122497 | GIR_EraseRootFromParent_Done, |
| 122498 | // Label 8483: @311151 |
| 122499 | GIM_Try, /*On fail goto*//*Label 8484*/ GIMT_Encode4(311228), // Rule ID 56037 // |
| 122500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 122501 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122502 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122503 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122504 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122505 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122506 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122507 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122508 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122509 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122510 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122511 | // (strict_fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 122512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 122513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122514 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122516 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122521 | GIR_RootConstrainSelectedInstOperands, |
| 122522 | // GIR_Coverage, 56037, |
| 122523 | GIR_EraseRootFromParent_Done, |
| 122524 | // Label 8484: @311228 |
| 122525 | GIM_Try, /*On fail goto*//*Label 8485*/ GIMT_Encode4(311305), // Rule ID 72498 // |
| 122526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 122527 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122528 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122529 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122530 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122531 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122532 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122533 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122534 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122535 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122536 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122537 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 122538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 122539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122540 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122547 | GIR_RootConstrainSelectedInstOperands, |
| 122548 | // GIR_Coverage, 72498, |
| 122549 | GIR_EraseRootFromParent_Done, |
| 122550 | // Label 8485: @311305 |
| 122551 | GIM_Try, /*On fail goto*//*Label 8486*/ GIMT_Encode4(311382), // Rule ID 72499 // |
| 122552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 122553 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122554 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122555 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122556 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122557 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122558 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122559 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122560 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122561 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122562 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122563 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFNMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 122564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E32), |
| 122565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122566 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122573 | GIR_RootConstrainSelectedInstOperands, |
| 122574 | // GIR_Coverage, 72499, |
| 122575 | GIR_EraseRootFromParent_Done, |
| 122576 | // Label 8486: @311382 |
| 122577 | GIM_Try, /*On fail goto*//*Label 8487*/ GIMT_Encode4(311444), // Rule ID 56040 // |
| 122578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 122579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122580 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122581 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122582 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122583 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122584 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122585 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122586 | // (strict_fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 122587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 122588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122589 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122590 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122591 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122596 | GIR_RootConstrainSelectedInstOperands, |
| 122597 | // GIR_Coverage, 56040, |
| 122598 | GIR_EraseRootFromParent_Done, |
| 122599 | // Label 8487: @311444 |
| 122600 | GIM_Try, /*On fail goto*//*Label 8488*/ GIMT_Encode4(311506), // Rule ID 56041 // |
| 122601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 122602 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122603 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122604 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122607 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122608 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122609 | // (strict_fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 122610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 122611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122612 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122614 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122619 | GIR_RootConstrainSelectedInstOperands, |
| 122620 | // GIR_Coverage, 56041, |
| 122621 | GIR_EraseRootFromParent_Done, |
| 122622 | // Label 8488: @311506 |
| 122623 | GIM_Try, /*On fail goto*//*Label 8489*/ GIMT_Encode4(311568), // Rule ID 72502 // |
| 122624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 122625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122626 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122627 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122628 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122629 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122630 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122631 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122632 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 122633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 122634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122635 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122637 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122642 | GIR_RootConstrainSelectedInstOperands, |
| 122643 | // GIR_Coverage, 72502, |
| 122644 | GIR_EraseRootFromParent_Done, |
| 122645 | // Label 8489: @311568 |
| 122646 | GIM_Try, /*On fail goto*//*Label 8490*/ GIMT_Encode4(311630), // Rule ID 72503 // |
| 122647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 122648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122649 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122650 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122651 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122652 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122653 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122654 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122655 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFNMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 122656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E32), |
| 122657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122658 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122660 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122665 | GIR_RootConstrainSelectedInstOperands, |
| 122666 | // GIR_Coverage, 72503, |
| 122667 | GIR_EraseRootFromParent_Done, |
| 122668 | // Label 8490: @311630 |
| 122669 | GIM_Try, /*On fail goto*//*Label 8491*/ GIMT_Encode4(311692), // Rule ID 56032 // |
| 122670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 122671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122672 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122674 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122677 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122678 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 122679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E32), |
| 122680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122681 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122682 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122688 | GIR_RootConstrainSelectedInstOperands, |
| 122689 | // GIR_Coverage, 56032, |
| 122690 | GIR_EraseRootFromParent_Done, |
| 122691 | // Label 8491: @311692 |
| 122692 | GIM_Try, /*On fail goto*//*Label 8492*/ GIMT_Encode4(311754), // Rule ID 56033 // |
| 122693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 122694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122696 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122697 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122698 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 122699 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122700 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122701 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)) => (PseudoVFMSUB_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 122702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E32), |
| 122703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122704 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122705 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122711 | GIR_RootConstrainSelectedInstOperands, |
| 122712 | // GIR_Coverage, 56033, |
| 122713 | GIR_EraseRootFromParent_Done, |
| 122714 | // Label 8492: @311754 |
| 122715 | GIM_Try, /*On fail goto*//*Label 8493*/ GIMT_Encode4(311799), // Rule ID 56028 // |
| 122716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 122717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122718 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122719 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122720 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 122721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E32), |
| 122722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122723 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122724 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122725 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122730 | GIR_RootConstrainSelectedInstOperands, |
| 122731 | // GIR_Coverage, 56028, |
| 122732 | GIR_EraseRootFromParent_Done, |
| 122733 | // Label 8493: @311799 |
| 122734 | GIM_Try, /*On fail goto*//*Label 8494*/ GIMT_Encode4(311844), // Rule ID 56029 // |
| 122735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 122736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122738 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 122739 | // (strict_fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFMADD_VV_M2_E32:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 122740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E32), |
| 122741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122742 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122743 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122744 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 122748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122749 | GIR_RootConstrainSelectedInstOperands, |
| 122750 | // GIR_Coverage, 56029, |
| 122751 | GIR_EraseRootFromParent_Done, |
| 122752 | // Label 8494: @311844 |
| 122753 | GIM_Reject, |
| 122754 | // Label 8482: @311845 |
| 122755 | GIM_Reject, |
| 122756 | // Label 8302: @311846 |
| 122757 | GIM_Try, /*On fail goto*//*Label 8495*/ GIMT_Encode4(312635), |
| 122758 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122759 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, |
| 122760 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s64, |
| 122761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122762 | GIM_Try, /*On fail goto*//*Label 8496*/ GIMT_Encode4(311941), // Rule ID 56292 // |
| 122763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122764 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122765 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122766 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122767 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122768 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122769 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122770 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122771 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122772 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122773 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122774 | // (strict_fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 122776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122777 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122784 | GIR_RootConstrainSelectedInstOperands, |
| 122785 | // GIR_Coverage, 56292, |
| 122786 | GIR_EraseRootFromParent_Done, |
| 122787 | // Label 8496: @311941 |
| 122788 | GIM_Try, /*On fail goto*//*Label 8497*/ GIMT_Encode4(312018), // Rule ID 56293 // |
| 122789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122790 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122791 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122792 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122793 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122794 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122795 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122796 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122797 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122798 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122799 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122800 | // (strict_fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 122802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122803 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122810 | GIR_RootConstrainSelectedInstOperands, |
| 122811 | // GIR_Coverage, 56293, |
| 122812 | GIR_EraseRootFromParent_Done, |
| 122813 | // Label 8497: @312018 |
| 122814 | GIM_Try, /*On fail goto*//*Label 8498*/ GIMT_Encode4(312095), // Rule ID 72722 // |
| 122815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122816 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122817 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122818 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122819 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122820 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122821 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122822 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122823 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122824 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122825 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122826 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 122828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122829 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122836 | GIR_RootConstrainSelectedInstOperands, |
| 122837 | // GIR_Coverage, 72722, |
| 122838 | GIR_EraseRootFromParent_Done, |
| 122839 | // Label 8498: @312095 |
| 122840 | GIM_Try, /*On fail goto*//*Label 8499*/ GIMT_Encode4(312172), // Rule ID 72723 // |
| 122841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122842 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122843 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122844 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122845 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122846 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122847 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 122848 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122849 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122850 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122851 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 122852 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFNMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E64), |
| 122854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122855 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 122858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122862 | GIR_RootConstrainSelectedInstOperands, |
| 122863 | // GIR_Coverage, 72723, |
| 122864 | GIR_EraseRootFromParent_Done, |
| 122865 | // Label 8499: @312172 |
| 122866 | GIM_Try, /*On fail goto*//*Label 8500*/ GIMT_Encode4(312234), // Rule ID 56296 // |
| 122867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122868 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122869 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122870 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122871 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122872 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122873 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122874 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122875 | // (strict_fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 122877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122878 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122880 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122885 | GIR_RootConstrainSelectedInstOperands, |
| 122886 | // GIR_Coverage, 56296, |
| 122887 | GIR_EraseRootFromParent_Done, |
| 122888 | // Label 8500: @312234 |
| 122889 | GIM_Try, /*On fail goto*//*Label 8501*/ GIMT_Encode4(312296), // Rule ID 56297 // |
| 122890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122891 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122892 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122893 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122894 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122895 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122896 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122897 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122898 | // (strict_fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 122900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122901 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122903 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122908 | GIR_RootConstrainSelectedInstOperands, |
| 122909 | // GIR_Coverage, 56297, |
| 122910 | GIR_EraseRootFromParent_Done, |
| 122911 | // Label 8501: @312296 |
| 122912 | GIM_Try, /*On fail goto*//*Label 8502*/ GIMT_Encode4(312358), // Rule ID 72726 // |
| 122913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122914 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122915 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122916 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122917 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122918 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122919 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122920 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122921 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 122923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122924 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122926 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122931 | GIR_RootConstrainSelectedInstOperands, |
| 122932 | // GIR_Coverage, 72726, |
| 122933 | GIR_EraseRootFromParent_Done, |
| 122934 | // Label 8502: @312358 |
| 122935 | GIM_Try, /*On fail goto*//*Label 8503*/ GIMT_Encode4(312420), // Rule ID 72727 // |
| 122936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122937 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122938 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 122939 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122940 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122941 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122942 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122943 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122944 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFNMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E64), |
| 122946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122947 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 122948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 122949 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 122950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122954 | GIR_RootConstrainSelectedInstOperands, |
| 122955 | // GIR_Coverage, 72727, |
| 122956 | GIR_EraseRootFromParent_Done, |
| 122957 | // Label 8503: @312420 |
| 122958 | GIM_Try, /*On fail goto*//*Label 8504*/ GIMT_Encode4(312482), // Rule ID 56288 // |
| 122959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 122960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122961 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122962 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122963 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122964 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122965 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122966 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122967 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 122968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E64), |
| 122969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122970 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122971 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 122977 | GIR_RootConstrainSelectedInstOperands, |
| 122978 | // GIR_Coverage, 56288, |
| 122979 | GIR_EraseRootFromParent_Done, |
| 122980 | // Label 8504: @312482 |
| 122981 | GIM_Try, /*On fail goto*//*Label 8505*/ GIMT_Encode4(312544), // Rule ID 56289 // |
| 122982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 122983 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122985 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 122986 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 122987 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 122988 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 122989 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 122990 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)) => (PseudoVFMSUB_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 122991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E64), |
| 122992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 122993 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 122994 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 122995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 122996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 122997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 122998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 122999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123000 | GIR_RootConstrainSelectedInstOperands, |
| 123001 | // GIR_Coverage, 56289, |
| 123002 | GIR_EraseRootFromParent_Done, |
| 123003 | // Label 8505: @312544 |
| 123004 | GIM_Try, /*On fail goto*//*Label 8506*/ GIMT_Encode4(312589), // Rule ID 56284 // |
| 123005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123008 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123009 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E64), |
| 123011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123012 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123013 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123014 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123019 | GIR_RootConstrainSelectedInstOperands, |
| 123020 | // GIR_Coverage, 56284, |
| 123021 | GIR_EraseRootFromParent_Done, |
| 123022 | // Label 8506: @312589 |
| 123023 | GIM_Try, /*On fail goto*//*Label 8507*/ GIMT_Encode4(312634), // Rule ID 56285 // |
| 123024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123025 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123026 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123027 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123028 | // (strict_fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFMADD_VV_M4_E64:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E64), |
| 123030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123031 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123032 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123033 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123038 | GIR_RootConstrainSelectedInstOperands, |
| 123039 | // GIR_Coverage, 56285, |
| 123040 | GIR_EraseRootFromParent_Done, |
| 123041 | // Label 8507: @312634 |
| 123042 | GIM_Reject, |
| 123043 | // Label 8495: @312635 |
| 123044 | GIM_Reject, |
| 123045 | // Label 8303: @312636 |
| 123046 | GIM_Try, /*On fail goto*//*Label 8508*/ GIMT_Encode4(313425), |
| 123047 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123048 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, |
| 123049 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16, |
| 123050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123051 | GIM_Try, /*On fail goto*//*Label 8509*/ GIMT_Encode4(312731), // Rule ID 55844 // |
| 123052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123053 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123054 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123055 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123056 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123057 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123058 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123059 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123060 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123061 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123062 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123063 | // (strict_fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 123065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123066 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123073 | GIR_RootConstrainSelectedInstOperands, |
| 123074 | // GIR_Coverage, 55844, |
| 123075 | GIR_EraseRootFromParent_Done, |
| 123076 | // Label 8509: @312731 |
| 123077 | GIM_Try, /*On fail goto*//*Label 8510*/ GIMT_Encode4(312808), // Rule ID 55845 // |
| 123078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123079 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123080 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123081 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123082 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123083 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123084 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123085 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123086 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123087 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123088 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123089 | // (strict_fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 123091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123092 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123099 | GIR_RootConstrainSelectedInstOperands, |
| 123100 | // GIR_Coverage, 55845, |
| 123101 | GIR_EraseRootFromParent_Done, |
| 123102 | // Label 8510: @312808 |
| 123103 | GIM_Try, /*On fail goto*//*Label 8511*/ GIMT_Encode4(312885), // Rule ID 72330 // |
| 123104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123105 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123106 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123107 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123108 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123109 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123110 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123111 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123112 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123113 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123114 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123115 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 123117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123118 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123119 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123125 | GIR_RootConstrainSelectedInstOperands, |
| 123126 | // GIR_Coverage, 72330, |
| 123127 | GIR_EraseRootFromParent_Done, |
| 123128 | // Label 8511: @312885 |
| 123129 | GIM_Try, /*On fail goto*//*Label 8512*/ GIMT_Encode4(312962), // Rule ID 72331 // |
| 123130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123131 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123132 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123133 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123134 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123135 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123136 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123137 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123138 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123139 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123140 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123141 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFNMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M2_E16), |
| 123143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123144 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123151 | GIR_RootConstrainSelectedInstOperands, |
| 123152 | // GIR_Coverage, 72331, |
| 123153 | GIR_EraseRootFromParent_Done, |
| 123154 | // Label 8512: @312962 |
| 123155 | GIM_Try, /*On fail goto*//*Label 8513*/ GIMT_Encode4(313024), // Rule ID 55848 // |
| 123156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123157 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123158 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123159 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123160 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123162 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123163 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123164 | // (strict_fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 123166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123167 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123168 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123169 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123174 | GIR_RootConstrainSelectedInstOperands, |
| 123175 | // GIR_Coverage, 55848, |
| 123176 | GIR_EraseRootFromParent_Done, |
| 123177 | // Label 8513: @313024 |
| 123178 | GIM_Try, /*On fail goto*//*Label 8514*/ GIMT_Encode4(313086), // Rule ID 55849 // |
| 123179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123182 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123183 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123184 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123185 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123186 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123187 | // (strict_fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 123189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123190 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123192 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123197 | GIR_RootConstrainSelectedInstOperands, |
| 123198 | // GIR_Coverage, 55849, |
| 123199 | GIR_EraseRootFromParent_Done, |
| 123200 | // Label 8514: @313086 |
| 123201 | GIM_Try, /*On fail goto*//*Label 8515*/ GIMT_Encode4(313148), // Rule ID 72334 // |
| 123202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123203 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123204 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123205 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123206 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123207 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123208 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123209 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123210 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 123212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123213 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123215 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123220 | GIR_RootConstrainSelectedInstOperands, |
| 123221 | // GIR_Coverage, 72334, |
| 123222 | GIR_EraseRootFromParent_Done, |
| 123223 | // Label 8515: @313148 |
| 123224 | GIM_Try, /*On fail goto*//*Label 8516*/ GIMT_Encode4(313210), // Rule ID 72335 // |
| 123225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123226 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123228 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123229 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123230 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123231 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123232 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123233 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFNMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M2_E16), |
| 123235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123236 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123238 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123243 | GIR_RootConstrainSelectedInstOperands, |
| 123244 | // GIR_Coverage, 72335, |
| 123245 | GIR_EraseRootFromParent_Done, |
| 123246 | // Label 8516: @313210 |
| 123247 | GIM_Try, /*On fail goto*//*Label 8517*/ GIMT_Encode4(313272), // Rule ID 55840 // |
| 123248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123249 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123250 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 123252 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123253 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123254 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123255 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123256 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E16), |
| 123258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123259 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123260 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 123262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123266 | GIR_RootConstrainSelectedInstOperands, |
| 123267 | // GIR_Coverage, 55840, |
| 123268 | GIR_EraseRootFromParent_Done, |
| 123269 | // Label 8517: @313272 |
| 123270 | GIM_Try, /*On fail goto*//*Label 8518*/ GIMT_Encode4(313334), // Rule ID 55841 // |
| 123271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123274 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 123275 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123276 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 123277 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123278 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123279 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)) => (PseudoVFMSUB_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M2_E16), |
| 123281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123282 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123283 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 123285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123289 | GIR_RootConstrainSelectedInstOperands, |
| 123290 | // GIR_Coverage, 55841, |
| 123291 | GIR_EraseRootFromParent_Done, |
| 123292 | // Label 8518: @313334 |
| 123293 | GIM_Try, /*On fail goto*//*Label 8519*/ GIMT_Encode4(313379), // Rule ID 55836 // |
| 123294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123295 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123296 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123297 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123298 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E16), |
| 123300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123301 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123302 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123303 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123308 | GIR_RootConstrainSelectedInstOperands, |
| 123309 | // GIR_Coverage, 55836, |
| 123310 | GIR_EraseRootFromParent_Done, |
| 123311 | // Label 8519: @313379 |
| 123312 | GIM_Try, /*On fail goto*//*Label 8520*/ GIMT_Encode4(313424), // Rule ID 55837 // |
| 123313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123315 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123316 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 123317 | // (strict_fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFMADD_VV_M2_E16:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M2_E16), |
| 123319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123320 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123321 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123322 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123327 | GIR_RootConstrainSelectedInstOperands, |
| 123328 | // GIR_Coverage, 55837, |
| 123329 | GIR_EraseRootFromParent_Done, |
| 123330 | // Label 8520: @313424 |
| 123331 | GIM_Reject, |
| 123332 | // Label 8508: @313425 |
| 123333 | GIM_Reject, |
| 123334 | // Label 8304: @313426 |
| 123335 | GIM_Try, /*On fail goto*//*Label 8521*/ GIMT_Encode4(314215), |
| 123336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123337 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, |
| 123338 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s32, |
| 123339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123340 | GIM_Try, /*On fail goto*//*Label 8522*/ GIMT_Encode4(313521), // Rule ID 56100 // |
| 123341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 123342 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123343 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123344 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123345 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123346 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123347 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123348 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123349 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123350 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123351 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123352 | // (strict_fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 123353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 123354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123355 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123362 | GIR_RootConstrainSelectedInstOperands, |
| 123363 | // GIR_Coverage, 56100, |
| 123364 | GIR_EraseRootFromParent_Done, |
| 123365 | // Label 8522: @313521 |
| 123366 | GIM_Try, /*On fail goto*//*Label 8523*/ GIMT_Encode4(313598), // Rule ID 56101 // |
| 123367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 123368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123369 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123370 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123371 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123372 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123373 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123374 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123375 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123376 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123377 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123378 | // (strict_fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 123379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 123380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123381 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123382 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123388 | GIR_RootConstrainSelectedInstOperands, |
| 123389 | // GIR_Coverage, 56101, |
| 123390 | GIR_EraseRootFromParent_Done, |
| 123391 | // Label 8523: @313598 |
| 123392 | GIM_Try, /*On fail goto*//*Label 8524*/ GIMT_Encode4(313675), // Rule ID 72554 // |
| 123393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 123394 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123395 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123396 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123397 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123398 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123399 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123400 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123401 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123402 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123403 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123404 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 123405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 123406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123407 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123409 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123414 | GIR_RootConstrainSelectedInstOperands, |
| 123415 | // GIR_Coverage, 72554, |
| 123416 | GIR_EraseRootFromParent_Done, |
| 123417 | // Label 8524: @313675 |
| 123418 | GIM_Try, /*On fail goto*//*Label 8525*/ GIMT_Encode4(313752), // Rule ID 72555 // |
| 123419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 123420 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123421 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123422 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123423 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123424 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123425 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123426 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123427 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123428 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123429 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123430 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFNMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 123431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E32), |
| 123432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123433 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123440 | GIR_RootConstrainSelectedInstOperands, |
| 123441 | // GIR_Coverage, 72555, |
| 123442 | GIR_EraseRootFromParent_Done, |
| 123443 | // Label 8525: @313752 |
| 123444 | GIM_Try, /*On fail goto*//*Label 8526*/ GIMT_Encode4(313814), // Rule ID 56104 // |
| 123445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 123446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123449 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123450 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123451 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123452 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123453 | // (strict_fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 123454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 123455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123456 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123458 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123463 | GIR_RootConstrainSelectedInstOperands, |
| 123464 | // GIR_Coverage, 56104, |
| 123465 | GIR_EraseRootFromParent_Done, |
| 123466 | // Label 8526: @313814 |
| 123467 | GIM_Try, /*On fail goto*//*Label 8527*/ GIMT_Encode4(313876), // Rule ID 56105 // |
| 123468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 123469 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123470 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123471 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123472 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123475 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123476 | // (strict_fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 123477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 123478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123479 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123481 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123486 | GIR_RootConstrainSelectedInstOperands, |
| 123487 | // GIR_Coverage, 56105, |
| 123488 | GIR_EraseRootFromParent_Done, |
| 123489 | // Label 8527: @313876 |
| 123490 | GIM_Try, /*On fail goto*//*Label 8528*/ GIMT_Encode4(313938), // Rule ID 72558 // |
| 123491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 123492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123493 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123494 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123495 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123496 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123497 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123498 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123499 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 123500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 123501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123502 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123504 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123509 | GIR_RootConstrainSelectedInstOperands, |
| 123510 | // GIR_Coverage, 72558, |
| 123511 | GIR_EraseRootFromParent_Done, |
| 123512 | // Label 8528: @313938 |
| 123513 | GIM_Try, /*On fail goto*//*Label 8529*/ GIMT_Encode4(314000), // Rule ID 72559 // |
| 123514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 123515 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123517 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123518 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123519 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123520 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123521 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123522 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFNMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 123523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E32), |
| 123524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123525 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123527 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123532 | GIR_RootConstrainSelectedInstOperands, |
| 123533 | // GIR_Coverage, 72559, |
| 123534 | GIR_EraseRootFromParent_Done, |
| 123535 | // Label 8529: @314000 |
| 123536 | GIM_Try, /*On fail goto*//*Label 8530*/ GIMT_Encode4(314062), // Rule ID 56096 // |
| 123537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 123538 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123540 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 123541 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123542 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123543 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123544 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123545 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 123546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E32), |
| 123547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123548 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123549 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 123551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123555 | GIR_RootConstrainSelectedInstOperands, |
| 123556 | // GIR_Coverage, 56096, |
| 123557 | GIR_EraseRootFromParent_Done, |
| 123558 | // Label 8530: @314062 |
| 123559 | GIM_Try, /*On fail goto*//*Label 8531*/ GIMT_Encode4(314124), // Rule ID 56097 // |
| 123560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 123561 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123563 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 123564 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123565 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 123566 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123567 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123568 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)) => (PseudoVFMSUB_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 123569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E32), |
| 123570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123571 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123572 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 123574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123578 | GIR_RootConstrainSelectedInstOperands, |
| 123579 | // GIR_Coverage, 56097, |
| 123580 | GIR_EraseRootFromParent_Done, |
| 123581 | // Label 8531: @314124 |
| 123582 | GIM_Try, /*On fail goto*//*Label 8532*/ GIMT_Encode4(314169), // Rule ID 56092 // |
| 123583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 123584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123585 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123586 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123587 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 123588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E32), |
| 123589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123590 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123591 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123592 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123597 | GIR_RootConstrainSelectedInstOperands, |
| 123598 | // GIR_Coverage, 56092, |
| 123599 | GIR_EraseRootFromParent_Done, |
| 123600 | // Label 8532: @314169 |
| 123601 | GIM_Try, /*On fail goto*//*Label 8533*/ GIMT_Encode4(314214), // Rule ID 56093 // |
| 123602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 123603 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123604 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123605 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123606 | // (strict_fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFMADD_VV_M4_E32:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 123607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E32), |
| 123608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123609 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123610 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123611 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 123615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123616 | GIR_RootConstrainSelectedInstOperands, |
| 123617 | // GIR_Coverage, 56093, |
| 123618 | GIR_EraseRootFromParent_Done, |
| 123619 | // Label 8533: @314214 |
| 123620 | GIM_Reject, |
| 123621 | // Label 8521: @314215 |
| 123622 | GIM_Reject, |
| 123623 | // Label 8305: @314216 |
| 123624 | GIM_Try, /*On fail goto*//*Label 8534*/ GIMT_Encode4(315005), |
| 123625 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123626 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, |
| 123627 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s64, |
| 123628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123629 | GIM_Try, /*On fail goto*//*Label 8535*/ GIMT_Encode4(314311), // Rule ID 56356 // |
| 123630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123631 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123632 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123633 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123634 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123635 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123636 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123637 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123638 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123639 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123640 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123641 | // (strict_fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 123643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123644 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123651 | GIR_RootConstrainSelectedInstOperands, |
| 123652 | // GIR_Coverage, 56356, |
| 123653 | GIR_EraseRootFromParent_Done, |
| 123654 | // Label 8535: @314311 |
| 123655 | GIM_Try, /*On fail goto*//*Label 8536*/ GIMT_Encode4(314388), // Rule ID 56357 // |
| 123656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123657 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123658 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123659 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123660 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123662 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123663 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123664 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123665 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123666 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123667 | // (strict_fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 123669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123670 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123677 | GIR_RootConstrainSelectedInstOperands, |
| 123678 | // GIR_Coverage, 56357, |
| 123679 | GIR_EraseRootFromParent_Done, |
| 123680 | // Label 8536: @314388 |
| 123681 | GIM_Try, /*On fail goto*//*Label 8537*/ GIMT_Encode4(314465), // Rule ID 72778 // |
| 123682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123687 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123688 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123689 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123690 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123691 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123692 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123693 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 123695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123696 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123697 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123703 | GIR_RootConstrainSelectedInstOperands, |
| 123704 | // GIR_Coverage, 72778, |
| 123705 | GIR_EraseRootFromParent_Done, |
| 123706 | // Label 8537: @314465 |
| 123707 | GIM_Try, /*On fail goto*//*Label 8538*/ GIMT_Encode4(314542), // Rule ID 72779 // |
| 123708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123709 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123710 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123711 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123712 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123713 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123714 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123715 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123716 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123717 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123718 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123719 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFNMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E64), |
| 123721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123722 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123723 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123724 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123729 | GIR_RootConstrainSelectedInstOperands, |
| 123730 | // GIR_Coverage, 72779, |
| 123731 | GIR_EraseRootFromParent_Done, |
| 123732 | // Label 8538: @314542 |
| 123733 | GIM_Try, /*On fail goto*//*Label 8539*/ GIMT_Encode4(314604), // Rule ID 56360 // |
| 123734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123735 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123736 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123737 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123738 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123739 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123740 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123741 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123742 | // (strict_fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 123744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123745 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123747 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123752 | GIR_RootConstrainSelectedInstOperands, |
| 123753 | // GIR_Coverage, 56360, |
| 123754 | GIR_EraseRootFromParent_Done, |
| 123755 | // Label 8539: @314604 |
| 123756 | GIM_Try, /*On fail goto*//*Label 8540*/ GIMT_Encode4(314666), // Rule ID 56361 // |
| 123757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123758 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123759 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123760 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123761 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123762 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123763 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123764 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123765 | // (strict_fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 123767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123768 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123769 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123770 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123775 | GIR_RootConstrainSelectedInstOperands, |
| 123776 | // GIR_Coverage, 56361, |
| 123777 | GIR_EraseRootFromParent_Done, |
| 123778 | // Label 8540: @314666 |
| 123779 | GIM_Try, /*On fail goto*//*Label 8541*/ GIMT_Encode4(314728), // Rule ID 72782 // |
| 123780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123782 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123783 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123784 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123785 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123786 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123787 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123788 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 123790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123791 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123793 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123798 | GIR_RootConstrainSelectedInstOperands, |
| 123799 | // GIR_Coverage, 72782, |
| 123800 | GIR_EraseRootFromParent_Done, |
| 123801 | // Label 8541: @314728 |
| 123802 | GIM_Try, /*On fail goto*//*Label 8542*/ GIMT_Encode4(314790), // Rule ID 72783 // |
| 123803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123804 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123805 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123806 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123807 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123808 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123809 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123810 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123811 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFNMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E64), |
| 123813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123814 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123816 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123821 | GIR_RootConstrainSelectedInstOperands, |
| 123822 | // GIR_Coverage, 72783, |
| 123823 | GIR_EraseRootFromParent_Done, |
| 123824 | // Label 8542: @314790 |
| 123825 | GIM_Try, /*On fail goto*//*Label 8543*/ GIMT_Encode4(314852), // Rule ID 56352 // |
| 123826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123827 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123828 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123829 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 123830 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123831 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123832 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123833 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123834 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E64), |
| 123836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123837 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123838 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 123840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123844 | GIR_RootConstrainSelectedInstOperands, |
| 123845 | // GIR_Coverage, 56352, |
| 123846 | GIR_EraseRootFromParent_Done, |
| 123847 | // Label 8543: @314852 |
| 123848 | GIM_Try, /*On fail goto*//*Label 8544*/ GIMT_Encode4(314914), // Rule ID 56353 // |
| 123849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123851 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123852 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 123853 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123854 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 123855 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123856 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 123857 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)) => (PseudoVFMSUB_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E64), |
| 123859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123860 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123861 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 123863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123867 | GIR_RootConstrainSelectedInstOperands, |
| 123868 | // GIR_Coverage, 56353, |
| 123869 | GIR_EraseRootFromParent_Done, |
| 123870 | // Label 8544: @314914 |
| 123871 | GIM_Try, /*On fail goto*//*Label 8545*/ GIMT_Encode4(314959), // Rule ID 56348 // |
| 123872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 123873 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123875 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123876 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] }) |
| 123877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E64), |
| 123878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123879 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123880 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123881 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123886 | GIR_RootConstrainSelectedInstOperands, |
| 123887 | // GIR_Coverage, 56348, |
| 123888 | GIR_EraseRootFromParent_Done, |
| 123889 | // Label 8545: @314959 |
| 123890 | GIM_Try, /*On fail goto*//*Label 8546*/ GIMT_Encode4(315004), // Rule ID 56349 // |
| 123891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 123892 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123893 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123894 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 123895 | // (strict_fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFMADD_VV_M8_E64:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] }) |
| 123896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E64), |
| 123897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123898 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123899 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 123900 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 123901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 123904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123905 | GIR_RootConstrainSelectedInstOperands, |
| 123906 | // GIR_Coverage, 56349, |
| 123907 | GIR_EraseRootFromParent_Done, |
| 123908 | // Label 8546: @315004 |
| 123909 | GIM_Reject, |
| 123910 | // Label 8534: @315005 |
| 123911 | GIM_Reject, |
| 123912 | // Label 8306: @315006 |
| 123913 | GIM_Try, /*On fail goto*//*Label 8547*/ GIMT_Encode4(315795), |
| 123914 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123915 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, |
| 123916 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s16, |
| 123917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123918 | GIM_Try, /*On fail goto*//*Label 8548*/ GIMT_Encode4(315101), // Rule ID 55908 // |
| 123919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123920 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123921 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123922 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123923 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123924 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123925 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123926 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123927 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123928 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123929 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123930 | // (strict_fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 123932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123933 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123940 | GIR_RootConstrainSelectedInstOperands, |
| 123941 | // GIR_Coverage, 55908, |
| 123942 | GIR_EraseRootFromParent_Done, |
| 123943 | // Label 8548: @315101 |
| 123944 | GIM_Try, /*On fail goto*//*Label 8549*/ GIMT_Encode4(315178), // Rule ID 55909 // |
| 123945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123946 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123947 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123948 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123949 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123950 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123951 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123952 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123953 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123954 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123955 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123956 | // (strict_fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 123957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 123958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123959 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 123960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123966 | GIR_RootConstrainSelectedInstOperands, |
| 123967 | // GIR_Coverage, 55909, |
| 123968 | GIR_EraseRootFromParent_Done, |
| 123969 | // Label 8549: @315178 |
| 123970 | GIM_Try, /*On fail goto*//*Label 8550*/ GIMT_Encode4(315255), // Rule ID 72386 // |
| 123971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 123972 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123973 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 123974 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123975 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123977 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 123978 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 123979 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 123980 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123981 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 123982 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 123983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 123984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 123985 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 123986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 123987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 123988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 123989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 123990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 123991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 123992 | GIR_RootConstrainSelectedInstOperands, |
| 123993 | // GIR_Coverage, 72386, |
| 123994 | GIR_EraseRootFromParent_Done, |
| 123995 | // Label 8550: @315255 |
| 123996 | GIM_Try, /*On fail goto*//*Label 8551*/ GIMT_Encode4(315332), // Rule ID 72387 // |
| 123997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 123998 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 123999 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124000 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124001 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124002 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124003 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124004 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124005 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124006 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124007 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124008 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFNMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M4_E16), |
| 124010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124011 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124018 | GIR_RootConstrainSelectedInstOperands, |
| 124019 | // GIR_Coverage, 72387, |
| 124020 | GIR_EraseRootFromParent_Done, |
| 124021 | // Label 8551: @315332 |
| 124022 | GIM_Try, /*On fail goto*//*Label 8552*/ GIMT_Encode4(315394), // Rule ID 55912 // |
| 124023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124025 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124026 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124027 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124028 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124029 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124030 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124031 | // (strict_fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 124033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124034 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124036 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124041 | GIR_RootConstrainSelectedInstOperands, |
| 124042 | // GIR_Coverage, 55912, |
| 124043 | GIR_EraseRootFromParent_Done, |
| 124044 | // Label 8552: @315394 |
| 124045 | GIM_Try, /*On fail goto*//*Label 8553*/ GIMT_Encode4(315456), // Rule ID 55913 // |
| 124046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124050 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124051 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124052 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124053 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124054 | // (strict_fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 124056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124057 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124059 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124064 | GIR_RootConstrainSelectedInstOperands, |
| 124065 | // GIR_Coverage, 55913, |
| 124066 | GIR_EraseRootFromParent_Done, |
| 124067 | // Label 8553: @315456 |
| 124068 | GIM_Try, /*On fail goto*//*Label 8554*/ GIMT_Encode4(315518), // Rule ID 72390 // |
| 124069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124072 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124074 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124075 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124076 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124077 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 124079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124080 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124082 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124087 | GIR_RootConstrainSelectedInstOperands, |
| 124088 | // GIR_Coverage, 72390, |
| 124089 | GIR_EraseRootFromParent_Done, |
| 124090 | // Label 8554: @315518 |
| 124091 | GIM_Try, /*On fail goto*//*Label 8555*/ GIMT_Encode4(315580), // Rule ID 72391 // |
| 124092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124093 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124094 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124095 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124096 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124097 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124098 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124099 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124100 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFNMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M4_E16), |
| 124102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124103 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124104 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124105 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124110 | GIR_RootConstrainSelectedInstOperands, |
| 124111 | // GIR_Coverage, 72391, |
| 124112 | GIR_EraseRootFromParent_Done, |
| 124113 | // Label 8555: @315580 |
| 124114 | GIM_Try, /*On fail goto*//*Label 8556*/ GIMT_Encode4(315642), // Rule ID 55904 // |
| 124115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124117 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124118 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 124119 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124120 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124121 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124122 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124123 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E16), |
| 124125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124126 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124127 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 124129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124133 | GIR_RootConstrainSelectedInstOperands, |
| 124134 | // GIR_Coverage, 55904, |
| 124135 | GIR_EraseRootFromParent_Done, |
| 124136 | // Label 8556: @315642 |
| 124137 | GIM_Try, /*On fail goto*//*Label 8557*/ GIMT_Encode4(315704), // Rule ID 55905 // |
| 124138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124140 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124141 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 124142 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124143 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 124144 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124145 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124146 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)) => (PseudoVFMSUB_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M4_E16), |
| 124148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124149 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124150 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 124152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124156 | GIR_RootConstrainSelectedInstOperands, |
| 124157 | // GIR_Coverage, 55905, |
| 124158 | GIR_EraseRootFromParent_Done, |
| 124159 | // Label 8557: @315704 |
| 124160 | GIM_Try, /*On fail goto*//*Label 8558*/ GIMT_Encode4(315749), // Rule ID 55900 // |
| 124161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124162 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124164 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124165 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E16), |
| 124167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124168 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124169 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124170 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124175 | GIR_RootConstrainSelectedInstOperands, |
| 124176 | // GIR_Coverage, 55900, |
| 124177 | GIR_EraseRootFromParent_Done, |
| 124178 | // Label 8558: @315749 |
| 124179 | GIM_Try, /*On fail goto*//*Label 8559*/ GIMT_Encode4(315794), // Rule ID 55901 // |
| 124180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124181 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124182 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124183 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 124184 | // (strict_fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFMADD_VV_M4_E16:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M4_E16), |
| 124186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124187 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124188 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124189 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124194 | GIR_RootConstrainSelectedInstOperands, |
| 124195 | // GIR_Coverage, 55901, |
| 124196 | GIR_EraseRootFromParent_Done, |
| 124197 | // Label 8559: @315794 |
| 124198 | GIM_Reject, |
| 124199 | // Label 8547: @315795 |
| 124200 | GIM_Reject, |
| 124201 | // Label 8307: @315796 |
| 124202 | GIM_Try, /*On fail goto*//*Label 8560*/ GIMT_Encode4(316585), |
| 124203 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124204 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, |
| 124205 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s32, |
| 124206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124207 | GIM_Try, /*On fail goto*//*Label 8561*/ GIMT_Encode4(315891), // Rule ID 56164 // |
| 124208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 124209 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124210 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124211 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124212 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124213 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124214 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124215 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124216 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124217 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124218 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124219 | // (strict_fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 124220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 124221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124222 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124229 | GIR_RootConstrainSelectedInstOperands, |
| 124230 | // GIR_Coverage, 56164, |
| 124231 | GIR_EraseRootFromParent_Done, |
| 124232 | // Label 8561: @315891 |
| 124233 | GIM_Try, /*On fail goto*//*Label 8562*/ GIMT_Encode4(315968), // Rule ID 56165 // |
| 124234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 124235 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124236 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124237 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124238 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124240 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124241 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124242 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124243 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124244 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124245 | // (strict_fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 124246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 124247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124248 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124250 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124255 | GIR_RootConstrainSelectedInstOperands, |
| 124256 | // GIR_Coverage, 56165, |
| 124257 | GIR_EraseRootFromParent_Done, |
| 124258 | // Label 8562: @315968 |
| 124259 | GIM_Try, /*On fail goto*//*Label 8563*/ GIMT_Encode4(316045), // Rule ID 72610 // |
| 124260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 124261 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124263 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124265 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124266 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124267 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124268 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124269 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124270 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124271 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 124272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 124273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124274 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124281 | GIR_RootConstrainSelectedInstOperands, |
| 124282 | // GIR_Coverage, 72610, |
| 124283 | GIR_EraseRootFromParent_Done, |
| 124284 | // Label 8563: @316045 |
| 124285 | GIM_Try, /*On fail goto*//*Label 8564*/ GIMT_Encode4(316122), // Rule ID 72611 // |
| 124286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 124287 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124288 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124289 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124290 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124291 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124292 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124293 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124294 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124295 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124296 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124297 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFNMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 124298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E32), |
| 124299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124300 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124307 | GIR_RootConstrainSelectedInstOperands, |
| 124308 | // GIR_Coverage, 72611, |
| 124309 | GIR_EraseRootFromParent_Done, |
| 124310 | // Label 8564: @316122 |
| 124311 | GIM_Try, /*On fail goto*//*Label 8565*/ GIMT_Encode4(316184), // Rule ID 56168 // |
| 124312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 124313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124316 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124318 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124319 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124320 | // (strict_fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 124321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 124322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124323 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124325 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124330 | GIR_RootConstrainSelectedInstOperands, |
| 124331 | // GIR_Coverage, 56168, |
| 124332 | GIR_EraseRootFromParent_Done, |
| 124333 | // Label 8565: @316184 |
| 124334 | GIM_Try, /*On fail goto*//*Label 8566*/ GIMT_Encode4(316246), // Rule ID 56169 // |
| 124335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 124336 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124337 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124338 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124339 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124340 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124341 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124342 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124343 | // (strict_fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 124344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 124345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124346 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124348 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124353 | GIR_RootConstrainSelectedInstOperands, |
| 124354 | // GIR_Coverage, 56169, |
| 124355 | GIR_EraseRootFromParent_Done, |
| 124356 | // Label 8566: @316246 |
| 124357 | GIM_Try, /*On fail goto*//*Label 8567*/ GIMT_Encode4(316308), // Rule ID 72614 // |
| 124358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 124359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124360 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124361 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124362 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124363 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124364 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124365 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124366 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 124367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 124368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124369 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124371 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124376 | GIR_RootConstrainSelectedInstOperands, |
| 124377 | // GIR_Coverage, 72614, |
| 124378 | GIR_EraseRootFromParent_Done, |
| 124379 | // Label 8567: @316308 |
| 124380 | GIM_Try, /*On fail goto*//*Label 8568*/ GIMT_Encode4(316370), // Rule ID 72615 // |
| 124381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 124382 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124383 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124384 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124385 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124386 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124387 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124388 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124389 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFNMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 124390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E32), |
| 124391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124392 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124394 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124399 | GIR_RootConstrainSelectedInstOperands, |
| 124400 | // GIR_Coverage, 72615, |
| 124401 | GIR_EraseRootFromParent_Done, |
| 124402 | // Label 8568: @316370 |
| 124403 | GIM_Try, /*On fail goto*//*Label 8569*/ GIMT_Encode4(316432), // Rule ID 56160 // |
| 124404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 124405 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124406 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 124408 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124410 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124411 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124412 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 124413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E32), |
| 124414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124415 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124416 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 124418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124422 | GIR_RootConstrainSelectedInstOperands, |
| 124423 | // GIR_Coverage, 56160, |
| 124424 | GIR_EraseRootFromParent_Done, |
| 124425 | // Label 8569: @316432 |
| 124426 | GIM_Try, /*On fail goto*//*Label 8570*/ GIMT_Encode4(316494), // Rule ID 56161 // |
| 124427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 124428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124430 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 124431 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124432 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 124433 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124434 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124435 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)) => (PseudoVFMSUB_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 124436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E32), |
| 124437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124438 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124439 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 124441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124445 | GIR_RootConstrainSelectedInstOperands, |
| 124446 | // GIR_Coverage, 56161, |
| 124447 | GIR_EraseRootFromParent_Done, |
| 124448 | // Label 8570: @316494 |
| 124449 | GIM_Try, /*On fail goto*//*Label 8571*/ GIMT_Encode4(316539), // Rule ID 56156 // |
| 124450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 124451 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124452 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124453 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124454 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] }) |
| 124455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E32), |
| 124456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124457 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124458 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124459 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124464 | GIR_RootConstrainSelectedInstOperands, |
| 124465 | // GIR_Coverage, 56156, |
| 124466 | GIR_EraseRootFromParent_Done, |
| 124467 | // Label 8571: @316539 |
| 124468 | GIM_Try, /*On fail goto*//*Label 8572*/ GIMT_Encode4(316584), // Rule ID 56157 // |
| 124469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 124470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124471 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124472 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124473 | // (strict_fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFMADD_VV_M8_E32:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] }) |
| 124474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E32), |
| 124475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124476 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124477 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124478 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 124482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124483 | GIR_RootConstrainSelectedInstOperands, |
| 124484 | // GIR_Coverage, 56157, |
| 124485 | GIR_EraseRootFromParent_Done, |
| 124486 | // Label 8572: @316584 |
| 124487 | GIM_Reject, |
| 124488 | // Label 8560: @316585 |
| 124489 | GIM_Reject, |
| 124490 | // Label 8308: @316586 |
| 124491 | GIM_Try, /*On fail goto*//*Label 8573*/ GIMT_Encode4(317375), |
| 124492 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124493 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, |
| 124494 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv32s16, |
| 124495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124496 | GIM_Try, /*On fail goto*//*Label 8574*/ GIMT_Encode4(316681), // Rule ID 55972 // |
| 124497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124498 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124499 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124500 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124501 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124502 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124503 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124504 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124505 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124506 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124507 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124508 | // (strict_fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 124510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124511 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124513 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124518 | GIR_RootConstrainSelectedInstOperands, |
| 124519 | // GIR_Coverage, 55972, |
| 124520 | GIR_EraseRootFromParent_Done, |
| 124521 | // Label 8574: @316681 |
| 124522 | GIM_Try, /*On fail goto*//*Label 8575*/ GIMT_Encode4(316758), // Rule ID 55973 // |
| 124523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124524 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124525 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124526 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124527 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124528 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124529 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124530 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124531 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124532 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124533 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124534 | // (strict_fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 124536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124537 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124539 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124544 | GIR_RootConstrainSelectedInstOperands, |
| 124545 | // GIR_Coverage, 55973, |
| 124546 | GIR_EraseRootFromParent_Done, |
| 124547 | // Label 8575: @316758 |
| 124548 | GIM_Try, /*On fail goto*//*Label 8576*/ GIMT_Encode4(316835), // Rule ID 72442 // |
| 124549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124550 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124551 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124552 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124553 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124554 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124555 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124556 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124557 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124558 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124559 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124560 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 124562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124563 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124570 | GIR_RootConstrainSelectedInstOperands, |
| 124571 | // GIR_Coverage, 72442, |
| 124572 | GIR_EraseRootFromParent_Done, |
| 124573 | // Label 8576: @316835 |
| 124574 | GIM_Try, /*On fail goto*//*Label 8577*/ GIMT_Encode4(316912), // Rule ID 72443 // |
| 124575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124578 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124579 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124580 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124581 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 124582 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124583 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124584 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124585 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124586 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFNMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMADD_VV_M8_E16), |
| 124588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124589 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124590 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2 |
| 124592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124596 | GIR_RootConstrainSelectedInstOperands, |
| 124597 | // GIR_Coverage, 72443, |
| 124598 | GIR_EraseRootFromParent_Done, |
| 124599 | // Label 8577: @316912 |
| 124600 | GIM_Try, /*On fail goto*//*Label 8578*/ GIMT_Encode4(316974), // Rule ID 55976 // |
| 124601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124602 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124603 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124604 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124607 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124608 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124609 | // (strict_fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 124611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124612 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124614 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124619 | GIR_RootConstrainSelectedInstOperands, |
| 124620 | // GIR_Coverage, 55976, |
| 124621 | GIR_EraseRootFromParent_Done, |
| 124622 | // Label 8578: @316974 |
| 124623 | GIM_Try, /*On fail goto*//*Label 8579*/ GIMT_Encode4(317036), // Rule ID 55977 // |
| 124624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124625 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124626 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124627 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124628 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124629 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124630 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124631 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124632 | // (strict_fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 124634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124635 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124637 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124642 | GIR_RootConstrainSelectedInstOperands, |
| 124643 | // GIR_Coverage, 55977, |
| 124644 | GIR_EraseRootFromParent_Done, |
| 124645 | // Label 8579: @317036 |
| 124646 | GIM_Try, /*On fail goto*//*Label 8580*/ GIMT_Encode4(317098), // Rule ID 72446 // |
| 124647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124649 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124650 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124651 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124652 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124653 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124654 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124655 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 124657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124658 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124660 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124665 | GIR_RootConstrainSelectedInstOperands, |
| 124666 | // GIR_Coverage, 72446, |
| 124667 | GIR_EraseRootFromParent_Done, |
| 124668 | // Label 8580: @317098 |
| 124669 | GIM_Try, /*On fail goto*//*Label 8581*/ GIMT_Encode4(317160), // Rule ID 72447 // |
| 124670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124675 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124676 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124677 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124678 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFNMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFNMSUB_VV_M8_E16), |
| 124680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124681 | GIR_RootToRootCopy, /*OpIdx*/1, // rd |
| 124682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 |
| 124683 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124688 | GIR_RootConstrainSelectedInstOperands, |
| 124689 | // GIR_Coverage, 72447, |
| 124690 | GIR_EraseRootFromParent_Done, |
| 124691 | // Label 8581: @317160 |
| 124692 | GIM_Try, /*On fail goto*//*Label 8582*/ GIMT_Encode4(317222), // Rule ID 55968 // |
| 124693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124694 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124696 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 124697 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124698 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124699 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124700 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124701 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E16), |
| 124703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124704 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124705 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 124707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124711 | GIR_RootConstrainSelectedInstOperands, |
| 124712 | // GIR_Coverage, 55968, |
| 124713 | GIR_EraseRootFromParent_Done, |
| 124714 | // Label 8582: @317222 |
| 124715 | GIM_Try, /*On fail goto*//*Label 8583*/ GIMT_Encode4(317284), // Rule ID 55969 // |
| 124716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124718 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124719 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 124720 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 124721 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 124722 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124723 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124724 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)) => (PseudoVFMSUB_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMSUB_VV_M8_E16), |
| 124726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124727 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124728 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 |
| 124730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124734 | GIR_RootConstrainSelectedInstOperands, |
| 124735 | // GIR_Coverage, 55969, |
| 124736 | GIR_EraseRootFromParent_Done, |
| 124737 | // Label 8583: @317284 |
| 124738 | GIM_Try, /*On fail goto*//*Label 8584*/ GIMT_Encode4(317329), // Rule ID 55964 // |
| 124739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124741 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124742 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124743 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] }) |
| 124744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E16), |
| 124745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124746 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124747 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124748 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124753 | GIR_RootConstrainSelectedInstOperands, |
| 124754 | // GIR_Coverage, 55964, |
| 124755 | GIR_EraseRootFromParent_Done, |
| 124756 | // Label 8584: @317329 |
| 124757 | GIM_Try, /*On fail goto*//*Label 8585*/ GIMT_Encode4(317374), // Rule ID 55965 // |
| 124758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 124759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124761 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 124762 | // (strict_fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFMADD_VV_M8_E16:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] }) |
| 124763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFMADD_VV_M8_E16), |
| 124764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124765 | GIR_RootToRootCopy, /*OpIdx*/2, // rd |
| 124766 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124767 | GIR_RootToRootCopy, /*OpIdx*/3, // rs2 |
| 124768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 124770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 124771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 124772 | GIR_RootConstrainSelectedInstOperands, |
| 124773 | // GIR_Coverage, 55965, |
| 124774 | GIR_EraseRootFromParent_Done, |
| 124775 | // Label 8585: @317374 |
| 124776 | GIM_Reject, |
| 124777 | // Label 8573: @317375 |
| 124778 | GIM_Reject, |
| 124779 | // Label 8309: @317376 |
| 124780 | GIM_Reject, |
| 124781 | // Label 94: @317377 |
| 124782 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(32), /*)*//*default:*//*Label 8604*/ GIMT_Encode4(319552), |
| 124783 | /*GILLT_s16*//*Label 8586*/ GIMT_Encode4(317508), |
| 124784 | /*GILLT_s32*//*Label 8587*/ GIMT_Encode4(317630), |
| 124785 | /*GILLT_s64*//*Label 8588*/ GIMT_Encode4(317752), GIMT_Encode4(0), GIMT_Encode4(0), |
| 124786 | /*GILLT_nxv1s16*//*Label 8589*/ GIMT_Encode4(317902), |
| 124787 | /*GILLT_nxv1s32*//*Label 8590*/ GIMT_Encode4(318012), |
| 124788 | /*GILLT_nxv1s64*//*Label 8591*/ GIMT_Encode4(318122), GIMT_Encode4(0), GIMT_Encode4(0), |
| 124789 | /*GILLT_nxv2s16*//*Label 8592*/ GIMT_Encode4(318232), |
| 124790 | /*GILLT_nxv2s32*//*Label 8593*/ GIMT_Encode4(318342), |
| 124791 | /*GILLT_nxv2s64*//*Label 8594*/ GIMT_Encode4(318452), GIMT_Encode4(0), GIMT_Encode4(0), |
| 124792 | /*GILLT_nxv4s16*//*Label 8595*/ GIMT_Encode4(318562), |
| 124793 | /*GILLT_nxv4s32*//*Label 8596*/ GIMT_Encode4(318672), |
| 124794 | /*GILLT_nxv4s64*//*Label 8597*/ GIMT_Encode4(318782), GIMT_Encode4(0), GIMT_Encode4(0), |
| 124795 | /*GILLT_nxv8s16*//*Label 8598*/ GIMT_Encode4(318892), |
| 124796 | /*GILLT_nxv8s32*//*Label 8599*/ GIMT_Encode4(319002), |
| 124797 | /*GILLT_nxv8s64*//*Label 8600*/ GIMT_Encode4(319112), GIMT_Encode4(0), GIMT_Encode4(0), |
| 124798 | /*GILLT_nxv16s16*//*Label 8601*/ GIMT_Encode4(319222), |
| 124799 | /*GILLT_nxv16s32*//*Label 8602*/ GIMT_Encode4(319332), GIMT_Encode4(0), GIMT_Encode4(0), |
| 124800 | /*GILLT_nxv32s16*//*Label 8603*/ GIMT_Encode4(319442), |
| 124801 | // Label 8586: @317508 |
| 124802 | GIM_Try, /*On fail goto*//*Label 8605*/ GIMT_Encode4(317629), |
| 124803 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 124804 | GIM_Try, /*On fail goto*//*Label 8606*/ GIMT_Encode4(317544), // Rule ID 2042 // |
| 124805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 124806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 124807 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 124808 | // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 124809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H), |
| 124810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124811 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124813 | GIR_RootConstrainSelectedInstOperands, |
| 124814 | // GIR_Coverage, 2042, |
| 124815 | GIR_EraseRootFromParent_Done, |
| 124816 | // Label 8606: @317544 |
| 124817 | GIM_Try, /*On fail goto*//*Label 8607*/ GIMT_Encode4(317572), // Rule ID 2043 // |
| 124818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 124819 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 124820 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 124821 | // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1) => (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 124822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H), |
| 124823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124824 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124826 | GIR_RootConstrainSelectedInstOperands, |
| 124827 | // GIR_Coverage, 2043, |
| 124828 | GIR_EraseRootFromParent_Done, |
| 124829 | // Label 8607: @317572 |
| 124830 | GIM_Try, /*On fail goto*//*Label 8608*/ GIMT_Encode4(317600), // Rule ID 2074 // |
| 124831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 124832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 124833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 124834 | // (strict_fsqrt:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1) => (FSQRT_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, 7:{ *:[i64] }) |
| 124835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H_INX), |
| 124836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124837 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124839 | GIR_RootConstrainSelectedInstOperands, |
| 124840 | // GIR_Coverage, 2074, |
| 124841 | GIR_EraseRootFromParent_Done, |
| 124842 | // Label 8608: @317600 |
| 124843 | GIM_Try, /*On fail goto*//*Label 8609*/ GIMT_Encode4(317628), // Rule ID 2075 // |
| 124844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 124845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 124846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 124847 | // (strict_fsqrt:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1) => (FSQRT_H_INX:{ *:[f16] } FPR16INX:{ *:[f16] }:$rs1, 7:{ *:[i32] }) |
| 124848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_H_INX), |
| 124849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124850 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124852 | GIR_RootConstrainSelectedInstOperands, |
| 124853 | // GIR_Coverage, 2075, |
| 124854 | GIR_EraseRootFromParent_Done, |
| 124855 | // Label 8609: @317628 |
| 124856 | GIM_Reject, |
| 124857 | // Label 8605: @317629 |
| 124858 | GIM_Reject, |
| 124859 | // Label 8587: @317630 |
| 124860 | GIM_Try, /*On fail goto*//*Label 8610*/ GIMT_Encode4(317751), |
| 124861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 124862 | GIM_Try, /*On fail goto*//*Label 8611*/ GIMT_Encode4(317666), // Rule ID 1354 // |
| 124863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 124864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 124865 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 124866 | // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 124867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S), |
| 124868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124869 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124871 | GIR_RootConstrainSelectedInstOperands, |
| 124872 | // GIR_Coverage, 1354, |
| 124873 | GIR_EraseRootFromParent_Done, |
| 124874 | // Label 8611: @317666 |
| 124875 | GIM_Try, /*On fail goto*//*Label 8612*/ GIMT_Encode4(317694), // Rule ID 1355 // |
| 124876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 124877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 124878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 124879 | // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 124880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S), |
| 124881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124882 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124884 | GIR_RootConstrainSelectedInstOperands, |
| 124885 | // GIR_Coverage, 1355, |
| 124886 | GIR_EraseRootFromParent_Done, |
| 124887 | // Label 8612: @317694 |
| 124888 | GIM_Try, /*On fail goto*//*Label 8613*/ GIMT_Encode4(317722), // Rule ID 1362 // |
| 124889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 124890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 124891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 124892 | // (strict_fsqrt:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1) => (FSQRT_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, 7:{ *:[i64] }) |
| 124893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S_INX), |
| 124894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124895 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124897 | GIR_RootConstrainSelectedInstOperands, |
| 124898 | // GIR_Coverage, 1362, |
| 124899 | GIR_EraseRootFromParent_Done, |
| 124900 | // Label 8613: @317722 |
| 124901 | GIM_Try, /*On fail goto*//*Label 8614*/ GIMT_Encode4(317750), // Rule ID 1363 // |
| 124902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 124903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 124904 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 124905 | // (strict_fsqrt:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1) => (FSQRT_S_INX:{ *:[f32] } FPR32INX:{ *:[f32] }:$rs1, 7:{ *:[i32] }) |
| 124906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_S_INX), |
| 124907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124908 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124910 | GIR_RootConstrainSelectedInstOperands, |
| 124911 | // GIR_Coverage, 1363, |
| 124912 | GIR_EraseRootFromParent_Done, |
| 124913 | // Label 8614: @317750 |
| 124914 | GIM_Reject, |
| 124915 | // Label 8610: @317751 |
| 124916 | GIM_Reject, |
| 124917 | // Label 8588: @317752 |
| 124918 | GIM_Try, /*On fail goto*//*Label 8615*/ GIMT_Encode4(317901), |
| 124919 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 124920 | GIM_Try, /*On fail goto*//*Label 8616*/ GIMT_Encode4(317788), // Rule ID 1689 // |
| 124921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 124922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 124923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 124924 | // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 124925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D), |
| 124926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124927 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124929 | GIR_RootConstrainSelectedInstOperands, |
| 124930 | // GIR_Coverage, 1689, |
| 124931 | GIR_EraseRootFromParent_Done, |
| 124932 | // Label 8616: @317788 |
| 124933 | GIM_Try, /*On fail goto*//*Label 8617*/ GIMT_Encode4(317816), // Rule ID 1690 // |
| 124934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 124935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 124936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 124937 | // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 124938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D), |
| 124939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124940 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124942 | GIR_RootConstrainSelectedInstOperands, |
| 124943 | // GIR_Coverage, 1690, |
| 124944 | GIR_EraseRootFromParent_Done, |
| 124945 | // Label 8617: @317816 |
| 124946 | GIM_Try, /*On fail goto*//*Label 8618*/ GIMT_Encode4(317844), // Rule ID 1723 // |
| 124947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 124948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 124949 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 124950 | // (strict_fsqrt:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1) => (FSQRT_D_INX:{ *:[f64] } FPR64INX:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 124951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D_INX), |
| 124952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124953 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124955 | GIR_RootConstrainSelectedInstOperands, |
| 124956 | // GIR_Coverage, 1723, |
| 124957 | GIR_EraseRootFromParent_Done, |
| 124958 | // Label 8618: @317844 |
| 124959 | GIM_Try, /*On fail goto*//*Label 8619*/ GIMT_Encode4(317872), // Rule ID 1742 // |
| 124960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 124961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 124962 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 124963 | // (strict_fsqrt:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FSQRT_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i64] }) |
| 124964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D_IN32X), |
| 124965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124966 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124968 | GIR_RootConstrainSelectedInstOperands, |
| 124969 | // GIR_Coverage, 1742, |
| 124970 | GIR_EraseRootFromParent_Done, |
| 124971 | // Label 8619: @317872 |
| 124972 | GIM_Try, /*On fail goto*//*Label 8620*/ GIMT_Encode4(317900), // Rule ID 1743 // |
| 124973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 124974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 124975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 124976 | // (strict_fsqrt:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FSQRT_D_IN32X:{ *:[f64] } FPR64IN32X:{ *:[f64] }:$rs1, 7:{ *:[i32] }) |
| 124977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::FSQRT_D_IN32X), |
| 124978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 124979 | GIR_RootToRootCopy, /*OpIdx*/1, // rs1 |
| 124980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 124981 | GIR_RootConstrainSelectedInstOperands, |
| 124982 | // GIR_Coverage, 1743, |
| 124983 | GIR_EraseRootFromParent_Done, |
| 124984 | // Label 8620: @317900 |
| 124985 | GIM_Reject, |
| 124986 | // Label 8615: @317901 |
| 124987 | GIM_Reject, |
| 124988 | // Label 8589: @317902 |
| 124989 | GIM_Try, /*On fail goto*//*Label 8621*/ GIMT_Encode4(318011), |
| 124990 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, |
| 124991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 124992 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 124993 | GIM_Try, /*On fail goto*//*Label 8622*/ GIMT_Encode4(317964), // Rule ID 56860 // |
| 124994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 124995 | // (strict_fsqrt:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSQRT_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 124996 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 124997 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 124998 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 124999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF4_E16), |
| 125001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125002 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125003 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125008 | GIR_RootConstrainSelectedInstOperands, |
| 125009 | // GIR_Coverage, 56860, |
| 125010 | GIR_EraseRootFromParent_Done, |
| 125011 | // Label 8622: @317964 |
| 125012 | GIM_Try, /*On fail goto*//*Label 8623*/ GIMT_Encode4(318010), // Rule ID 56861 // |
| 125013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 125014 | // (strict_fsqrt:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2) => (PseudoVFSQRT_V_MF4_E16:{ *:[nxv1f16] } (IMPLICIT_DEF:{ *:[nxv1f16] }), VR:{ *:[nxv1f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 125015 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, |
| 125016 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125017 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF4_E16), |
| 125020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125021 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125022 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125027 | GIR_RootConstrainSelectedInstOperands, |
| 125028 | // GIR_Coverage, 56861, |
| 125029 | GIR_EraseRootFromParent_Done, |
| 125030 | // Label 8623: @318010 |
| 125031 | GIM_Reject, |
| 125032 | // Label 8621: @318011 |
| 125033 | GIM_Reject, |
| 125034 | // Label 8590: @318012 |
| 125035 | GIM_Try, /*On fail goto*//*Label 8624*/ GIMT_Encode4(318121), |
| 125036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, |
| 125037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125038 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125039 | GIM_Try, /*On fail goto*//*Label 8625*/ GIMT_Encode4(318074), // Rule ID 56900 // |
| 125040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 125041 | // (strict_fsqrt:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSQRT_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 125042 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 125043 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125044 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E32), |
| 125047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125048 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125049 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125054 | GIR_RootConstrainSelectedInstOperands, |
| 125055 | // GIR_Coverage, 56900, |
| 125056 | GIR_EraseRootFromParent_Done, |
| 125057 | // Label 8625: @318074 |
| 125058 | GIM_Try, /*On fail goto*//*Label 8626*/ GIMT_Encode4(318120), // Rule ID 56901 // |
| 125059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 125060 | // (strict_fsqrt:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2) => (PseudoVFSQRT_V_MF2_E32:{ *:[nxv1f32] } (IMPLICIT_DEF:{ *:[nxv1f32] }), VR:{ *:[nxv1f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 125061 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, |
| 125062 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125063 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125064 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E32), |
| 125066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125067 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125068 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125073 | GIR_RootConstrainSelectedInstOperands, |
| 125074 | // GIR_Coverage, 56901, |
| 125075 | GIR_EraseRootFromParent_Done, |
| 125076 | // Label 8626: @318120 |
| 125077 | GIM_Reject, |
| 125078 | // Label 8624: @318121 |
| 125079 | GIM_Reject, |
| 125080 | // Label 8591: @318122 |
| 125081 | GIM_Try, /*On fail goto*//*Label 8627*/ GIMT_Encode4(318231), |
| 125082 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, |
| 125083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125084 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125085 | GIM_Try, /*On fail goto*//*Label 8628*/ GIMT_Encode4(318184), // Rule ID 56960 // |
| 125086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 125087 | // (strict_fsqrt:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSQRT_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 125088 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 125089 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125090 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E64), |
| 125093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125095 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125100 | GIR_RootConstrainSelectedInstOperands, |
| 125101 | // GIR_Coverage, 56960, |
| 125102 | GIR_EraseRootFromParent_Done, |
| 125103 | // Label 8628: @318184 |
| 125104 | GIM_Try, /*On fail goto*//*Label 8629*/ GIMT_Encode4(318230), // Rule ID 56961 // |
| 125105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 125106 | // (strict_fsqrt:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2) => (PseudoVFSQRT_V_M1_E64:{ *:[nxv1f64] } (IMPLICIT_DEF:{ *:[nxv1f64] }), VR:{ *:[nxv1f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 125107 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, |
| 125108 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125109 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E64), |
| 125112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125113 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125114 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125119 | GIR_RootConstrainSelectedInstOperands, |
| 125120 | // GIR_Coverage, 56961, |
| 125121 | GIR_EraseRootFromParent_Done, |
| 125122 | // Label 8629: @318230 |
| 125123 | GIM_Reject, |
| 125124 | // Label 8627: @318231 |
| 125125 | GIM_Reject, |
| 125126 | // Label 8592: @318232 |
| 125127 | GIM_Try, /*On fail goto*//*Label 8630*/ GIMT_Encode4(318341), |
| 125128 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, |
| 125129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125130 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125131 | GIM_Try, /*On fail goto*//*Label 8631*/ GIMT_Encode4(318294), // Rule ID 56880 // |
| 125132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 125133 | // (strict_fsqrt:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSQRT_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 125134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 125135 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125136 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E16), |
| 125139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125141 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125146 | GIR_RootConstrainSelectedInstOperands, |
| 125147 | // GIR_Coverage, 56880, |
| 125148 | GIR_EraseRootFromParent_Done, |
| 125149 | // Label 8631: @318294 |
| 125150 | GIM_Try, /*On fail goto*//*Label 8632*/ GIMT_Encode4(318340), // Rule ID 56881 // |
| 125151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 125152 | // (strict_fsqrt:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2) => (PseudoVFSQRT_V_MF2_E16:{ *:[nxv2f16] } (IMPLICIT_DEF:{ *:[nxv2f16] }), VR:{ *:[nxv2f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 125153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, |
| 125154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_MF2_E16), |
| 125158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125160 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125165 | GIR_RootConstrainSelectedInstOperands, |
| 125166 | // GIR_Coverage, 56881, |
| 125167 | GIR_EraseRootFromParent_Done, |
| 125168 | // Label 8632: @318340 |
| 125169 | GIM_Reject, |
| 125170 | // Label 8630: @318341 |
| 125171 | GIM_Reject, |
| 125172 | // Label 8593: @318342 |
| 125173 | GIM_Try, /*On fail goto*//*Label 8633*/ GIMT_Encode4(318451), |
| 125174 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, |
| 125175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125176 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125177 | GIM_Try, /*On fail goto*//*Label 8634*/ GIMT_Encode4(318404), // Rule ID 56940 // |
| 125178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 125179 | // (strict_fsqrt:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSQRT_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 125180 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 125181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E32), |
| 125185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125187 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125192 | GIR_RootConstrainSelectedInstOperands, |
| 125193 | // GIR_Coverage, 56940, |
| 125194 | GIR_EraseRootFromParent_Done, |
| 125195 | // Label 8634: @318404 |
| 125196 | GIM_Try, /*On fail goto*//*Label 8635*/ GIMT_Encode4(318450), // Rule ID 56941 // |
| 125197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 125198 | // (strict_fsqrt:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2) => (PseudoVFSQRT_V_M1_E32:{ *:[nxv2f32] } (IMPLICIT_DEF:{ *:[nxv2f32] }), VR:{ *:[nxv2f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 125199 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, |
| 125200 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125201 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E32), |
| 125204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125205 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125206 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125211 | GIR_RootConstrainSelectedInstOperands, |
| 125212 | // GIR_Coverage, 56941, |
| 125213 | GIR_EraseRootFromParent_Done, |
| 125214 | // Label 8635: @318450 |
| 125215 | GIM_Reject, |
| 125216 | // Label 8633: @318451 |
| 125217 | GIM_Reject, |
| 125218 | // Label 8594: @318452 |
| 125219 | GIM_Try, /*On fail goto*//*Label 8636*/ GIMT_Encode4(318561), |
| 125220 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, |
| 125221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 125222 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 125223 | GIM_Try, /*On fail goto*//*Label 8637*/ GIMT_Encode4(318514), // Rule ID 57100 // |
| 125224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 125225 | // (strict_fsqrt:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSQRT_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 125226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 125227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E64), |
| 125231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125232 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125233 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125238 | GIR_RootConstrainSelectedInstOperands, |
| 125239 | // GIR_Coverage, 57100, |
| 125240 | GIR_EraseRootFromParent_Done, |
| 125241 | // Label 8637: @318514 |
| 125242 | GIM_Try, /*On fail goto*//*Label 8638*/ GIMT_Encode4(318560), // Rule ID 57101 // |
| 125243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 125244 | // (strict_fsqrt:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2) => (PseudoVFSQRT_V_M2_E64:{ *:[nxv2f64] } (IMPLICIT_DEF:{ *:[nxv2f64] }), VRM2:{ *:[nxv2f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 125245 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, |
| 125246 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125247 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125248 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E64), |
| 125250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125251 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125252 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125257 | GIR_RootConstrainSelectedInstOperands, |
| 125258 | // GIR_Coverage, 57101, |
| 125259 | GIR_EraseRootFromParent_Done, |
| 125260 | // Label 8638: @318560 |
| 125261 | GIM_Reject, |
| 125262 | // Label 8636: @318561 |
| 125263 | GIM_Reject, |
| 125264 | // Label 8595: @318562 |
| 125265 | GIM_Try, /*On fail goto*//*Label 8639*/ GIMT_Encode4(318671), |
| 125266 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, |
| 125267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125268 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), |
| 125269 | GIM_Try, /*On fail goto*//*Label 8640*/ GIMT_Encode4(318624), // Rule ID 56920 // |
| 125270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 125271 | // (strict_fsqrt:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSQRT_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 125272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 125273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E16), |
| 125277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125278 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125279 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125284 | GIR_RootConstrainSelectedInstOperands, |
| 125285 | // GIR_Coverage, 56920, |
| 125286 | GIR_EraseRootFromParent_Done, |
| 125287 | // Label 8640: @318624 |
| 125288 | GIM_Try, /*On fail goto*//*Label 8641*/ GIMT_Encode4(318670), // Rule ID 56921 // |
| 125289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 125290 | // (strict_fsqrt:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2) => (PseudoVFSQRT_V_M1_E16:{ *:[nxv4f16] } (IMPLICIT_DEF:{ *:[nxv4f16] }), VR:{ *:[nxv4f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 125291 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, |
| 125292 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125293 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125294 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M1_E16), |
| 125296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125298 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125303 | GIR_RootConstrainSelectedInstOperands, |
| 125304 | // GIR_Coverage, 56921, |
| 125305 | GIR_EraseRootFromParent_Done, |
| 125306 | // Label 8641: @318670 |
| 125307 | GIM_Reject, |
| 125308 | // Label 8639: @318671 |
| 125309 | GIM_Reject, |
| 125310 | // Label 8596: @318672 |
| 125311 | GIM_Try, /*On fail goto*//*Label 8642*/ GIMT_Encode4(318781), |
| 125312 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, |
| 125313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 125314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 125315 | GIM_Try, /*On fail goto*//*Label 8643*/ GIMT_Encode4(318734), // Rule ID 57040 // |
| 125316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 125317 | // (strict_fsqrt:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSQRT_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 125318 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 125319 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125320 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E32), |
| 125323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125324 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125325 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125330 | GIR_RootConstrainSelectedInstOperands, |
| 125331 | // GIR_Coverage, 57040, |
| 125332 | GIR_EraseRootFromParent_Done, |
| 125333 | // Label 8643: @318734 |
| 125334 | GIM_Try, /*On fail goto*//*Label 8644*/ GIMT_Encode4(318780), // Rule ID 57041 // |
| 125335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 125336 | // (strict_fsqrt:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2) => (PseudoVFSQRT_V_M2_E32:{ *:[nxv4f32] } (IMPLICIT_DEF:{ *:[nxv4f32] }), VRM2:{ *:[nxv4f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 125337 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, |
| 125338 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125339 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E32), |
| 125342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125343 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125344 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125349 | GIR_RootConstrainSelectedInstOperands, |
| 125350 | // GIR_Coverage, 57041, |
| 125351 | GIR_EraseRootFromParent_Done, |
| 125352 | // Label 8644: @318780 |
| 125353 | GIM_Reject, |
| 125354 | // Label 8642: @318781 |
| 125355 | GIM_Reject, |
| 125356 | // Label 8597: @318782 |
| 125357 | GIM_Try, /*On fail goto*//*Label 8645*/ GIMT_Encode4(318891), |
| 125358 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, |
| 125359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 125360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 125361 | GIM_Try, /*On fail goto*//*Label 8646*/ GIMT_Encode4(318844), // Rule ID 57120 // |
| 125362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 125363 | // (strict_fsqrt:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSQRT_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 125364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 125365 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125366 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E64), |
| 125369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125371 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125376 | GIR_RootConstrainSelectedInstOperands, |
| 125377 | // GIR_Coverage, 57120, |
| 125378 | GIR_EraseRootFromParent_Done, |
| 125379 | // Label 8646: @318844 |
| 125380 | GIM_Try, /*On fail goto*//*Label 8647*/ GIMT_Encode4(318890), // Rule ID 57121 // |
| 125381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 125382 | // (strict_fsqrt:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2) => (PseudoVFSQRT_V_M4_E64:{ *:[nxv4f64] } (IMPLICIT_DEF:{ *:[nxv4f64] }), VRM4:{ *:[nxv4f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 125383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, |
| 125384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E64), |
| 125388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125389 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125390 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125395 | GIR_RootConstrainSelectedInstOperands, |
| 125396 | // GIR_Coverage, 57121, |
| 125397 | GIR_EraseRootFromParent_Done, |
| 125398 | // Label 8647: @318890 |
| 125399 | GIM_Reject, |
| 125400 | // Label 8645: @318891 |
| 125401 | GIM_Reject, |
| 125402 | // Label 8598: @318892 |
| 125403 | GIM_Try, /*On fail goto*//*Label 8648*/ GIMT_Encode4(319001), |
| 125404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, |
| 125405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 125406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), |
| 125407 | GIM_Try, /*On fail goto*//*Label 8649*/ GIMT_Encode4(318954), // Rule ID 56980 // |
| 125408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 125409 | // (strict_fsqrt:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSQRT_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 125410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 125411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E16), |
| 125415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125416 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125417 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125422 | GIR_RootConstrainSelectedInstOperands, |
| 125423 | // GIR_Coverage, 56980, |
| 125424 | GIR_EraseRootFromParent_Done, |
| 125425 | // Label 8649: @318954 |
| 125426 | GIM_Try, /*On fail goto*//*Label 8650*/ GIMT_Encode4(319000), // Rule ID 56981 // |
| 125427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 125428 | // (strict_fsqrt:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2) => (PseudoVFSQRT_V_M2_E16:{ *:[nxv8f16] } (IMPLICIT_DEF:{ *:[nxv8f16] }), VRM2:{ *:[nxv8f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 125429 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, |
| 125430 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125431 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M2_E16), |
| 125434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125435 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125436 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125441 | GIR_RootConstrainSelectedInstOperands, |
| 125442 | // GIR_Coverage, 56981, |
| 125443 | GIR_EraseRootFromParent_Done, |
| 125444 | // Label 8650: @319000 |
| 125445 | GIM_Reject, |
| 125446 | // Label 8648: @319001 |
| 125447 | GIM_Reject, |
| 125448 | // Label 8599: @319002 |
| 125449 | GIM_Try, /*On fail goto*//*Label 8651*/ GIMT_Encode4(319111), |
| 125450 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, |
| 125451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 125452 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 125453 | GIM_Try, /*On fail goto*//*Label 8652*/ GIMT_Encode4(319064), // Rule ID 57060 // |
| 125454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 125455 | // (strict_fsqrt:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSQRT_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 125456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 125457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E32), |
| 125461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125463 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125468 | GIR_RootConstrainSelectedInstOperands, |
| 125469 | // GIR_Coverage, 57060, |
| 125470 | GIR_EraseRootFromParent_Done, |
| 125471 | // Label 8652: @319064 |
| 125472 | GIM_Try, /*On fail goto*//*Label 8653*/ GIMT_Encode4(319110), // Rule ID 57061 // |
| 125473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 125474 | // (strict_fsqrt:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2) => (PseudoVFSQRT_V_M4_E32:{ *:[nxv8f32] } (IMPLICIT_DEF:{ *:[nxv8f32] }), VRM4:{ *:[nxv8f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 125475 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, |
| 125476 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125477 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125478 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E32), |
| 125480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125481 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125482 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125487 | GIR_RootConstrainSelectedInstOperands, |
| 125488 | // GIR_Coverage, 57061, |
| 125489 | GIR_EraseRootFromParent_Done, |
| 125490 | // Label 8653: @319110 |
| 125491 | GIM_Reject, |
| 125492 | // Label 8651: @319111 |
| 125493 | GIM_Reject, |
| 125494 | // Label 8600: @319112 |
| 125495 | GIM_Try, /*On fail goto*//*Label 8654*/ GIMT_Encode4(319221), |
| 125496 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, |
| 125497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 125498 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 125499 | GIM_Try, /*On fail goto*//*Label 8655*/ GIMT_Encode4(319174), // Rule ID 57140 // |
| 125500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode0), |
| 125501 | // (strict_fsqrt:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSQRT_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) |
| 125502 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 125503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125504 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E64), |
| 125507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125508 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125509 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125514 | GIR_RootConstrainSelectedInstOperands, |
| 125515 | // GIR_Coverage, 57140, |
| 125516 | GIR_EraseRootFromParent_Done, |
| 125517 | // Label 8655: @319174 |
| 125518 | GIM_Try, /*On fail goto*//*Label 8656*/ GIMT_Encode4(319220), // Rule ID 57141 // |
| 125519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF64_HwMode1), |
| 125520 | // (strict_fsqrt:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2) => (PseudoVFSQRT_V_M8_E64:{ *:[nxv8f64] } (IMPLICIT_DEF:{ *:[nxv8f64] }), VRM8:{ *:[nxv8f64] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) |
| 125521 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, |
| 125522 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125523 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E64), |
| 125526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125527 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125528 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/6, |
| 125532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125533 | GIR_RootConstrainSelectedInstOperands, |
| 125534 | // GIR_Coverage, 57141, |
| 125535 | GIR_EraseRootFromParent_Done, |
| 125536 | // Label 8656: @319220 |
| 125537 | GIM_Reject, |
| 125538 | // Label 8654: @319221 |
| 125539 | GIM_Reject, |
| 125540 | // Label 8601: @319222 |
| 125541 | GIM_Try, /*On fail goto*//*Label 8657*/ GIMT_Encode4(319331), |
| 125542 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, |
| 125543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 125544 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), |
| 125545 | GIM_Try, /*On fail goto*//*Label 8658*/ GIMT_Encode4(319284), // Rule ID 57000 // |
| 125546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 125547 | // (strict_fsqrt:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSQRT_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 125548 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 125549 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125550 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E16), |
| 125553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125555 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125560 | GIR_RootConstrainSelectedInstOperands, |
| 125561 | // GIR_Coverage, 57000, |
| 125562 | GIR_EraseRootFromParent_Done, |
| 125563 | // Label 8658: @319284 |
| 125564 | GIM_Try, /*On fail goto*//*Label 8659*/ GIMT_Encode4(319330), // Rule ID 57001 // |
| 125565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 125566 | // (strict_fsqrt:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2) => (PseudoVFSQRT_V_M4_E16:{ *:[nxv16f16] } (IMPLICIT_DEF:{ *:[nxv16f16] }), VRM4:{ *:[nxv16f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 125567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, |
| 125568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M4_E16), |
| 125572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125573 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125574 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125579 | GIR_RootConstrainSelectedInstOperands, |
| 125580 | // GIR_Coverage, 57001, |
| 125581 | GIR_EraseRootFromParent_Done, |
| 125582 | // Label 8659: @319330 |
| 125583 | GIM_Reject, |
| 125584 | // Label 8657: @319331 |
| 125585 | GIM_Reject, |
| 125586 | // Label 8602: @319332 |
| 125587 | GIM_Try, /*On fail goto*//*Label 8660*/ GIMT_Encode4(319441), |
| 125588 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, |
| 125589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 125590 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 125591 | GIM_Try, /*On fail goto*//*Label 8661*/ GIMT_Encode4(319394), // Rule ID 57080 // |
| 125592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode0), |
| 125593 | // (strict_fsqrt:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSQRT_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) |
| 125594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 125595 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125596 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E32), |
| 125599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125600 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125601 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125606 | GIR_RootConstrainSelectedInstOperands, |
| 125607 | // GIR_Coverage, 57080, |
| 125608 | GIR_EraseRootFromParent_Done, |
| 125609 | // Label 8661: @319394 |
| 125610 | GIM_Try, /*On fail goto*//*Label 8662*/ GIMT_Encode4(319440), // Rule ID 57081 // |
| 125611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsAnyF_HwMode1), |
| 125612 | // (strict_fsqrt:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2) => (PseudoVFSQRT_V_M8_E32:{ *:[nxv16f32] } (IMPLICIT_DEF:{ *:[nxv16f32] }), VRM8:{ *:[nxv16f32] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) |
| 125613 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, |
| 125614 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125615 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E32), |
| 125618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125619 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125620 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 125624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125625 | GIR_RootConstrainSelectedInstOperands, |
| 125626 | // GIR_Coverage, 57081, |
| 125627 | GIR_EraseRootFromParent_Done, |
| 125628 | // Label 8662: @319440 |
| 125629 | GIM_Reject, |
| 125630 | // Label 8660: @319441 |
| 125631 | GIM_Reject, |
| 125632 | // Label 8603: @319442 |
| 125633 | GIM_Try, /*On fail goto*//*Label 8663*/ GIMT_Encode4(319551), |
| 125634 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, |
| 125635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 125636 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), |
| 125637 | GIM_Try, /*On fail goto*//*Label 8664*/ GIMT_Encode4(319504), // Rule ID 57020 // |
| 125638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode0), |
| 125639 | // (strict_fsqrt:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSQRT_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i64] }, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) |
| 125640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 125641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E16), |
| 125645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125647 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125652 | GIR_RootConstrainSelectedInstOperands, |
| 125653 | // GIR_Coverage, 57020, |
| 125654 | GIR_EraseRootFromParent_Done, |
| 125655 | // Label 8664: @319504 |
| 125656 | GIM_Try, /*On fail goto*//*Label 8665*/ GIMT_Encode4(319550), // Rule ID 57021 // |
| 125657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsF16_HwMode1), |
| 125658 | // (strict_fsqrt:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2) => (PseudoVFSQRT_V_M8_E16:{ *:[nxv32f16] } (IMPLICIT_DEF:{ *:[nxv32f16] }), VRM8:{ *:[nxv32f16] }:$rs2, 7:{ *:[i32] }, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) |
| 125659 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, |
| 125660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 125661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 125662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 125663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVFSQRT_V_M8_E16), |
| 125664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 125665 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 125666 | GIR_RootToRootCopy, /*OpIdx*/1, // rs2 |
| 125667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 125668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 125669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 125670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 125671 | GIR_RootConstrainSelectedInstOperands, |
| 125672 | // GIR_Coverage, 57021, |
| 125673 | GIR_EraseRootFromParent_Done, |
| 125674 | // Label 8665: @319550 |
| 125675 | GIM_Reject, |
| 125676 | // Label 8663: @319551 |
| 125677 | GIM_Reject, |
| 125678 | // Label 8604: @319552 |
| 125679 | GIM_Reject, |
| 125680 | // Label 95: @319553 |
| 125681 | GIM_Try, /*On fail goto*//*Label 8666*/ GIMT_Encode4(319565), // Rule ID 272 // |
| 125682 | // (trap) => (UNIMP) |
| 125683 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::UNIMP), |
| 125684 | GIR_RootConstrainSelectedInstOperands, |
| 125685 | // GIR_Coverage, 272, |
| 125686 | GIR_Done, |
| 125687 | // Label 8666: @319565 |
| 125688 | GIM_Reject, |
| 125689 | // Label 96: @319566 |
| 125690 | GIM_Try, /*On fail goto*//*Label 8667*/ GIMT_Encode4(319578), // Rule ID 273 // |
| 125691 | // (debugtrap) => (EBREAK) |
| 125692 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::EBREAK), |
| 125693 | GIR_RootConstrainSelectedInstOperands, |
| 125694 | // GIR_Coverage, 273, |
| 125695 | GIR_Done, |
| 125696 | // Label 8667: @319578 |
| 125697 | GIM_Reject, |
| 125698 | // Label 97: @319579 |
| 125699 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 8670*/ GIMT_Encode4(319938), |
| 125700 | /*GILLT_s32*//*Label 8668*/ GIMT_Encode4(319598), |
| 125701 | /*GILLT_s64*//*Label 8669*/ GIMT_Encode4(319755), |
| 125702 | // Label 8668: @319598 |
| 125703 | GIM_Try, /*On fail goto*//*Label 8671*/ GIMT_Encode4(319624), // Rule ID 1361 // |
| 125704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode1), |
| 125705 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 125706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 125708 | // (riscv_fclass:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FCLASS_S:{ *:[i32] } ?:{ *:[f32] }:$rs1) |
| 125709 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_S), |
| 125710 | GIR_RootConstrainSelectedInstOperands, |
| 125711 | // GIR_Coverage, 1361, |
| 125712 | GIR_Done, |
| 125713 | // Label 8671: @319624 |
| 125714 | GIM_Try, /*On fail goto*//*Label 8672*/ GIMT_Encode4(319650), // Rule ID 1369 // |
| 125715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode1), |
| 125716 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 125717 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125718 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 125719 | // (riscv_fclass:{ *:[i32] } FPR32INX:{ *:[f32] }:$rs1) => (FCLASS_S_INX:{ *:[i32] } ?:{ *:[f32] }:$rs1) |
| 125720 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_S_INX), |
| 125721 | GIR_RootConstrainSelectedInstOperands, |
| 125722 | // GIR_Coverage, 1369, |
| 125723 | GIR_Done, |
| 125724 | // Label 8672: @319650 |
| 125725 | GIM_Try, /*On fail goto*//*Label 8673*/ GIMT_Encode4(319676), // Rule ID 1696 // |
| 125726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode1), |
| 125727 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 125728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125729 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 125730 | // (riscv_fclass:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCLASS_D:{ *:[i32] } ?:{ *:[f64] }:$rs1) |
| 125731 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_D), |
| 125732 | GIR_RootConstrainSelectedInstOperands, |
| 125733 | // GIR_Coverage, 1696, |
| 125734 | GIR_Done, |
| 125735 | // Label 8673: @319676 |
| 125736 | GIM_Try, /*On fail goto*//*Label 8674*/ GIMT_Encode4(319702), // Rule ID 1749 // |
| 125737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode1), |
| 125738 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 125739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 125741 | // (riscv_fclass:{ *:[i32] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCLASS_D_IN32X:{ *:[i32] } ?:{ *:[f64] }:$rs1) |
| 125742 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_D_IN32X), |
| 125743 | GIR_RootConstrainSelectedInstOperands, |
| 125744 | // GIR_Coverage, 1749, |
| 125745 | GIR_Done, |
| 125746 | // Label 8674: @319702 |
| 125747 | GIM_Try, /*On fail goto*//*Label 8675*/ GIMT_Encode4(319728), // Rule ID 2049 // |
| 125748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode1), |
| 125749 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 125750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 125752 | // (riscv_fclass:{ *:[i32] } FPR16:{ *:[f16] }:$rs1) => (FCLASS_H:{ *:[i32] } ?:{ *:[f16] }:$rs1) |
| 125753 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_H), |
| 125754 | GIR_RootConstrainSelectedInstOperands, |
| 125755 | // GIR_Coverage, 2049, |
| 125756 | GIR_Done, |
| 125757 | // Label 8675: @319728 |
| 125758 | GIM_Try, /*On fail goto*//*Label 8676*/ GIMT_Encode4(319754), // Rule ID 2081 // |
| 125759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode1), |
| 125760 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 125761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125762 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 125763 | // (riscv_fclass:{ *:[i32] } FPR16INX:{ *:[f16] }:$rs1) => (FCLASS_H_INX:{ *:[i32] } ?:{ *:[f16] }:$rs1) |
| 125764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_H_INX), |
| 125765 | GIR_RootConstrainSelectedInstOperands, |
| 125766 | // GIR_Coverage, 2081, |
| 125767 | GIR_Done, |
| 125768 | // Label 8676: @319754 |
| 125769 | GIM_Reject, |
| 125770 | // Label 8669: @319755 |
| 125771 | GIM_Try, /*On fail goto*//*Label 8677*/ GIMT_Encode4(319781), // Rule ID 1360 // |
| 125772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtF_HwMode0), |
| 125773 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 125774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR32RegClassID), |
| 125776 | // (riscv_fclass:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FCLASS_S:{ *:[i64] } ?:{ *:[f32] }:$rs1) |
| 125777 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_S), |
| 125778 | GIR_RootConstrainSelectedInstOperands, |
| 125779 | // GIR_Coverage, 1360, |
| 125780 | GIR_Done, |
| 125781 | // Label 8677: @319781 |
| 125782 | GIM_Try, /*On fail goto*//*Label 8678*/ GIMT_Encode4(319807), // Rule ID 1368 // |
| 125783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfinx_HwMode0), |
| 125784 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 125785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125786 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF32RegClassID), |
| 125787 | // (riscv_fclass:{ *:[i64] } FPR32INX:{ *:[f32] }:$rs1) => (FCLASS_S_INX:{ *:[i64] } ?:{ *:[f32] }:$rs1) |
| 125788 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_S_INX), |
| 125789 | GIR_RootConstrainSelectedInstOperands, |
| 125790 | // GIR_Coverage, 1368, |
| 125791 | GIR_Done, |
| 125792 | // Label 8678: @319807 |
| 125793 | GIM_Try, /*On fail goto*//*Label 8679*/ GIMT_Encode4(319833), // Rule ID 1695 // |
| 125794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtD_HwMode0), |
| 125795 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 125796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125797 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR64RegClassID), |
| 125798 | // (riscv_fclass:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCLASS_D:{ *:[i64] } ?:{ *:[f64] }:$rs1) |
| 125799 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_D), |
| 125800 | GIR_RootConstrainSelectedInstOperands, |
| 125801 | // GIR_Coverage, 1695, |
| 125802 | GIR_Done, |
| 125803 | // Label 8679: @319833 |
| 125804 | GIM_Try, /*On fail goto*//*Label 8680*/ GIMT_Encode4(319859), // Rule ID 1727 // |
| 125805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV64_HwMode0), |
| 125806 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 125807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125808 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125809 | // (riscv_fclass:{ *:[i64] } FPR64INX:{ *:[f64] }:$rs1) => (FCLASS_D_INX:{ *:[i64] } ?:{ *:[f64] }:$rs1) |
| 125810 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_D_INX), |
| 125811 | GIR_RootConstrainSelectedInstOperands, |
| 125812 | // GIR_Coverage, 1727, |
| 125813 | GIR_Done, |
| 125814 | // Label 8680: @319859 |
| 125815 | GIM_Try, /*On fail goto*//*Label 8681*/ GIMT_Encode4(319885), // Rule ID 1748 // |
| 125816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZdinx_IsRV32_HwMode0), |
| 125817 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 125818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRPairRegClassID), |
| 125820 | // (riscv_fclass:{ *:[i64] } FPR64IN32X:{ *:[f64] }:$rs1) => (FCLASS_D_IN32X:{ *:[i64] } ?:{ *:[f64] }:$rs1) |
| 125821 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_D_IN32X), |
| 125822 | GIR_RootConstrainSelectedInstOperands, |
| 125823 | // GIR_Coverage, 1748, |
| 125824 | GIR_Done, |
| 125825 | // Label 8681: @319885 |
| 125826 | GIM_Try, /*On fail goto*//*Label 8682*/ GIMT_Encode4(319911), // Rule ID 2048 // |
| 125827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZfh_HwMode0), |
| 125828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 125829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125830 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::FPR16RegClassID), |
| 125831 | // (riscv_fclass:{ *:[i64] } FPR16:{ *:[f16] }:$rs1) => (FCLASS_H:{ *:[i64] } ?:{ *:[f16] }:$rs1) |
| 125832 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_H), |
| 125833 | GIR_RootConstrainSelectedInstOperands, |
| 125834 | // GIR_Coverage, 2048, |
| 125835 | GIR_Done, |
| 125836 | // Label 8682: @319911 |
| 125837 | GIM_Try, /*On fail goto*//*Label 8683*/ GIMT_Encode4(319937), // Rule ID 2080 // |
| 125838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZhinx_HwMode0), |
| 125839 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 125840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRF16RegClassID), |
| 125842 | // (riscv_fclass:{ *:[i64] } FPR16INX:{ *:[f16] }:$rs1) => (FCLASS_H_INX:{ *:[i64] } ?:{ *:[f16] }:$rs1) |
| 125843 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::FCLASS_H_INX), |
| 125844 | GIR_RootConstrainSelectedInstOperands, |
| 125845 | // GIR_Coverage, 2080, |
| 125846 | GIR_Done, |
| 125847 | // Label 8683: @319937 |
| 125848 | GIM_Reject, |
| 125849 | // Label 8670: @319938 |
| 125850 | GIM_Reject, |
| 125851 | // Label 98: @319939 |
| 125852 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(5), /*)*//*default:*//*Label 8686*/ GIMT_Encode4(319998), |
| 125853 | /*GILLT_s32*//*Label 8684*/ GIMT_Encode4(319958), |
| 125854 | /*GILLT_s64*//*Label 8685*/ GIMT_Encode4(319978), |
| 125855 | // Label 8684: @319958 |
| 125856 | GIM_Try, /*On fail goto*//*Label 8687*/ GIMT_Encode4(319977), // Rule ID 61 // |
| 125857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), |
| 125858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125859 | // (riscv_read_vlenb:{ *:[i32] }) => (PseudoReadVLENB:{ *:[i32] }) |
| 125860 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::PseudoReadVLENB), |
| 125861 | GIR_RootConstrainSelectedInstOperands, |
| 125862 | // GIR_Coverage, 61, |
| 125863 | GIR_Done, |
| 125864 | // Label 8687: @319977 |
| 125865 | GIM_Reject, |
| 125866 | // Label 8685: @319978 |
| 125867 | GIM_Try, /*On fail goto*//*Label 8688*/ GIMT_Encode4(319997), // Rule ID 60 // |
| 125868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), |
| 125869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), |
| 125870 | // (riscv_read_vlenb:{ *:[i64] }) => (PseudoReadVLENB:{ *:[i64] }) |
| 125871 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::PseudoReadVLENB), |
| 125872 | GIR_RootConstrainSelectedInstOperands, |
| 125873 | // GIR_Coverage, 60, |
| 125874 | GIR_Done, |
| 125875 | // Label 8688: @319997 |
| 125876 | GIM_Reject, |
| 125877 | // Label 8686: @319998 |
| 125878 | GIM_Reject, |
| 125879 | // Label 99: @319999 |
| 125880 | GIM_Reject, |
| 125881 | }; // Size: 320000 bytes |
| 125882 | return MatchTable0; |
| 125883 | } |
| 125884 | #undef GIMT_Encode2 |
| 125885 | #undef GIMT_Encode4 |
| 125886 | #undef GIMT_Encode8 |
| 125887 | |
| 125888 | #endif // ifdef GET_GLOBALISEL_IMPL |
| 125889 | |
| 125890 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 125891 | PredicateBitset AvailableModuleFeatures; |
| 125892 | mutable PredicateBitset AvailableFunctionFeatures; |
| 125893 | PredicateBitset getAvailableFeatures() const { |
| 125894 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 125895 | } |
| 125896 | PredicateBitset |
| 125897 | computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const; |
| 125898 | PredicateBitset |
| 125899 | computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, |
| 125900 | const MachineFunction *MF) const; |
| 125901 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 125902 | #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 125903 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 125904 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 125905 | AvailableFunctionFeatures() |
| 125906 | #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 125907 |
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