1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(0),
782 UINT64_C(0),
783 UINT64_C(0),
784 UINT64_C(0),
785 UINT64_C(0),
786 UINT64_C(0),
787 UINT64_C(0),
788 UINT64_C(0),
789 UINT64_C(0),
790 UINT64_C(0),
791 UINT64_C(0),
792 UINT64_C(0),
793 UINT64_C(0),
794 UINT64_C(0),
795 UINT64_C(0),
796 UINT64_C(0),
797 UINT64_C(0),
798 UINT64_C(0),
799 UINT64_C(0),
800 UINT64_C(0),
801 UINT64_C(0),
802 UINT64_C(0),
803 UINT64_C(0),
804 UINT64_C(0),
805 UINT64_C(0),
806 UINT64_C(0),
807 UINT64_C(0),
808 UINT64_C(0),
809 UINT64_C(0),
810 UINT64_C(0),
811 UINT64_C(0),
812 UINT64_C(0),
813 UINT64_C(0),
814 UINT64_C(0),
815 UINT64_C(0),
816 UINT64_C(0),
817 UINT64_C(0),
818 UINT64_C(0),
819 UINT64_C(0),
820 UINT64_C(0),
821 UINT64_C(0),
822 UINT64_C(0),
823 UINT64_C(0),
824 UINT64_C(0),
825 UINT64_C(0),
826 UINT64_C(0),
827 UINT64_C(0),
828 UINT64_C(0),
829 UINT64_C(0),
830 UINT64_C(0),
831 UINT64_C(0),
832 UINT64_C(0),
833 UINT64_C(0),
834 UINT64_C(0),
835 UINT64_C(0),
836 UINT64_C(0),
837 UINT64_C(0),
838 UINT64_C(0),
839 UINT64_C(0),
840 UINT64_C(0),
841 UINT64_C(0),
842 UINT64_C(0),
843 UINT64_C(0),
844 UINT64_C(0),
845 UINT64_C(0),
846 UINT64_C(0),
847 UINT64_C(0),
848 UINT64_C(0),
849 UINT64_C(0),
850 UINT64_C(0),
851 UINT64_C(0),
852 UINT64_C(0),
853 UINT64_C(0),
854 UINT64_C(0),
855 UINT64_C(0),
856 UINT64_C(0),
857 UINT64_C(0),
858 UINT64_C(0),
859 UINT64_C(0),
860 UINT64_C(0),
861 UINT64_C(0),
862 UINT64_C(0),
863 UINT64_C(0),
864 UINT64_C(0),
865 UINT64_C(0),
866 UINT64_C(0),
867 UINT64_C(0),
868 UINT64_C(0),
869 UINT64_C(0),
870 UINT64_C(0),
871 UINT64_C(0),
872 UINT64_C(0),
873 UINT64_C(0),
874 UINT64_C(0),
875 UINT64_C(0),
876 UINT64_C(0),
877 UINT64_C(0),
878 UINT64_C(0),
879 UINT64_C(0),
880 UINT64_C(0),
881 UINT64_C(0),
882 UINT64_C(0),
883 UINT64_C(0),
884 UINT64_C(0),
885 UINT64_C(0),
886 UINT64_C(0),
887 UINT64_C(0),
888 UINT64_C(0),
889 UINT64_C(0),
890 UINT64_C(0),
891 UINT64_C(0),
892 UINT64_C(0),
893 UINT64_C(0),
894 UINT64_C(0),
895 UINT64_C(0),
896 UINT64_C(0),
897 UINT64_C(0),
898 UINT64_C(0),
899 UINT64_C(0),
900 UINT64_C(0),
901 UINT64_C(0),
902 UINT64_C(0),
903 UINT64_C(0),
904 UINT64_C(0),
905 UINT64_C(0),
906 UINT64_C(0),
907 UINT64_C(0),
908 UINT64_C(0),
909 UINT64_C(0),
910 UINT64_C(0),
911 UINT64_C(0),
912 UINT64_C(0),
913 UINT64_C(0),
914 UINT64_C(0),
915 UINT64_C(0),
916 UINT64_C(0),
917 UINT64_C(0),
918 UINT64_C(0),
919 UINT64_C(0),
920 UINT64_C(0),
921 UINT64_C(0),
922 UINT64_C(0),
923 UINT64_C(0),
924 UINT64_C(0),
925 UINT64_C(0),
926 UINT64_C(0),
927 UINT64_C(0),
928 UINT64_C(0),
929 UINT64_C(0),
930 UINT64_C(0),
931 UINT64_C(0),
932 UINT64_C(0),
933 UINT64_C(0),
934 UINT64_C(0),
935 UINT64_C(0),
936 UINT64_C(0),
937 UINT64_C(0),
938 UINT64_C(0),
939 UINT64_C(0),
940 UINT64_C(0),
941 UINT64_C(0),
942 UINT64_C(0),
943 UINT64_C(0),
944 UINT64_C(0),
945 UINT64_C(0),
946 UINT64_C(0),
947 UINT64_C(0),
948 UINT64_C(0),
949 UINT64_C(0),
950 UINT64_C(0),
951 UINT64_C(0),
952 UINT64_C(0),
953 UINT64_C(0),
954 UINT64_C(0),
955 UINT64_C(0),
956 UINT64_C(0),
957 UINT64_C(0),
958 UINT64_C(0),
959 UINT64_C(0),
960 UINT64_C(0),
961 UINT64_C(0),
962 UINT64_C(0),
963 UINT64_C(0),
964 UINT64_C(0),
965 UINT64_C(0),
966 UINT64_C(0),
967 UINT64_C(0),
968 UINT64_C(0),
969 UINT64_C(0),
970 UINT64_C(0),
971 UINT64_C(0),
972 UINT64_C(0),
973 UINT64_C(0),
974 UINT64_C(0),
975 UINT64_C(0),
976 UINT64_C(0),
977 UINT64_C(0),
978 UINT64_C(0),
979 UINT64_C(0),
980 UINT64_C(0),
981 UINT64_C(0),
982 UINT64_C(0),
983 UINT64_C(0),
984 UINT64_C(0),
985 UINT64_C(0),
986 UINT64_C(0),
987 UINT64_C(0),
988 UINT64_C(0),
989 UINT64_C(0),
990 UINT64_C(0),
991 UINT64_C(0),
992 UINT64_C(0),
993 UINT64_C(0),
994 UINT64_C(0),
995 UINT64_C(0),
996 UINT64_C(0),
997 UINT64_C(0),
998 UINT64_C(0),
999 UINT64_C(0),
1000 UINT64_C(0),
1001 UINT64_C(0),
1002 UINT64_C(0),
1003 UINT64_C(0),
1004 UINT64_C(0),
1005 UINT64_C(0),
1006 UINT64_C(0),
1007 UINT64_C(0),
1008 UINT64_C(0),
1009 UINT64_C(0),
1010 UINT64_C(0),
1011 UINT64_C(0),
1012 UINT64_C(0),
1013 UINT64_C(0),
1014 UINT64_C(0),
1015 UINT64_C(0),
1016 UINT64_C(0),
1017 UINT64_C(0),
1018 UINT64_C(0),
1019 UINT64_C(0),
1020 UINT64_C(0),
1021 UINT64_C(0),
1022 UINT64_C(0),
1023 UINT64_C(0),
1024 UINT64_C(0),
1025 UINT64_C(0),
1026 UINT64_C(0),
1027 UINT64_C(0),
1028 UINT64_C(0),
1029 UINT64_C(0),
1030 UINT64_C(0),
1031 UINT64_C(0),
1032 UINT64_C(0),
1033 UINT64_C(0),
1034 UINT64_C(0),
1035 UINT64_C(0),
1036 UINT64_C(0),
1037 UINT64_C(0),
1038 UINT64_C(0),
1039 UINT64_C(0),
1040 UINT64_C(0),
1041 UINT64_C(0),
1042 UINT64_C(0),
1043 UINT64_C(0),
1044 UINT64_C(0),
1045 UINT64_C(0),
1046 UINT64_C(0),
1047 UINT64_C(0),
1048 UINT64_C(0),
1049 UINT64_C(0),
1050 UINT64_C(0),
1051 UINT64_C(0),
1052 UINT64_C(0),
1053 UINT64_C(0),
1054 UINT64_C(0),
1055 UINT64_C(0),
1056 UINT64_C(0),
1057 UINT64_C(0),
1058 UINT64_C(0),
1059 UINT64_C(0),
1060 UINT64_C(0),
1061 UINT64_C(0),
1062 UINT64_C(0),
1063 UINT64_C(0),
1064 UINT64_C(0),
1065 UINT64_C(0),
1066 UINT64_C(0),
1067 UINT64_C(0),
1068 UINT64_C(0),
1069 UINT64_C(0),
1070 UINT64_C(0),
1071 UINT64_C(0),
1072 UINT64_C(0),
1073 UINT64_C(0),
1074 UINT64_C(0),
1075 UINT64_C(0),
1076 UINT64_C(0),
1077 UINT64_C(0),
1078 UINT64_C(0),
1079 UINT64_C(0),
1080 UINT64_C(0),
1081 UINT64_C(0),
1082 UINT64_C(0),
1083 UINT64_C(0),
1084 UINT64_C(0),
1085 UINT64_C(0),
1086 UINT64_C(0),
1087 UINT64_C(0),
1088 UINT64_C(0),
1089 UINT64_C(0),
1090 UINT64_C(0),
1091 UINT64_C(0),
1092 UINT64_C(0),
1093 UINT64_C(0),
1094 UINT64_C(0),
1095 UINT64_C(0),
1096 UINT64_C(0),
1097 UINT64_C(0),
1098 UINT64_C(0),
1099 UINT64_C(0),
1100 UINT64_C(0),
1101 UINT64_C(0),
1102 UINT64_C(0),
1103 UINT64_C(0),
1104 UINT64_C(0),
1105 UINT64_C(0),
1106 UINT64_C(0),
1107 UINT64_C(0),
1108 UINT64_C(0),
1109 UINT64_C(0),
1110 UINT64_C(0),
1111 UINT64_C(0),
1112 UINT64_C(0),
1113 UINT64_C(0),
1114 UINT64_C(0),
1115 UINT64_C(0),
1116 UINT64_C(0),
1117 UINT64_C(0),
1118 UINT64_C(0),
1119 UINT64_C(0),
1120 UINT64_C(0),
1121 UINT64_C(0),
1122 UINT64_C(0),
1123 UINT64_C(0),
1124 UINT64_C(0),
1125 UINT64_C(0),
1126 UINT64_C(0),
1127 UINT64_C(0),
1128 UINT64_C(0),
1129 UINT64_C(0),
1130 UINT64_C(0),
1131 UINT64_C(0),
1132 UINT64_C(0),
1133 UINT64_C(0),
1134 UINT64_C(0),
1135 UINT64_C(0),
1136 UINT64_C(0),
1137 UINT64_C(0),
1138 UINT64_C(0),
1139 UINT64_C(0),
1140 UINT64_C(0),
1141 UINT64_C(0),
1142 UINT64_C(0),
1143 UINT64_C(0),
1144 UINT64_C(0),
1145 UINT64_C(0),
1146 UINT64_C(0),
1147 UINT64_C(0),
1148 UINT64_C(0),
1149 UINT64_C(0),
1150 UINT64_C(0),
1151 UINT64_C(0),
1152 UINT64_C(0),
1153 UINT64_C(0),
1154 UINT64_C(0),
1155 UINT64_C(0),
1156 UINT64_C(0),
1157 UINT64_C(0),
1158 UINT64_C(0),
1159 UINT64_C(0),
1160 UINT64_C(0),
1161 UINT64_C(0),
1162 UINT64_C(0),
1163 UINT64_C(0),
1164 UINT64_C(0),
1165 UINT64_C(0),
1166 UINT64_C(0),
1167 UINT64_C(0),
1168 UINT64_C(0),
1169 UINT64_C(0),
1170 UINT64_C(0),
1171 UINT64_C(0),
1172 UINT64_C(0),
1173 UINT64_C(0),
1174 UINT64_C(0),
1175 UINT64_C(0),
1176 UINT64_C(0),
1177 UINT64_C(0),
1178 UINT64_C(0),
1179 UINT64_C(0),
1180 UINT64_C(0),
1181 UINT64_C(0),
1182 UINT64_C(0),
1183 UINT64_C(0),
1184 UINT64_C(0),
1185 UINT64_C(0),
1186 UINT64_C(0),
1187 UINT64_C(0),
1188 UINT64_C(0),
1189 UINT64_C(0),
1190 UINT64_C(0),
1191 UINT64_C(0),
1192 UINT64_C(0),
1193 UINT64_C(0),
1194 UINT64_C(0),
1195 UINT64_C(0),
1196 UINT64_C(0),
1197 UINT64_C(0),
1198 UINT64_C(0),
1199 UINT64_C(0),
1200 UINT64_C(0),
1201 UINT64_C(0),
1202 UINT64_C(0),
1203 UINT64_C(0),
1204 UINT64_C(0),
1205 UINT64_C(0),
1206 UINT64_C(0),
1207 UINT64_C(0),
1208 UINT64_C(0),
1209 UINT64_C(0),
1210 UINT64_C(0),
1211 UINT64_C(0),
1212 UINT64_C(0),
1213 UINT64_C(0),
1214 UINT64_C(0),
1215 UINT64_C(0),
1216 UINT64_C(0),
1217 UINT64_C(0),
1218 UINT64_C(0),
1219 UINT64_C(0),
1220 UINT64_C(0),
1221 UINT64_C(0),
1222 UINT64_C(0),
1223 UINT64_C(0),
1224 UINT64_C(0),
1225 UINT64_C(0),
1226 UINT64_C(0),
1227 UINT64_C(0),
1228 UINT64_C(0),
1229 UINT64_C(0),
1230 UINT64_C(0),
1231 UINT64_C(0),
1232 UINT64_C(0),
1233 UINT64_C(0),
1234 UINT64_C(0),
1235 UINT64_C(0),
1236 UINT64_C(0),
1237 UINT64_C(0),
1238 UINT64_C(0),
1239 UINT64_C(0),
1240 UINT64_C(0),
1241 UINT64_C(0),
1242 UINT64_C(0),
1243 UINT64_C(0),
1244 UINT64_C(0),
1245 UINT64_C(0),
1246 UINT64_C(0),
1247 UINT64_C(0),
1248 UINT64_C(0),
1249 UINT64_C(0),
1250 UINT64_C(0),
1251 UINT64_C(0),
1252 UINT64_C(0),
1253 UINT64_C(0),
1254 UINT64_C(0),
1255 UINT64_C(0),
1256 UINT64_C(0),
1257 UINT64_C(0),
1258 UINT64_C(0),
1259 UINT64_C(0),
1260 UINT64_C(0),
1261 UINT64_C(0),
1262 UINT64_C(0),
1263 UINT64_C(0),
1264 UINT64_C(0),
1265 UINT64_C(0),
1266 UINT64_C(0),
1267 UINT64_C(0),
1268 UINT64_C(0),
1269 UINT64_C(0),
1270 UINT64_C(0),
1271 UINT64_C(0),
1272 UINT64_C(0),
1273 UINT64_C(0),
1274 UINT64_C(0),
1275 UINT64_C(0),
1276 UINT64_C(0),
1277 UINT64_C(0),
1278 UINT64_C(0),
1279 UINT64_C(0),
1280 UINT64_C(0),
1281 UINT64_C(0),
1282 UINT64_C(0),
1283 UINT64_C(0),
1284 UINT64_C(0),
1285 UINT64_C(0),
1286 UINT64_C(0),
1287 UINT64_C(0),
1288 UINT64_C(0),
1289 UINT64_C(0),
1290 UINT64_C(0),
1291 UINT64_C(0),
1292 UINT64_C(0),
1293 UINT64_C(0),
1294 UINT64_C(0),
1295 UINT64_C(0),
1296 UINT64_C(0),
1297 UINT64_C(0),
1298 UINT64_C(0),
1299 UINT64_C(0),
1300 UINT64_C(0),
1301 UINT64_C(0),
1302 UINT64_C(0),
1303 UINT64_C(0),
1304 UINT64_C(0),
1305 UINT64_C(0),
1306 UINT64_C(0),
1307 UINT64_C(0),
1308 UINT64_C(0),
1309 UINT64_C(0),
1310 UINT64_C(0),
1311 UINT64_C(0),
1312 UINT64_C(0),
1313 UINT64_C(0),
1314 UINT64_C(0),
1315 UINT64_C(0),
1316 UINT64_C(0),
1317 UINT64_C(0),
1318 UINT64_C(0),
1319 UINT64_C(0),
1320 UINT64_C(0),
1321 UINT64_C(0),
1322 UINT64_C(0),
1323 UINT64_C(0),
1324 UINT64_C(0),
1325 UINT64_C(0),
1326 UINT64_C(0),
1327 UINT64_C(0),
1328 UINT64_C(0),
1329 UINT64_C(0),
1330 UINT64_C(0),
1331 UINT64_C(0),
1332 UINT64_C(0),
1333 UINT64_C(0),
1334 UINT64_C(0),
1335 UINT64_C(0),
1336 UINT64_C(0),
1337 UINT64_C(0),
1338 UINT64_C(0),
1339 UINT64_C(0),
1340 UINT64_C(0),
1341 UINT64_C(0),
1342 UINT64_C(0),
1343 UINT64_C(0),
1344 UINT64_C(0),
1345 UINT64_C(0),
1346 UINT64_C(0),
1347 UINT64_C(0),
1348 UINT64_C(0),
1349 UINT64_C(0),
1350 UINT64_C(0),
1351 UINT64_C(0),
1352 UINT64_C(0),
1353 UINT64_C(0),
1354 UINT64_C(0),
1355 UINT64_C(0),
1356 UINT64_C(0),
1357 UINT64_C(0),
1358 UINT64_C(0),
1359 UINT64_C(0),
1360 UINT64_C(0),
1361 UINT64_C(0),
1362 UINT64_C(0),
1363 UINT64_C(0),
1364 UINT64_C(0),
1365 UINT64_C(0),
1366 UINT64_C(0),
1367 UINT64_C(0),
1368 UINT64_C(0),
1369 UINT64_C(0),
1370 UINT64_C(0),
1371 UINT64_C(0),
1372 UINT64_C(0),
1373 UINT64_C(0),
1374 UINT64_C(0),
1375 UINT64_C(0),
1376 UINT64_C(0),
1377 UINT64_C(0),
1378 UINT64_C(0),
1379 UINT64_C(0),
1380 UINT64_C(0),
1381 UINT64_C(0),
1382 UINT64_C(0),
1383 UINT64_C(0),
1384 UINT64_C(0),
1385 UINT64_C(0),
1386 UINT64_C(0),
1387 UINT64_C(0),
1388 UINT64_C(0),
1389 UINT64_C(0),
1390 UINT64_C(0),
1391 UINT64_C(0),
1392 UINT64_C(0),
1393 UINT64_C(0),
1394 UINT64_C(0),
1395 UINT64_C(0),
1396 UINT64_C(0),
1397 UINT64_C(0),
1398 UINT64_C(0),
1399 UINT64_C(0),
1400 UINT64_C(0),
1401 UINT64_C(0),
1402 UINT64_C(0),
1403 UINT64_C(0),
1404 UINT64_C(0),
1405 UINT64_C(0),
1406 UINT64_C(0),
1407 UINT64_C(0),
1408 UINT64_C(0),
1409 UINT64_C(0),
1410 UINT64_C(0),
1411 UINT64_C(0),
1412 UINT64_C(0),
1413 UINT64_C(0),
1414 UINT64_C(0),
1415 UINT64_C(0),
1416 UINT64_C(0),
1417 UINT64_C(0),
1418 UINT64_C(0),
1419 UINT64_C(0),
1420 UINT64_C(0),
1421 UINT64_C(0),
1422 UINT64_C(0),
1423 UINT64_C(0),
1424 UINT64_C(0),
1425 UINT64_C(0),
1426 UINT64_C(0),
1427 UINT64_C(0),
1428 UINT64_C(0),
1429 UINT64_C(0),
1430 UINT64_C(0),
1431 UINT64_C(0),
1432 UINT64_C(0),
1433 UINT64_C(0),
1434 UINT64_C(0),
1435 UINT64_C(0),
1436 UINT64_C(0),
1437 UINT64_C(0),
1438 UINT64_C(0),
1439 UINT64_C(0),
1440 UINT64_C(0),
1441 UINT64_C(0),
1442 UINT64_C(0),
1443 UINT64_C(0),
1444 UINT64_C(0),
1445 UINT64_C(0),
1446 UINT64_C(0),
1447 UINT64_C(0),
1448 UINT64_C(0),
1449 UINT64_C(0),
1450 UINT64_C(0),
1451 UINT64_C(0),
1452 UINT64_C(0),
1453 UINT64_C(0),
1454 UINT64_C(0),
1455 UINT64_C(0),
1456 UINT64_C(0),
1457 UINT64_C(0),
1458 UINT64_C(0),
1459 UINT64_C(0),
1460 UINT64_C(0),
1461 UINT64_C(0),
1462 UINT64_C(0),
1463 UINT64_C(0),
1464 UINT64_C(0),
1465 UINT64_C(0),
1466 UINT64_C(0),
1467 UINT64_C(0),
1468 UINT64_C(0),
1469 UINT64_C(0),
1470 UINT64_C(0),
1471 UINT64_C(0),
1472 UINT64_C(0),
1473 UINT64_C(0),
1474 UINT64_C(0),
1475 UINT64_C(0),
1476 UINT64_C(0),
1477 UINT64_C(0),
1478 UINT64_C(0),
1479 UINT64_C(0),
1480 UINT64_C(0),
1481 UINT64_C(0),
1482 UINT64_C(0),
1483 UINT64_C(0),
1484 UINT64_C(0),
1485 UINT64_C(0),
1486 UINT64_C(0),
1487 UINT64_C(0),
1488 UINT64_C(0),
1489 UINT64_C(0),
1490 UINT64_C(0),
1491 UINT64_C(0),
1492 UINT64_C(0),
1493 UINT64_C(0),
1494 UINT64_C(0),
1495 UINT64_C(0),
1496 UINT64_C(0),
1497 UINT64_C(0),
1498 UINT64_C(0),
1499 UINT64_C(0),
1500 UINT64_C(0),
1501 UINT64_C(0),
1502 UINT64_C(0),
1503 UINT64_C(0),
1504 UINT64_C(0),
1505 UINT64_C(0),
1506 UINT64_C(0),
1507 UINT64_C(0),
1508 UINT64_C(0),
1509 UINT64_C(0),
1510 UINT64_C(0),
1511 UINT64_C(0),
1512 UINT64_C(0),
1513 UINT64_C(0),
1514 UINT64_C(0),
1515 UINT64_C(0),
1516 UINT64_C(0),
1517 UINT64_C(0),
1518 UINT64_C(0),
1519 UINT64_C(0),
1520 UINT64_C(0),
1521 UINT64_C(0),
1522 UINT64_C(0),
1523 UINT64_C(0),
1524 UINT64_C(0),
1525 UINT64_C(0),
1526 UINT64_C(0),
1527 UINT64_C(0),
1528 UINT64_C(0),
1529 UINT64_C(0),
1530 UINT64_C(0),
1531 UINT64_C(0),
1532 UINT64_C(0),
1533 UINT64_C(0),
1534 UINT64_C(0),
1535 UINT64_C(0),
1536 UINT64_C(0),
1537 UINT64_C(0),
1538 UINT64_C(0),
1539 UINT64_C(0),
1540 UINT64_C(0),
1541 UINT64_C(0),
1542 UINT64_C(0),
1543 UINT64_C(0),
1544 UINT64_C(0),
1545 UINT64_C(0),
1546 UINT64_C(0),
1547 UINT64_C(0),
1548 UINT64_C(0),
1549 UINT64_C(0),
1550 UINT64_C(0),
1551 UINT64_C(0),
1552 UINT64_C(0),
1553 UINT64_C(0),
1554 UINT64_C(0),
1555 UINT64_C(0),
1556 UINT64_C(0),
1557 UINT64_C(0),
1558 UINT64_C(0),
1559 UINT64_C(0),
1560 UINT64_C(0),
1561 UINT64_C(0),
1562 UINT64_C(0),
1563 UINT64_C(0),
1564 UINT64_C(0),
1565 UINT64_C(0),
1566 UINT64_C(0),
1567 UINT64_C(0),
1568 UINT64_C(0),
1569 UINT64_C(0),
1570 UINT64_C(0),
1571 UINT64_C(0),
1572 UINT64_C(0),
1573 UINT64_C(0),
1574 UINT64_C(0),
1575 UINT64_C(0),
1576 UINT64_C(0),
1577 UINT64_C(0),
1578 UINT64_C(0),
1579 UINT64_C(0),
1580 UINT64_C(0),
1581 UINT64_C(0),
1582 UINT64_C(0),
1583 UINT64_C(0),
1584 UINT64_C(0),
1585 UINT64_C(0),
1586 UINT64_C(0),
1587 UINT64_C(0),
1588 UINT64_C(0),
1589 UINT64_C(0),
1590 UINT64_C(0),
1591 UINT64_C(0),
1592 UINT64_C(0),
1593 UINT64_C(0),
1594 UINT64_C(0),
1595 UINT64_C(0),
1596 UINT64_C(0),
1597 UINT64_C(0),
1598 UINT64_C(0),
1599 UINT64_C(0),
1600 UINT64_C(0),
1601 UINT64_C(0),
1602 UINT64_C(0),
1603 UINT64_C(0),
1604 UINT64_C(0),
1605 UINT64_C(0),
1606 UINT64_C(0),
1607 UINT64_C(0),
1608 UINT64_C(0),
1609 UINT64_C(0),
1610 UINT64_C(0),
1611 UINT64_C(0),
1612 UINT64_C(0),
1613 UINT64_C(0),
1614 UINT64_C(0),
1615 UINT64_C(0),
1616 UINT64_C(0),
1617 UINT64_C(0),
1618 UINT64_C(0),
1619 UINT64_C(0),
1620 UINT64_C(0),
1621 UINT64_C(0),
1622 UINT64_C(0),
1623 UINT64_C(0),
1624 UINT64_C(0),
1625 UINT64_C(0),
1626 UINT64_C(0),
1627 UINT64_C(0),
1628 UINT64_C(0),
1629 UINT64_C(0),
1630 UINT64_C(0),
1631 UINT64_C(0),
1632 UINT64_C(0),
1633 UINT64_C(0),
1634 UINT64_C(0),
1635 UINT64_C(0),
1636 UINT64_C(0),
1637 UINT64_C(0),
1638 UINT64_C(0),
1639 UINT64_C(0),
1640 UINT64_C(0),
1641 UINT64_C(0),
1642 UINT64_C(0),
1643 UINT64_C(0),
1644 UINT64_C(0),
1645 UINT64_C(0),
1646 UINT64_C(0),
1647 UINT64_C(0),
1648 UINT64_C(0),
1649 UINT64_C(0),
1650 UINT64_C(0),
1651 UINT64_C(0),
1652 UINT64_C(0),
1653 UINT64_C(0),
1654 UINT64_C(0),
1655 UINT64_C(0),
1656 UINT64_C(0),
1657 UINT64_C(0),
1658 UINT64_C(0),
1659 UINT64_C(0),
1660 UINT64_C(0),
1661 UINT64_C(0),
1662 UINT64_C(0),
1663 UINT64_C(0),
1664 UINT64_C(0),
1665 UINT64_C(0),
1666 UINT64_C(0),
1667 UINT64_C(0),
1668 UINT64_C(0),
1669 UINT64_C(0),
1670 UINT64_C(0),
1671 UINT64_C(0),
1672 UINT64_C(0),
1673 UINT64_C(0),
1674 UINT64_C(0),
1675 UINT64_C(0),
1676 UINT64_C(0),
1677 UINT64_C(0),
1678 UINT64_C(0),
1679 UINT64_C(0),
1680 UINT64_C(0),
1681 UINT64_C(0),
1682 UINT64_C(0),
1683 UINT64_C(0),
1684 UINT64_C(0),
1685 UINT64_C(0),
1686 UINT64_C(0),
1687 UINT64_C(0),
1688 UINT64_C(0),
1689 UINT64_C(0),
1690 UINT64_C(0),
1691 UINT64_C(0),
1692 UINT64_C(0),
1693 UINT64_C(0),
1694 UINT64_C(0),
1695 UINT64_C(0),
1696 UINT64_C(0),
1697 UINT64_C(0),
1698 UINT64_C(0),
1699 UINT64_C(0),
1700 UINT64_C(0),
1701 UINT64_C(0),
1702 UINT64_C(0),
1703 UINT64_C(0),
1704 UINT64_C(0),
1705 UINT64_C(0),
1706 UINT64_C(0),
1707 UINT64_C(0),
1708 UINT64_C(0),
1709 UINT64_C(0),
1710 UINT64_C(0),
1711 UINT64_C(0),
1712 UINT64_C(0),
1713 UINT64_C(0),
1714 UINT64_C(0),
1715 UINT64_C(0),
1716 UINT64_C(0),
1717 UINT64_C(0),
1718 UINT64_C(0),
1719 UINT64_C(0),
1720 UINT64_C(0),
1721 UINT64_C(0),
1722 UINT64_C(0),
1723 UINT64_C(0),
1724 UINT64_C(0),
1725 UINT64_C(0),
1726 UINT64_C(0),
1727 UINT64_C(0),
1728 UINT64_C(0),
1729 UINT64_C(0),
1730 UINT64_C(0),
1731 UINT64_C(0),
1732 UINT64_C(0),
1733 UINT64_C(0),
1734 UINT64_C(0),
1735 UINT64_C(0),
1736 UINT64_C(0),
1737 UINT64_C(0),
1738 UINT64_C(0),
1739 UINT64_C(0),
1740 UINT64_C(0),
1741 UINT64_C(0),
1742 UINT64_C(0),
1743 UINT64_C(0),
1744 UINT64_C(0),
1745 UINT64_C(0),
1746 UINT64_C(0),
1747 UINT64_C(0),
1748 UINT64_C(0),
1749 UINT64_C(0),
1750 UINT64_C(0),
1751 UINT64_C(0),
1752 UINT64_C(0),
1753 UINT64_C(0),
1754 UINT64_C(0),
1755 UINT64_C(0),
1756 UINT64_C(0),
1757 UINT64_C(0),
1758 UINT64_C(0),
1759 UINT64_C(0),
1760 UINT64_C(0),
1761 UINT64_C(0),
1762 UINT64_C(0),
1763 UINT64_C(0),
1764 UINT64_C(0),
1765 UINT64_C(0),
1766 UINT64_C(0),
1767 UINT64_C(0),
1768 UINT64_C(0),
1769 UINT64_C(0),
1770 UINT64_C(0),
1771 UINT64_C(0),
1772 UINT64_C(0),
1773 UINT64_C(0),
1774 UINT64_C(0),
1775 UINT64_C(0),
1776 UINT64_C(0),
1777 UINT64_C(0),
1778 UINT64_C(0),
1779 UINT64_C(0),
1780 UINT64_C(0),
1781 UINT64_C(0),
1782 UINT64_C(0),
1783 UINT64_C(0),
1784 UINT64_C(0),
1785 UINT64_C(0),
1786 UINT64_C(0),
1787 UINT64_C(0),
1788 UINT64_C(0),
1789 UINT64_C(0),
1790 UINT64_C(0),
1791 UINT64_C(0),
1792 UINT64_C(0),
1793 UINT64_C(0),
1794 UINT64_C(0),
1795 UINT64_C(0),
1796 UINT64_C(0),
1797 UINT64_C(0),
1798 UINT64_C(0),
1799 UINT64_C(0),
1800 UINT64_C(0),
1801 UINT64_C(0),
1802 UINT64_C(0),
1803 UINT64_C(0),
1804 UINT64_C(0),
1805 UINT64_C(0),
1806 UINT64_C(0),
1807 UINT64_C(0),
1808 UINT64_C(0),
1809 UINT64_C(0),
1810 UINT64_C(0),
1811 UINT64_C(0),
1812 UINT64_C(0),
1813 UINT64_C(0),
1814 UINT64_C(0),
1815 UINT64_C(0),
1816 UINT64_C(0),
1817 UINT64_C(0),
1818 UINT64_C(0),
1819 UINT64_C(0),
1820 UINT64_C(0),
1821 UINT64_C(0),
1822 UINT64_C(0),
1823 UINT64_C(0),
1824 UINT64_C(0),
1825 UINT64_C(0),
1826 UINT64_C(0),
1827 UINT64_C(0),
1828 UINT64_C(0),
1829 UINT64_C(0),
1830 UINT64_C(0),
1831 UINT64_C(0),
1832 UINT64_C(0),
1833 UINT64_C(0),
1834 UINT64_C(0),
1835 UINT64_C(0),
1836 UINT64_C(0),
1837 UINT64_C(0),
1838 UINT64_C(0),
1839 UINT64_C(0),
1840 UINT64_C(0),
1841 UINT64_C(0),
1842 UINT64_C(0),
1843 UINT64_C(0),
1844 UINT64_C(0),
1845 UINT64_C(0),
1846 UINT64_C(0),
1847 UINT64_C(0),
1848 UINT64_C(0),
1849 UINT64_C(0),
1850 UINT64_C(0),
1851 UINT64_C(0),
1852 UINT64_C(0),
1853 UINT64_C(0),
1854 UINT64_C(0),
1855 UINT64_C(0),
1856 UINT64_C(0),
1857 UINT64_C(0),
1858 UINT64_C(0),
1859 UINT64_C(0),
1860 UINT64_C(0),
1861 UINT64_C(0),
1862 UINT64_C(0),
1863 UINT64_C(0),
1864 UINT64_C(0),
1865 UINT64_C(0),
1866 UINT64_C(0),
1867 UINT64_C(0),
1868 UINT64_C(0),
1869 UINT64_C(0),
1870 UINT64_C(0),
1871 UINT64_C(0),
1872 UINT64_C(0),
1873 UINT64_C(0),
1874 UINT64_C(0),
1875 UINT64_C(0),
1876 UINT64_C(0),
1877 UINT64_C(0),
1878 UINT64_C(0),
1879 UINT64_C(0),
1880 UINT64_C(0),
1881 UINT64_C(0),
1882 UINT64_C(0),
1883 UINT64_C(0),
1884 UINT64_C(0),
1885 UINT64_C(0),
1886 UINT64_C(0),
1887 UINT64_C(0),
1888 UINT64_C(0),
1889 UINT64_C(0),
1890 UINT64_C(0),
1891 UINT64_C(0),
1892 UINT64_C(0),
1893 UINT64_C(0),
1894 UINT64_C(0),
1895 UINT64_C(0),
1896 UINT64_C(0),
1897 UINT64_C(0),
1898 UINT64_C(0),
1899 UINT64_C(0),
1900 UINT64_C(0),
1901 UINT64_C(0),
1902 UINT64_C(0),
1903 UINT64_C(0),
1904 UINT64_C(0),
1905 UINT64_C(0),
1906 UINT64_C(0),
1907 UINT64_C(0),
1908 UINT64_C(0),
1909 UINT64_C(0),
1910 UINT64_C(0),
1911 UINT64_C(0),
1912 UINT64_C(0),
1913 UINT64_C(0),
1914 UINT64_C(0),
1915 UINT64_C(0),
1916 UINT64_C(0),
1917 UINT64_C(0),
1918 UINT64_C(0),
1919 UINT64_C(0),
1920 UINT64_C(0),
1921 UINT64_C(0),
1922 UINT64_C(0),
1923 UINT64_C(0),
1924 UINT64_C(0),
1925 UINT64_C(0),
1926 UINT64_C(0),
1927 UINT64_C(0),
1928 UINT64_C(0),
1929 UINT64_C(0),
1930 UINT64_C(0),
1931 UINT64_C(0),
1932 UINT64_C(0),
1933 UINT64_C(0),
1934 UINT64_C(0),
1935 UINT64_C(0),
1936 UINT64_C(0),
1937 UINT64_C(0),
1938 UINT64_C(0),
1939 UINT64_C(0),
1940 UINT64_C(0),
1941 UINT64_C(0),
1942 UINT64_C(0),
1943 UINT64_C(0),
1944 UINT64_C(0),
1945 UINT64_C(0),
1946 UINT64_C(0),
1947 UINT64_C(0),
1948 UINT64_C(0),
1949 UINT64_C(0),
1950 UINT64_C(0),
1951 UINT64_C(0),
1952 UINT64_C(0),
1953 UINT64_C(0),
1954 UINT64_C(0),
1955 UINT64_C(0),
1956 UINT64_C(0),
1957 UINT64_C(0),
1958 UINT64_C(0),
1959 UINT64_C(0),
1960 UINT64_C(0),
1961 UINT64_C(0),
1962 UINT64_C(0),
1963 UINT64_C(0),
1964 UINT64_C(0),
1965 UINT64_C(0),
1966 UINT64_C(0),
1967 UINT64_C(0),
1968 UINT64_C(0),
1969 UINT64_C(0),
1970 UINT64_C(0),
1971 UINT64_C(0),
1972 UINT64_C(0),
1973 UINT64_C(0),
1974 UINT64_C(0),
1975 UINT64_C(0),
1976 UINT64_C(0),
1977 UINT64_C(0),
1978 UINT64_C(0),
1979 UINT64_C(0),
1980 UINT64_C(0),
1981 UINT64_C(0),
1982 UINT64_C(0),
1983 UINT64_C(0),
1984 UINT64_C(0),
1985 UINT64_C(0),
1986 UINT64_C(0),
1987 UINT64_C(0),
1988 UINT64_C(0),
1989 UINT64_C(0),
1990 UINT64_C(0),
1991 UINT64_C(0),
1992 UINT64_C(0),
1993 UINT64_C(0),
1994 UINT64_C(0),
1995 UINT64_C(0),
1996 UINT64_C(0),
1997 UINT64_C(0),
1998 UINT64_C(0),
1999 UINT64_C(0),
2000 UINT64_C(0),
2001 UINT64_C(0),
2002 UINT64_C(0),
2003 UINT64_C(0),
2004 UINT64_C(0),
2005 UINT64_C(0),
2006 UINT64_C(0),
2007 UINT64_C(0),
2008 UINT64_C(0),
2009 UINT64_C(0),
2010 UINT64_C(0),
2011 UINT64_C(0),
2012 UINT64_C(0),
2013 UINT64_C(0),
2014 UINT64_C(0),
2015 UINT64_C(0),
2016 UINT64_C(0),
2017 UINT64_C(0),
2018 UINT64_C(0),
2019 UINT64_C(0),
2020 UINT64_C(0),
2021 UINT64_C(0),
2022 UINT64_C(0),
2023 UINT64_C(0),
2024 UINT64_C(0),
2025 UINT64_C(0),
2026 UINT64_C(0),
2027 UINT64_C(0),
2028 UINT64_C(0),
2029 UINT64_C(0),
2030 UINT64_C(0),
2031 UINT64_C(0),
2032 UINT64_C(0),
2033 UINT64_C(0),
2034 UINT64_C(0),
2035 UINT64_C(0),
2036 UINT64_C(0),
2037 UINT64_C(0),
2038 UINT64_C(0),
2039 UINT64_C(0),
2040 UINT64_C(0),
2041 UINT64_C(0),
2042 UINT64_C(0),
2043 UINT64_C(0),
2044 UINT64_C(0),
2045 UINT64_C(0),
2046 UINT64_C(0),
2047 UINT64_C(0),
2048 UINT64_C(0),
2049 UINT64_C(0),
2050 UINT64_C(0),
2051 UINT64_C(0),
2052 UINT64_C(0),
2053 UINT64_C(0),
2054 UINT64_C(0),
2055 UINT64_C(0),
2056 UINT64_C(0),
2057 UINT64_C(0),
2058 UINT64_C(0),
2059 UINT64_C(0),
2060 UINT64_C(0),
2061 UINT64_C(0),
2062 UINT64_C(0),
2063 UINT64_C(0),
2064 UINT64_C(0),
2065 UINT64_C(0),
2066 UINT64_C(0),
2067 UINT64_C(0),
2068 UINT64_C(0),
2069 UINT64_C(0),
2070 UINT64_C(0),
2071 UINT64_C(0),
2072 UINT64_C(0),
2073 UINT64_C(0),
2074 UINT64_C(0),
2075 UINT64_C(0),
2076 UINT64_C(0),
2077 UINT64_C(0),
2078 UINT64_C(0),
2079 UINT64_C(0),
2080 UINT64_C(0),
2081 UINT64_C(0),
2082 UINT64_C(0),
2083 UINT64_C(0),
2084 UINT64_C(0),
2085 UINT64_C(0),
2086 UINT64_C(0),
2087 UINT64_C(0),
2088 UINT64_C(0),
2089 UINT64_C(0),
2090 UINT64_C(0),
2091 UINT64_C(0),
2092 UINT64_C(0),
2093 UINT64_C(0),
2094 UINT64_C(0),
2095 UINT64_C(0),
2096 UINT64_C(0),
2097 UINT64_C(0),
2098 UINT64_C(0),
2099 UINT64_C(0),
2100 UINT64_C(0),
2101 UINT64_C(0),
2102 UINT64_C(0),
2103 UINT64_C(0),
2104 UINT64_C(0),
2105 UINT64_C(0),
2106 UINT64_C(0),
2107 UINT64_C(0),
2108 UINT64_C(0),
2109 UINT64_C(0),
2110 UINT64_C(0),
2111 UINT64_C(0),
2112 UINT64_C(0),
2113 UINT64_C(0),
2114 UINT64_C(0),
2115 UINT64_C(0),
2116 UINT64_C(0),
2117 UINT64_C(0),
2118 UINT64_C(0),
2119 UINT64_C(0),
2120 UINT64_C(0),
2121 UINT64_C(0),
2122 UINT64_C(0),
2123 UINT64_C(0),
2124 UINT64_C(0),
2125 UINT64_C(0),
2126 UINT64_C(0),
2127 UINT64_C(0),
2128 UINT64_C(0),
2129 UINT64_C(0),
2130 UINT64_C(0),
2131 UINT64_C(0),
2132 UINT64_C(0),
2133 UINT64_C(0),
2134 UINT64_C(0),
2135 UINT64_C(0),
2136 UINT64_C(0),
2137 UINT64_C(0),
2138 UINT64_C(0),
2139 UINT64_C(0),
2140 UINT64_C(0),
2141 UINT64_C(0),
2142 UINT64_C(0),
2143 UINT64_C(0),
2144 UINT64_C(0),
2145 UINT64_C(0),
2146 UINT64_C(0),
2147 UINT64_C(0),
2148 UINT64_C(0),
2149 UINT64_C(0),
2150 UINT64_C(0),
2151 UINT64_C(0),
2152 UINT64_C(0),
2153 UINT64_C(0),
2154 UINT64_C(0),
2155 UINT64_C(0),
2156 UINT64_C(0),
2157 UINT64_C(0),
2158 UINT64_C(0),
2159 UINT64_C(0),
2160 UINT64_C(0),
2161 UINT64_C(0),
2162 UINT64_C(0),
2163 UINT64_C(0),
2164 UINT64_C(0),
2165 UINT64_C(0),
2166 UINT64_C(0),
2167 UINT64_C(0),
2168 UINT64_C(0),
2169 UINT64_C(0),
2170 UINT64_C(0),
2171 UINT64_C(0),
2172 UINT64_C(0),
2173 UINT64_C(0),
2174 UINT64_C(0),
2175 UINT64_C(0),
2176 UINT64_C(0),
2177 UINT64_C(0),
2178 UINT64_C(0),
2179 UINT64_C(0),
2180 UINT64_C(0),
2181 UINT64_C(0),
2182 UINT64_C(0),
2183 UINT64_C(0),
2184 UINT64_C(0),
2185 UINT64_C(0),
2186 UINT64_C(0),
2187 UINT64_C(0),
2188 UINT64_C(0),
2189 UINT64_C(0),
2190 UINT64_C(0),
2191 UINT64_C(0),
2192 UINT64_C(0),
2193 UINT64_C(0),
2194 UINT64_C(0),
2195 UINT64_C(0),
2196 UINT64_C(0),
2197 UINT64_C(0),
2198 UINT64_C(0),
2199 UINT64_C(0),
2200 UINT64_C(0),
2201 UINT64_C(0),
2202 UINT64_C(0),
2203 UINT64_C(0),
2204 UINT64_C(0),
2205 UINT64_C(0),
2206 UINT64_C(0),
2207 UINT64_C(0),
2208 UINT64_C(0),
2209 UINT64_C(0),
2210 UINT64_C(0),
2211 UINT64_C(0),
2212 UINT64_C(0),
2213 UINT64_C(0),
2214 UINT64_C(0),
2215 UINT64_C(0),
2216 UINT64_C(0),
2217 UINT64_C(0),
2218 UINT64_C(0),
2219 UINT64_C(0),
2220 UINT64_C(0),
2221 UINT64_C(0),
2222 UINT64_C(0),
2223 UINT64_C(0),
2224 UINT64_C(0),
2225 UINT64_C(0),
2226 UINT64_C(0),
2227 UINT64_C(0),
2228 UINT64_C(0),
2229 UINT64_C(0),
2230 UINT64_C(0),
2231 UINT64_C(0),
2232 UINT64_C(0),
2233 UINT64_C(0),
2234 UINT64_C(0),
2235 UINT64_C(0),
2236 UINT64_C(0),
2237 UINT64_C(0),
2238 UINT64_C(0),
2239 UINT64_C(0),
2240 UINT64_C(0),
2241 UINT64_C(0),
2242 UINT64_C(0),
2243 UINT64_C(0),
2244 UINT64_C(0),
2245 UINT64_C(0),
2246 UINT64_C(0),
2247 UINT64_C(0),
2248 UINT64_C(0),
2249 UINT64_C(0),
2250 UINT64_C(0),
2251 UINT64_C(0),
2252 UINT64_C(0),
2253 UINT64_C(0),
2254 UINT64_C(0),
2255 UINT64_C(0),
2256 UINT64_C(0),
2257 UINT64_C(0),
2258 UINT64_C(0),
2259 UINT64_C(0),
2260 UINT64_C(0),
2261 UINT64_C(0),
2262 UINT64_C(0),
2263 UINT64_C(0),
2264 UINT64_C(0),
2265 UINT64_C(0),
2266 UINT64_C(0),
2267 UINT64_C(0),
2268 UINT64_C(0),
2269 UINT64_C(0),
2270 UINT64_C(0),
2271 UINT64_C(0),
2272 UINT64_C(0),
2273 UINT64_C(0),
2274 UINT64_C(0),
2275 UINT64_C(0),
2276 UINT64_C(0),
2277 UINT64_C(0),
2278 UINT64_C(0),
2279 UINT64_C(0),
2280 UINT64_C(0),
2281 UINT64_C(0),
2282 UINT64_C(0),
2283 UINT64_C(0),
2284 UINT64_C(0),
2285 UINT64_C(0),
2286 UINT64_C(0),
2287 UINT64_C(0),
2288 UINT64_C(0),
2289 UINT64_C(0),
2290 UINT64_C(0),
2291 UINT64_C(0),
2292 UINT64_C(0),
2293 UINT64_C(0),
2294 UINT64_C(0),
2295 UINT64_C(0),
2296 UINT64_C(0),
2297 UINT64_C(0),
2298 UINT64_C(0),
2299 UINT64_C(0),
2300 UINT64_C(0),
2301 UINT64_C(0),
2302 UINT64_C(0),
2303 UINT64_C(0),
2304 UINT64_C(0),
2305 UINT64_C(0),
2306 UINT64_C(0),
2307 UINT64_C(0),
2308 UINT64_C(0),
2309 UINT64_C(0),
2310 UINT64_C(0),
2311 UINT64_C(0),
2312 UINT64_C(0),
2313 UINT64_C(0),
2314 UINT64_C(0),
2315 UINT64_C(0),
2316 UINT64_C(0),
2317 UINT64_C(0),
2318 UINT64_C(0),
2319 UINT64_C(0),
2320 UINT64_C(0),
2321 UINT64_C(0),
2322 UINT64_C(0),
2323 UINT64_C(0),
2324 UINT64_C(0),
2325 UINT64_C(0),
2326 UINT64_C(0),
2327 UINT64_C(0),
2328 UINT64_C(0),
2329 UINT64_C(0),
2330 UINT64_C(0),
2331 UINT64_C(0),
2332 UINT64_C(0),
2333 UINT64_C(0),
2334 UINT64_C(0),
2335 UINT64_C(0),
2336 UINT64_C(0),
2337 UINT64_C(0),
2338 UINT64_C(0),
2339 UINT64_C(0),
2340 UINT64_C(0),
2341 UINT64_C(0),
2342 UINT64_C(0),
2343 UINT64_C(0),
2344 UINT64_C(0),
2345 UINT64_C(0),
2346 UINT64_C(0),
2347 UINT64_C(0),
2348 UINT64_C(0),
2349 UINT64_C(0),
2350 UINT64_C(0),
2351 UINT64_C(0),
2352 UINT64_C(0),
2353 UINT64_C(0),
2354 UINT64_C(0),
2355 UINT64_C(0),
2356 UINT64_C(0),
2357 UINT64_C(0),
2358 UINT64_C(0),
2359 UINT64_C(0),
2360 UINT64_C(0),
2361 UINT64_C(0),
2362 UINT64_C(0),
2363 UINT64_C(0),
2364 UINT64_C(0),
2365 UINT64_C(0),
2366 UINT64_C(0),
2367 UINT64_C(0),
2368 UINT64_C(0),
2369 UINT64_C(0),
2370 UINT64_C(0),
2371 UINT64_C(0),
2372 UINT64_C(0),
2373 UINT64_C(0),
2374 UINT64_C(0),
2375 UINT64_C(0),
2376 UINT64_C(0),
2377 UINT64_C(0),
2378 UINT64_C(0),
2379 UINT64_C(0),
2380 UINT64_C(0),
2381 UINT64_C(0),
2382 UINT64_C(0),
2383 UINT64_C(0),
2384 UINT64_C(0),
2385 UINT64_C(0),
2386 UINT64_C(0),
2387 UINT64_C(0),
2388 UINT64_C(0),
2389 UINT64_C(0),
2390 UINT64_C(0),
2391 UINT64_C(0),
2392 UINT64_C(0),
2393 UINT64_C(0),
2394 UINT64_C(0),
2395 UINT64_C(0),
2396 UINT64_C(0),
2397 UINT64_C(0),
2398 UINT64_C(0),
2399 UINT64_C(0),
2400 UINT64_C(0),
2401 UINT64_C(0),
2402 UINT64_C(0),
2403 UINT64_C(0),
2404 UINT64_C(0),
2405 UINT64_C(0),
2406 UINT64_C(0),
2407 UINT64_C(0),
2408 UINT64_C(0),
2409 UINT64_C(0),
2410 UINT64_C(0),
2411 UINT64_C(0),
2412 UINT64_C(0),
2413 UINT64_C(0),
2414 UINT64_C(0),
2415 UINT64_C(0),
2416 UINT64_C(0),
2417 UINT64_C(0),
2418 UINT64_C(0),
2419 UINT64_C(0),
2420 UINT64_C(0),
2421 UINT64_C(0),
2422 UINT64_C(0),
2423 UINT64_C(0),
2424 UINT64_C(0),
2425 UINT64_C(0),
2426 UINT64_C(0),
2427 UINT64_C(0),
2428 UINT64_C(0),
2429 UINT64_C(0),
2430 UINT64_C(0),
2431 UINT64_C(0),
2432 UINT64_C(0),
2433 UINT64_C(0),
2434 UINT64_C(0),
2435 UINT64_C(0),
2436 UINT64_C(0),
2437 UINT64_C(0),
2438 UINT64_C(0),
2439 UINT64_C(0),
2440 UINT64_C(0),
2441 UINT64_C(0),
2442 UINT64_C(0),
2443 UINT64_C(0),
2444 UINT64_C(0),
2445 UINT64_C(0),
2446 UINT64_C(0),
2447 UINT64_C(0),
2448 UINT64_C(0),
2449 UINT64_C(0),
2450 UINT64_C(0),
2451 UINT64_C(0),
2452 UINT64_C(0),
2453 UINT64_C(0),
2454 UINT64_C(0),
2455 UINT64_C(0),
2456 UINT64_C(0),
2457 UINT64_C(0),
2458 UINT64_C(0),
2459 UINT64_C(0),
2460 UINT64_C(0),
2461 UINT64_C(0),
2462 UINT64_C(0),
2463 UINT64_C(0),
2464 UINT64_C(0),
2465 UINT64_C(0),
2466 UINT64_C(0),
2467 UINT64_C(0),
2468 UINT64_C(0),
2469 UINT64_C(0),
2470 UINT64_C(0),
2471 UINT64_C(0),
2472 UINT64_C(0),
2473 UINT64_C(0),
2474 UINT64_C(0),
2475 UINT64_C(0),
2476 UINT64_C(0),
2477 UINT64_C(0),
2478 UINT64_C(0),
2479 UINT64_C(0),
2480 UINT64_C(0),
2481 UINT64_C(0),
2482 UINT64_C(0),
2483 UINT64_C(0),
2484 UINT64_C(0),
2485 UINT64_C(0),
2486 UINT64_C(0),
2487 UINT64_C(0),
2488 UINT64_C(0),
2489 UINT64_C(0),
2490 UINT64_C(0),
2491 UINT64_C(0),
2492 UINT64_C(0),
2493 UINT64_C(0),
2494 UINT64_C(0),
2495 UINT64_C(0),
2496 UINT64_C(0),
2497 UINT64_C(0),
2498 UINT64_C(0),
2499 UINT64_C(0),
2500 UINT64_C(0),
2501 UINT64_C(0),
2502 UINT64_C(0),
2503 UINT64_C(0),
2504 UINT64_C(0),
2505 UINT64_C(0),
2506 UINT64_C(0),
2507 UINT64_C(0),
2508 UINT64_C(0),
2509 UINT64_C(0),
2510 UINT64_C(0),
2511 UINT64_C(0),
2512 UINT64_C(0),
2513 UINT64_C(0),
2514 UINT64_C(0),
2515 UINT64_C(0),
2516 UINT64_C(0),
2517 UINT64_C(0),
2518 UINT64_C(0),
2519 UINT64_C(0),
2520 UINT64_C(0),
2521 UINT64_C(0),
2522 UINT64_C(0),
2523 UINT64_C(0),
2524 UINT64_C(0),
2525 UINT64_C(0),
2526 UINT64_C(0),
2527 UINT64_C(0),
2528 UINT64_C(0),
2529 UINT64_C(0),
2530 UINT64_C(0),
2531 UINT64_C(0),
2532 UINT64_C(0),
2533 UINT64_C(0),
2534 UINT64_C(0),
2535 UINT64_C(0),
2536 UINT64_C(0),
2537 UINT64_C(0),
2538 UINT64_C(0),
2539 UINT64_C(0),
2540 UINT64_C(0),
2541 UINT64_C(0),
2542 UINT64_C(0),
2543 UINT64_C(0),
2544 UINT64_C(0),
2545 UINT64_C(0),
2546 UINT64_C(0),
2547 UINT64_C(0),
2548 UINT64_C(0),
2549 UINT64_C(0),
2550 UINT64_C(0),
2551 UINT64_C(0),
2552 UINT64_C(0),
2553 UINT64_C(0),
2554 UINT64_C(0),
2555 UINT64_C(0),
2556 UINT64_C(0),
2557 UINT64_C(0),
2558 UINT64_C(0),
2559 UINT64_C(0),
2560 UINT64_C(0),
2561 UINT64_C(0),
2562 UINT64_C(0),
2563 UINT64_C(0),
2564 UINT64_C(0),
2565 UINT64_C(0),
2566 UINT64_C(0),
2567 UINT64_C(0),
2568 UINT64_C(0),
2569 UINT64_C(0),
2570 UINT64_C(0),
2571 UINT64_C(0),
2572 UINT64_C(0),
2573 UINT64_C(0),
2574 UINT64_C(0),
2575 UINT64_C(0),
2576 UINT64_C(0),
2577 UINT64_C(0),
2578 UINT64_C(0),
2579 UINT64_C(0),
2580 UINT64_C(0),
2581 UINT64_C(0),
2582 UINT64_C(0),
2583 UINT64_C(0),
2584 UINT64_C(0),
2585 UINT64_C(0),
2586 UINT64_C(0),
2587 UINT64_C(0),
2588 UINT64_C(0),
2589 UINT64_C(0),
2590 UINT64_C(0),
2591 UINT64_C(0),
2592 UINT64_C(0),
2593 UINT64_C(0),
2594 UINT64_C(0),
2595 UINT64_C(0),
2596 UINT64_C(0),
2597 UINT64_C(0),
2598 UINT64_C(0),
2599 UINT64_C(0),
2600 UINT64_C(0),
2601 UINT64_C(0),
2602 UINT64_C(0),
2603 UINT64_C(0),
2604 UINT64_C(0),
2605 UINT64_C(0),
2606 UINT64_C(0),
2607 UINT64_C(0),
2608 UINT64_C(0),
2609 UINT64_C(0),
2610 UINT64_C(0),
2611 UINT64_C(0),
2612 UINT64_C(0),
2613 UINT64_C(0),
2614 UINT64_C(0),
2615 UINT64_C(0),
2616 UINT64_C(0),
2617 UINT64_C(0),
2618 UINT64_C(0),
2619 UINT64_C(0),
2620 UINT64_C(0),
2621 UINT64_C(0),
2622 UINT64_C(0),
2623 UINT64_C(0),
2624 UINT64_C(0),
2625 UINT64_C(0),
2626 UINT64_C(0),
2627 UINT64_C(0),
2628 UINT64_C(0),
2629 UINT64_C(0),
2630 UINT64_C(0),
2631 UINT64_C(0),
2632 UINT64_C(0),
2633 UINT64_C(0),
2634 UINT64_C(0),
2635 UINT64_C(0),
2636 UINT64_C(0),
2637 UINT64_C(0),
2638 UINT64_C(0),
2639 UINT64_C(0),
2640 UINT64_C(0),
2641 UINT64_C(0),
2642 UINT64_C(0),
2643 UINT64_C(0),
2644 UINT64_C(0),
2645 UINT64_C(0),
2646 UINT64_C(0),
2647 UINT64_C(0),
2648 UINT64_C(0),
2649 UINT64_C(0),
2650 UINT64_C(0),
2651 UINT64_C(0),
2652 UINT64_C(0),
2653 UINT64_C(0),
2654 UINT64_C(0),
2655 UINT64_C(0),
2656 UINT64_C(0),
2657 UINT64_C(0),
2658 UINT64_C(0),
2659 UINT64_C(0),
2660 UINT64_C(0),
2661 UINT64_C(0),
2662 UINT64_C(0),
2663 UINT64_C(0),
2664 UINT64_C(0),
2665 UINT64_C(0),
2666 UINT64_C(0),
2667 UINT64_C(0),
2668 UINT64_C(0),
2669 UINT64_C(0),
2670 UINT64_C(0),
2671 UINT64_C(0),
2672 UINT64_C(0),
2673 UINT64_C(0),
2674 UINT64_C(0),
2675 UINT64_C(0),
2676 UINT64_C(0),
2677 UINT64_C(0),
2678 UINT64_C(0),
2679 UINT64_C(0),
2680 UINT64_C(0),
2681 UINT64_C(0),
2682 UINT64_C(0),
2683 UINT64_C(0),
2684 UINT64_C(0),
2685 UINT64_C(0),
2686 UINT64_C(0),
2687 UINT64_C(0),
2688 UINT64_C(0),
2689 UINT64_C(0),
2690 UINT64_C(0),
2691 UINT64_C(0),
2692 UINT64_C(0),
2693 UINT64_C(0),
2694 UINT64_C(0),
2695 UINT64_C(0),
2696 UINT64_C(0),
2697 UINT64_C(0),
2698 UINT64_C(0),
2699 UINT64_C(0),
2700 UINT64_C(0),
2701 UINT64_C(0),
2702 UINT64_C(0),
2703 UINT64_C(0),
2704 UINT64_C(0),
2705 UINT64_C(0),
2706 UINT64_C(0),
2707 UINT64_C(0),
2708 UINT64_C(0),
2709 UINT64_C(0),
2710 UINT64_C(0),
2711 UINT64_C(0),
2712 UINT64_C(0),
2713 UINT64_C(0),
2714 UINT64_C(0),
2715 UINT64_C(0),
2716 UINT64_C(0),
2717 UINT64_C(0),
2718 UINT64_C(0),
2719 UINT64_C(0),
2720 UINT64_C(0),
2721 UINT64_C(0),
2722 UINT64_C(0),
2723 UINT64_C(0),
2724 UINT64_C(0),
2725 UINT64_C(0),
2726 UINT64_C(0),
2727 UINT64_C(0),
2728 UINT64_C(0),
2729 UINT64_C(0),
2730 UINT64_C(0),
2731 UINT64_C(0),
2732 UINT64_C(0),
2733 UINT64_C(0),
2734 UINT64_C(0),
2735 UINT64_C(0),
2736 UINT64_C(0),
2737 UINT64_C(0),
2738 UINT64_C(0),
2739 UINT64_C(0),
2740 UINT64_C(0),
2741 UINT64_C(0),
2742 UINT64_C(0),
2743 UINT64_C(0),
2744 UINT64_C(0),
2745 UINT64_C(0),
2746 UINT64_C(0),
2747 UINT64_C(0),
2748 UINT64_C(0),
2749 UINT64_C(0),
2750 UINT64_C(0),
2751 UINT64_C(0),
2752 UINT64_C(0),
2753 UINT64_C(0),
2754 UINT64_C(0),
2755 UINT64_C(0),
2756 UINT64_C(0),
2757 UINT64_C(0),
2758 UINT64_C(0),
2759 UINT64_C(0),
2760 UINT64_C(0),
2761 UINT64_C(0),
2762 UINT64_C(0),
2763 UINT64_C(0),
2764 UINT64_C(0),
2765 UINT64_C(0),
2766 UINT64_C(0),
2767 UINT64_C(0),
2768 UINT64_C(0),
2769 UINT64_C(0),
2770 UINT64_C(0),
2771 UINT64_C(0),
2772 UINT64_C(0),
2773 UINT64_C(0),
2774 UINT64_C(0),
2775 UINT64_C(0),
2776 UINT64_C(0),
2777 UINT64_C(0),
2778 UINT64_C(0),
2779 UINT64_C(0),
2780 UINT64_C(0),
2781 UINT64_C(0),
2782 UINT64_C(0),
2783 UINT64_C(0),
2784 UINT64_C(0),
2785 UINT64_C(0),
2786 UINT64_C(0),
2787 UINT64_C(0),
2788 UINT64_C(0),
2789 UINT64_C(0),
2790 UINT64_C(0),
2791 UINT64_C(0),
2792 UINT64_C(0),
2793 UINT64_C(0),
2794 UINT64_C(0),
2795 UINT64_C(0),
2796 UINT64_C(0),
2797 UINT64_C(0),
2798 UINT64_C(0),
2799 UINT64_C(0),
2800 UINT64_C(0),
2801 UINT64_C(0),
2802 UINT64_C(0),
2803 UINT64_C(0),
2804 UINT64_C(0),
2805 UINT64_C(0),
2806 UINT64_C(0),
2807 UINT64_C(0),
2808 UINT64_C(0),
2809 UINT64_C(0),
2810 UINT64_C(0),
2811 UINT64_C(0),
2812 UINT64_C(0),
2813 UINT64_C(0),
2814 UINT64_C(0),
2815 UINT64_C(0),
2816 UINT64_C(0),
2817 UINT64_C(0),
2818 UINT64_C(0),
2819 UINT64_C(0),
2820 UINT64_C(0),
2821 UINT64_C(0),
2822 UINT64_C(0),
2823 UINT64_C(0),
2824 UINT64_C(0),
2825 UINT64_C(0),
2826 UINT64_C(0),
2827 UINT64_C(0),
2828 UINT64_C(0),
2829 UINT64_C(0),
2830 UINT64_C(0),
2831 UINT64_C(0),
2832 UINT64_C(0),
2833 UINT64_C(0),
2834 UINT64_C(0),
2835 UINT64_C(0),
2836 UINT64_C(0),
2837 UINT64_C(0),
2838 UINT64_C(0),
2839 UINT64_C(0),
2840 UINT64_C(0),
2841 UINT64_C(0),
2842 UINT64_C(0),
2843 UINT64_C(0),
2844 UINT64_C(0),
2845 UINT64_C(0),
2846 UINT64_C(0),
2847 UINT64_C(0),
2848 UINT64_C(0),
2849 UINT64_C(0),
2850 UINT64_C(0),
2851 UINT64_C(0),
2852 UINT64_C(0),
2853 UINT64_C(0),
2854 UINT64_C(0),
2855 UINT64_C(0),
2856 UINT64_C(0),
2857 UINT64_C(0),
2858 UINT64_C(0),
2859 UINT64_C(0),
2860 UINT64_C(0),
2861 UINT64_C(0),
2862 UINT64_C(0),
2863 UINT64_C(0),
2864 UINT64_C(0),
2865 UINT64_C(0),
2866 UINT64_C(0),
2867 UINT64_C(0),
2868 UINT64_C(0),
2869 UINT64_C(0),
2870 UINT64_C(0),
2871 UINT64_C(0),
2872 UINT64_C(0),
2873 UINT64_C(0),
2874 UINT64_C(0),
2875 UINT64_C(0),
2876 UINT64_C(0),
2877 UINT64_C(0),
2878 UINT64_C(0),
2879 UINT64_C(0),
2880 UINT64_C(0),
2881 UINT64_C(0),
2882 UINT64_C(0),
2883 UINT64_C(0),
2884 UINT64_C(0),
2885 UINT64_C(0),
2886 UINT64_C(0),
2887 UINT64_C(0),
2888 UINT64_C(0),
2889 UINT64_C(0),
2890 UINT64_C(0),
2891 UINT64_C(0),
2892 UINT64_C(0),
2893 UINT64_C(0),
2894 UINT64_C(0),
2895 UINT64_C(0),
2896 UINT64_C(0),
2897 UINT64_C(0),
2898 UINT64_C(0),
2899 UINT64_C(0),
2900 UINT64_C(0),
2901 UINT64_C(0),
2902 UINT64_C(0),
2903 UINT64_C(0),
2904 UINT64_C(0),
2905 UINT64_C(0),
2906 UINT64_C(0),
2907 UINT64_C(0),
2908 UINT64_C(0),
2909 UINT64_C(0),
2910 UINT64_C(0),
2911 UINT64_C(0),
2912 UINT64_C(0),
2913 UINT64_C(0),
2914 UINT64_C(0),
2915 UINT64_C(0),
2916 UINT64_C(0),
2917 UINT64_C(0),
2918 UINT64_C(0),
2919 UINT64_C(0),
2920 UINT64_C(0),
2921 UINT64_C(0),
2922 UINT64_C(0),
2923 UINT64_C(0),
2924 UINT64_C(0),
2925 UINT64_C(0),
2926 UINT64_C(0),
2927 UINT64_C(0),
2928 UINT64_C(0),
2929 UINT64_C(0),
2930 UINT64_C(0),
2931 UINT64_C(0),
2932 UINT64_C(0),
2933 UINT64_C(0),
2934 UINT64_C(0),
2935 UINT64_C(0),
2936 UINT64_C(0),
2937 UINT64_C(0),
2938 UINT64_C(0),
2939 UINT64_C(0),
2940 UINT64_C(0),
2941 UINT64_C(0),
2942 UINT64_C(0),
2943 UINT64_C(0),
2944 UINT64_C(0),
2945 UINT64_C(0),
2946 UINT64_C(0),
2947 UINT64_C(0),
2948 UINT64_C(0),
2949 UINT64_C(0),
2950 UINT64_C(0),
2951 UINT64_C(0),
2952 UINT64_C(0),
2953 UINT64_C(0),
2954 UINT64_C(0),
2955 UINT64_C(0),
2956 UINT64_C(0),
2957 UINT64_C(0),
2958 UINT64_C(0),
2959 UINT64_C(0),
2960 UINT64_C(0),
2961 UINT64_C(0),
2962 UINT64_C(0),
2963 UINT64_C(0),
2964 UINT64_C(0),
2965 UINT64_C(0),
2966 UINT64_C(0),
2967 UINT64_C(0),
2968 UINT64_C(0),
2969 UINT64_C(0),
2970 UINT64_C(0),
2971 UINT64_C(0),
2972 UINT64_C(0),
2973 UINT64_C(0),
2974 UINT64_C(0),
2975 UINT64_C(0),
2976 UINT64_C(0),
2977 UINT64_C(0),
2978 UINT64_C(0),
2979 UINT64_C(0),
2980 UINT64_C(0),
2981 UINT64_C(0),
2982 UINT64_C(0),
2983 UINT64_C(0),
2984 UINT64_C(0),
2985 UINT64_C(0),
2986 UINT64_C(0),
2987 UINT64_C(0),
2988 UINT64_C(0),
2989 UINT64_C(0),
2990 UINT64_C(0),
2991 UINT64_C(0),
2992 UINT64_C(0),
2993 UINT64_C(0),
2994 UINT64_C(0),
2995 UINT64_C(0),
2996 UINT64_C(0),
2997 UINT64_C(0),
2998 UINT64_C(0),
2999 UINT64_C(0),
3000 UINT64_C(0),
3001 UINT64_C(0),
3002 UINT64_C(0),
3003 UINT64_C(0),
3004 UINT64_C(0),
3005 UINT64_C(0),
3006 UINT64_C(0),
3007 UINT64_C(0),
3008 UINT64_C(0),
3009 UINT64_C(0),
3010 UINT64_C(0),
3011 UINT64_C(0),
3012 UINT64_C(0),
3013 UINT64_C(0),
3014 UINT64_C(0),
3015 UINT64_C(0),
3016 UINT64_C(0),
3017 UINT64_C(0),
3018 UINT64_C(0),
3019 UINT64_C(0),
3020 UINT64_C(0),
3021 UINT64_C(0),
3022 UINT64_C(0),
3023 UINT64_C(0),
3024 UINT64_C(0),
3025 UINT64_C(0),
3026 UINT64_C(0),
3027 UINT64_C(0),
3028 UINT64_C(0),
3029 UINT64_C(0),
3030 UINT64_C(0),
3031 UINT64_C(0),
3032 UINT64_C(0),
3033 UINT64_C(0),
3034 UINT64_C(0),
3035 UINT64_C(0),
3036 UINT64_C(0),
3037 UINT64_C(0),
3038 UINT64_C(0),
3039 UINT64_C(0),
3040 UINT64_C(0),
3041 UINT64_C(0),
3042 UINT64_C(0),
3043 UINT64_C(0),
3044 UINT64_C(0),
3045 UINT64_C(0),
3046 UINT64_C(0),
3047 UINT64_C(0),
3048 UINT64_C(0),
3049 UINT64_C(0),
3050 UINT64_C(0),
3051 UINT64_C(0),
3052 UINT64_C(0),
3053 UINT64_C(0),
3054 UINT64_C(0),
3055 UINT64_C(0),
3056 UINT64_C(0),
3057 UINT64_C(0),
3058 UINT64_C(0),
3059 UINT64_C(0),
3060 UINT64_C(0),
3061 UINT64_C(0),
3062 UINT64_C(0),
3063 UINT64_C(0),
3064 UINT64_C(0),
3065 UINT64_C(0),
3066 UINT64_C(0),
3067 UINT64_C(0),
3068 UINT64_C(0),
3069 UINT64_C(0),
3070 UINT64_C(0),
3071 UINT64_C(0),
3072 UINT64_C(0),
3073 UINT64_C(0),
3074 UINT64_C(0),
3075 UINT64_C(0),
3076 UINT64_C(0),
3077 UINT64_C(0),
3078 UINT64_C(0),
3079 UINT64_C(0),
3080 UINT64_C(0),
3081 UINT64_C(0),
3082 UINT64_C(0),
3083 UINT64_C(0),
3084 UINT64_C(0),
3085 UINT64_C(0),
3086 UINT64_C(0),
3087 UINT64_C(0),
3088 UINT64_C(0),
3089 UINT64_C(0),
3090 UINT64_C(0),
3091 UINT64_C(0),
3092 UINT64_C(0),
3093 UINT64_C(0),
3094 UINT64_C(0),
3095 UINT64_C(0),
3096 UINT64_C(0),
3097 UINT64_C(0),
3098 UINT64_C(0),
3099 UINT64_C(0),
3100 UINT64_C(0),
3101 UINT64_C(0),
3102 UINT64_C(0),
3103 UINT64_C(0),
3104 UINT64_C(0),
3105 UINT64_C(0),
3106 UINT64_C(0),
3107 UINT64_C(0),
3108 UINT64_C(0),
3109 UINT64_C(0),
3110 UINT64_C(0),
3111 UINT64_C(0),
3112 UINT64_C(0),
3113 UINT64_C(0),
3114 UINT64_C(0),
3115 UINT64_C(0),
3116 UINT64_C(0),
3117 UINT64_C(0),
3118 UINT64_C(0),
3119 UINT64_C(0),
3120 UINT64_C(0),
3121 UINT64_C(0),
3122 UINT64_C(0),
3123 UINT64_C(0),
3124 UINT64_C(0),
3125 UINT64_C(0),
3126 UINT64_C(0),
3127 UINT64_C(0),
3128 UINT64_C(0),
3129 UINT64_C(0),
3130 UINT64_C(0),
3131 UINT64_C(0),
3132 UINT64_C(0),
3133 UINT64_C(0),
3134 UINT64_C(0),
3135 UINT64_C(0),
3136 UINT64_C(0),
3137 UINT64_C(0),
3138 UINT64_C(0),
3139 UINT64_C(0),
3140 UINT64_C(0),
3141 UINT64_C(0),
3142 UINT64_C(0),
3143 UINT64_C(0),
3144 UINT64_C(0),
3145 UINT64_C(0),
3146 UINT64_C(0),
3147 UINT64_C(0),
3148 UINT64_C(0),
3149 UINT64_C(0),
3150 UINT64_C(0),
3151 UINT64_C(0),
3152 UINT64_C(0),
3153 UINT64_C(0),
3154 UINT64_C(0),
3155 UINT64_C(0),
3156 UINT64_C(0),
3157 UINT64_C(0),
3158 UINT64_C(0),
3159 UINT64_C(0),
3160 UINT64_C(0),
3161 UINT64_C(0),
3162 UINT64_C(0),
3163 UINT64_C(0),
3164 UINT64_C(0),
3165 UINT64_C(0),
3166 UINT64_C(0),
3167 UINT64_C(0),
3168 UINT64_C(0),
3169 UINT64_C(0),
3170 UINT64_C(0),
3171 UINT64_C(0),
3172 UINT64_C(0),
3173 UINT64_C(0),
3174 UINT64_C(0),
3175 UINT64_C(0),
3176 UINT64_C(0),
3177 UINT64_C(0),
3178 UINT64_C(0),
3179 UINT64_C(0),
3180 UINT64_C(0),
3181 UINT64_C(0),
3182 UINT64_C(0),
3183 UINT64_C(0),
3184 UINT64_C(0),
3185 UINT64_C(0),
3186 UINT64_C(0),
3187 UINT64_C(0),
3188 UINT64_C(0),
3189 UINT64_C(0),
3190 UINT64_C(0),
3191 UINT64_C(0),
3192 UINT64_C(0),
3193 UINT64_C(0),
3194 UINT64_C(0),
3195 UINT64_C(0),
3196 UINT64_C(0),
3197 UINT64_C(0),
3198 UINT64_C(0),
3199 UINT64_C(0),
3200 UINT64_C(0),
3201 UINT64_C(0),
3202 UINT64_C(0),
3203 UINT64_C(0),
3204 UINT64_C(0),
3205 UINT64_C(0),
3206 UINT64_C(0),
3207 UINT64_C(0),
3208 UINT64_C(0),
3209 UINT64_C(0),
3210 UINT64_C(0),
3211 UINT64_C(0),
3212 UINT64_C(0),
3213 UINT64_C(0),
3214 UINT64_C(0),
3215 UINT64_C(0),
3216 UINT64_C(0),
3217 UINT64_C(0),
3218 UINT64_C(0),
3219 UINT64_C(0),
3220 UINT64_C(0),
3221 UINT64_C(0),
3222 UINT64_C(0),
3223 UINT64_C(0),
3224 UINT64_C(0),
3225 UINT64_C(0),
3226 UINT64_C(0),
3227 UINT64_C(0),
3228 UINT64_C(0),
3229 UINT64_C(0),
3230 UINT64_C(0),
3231 UINT64_C(0),
3232 UINT64_C(0),
3233 UINT64_C(0),
3234 UINT64_C(0),
3235 UINT64_C(0),
3236 UINT64_C(0),
3237 UINT64_C(0),
3238 UINT64_C(0),
3239 UINT64_C(0),
3240 UINT64_C(0),
3241 UINT64_C(0),
3242 UINT64_C(0),
3243 UINT64_C(0),
3244 UINT64_C(0),
3245 UINT64_C(0),
3246 UINT64_C(0),
3247 UINT64_C(0),
3248 UINT64_C(0),
3249 UINT64_C(0),
3250 UINT64_C(0),
3251 UINT64_C(0),
3252 UINT64_C(0),
3253 UINT64_C(0),
3254 UINT64_C(0),
3255 UINT64_C(0),
3256 UINT64_C(0),
3257 UINT64_C(0),
3258 UINT64_C(0),
3259 UINT64_C(0),
3260 UINT64_C(0),
3261 UINT64_C(0),
3262 UINT64_C(0),
3263 UINT64_C(0),
3264 UINT64_C(0),
3265 UINT64_C(0),
3266 UINT64_C(0),
3267 UINT64_C(0),
3268 UINT64_C(0),
3269 UINT64_C(0),
3270 UINT64_C(0),
3271 UINT64_C(0),
3272 UINT64_C(0),
3273 UINT64_C(0),
3274 UINT64_C(0),
3275 UINT64_C(0),
3276 UINT64_C(0),
3277 UINT64_C(0),
3278 UINT64_C(0),
3279 UINT64_C(0),
3280 UINT64_C(0),
3281 UINT64_C(0),
3282 UINT64_C(0),
3283 UINT64_C(0),
3284 UINT64_C(0),
3285 UINT64_C(0),
3286 UINT64_C(0),
3287 UINT64_C(0),
3288 UINT64_C(0),
3289 UINT64_C(0),
3290 UINT64_C(0),
3291 UINT64_C(0),
3292 UINT64_C(0),
3293 UINT64_C(0),
3294 UINT64_C(0),
3295 UINT64_C(0),
3296 UINT64_C(0),
3297 UINT64_C(0),
3298 UINT64_C(0),
3299 UINT64_C(0),
3300 UINT64_C(0),
3301 UINT64_C(0),
3302 UINT64_C(0),
3303 UINT64_C(0),
3304 UINT64_C(0),
3305 UINT64_C(0),
3306 UINT64_C(0),
3307 UINT64_C(0),
3308 UINT64_C(0),
3309 UINT64_C(0),
3310 UINT64_C(0),
3311 UINT64_C(0),
3312 UINT64_C(0),
3313 UINT64_C(0),
3314 UINT64_C(0),
3315 UINT64_C(0),
3316 UINT64_C(0),
3317 UINT64_C(0),
3318 UINT64_C(0),
3319 UINT64_C(0),
3320 UINT64_C(0),
3321 UINT64_C(0),
3322 UINT64_C(0),
3323 UINT64_C(0),
3324 UINT64_C(0),
3325 UINT64_C(0),
3326 UINT64_C(0),
3327 UINT64_C(0),
3328 UINT64_C(0),
3329 UINT64_C(0),
3330 UINT64_C(0),
3331 UINT64_C(0),
3332 UINT64_C(0),
3333 UINT64_C(0),
3334 UINT64_C(0),
3335 UINT64_C(0),
3336 UINT64_C(0),
3337 UINT64_C(0),
3338 UINT64_C(0),
3339 UINT64_C(0),
3340 UINT64_C(0),
3341 UINT64_C(0),
3342 UINT64_C(0),
3343 UINT64_C(0),
3344 UINT64_C(0),
3345 UINT64_C(0),
3346 UINT64_C(0),
3347 UINT64_C(0),
3348 UINT64_C(0),
3349 UINT64_C(0),
3350 UINT64_C(0),
3351 UINT64_C(0),
3352 UINT64_C(0),
3353 UINT64_C(0),
3354 UINT64_C(0),
3355 UINT64_C(0),
3356 UINT64_C(0),
3357 UINT64_C(0),
3358 UINT64_C(0),
3359 UINT64_C(0),
3360 UINT64_C(0),
3361 UINT64_C(0),
3362 UINT64_C(0),
3363 UINT64_C(0),
3364 UINT64_C(0),
3365 UINT64_C(0),
3366 UINT64_C(0),
3367 UINT64_C(0),
3368 UINT64_C(0),
3369 UINT64_C(0),
3370 UINT64_C(0),
3371 UINT64_C(0),
3372 UINT64_C(0),
3373 UINT64_C(0),
3374 UINT64_C(0),
3375 UINT64_C(0),
3376 UINT64_C(0),
3377 UINT64_C(0),
3378 UINT64_C(0),
3379 UINT64_C(0),
3380 UINT64_C(0),
3381 UINT64_C(0),
3382 UINT64_C(0),
3383 UINT64_C(0),
3384 UINT64_C(0),
3385 UINT64_C(0),
3386 UINT64_C(0),
3387 UINT64_C(0),
3388 UINT64_C(0),
3389 UINT64_C(0),
3390 UINT64_C(0),
3391 UINT64_C(0),
3392 UINT64_C(0),
3393 UINT64_C(0),
3394 UINT64_C(0),
3395 UINT64_C(0),
3396 UINT64_C(0),
3397 UINT64_C(0),
3398 UINT64_C(0),
3399 UINT64_C(0),
3400 UINT64_C(0),
3401 UINT64_C(0),
3402 UINT64_C(0),
3403 UINT64_C(0),
3404 UINT64_C(0),
3405 UINT64_C(0),
3406 UINT64_C(0),
3407 UINT64_C(0),
3408 UINT64_C(0),
3409 UINT64_C(0),
3410 UINT64_C(0),
3411 UINT64_C(0),
3412 UINT64_C(0),
3413 UINT64_C(0),
3414 UINT64_C(0),
3415 UINT64_C(0),
3416 UINT64_C(0),
3417 UINT64_C(0),
3418 UINT64_C(0),
3419 UINT64_C(0),
3420 UINT64_C(0),
3421 UINT64_C(0),
3422 UINT64_C(0),
3423 UINT64_C(0),
3424 UINT64_C(0),
3425 UINT64_C(0),
3426 UINT64_C(0),
3427 UINT64_C(0),
3428 UINT64_C(0),
3429 UINT64_C(0),
3430 UINT64_C(0),
3431 UINT64_C(0),
3432 UINT64_C(0),
3433 UINT64_C(0),
3434 UINT64_C(0),
3435 UINT64_C(0),
3436 UINT64_C(0),
3437 UINT64_C(0),
3438 UINT64_C(0),
3439 UINT64_C(0),
3440 UINT64_C(0),
3441 UINT64_C(0),
3442 UINT64_C(0),
3443 UINT64_C(0),
3444 UINT64_C(0),
3445 UINT64_C(0),
3446 UINT64_C(0),
3447 UINT64_C(0),
3448 UINT64_C(0),
3449 UINT64_C(0),
3450 UINT64_C(0),
3451 UINT64_C(0),
3452 UINT64_C(0),
3453 UINT64_C(0),
3454 UINT64_C(0),
3455 UINT64_C(0),
3456 UINT64_C(0),
3457 UINT64_C(0),
3458 UINT64_C(0),
3459 UINT64_C(0),
3460 UINT64_C(0),
3461 UINT64_C(0),
3462 UINT64_C(0),
3463 UINT64_C(0),
3464 UINT64_C(0),
3465 UINT64_C(0),
3466 UINT64_C(0),
3467 UINT64_C(0),
3468 UINT64_C(0),
3469 UINT64_C(0),
3470 UINT64_C(0),
3471 UINT64_C(0),
3472 UINT64_C(0),
3473 UINT64_C(0),
3474 UINT64_C(0),
3475 UINT64_C(0),
3476 UINT64_C(0),
3477 UINT64_C(0),
3478 UINT64_C(0),
3479 UINT64_C(0),
3480 UINT64_C(0),
3481 UINT64_C(0),
3482 UINT64_C(0),
3483 UINT64_C(0),
3484 UINT64_C(0),
3485 UINT64_C(0),
3486 UINT64_C(0),
3487 UINT64_C(0),
3488 UINT64_C(0),
3489 UINT64_C(0),
3490 UINT64_C(0),
3491 UINT64_C(0),
3492 UINT64_C(0),
3493 UINT64_C(0),
3494 UINT64_C(0),
3495 UINT64_C(0),
3496 UINT64_C(0),
3497 UINT64_C(0),
3498 UINT64_C(0),
3499 UINT64_C(0),
3500 UINT64_C(0),
3501 UINT64_C(0),
3502 UINT64_C(0),
3503 UINT64_C(0),
3504 UINT64_C(0),
3505 UINT64_C(0),
3506 UINT64_C(0),
3507 UINT64_C(0),
3508 UINT64_C(0),
3509 UINT64_C(0),
3510 UINT64_C(0),
3511 UINT64_C(0),
3512 UINT64_C(0),
3513 UINT64_C(0),
3514 UINT64_C(0),
3515 UINT64_C(0),
3516 UINT64_C(0),
3517 UINT64_C(0),
3518 UINT64_C(0),
3519 UINT64_C(0),
3520 UINT64_C(0),
3521 UINT64_C(0),
3522 UINT64_C(0),
3523 UINT64_C(0),
3524 UINT64_C(0),
3525 UINT64_C(0),
3526 UINT64_C(0),
3527 UINT64_C(0),
3528 UINT64_C(0),
3529 UINT64_C(0),
3530 UINT64_C(0),
3531 UINT64_C(0),
3532 UINT64_C(0),
3533 UINT64_C(0),
3534 UINT64_C(0),
3535 UINT64_C(0),
3536 UINT64_C(0),
3537 UINT64_C(0),
3538 UINT64_C(0),
3539 UINT64_C(0),
3540 UINT64_C(0),
3541 UINT64_C(0),
3542 UINT64_C(0),
3543 UINT64_C(0),
3544 UINT64_C(0),
3545 UINT64_C(0),
3546 UINT64_C(0),
3547 UINT64_C(0),
3548 UINT64_C(0),
3549 UINT64_C(0),
3550 UINT64_C(0),
3551 UINT64_C(0),
3552 UINT64_C(0),
3553 UINT64_C(0),
3554 UINT64_C(0),
3555 UINT64_C(0),
3556 UINT64_C(0),
3557 UINT64_C(0),
3558 UINT64_C(0),
3559 UINT64_C(0),
3560 UINT64_C(0),
3561 UINT64_C(0),
3562 UINT64_C(0),
3563 UINT64_C(0),
3564 UINT64_C(0),
3565 UINT64_C(0),
3566 UINT64_C(0),
3567 UINT64_C(0),
3568 UINT64_C(0),
3569 UINT64_C(0),
3570 UINT64_C(0),
3571 UINT64_C(0),
3572 UINT64_C(0),
3573 UINT64_C(0),
3574 UINT64_C(0),
3575 UINT64_C(0),
3576 UINT64_C(0),
3577 UINT64_C(0),
3578 UINT64_C(0),
3579 UINT64_C(0),
3580 UINT64_C(0),
3581 UINT64_C(0),
3582 UINT64_C(0),
3583 UINT64_C(0),
3584 UINT64_C(0),
3585 UINT64_C(0),
3586 UINT64_C(0),
3587 UINT64_C(0),
3588 UINT64_C(0),
3589 UINT64_C(0),
3590 UINT64_C(0),
3591 UINT64_C(0),
3592 UINT64_C(0),
3593 UINT64_C(0),
3594 UINT64_C(0),
3595 UINT64_C(0),
3596 UINT64_C(0),
3597 UINT64_C(0),
3598 UINT64_C(0),
3599 UINT64_C(0),
3600 UINT64_C(0),
3601 UINT64_C(0),
3602 UINT64_C(0),
3603 UINT64_C(0),
3604 UINT64_C(0),
3605 UINT64_C(0),
3606 UINT64_C(0),
3607 UINT64_C(0),
3608 UINT64_C(0),
3609 UINT64_C(0),
3610 UINT64_C(0),
3611 UINT64_C(0),
3612 UINT64_C(0),
3613 UINT64_C(0),
3614 UINT64_C(0),
3615 UINT64_C(0),
3616 UINT64_C(0),
3617 UINT64_C(0),
3618 UINT64_C(0),
3619 UINT64_C(0),
3620 UINT64_C(0),
3621 UINT64_C(0),
3622 UINT64_C(0),
3623 UINT64_C(0),
3624 UINT64_C(0),
3625 UINT64_C(0),
3626 UINT64_C(0),
3627 UINT64_C(0),
3628 UINT64_C(0),
3629 UINT64_C(0),
3630 UINT64_C(0),
3631 UINT64_C(0),
3632 UINT64_C(0),
3633 UINT64_C(0),
3634 UINT64_C(0),
3635 UINT64_C(0),
3636 UINT64_C(0),
3637 UINT64_C(0),
3638 UINT64_C(0),
3639 UINT64_C(0),
3640 UINT64_C(0),
3641 UINT64_C(0),
3642 UINT64_C(0),
3643 UINT64_C(0),
3644 UINT64_C(0),
3645 UINT64_C(0),
3646 UINT64_C(0),
3647 UINT64_C(0),
3648 UINT64_C(0),
3649 UINT64_C(0),
3650 UINT64_C(0),
3651 UINT64_C(0),
3652 UINT64_C(0),
3653 UINT64_C(0),
3654 UINT64_C(0),
3655 UINT64_C(0),
3656 UINT64_C(0),
3657 UINT64_C(0),
3658 UINT64_C(0),
3659 UINT64_C(0),
3660 UINT64_C(0),
3661 UINT64_C(0),
3662 UINT64_C(0),
3663 UINT64_C(0),
3664 UINT64_C(0),
3665 UINT64_C(0),
3666 UINT64_C(0),
3667 UINT64_C(0),
3668 UINT64_C(0),
3669 UINT64_C(0),
3670 UINT64_C(0),
3671 UINT64_C(0),
3672 UINT64_C(0),
3673 UINT64_C(0),
3674 UINT64_C(0),
3675 UINT64_C(0),
3676 UINT64_C(0),
3677 UINT64_C(0),
3678 UINT64_C(0),
3679 UINT64_C(0),
3680 UINT64_C(0),
3681 UINT64_C(0),
3682 UINT64_C(0),
3683 UINT64_C(0),
3684 UINT64_C(0),
3685 UINT64_C(0),
3686 UINT64_C(0),
3687 UINT64_C(0),
3688 UINT64_C(0),
3689 UINT64_C(0),
3690 UINT64_C(0),
3691 UINT64_C(0),
3692 UINT64_C(0),
3693 UINT64_C(0),
3694 UINT64_C(0),
3695 UINT64_C(0),
3696 UINT64_C(0),
3697 UINT64_C(0),
3698 UINT64_C(0),
3699 UINT64_C(0),
3700 UINT64_C(0),
3701 UINT64_C(0),
3702 UINT64_C(0),
3703 UINT64_C(0),
3704 UINT64_C(0),
3705 UINT64_C(0),
3706 UINT64_C(0),
3707 UINT64_C(0),
3708 UINT64_C(0),
3709 UINT64_C(0),
3710 UINT64_C(0),
3711 UINT64_C(0),
3712 UINT64_C(0),
3713 UINT64_C(0),
3714 UINT64_C(0),
3715 UINT64_C(0),
3716 UINT64_C(0),
3717 UINT64_C(0),
3718 UINT64_C(0),
3719 UINT64_C(0),
3720 UINT64_C(0),
3721 UINT64_C(0),
3722 UINT64_C(0),
3723 UINT64_C(0),
3724 UINT64_C(0),
3725 UINT64_C(0),
3726 UINT64_C(0),
3727 UINT64_C(0),
3728 UINT64_C(0),
3729 UINT64_C(0),
3730 UINT64_C(0),
3731 UINT64_C(0),
3732 UINT64_C(0),
3733 UINT64_C(0),
3734 UINT64_C(0),
3735 UINT64_C(0),
3736 UINT64_C(0),
3737 UINT64_C(0),
3738 UINT64_C(0),
3739 UINT64_C(0),
3740 UINT64_C(0),
3741 UINT64_C(0),
3742 UINT64_C(0),
3743 UINT64_C(0),
3744 UINT64_C(0),
3745 UINT64_C(0),
3746 UINT64_C(0),
3747 UINT64_C(0),
3748 UINT64_C(0),
3749 UINT64_C(0),
3750 UINT64_C(0),
3751 UINT64_C(0),
3752 UINT64_C(0),
3753 UINT64_C(0),
3754 UINT64_C(0),
3755 UINT64_C(0),
3756 UINT64_C(0),
3757 UINT64_C(0),
3758 UINT64_C(0),
3759 UINT64_C(0),
3760 UINT64_C(0),
3761 UINT64_C(0),
3762 UINT64_C(0),
3763 UINT64_C(0),
3764 UINT64_C(0),
3765 UINT64_C(0),
3766 UINT64_C(0),
3767 UINT64_C(0),
3768 UINT64_C(0),
3769 UINT64_C(0),
3770 UINT64_C(0),
3771 UINT64_C(0),
3772 UINT64_C(0),
3773 UINT64_C(0),
3774 UINT64_C(0),
3775 UINT64_C(0),
3776 UINT64_C(0),
3777 UINT64_C(0),
3778 UINT64_C(0),
3779 UINT64_C(0),
3780 UINT64_C(0),
3781 UINT64_C(0),
3782 UINT64_C(0),
3783 UINT64_C(0),
3784 UINT64_C(0),
3785 UINT64_C(0),
3786 UINT64_C(0),
3787 UINT64_C(0),
3788 UINT64_C(0),
3789 UINT64_C(0),
3790 UINT64_C(0),
3791 UINT64_C(0),
3792 UINT64_C(0),
3793 UINT64_C(0),
3794 UINT64_C(0),
3795 UINT64_C(0),
3796 UINT64_C(0),
3797 UINT64_C(0),
3798 UINT64_C(0),
3799 UINT64_C(0),
3800 UINT64_C(0),
3801 UINT64_C(0),
3802 UINT64_C(0),
3803 UINT64_C(0),
3804 UINT64_C(0),
3805 UINT64_C(0),
3806 UINT64_C(0),
3807 UINT64_C(0),
3808 UINT64_C(0),
3809 UINT64_C(0),
3810 UINT64_C(0),
3811 UINT64_C(0),
3812 UINT64_C(0),
3813 UINT64_C(0),
3814 UINT64_C(0),
3815 UINT64_C(0),
3816 UINT64_C(0),
3817 UINT64_C(0),
3818 UINT64_C(0),
3819 UINT64_C(0),
3820 UINT64_C(0),
3821 UINT64_C(0),
3822 UINT64_C(0),
3823 UINT64_C(0),
3824 UINT64_C(0),
3825 UINT64_C(0),
3826 UINT64_C(0),
3827 UINT64_C(0),
3828 UINT64_C(0),
3829 UINT64_C(0),
3830 UINT64_C(0),
3831 UINT64_C(0),
3832 UINT64_C(0),
3833 UINT64_C(0),
3834 UINT64_C(0),
3835 UINT64_C(0),
3836 UINT64_C(0),
3837 UINT64_C(0),
3838 UINT64_C(0),
3839 UINT64_C(0),
3840 UINT64_C(0),
3841 UINT64_C(0),
3842 UINT64_C(0),
3843 UINT64_C(0),
3844 UINT64_C(0),
3845 UINT64_C(0),
3846 UINT64_C(0),
3847 UINT64_C(0),
3848 UINT64_C(0),
3849 UINT64_C(0),
3850 UINT64_C(0),
3851 UINT64_C(0),
3852 UINT64_C(0),
3853 UINT64_C(0),
3854 UINT64_C(0),
3855 UINT64_C(0),
3856 UINT64_C(0),
3857 UINT64_C(0),
3858 UINT64_C(0),
3859 UINT64_C(0),
3860 UINT64_C(0),
3861 UINT64_C(0),
3862 UINT64_C(0),
3863 UINT64_C(0),
3864 UINT64_C(0),
3865 UINT64_C(0),
3866 UINT64_C(0),
3867 UINT64_C(0),
3868 UINT64_C(0),
3869 UINT64_C(0),
3870 UINT64_C(0),
3871 UINT64_C(0),
3872 UINT64_C(0),
3873 UINT64_C(0),
3874 UINT64_C(0),
3875 UINT64_C(0),
3876 UINT64_C(0),
3877 UINT64_C(0),
3878 UINT64_C(0),
3879 UINT64_C(0),
3880 UINT64_C(0),
3881 UINT64_C(0),
3882 UINT64_C(0),
3883 UINT64_C(0),
3884 UINT64_C(0),
3885 UINT64_C(0),
3886 UINT64_C(0),
3887 UINT64_C(0),
3888 UINT64_C(0),
3889 UINT64_C(0),
3890 UINT64_C(0),
3891 UINT64_C(0),
3892 UINT64_C(0),
3893 UINT64_C(0),
3894 UINT64_C(0),
3895 UINT64_C(0),
3896 UINT64_C(0),
3897 UINT64_C(0),
3898 UINT64_C(0),
3899 UINT64_C(0),
3900 UINT64_C(0),
3901 UINT64_C(0),
3902 UINT64_C(0),
3903 UINT64_C(0),
3904 UINT64_C(0),
3905 UINT64_C(0),
3906 UINT64_C(0),
3907 UINT64_C(0),
3908 UINT64_C(0),
3909 UINT64_C(0),
3910 UINT64_C(0),
3911 UINT64_C(0),
3912 UINT64_C(0),
3913 UINT64_C(0),
3914 UINT64_C(0),
3915 UINT64_C(0),
3916 UINT64_C(0),
3917 UINT64_C(0),
3918 UINT64_C(0),
3919 UINT64_C(0),
3920 UINT64_C(0),
3921 UINT64_C(0),
3922 UINT64_C(0),
3923 UINT64_C(0),
3924 UINT64_C(0),
3925 UINT64_C(0),
3926 UINT64_C(0),
3927 UINT64_C(0),
3928 UINT64_C(0),
3929 UINT64_C(0),
3930 UINT64_C(0),
3931 UINT64_C(0),
3932 UINT64_C(0),
3933 UINT64_C(0),
3934 UINT64_C(0),
3935 UINT64_C(0),
3936 UINT64_C(0),
3937 UINT64_C(0),
3938 UINT64_C(0),
3939 UINT64_C(0),
3940 UINT64_C(0),
3941 UINT64_C(0),
3942 UINT64_C(0),
3943 UINT64_C(0),
3944 UINT64_C(0),
3945 UINT64_C(0),
3946 UINT64_C(0),
3947 UINT64_C(0),
3948 UINT64_C(0),
3949 UINT64_C(0),
3950 UINT64_C(0),
3951 UINT64_C(0),
3952 UINT64_C(0),
3953 UINT64_C(0),
3954 UINT64_C(0),
3955 UINT64_C(0),
3956 UINT64_C(0),
3957 UINT64_C(0),
3958 UINT64_C(0),
3959 UINT64_C(0),
3960 UINT64_C(0),
3961 UINT64_C(0),
3962 UINT64_C(0),
3963 UINT64_C(0),
3964 UINT64_C(0),
3965 UINT64_C(0),
3966 UINT64_C(0),
3967 UINT64_C(0),
3968 UINT64_C(0),
3969 UINT64_C(0),
3970 UINT64_C(0),
3971 UINT64_C(0),
3972 UINT64_C(0),
3973 UINT64_C(0),
3974 UINT64_C(0),
3975 UINT64_C(0),
3976 UINT64_C(0),
3977 UINT64_C(0),
3978 UINT64_C(0),
3979 UINT64_C(0),
3980 UINT64_C(0),
3981 UINT64_C(0),
3982 UINT64_C(0),
3983 UINT64_C(0),
3984 UINT64_C(0),
3985 UINT64_C(0),
3986 UINT64_C(0),
3987 UINT64_C(0),
3988 UINT64_C(0),
3989 UINT64_C(0),
3990 UINT64_C(0),
3991 UINT64_C(0),
3992 UINT64_C(0),
3993 UINT64_C(0),
3994 UINT64_C(0),
3995 UINT64_C(0),
3996 UINT64_C(0),
3997 UINT64_C(0),
3998 UINT64_C(0),
3999 UINT64_C(0),
4000 UINT64_C(0),
4001 UINT64_C(0),
4002 UINT64_C(0),
4003 UINT64_C(0),
4004 UINT64_C(0),
4005 UINT64_C(0),
4006 UINT64_C(0),
4007 UINT64_C(0),
4008 UINT64_C(0),
4009 UINT64_C(0),
4010 UINT64_C(0),
4011 UINT64_C(0),
4012 UINT64_C(0),
4013 UINT64_C(0),
4014 UINT64_C(0),
4015 UINT64_C(0),
4016 UINT64_C(0),
4017 UINT64_C(0),
4018 UINT64_C(0),
4019 UINT64_C(0),
4020 UINT64_C(0),
4021 UINT64_C(0),
4022 UINT64_C(0),
4023 UINT64_C(0),
4024 UINT64_C(0),
4025 UINT64_C(0),
4026 UINT64_C(0),
4027 UINT64_C(0),
4028 UINT64_C(0),
4029 UINT64_C(0),
4030 UINT64_C(0),
4031 UINT64_C(0),
4032 UINT64_C(0),
4033 UINT64_C(0),
4034 UINT64_C(0),
4035 UINT64_C(0),
4036 UINT64_C(0),
4037 UINT64_C(0),
4038 UINT64_C(0),
4039 UINT64_C(0),
4040 UINT64_C(0),
4041 UINT64_C(0),
4042 UINT64_C(0),
4043 UINT64_C(0),
4044 UINT64_C(0),
4045 UINT64_C(0),
4046 UINT64_C(0),
4047 UINT64_C(0),
4048 UINT64_C(0),
4049 UINT64_C(0),
4050 UINT64_C(0),
4051 UINT64_C(0),
4052 UINT64_C(0),
4053 UINT64_C(0),
4054 UINT64_C(0),
4055 UINT64_C(0),
4056 UINT64_C(0),
4057 UINT64_C(0),
4058 UINT64_C(0),
4059 UINT64_C(0),
4060 UINT64_C(0),
4061 UINT64_C(0),
4062 UINT64_C(0),
4063 UINT64_C(0),
4064 UINT64_C(0),
4065 UINT64_C(0),
4066 UINT64_C(0),
4067 UINT64_C(0),
4068 UINT64_C(0),
4069 UINT64_C(0),
4070 UINT64_C(0),
4071 UINT64_C(0),
4072 UINT64_C(0),
4073 UINT64_C(0),
4074 UINT64_C(0),
4075 UINT64_C(0),
4076 UINT64_C(0),
4077 UINT64_C(0),
4078 UINT64_C(0),
4079 UINT64_C(0),
4080 UINT64_C(0),
4081 UINT64_C(0),
4082 UINT64_C(0),
4083 UINT64_C(0),
4084 UINT64_C(0),
4085 UINT64_C(0),
4086 UINT64_C(0),
4087 UINT64_C(0),
4088 UINT64_C(0),
4089 UINT64_C(0),
4090 UINT64_C(0),
4091 UINT64_C(0),
4092 UINT64_C(0),
4093 UINT64_C(0),
4094 UINT64_C(0),
4095 UINT64_C(0),
4096 UINT64_C(0),
4097 UINT64_C(0),
4098 UINT64_C(0),
4099 UINT64_C(0),
4100 UINT64_C(0),
4101 UINT64_C(0),
4102 UINT64_C(0),
4103 UINT64_C(0),
4104 UINT64_C(0),
4105 UINT64_C(0),
4106 UINT64_C(0),
4107 UINT64_C(0),
4108 UINT64_C(0),
4109 UINT64_C(0),
4110 UINT64_C(0),
4111 UINT64_C(0),
4112 UINT64_C(0),
4113 UINT64_C(0),
4114 UINT64_C(0),
4115 UINT64_C(0),
4116 UINT64_C(0),
4117 UINT64_C(0),
4118 UINT64_C(0),
4119 UINT64_C(0),
4120 UINT64_C(0),
4121 UINT64_C(0),
4122 UINT64_C(0),
4123 UINT64_C(0),
4124 UINT64_C(0),
4125 UINT64_C(0),
4126 UINT64_C(0),
4127 UINT64_C(0),
4128 UINT64_C(0),
4129 UINT64_C(0),
4130 UINT64_C(0),
4131 UINT64_C(0),
4132 UINT64_C(0),
4133 UINT64_C(0),
4134 UINT64_C(0),
4135 UINT64_C(0),
4136 UINT64_C(0),
4137 UINT64_C(0),
4138 UINT64_C(0),
4139 UINT64_C(0),
4140 UINT64_C(0),
4141 UINT64_C(0),
4142 UINT64_C(0),
4143 UINT64_C(0),
4144 UINT64_C(0),
4145 UINT64_C(0),
4146 UINT64_C(0),
4147 UINT64_C(0),
4148 UINT64_C(0),
4149 UINT64_C(0),
4150 UINT64_C(0),
4151 UINT64_C(0),
4152 UINT64_C(0),
4153 UINT64_C(0),
4154 UINT64_C(0),
4155 UINT64_C(0),
4156 UINT64_C(0),
4157 UINT64_C(0),
4158 UINT64_C(0),
4159 UINT64_C(0),
4160 UINT64_C(0),
4161 UINT64_C(0),
4162 UINT64_C(0),
4163 UINT64_C(0),
4164 UINT64_C(0),
4165 UINT64_C(0),
4166 UINT64_C(0),
4167 UINT64_C(0),
4168 UINT64_C(0),
4169 UINT64_C(0),
4170 UINT64_C(0),
4171 UINT64_C(0),
4172 UINT64_C(0),
4173 UINT64_C(0),
4174 UINT64_C(0),
4175 UINT64_C(0),
4176 UINT64_C(0),
4177 UINT64_C(0),
4178 UINT64_C(0),
4179 UINT64_C(0),
4180 UINT64_C(0),
4181 UINT64_C(0),
4182 UINT64_C(0),
4183 UINT64_C(0),
4184 UINT64_C(0),
4185 UINT64_C(0),
4186 UINT64_C(0),
4187 UINT64_C(0),
4188 UINT64_C(0),
4189 UINT64_C(0),
4190 UINT64_C(0),
4191 UINT64_C(0),
4192 UINT64_C(0),
4193 UINT64_C(0),
4194 UINT64_C(0),
4195 UINT64_C(0),
4196 UINT64_C(0),
4197 UINT64_C(0),
4198 UINT64_C(0),
4199 UINT64_C(0),
4200 UINT64_C(0),
4201 UINT64_C(0),
4202 UINT64_C(0),
4203 UINT64_C(0),
4204 UINT64_C(0),
4205 UINT64_C(0),
4206 UINT64_C(0),
4207 UINT64_C(0),
4208 UINT64_C(0),
4209 UINT64_C(0),
4210 UINT64_C(0),
4211 UINT64_C(0),
4212 UINT64_C(0),
4213 UINT64_C(0),
4214 UINT64_C(0),
4215 UINT64_C(0),
4216 UINT64_C(0),
4217 UINT64_C(0),
4218 UINT64_C(0),
4219 UINT64_C(0),
4220 UINT64_C(0),
4221 UINT64_C(0),
4222 UINT64_C(0),
4223 UINT64_C(0),
4224 UINT64_C(0),
4225 UINT64_C(0),
4226 UINT64_C(0),
4227 UINT64_C(0),
4228 UINT64_C(0),
4229 UINT64_C(0),
4230 UINT64_C(0),
4231 UINT64_C(0),
4232 UINT64_C(0),
4233 UINT64_C(0),
4234 UINT64_C(0),
4235 UINT64_C(0),
4236 UINT64_C(0),
4237 UINT64_C(0),
4238 UINT64_C(0),
4239 UINT64_C(0),
4240 UINT64_C(0),
4241 UINT64_C(0),
4242 UINT64_C(0),
4243 UINT64_C(0),
4244 UINT64_C(0),
4245 UINT64_C(0),
4246 UINT64_C(0),
4247 UINT64_C(0),
4248 UINT64_C(0),
4249 UINT64_C(0),
4250 UINT64_C(0),
4251 UINT64_C(0),
4252 UINT64_C(0),
4253 UINT64_C(0),
4254 UINT64_C(0),
4255 UINT64_C(0),
4256 UINT64_C(0),
4257 UINT64_C(0),
4258 UINT64_C(0),
4259 UINT64_C(0),
4260 UINT64_C(0),
4261 UINT64_C(0),
4262 UINT64_C(0),
4263 UINT64_C(0),
4264 UINT64_C(0),
4265 UINT64_C(0),
4266 UINT64_C(0),
4267 UINT64_C(0),
4268 UINT64_C(0),
4269 UINT64_C(0),
4270 UINT64_C(0),
4271 UINT64_C(0),
4272 UINT64_C(0),
4273 UINT64_C(0),
4274 UINT64_C(0),
4275 UINT64_C(0),
4276 UINT64_C(0),
4277 UINT64_C(0),
4278 UINT64_C(0),
4279 UINT64_C(0),
4280 UINT64_C(0),
4281 UINT64_C(0),
4282 UINT64_C(0),
4283 UINT64_C(0),
4284 UINT64_C(0),
4285 UINT64_C(0),
4286 UINT64_C(0),
4287 UINT64_C(0),
4288 UINT64_C(0),
4289 UINT64_C(0),
4290 UINT64_C(0),
4291 UINT64_C(0),
4292 UINT64_C(0),
4293 UINT64_C(0),
4294 UINT64_C(0),
4295 UINT64_C(0),
4296 UINT64_C(0),
4297 UINT64_C(0),
4298 UINT64_C(0),
4299 UINT64_C(0),
4300 UINT64_C(0),
4301 UINT64_C(0),
4302 UINT64_C(0),
4303 UINT64_C(0),
4304 UINT64_C(0),
4305 UINT64_C(0),
4306 UINT64_C(0),
4307 UINT64_C(0),
4308 UINT64_C(0),
4309 UINT64_C(0),
4310 UINT64_C(0),
4311 UINT64_C(0),
4312 UINT64_C(0),
4313 UINT64_C(0),
4314 UINT64_C(0),
4315 UINT64_C(0),
4316 UINT64_C(0),
4317 UINT64_C(0),
4318 UINT64_C(0),
4319 UINT64_C(0),
4320 UINT64_C(0),
4321 UINT64_C(0),
4322 UINT64_C(0),
4323 UINT64_C(0),
4324 UINT64_C(0),
4325 UINT64_C(0),
4326 UINT64_C(0),
4327 UINT64_C(0),
4328 UINT64_C(0),
4329 UINT64_C(0),
4330 UINT64_C(0),
4331 UINT64_C(0),
4332 UINT64_C(0),
4333 UINT64_C(0),
4334 UINT64_C(0),
4335 UINT64_C(0),
4336 UINT64_C(0),
4337 UINT64_C(0),
4338 UINT64_C(0),
4339 UINT64_C(0),
4340 UINT64_C(0),
4341 UINT64_C(0),
4342 UINT64_C(0),
4343 UINT64_C(0),
4344 UINT64_C(0),
4345 UINT64_C(0),
4346 UINT64_C(0),
4347 UINT64_C(0),
4348 UINT64_C(0),
4349 UINT64_C(0),
4350 UINT64_C(0),
4351 UINT64_C(0),
4352 UINT64_C(0),
4353 UINT64_C(0),
4354 UINT64_C(0),
4355 UINT64_C(0),
4356 UINT64_C(0),
4357 UINT64_C(0),
4358 UINT64_C(0),
4359 UINT64_C(0),
4360 UINT64_C(0),
4361 UINT64_C(0),
4362 UINT64_C(0),
4363 UINT64_C(0),
4364 UINT64_C(0),
4365 UINT64_C(0),
4366 UINT64_C(0),
4367 UINT64_C(0),
4368 UINT64_C(0),
4369 UINT64_C(0),
4370 UINT64_C(0),
4371 UINT64_C(0),
4372 UINT64_C(0),
4373 UINT64_C(0),
4374 UINT64_C(0),
4375 UINT64_C(0),
4376 UINT64_C(0),
4377 UINT64_C(0),
4378 UINT64_C(0),
4379 UINT64_C(0),
4380 UINT64_C(0),
4381 UINT64_C(0),
4382 UINT64_C(0),
4383 UINT64_C(0),
4384 UINT64_C(0),
4385 UINT64_C(0),
4386 UINT64_C(0),
4387 UINT64_C(0),
4388 UINT64_C(0),
4389 UINT64_C(0),
4390 UINT64_C(0),
4391 UINT64_C(0),
4392 UINT64_C(0),
4393 UINT64_C(0),
4394 UINT64_C(0),
4395 UINT64_C(0),
4396 UINT64_C(0),
4397 UINT64_C(0),
4398 UINT64_C(0),
4399 UINT64_C(0),
4400 UINT64_C(0),
4401 UINT64_C(0),
4402 UINT64_C(0),
4403 UINT64_C(0),
4404 UINT64_C(0),
4405 UINT64_C(0),
4406 UINT64_C(0),
4407 UINT64_C(0),
4408 UINT64_C(0),
4409 UINT64_C(0),
4410 UINT64_C(0),
4411 UINT64_C(0),
4412 UINT64_C(0),
4413 UINT64_C(0),
4414 UINT64_C(0),
4415 UINT64_C(0),
4416 UINT64_C(0),
4417 UINT64_C(0),
4418 UINT64_C(0),
4419 UINT64_C(0),
4420 UINT64_C(0),
4421 UINT64_C(0),
4422 UINT64_C(0),
4423 UINT64_C(0),
4424 UINT64_C(0),
4425 UINT64_C(0),
4426 UINT64_C(0),
4427 UINT64_C(0),
4428 UINT64_C(0),
4429 UINT64_C(0),
4430 UINT64_C(0),
4431 UINT64_C(0),
4432 UINT64_C(0),
4433 UINT64_C(0),
4434 UINT64_C(0),
4435 UINT64_C(0),
4436 UINT64_C(0),
4437 UINT64_C(0),
4438 UINT64_C(0),
4439 UINT64_C(0),
4440 UINT64_C(0),
4441 UINT64_C(0),
4442 UINT64_C(0),
4443 UINT64_C(0),
4444 UINT64_C(0),
4445 UINT64_C(0),
4446 UINT64_C(0),
4447 UINT64_C(0),
4448 UINT64_C(0),
4449 UINT64_C(0),
4450 UINT64_C(0),
4451 UINT64_C(0),
4452 UINT64_C(0),
4453 UINT64_C(0),
4454 UINT64_C(0),
4455 UINT64_C(0),
4456 UINT64_C(0),
4457 UINT64_C(0),
4458 UINT64_C(0),
4459 UINT64_C(0),
4460 UINT64_C(0),
4461 UINT64_C(0),
4462 UINT64_C(0),
4463 UINT64_C(0),
4464 UINT64_C(0),
4465 UINT64_C(0),
4466 UINT64_C(0),
4467 UINT64_C(0),
4468 UINT64_C(0),
4469 UINT64_C(0),
4470 UINT64_C(0),
4471 UINT64_C(0),
4472 UINT64_C(0),
4473 UINT64_C(0),
4474 UINT64_C(0),
4475 UINT64_C(0),
4476 UINT64_C(0),
4477 UINT64_C(0),
4478 UINT64_C(0),
4479 UINT64_C(0),
4480 UINT64_C(0),
4481 UINT64_C(0),
4482 UINT64_C(0),
4483 UINT64_C(0),
4484 UINT64_C(0),
4485 UINT64_C(0),
4486 UINT64_C(0),
4487 UINT64_C(0),
4488 UINT64_C(0),
4489 UINT64_C(0),
4490 UINT64_C(0),
4491 UINT64_C(0),
4492 UINT64_C(0),
4493 UINT64_C(0),
4494 UINT64_C(0),
4495 UINT64_C(0),
4496 UINT64_C(0),
4497 UINT64_C(0),
4498 UINT64_C(0),
4499 UINT64_C(0),
4500 UINT64_C(0),
4501 UINT64_C(0),
4502 UINT64_C(0),
4503 UINT64_C(0),
4504 UINT64_C(0),
4505 UINT64_C(0),
4506 UINT64_C(0),
4507 UINT64_C(0),
4508 UINT64_C(0),
4509 UINT64_C(0),
4510 UINT64_C(0),
4511 UINT64_C(0),
4512 UINT64_C(0),
4513 UINT64_C(0),
4514 UINT64_C(0),
4515 UINT64_C(0),
4516 UINT64_C(0),
4517 UINT64_C(0),
4518 UINT64_C(0),
4519 UINT64_C(0),
4520 UINT64_C(0),
4521 UINT64_C(0),
4522 UINT64_C(0),
4523 UINT64_C(0),
4524 UINT64_C(0),
4525 UINT64_C(0),
4526 UINT64_C(0),
4527 UINT64_C(0),
4528 UINT64_C(0),
4529 UINT64_C(0),
4530 UINT64_C(0),
4531 UINT64_C(0),
4532 UINT64_C(0),
4533 UINT64_C(0),
4534 UINT64_C(0),
4535 UINT64_C(0),
4536 UINT64_C(0),
4537 UINT64_C(0),
4538 UINT64_C(0),
4539 UINT64_C(0),
4540 UINT64_C(0),
4541 UINT64_C(0),
4542 UINT64_C(0),
4543 UINT64_C(0),
4544 UINT64_C(0),
4545 UINT64_C(0),
4546 UINT64_C(0),
4547 UINT64_C(0),
4548 UINT64_C(0),
4549 UINT64_C(0),
4550 UINT64_C(0),
4551 UINT64_C(0),
4552 UINT64_C(0),
4553 UINT64_C(0),
4554 UINT64_C(0),
4555 UINT64_C(0),
4556 UINT64_C(0),
4557 UINT64_C(0),
4558 UINT64_C(0),
4559 UINT64_C(0),
4560 UINT64_C(0),
4561 UINT64_C(0),
4562 UINT64_C(0),
4563 UINT64_C(0),
4564 UINT64_C(0),
4565 UINT64_C(0),
4566 UINT64_C(0),
4567 UINT64_C(0),
4568 UINT64_C(0),
4569 UINT64_C(0),
4570 UINT64_C(0),
4571 UINT64_C(0),
4572 UINT64_C(0),
4573 UINT64_C(0),
4574 UINT64_C(0),
4575 UINT64_C(0),
4576 UINT64_C(0),
4577 UINT64_C(0),
4578 UINT64_C(0),
4579 UINT64_C(0),
4580 UINT64_C(0),
4581 UINT64_C(0),
4582 UINT64_C(0),
4583 UINT64_C(0),
4584 UINT64_C(0),
4585 UINT64_C(0),
4586 UINT64_C(0),
4587 UINT64_C(0),
4588 UINT64_C(0),
4589 UINT64_C(0),
4590 UINT64_C(0),
4591 UINT64_C(0),
4592 UINT64_C(0),
4593 UINT64_C(0),
4594 UINT64_C(0),
4595 UINT64_C(0),
4596 UINT64_C(0),
4597 UINT64_C(0),
4598 UINT64_C(0),
4599 UINT64_C(0),
4600 UINT64_C(0),
4601 UINT64_C(0),
4602 UINT64_C(0),
4603 UINT64_C(0),
4604 UINT64_C(0),
4605 UINT64_C(0),
4606 UINT64_C(0),
4607 UINT64_C(0),
4608 UINT64_C(0),
4609 UINT64_C(0),
4610 UINT64_C(0),
4611 UINT64_C(0),
4612 UINT64_C(0),
4613 UINT64_C(0),
4614 UINT64_C(0),
4615 UINT64_C(0),
4616 UINT64_C(0),
4617 UINT64_C(0),
4618 UINT64_C(0),
4619 UINT64_C(0),
4620 UINT64_C(0),
4621 UINT64_C(0),
4622 UINT64_C(0),
4623 UINT64_C(0),
4624 UINT64_C(0),
4625 UINT64_C(0),
4626 UINT64_C(0),
4627 UINT64_C(0),
4628 UINT64_C(0),
4629 UINT64_C(0),
4630 UINT64_C(0),
4631 UINT64_C(0),
4632 UINT64_C(0),
4633 UINT64_C(0),
4634 UINT64_C(0),
4635 UINT64_C(0),
4636 UINT64_C(0),
4637 UINT64_C(0),
4638 UINT64_C(0),
4639 UINT64_C(0),
4640 UINT64_C(0),
4641 UINT64_C(0),
4642 UINT64_C(0),
4643 UINT64_C(0),
4644 UINT64_C(0),
4645 UINT64_C(0),
4646 UINT64_C(0),
4647 UINT64_C(0),
4648 UINT64_C(0),
4649 UINT64_C(0),
4650 UINT64_C(0),
4651 UINT64_C(0),
4652 UINT64_C(0),
4653 UINT64_C(0),
4654 UINT64_C(0),
4655 UINT64_C(0),
4656 UINT64_C(0),
4657 UINT64_C(0),
4658 UINT64_C(0),
4659 UINT64_C(0),
4660 UINT64_C(0),
4661 UINT64_C(0),
4662 UINT64_C(0),
4663 UINT64_C(0),
4664 UINT64_C(0),
4665 UINT64_C(0),
4666 UINT64_C(0),
4667 UINT64_C(0),
4668 UINT64_C(0),
4669 UINT64_C(0),
4670 UINT64_C(0),
4671 UINT64_C(0),
4672 UINT64_C(0),
4673 UINT64_C(0),
4674 UINT64_C(0),
4675 UINT64_C(0),
4676 UINT64_C(0),
4677 UINT64_C(0),
4678 UINT64_C(0),
4679 UINT64_C(0),
4680 UINT64_C(0),
4681 UINT64_C(0),
4682 UINT64_C(0),
4683 UINT64_C(0),
4684 UINT64_C(0),
4685 UINT64_C(0),
4686 UINT64_C(0),
4687 UINT64_C(0),
4688 UINT64_C(0),
4689 UINT64_C(0),
4690 UINT64_C(0),
4691 UINT64_C(0),
4692 UINT64_C(0),
4693 UINT64_C(0),
4694 UINT64_C(0),
4695 UINT64_C(0),
4696 UINT64_C(0),
4697 UINT64_C(0),
4698 UINT64_C(0),
4699 UINT64_C(0),
4700 UINT64_C(0),
4701 UINT64_C(0),
4702 UINT64_C(0),
4703 UINT64_C(0),
4704 UINT64_C(0),
4705 UINT64_C(0),
4706 UINT64_C(0),
4707 UINT64_C(0),
4708 UINT64_C(0),
4709 UINT64_C(0),
4710 UINT64_C(0),
4711 UINT64_C(0),
4712 UINT64_C(0),
4713 UINT64_C(0),
4714 UINT64_C(0),
4715 UINT64_C(0),
4716 UINT64_C(0),
4717 UINT64_C(0),
4718 UINT64_C(0),
4719 UINT64_C(0),
4720 UINT64_C(0),
4721 UINT64_C(0),
4722 UINT64_C(0),
4723 UINT64_C(0),
4724 UINT64_C(0),
4725 UINT64_C(0),
4726 UINT64_C(0),
4727 UINT64_C(0),
4728 UINT64_C(0),
4729 UINT64_C(0),
4730 UINT64_C(0),
4731 UINT64_C(0),
4732 UINT64_C(0),
4733 UINT64_C(0),
4734 UINT64_C(0),
4735 UINT64_C(0),
4736 UINT64_C(0),
4737 UINT64_C(0),
4738 UINT64_C(0),
4739 UINT64_C(0),
4740 UINT64_C(0),
4741 UINT64_C(0),
4742 UINT64_C(0),
4743 UINT64_C(0),
4744 UINT64_C(0),
4745 UINT64_C(0),
4746 UINT64_C(0),
4747 UINT64_C(0),
4748 UINT64_C(0),
4749 UINT64_C(0),
4750 UINT64_C(0),
4751 UINT64_C(0),
4752 UINT64_C(0),
4753 UINT64_C(0),
4754 UINT64_C(0),
4755 UINT64_C(0),
4756 UINT64_C(0),
4757 UINT64_C(0),
4758 UINT64_C(0),
4759 UINT64_C(0),
4760 UINT64_C(0),
4761 UINT64_C(0),
4762 UINT64_C(0),
4763 UINT64_C(0),
4764 UINT64_C(0),
4765 UINT64_C(0),
4766 UINT64_C(0),
4767 UINT64_C(0),
4768 UINT64_C(0),
4769 UINT64_C(0),
4770 UINT64_C(0),
4771 UINT64_C(0),
4772 UINT64_C(0),
4773 UINT64_C(0),
4774 UINT64_C(0),
4775 UINT64_C(0),
4776 UINT64_C(0),
4777 UINT64_C(0),
4778 UINT64_C(0),
4779 UINT64_C(0),
4780 UINT64_C(0),
4781 UINT64_C(0),
4782 UINT64_C(0),
4783 UINT64_C(0),
4784 UINT64_C(0),
4785 UINT64_C(0),
4786 UINT64_C(0),
4787 UINT64_C(0),
4788 UINT64_C(0),
4789 UINT64_C(0),
4790 UINT64_C(0),
4791 UINT64_C(0),
4792 UINT64_C(0),
4793 UINT64_C(0),
4794 UINT64_C(0),
4795 UINT64_C(0),
4796 UINT64_C(0),
4797 UINT64_C(0),
4798 UINT64_C(0),
4799 UINT64_C(0),
4800 UINT64_C(0),
4801 UINT64_C(0),
4802 UINT64_C(0),
4803 UINT64_C(0),
4804 UINT64_C(0),
4805 UINT64_C(0),
4806 UINT64_C(0),
4807 UINT64_C(0),
4808 UINT64_C(0),
4809 UINT64_C(0),
4810 UINT64_C(0),
4811 UINT64_C(0),
4812 UINT64_C(0),
4813 UINT64_C(0),
4814 UINT64_C(0),
4815 UINT64_C(0),
4816 UINT64_C(0),
4817 UINT64_C(0),
4818 UINT64_C(0),
4819 UINT64_C(0),
4820 UINT64_C(0),
4821 UINT64_C(0),
4822 UINT64_C(0),
4823 UINT64_C(0),
4824 UINT64_C(0),
4825 UINT64_C(0),
4826 UINT64_C(0),
4827 UINT64_C(0),
4828 UINT64_C(0),
4829 UINT64_C(0),
4830 UINT64_C(0),
4831 UINT64_C(0),
4832 UINT64_C(0),
4833 UINT64_C(0),
4834 UINT64_C(0),
4835 UINT64_C(0),
4836 UINT64_C(0),
4837 UINT64_C(0),
4838 UINT64_C(0),
4839 UINT64_C(0),
4840 UINT64_C(0),
4841 UINT64_C(0),
4842 UINT64_C(0),
4843 UINT64_C(0),
4844 UINT64_C(0),
4845 UINT64_C(0),
4846 UINT64_C(0),
4847 UINT64_C(0),
4848 UINT64_C(0),
4849 UINT64_C(0),
4850 UINT64_C(0),
4851 UINT64_C(0),
4852 UINT64_C(0),
4853 UINT64_C(0),
4854 UINT64_C(0),
4855 UINT64_C(0),
4856 UINT64_C(0),
4857 UINT64_C(0),
4858 UINT64_C(0),
4859 UINT64_C(0),
4860 UINT64_C(0),
4861 UINT64_C(0),
4862 UINT64_C(0),
4863 UINT64_C(0),
4864 UINT64_C(0),
4865 UINT64_C(0),
4866 UINT64_C(0),
4867 UINT64_C(0),
4868 UINT64_C(0),
4869 UINT64_C(0),
4870 UINT64_C(0),
4871 UINT64_C(0),
4872 UINT64_C(0),
4873 UINT64_C(0),
4874 UINT64_C(0),
4875 UINT64_C(0),
4876 UINT64_C(0),
4877 UINT64_C(0),
4878 UINT64_C(0),
4879 UINT64_C(0),
4880 UINT64_C(0),
4881 UINT64_C(0),
4882 UINT64_C(0),
4883 UINT64_C(0),
4884 UINT64_C(0),
4885 UINT64_C(0),
4886 UINT64_C(0),
4887 UINT64_C(0),
4888 UINT64_C(0),
4889 UINT64_C(0),
4890 UINT64_C(0),
4891 UINT64_C(0),
4892 UINT64_C(0),
4893 UINT64_C(0),
4894 UINT64_C(0),
4895 UINT64_C(0),
4896 UINT64_C(0),
4897 UINT64_C(0),
4898 UINT64_C(0),
4899 UINT64_C(0),
4900 UINT64_C(0),
4901 UINT64_C(0),
4902 UINT64_C(0),
4903 UINT64_C(0),
4904 UINT64_C(0),
4905 UINT64_C(0),
4906 UINT64_C(0),
4907 UINT64_C(0),
4908 UINT64_C(0),
4909 UINT64_C(0),
4910 UINT64_C(0),
4911 UINT64_C(0),
4912 UINT64_C(0),
4913 UINT64_C(0),
4914 UINT64_C(0),
4915 UINT64_C(0),
4916 UINT64_C(0),
4917 UINT64_C(0),
4918 UINT64_C(0),
4919 UINT64_C(0),
4920 UINT64_C(0),
4921 UINT64_C(0),
4922 UINT64_C(0),
4923 UINT64_C(0),
4924 UINT64_C(0),
4925 UINT64_C(0),
4926 UINT64_C(0),
4927 UINT64_C(0),
4928 UINT64_C(0),
4929 UINT64_C(0),
4930 UINT64_C(0),
4931 UINT64_C(0),
4932 UINT64_C(0),
4933 UINT64_C(0),
4934 UINT64_C(0),
4935 UINT64_C(0),
4936 UINT64_C(0),
4937 UINT64_C(0),
4938 UINT64_C(0),
4939 UINT64_C(0),
4940 UINT64_C(0),
4941 UINT64_C(0),
4942 UINT64_C(0),
4943 UINT64_C(0),
4944 UINT64_C(0),
4945 UINT64_C(0),
4946 UINT64_C(0),
4947 UINT64_C(0),
4948 UINT64_C(0),
4949 UINT64_C(0),
4950 UINT64_C(0),
4951 UINT64_C(0),
4952 UINT64_C(0),
4953 UINT64_C(0),
4954 UINT64_C(0),
4955 UINT64_C(0),
4956 UINT64_C(0),
4957 UINT64_C(0),
4958 UINT64_C(0),
4959 UINT64_C(0),
4960 UINT64_C(0),
4961 UINT64_C(0),
4962 UINT64_C(0),
4963 UINT64_C(0),
4964 UINT64_C(0),
4965 UINT64_C(0),
4966 UINT64_C(0),
4967 UINT64_C(0),
4968 UINT64_C(0),
4969 UINT64_C(0),
4970 UINT64_C(0),
4971 UINT64_C(0),
4972 UINT64_C(0),
4973 UINT64_C(0),
4974 UINT64_C(0),
4975 UINT64_C(0),
4976 UINT64_C(0),
4977 UINT64_C(0),
4978 UINT64_C(0),
4979 UINT64_C(0),
4980 UINT64_C(0),
4981 UINT64_C(0),
4982 UINT64_C(0),
4983 UINT64_C(0),
4984 UINT64_C(0),
4985 UINT64_C(0),
4986 UINT64_C(0),
4987 UINT64_C(0),
4988 UINT64_C(0),
4989 UINT64_C(0),
4990 UINT64_C(0),
4991 UINT64_C(0),
4992 UINT64_C(0),
4993 UINT64_C(0),
4994 UINT64_C(0),
4995 UINT64_C(0),
4996 UINT64_C(0),
4997 UINT64_C(0),
4998 UINT64_C(0),
4999 UINT64_C(0),
5000 UINT64_C(0),
5001 UINT64_C(0),
5002 UINT64_C(0),
5003 UINT64_C(0),
5004 UINT64_C(0),
5005 UINT64_C(0),
5006 UINT64_C(0),
5007 UINT64_C(0),
5008 UINT64_C(0),
5009 UINT64_C(0),
5010 UINT64_C(0),
5011 UINT64_C(0),
5012 UINT64_C(0),
5013 UINT64_C(0),
5014 UINT64_C(0),
5015 UINT64_C(0),
5016 UINT64_C(0),
5017 UINT64_C(0),
5018 UINT64_C(0),
5019 UINT64_C(0),
5020 UINT64_C(0),
5021 UINT64_C(0),
5022 UINT64_C(0),
5023 UINT64_C(0),
5024 UINT64_C(0),
5025 UINT64_C(0),
5026 UINT64_C(0),
5027 UINT64_C(0),
5028 UINT64_C(0),
5029 UINT64_C(0),
5030 UINT64_C(0),
5031 UINT64_C(0),
5032 UINT64_C(0),
5033 UINT64_C(0),
5034 UINT64_C(0),
5035 UINT64_C(0),
5036 UINT64_C(0),
5037 UINT64_C(0),
5038 UINT64_C(0),
5039 UINT64_C(0),
5040 UINT64_C(0),
5041 UINT64_C(0),
5042 UINT64_C(0),
5043 UINT64_C(0),
5044 UINT64_C(0),
5045 UINT64_C(0),
5046 UINT64_C(0),
5047 UINT64_C(0),
5048 UINT64_C(0),
5049 UINT64_C(0),
5050 UINT64_C(0),
5051 UINT64_C(0),
5052 UINT64_C(0),
5053 UINT64_C(0),
5054 UINT64_C(0),
5055 UINT64_C(0),
5056 UINT64_C(0),
5057 UINT64_C(0),
5058 UINT64_C(0),
5059 UINT64_C(0),
5060 UINT64_C(0),
5061 UINT64_C(0),
5062 UINT64_C(0),
5063 UINT64_C(0),
5064 UINT64_C(0),
5065 UINT64_C(0),
5066 UINT64_C(0),
5067 UINT64_C(0),
5068 UINT64_C(0),
5069 UINT64_C(0),
5070 UINT64_C(0),
5071 UINT64_C(0),
5072 UINT64_C(0),
5073 UINT64_C(0),
5074 UINT64_C(0),
5075 UINT64_C(0),
5076 UINT64_C(0),
5077 UINT64_C(0),
5078 UINT64_C(0),
5079 UINT64_C(0),
5080 UINT64_C(0),
5081 UINT64_C(0),
5082 UINT64_C(0),
5083 UINT64_C(0),
5084 UINT64_C(0),
5085 UINT64_C(0),
5086 UINT64_C(0),
5087 UINT64_C(0),
5088 UINT64_C(0),
5089 UINT64_C(0),
5090 UINT64_C(0),
5091 UINT64_C(0),
5092 UINT64_C(0),
5093 UINT64_C(0),
5094 UINT64_C(0),
5095 UINT64_C(0),
5096 UINT64_C(0),
5097 UINT64_C(0),
5098 UINT64_C(0),
5099 UINT64_C(0),
5100 UINT64_C(0),
5101 UINT64_C(0),
5102 UINT64_C(0),
5103 UINT64_C(0),
5104 UINT64_C(0),
5105 UINT64_C(0),
5106 UINT64_C(0),
5107 UINT64_C(0),
5108 UINT64_C(0),
5109 UINT64_C(0),
5110 UINT64_C(0),
5111 UINT64_C(0),
5112 UINT64_C(0),
5113 UINT64_C(0),
5114 UINT64_C(0),
5115 UINT64_C(0),
5116 UINT64_C(0),
5117 UINT64_C(0),
5118 UINT64_C(0),
5119 UINT64_C(0),
5120 UINT64_C(0),
5121 UINT64_C(0),
5122 UINT64_C(0),
5123 UINT64_C(0),
5124 UINT64_C(0),
5125 UINT64_C(0),
5126 UINT64_C(0),
5127 UINT64_C(0),
5128 UINT64_C(0),
5129 UINT64_C(0),
5130 UINT64_C(0),
5131 UINT64_C(0),
5132 UINT64_C(0),
5133 UINT64_C(0),
5134 UINT64_C(0),
5135 UINT64_C(0),
5136 UINT64_C(0),
5137 UINT64_C(0),
5138 UINT64_C(0),
5139 UINT64_C(0),
5140 UINT64_C(0),
5141 UINT64_C(0),
5142 UINT64_C(0),
5143 UINT64_C(0),
5144 UINT64_C(0),
5145 UINT64_C(0),
5146 UINT64_C(0),
5147 UINT64_C(0),
5148 UINT64_C(0),
5149 UINT64_C(0),
5150 UINT64_C(0),
5151 UINT64_C(0),
5152 UINT64_C(0),
5153 UINT64_C(0),
5154 UINT64_C(0),
5155 UINT64_C(0),
5156 UINT64_C(0),
5157 UINT64_C(0),
5158 UINT64_C(0),
5159 UINT64_C(0),
5160 UINT64_C(0),
5161 UINT64_C(0),
5162 UINT64_C(0),
5163 UINT64_C(0),
5164 UINT64_C(0),
5165 UINT64_C(0),
5166 UINT64_C(0),
5167 UINT64_C(0),
5168 UINT64_C(0),
5169 UINT64_C(0),
5170 UINT64_C(0),
5171 UINT64_C(0),
5172 UINT64_C(0),
5173 UINT64_C(0),
5174 UINT64_C(0),
5175 UINT64_C(0),
5176 UINT64_C(0),
5177 UINT64_C(0),
5178 UINT64_C(0),
5179 UINT64_C(0),
5180 UINT64_C(0),
5181 UINT64_C(0),
5182 UINT64_C(0),
5183 UINT64_C(0),
5184 UINT64_C(0),
5185 UINT64_C(0),
5186 UINT64_C(0),
5187 UINT64_C(0),
5188 UINT64_C(0),
5189 UINT64_C(0),
5190 UINT64_C(0),
5191 UINT64_C(0),
5192 UINT64_C(0),
5193 UINT64_C(0),
5194 UINT64_C(0),
5195 UINT64_C(0),
5196 UINT64_C(0),
5197 UINT64_C(0),
5198 UINT64_C(0),
5199 UINT64_C(0),
5200 UINT64_C(0),
5201 UINT64_C(0),
5202 UINT64_C(0),
5203 UINT64_C(0),
5204 UINT64_C(0),
5205 UINT64_C(0),
5206 UINT64_C(0),
5207 UINT64_C(0),
5208 UINT64_C(0),
5209 UINT64_C(0),
5210 UINT64_C(0),
5211 UINT64_C(0),
5212 UINT64_C(0),
5213 UINT64_C(0),
5214 UINT64_C(0),
5215 UINT64_C(0),
5216 UINT64_C(0),
5217 UINT64_C(0),
5218 UINT64_C(0),
5219 UINT64_C(0),
5220 UINT64_C(0),
5221 UINT64_C(0),
5222 UINT64_C(0),
5223 UINT64_C(0),
5224 UINT64_C(0),
5225 UINT64_C(0),
5226 UINT64_C(0),
5227 UINT64_C(0),
5228 UINT64_C(0),
5229 UINT64_C(0),
5230 UINT64_C(0),
5231 UINT64_C(0),
5232 UINT64_C(0),
5233 UINT64_C(0),
5234 UINT64_C(0),
5235 UINT64_C(0),
5236 UINT64_C(0),
5237 UINT64_C(0),
5238 UINT64_C(0),
5239 UINT64_C(0),
5240 UINT64_C(0),
5241 UINT64_C(0),
5242 UINT64_C(0),
5243 UINT64_C(0),
5244 UINT64_C(0),
5245 UINT64_C(0),
5246 UINT64_C(0),
5247 UINT64_C(0),
5248 UINT64_C(0),
5249 UINT64_C(0),
5250 UINT64_C(0),
5251 UINT64_C(0),
5252 UINT64_C(0),
5253 UINT64_C(0),
5254 UINT64_C(0),
5255 UINT64_C(0),
5256 UINT64_C(0),
5257 UINT64_C(0),
5258 UINT64_C(0),
5259 UINT64_C(0),
5260 UINT64_C(0),
5261 UINT64_C(0),
5262 UINT64_C(0),
5263 UINT64_C(0),
5264 UINT64_C(0),
5265 UINT64_C(0),
5266 UINT64_C(0),
5267 UINT64_C(0),
5268 UINT64_C(0),
5269 UINT64_C(0),
5270 UINT64_C(0),
5271 UINT64_C(0),
5272 UINT64_C(0),
5273 UINT64_C(0),
5274 UINT64_C(0),
5275 UINT64_C(0),
5276 UINT64_C(0),
5277 UINT64_C(0),
5278 UINT64_C(0),
5279 UINT64_C(0),
5280 UINT64_C(0),
5281 UINT64_C(0),
5282 UINT64_C(0),
5283 UINT64_C(0),
5284 UINT64_C(0),
5285 UINT64_C(0),
5286 UINT64_C(0),
5287 UINT64_C(0),
5288 UINT64_C(0),
5289 UINT64_C(0),
5290 UINT64_C(0),
5291 UINT64_C(0),
5292 UINT64_C(0),
5293 UINT64_C(0),
5294 UINT64_C(0),
5295 UINT64_C(0),
5296 UINT64_C(0),
5297 UINT64_C(0),
5298 UINT64_C(0),
5299 UINT64_C(0),
5300 UINT64_C(0),
5301 UINT64_C(0),
5302 UINT64_C(0),
5303 UINT64_C(0),
5304 UINT64_C(0),
5305 UINT64_C(0),
5306 UINT64_C(0),
5307 UINT64_C(0),
5308 UINT64_C(0),
5309 UINT64_C(0),
5310 UINT64_C(0),
5311 UINT64_C(0),
5312 UINT64_C(0),
5313 UINT64_C(0),
5314 UINT64_C(0),
5315 UINT64_C(0),
5316 UINT64_C(0),
5317 UINT64_C(0),
5318 UINT64_C(0),
5319 UINT64_C(0),
5320 UINT64_C(0),
5321 UINT64_C(0),
5322 UINT64_C(0),
5323 UINT64_C(0),
5324 UINT64_C(0),
5325 UINT64_C(0),
5326 UINT64_C(0),
5327 UINT64_C(0),
5328 UINT64_C(0),
5329 UINT64_C(0),
5330 UINT64_C(0),
5331 UINT64_C(0),
5332 UINT64_C(0),
5333 UINT64_C(0),
5334 UINT64_C(0),
5335 UINT64_C(0),
5336 UINT64_C(0),
5337 UINT64_C(0),
5338 UINT64_C(0),
5339 UINT64_C(0),
5340 UINT64_C(0),
5341 UINT64_C(0),
5342 UINT64_C(0),
5343 UINT64_C(0),
5344 UINT64_C(0),
5345 UINT64_C(0),
5346 UINT64_C(0),
5347 UINT64_C(0),
5348 UINT64_C(0),
5349 UINT64_C(0),
5350 UINT64_C(0),
5351 UINT64_C(0),
5352 UINT64_C(0),
5353 UINT64_C(0),
5354 UINT64_C(0),
5355 UINT64_C(0),
5356 UINT64_C(0),
5357 UINT64_C(0),
5358 UINT64_C(0),
5359 UINT64_C(0),
5360 UINT64_C(0),
5361 UINT64_C(0),
5362 UINT64_C(0),
5363 UINT64_C(0),
5364 UINT64_C(0),
5365 UINT64_C(0),
5366 UINT64_C(0),
5367 UINT64_C(0),
5368 UINT64_C(0),
5369 UINT64_C(0),
5370 UINT64_C(0),
5371 UINT64_C(0),
5372 UINT64_C(0),
5373 UINT64_C(0),
5374 UINT64_C(0),
5375 UINT64_C(0),
5376 UINT64_C(0),
5377 UINT64_C(0),
5378 UINT64_C(0),
5379 UINT64_C(0),
5380 UINT64_C(0),
5381 UINT64_C(0),
5382 UINT64_C(0),
5383 UINT64_C(0),
5384 UINT64_C(0),
5385 UINT64_C(0),
5386 UINT64_C(0),
5387 UINT64_C(0),
5388 UINT64_C(0),
5389 UINT64_C(0),
5390 UINT64_C(0),
5391 UINT64_C(0),
5392 UINT64_C(0),
5393 UINT64_C(0),
5394 UINT64_C(0),
5395 UINT64_C(0),
5396 UINT64_C(0),
5397 UINT64_C(0),
5398 UINT64_C(0),
5399 UINT64_C(0),
5400 UINT64_C(0),
5401 UINT64_C(0),
5402 UINT64_C(0),
5403 UINT64_C(0),
5404 UINT64_C(0),
5405 UINT64_C(0),
5406 UINT64_C(0),
5407 UINT64_C(0),
5408 UINT64_C(0),
5409 UINT64_C(0),
5410 UINT64_C(0),
5411 UINT64_C(0),
5412 UINT64_C(0),
5413 UINT64_C(0),
5414 UINT64_C(0),
5415 UINT64_C(0),
5416 UINT64_C(0),
5417 UINT64_C(0),
5418 UINT64_C(0),
5419 UINT64_C(0),
5420 UINT64_C(0),
5421 UINT64_C(0),
5422 UINT64_C(0),
5423 UINT64_C(0),
5424 UINT64_C(0),
5425 UINT64_C(0),
5426 UINT64_C(0),
5427 UINT64_C(0),
5428 UINT64_C(0),
5429 UINT64_C(0),
5430 UINT64_C(0),
5431 UINT64_C(0),
5432 UINT64_C(0),
5433 UINT64_C(0),
5434 UINT64_C(0),
5435 UINT64_C(0),
5436 UINT64_C(0),
5437 UINT64_C(0),
5438 UINT64_C(0),
5439 UINT64_C(0),
5440 UINT64_C(0),
5441 UINT64_C(0),
5442 UINT64_C(0),
5443 UINT64_C(0),
5444 UINT64_C(0),
5445 UINT64_C(0),
5446 UINT64_C(0),
5447 UINT64_C(0),
5448 UINT64_C(0),
5449 UINT64_C(0),
5450 UINT64_C(0),
5451 UINT64_C(0),
5452 UINT64_C(0),
5453 UINT64_C(0),
5454 UINT64_C(0),
5455 UINT64_C(0),
5456 UINT64_C(0),
5457 UINT64_C(0),
5458 UINT64_C(0),
5459 UINT64_C(0),
5460 UINT64_C(0),
5461 UINT64_C(0),
5462 UINT64_C(0),
5463 UINT64_C(0),
5464 UINT64_C(0),
5465 UINT64_C(0),
5466 UINT64_C(0),
5467 UINT64_C(0),
5468 UINT64_C(0),
5469 UINT64_C(0),
5470 UINT64_C(0),
5471 UINT64_C(0),
5472 UINT64_C(0),
5473 UINT64_C(0),
5474 UINT64_C(0),
5475 UINT64_C(0),
5476 UINT64_C(0),
5477 UINT64_C(0),
5478 UINT64_C(0),
5479 UINT64_C(0),
5480 UINT64_C(0),
5481 UINT64_C(0),
5482 UINT64_C(0),
5483 UINT64_C(0),
5484 UINT64_C(0),
5485 UINT64_C(0),
5486 UINT64_C(0),
5487 UINT64_C(0),
5488 UINT64_C(0),
5489 UINT64_C(0),
5490 UINT64_C(0),
5491 UINT64_C(0),
5492 UINT64_C(0),
5493 UINT64_C(0),
5494 UINT64_C(0),
5495 UINT64_C(0),
5496 UINT64_C(0),
5497 UINT64_C(0),
5498 UINT64_C(0),
5499 UINT64_C(0),
5500 UINT64_C(0),
5501 UINT64_C(0),
5502 UINT64_C(0),
5503 UINT64_C(0),
5504 UINT64_C(0),
5505 UINT64_C(0),
5506 UINT64_C(0),
5507 UINT64_C(0),
5508 UINT64_C(0),
5509 UINT64_C(0),
5510 UINT64_C(0),
5511 UINT64_C(0),
5512 UINT64_C(0),
5513 UINT64_C(0),
5514 UINT64_C(0),
5515 UINT64_C(0),
5516 UINT64_C(0),
5517 UINT64_C(0),
5518 UINT64_C(0),
5519 UINT64_C(0),
5520 UINT64_C(0),
5521 UINT64_C(0),
5522 UINT64_C(0),
5523 UINT64_C(0),
5524 UINT64_C(0),
5525 UINT64_C(0),
5526 UINT64_C(0),
5527 UINT64_C(0),
5528 UINT64_C(0),
5529 UINT64_C(0),
5530 UINT64_C(0),
5531 UINT64_C(0),
5532 UINT64_C(0),
5533 UINT64_C(0),
5534 UINT64_C(0),
5535 UINT64_C(0),
5536 UINT64_C(0),
5537 UINT64_C(0),
5538 UINT64_C(0),
5539 UINT64_C(0),
5540 UINT64_C(0),
5541 UINT64_C(0),
5542 UINT64_C(0),
5543 UINT64_C(0),
5544 UINT64_C(0),
5545 UINT64_C(0),
5546 UINT64_C(0),
5547 UINT64_C(0),
5548 UINT64_C(0),
5549 UINT64_C(0),
5550 UINT64_C(0),
5551 UINT64_C(0),
5552 UINT64_C(0),
5553 UINT64_C(0),
5554 UINT64_C(0),
5555 UINT64_C(0),
5556 UINT64_C(0),
5557 UINT64_C(0),
5558 UINT64_C(0),
5559 UINT64_C(0),
5560 UINT64_C(0),
5561 UINT64_C(0),
5562 UINT64_C(0),
5563 UINT64_C(0),
5564 UINT64_C(0),
5565 UINT64_C(0),
5566 UINT64_C(0),
5567 UINT64_C(0),
5568 UINT64_C(0),
5569 UINT64_C(0),
5570 UINT64_C(0),
5571 UINT64_C(0),
5572 UINT64_C(0),
5573 UINT64_C(0),
5574 UINT64_C(0),
5575 UINT64_C(0),
5576 UINT64_C(0),
5577 UINT64_C(0),
5578 UINT64_C(0),
5579 UINT64_C(0),
5580 UINT64_C(0),
5581 UINT64_C(0),
5582 UINT64_C(0),
5583 UINT64_C(0),
5584 UINT64_C(0),
5585 UINT64_C(0),
5586 UINT64_C(0),
5587 UINT64_C(0),
5588 UINT64_C(0),
5589 UINT64_C(0),
5590 UINT64_C(0),
5591 UINT64_C(0),
5592 UINT64_C(0),
5593 UINT64_C(0),
5594 UINT64_C(0),
5595 UINT64_C(0),
5596 UINT64_C(0),
5597 UINT64_C(0),
5598 UINT64_C(0),
5599 UINT64_C(0),
5600 UINT64_C(0),
5601 UINT64_C(0),
5602 UINT64_C(0),
5603 UINT64_C(0),
5604 UINT64_C(0),
5605 UINT64_C(0),
5606 UINT64_C(0),
5607 UINT64_C(0),
5608 UINT64_C(0),
5609 UINT64_C(0),
5610 UINT64_C(0),
5611 UINT64_C(0),
5612 UINT64_C(0),
5613 UINT64_C(0),
5614 UINT64_C(0),
5615 UINT64_C(0),
5616 UINT64_C(0),
5617 UINT64_C(0),
5618 UINT64_C(0),
5619 UINT64_C(0),
5620 UINT64_C(0),
5621 UINT64_C(0),
5622 UINT64_C(0),
5623 UINT64_C(0),
5624 UINT64_C(0),
5625 UINT64_C(0),
5626 UINT64_C(0),
5627 UINT64_C(0),
5628 UINT64_C(0),
5629 UINT64_C(0),
5630 UINT64_C(0),
5631 UINT64_C(0),
5632 UINT64_C(0),
5633 UINT64_C(0),
5634 UINT64_C(0),
5635 UINT64_C(0),
5636 UINT64_C(0),
5637 UINT64_C(0),
5638 UINT64_C(0),
5639 UINT64_C(0),
5640 UINT64_C(0),
5641 UINT64_C(0),
5642 UINT64_C(0),
5643 UINT64_C(0),
5644 UINT64_C(0),
5645 UINT64_C(0),
5646 UINT64_C(0),
5647 UINT64_C(0),
5648 UINT64_C(0),
5649 UINT64_C(0),
5650 UINT64_C(0),
5651 UINT64_C(0),
5652 UINT64_C(0),
5653 UINT64_C(0),
5654 UINT64_C(0),
5655 UINT64_C(0),
5656 UINT64_C(0),
5657 UINT64_C(0),
5658 UINT64_C(0),
5659 UINT64_C(0),
5660 UINT64_C(0),
5661 UINT64_C(0),
5662 UINT64_C(0),
5663 UINT64_C(0),
5664 UINT64_C(0),
5665 UINT64_C(0),
5666 UINT64_C(0),
5667 UINT64_C(0),
5668 UINT64_C(0),
5669 UINT64_C(0),
5670 UINT64_C(0),
5671 UINT64_C(0),
5672 UINT64_C(0),
5673 UINT64_C(0),
5674 UINT64_C(0),
5675 UINT64_C(0),
5676 UINT64_C(0),
5677 UINT64_C(0),
5678 UINT64_C(0),
5679 UINT64_C(0),
5680 UINT64_C(0),
5681 UINT64_C(0),
5682 UINT64_C(0),
5683 UINT64_C(0),
5684 UINT64_C(0),
5685 UINT64_C(0),
5686 UINT64_C(0),
5687 UINT64_C(0),
5688 UINT64_C(0),
5689 UINT64_C(0),
5690 UINT64_C(0),
5691 UINT64_C(0),
5692 UINT64_C(0),
5693 UINT64_C(0),
5694 UINT64_C(0),
5695 UINT64_C(0),
5696 UINT64_C(0),
5697 UINT64_C(0),
5698 UINT64_C(0),
5699 UINT64_C(0),
5700 UINT64_C(0),
5701 UINT64_C(0),
5702 UINT64_C(0),
5703 UINT64_C(0),
5704 UINT64_C(0),
5705 UINT64_C(0),
5706 UINT64_C(0),
5707 UINT64_C(0),
5708 UINT64_C(0),
5709 UINT64_C(0),
5710 UINT64_C(0),
5711 UINT64_C(0),
5712 UINT64_C(0),
5713 UINT64_C(0),
5714 UINT64_C(0),
5715 UINT64_C(0),
5716 UINT64_C(0),
5717 UINT64_C(0),
5718 UINT64_C(0),
5719 UINT64_C(0),
5720 UINT64_C(0),
5721 UINT64_C(0),
5722 UINT64_C(0),
5723 UINT64_C(0),
5724 UINT64_C(0),
5725 UINT64_C(0),
5726 UINT64_C(0),
5727 UINT64_C(0),
5728 UINT64_C(0),
5729 UINT64_C(0),
5730 UINT64_C(0),
5731 UINT64_C(0),
5732 UINT64_C(0),
5733 UINT64_C(0),
5734 UINT64_C(0),
5735 UINT64_C(0),
5736 UINT64_C(0),
5737 UINT64_C(0),
5738 UINT64_C(0),
5739 UINT64_C(0),
5740 UINT64_C(0),
5741 UINT64_C(0),
5742 UINT64_C(0),
5743 UINT64_C(0),
5744 UINT64_C(0),
5745 UINT64_C(0),
5746 UINT64_C(0),
5747 UINT64_C(0),
5748 UINT64_C(0),
5749 UINT64_C(0),
5750 UINT64_C(0),
5751 UINT64_C(0),
5752 UINT64_C(0),
5753 UINT64_C(0),
5754 UINT64_C(0),
5755 UINT64_C(0),
5756 UINT64_C(0),
5757 UINT64_C(0),
5758 UINT64_C(0),
5759 UINT64_C(0),
5760 UINT64_C(0),
5761 UINT64_C(0),
5762 UINT64_C(0),
5763 UINT64_C(0),
5764 UINT64_C(0),
5765 UINT64_C(0),
5766 UINT64_C(0),
5767 UINT64_C(0),
5768 UINT64_C(0),
5769 UINT64_C(0),
5770 UINT64_C(0),
5771 UINT64_C(0),
5772 UINT64_C(0),
5773 UINT64_C(0),
5774 UINT64_C(0),
5775 UINT64_C(0),
5776 UINT64_C(0),
5777 UINT64_C(0),
5778 UINT64_C(0),
5779 UINT64_C(0),
5780 UINT64_C(0),
5781 UINT64_C(0),
5782 UINT64_C(0),
5783 UINT64_C(0),
5784 UINT64_C(0),
5785 UINT64_C(0),
5786 UINT64_C(0),
5787 UINT64_C(0),
5788 UINT64_C(0),
5789 UINT64_C(0),
5790 UINT64_C(0),
5791 UINT64_C(0),
5792 UINT64_C(0),
5793 UINT64_C(0),
5794 UINT64_C(0),
5795 UINT64_C(0),
5796 UINT64_C(0),
5797 UINT64_C(0),
5798 UINT64_C(0),
5799 UINT64_C(0),
5800 UINT64_C(0),
5801 UINT64_C(0),
5802 UINT64_C(0),
5803 UINT64_C(0),
5804 UINT64_C(0),
5805 UINT64_C(0),
5806 UINT64_C(0),
5807 UINT64_C(0),
5808 UINT64_C(0),
5809 UINT64_C(0),
5810 UINT64_C(0),
5811 UINT64_C(0),
5812 UINT64_C(0),
5813 UINT64_C(0),
5814 UINT64_C(0),
5815 UINT64_C(0),
5816 UINT64_C(0),
5817 UINT64_C(0),
5818 UINT64_C(0),
5819 UINT64_C(0),
5820 UINT64_C(0),
5821 UINT64_C(0),
5822 UINT64_C(0),
5823 UINT64_C(0),
5824 UINT64_C(0),
5825 UINT64_C(0),
5826 UINT64_C(0),
5827 UINT64_C(0),
5828 UINT64_C(0),
5829 UINT64_C(0),
5830 UINT64_C(0),
5831 UINT64_C(0),
5832 UINT64_C(0),
5833 UINT64_C(0),
5834 UINT64_C(0),
5835 UINT64_C(0),
5836 UINT64_C(0),
5837 UINT64_C(0),
5838 UINT64_C(0),
5839 UINT64_C(0),
5840 UINT64_C(0),
5841 UINT64_C(0),
5842 UINT64_C(0),
5843 UINT64_C(0),
5844 UINT64_C(0),
5845 UINT64_C(0),
5846 UINT64_C(0),
5847 UINT64_C(0),
5848 UINT64_C(0),
5849 UINT64_C(0),
5850 UINT64_C(0),
5851 UINT64_C(0),
5852 UINT64_C(0),
5853 UINT64_C(0),
5854 UINT64_C(0),
5855 UINT64_C(0),
5856 UINT64_C(0),
5857 UINT64_C(0),
5858 UINT64_C(0),
5859 UINT64_C(0),
5860 UINT64_C(0),
5861 UINT64_C(0),
5862 UINT64_C(0),
5863 UINT64_C(0),
5864 UINT64_C(0),
5865 UINT64_C(0),
5866 UINT64_C(0),
5867 UINT64_C(0),
5868 UINT64_C(0),
5869 UINT64_C(0),
5870 UINT64_C(0),
5871 UINT64_C(0),
5872 UINT64_C(0),
5873 UINT64_C(0),
5874 UINT64_C(0),
5875 UINT64_C(0),
5876 UINT64_C(0),
5877 UINT64_C(0),
5878 UINT64_C(0),
5879 UINT64_C(0),
5880 UINT64_C(0),
5881 UINT64_C(0),
5882 UINT64_C(0),
5883 UINT64_C(0),
5884 UINT64_C(0),
5885 UINT64_C(0),
5886 UINT64_C(0),
5887 UINT64_C(0),
5888 UINT64_C(0),
5889 UINT64_C(0),
5890 UINT64_C(0),
5891 UINT64_C(0),
5892 UINT64_C(0),
5893 UINT64_C(0),
5894 UINT64_C(0),
5895 UINT64_C(0),
5896 UINT64_C(0),
5897 UINT64_C(0),
5898 UINT64_C(0),
5899 UINT64_C(0),
5900 UINT64_C(0),
5901 UINT64_C(0),
5902 UINT64_C(0),
5903 UINT64_C(0),
5904 UINT64_C(0),
5905 UINT64_C(0),
5906 UINT64_C(0),
5907 UINT64_C(0),
5908 UINT64_C(0),
5909 UINT64_C(0),
5910 UINT64_C(0),
5911 UINT64_C(0),
5912 UINT64_C(0),
5913 UINT64_C(0),
5914 UINT64_C(0),
5915 UINT64_C(0),
5916 UINT64_C(0),
5917 UINT64_C(0),
5918 UINT64_C(0),
5919 UINT64_C(0),
5920 UINT64_C(0),
5921 UINT64_C(0),
5922 UINT64_C(0),
5923 UINT64_C(0),
5924 UINT64_C(0),
5925 UINT64_C(0),
5926 UINT64_C(0),
5927 UINT64_C(0),
5928 UINT64_C(0),
5929 UINT64_C(0),
5930 UINT64_C(0),
5931 UINT64_C(0),
5932 UINT64_C(0),
5933 UINT64_C(0),
5934 UINT64_C(0),
5935 UINT64_C(0),
5936 UINT64_C(0),
5937 UINT64_C(0),
5938 UINT64_C(0),
5939 UINT64_C(0),
5940 UINT64_C(0),
5941 UINT64_C(0),
5942 UINT64_C(0),
5943 UINT64_C(0),
5944 UINT64_C(0),
5945 UINT64_C(0),
5946 UINT64_C(0),
5947 UINT64_C(0),
5948 UINT64_C(0),
5949 UINT64_C(0),
5950 UINT64_C(0),
5951 UINT64_C(0),
5952 UINT64_C(0),
5953 UINT64_C(0),
5954 UINT64_C(0),
5955 UINT64_C(0),
5956 UINT64_C(0),
5957 UINT64_C(0),
5958 UINT64_C(0),
5959 UINT64_C(0),
5960 UINT64_C(0),
5961 UINT64_C(0),
5962 UINT64_C(0),
5963 UINT64_C(0),
5964 UINT64_C(0),
5965 UINT64_C(0),
5966 UINT64_C(0),
5967 UINT64_C(0),
5968 UINT64_C(0),
5969 UINT64_C(0),
5970 UINT64_C(0),
5971 UINT64_C(0),
5972 UINT64_C(0),
5973 UINT64_C(0),
5974 UINT64_C(0),
5975 UINT64_C(0),
5976 UINT64_C(0),
5977 UINT64_C(0),
5978 UINT64_C(0),
5979 UINT64_C(0),
5980 UINT64_C(0),
5981 UINT64_C(0),
5982 UINT64_C(0),
5983 UINT64_C(0),
5984 UINT64_C(0),
5985 UINT64_C(0),
5986 UINT64_C(0),
5987 UINT64_C(0),
5988 UINT64_C(0),
5989 UINT64_C(0),
5990 UINT64_C(0),
5991 UINT64_C(0),
5992 UINT64_C(0),
5993 UINT64_C(0),
5994 UINT64_C(0),
5995 UINT64_C(0),
5996 UINT64_C(0),
5997 UINT64_C(0),
5998 UINT64_C(0),
5999 UINT64_C(0),
6000 UINT64_C(0),
6001 UINT64_C(0),
6002 UINT64_C(0),
6003 UINT64_C(0),
6004 UINT64_C(0),
6005 UINT64_C(0),
6006 UINT64_C(0),
6007 UINT64_C(0),
6008 UINT64_C(0),
6009 UINT64_C(0),
6010 UINT64_C(0),
6011 UINT64_C(0),
6012 UINT64_C(0),
6013 UINT64_C(0),
6014 UINT64_C(0),
6015 UINT64_C(0),
6016 UINT64_C(0),
6017 UINT64_C(0),
6018 UINT64_C(0),
6019 UINT64_C(0),
6020 UINT64_C(0),
6021 UINT64_C(0),
6022 UINT64_C(0),
6023 UINT64_C(0),
6024 UINT64_C(0),
6025 UINT64_C(0),
6026 UINT64_C(0),
6027 UINT64_C(0),
6028 UINT64_C(0),
6029 UINT64_C(0),
6030 UINT64_C(0),
6031 UINT64_C(0),
6032 UINT64_C(0),
6033 UINT64_C(0),
6034 UINT64_C(0),
6035 UINT64_C(0),
6036 UINT64_C(0),
6037 UINT64_C(0),
6038 UINT64_C(0),
6039 UINT64_C(0),
6040 UINT64_C(0),
6041 UINT64_C(0),
6042 UINT64_C(0),
6043 UINT64_C(0),
6044 UINT64_C(0),
6045 UINT64_C(0),
6046 UINT64_C(0),
6047 UINT64_C(0),
6048 UINT64_C(0),
6049 UINT64_C(0),
6050 UINT64_C(0),
6051 UINT64_C(0),
6052 UINT64_C(0),
6053 UINT64_C(0),
6054 UINT64_C(0),
6055 UINT64_C(0),
6056 UINT64_C(0),
6057 UINT64_C(0),
6058 UINT64_C(0),
6059 UINT64_C(0),
6060 UINT64_C(0),
6061 UINT64_C(0),
6062 UINT64_C(0),
6063 UINT64_C(0),
6064 UINT64_C(0),
6065 UINT64_C(0),
6066 UINT64_C(0),
6067 UINT64_C(0),
6068 UINT64_C(0),
6069 UINT64_C(0),
6070 UINT64_C(0),
6071 UINT64_C(0),
6072 UINT64_C(0),
6073 UINT64_C(0),
6074 UINT64_C(0),
6075 UINT64_C(0),
6076 UINT64_C(0),
6077 UINT64_C(0),
6078 UINT64_C(0),
6079 UINT64_C(0),
6080 UINT64_C(0),
6081 UINT64_C(0),
6082 UINT64_C(0),
6083 UINT64_C(0),
6084 UINT64_C(0),
6085 UINT64_C(0),
6086 UINT64_C(0),
6087 UINT64_C(0),
6088 UINT64_C(0),
6089 UINT64_C(0),
6090 UINT64_C(0),
6091 UINT64_C(0),
6092 UINT64_C(0),
6093 UINT64_C(0),
6094 UINT64_C(0),
6095 UINT64_C(0),
6096 UINT64_C(0),
6097 UINT64_C(0),
6098 UINT64_C(0),
6099 UINT64_C(0),
6100 UINT64_C(0),
6101 UINT64_C(0),
6102 UINT64_C(0),
6103 UINT64_C(0),
6104 UINT64_C(0),
6105 UINT64_C(0),
6106 UINT64_C(0),
6107 UINT64_C(0),
6108 UINT64_C(0),
6109 UINT64_C(0),
6110 UINT64_C(0),
6111 UINT64_C(0),
6112 UINT64_C(0),
6113 UINT64_C(0),
6114 UINT64_C(0),
6115 UINT64_C(0),
6116 UINT64_C(0),
6117 UINT64_C(0),
6118 UINT64_C(0),
6119 UINT64_C(0),
6120 UINT64_C(0),
6121 UINT64_C(0),
6122 UINT64_C(0),
6123 UINT64_C(0),
6124 UINT64_C(0),
6125 UINT64_C(0),
6126 UINT64_C(0),
6127 UINT64_C(0),
6128 UINT64_C(0),
6129 UINT64_C(0),
6130 UINT64_C(0),
6131 UINT64_C(0),
6132 UINT64_C(0),
6133 UINT64_C(0),
6134 UINT64_C(0),
6135 UINT64_C(0),
6136 UINT64_C(0),
6137 UINT64_C(0),
6138 UINT64_C(0),
6139 UINT64_C(0),
6140 UINT64_C(0),
6141 UINT64_C(0),
6142 UINT64_C(0),
6143 UINT64_C(0),
6144 UINT64_C(0),
6145 UINT64_C(0),
6146 UINT64_C(0),
6147 UINT64_C(0),
6148 UINT64_C(0),
6149 UINT64_C(0),
6150 UINT64_C(0),
6151 UINT64_C(0),
6152 UINT64_C(0),
6153 UINT64_C(0),
6154 UINT64_C(0),
6155 UINT64_C(0),
6156 UINT64_C(0),
6157 UINT64_C(0),
6158 UINT64_C(0),
6159 UINT64_C(0),
6160 UINT64_C(0),
6161 UINT64_C(0),
6162 UINT64_C(0),
6163 UINT64_C(0),
6164 UINT64_C(0),
6165 UINT64_C(0),
6166 UINT64_C(0),
6167 UINT64_C(0),
6168 UINT64_C(0),
6169 UINT64_C(0),
6170 UINT64_C(0),
6171 UINT64_C(0),
6172 UINT64_C(0),
6173 UINT64_C(0),
6174 UINT64_C(0),
6175 UINT64_C(0),
6176 UINT64_C(0),
6177 UINT64_C(0),
6178 UINT64_C(0),
6179 UINT64_C(0),
6180 UINT64_C(0),
6181 UINT64_C(0),
6182 UINT64_C(0),
6183 UINT64_C(0),
6184 UINT64_C(0),
6185 UINT64_C(0),
6186 UINT64_C(0),
6187 UINT64_C(0),
6188 UINT64_C(0),
6189 UINT64_C(0),
6190 UINT64_C(0),
6191 UINT64_C(0),
6192 UINT64_C(0),
6193 UINT64_C(0),
6194 UINT64_C(0),
6195 UINT64_C(0),
6196 UINT64_C(0),
6197 UINT64_C(0),
6198 UINT64_C(0),
6199 UINT64_C(0),
6200 UINT64_C(0),
6201 UINT64_C(0),
6202 UINT64_C(0),
6203 UINT64_C(0),
6204 UINT64_C(0),
6205 UINT64_C(0),
6206 UINT64_C(0),
6207 UINT64_C(0),
6208 UINT64_C(0),
6209 UINT64_C(0),
6210 UINT64_C(0),
6211 UINT64_C(0),
6212 UINT64_C(0),
6213 UINT64_C(0),
6214 UINT64_C(0),
6215 UINT64_C(0),
6216 UINT64_C(0),
6217 UINT64_C(0),
6218 UINT64_C(0),
6219 UINT64_C(0),
6220 UINT64_C(0),
6221 UINT64_C(0),
6222 UINT64_C(0),
6223 UINT64_C(0),
6224 UINT64_C(0),
6225 UINT64_C(0),
6226 UINT64_C(0),
6227 UINT64_C(0),
6228 UINT64_C(0),
6229 UINT64_C(0),
6230 UINT64_C(0),
6231 UINT64_C(0),
6232 UINT64_C(0),
6233 UINT64_C(0),
6234 UINT64_C(0),
6235 UINT64_C(0),
6236 UINT64_C(0),
6237 UINT64_C(0),
6238 UINT64_C(0),
6239 UINT64_C(0),
6240 UINT64_C(0),
6241 UINT64_C(0),
6242 UINT64_C(0),
6243 UINT64_C(0),
6244 UINT64_C(0),
6245 UINT64_C(0),
6246 UINT64_C(0),
6247 UINT64_C(0),
6248 UINT64_C(0),
6249 UINT64_C(0),
6250 UINT64_C(0),
6251 UINT64_C(0),
6252 UINT64_C(0),
6253 UINT64_C(0),
6254 UINT64_C(0),
6255 UINT64_C(0),
6256 UINT64_C(0),
6257 UINT64_C(0),
6258 UINT64_C(0),
6259 UINT64_C(0),
6260 UINT64_C(0),
6261 UINT64_C(0),
6262 UINT64_C(0),
6263 UINT64_C(0),
6264 UINT64_C(0),
6265 UINT64_C(0),
6266 UINT64_C(0),
6267 UINT64_C(0),
6268 UINT64_C(0),
6269 UINT64_C(0),
6270 UINT64_C(0),
6271 UINT64_C(0),
6272 UINT64_C(0),
6273 UINT64_C(0),
6274 UINT64_C(0),
6275 UINT64_C(0),
6276 UINT64_C(0),
6277 UINT64_C(0),
6278 UINT64_C(0),
6279 UINT64_C(0),
6280 UINT64_C(0),
6281 UINT64_C(0),
6282 UINT64_C(0),
6283 UINT64_C(0),
6284 UINT64_C(0),
6285 UINT64_C(0),
6286 UINT64_C(0),
6287 UINT64_C(0),
6288 UINT64_C(0),
6289 UINT64_C(0),
6290 UINT64_C(0),
6291 UINT64_C(0),
6292 UINT64_C(0),
6293 UINT64_C(0),
6294 UINT64_C(0),
6295 UINT64_C(0),
6296 UINT64_C(0),
6297 UINT64_C(0),
6298 UINT64_C(0),
6299 UINT64_C(0),
6300 UINT64_C(0),
6301 UINT64_C(0),
6302 UINT64_C(0),
6303 UINT64_C(0),
6304 UINT64_C(0),
6305 UINT64_C(0),
6306 UINT64_C(0),
6307 UINT64_C(0),
6308 UINT64_C(0),
6309 UINT64_C(0),
6310 UINT64_C(0),
6311 UINT64_C(0),
6312 UINT64_C(0),
6313 UINT64_C(0),
6314 UINT64_C(0),
6315 UINT64_C(0),
6316 UINT64_C(0),
6317 UINT64_C(0),
6318 UINT64_C(0),
6319 UINT64_C(0),
6320 UINT64_C(0),
6321 UINT64_C(0),
6322 UINT64_C(0),
6323 UINT64_C(0),
6324 UINT64_C(0),
6325 UINT64_C(0),
6326 UINT64_C(0),
6327 UINT64_C(0),
6328 UINT64_C(0),
6329 UINT64_C(0),
6330 UINT64_C(0),
6331 UINT64_C(0),
6332 UINT64_C(0),
6333 UINT64_C(0),
6334 UINT64_C(0),
6335 UINT64_C(0),
6336 UINT64_C(0),
6337 UINT64_C(0),
6338 UINT64_C(0),
6339 UINT64_C(0),
6340 UINT64_C(0),
6341 UINT64_C(0),
6342 UINT64_C(0),
6343 UINT64_C(0),
6344 UINT64_C(0),
6345 UINT64_C(0),
6346 UINT64_C(0),
6347 UINT64_C(0),
6348 UINT64_C(0),
6349 UINT64_C(0),
6350 UINT64_C(0),
6351 UINT64_C(0),
6352 UINT64_C(0),
6353 UINT64_C(0),
6354 UINT64_C(0),
6355 UINT64_C(0),
6356 UINT64_C(0),
6357 UINT64_C(0),
6358 UINT64_C(0),
6359 UINT64_C(0),
6360 UINT64_C(0),
6361 UINT64_C(0),
6362 UINT64_C(0),
6363 UINT64_C(0),
6364 UINT64_C(0),
6365 UINT64_C(0),
6366 UINT64_C(0),
6367 UINT64_C(0),
6368 UINT64_C(0),
6369 UINT64_C(0),
6370 UINT64_C(0),
6371 UINT64_C(0),
6372 UINT64_C(0),
6373 UINT64_C(0),
6374 UINT64_C(0),
6375 UINT64_C(0),
6376 UINT64_C(0),
6377 UINT64_C(0),
6378 UINT64_C(0),
6379 UINT64_C(0),
6380 UINT64_C(0),
6381 UINT64_C(0),
6382 UINT64_C(0),
6383 UINT64_C(0),
6384 UINT64_C(0),
6385 UINT64_C(0),
6386 UINT64_C(0),
6387 UINT64_C(0),
6388 UINT64_C(0),
6389 UINT64_C(0),
6390 UINT64_C(0),
6391 UINT64_C(0),
6392 UINT64_C(0),
6393 UINT64_C(0),
6394 UINT64_C(0),
6395 UINT64_C(0),
6396 UINT64_C(0),
6397 UINT64_C(0),
6398 UINT64_C(0),
6399 UINT64_C(0),
6400 UINT64_C(0),
6401 UINT64_C(0),
6402 UINT64_C(0),
6403 UINT64_C(0),
6404 UINT64_C(0),
6405 UINT64_C(0),
6406 UINT64_C(0),
6407 UINT64_C(0),
6408 UINT64_C(0),
6409 UINT64_C(0),
6410 UINT64_C(0),
6411 UINT64_C(0),
6412 UINT64_C(0),
6413 UINT64_C(0),
6414 UINT64_C(0),
6415 UINT64_C(0),
6416 UINT64_C(0),
6417 UINT64_C(0),
6418 UINT64_C(0),
6419 UINT64_C(0),
6420 UINT64_C(0),
6421 UINT64_C(0),
6422 UINT64_C(0),
6423 UINT64_C(0),
6424 UINT64_C(0),
6425 UINT64_C(0),
6426 UINT64_C(0),
6427 UINT64_C(0),
6428 UINT64_C(0),
6429 UINT64_C(0),
6430 UINT64_C(0),
6431 UINT64_C(0),
6432 UINT64_C(0),
6433 UINT64_C(0),
6434 UINT64_C(0),
6435 UINT64_C(0),
6436 UINT64_C(0),
6437 UINT64_C(0),
6438 UINT64_C(0),
6439 UINT64_C(0),
6440 UINT64_C(0),
6441 UINT64_C(0),
6442 UINT64_C(0),
6443 UINT64_C(0),
6444 UINT64_C(0),
6445 UINT64_C(0),
6446 UINT64_C(0),
6447 UINT64_C(0),
6448 UINT64_C(0),
6449 UINT64_C(0),
6450 UINT64_C(0),
6451 UINT64_C(0),
6452 UINT64_C(0),
6453 UINT64_C(0),
6454 UINT64_C(0),
6455 UINT64_C(0),
6456 UINT64_C(0),
6457 UINT64_C(0),
6458 UINT64_C(0),
6459 UINT64_C(0),
6460 UINT64_C(0),
6461 UINT64_C(0),
6462 UINT64_C(0),
6463 UINT64_C(0),
6464 UINT64_C(0),
6465 UINT64_C(0),
6466 UINT64_C(0),
6467 UINT64_C(0),
6468 UINT64_C(0),
6469 UINT64_C(0),
6470 UINT64_C(0),
6471 UINT64_C(0),
6472 UINT64_C(0),
6473 UINT64_C(0),
6474 UINT64_C(0),
6475 UINT64_C(0),
6476 UINT64_C(0),
6477 UINT64_C(0),
6478 UINT64_C(0),
6479 UINT64_C(0),
6480 UINT64_C(0),
6481 UINT64_C(0),
6482 UINT64_C(0),
6483 UINT64_C(0),
6484 UINT64_C(0),
6485 UINT64_C(0),
6486 UINT64_C(0),
6487 UINT64_C(0),
6488 UINT64_C(0),
6489 UINT64_C(0),
6490 UINT64_C(0),
6491 UINT64_C(0),
6492 UINT64_C(0),
6493 UINT64_C(0),
6494 UINT64_C(0),
6495 UINT64_C(0),
6496 UINT64_C(0),
6497 UINT64_C(0),
6498 UINT64_C(0),
6499 UINT64_C(0),
6500 UINT64_C(0),
6501 UINT64_C(0),
6502 UINT64_C(0),
6503 UINT64_C(0),
6504 UINT64_C(0),
6505 UINT64_C(0),
6506 UINT64_C(0),
6507 UINT64_C(0),
6508 UINT64_C(0),
6509 UINT64_C(0),
6510 UINT64_C(0),
6511 UINT64_C(0),
6512 UINT64_C(0),
6513 UINT64_C(0),
6514 UINT64_C(0),
6515 UINT64_C(0),
6516 UINT64_C(0),
6517 UINT64_C(0),
6518 UINT64_C(0),
6519 UINT64_C(0),
6520 UINT64_C(0),
6521 UINT64_C(0),
6522 UINT64_C(0),
6523 UINT64_C(0),
6524 UINT64_C(0),
6525 UINT64_C(0),
6526 UINT64_C(0),
6527 UINT64_C(0),
6528 UINT64_C(0),
6529 UINT64_C(0),
6530 UINT64_C(0),
6531 UINT64_C(0),
6532 UINT64_C(0),
6533 UINT64_C(0),
6534 UINT64_C(0),
6535 UINT64_C(0),
6536 UINT64_C(0),
6537 UINT64_C(0),
6538 UINT64_C(0),
6539 UINT64_C(0),
6540 UINT64_C(0),
6541 UINT64_C(0),
6542 UINT64_C(0),
6543 UINT64_C(0),
6544 UINT64_C(0),
6545 UINT64_C(0),
6546 UINT64_C(0),
6547 UINT64_C(0),
6548 UINT64_C(0),
6549 UINT64_C(0),
6550 UINT64_C(0),
6551 UINT64_C(0),
6552 UINT64_C(0),
6553 UINT64_C(0),
6554 UINT64_C(0),
6555 UINT64_C(0),
6556 UINT64_C(0),
6557 UINT64_C(0),
6558 UINT64_C(0),
6559 UINT64_C(0),
6560 UINT64_C(0),
6561 UINT64_C(0),
6562 UINT64_C(0),
6563 UINT64_C(0),
6564 UINT64_C(0),
6565 UINT64_C(0),
6566 UINT64_C(0),
6567 UINT64_C(0),
6568 UINT64_C(0),
6569 UINT64_C(0),
6570 UINT64_C(0),
6571 UINT64_C(0),
6572 UINT64_C(0),
6573 UINT64_C(0),
6574 UINT64_C(0),
6575 UINT64_C(0),
6576 UINT64_C(0),
6577 UINT64_C(0),
6578 UINT64_C(0),
6579 UINT64_C(0),
6580 UINT64_C(0),
6581 UINT64_C(0),
6582 UINT64_C(0),
6583 UINT64_C(0),
6584 UINT64_C(0),
6585 UINT64_C(0),
6586 UINT64_C(0),
6587 UINT64_C(0),
6588 UINT64_C(0),
6589 UINT64_C(0),
6590 UINT64_C(0),
6591 UINT64_C(0),
6592 UINT64_C(0),
6593 UINT64_C(0),
6594 UINT64_C(0),
6595 UINT64_C(0),
6596 UINT64_C(0),
6597 UINT64_C(0),
6598 UINT64_C(0),
6599 UINT64_C(0),
6600 UINT64_C(0),
6601 UINT64_C(0),
6602 UINT64_C(0),
6603 UINT64_C(0),
6604 UINT64_C(0),
6605 UINT64_C(0),
6606 UINT64_C(0),
6607 UINT64_C(0),
6608 UINT64_C(0),
6609 UINT64_C(0),
6610 UINT64_C(0),
6611 UINT64_C(0),
6612 UINT64_C(0),
6613 UINT64_C(0),
6614 UINT64_C(0),
6615 UINT64_C(0),
6616 UINT64_C(0),
6617 UINT64_C(0),
6618 UINT64_C(0),
6619 UINT64_C(0),
6620 UINT64_C(0),
6621 UINT64_C(0),
6622 UINT64_C(0),
6623 UINT64_C(0),
6624 UINT64_C(0),
6625 UINT64_C(0),
6626 UINT64_C(0),
6627 UINT64_C(0),
6628 UINT64_C(0),
6629 UINT64_C(0),
6630 UINT64_C(0),
6631 UINT64_C(0),
6632 UINT64_C(0),
6633 UINT64_C(0),
6634 UINT64_C(0),
6635 UINT64_C(0),
6636 UINT64_C(0),
6637 UINT64_C(0),
6638 UINT64_C(0),
6639 UINT64_C(0),
6640 UINT64_C(0),
6641 UINT64_C(0),
6642 UINT64_C(0),
6643 UINT64_C(0),
6644 UINT64_C(0),
6645 UINT64_C(0),
6646 UINT64_C(0),
6647 UINT64_C(0),
6648 UINT64_C(0),
6649 UINT64_C(0),
6650 UINT64_C(0),
6651 UINT64_C(0),
6652 UINT64_C(0),
6653 UINT64_C(0),
6654 UINT64_C(0),
6655 UINT64_C(0),
6656 UINT64_C(0),
6657 UINT64_C(0),
6658 UINT64_C(0),
6659 UINT64_C(0),
6660 UINT64_C(0),
6661 UINT64_C(0),
6662 UINT64_C(0),
6663 UINT64_C(0),
6664 UINT64_C(0),
6665 UINT64_C(0),
6666 UINT64_C(0),
6667 UINT64_C(0),
6668 UINT64_C(0),
6669 UINT64_C(0),
6670 UINT64_C(0),
6671 UINT64_C(0),
6672 UINT64_C(0),
6673 UINT64_C(0),
6674 UINT64_C(0),
6675 UINT64_C(0),
6676 UINT64_C(0),
6677 UINT64_C(0),
6678 UINT64_C(0),
6679 UINT64_C(0),
6680 UINT64_C(0),
6681 UINT64_C(0),
6682 UINT64_C(0),
6683 UINT64_C(0),
6684 UINT64_C(0),
6685 UINT64_C(0),
6686 UINT64_C(0),
6687 UINT64_C(0),
6688 UINT64_C(0),
6689 UINT64_C(0),
6690 UINT64_C(0),
6691 UINT64_C(0),
6692 UINT64_C(0),
6693 UINT64_C(0),
6694 UINT64_C(0),
6695 UINT64_C(0),
6696 UINT64_C(0),
6697 UINT64_C(0),
6698 UINT64_C(0),
6699 UINT64_C(0),
6700 UINT64_C(0),
6701 UINT64_C(0),
6702 UINT64_C(0),
6703 UINT64_C(0),
6704 UINT64_C(0),
6705 UINT64_C(0),
6706 UINT64_C(0),
6707 UINT64_C(0),
6708 UINT64_C(0),
6709 UINT64_C(0),
6710 UINT64_C(0),
6711 UINT64_C(0),
6712 UINT64_C(0),
6713 UINT64_C(0),
6714 UINT64_C(0),
6715 UINT64_C(0),
6716 UINT64_C(0),
6717 UINT64_C(0),
6718 UINT64_C(0),
6719 UINT64_C(0),
6720 UINT64_C(0),
6721 UINT64_C(0),
6722 UINT64_C(0),
6723 UINT64_C(0),
6724 UINT64_C(0),
6725 UINT64_C(0),
6726 UINT64_C(0),
6727 UINT64_C(0),
6728 UINT64_C(0),
6729 UINT64_C(0),
6730 UINT64_C(0),
6731 UINT64_C(0),
6732 UINT64_C(0),
6733 UINT64_C(0),
6734 UINT64_C(0),
6735 UINT64_C(0),
6736 UINT64_C(0),
6737 UINT64_C(0),
6738 UINT64_C(0),
6739 UINT64_C(0),
6740 UINT64_C(0),
6741 UINT64_C(0),
6742 UINT64_C(0),
6743 UINT64_C(0),
6744 UINT64_C(0),
6745 UINT64_C(0),
6746 UINT64_C(0),
6747 UINT64_C(0),
6748 UINT64_C(0),
6749 UINT64_C(0),
6750 UINT64_C(0),
6751 UINT64_C(0),
6752 UINT64_C(0),
6753 UINT64_C(0),
6754 UINT64_C(0),
6755 UINT64_C(0),
6756 UINT64_C(0),
6757 UINT64_C(0),
6758 UINT64_C(0),
6759 UINT64_C(0),
6760 UINT64_C(0),
6761 UINT64_C(0),
6762 UINT64_C(0),
6763 UINT64_C(0),
6764 UINT64_C(0),
6765 UINT64_C(0),
6766 UINT64_C(0),
6767 UINT64_C(0),
6768 UINT64_C(0),
6769 UINT64_C(0),
6770 UINT64_C(0),
6771 UINT64_C(0),
6772 UINT64_C(0),
6773 UINT64_C(0),
6774 UINT64_C(0),
6775 UINT64_C(0),
6776 UINT64_C(0),
6777 UINT64_C(0),
6778 UINT64_C(0),
6779 UINT64_C(0),
6780 UINT64_C(0),
6781 UINT64_C(0),
6782 UINT64_C(0),
6783 UINT64_C(0),
6784 UINT64_C(0),
6785 UINT64_C(0),
6786 UINT64_C(0),
6787 UINT64_C(0),
6788 UINT64_C(0),
6789 UINT64_C(0),
6790 UINT64_C(0),
6791 UINT64_C(0),
6792 UINT64_C(0),
6793 UINT64_C(0),
6794 UINT64_C(0),
6795 UINT64_C(0),
6796 UINT64_C(0),
6797 UINT64_C(0),
6798 UINT64_C(0),
6799 UINT64_C(0),
6800 UINT64_C(0),
6801 UINT64_C(0),
6802 UINT64_C(0),
6803 UINT64_C(0),
6804 UINT64_C(0),
6805 UINT64_C(0),
6806 UINT64_C(0),
6807 UINT64_C(0),
6808 UINT64_C(0),
6809 UINT64_C(0),
6810 UINT64_C(0),
6811 UINT64_C(0),
6812 UINT64_C(0),
6813 UINT64_C(0),
6814 UINT64_C(0),
6815 UINT64_C(0),
6816 UINT64_C(0),
6817 UINT64_C(0),
6818 UINT64_C(0),
6819 UINT64_C(0),
6820 UINT64_C(0),
6821 UINT64_C(0),
6822 UINT64_C(0),
6823 UINT64_C(0),
6824 UINT64_C(0),
6825 UINT64_C(0),
6826 UINT64_C(0),
6827 UINT64_C(0),
6828 UINT64_C(0),
6829 UINT64_C(0),
6830 UINT64_C(0),
6831 UINT64_C(0),
6832 UINT64_C(0),
6833 UINT64_C(0),
6834 UINT64_C(0),
6835 UINT64_C(0),
6836 UINT64_C(0),
6837 UINT64_C(0),
6838 UINT64_C(0),
6839 UINT64_C(0),
6840 UINT64_C(0),
6841 UINT64_C(0),
6842 UINT64_C(0),
6843 UINT64_C(0),
6844 UINT64_C(0),
6845 UINT64_C(0),
6846 UINT64_C(0),
6847 UINT64_C(0),
6848 UINT64_C(0),
6849 UINT64_C(0),
6850 UINT64_C(0),
6851 UINT64_C(0),
6852 UINT64_C(0),
6853 UINT64_C(0),
6854 UINT64_C(0),
6855 UINT64_C(0),
6856 UINT64_C(0),
6857 UINT64_C(0),
6858 UINT64_C(0),
6859 UINT64_C(0),
6860 UINT64_C(0),
6861 UINT64_C(0),
6862 UINT64_C(0),
6863 UINT64_C(0),
6864 UINT64_C(0),
6865 UINT64_C(0),
6866 UINT64_C(0),
6867 UINT64_C(0),
6868 UINT64_C(0),
6869 UINT64_C(0),
6870 UINT64_C(0),
6871 UINT64_C(0),
6872 UINT64_C(0),
6873 UINT64_C(0),
6874 UINT64_C(0),
6875 UINT64_C(0),
6876 UINT64_C(0),
6877 UINT64_C(0),
6878 UINT64_C(0),
6879 UINT64_C(0),
6880 UINT64_C(0),
6881 UINT64_C(0),
6882 UINT64_C(0),
6883 UINT64_C(0),
6884 UINT64_C(0),
6885 UINT64_C(0),
6886 UINT64_C(0),
6887 UINT64_C(0),
6888 UINT64_C(0),
6889 UINT64_C(0),
6890 UINT64_C(0),
6891 UINT64_C(0),
6892 UINT64_C(0),
6893 UINT64_C(0),
6894 UINT64_C(0),
6895 UINT64_C(0),
6896 UINT64_C(0),
6897 UINT64_C(0),
6898 UINT64_C(0),
6899 UINT64_C(0),
6900 UINT64_C(0),
6901 UINT64_C(0),
6902 UINT64_C(0),
6903 UINT64_C(0),
6904 UINT64_C(0),
6905 UINT64_C(0),
6906 UINT64_C(0),
6907 UINT64_C(0),
6908 UINT64_C(0),
6909 UINT64_C(0),
6910 UINT64_C(0),
6911 UINT64_C(0),
6912 UINT64_C(0),
6913 UINT64_C(0),
6914 UINT64_C(0),
6915 UINT64_C(0),
6916 UINT64_C(0),
6917 UINT64_C(0),
6918 UINT64_C(0),
6919 UINT64_C(0),
6920 UINT64_C(0),
6921 UINT64_C(0),
6922 UINT64_C(0),
6923 UINT64_C(0),
6924 UINT64_C(0),
6925 UINT64_C(0),
6926 UINT64_C(0),
6927 UINT64_C(0),
6928 UINT64_C(0),
6929 UINT64_C(0),
6930 UINT64_C(0),
6931 UINT64_C(0),
6932 UINT64_C(0),
6933 UINT64_C(0),
6934 UINT64_C(0),
6935 UINT64_C(0),
6936 UINT64_C(0),
6937 UINT64_C(0),
6938 UINT64_C(0),
6939 UINT64_C(0),
6940 UINT64_C(0),
6941 UINT64_C(0),
6942 UINT64_C(0),
6943 UINT64_C(0),
6944 UINT64_C(0),
6945 UINT64_C(0),
6946 UINT64_C(0),
6947 UINT64_C(0),
6948 UINT64_C(0),
6949 UINT64_C(0),
6950 UINT64_C(0),
6951 UINT64_C(0),
6952 UINT64_C(0),
6953 UINT64_C(0),
6954 UINT64_C(0),
6955 UINT64_C(0),
6956 UINT64_C(0),
6957 UINT64_C(0),
6958 UINT64_C(0),
6959 UINT64_C(0),
6960 UINT64_C(0),
6961 UINT64_C(0),
6962 UINT64_C(0),
6963 UINT64_C(0),
6964 UINT64_C(0),
6965 UINT64_C(0),
6966 UINT64_C(0),
6967 UINT64_C(0),
6968 UINT64_C(0),
6969 UINT64_C(0),
6970 UINT64_C(0),
6971 UINT64_C(0),
6972 UINT64_C(0),
6973 UINT64_C(0),
6974 UINT64_C(0),
6975 UINT64_C(0),
6976 UINT64_C(0),
6977 UINT64_C(0),
6978 UINT64_C(0),
6979 UINT64_C(0),
6980 UINT64_C(0),
6981 UINT64_C(0),
6982 UINT64_C(0),
6983 UINT64_C(0),
6984 UINT64_C(0),
6985 UINT64_C(0),
6986 UINT64_C(0),
6987 UINT64_C(0),
6988 UINT64_C(0),
6989 UINT64_C(0),
6990 UINT64_C(0),
6991 UINT64_C(0),
6992 UINT64_C(0),
6993 UINT64_C(0),
6994 UINT64_C(0),
6995 UINT64_C(0),
6996 UINT64_C(0),
6997 UINT64_C(0),
6998 UINT64_C(0),
6999 UINT64_C(0),
7000 UINT64_C(0),
7001 UINT64_C(0),
7002 UINT64_C(0),
7003 UINT64_C(0),
7004 UINT64_C(0),
7005 UINT64_C(0),
7006 UINT64_C(0),
7007 UINT64_C(0),
7008 UINT64_C(0),
7009 UINT64_C(0),
7010 UINT64_C(0),
7011 UINT64_C(0),
7012 UINT64_C(0),
7013 UINT64_C(0),
7014 UINT64_C(0),
7015 UINT64_C(0),
7016 UINT64_C(0),
7017 UINT64_C(0),
7018 UINT64_C(0),
7019 UINT64_C(0),
7020 UINT64_C(0),
7021 UINT64_C(0),
7022 UINT64_C(0),
7023 UINT64_C(0),
7024 UINT64_C(0),
7025 UINT64_C(0),
7026 UINT64_C(0),
7027 UINT64_C(0),
7028 UINT64_C(0),
7029 UINT64_C(0),
7030 UINT64_C(0),
7031 UINT64_C(0),
7032 UINT64_C(0),
7033 UINT64_C(0),
7034 UINT64_C(0),
7035 UINT64_C(0),
7036 UINT64_C(0),
7037 UINT64_C(0),
7038 UINT64_C(0),
7039 UINT64_C(0),
7040 UINT64_C(0),
7041 UINT64_C(0),
7042 UINT64_C(0),
7043 UINT64_C(0),
7044 UINT64_C(0),
7045 UINT64_C(0),
7046 UINT64_C(0),
7047 UINT64_C(0),
7048 UINT64_C(0),
7049 UINT64_C(0),
7050 UINT64_C(0),
7051 UINT64_C(0),
7052 UINT64_C(0),
7053 UINT64_C(0),
7054 UINT64_C(0),
7055 UINT64_C(0),
7056 UINT64_C(0),
7057 UINT64_C(0),
7058 UINT64_C(0),
7059 UINT64_C(0),
7060 UINT64_C(0),
7061 UINT64_C(0),
7062 UINT64_C(0),
7063 UINT64_C(0),
7064 UINT64_C(0),
7065 UINT64_C(0),
7066 UINT64_C(0),
7067 UINT64_C(0),
7068 UINT64_C(0),
7069 UINT64_C(0),
7070 UINT64_C(0),
7071 UINT64_C(0),
7072 UINT64_C(0),
7073 UINT64_C(0),
7074 UINT64_C(0),
7075 UINT64_C(0),
7076 UINT64_C(0),
7077 UINT64_C(0),
7078 UINT64_C(0),
7079 UINT64_C(0),
7080 UINT64_C(0),
7081 UINT64_C(0),
7082 UINT64_C(0),
7083 UINT64_C(0),
7084 UINT64_C(0),
7085 UINT64_C(0),
7086 UINT64_C(0),
7087 UINT64_C(0),
7088 UINT64_C(0),
7089 UINT64_C(0),
7090 UINT64_C(0),
7091 UINT64_C(0),
7092 UINT64_C(0),
7093 UINT64_C(0),
7094 UINT64_C(0),
7095 UINT64_C(0),
7096 UINT64_C(0),
7097 UINT64_C(0),
7098 UINT64_C(0),
7099 UINT64_C(0),
7100 UINT64_C(0),
7101 UINT64_C(0),
7102 UINT64_C(0),
7103 UINT64_C(0),
7104 UINT64_C(0),
7105 UINT64_C(0),
7106 UINT64_C(0),
7107 UINT64_C(0),
7108 UINT64_C(0),
7109 UINT64_C(0),
7110 UINT64_C(0),
7111 UINT64_C(0),
7112 UINT64_C(0),
7113 UINT64_C(0),
7114 UINT64_C(0),
7115 UINT64_C(0),
7116 UINT64_C(0),
7117 UINT64_C(0),
7118 UINT64_C(0),
7119 UINT64_C(0),
7120 UINT64_C(0),
7121 UINT64_C(0),
7122 UINT64_C(0),
7123 UINT64_C(0),
7124 UINT64_C(0),
7125 UINT64_C(0),
7126 UINT64_C(0),
7127 UINT64_C(0),
7128 UINT64_C(0),
7129 UINT64_C(0),
7130 UINT64_C(0),
7131 UINT64_C(0),
7132 UINT64_C(0),
7133 UINT64_C(0),
7134 UINT64_C(0),
7135 UINT64_C(0),
7136 UINT64_C(0),
7137 UINT64_C(0),
7138 UINT64_C(0),
7139 UINT64_C(0),
7140 UINT64_C(0),
7141 UINT64_C(0),
7142 UINT64_C(0),
7143 UINT64_C(0),
7144 UINT64_C(0),
7145 UINT64_C(0),
7146 UINT64_C(0),
7147 UINT64_C(0),
7148 UINT64_C(0),
7149 UINT64_C(0),
7150 UINT64_C(0),
7151 UINT64_C(0),
7152 UINT64_C(0),
7153 UINT64_C(0),
7154 UINT64_C(0),
7155 UINT64_C(0),
7156 UINT64_C(0),
7157 UINT64_C(0),
7158 UINT64_C(0),
7159 UINT64_C(0),
7160 UINT64_C(0),
7161 UINT64_C(0),
7162 UINT64_C(0),
7163 UINT64_C(0),
7164 UINT64_C(0),
7165 UINT64_C(0),
7166 UINT64_C(0),
7167 UINT64_C(0),
7168 UINT64_C(0),
7169 UINT64_C(0),
7170 UINT64_C(0),
7171 UINT64_C(0),
7172 UINT64_C(0),
7173 UINT64_C(0),
7174 UINT64_C(0),
7175 UINT64_C(0),
7176 UINT64_C(0),
7177 UINT64_C(0),
7178 UINT64_C(0),
7179 UINT64_C(0),
7180 UINT64_C(0),
7181 UINT64_C(0),
7182 UINT64_C(0),
7183 UINT64_C(0),
7184 UINT64_C(0),
7185 UINT64_C(0),
7186 UINT64_C(0),
7187 UINT64_C(0),
7188 UINT64_C(0),
7189 UINT64_C(0),
7190 UINT64_C(0),
7191 UINT64_C(0),
7192 UINT64_C(0),
7193 UINT64_C(0),
7194 UINT64_C(0),
7195 UINT64_C(0),
7196 UINT64_C(0),
7197 UINT64_C(0),
7198 UINT64_C(0),
7199 UINT64_C(0),
7200 UINT64_C(0),
7201 UINT64_C(0),
7202 UINT64_C(0),
7203 UINT64_C(0),
7204 UINT64_C(0),
7205 UINT64_C(0),
7206 UINT64_C(0),
7207 UINT64_C(0),
7208 UINT64_C(0),
7209 UINT64_C(0),
7210 UINT64_C(0),
7211 UINT64_C(0),
7212 UINT64_C(0),
7213 UINT64_C(0),
7214 UINT64_C(0),
7215 UINT64_C(0),
7216 UINT64_C(0),
7217 UINT64_C(0),
7218 UINT64_C(0),
7219 UINT64_C(0),
7220 UINT64_C(0),
7221 UINT64_C(0),
7222 UINT64_C(0),
7223 UINT64_C(0),
7224 UINT64_C(0),
7225 UINT64_C(0),
7226 UINT64_C(0),
7227 UINT64_C(0),
7228 UINT64_C(0),
7229 UINT64_C(0),
7230 UINT64_C(0),
7231 UINT64_C(0),
7232 UINT64_C(0),
7233 UINT64_C(0),
7234 UINT64_C(0),
7235 UINT64_C(0),
7236 UINT64_C(0),
7237 UINT64_C(0),
7238 UINT64_C(0),
7239 UINT64_C(0),
7240 UINT64_C(0),
7241 UINT64_C(0),
7242 UINT64_C(0),
7243 UINT64_C(0),
7244 UINT64_C(0),
7245 UINT64_C(0),
7246 UINT64_C(0),
7247 UINT64_C(0),
7248 UINT64_C(0),
7249 UINT64_C(0),
7250 UINT64_C(0),
7251 UINT64_C(0),
7252 UINT64_C(0),
7253 UINT64_C(0),
7254 UINT64_C(0),
7255 UINT64_C(0),
7256 UINT64_C(0),
7257 UINT64_C(0),
7258 UINT64_C(0),
7259 UINT64_C(0),
7260 UINT64_C(0),
7261 UINT64_C(0),
7262 UINT64_C(0),
7263 UINT64_C(0),
7264 UINT64_C(0),
7265 UINT64_C(0),
7266 UINT64_C(0),
7267 UINT64_C(0),
7268 UINT64_C(0),
7269 UINT64_C(0),
7270 UINT64_C(0),
7271 UINT64_C(0),
7272 UINT64_C(0),
7273 UINT64_C(0),
7274 UINT64_C(0),
7275 UINT64_C(0),
7276 UINT64_C(0),
7277 UINT64_C(0),
7278 UINT64_C(0),
7279 UINT64_C(0),
7280 UINT64_C(0),
7281 UINT64_C(0),
7282 UINT64_C(0),
7283 UINT64_C(0),
7284 UINT64_C(0),
7285 UINT64_C(0),
7286 UINT64_C(0),
7287 UINT64_C(0),
7288 UINT64_C(0),
7289 UINT64_C(0),
7290 UINT64_C(0),
7291 UINT64_C(0),
7292 UINT64_C(0),
7293 UINT64_C(0),
7294 UINT64_C(0),
7295 UINT64_C(0),
7296 UINT64_C(0),
7297 UINT64_C(0),
7298 UINT64_C(0),
7299 UINT64_C(0),
7300 UINT64_C(0),
7301 UINT64_C(0),
7302 UINT64_C(0),
7303 UINT64_C(0),
7304 UINT64_C(0),
7305 UINT64_C(0),
7306 UINT64_C(0),
7307 UINT64_C(0),
7308 UINT64_C(0),
7309 UINT64_C(0),
7310 UINT64_C(0),
7311 UINT64_C(0),
7312 UINT64_C(0),
7313 UINT64_C(0),
7314 UINT64_C(0),
7315 UINT64_C(0),
7316 UINT64_C(0),
7317 UINT64_C(0),
7318 UINT64_C(0),
7319 UINT64_C(0),
7320 UINT64_C(0),
7321 UINT64_C(0),
7322 UINT64_C(0),
7323 UINT64_C(0),
7324 UINT64_C(0),
7325 UINT64_C(0),
7326 UINT64_C(0),
7327 UINT64_C(0),
7328 UINT64_C(0),
7329 UINT64_C(0),
7330 UINT64_C(0),
7331 UINT64_C(0),
7332 UINT64_C(0),
7333 UINT64_C(0),
7334 UINT64_C(0),
7335 UINT64_C(0),
7336 UINT64_C(0),
7337 UINT64_C(0),
7338 UINT64_C(0),
7339 UINT64_C(0),
7340 UINT64_C(0),
7341 UINT64_C(0),
7342 UINT64_C(0),
7343 UINT64_C(0),
7344 UINT64_C(0),
7345 UINT64_C(0),
7346 UINT64_C(0),
7347 UINT64_C(0),
7348 UINT64_C(0),
7349 UINT64_C(0),
7350 UINT64_C(0),
7351 UINT64_C(0),
7352 UINT64_C(0),
7353 UINT64_C(0),
7354 UINT64_C(0),
7355 UINT64_C(0),
7356 UINT64_C(0),
7357 UINT64_C(0),
7358 UINT64_C(0),
7359 UINT64_C(0),
7360 UINT64_C(0),
7361 UINT64_C(0),
7362 UINT64_C(0),
7363 UINT64_C(0),
7364 UINT64_C(0),
7365 UINT64_C(0),
7366 UINT64_C(0),
7367 UINT64_C(0),
7368 UINT64_C(0),
7369 UINT64_C(0),
7370 UINT64_C(0),
7371 UINT64_C(0),
7372 UINT64_C(0),
7373 UINT64_C(0),
7374 UINT64_C(0),
7375 UINT64_C(0),
7376 UINT64_C(0),
7377 UINT64_C(0),
7378 UINT64_C(0),
7379 UINT64_C(0),
7380 UINT64_C(0),
7381 UINT64_C(0),
7382 UINT64_C(0),
7383 UINT64_C(0),
7384 UINT64_C(0),
7385 UINT64_C(0),
7386 UINT64_C(0),
7387 UINT64_C(0),
7388 UINT64_C(0),
7389 UINT64_C(0),
7390 UINT64_C(0),
7391 UINT64_C(0),
7392 UINT64_C(0),
7393 UINT64_C(0),
7394 UINT64_C(0),
7395 UINT64_C(0),
7396 UINT64_C(0),
7397 UINT64_C(0),
7398 UINT64_C(0),
7399 UINT64_C(0),
7400 UINT64_C(0),
7401 UINT64_C(0),
7402 UINT64_C(0),
7403 UINT64_C(0),
7404 UINT64_C(0),
7405 UINT64_C(0),
7406 UINT64_C(0),
7407 UINT64_C(0),
7408 UINT64_C(0),
7409 UINT64_C(0),
7410 UINT64_C(0),
7411 UINT64_C(0),
7412 UINT64_C(0),
7413 UINT64_C(0),
7414 UINT64_C(0),
7415 UINT64_C(0),
7416 UINT64_C(0),
7417 UINT64_C(0),
7418 UINT64_C(0),
7419 UINT64_C(0),
7420 UINT64_C(0),
7421 UINT64_C(0),
7422 UINT64_C(0),
7423 UINT64_C(0),
7424 UINT64_C(0),
7425 UINT64_C(0),
7426 UINT64_C(0),
7427 UINT64_C(0),
7428 UINT64_C(0),
7429 UINT64_C(0),
7430 UINT64_C(0),
7431 UINT64_C(0),
7432 UINT64_C(0),
7433 UINT64_C(0),
7434 UINT64_C(0),
7435 UINT64_C(0),
7436 UINT64_C(0),
7437 UINT64_C(0),
7438 UINT64_C(0),
7439 UINT64_C(0),
7440 UINT64_C(0),
7441 UINT64_C(0),
7442 UINT64_C(0),
7443 UINT64_C(0),
7444 UINT64_C(0),
7445 UINT64_C(0),
7446 UINT64_C(0),
7447 UINT64_C(0),
7448 UINT64_C(0),
7449 UINT64_C(0),
7450 UINT64_C(0),
7451 UINT64_C(0),
7452 UINT64_C(0),
7453 UINT64_C(0),
7454 UINT64_C(0),
7455 UINT64_C(0),
7456 UINT64_C(0),
7457 UINT64_C(0),
7458 UINT64_C(0),
7459 UINT64_C(0),
7460 UINT64_C(0),
7461 UINT64_C(0),
7462 UINT64_C(0),
7463 UINT64_C(0),
7464 UINT64_C(0),
7465 UINT64_C(0),
7466 UINT64_C(0),
7467 UINT64_C(0),
7468 UINT64_C(0),
7469 UINT64_C(0),
7470 UINT64_C(0),
7471 UINT64_C(0),
7472 UINT64_C(0),
7473 UINT64_C(0),
7474 UINT64_C(0),
7475 UINT64_C(0),
7476 UINT64_C(0),
7477 UINT64_C(0),
7478 UINT64_C(0),
7479 UINT64_C(0),
7480 UINT64_C(0),
7481 UINT64_C(0),
7482 UINT64_C(0),
7483 UINT64_C(0),
7484 UINT64_C(0),
7485 UINT64_C(0),
7486 UINT64_C(0),
7487 UINT64_C(0),
7488 UINT64_C(0),
7489 UINT64_C(0),
7490 UINT64_C(0),
7491 UINT64_C(0),
7492 UINT64_C(0),
7493 UINT64_C(0),
7494 UINT64_C(0),
7495 UINT64_C(0),
7496 UINT64_C(0),
7497 UINT64_C(0),
7498 UINT64_C(0),
7499 UINT64_C(0),
7500 UINT64_C(0),
7501 UINT64_C(0),
7502 UINT64_C(0),
7503 UINT64_C(0),
7504 UINT64_C(0),
7505 UINT64_C(0),
7506 UINT64_C(0),
7507 UINT64_C(0),
7508 UINT64_C(0),
7509 UINT64_C(0),
7510 UINT64_C(0),
7511 UINT64_C(0),
7512 UINT64_C(0),
7513 UINT64_C(0),
7514 UINT64_C(0),
7515 UINT64_C(0),
7516 UINT64_C(0),
7517 UINT64_C(0),
7518 UINT64_C(0),
7519 UINT64_C(0),
7520 UINT64_C(0),
7521 UINT64_C(0),
7522 UINT64_C(0),
7523 UINT64_C(0),
7524 UINT64_C(0),
7525 UINT64_C(0),
7526 UINT64_C(0),
7527 UINT64_C(0),
7528 UINT64_C(0),
7529 UINT64_C(0),
7530 UINT64_C(0),
7531 UINT64_C(0),
7532 UINT64_C(0),
7533 UINT64_C(0),
7534 UINT64_C(0),
7535 UINT64_C(0),
7536 UINT64_C(0),
7537 UINT64_C(0),
7538 UINT64_C(0),
7539 UINT64_C(0),
7540 UINT64_C(0),
7541 UINT64_C(0),
7542 UINT64_C(0),
7543 UINT64_C(0),
7544 UINT64_C(0),
7545 UINT64_C(0),
7546 UINT64_C(0),
7547 UINT64_C(0),
7548 UINT64_C(0),
7549 UINT64_C(0),
7550 UINT64_C(0),
7551 UINT64_C(0),
7552 UINT64_C(0),
7553 UINT64_C(0),
7554 UINT64_C(0),
7555 UINT64_C(0),
7556 UINT64_C(0),
7557 UINT64_C(0),
7558 UINT64_C(0),
7559 UINT64_C(0),
7560 UINT64_C(0),
7561 UINT64_C(0),
7562 UINT64_C(0),
7563 UINT64_C(0),
7564 UINT64_C(0),
7565 UINT64_C(0),
7566 UINT64_C(0),
7567 UINT64_C(0),
7568 UINT64_C(0),
7569 UINT64_C(0),
7570 UINT64_C(0),
7571 UINT64_C(0),
7572 UINT64_C(0),
7573 UINT64_C(0),
7574 UINT64_C(0),
7575 UINT64_C(0),
7576 UINT64_C(0),
7577 UINT64_C(0),
7578 UINT64_C(0),
7579 UINT64_C(0),
7580 UINT64_C(0),
7581 UINT64_C(0),
7582 UINT64_C(0),
7583 UINT64_C(0),
7584 UINT64_C(0),
7585 UINT64_C(0),
7586 UINT64_C(0),
7587 UINT64_C(0),
7588 UINT64_C(0),
7589 UINT64_C(0),
7590 UINT64_C(0),
7591 UINT64_C(0),
7592 UINT64_C(0),
7593 UINT64_C(0),
7594 UINT64_C(0),
7595 UINT64_C(0),
7596 UINT64_C(0),
7597 UINT64_C(0),
7598 UINT64_C(0),
7599 UINT64_C(0),
7600 UINT64_C(0),
7601 UINT64_C(0),
7602 UINT64_C(0),
7603 UINT64_C(0),
7604 UINT64_C(0),
7605 UINT64_C(0),
7606 UINT64_C(0),
7607 UINT64_C(0),
7608 UINT64_C(0),
7609 UINT64_C(0),
7610 UINT64_C(0),
7611 UINT64_C(0),
7612 UINT64_C(0),
7613 UINT64_C(0),
7614 UINT64_C(0),
7615 UINT64_C(0),
7616 UINT64_C(0),
7617 UINT64_C(0),
7618 UINT64_C(0),
7619 UINT64_C(0),
7620 UINT64_C(0),
7621 UINT64_C(0),
7622 UINT64_C(0),
7623 UINT64_C(0),
7624 UINT64_C(0),
7625 UINT64_C(0),
7626 UINT64_C(0),
7627 UINT64_C(0),
7628 UINT64_C(0),
7629 UINT64_C(0),
7630 UINT64_C(0),
7631 UINT64_C(0),
7632 UINT64_C(0),
7633 UINT64_C(0),
7634 UINT64_C(0),
7635 UINT64_C(0),
7636 UINT64_C(0),
7637 UINT64_C(0),
7638 UINT64_C(0),
7639 UINT64_C(0),
7640 UINT64_C(0),
7641 UINT64_C(0),
7642 UINT64_C(0),
7643 UINT64_C(0),
7644 UINT64_C(0),
7645 UINT64_C(0),
7646 UINT64_C(0),
7647 UINT64_C(0),
7648 UINT64_C(0),
7649 UINT64_C(0),
7650 UINT64_C(0),
7651 UINT64_C(0),
7652 UINT64_C(0),
7653 UINT64_C(0),
7654 UINT64_C(0),
7655 UINT64_C(0),
7656 UINT64_C(0),
7657 UINT64_C(0),
7658 UINT64_C(0),
7659 UINT64_C(0),
7660 UINT64_C(0),
7661 UINT64_C(0),
7662 UINT64_C(0),
7663 UINT64_C(0),
7664 UINT64_C(0),
7665 UINT64_C(0),
7666 UINT64_C(0),
7667 UINT64_C(0),
7668 UINT64_C(0),
7669 UINT64_C(0),
7670 UINT64_C(0),
7671 UINT64_C(0),
7672 UINT64_C(0),
7673 UINT64_C(0),
7674 UINT64_C(0),
7675 UINT64_C(0),
7676 UINT64_C(0),
7677 UINT64_C(0),
7678 UINT64_C(0),
7679 UINT64_C(0),
7680 UINT64_C(0),
7681 UINT64_C(0),
7682 UINT64_C(0),
7683 UINT64_C(0),
7684 UINT64_C(0),
7685 UINT64_C(0),
7686 UINT64_C(0),
7687 UINT64_C(0),
7688 UINT64_C(0),
7689 UINT64_C(0),
7690 UINT64_C(0),
7691 UINT64_C(0),
7692 UINT64_C(0),
7693 UINT64_C(0),
7694 UINT64_C(0),
7695 UINT64_C(0),
7696 UINT64_C(0),
7697 UINT64_C(0),
7698 UINT64_C(0),
7699 UINT64_C(0),
7700 UINT64_C(0),
7701 UINT64_C(0),
7702 UINT64_C(0),
7703 UINT64_C(0),
7704 UINT64_C(0),
7705 UINT64_C(0),
7706 UINT64_C(0),
7707 UINT64_C(0),
7708 UINT64_C(0),
7709 UINT64_C(0),
7710 UINT64_C(0),
7711 UINT64_C(0),
7712 UINT64_C(0),
7713 UINT64_C(0),
7714 UINT64_C(0),
7715 UINT64_C(0),
7716 UINT64_C(0),
7717 UINT64_C(0),
7718 UINT64_C(0),
7719 UINT64_C(0),
7720 UINT64_C(0),
7721 UINT64_C(0),
7722 UINT64_C(0),
7723 UINT64_C(0),
7724 UINT64_C(0),
7725 UINT64_C(0),
7726 UINT64_C(0),
7727 UINT64_C(0),
7728 UINT64_C(0),
7729 UINT64_C(0),
7730 UINT64_C(0),
7731 UINT64_C(0),
7732 UINT64_C(0),
7733 UINT64_C(0),
7734 UINT64_C(0),
7735 UINT64_C(0),
7736 UINT64_C(0),
7737 UINT64_C(0),
7738 UINT64_C(0),
7739 UINT64_C(0),
7740 UINT64_C(0),
7741 UINT64_C(0),
7742 UINT64_C(0),
7743 UINT64_C(0),
7744 UINT64_C(0),
7745 UINT64_C(0),
7746 UINT64_C(0),
7747 UINT64_C(0),
7748 UINT64_C(0),
7749 UINT64_C(0),
7750 UINT64_C(0),
7751 UINT64_C(0),
7752 UINT64_C(0),
7753 UINT64_C(0),
7754 UINT64_C(0),
7755 UINT64_C(0),
7756 UINT64_C(0),
7757 UINT64_C(0),
7758 UINT64_C(0),
7759 UINT64_C(0),
7760 UINT64_C(0),
7761 UINT64_C(0),
7762 UINT64_C(0),
7763 UINT64_C(0),
7764 UINT64_C(0),
7765 UINT64_C(0),
7766 UINT64_C(0),
7767 UINT64_C(0),
7768 UINT64_C(0),
7769 UINT64_C(0),
7770 UINT64_C(0),
7771 UINT64_C(0),
7772 UINT64_C(0),
7773 UINT64_C(0),
7774 UINT64_C(0),
7775 UINT64_C(0),
7776 UINT64_C(0),
7777 UINT64_C(0),
7778 UINT64_C(0),
7779 UINT64_C(0),
7780 UINT64_C(0),
7781 UINT64_C(0),
7782 UINT64_C(0),
7783 UINT64_C(0),
7784 UINT64_C(0),
7785 UINT64_C(0),
7786 UINT64_C(0),
7787 UINT64_C(0),
7788 UINT64_C(0),
7789 UINT64_C(0),
7790 UINT64_C(0),
7791 UINT64_C(0),
7792 UINT64_C(0),
7793 UINT64_C(0),
7794 UINT64_C(0),
7795 UINT64_C(0),
7796 UINT64_C(0),
7797 UINT64_C(0),
7798 UINT64_C(0),
7799 UINT64_C(0),
7800 UINT64_C(0),
7801 UINT64_C(0),
7802 UINT64_C(0),
7803 UINT64_C(0),
7804 UINT64_C(0),
7805 UINT64_C(0),
7806 UINT64_C(0),
7807 UINT64_C(0),
7808 UINT64_C(0),
7809 UINT64_C(0),
7810 UINT64_C(0),
7811 UINT64_C(0),
7812 UINT64_C(0),
7813 UINT64_C(0),
7814 UINT64_C(0),
7815 UINT64_C(0),
7816 UINT64_C(0),
7817 UINT64_C(0),
7818 UINT64_C(0),
7819 UINT64_C(0),
7820 UINT64_C(0),
7821 UINT64_C(0),
7822 UINT64_C(0),
7823 UINT64_C(0),
7824 UINT64_C(0),
7825 UINT64_C(0),
7826 UINT64_C(0),
7827 UINT64_C(0),
7828 UINT64_C(0),
7829 UINT64_C(0),
7830 UINT64_C(0),
7831 UINT64_C(0),
7832 UINT64_C(0),
7833 UINT64_C(0),
7834 UINT64_C(0),
7835 UINT64_C(0),
7836 UINT64_C(0),
7837 UINT64_C(0),
7838 UINT64_C(0),
7839 UINT64_C(0),
7840 UINT64_C(0),
7841 UINT64_C(0),
7842 UINT64_C(0),
7843 UINT64_C(0),
7844 UINT64_C(0),
7845 UINT64_C(0),
7846 UINT64_C(0),
7847 UINT64_C(0),
7848 UINT64_C(0),
7849 UINT64_C(0),
7850 UINT64_C(0),
7851 UINT64_C(0),
7852 UINT64_C(0),
7853 UINT64_C(0),
7854 UINT64_C(0),
7855 UINT64_C(0),
7856 UINT64_C(0),
7857 UINT64_C(0),
7858 UINT64_C(0),
7859 UINT64_C(0),
7860 UINT64_C(0),
7861 UINT64_C(0),
7862 UINT64_C(0),
7863 UINT64_C(0),
7864 UINT64_C(0),
7865 UINT64_C(0),
7866 UINT64_C(0),
7867 UINT64_C(0),
7868 UINT64_C(0),
7869 UINT64_C(0),
7870 UINT64_C(0),
7871 UINT64_C(0),
7872 UINT64_C(0),
7873 UINT64_C(0),
7874 UINT64_C(0),
7875 UINT64_C(0),
7876 UINT64_C(0),
7877 UINT64_C(0),
7878 UINT64_C(0),
7879 UINT64_C(0),
7880 UINT64_C(0),
7881 UINT64_C(0),
7882 UINT64_C(0),
7883 UINT64_C(0),
7884 UINT64_C(0),
7885 UINT64_C(0),
7886 UINT64_C(0),
7887 UINT64_C(0),
7888 UINT64_C(0),
7889 UINT64_C(0),
7890 UINT64_C(0),
7891 UINT64_C(0),
7892 UINT64_C(0),
7893 UINT64_C(0),
7894 UINT64_C(0),
7895 UINT64_C(0),
7896 UINT64_C(0),
7897 UINT64_C(0),
7898 UINT64_C(0),
7899 UINT64_C(0),
7900 UINT64_C(0),
7901 UINT64_C(0),
7902 UINT64_C(0),
7903 UINT64_C(0),
7904 UINT64_C(0),
7905 UINT64_C(0),
7906 UINT64_C(0),
7907 UINT64_C(0),
7908 UINT64_C(0),
7909 UINT64_C(0),
7910 UINT64_C(0),
7911 UINT64_C(0),
7912 UINT64_C(0),
7913 UINT64_C(0),
7914 UINT64_C(0),
7915 UINT64_C(0),
7916 UINT64_C(0),
7917 UINT64_C(0),
7918 UINT64_C(0),
7919 UINT64_C(0),
7920 UINT64_C(0),
7921 UINT64_C(0),
7922 UINT64_C(0),
7923 UINT64_C(0),
7924 UINT64_C(0),
7925 UINT64_C(0),
7926 UINT64_C(0),
7927 UINT64_C(0),
7928 UINT64_C(0),
7929 UINT64_C(0),
7930 UINT64_C(0),
7931 UINT64_C(0),
7932 UINT64_C(0),
7933 UINT64_C(0),
7934 UINT64_C(0),
7935 UINT64_C(0),
7936 UINT64_C(0),
7937 UINT64_C(0),
7938 UINT64_C(0),
7939 UINT64_C(0),
7940 UINT64_C(0),
7941 UINT64_C(0),
7942 UINT64_C(0),
7943 UINT64_C(0),
7944 UINT64_C(0),
7945 UINT64_C(0),
7946 UINT64_C(0),
7947 UINT64_C(0),
7948 UINT64_C(0),
7949 UINT64_C(0),
7950 UINT64_C(0),
7951 UINT64_C(0),
7952 UINT64_C(0),
7953 UINT64_C(0),
7954 UINT64_C(0),
7955 UINT64_C(0),
7956 UINT64_C(0),
7957 UINT64_C(0),
7958 UINT64_C(0),
7959 UINT64_C(0),
7960 UINT64_C(0),
7961 UINT64_C(0),
7962 UINT64_C(0),
7963 UINT64_C(0),
7964 UINT64_C(0),
7965 UINT64_C(0),
7966 UINT64_C(0),
7967 UINT64_C(0),
7968 UINT64_C(0),
7969 UINT64_C(0),
7970 UINT64_C(0),
7971 UINT64_C(0),
7972 UINT64_C(0),
7973 UINT64_C(0),
7974 UINT64_C(0),
7975 UINT64_C(0),
7976 UINT64_C(0),
7977 UINT64_C(0),
7978 UINT64_C(0),
7979 UINT64_C(0),
7980 UINT64_C(0),
7981 UINT64_C(0),
7982 UINT64_C(0),
7983 UINT64_C(0),
7984 UINT64_C(0),
7985 UINT64_C(0),
7986 UINT64_C(0),
7987 UINT64_C(0),
7988 UINT64_C(0),
7989 UINT64_C(0),
7990 UINT64_C(0),
7991 UINT64_C(0),
7992 UINT64_C(0),
7993 UINT64_C(0),
7994 UINT64_C(0),
7995 UINT64_C(0),
7996 UINT64_C(0),
7997 UINT64_C(0),
7998 UINT64_C(0),
7999 UINT64_C(0),
8000 UINT64_C(0),
8001 UINT64_C(0),
8002 UINT64_C(0),
8003 UINT64_C(0),
8004 UINT64_C(0),
8005 UINT64_C(0),
8006 UINT64_C(0),
8007 UINT64_C(0),
8008 UINT64_C(0),
8009 UINT64_C(0),
8010 UINT64_C(0),
8011 UINT64_C(0),
8012 UINT64_C(0),
8013 UINT64_C(0),
8014 UINT64_C(0),
8015 UINT64_C(0),
8016 UINT64_C(0),
8017 UINT64_C(0),
8018 UINT64_C(0),
8019 UINT64_C(0),
8020 UINT64_C(0),
8021 UINT64_C(0),
8022 UINT64_C(0),
8023 UINT64_C(0),
8024 UINT64_C(0),
8025 UINT64_C(0),
8026 UINT64_C(0),
8027 UINT64_C(0),
8028 UINT64_C(0),
8029 UINT64_C(0),
8030 UINT64_C(0),
8031 UINT64_C(0),
8032 UINT64_C(0),
8033 UINT64_C(0),
8034 UINT64_C(0),
8035 UINT64_C(0),
8036 UINT64_C(0),
8037 UINT64_C(0),
8038 UINT64_C(0),
8039 UINT64_C(0),
8040 UINT64_C(0),
8041 UINT64_C(0),
8042 UINT64_C(0),
8043 UINT64_C(0),
8044 UINT64_C(0),
8045 UINT64_C(0),
8046 UINT64_C(0),
8047 UINT64_C(0),
8048 UINT64_C(0),
8049 UINT64_C(0),
8050 UINT64_C(0),
8051 UINT64_C(0),
8052 UINT64_C(0),
8053 UINT64_C(0),
8054 UINT64_C(0),
8055 UINT64_C(0),
8056 UINT64_C(0),
8057 UINT64_C(0),
8058 UINT64_C(0),
8059 UINT64_C(0),
8060 UINT64_C(0),
8061 UINT64_C(0),
8062 UINT64_C(0),
8063 UINT64_C(0),
8064 UINT64_C(0),
8065 UINT64_C(0),
8066 UINT64_C(0),
8067 UINT64_C(0),
8068 UINT64_C(0),
8069 UINT64_C(0),
8070 UINT64_C(0),
8071 UINT64_C(0),
8072 UINT64_C(0),
8073 UINT64_C(0),
8074 UINT64_C(0),
8075 UINT64_C(0),
8076 UINT64_C(0),
8077 UINT64_C(0),
8078 UINT64_C(0),
8079 UINT64_C(0),
8080 UINT64_C(0),
8081 UINT64_C(0),
8082 UINT64_C(0),
8083 UINT64_C(0),
8084 UINT64_C(0),
8085 UINT64_C(0),
8086 UINT64_C(0),
8087 UINT64_C(0),
8088 UINT64_C(0),
8089 UINT64_C(0),
8090 UINT64_C(0),
8091 UINT64_C(0),
8092 UINT64_C(0),
8093 UINT64_C(0),
8094 UINT64_C(0),
8095 UINT64_C(0),
8096 UINT64_C(0),
8097 UINT64_C(0),
8098 UINT64_C(0),
8099 UINT64_C(0),
8100 UINT64_C(0),
8101 UINT64_C(0),
8102 UINT64_C(0),
8103 UINT64_C(0),
8104 UINT64_C(0),
8105 UINT64_C(0),
8106 UINT64_C(0),
8107 UINT64_C(0),
8108 UINT64_C(0),
8109 UINT64_C(0),
8110 UINT64_C(0),
8111 UINT64_C(0),
8112 UINT64_C(0),
8113 UINT64_C(0),
8114 UINT64_C(0),
8115 UINT64_C(0),
8116 UINT64_C(0),
8117 UINT64_C(0),
8118 UINT64_C(0),
8119 UINT64_C(0),
8120 UINT64_C(0),
8121 UINT64_C(0),
8122 UINT64_C(0),
8123 UINT64_C(0),
8124 UINT64_C(0),
8125 UINT64_C(0),
8126 UINT64_C(0),
8127 UINT64_C(0),
8128 UINT64_C(0),
8129 UINT64_C(0),
8130 UINT64_C(0),
8131 UINT64_C(0),
8132 UINT64_C(0),
8133 UINT64_C(0),
8134 UINT64_C(0),
8135 UINT64_C(0),
8136 UINT64_C(0),
8137 UINT64_C(0),
8138 UINT64_C(0),
8139 UINT64_C(0),
8140 UINT64_C(0),
8141 UINT64_C(0),
8142 UINT64_C(0),
8143 UINT64_C(0),
8144 UINT64_C(0),
8145 UINT64_C(0),
8146 UINT64_C(0),
8147 UINT64_C(0),
8148 UINT64_C(0),
8149 UINT64_C(0),
8150 UINT64_C(0),
8151 UINT64_C(0),
8152 UINT64_C(0),
8153 UINT64_C(0),
8154 UINT64_C(0),
8155 UINT64_C(0),
8156 UINT64_C(0),
8157 UINT64_C(0),
8158 UINT64_C(0),
8159 UINT64_C(0),
8160 UINT64_C(0),
8161 UINT64_C(0),
8162 UINT64_C(0),
8163 UINT64_C(0),
8164 UINT64_C(0),
8165 UINT64_C(0),
8166 UINT64_C(0),
8167 UINT64_C(0),
8168 UINT64_C(0),
8169 UINT64_C(0),
8170 UINT64_C(0),
8171 UINT64_C(0),
8172 UINT64_C(0),
8173 UINT64_C(0),
8174 UINT64_C(0),
8175 UINT64_C(0),
8176 UINT64_C(0),
8177 UINT64_C(0),
8178 UINT64_C(0),
8179 UINT64_C(0),
8180 UINT64_C(0),
8181 UINT64_C(0),
8182 UINT64_C(0),
8183 UINT64_C(0),
8184 UINT64_C(0),
8185 UINT64_C(0),
8186 UINT64_C(0),
8187 UINT64_C(0),
8188 UINT64_C(0),
8189 UINT64_C(0),
8190 UINT64_C(0),
8191 UINT64_C(0),
8192 UINT64_C(0),
8193 UINT64_C(0),
8194 UINT64_C(0),
8195 UINT64_C(0),
8196 UINT64_C(0),
8197 UINT64_C(0),
8198 UINT64_C(0),
8199 UINT64_C(0),
8200 UINT64_C(0),
8201 UINT64_C(0),
8202 UINT64_C(0),
8203 UINT64_C(0),
8204 UINT64_C(0),
8205 UINT64_C(0),
8206 UINT64_C(0),
8207 UINT64_C(0),
8208 UINT64_C(0),
8209 UINT64_C(0),
8210 UINT64_C(0),
8211 UINT64_C(0),
8212 UINT64_C(0),
8213 UINT64_C(0),
8214 UINT64_C(0),
8215 UINT64_C(0),
8216 UINT64_C(0),
8217 UINT64_C(0),
8218 UINT64_C(0),
8219 UINT64_C(0),
8220 UINT64_C(0),
8221 UINT64_C(0),
8222 UINT64_C(0),
8223 UINT64_C(0),
8224 UINT64_C(0),
8225 UINT64_C(0),
8226 UINT64_C(0),
8227 UINT64_C(0),
8228 UINT64_C(0),
8229 UINT64_C(0),
8230 UINT64_C(0),
8231 UINT64_C(0),
8232 UINT64_C(0),
8233 UINT64_C(0),
8234 UINT64_C(0),
8235 UINT64_C(0),
8236 UINT64_C(0),
8237 UINT64_C(0),
8238 UINT64_C(0),
8239 UINT64_C(0),
8240 UINT64_C(0),
8241 UINT64_C(0),
8242 UINT64_C(0),
8243 UINT64_C(0),
8244 UINT64_C(0),
8245 UINT64_C(0),
8246 UINT64_C(0),
8247 UINT64_C(0),
8248 UINT64_C(0),
8249 UINT64_C(0),
8250 UINT64_C(0),
8251 UINT64_C(0),
8252 UINT64_C(0),
8253 UINT64_C(0),
8254 UINT64_C(0),
8255 UINT64_C(0),
8256 UINT64_C(0),
8257 UINT64_C(0),
8258 UINT64_C(0),
8259 UINT64_C(0),
8260 UINT64_C(0),
8261 UINT64_C(0),
8262 UINT64_C(0),
8263 UINT64_C(0),
8264 UINT64_C(0),
8265 UINT64_C(0),
8266 UINT64_C(0),
8267 UINT64_C(0),
8268 UINT64_C(0),
8269 UINT64_C(0),
8270 UINT64_C(0),
8271 UINT64_C(0),
8272 UINT64_C(0),
8273 UINT64_C(0),
8274 UINT64_C(0),
8275 UINT64_C(0),
8276 UINT64_C(0),
8277 UINT64_C(0),
8278 UINT64_C(0),
8279 UINT64_C(0),
8280 UINT64_C(0),
8281 UINT64_C(0),
8282 UINT64_C(0),
8283 UINT64_C(0),
8284 UINT64_C(0),
8285 UINT64_C(0),
8286 UINT64_C(0),
8287 UINT64_C(0),
8288 UINT64_C(0),
8289 UINT64_C(0),
8290 UINT64_C(0),
8291 UINT64_C(0),
8292 UINT64_C(0),
8293 UINT64_C(0),
8294 UINT64_C(0),
8295 UINT64_C(0),
8296 UINT64_C(0),
8297 UINT64_C(0),
8298 UINT64_C(0),
8299 UINT64_C(0),
8300 UINT64_C(0),
8301 UINT64_C(0),
8302 UINT64_C(0),
8303 UINT64_C(0),
8304 UINT64_C(0),
8305 UINT64_C(0),
8306 UINT64_C(0),
8307 UINT64_C(0),
8308 UINT64_C(0),
8309 UINT64_C(0),
8310 UINT64_C(0),
8311 UINT64_C(0),
8312 UINT64_C(0),
8313 UINT64_C(0),
8314 UINT64_C(0),
8315 UINT64_C(0),
8316 UINT64_C(0),
8317 UINT64_C(0),
8318 UINT64_C(0),
8319 UINT64_C(0),
8320 UINT64_C(0),
8321 UINT64_C(0),
8322 UINT64_C(0),
8323 UINT64_C(0),
8324 UINT64_C(0),
8325 UINT64_C(0),
8326 UINT64_C(0),
8327 UINT64_C(0),
8328 UINT64_C(0),
8329 UINT64_C(0),
8330 UINT64_C(0),
8331 UINT64_C(0),
8332 UINT64_C(0),
8333 UINT64_C(0),
8334 UINT64_C(0),
8335 UINT64_C(0),
8336 UINT64_C(0),
8337 UINT64_C(0),
8338 UINT64_C(0),
8339 UINT64_C(0),
8340 UINT64_C(0),
8341 UINT64_C(0),
8342 UINT64_C(0),
8343 UINT64_C(0),
8344 UINT64_C(0),
8345 UINT64_C(0),
8346 UINT64_C(0),
8347 UINT64_C(0),
8348 UINT64_C(0),
8349 UINT64_C(0),
8350 UINT64_C(0),
8351 UINT64_C(0),
8352 UINT64_C(0),
8353 UINT64_C(0),
8354 UINT64_C(0),
8355 UINT64_C(0),
8356 UINT64_C(0),
8357 UINT64_C(0),
8358 UINT64_C(0),
8359 UINT64_C(0),
8360 UINT64_C(0),
8361 UINT64_C(0),
8362 UINT64_C(0),
8363 UINT64_C(0),
8364 UINT64_C(0),
8365 UINT64_C(0),
8366 UINT64_C(0),
8367 UINT64_C(0),
8368 UINT64_C(0),
8369 UINT64_C(0),
8370 UINT64_C(0),
8371 UINT64_C(0),
8372 UINT64_C(0),
8373 UINT64_C(0),
8374 UINT64_C(0),
8375 UINT64_C(0),
8376 UINT64_C(0),
8377 UINT64_C(0),
8378 UINT64_C(0),
8379 UINT64_C(0),
8380 UINT64_C(0),
8381 UINT64_C(0),
8382 UINT64_C(0),
8383 UINT64_C(0),
8384 UINT64_C(0),
8385 UINT64_C(0),
8386 UINT64_C(0),
8387 UINT64_C(0),
8388 UINT64_C(0),
8389 UINT64_C(0),
8390 UINT64_C(0),
8391 UINT64_C(0),
8392 UINT64_C(0),
8393 UINT64_C(0),
8394 UINT64_C(0),
8395 UINT64_C(0),
8396 UINT64_C(0),
8397 UINT64_C(0),
8398 UINT64_C(0),
8399 UINT64_C(0),
8400 UINT64_C(0),
8401 UINT64_C(0),
8402 UINT64_C(0),
8403 UINT64_C(0),
8404 UINT64_C(0),
8405 UINT64_C(0),
8406 UINT64_C(0),
8407 UINT64_C(0),
8408 UINT64_C(0),
8409 UINT64_C(0),
8410 UINT64_C(0),
8411 UINT64_C(0),
8412 UINT64_C(0),
8413 UINT64_C(0),
8414 UINT64_C(0),
8415 UINT64_C(0),
8416 UINT64_C(0),
8417 UINT64_C(0),
8418 UINT64_C(0),
8419 UINT64_C(0),
8420 UINT64_C(0),
8421 UINT64_C(0),
8422 UINT64_C(0),
8423 UINT64_C(0),
8424 UINT64_C(0),
8425 UINT64_C(0),
8426 UINT64_C(0),
8427 UINT64_C(0),
8428 UINT64_C(0),
8429 UINT64_C(0),
8430 UINT64_C(0),
8431 UINT64_C(0),
8432 UINT64_C(0),
8433 UINT64_C(0),
8434 UINT64_C(0),
8435 UINT64_C(0),
8436 UINT64_C(0),
8437 UINT64_C(0),
8438 UINT64_C(0),
8439 UINT64_C(0),
8440 UINT64_C(0),
8441 UINT64_C(0),
8442 UINT64_C(0),
8443 UINT64_C(0),
8444 UINT64_C(0),
8445 UINT64_C(0),
8446 UINT64_C(0),
8447 UINT64_C(0),
8448 UINT64_C(0),
8449 UINT64_C(0),
8450 UINT64_C(0),
8451 UINT64_C(0),
8452 UINT64_C(0),
8453 UINT64_C(0),
8454 UINT64_C(0),
8455 UINT64_C(0),
8456 UINT64_C(0),
8457 UINT64_C(0),
8458 UINT64_C(0),
8459 UINT64_C(0),
8460 UINT64_C(0),
8461 UINT64_C(0),
8462 UINT64_C(0),
8463 UINT64_C(0),
8464 UINT64_C(0),
8465 UINT64_C(0),
8466 UINT64_C(0),
8467 UINT64_C(0),
8468 UINT64_C(0),
8469 UINT64_C(0),
8470 UINT64_C(0),
8471 UINT64_C(0),
8472 UINT64_C(0),
8473 UINT64_C(0),
8474 UINT64_C(0),
8475 UINT64_C(0),
8476 UINT64_C(0),
8477 UINT64_C(0),
8478 UINT64_C(0),
8479 UINT64_C(0),
8480 UINT64_C(0),
8481 UINT64_C(0),
8482 UINT64_C(0),
8483 UINT64_C(0),
8484 UINT64_C(0),
8485 UINT64_C(0),
8486 UINT64_C(0),
8487 UINT64_C(0),
8488 UINT64_C(0),
8489 UINT64_C(0),
8490 UINT64_C(0),
8491 UINT64_C(0),
8492 UINT64_C(0),
8493 UINT64_C(0),
8494 UINT64_C(0),
8495 UINT64_C(0),
8496 UINT64_C(0),
8497 UINT64_C(0),
8498 UINT64_C(0),
8499 UINT64_C(0),
8500 UINT64_C(0),
8501 UINT64_C(0),
8502 UINT64_C(0),
8503 UINT64_C(0),
8504 UINT64_C(0),
8505 UINT64_C(0),
8506 UINT64_C(0),
8507 UINT64_C(0),
8508 UINT64_C(0),
8509 UINT64_C(0),
8510 UINT64_C(0),
8511 UINT64_C(0),
8512 UINT64_C(0),
8513 UINT64_C(0),
8514 UINT64_C(0),
8515 UINT64_C(0),
8516 UINT64_C(0),
8517 UINT64_C(0),
8518 UINT64_C(0),
8519 UINT64_C(0),
8520 UINT64_C(0),
8521 UINT64_C(0),
8522 UINT64_C(0),
8523 UINT64_C(0),
8524 UINT64_C(0),
8525 UINT64_C(0),
8526 UINT64_C(0),
8527 UINT64_C(0),
8528 UINT64_C(0),
8529 UINT64_C(0),
8530 UINT64_C(0),
8531 UINT64_C(0),
8532 UINT64_C(0),
8533 UINT64_C(0),
8534 UINT64_C(0),
8535 UINT64_C(0),
8536 UINT64_C(0),
8537 UINT64_C(0),
8538 UINT64_C(0),
8539 UINT64_C(0),
8540 UINT64_C(0),
8541 UINT64_C(0),
8542 UINT64_C(0),
8543 UINT64_C(0),
8544 UINT64_C(0),
8545 UINT64_C(0),
8546 UINT64_C(0),
8547 UINT64_C(0),
8548 UINT64_C(0),
8549 UINT64_C(0),
8550 UINT64_C(0),
8551 UINT64_C(0),
8552 UINT64_C(0),
8553 UINT64_C(0),
8554 UINT64_C(0),
8555 UINT64_C(0),
8556 UINT64_C(0),
8557 UINT64_C(0),
8558 UINT64_C(0),
8559 UINT64_C(0),
8560 UINT64_C(0),
8561 UINT64_C(0),
8562 UINT64_C(0),
8563 UINT64_C(0),
8564 UINT64_C(0),
8565 UINT64_C(0),
8566 UINT64_C(0),
8567 UINT64_C(0),
8568 UINT64_C(0),
8569 UINT64_C(0),
8570 UINT64_C(0),
8571 UINT64_C(0),
8572 UINT64_C(0),
8573 UINT64_C(0),
8574 UINT64_C(0),
8575 UINT64_C(0),
8576 UINT64_C(0),
8577 UINT64_C(0),
8578 UINT64_C(0),
8579 UINT64_C(0),
8580 UINT64_C(0),
8581 UINT64_C(0),
8582 UINT64_C(0),
8583 UINT64_C(0),
8584 UINT64_C(0),
8585 UINT64_C(0),
8586 UINT64_C(0),
8587 UINT64_C(0),
8588 UINT64_C(0),
8589 UINT64_C(0),
8590 UINT64_C(0),
8591 UINT64_C(0),
8592 UINT64_C(0),
8593 UINT64_C(0),
8594 UINT64_C(0),
8595 UINT64_C(0),
8596 UINT64_C(0),
8597 UINT64_C(0),
8598 UINT64_C(0),
8599 UINT64_C(0),
8600 UINT64_C(0),
8601 UINT64_C(0),
8602 UINT64_C(0),
8603 UINT64_C(0),
8604 UINT64_C(0),
8605 UINT64_C(0),
8606 UINT64_C(0),
8607 UINT64_C(0),
8608 UINT64_C(0),
8609 UINT64_C(0),
8610 UINT64_C(0),
8611 UINT64_C(0),
8612 UINT64_C(0),
8613 UINT64_C(0),
8614 UINT64_C(0),
8615 UINT64_C(0),
8616 UINT64_C(0),
8617 UINT64_C(0),
8618 UINT64_C(0),
8619 UINT64_C(0),
8620 UINT64_C(0),
8621 UINT64_C(0),
8622 UINT64_C(0),
8623 UINT64_C(0),
8624 UINT64_C(0),
8625 UINT64_C(0),
8626 UINT64_C(0),
8627 UINT64_C(0),
8628 UINT64_C(0),
8629 UINT64_C(0),
8630 UINT64_C(0),
8631 UINT64_C(0),
8632 UINT64_C(0),
8633 UINT64_C(0),
8634 UINT64_C(0),
8635 UINT64_C(0),
8636 UINT64_C(0),
8637 UINT64_C(0),
8638 UINT64_C(0),
8639 UINT64_C(0),
8640 UINT64_C(0),
8641 UINT64_C(0),
8642 UINT64_C(0),
8643 UINT64_C(0),
8644 UINT64_C(0),
8645 UINT64_C(0),
8646 UINT64_C(0),
8647 UINT64_C(0),
8648 UINT64_C(0),
8649 UINT64_C(0),
8650 UINT64_C(0),
8651 UINT64_C(0),
8652 UINT64_C(0),
8653 UINT64_C(0),
8654 UINT64_C(0),
8655 UINT64_C(0),
8656 UINT64_C(0),
8657 UINT64_C(0),
8658 UINT64_C(0),
8659 UINT64_C(0),
8660 UINT64_C(0),
8661 UINT64_C(0),
8662 UINT64_C(0),
8663 UINT64_C(0),
8664 UINT64_C(0),
8665 UINT64_C(0),
8666 UINT64_C(0),
8667 UINT64_C(0),
8668 UINT64_C(0),
8669 UINT64_C(0),
8670 UINT64_C(0),
8671 UINT64_C(0),
8672 UINT64_C(0),
8673 UINT64_C(0),
8674 UINT64_C(0),
8675 UINT64_C(0),
8676 UINT64_C(0),
8677 UINT64_C(0),
8678 UINT64_C(0),
8679 UINT64_C(0),
8680 UINT64_C(0),
8681 UINT64_C(0),
8682 UINT64_C(0),
8683 UINT64_C(0),
8684 UINT64_C(0),
8685 UINT64_C(0),
8686 UINT64_C(0),
8687 UINT64_C(0),
8688 UINT64_C(0),
8689 UINT64_C(0),
8690 UINT64_C(0),
8691 UINT64_C(0),
8692 UINT64_C(0),
8693 UINT64_C(0),
8694 UINT64_C(0),
8695 UINT64_C(0),
8696 UINT64_C(0),
8697 UINT64_C(0),
8698 UINT64_C(0),
8699 UINT64_C(0),
8700 UINT64_C(0),
8701 UINT64_C(0),
8702 UINT64_C(0),
8703 UINT64_C(0),
8704 UINT64_C(0),
8705 UINT64_C(0),
8706 UINT64_C(0),
8707 UINT64_C(0),
8708 UINT64_C(0),
8709 UINT64_C(0),
8710 UINT64_C(0),
8711 UINT64_C(0),
8712 UINT64_C(0),
8713 UINT64_C(0),
8714 UINT64_C(0),
8715 UINT64_C(0),
8716 UINT64_C(0),
8717 UINT64_C(0),
8718 UINT64_C(0),
8719 UINT64_C(0),
8720 UINT64_C(0),
8721 UINT64_C(0),
8722 UINT64_C(0),
8723 UINT64_C(0),
8724 UINT64_C(0),
8725 UINT64_C(0),
8726 UINT64_C(0),
8727 UINT64_C(0),
8728 UINT64_C(0),
8729 UINT64_C(0),
8730 UINT64_C(0),
8731 UINT64_C(0),
8732 UINT64_C(0),
8733 UINT64_C(0),
8734 UINT64_C(0),
8735 UINT64_C(0),
8736 UINT64_C(0),
8737 UINT64_C(0),
8738 UINT64_C(0),
8739 UINT64_C(0),
8740 UINT64_C(0),
8741 UINT64_C(0),
8742 UINT64_C(0),
8743 UINT64_C(0),
8744 UINT64_C(0),
8745 UINT64_C(0),
8746 UINT64_C(0),
8747 UINT64_C(0),
8748 UINT64_C(0),
8749 UINT64_C(0),
8750 UINT64_C(0),
8751 UINT64_C(0),
8752 UINT64_C(0),
8753 UINT64_C(0),
8754 UINT64_C(0),
8755 UINT64_C(0),
8756 UINT64_C(0),
8757 UINT64_C(0),
8758 UINT64_C(0),
8759 UINT64_C(0),
8760 UINT64_C(0),
8761 UINT64_C(0),
8762 UINT64_C(0),
8763 UINT64_C(0),
8764 UINT64_C(0),
8765 UINT64_C(0),
8766 UINT64_C(0),
8767 UINT64_C(0),
8768 UINT64_C(0),
8769 UINT64_C(0),
8770 UINT64_C(0),
8771 UINT64_C(0),
8772 UINT64_C(0),
8773 UINT64_C(0),
8774 UINT64_C(0),
8775 UINT64_C(0),
8776 UINT64_C(0),
8777 UINT64_C(0),
8778 UINT64_C(0),
8779 UINT64_C(0),
8780 UINT64_C(0),
8781 UINT64_C(0),
8782 UINT64_C(0),
8783 UINT64_C(0),
8784 UINT64_C(0),
8785 UINT64_C(0),
8786 UINT64_C(0),
8787 UINT64_C(0),
8788 UINT64_C(0),
8789 UINT64_C(0),
8790 UINT64_C(0),
8791 UINT64_C(0),
8792 UINT64_C(0),
8793 UINT64_C(0),
8794 UINT64_C(0),
8795 UINT64_C(0),
8796 UINT64_C(0),
8797 UINT64_C(0),
8798 UINT64_C(0),
8799 UINT64_C(0),
8800 UINT64_C(0),
8801 UINT64_C(0),
8802 UINT64_C(0),
8803 UINT64_C(0),
8804 UINT64_C(0),
8805 UINT64_C(0),
8806 UINT64_C(0),
8807 UINT64_C(0),
8808 UINT64_C(0),
8809 UINT64_C(0),
8810 UINT64_C(0),
8811 UINT64_C(0),
8812 UINT64_C(0),
8813 UINT64_C(0),
8814 UINT64_C(0),
8815 UINT64_C(0),
8816 UINT64_C(0),
8817 UINT64_C(0),
8818 UINT64_C(0),
8819 UINT64_C(0),
8820 UINT64_C(0),
8821 UINT64_C(0),
8822 UINT64_C(0),
8823 UINT64_C(0),
8824 UINT64_C(0),
8825 UINT64_C(0),
8826 UINT64_C(0),
8827 UINT64_C(0),
8828 UINT64_C(0),
8829 UINT64_C(0),
8830 UINT64_C(0),
8831 UINT64_C(0),
8832 UINT64_C(0),
8833 UINT64_C(0),
8834 UINT64_C(0),
8835 UINT64_C(0),
8836 UINT64_C(0),
8837 UINT64_C(0),
8838 UINT64_C(0),
8839 UINT64_C(0),
8840 UINT64_C(0),
8841 UINT64_C(0),
8842 UINT64_C(0),
8843 UINT64_C(0),
8844 UINT64_C(0),
8845 UINT64_C(0),
8846 UINT64_C(0),
8847 UINT64_C(0),
8848 UINT64_C(0),
8849 UINT64_C(0),
8850 UINT64_C(0),
8851 UINT64_C(0),
8852 UINT64_C(0),
8853 UINT64_C(0),
8854 UINT64_C(0),
8855 UINT64_C(0),
8856 UINT64_C(0),
8857 UINT64_C(0),
8858 UINT64_C(0),
8859 UINT64_C(0),
8860 UINT64_C(0),
8861 UINT64_C(0),
8862 UINT64_C(0),
8863 UINT64_C(0),
8864 UINT64_C(0),
8865 UINT64_C(0),
8866 UINT64_C(0),
8867 UINT64_C(0),
8868 UINT64_C(0),
8869 UINT64_C(0),
8870 UINT64_C(0),
8871 UINT64_C(0),
8872 UINT64_C(0),
8873 UINT64_C(0),
8874 UINT64_C(0),
8875 UINT64_C(0),
8876 UINT64_C(0),
8877 UINT64_C(0),
8878 UINT64_C(0),
8879 UINT64_C(0),
8880 UINT64_C(0),
8881 UINT64_C(0),
8882 UINT64_C(0),
8883 UINT64_C(0),
8884 UINT64_C(0),
8885 UINT64_C(0),
8886 UINT64_C(0),
8887 UINT64_C(0),
8888 UINT64_C(0),
8889 UINT64_C(0),
8890 UINT64_C(0),
8891 UINT64_C(0),
8892 UINT64_C(0),
8893 UINT64_C(0),
8894 UINT64_C(0),
8895 UINT64_C(0),
8896 UINT64_C(0),
8897 UINT64_C(0),
8898 UINT64_C(0),
8899 UINT64_C(0),
8900 UINT64_C(0),
8901 UINT64_C(0),
8902 UINT64_C(0),
8903 UINT64_C(0),
8904 UINT64_C(0),
8905 UINT64_C(0),
8906 UINT64_C(0),
8907 UINT64_C(0),
8908 UINT64_C(0),
8909 UINT64_C(0),
8910 UINT64_C(0),
8911 UINT64_C(0),
8912 UINT64_C(0),
8913 UINT64_C(0),
8914 UINT64_C(0),
8915 UINT64_C(0),
8916 UINT64_C(0),
8917 UINT64_C(0),
8918 UINT64_C(0),
8919 UINT64_C(0),
8920 UINT64_C(0),
8921 UINT64_C(0),
8922 UINT64_C(0),
8923 UINT64_C(0),
8924 UINT64_C(0),
8925 UINT64_C(0),
8926 UINT64_C(0),
8927 UINT64_C(0),
8928 UINT64_C(0),
8929 UINT64_C(0),
8930 UINT64_C(0),
8931 UINT64_C(0),
8932 UINT64_C(0),
8933 UINT64_C(0),
8934 UINT64_C(0),
8935 UINT64_C(0),
8936 UINT64_C(0),
8937 UINT64_C(0),
8938 UINT64_C(0),
8939 UINT64_C(0),
8940 UINT64_C(0),
8941 UINT64_C(0),
8942 UINT64_C(0),
8943 UINT64_C(0),
8944 UINT64_C(0),
8945 UINT64_C(0),
8946 UINT64_C(0),
8947 UINT64_C(0),
8948 UINT64_C(0),
8949 UINT64_C(0),
8950 UINT64_C(0),
8951 UINT64_C(0),
8952 UINT64_C(0),
8953 UINT64_C(0),
8954 UINT64_C(0),
8955 UINT64_C(0),
8956 UINT64_C(0),
8957 UINT64_C(0),
8958 UINT64_C(0),
8959 UINT64_C(0),
8960 UINT64_C(0),
8961 UINT64_C(0),
8962 UINT64_C(0),
8963 UINT64_C(0),
8964 UINT64_C(0),
8965 UINT64_C(0),
8966 UINT64_C(0),
8967 UINT64_C(0),
8968 UINT64_C(0),
8969 UINT64_C(0),
8970 UINT64_C(0),
8971 UINT64_C(0),
8972 UINT64_C(0),
8973 UINT64_C(0),
8974 UINT64_C(0),
8975 UINT64_C(0),
8976 UINT64_C(0),
8977 UINT64_C(0),
8978 UINT64_C(0),
8979 UINT64_C(0),
8980 UINT64_C(0),
8981 UINT64_C(0),
8982 UINT64_C(0),
8983 UINT64_C(0),
8984 UINT64_C(0),
8985 UINT64_C(0),
8986 UINT64_C(0),
8987 UINT64_C(0),
8988 UINT64_C(0),
8989 UINT64_C(0),
8990 UINT64_C(0),
8991 UINT64_C(0),
8992 UINT64_C(0),
8993 UINT64_C(0),
8994 UINT64_C(0),
8995 UINT64_C(0),
8996 UINT64_C(0),
8997 UINT64_C(0),
8998 UINT64_C(0),
8999 UINT64_C(0),
9000 UINT64_C(0),
9001 UINT64_C(0),
9002 UINT64_C(0),
9003 UINT64_C(0),
9004 UINT64_C(0),
9005 UINT64_C(0),
9006 UINT64_C(0),
9007 UINT64_C(0),
9008 UINT64_C(0),
9009 UINT64_C(0),
9010 UINT64_C(0),
9011 UINT64_C(0),
9012 UINT64_C(0),
9013 UINT64_C(0),
9014 UINT64_C(0),
9015 UINT64_C(0),
9016 UINT64_C(0),
9017 UINT64_C(0),
9018 UINT64_C(0),
9019 UINT64_C(0),
9020 UINT64_C(0),
9021 UINT64_C(0),
9022 UINT64_C(0),
9023 UINT64_C(0),
9024 UINT64_C(0),
9025 UINT64_C(0),
9026 UINT64_C(0),
9027 UINT64_C(0),
9028 UINT64_C(0),
9029 UINT64_C(0),
9030 UINT64_C(0),
9031 UINT64_C(0),
9032 UINT64_C(0),
9033 UINT64_C(0),
9034 UINT64_C(0),
9035 UINT64_C(0),
9036 UINT64_C(0),
9037 UINT64_C(0),
9038 UINT64_C(0),
9039 UINT64_C(0),
9040 UINT64_C(0),
9041 UINT64_C(0),
9042 UINT64_C(0),
9043 UINT64_C(0),
9044 UINT64_C(0),
9045 UINT64_C(0),
9046 UINT64_C(0),
9047 UINT64_C(0),
9048 UINT64_C(0),
9049 UINT64_C(0),
9050 UINT64_C(0),
9051 UINT64_C(0),
9052 UINT64_C(0),
9053 UINT64_C(0),
9054 UINT64_C(0),
9055 UINT64_C(0),
9056 UINT64_C(0),
9057 UINT64_C(0),
9058 UINT64_C(0),
9059 UINT64_C(0),
9060 UINT64_C(0),
9061 UINT64_C(0),
9062 UINT64_C(0),
9063 UINT64_C(0),
9064 UINT64_C(0),
9065 UINT64_C(0),
9066 UINT64_C(0),
9067 UINT64_C(0),
9068 UINT64_C(0),
9069 UINT64_C(0),
9070 UINT64_C(0),
9071 UINT64_C(0),
9072 UINT64_C(0),
9073 UINT64_C(0),
9074 UINT64_C(0),
9075 UINT64_C(0),
9076 UINT64_C(0),
9077 UINT64_C(0),
9078 UINT64_C(0),
9079 UINT64_C(0),
9080 UINT64_C(0),
9081 UINT64_C(0),
9082 UINT64_C(0),
9083 UINT64_C(0),
9084 UINT64_C(0),
9085 UINT64_C(0),
9086 UINT64_C(0),
9087 UINT64_C(0),
9088 UINT64_C(0),
9089 UINT64_C(0),
9090 UINT64_C(0),
9091 UINT64_C(0),
9092 UINT64_C(0),
9093 UINT64_C(0),
9094 UINT64_C(0),
9095 UINT64_C(0),
9096 UINT64_C(0),
9097 UINT64_C(0),
9098 UINT64_C(0),
9099 UINT64_C(0),
9100 UINT64_C(0),
9101 UINT64_C(0),
9102 UINT64_C(0),
9103 UINT64_C(0),
9104 UINT64_C(0),
9105 UINT64_C(0),
9106 UINT64_C(0),
9107 UINT64_C(0),
9108 UINT64_C(0),
9109 UINT64_C(0),
9110 UINT64_C(0),
9111 UINT64_C(0),
9112 UINT64_C(0),
9113 UINT64_C(0),
9114 UINT64_C(0),
9115 UINT64_C(0),
9116 UINT64_C(0),
9117 UINT64_C(0),
9118 UINT64_C(0),
9119 UINT64_C(0),
9120 UINT64_C(0),
9121 UINT64_C(0),
9122 UINT64_C(0),
9123 UINT64_C(0),
9124 UINT64_C(0),
9125 UINT64_C(0),
9126 UINT64_C(0),
9127 UINT64_C(0),
9128 UINT64_C(0),
9129 UINT64_C(0),
9130 UINT64_C(0),
9131 UINT64_C(0),
9132 UINT64_C(0),
9133 UINT64_C(0),
9134 UINT64_C(0),
9135 UINT64_C(0),
9136 UINT64_C(0),
9137 UINT64_C(0),
9138 UINT64_C(0),
9139 UINT64_C(0),
9140 UINT64_C(0),
9141 UINT64_C(0),
9142 UINT64_C(0),
9143 UINT64_C(0),
9144 UINT64_C(0),
9145 UINT64_C(0),
9146 UINT64_C(0),
9147 UINT64_C(0),
9148 UINT64_C(0),
9149 UINT64_C(0),
9150 UINT64_C(0),
9151 UINT64_C(0),
9152 UINT64_C(0),
9153 UINT64_C(0),
9154 UINT64_C(0),
9155 UINT64_C(0),
9156 UINT64_C(0),
9157 UINT64_C(0),
9158 UINT64_C(0),
9159 UINT64_C(0),
9160 UINT64_C(0),
9161 UINT64_C(0),
9162 UINT64_C(0),
9163 UINT64_C(0),
9164 UINT64_C(0),
9165 UINT64_C(0),
9166 UINT64_C(0),
9167 UINT64_C(0),
9168 UINT64_C(0),
9169 UINT64_C(0),
9170 UINT64_C(0),
9171 UINT64_C(0),
9172 UINT64_C(0),
9173 UINT64_C(0),
9174 UINT64_C(0),
9175 UINT64_C(0),
9176 UINT64_C(0),
9177 UINT64_C(0),
9178 UINT64_C(0),
9179 UINT64_C(0),
9180 UINT64_C(0),
9181 UINT64_C(0),
9182 UINT64_C(0),
9183 UINT64_C(0),
9184 UINT64_C(0),
9185 UINT64_C(0),
9186 UINT64_C(0),
9187 UINT64_C(0),
9188 UINT64_C(0),
9189 UINT64_C(0),
9190 UINT64_C(0),
9191 UINT64_C(0),
9192 UINT64_C(0),
9193 UINT64_C(0),
9194 UINT64_C(0),
9195 UINT64_C(0),
9196 UINT64_C(0),
9197 UINT64_C(0),
9198 UINT64_C(0),
9199 UINT64_C(0),
9200 UINT64_C(0),
9201 UINT64_C(0),
9202 UINT64_C(0),
9203 UINT64_C(0),
9204 UINT64_C(0),
9205 UINT64_C(0),
9206 UINT64_C(0),
9207 UINT64_C(0),
9208 UINT64_C(0),
9209 UINT64_C(0),
9210 UINT64_C(0),
9211 UINT64_C(0),
9212 UINT64_C(0),
9213 UINT64_C(0),
9214 UINT64_C(0),
9215 UINT64_C(0),
9216 UINT64_C(0),
9217 UINT64_C(0),
9218 UINT64_C(0),
9219 UINT64_C(0),
9220 UINT64_C(0),
9221 UINT64_C(0),
9222 UINT64_C(0),
9223 UINT64_C(0),
9224 UINT64_C(0),
9225 UINT64_C(0),
9226 UINT64_C(0),
9227 UINT64_C(0),
9228 UINT64_C(0),
9229 UINT64_C(0),
9230 UINT64_C(0),
9231 UINT64_C(0),
9232 UINT64_C(0),
9233 UINT64_C(0),
9234 UINT64_C(0),
9235 UINT64_C(0),
9236 UINT64_C(0),
9237 UINT64_C(0),
9238 UINT64_C(0),
9239 UINT64_C(0),
9240 UINT64_C(0),
9241 UINT64_C(0),
9242 UINT64_C(0),
9243 UINT64_C(0),
9244 UINT64_C(0),
9245 UINT64_C(0),
9246 UINT64_C(0),
9247 UINT64_C(0),
9248 UINT64_C(0),
9249 UINT64_C(0),
9250 UINT64_C(0),
9251 UINT64_C(0),
9252 UINT64_C(0),
9253 UINT64_C(0),
9254 UINT64_C(0),
9255 UINT64_C(0),
9256 UINT64_C(0),
9257 UINT64_C(0),
9258 UINT64_C(0),
9259 UINT64_C(0),
9260 UINT64_C(0),
9261 UINT64_C(0),
9262 UINT64_C(0),
9263 UINT64_C(0),
9264 UINT64_C(0),
9265 UINT64_C(0),
9266 UINT64_C(0),
9267 UINT64_C(0),
9268 UINT64_C(0),
9269 UINT64_C(0),
9270 UINT64_C(0),
9271 UINT64_C(0),
9272 UINT64_C(0),
9273 UINT64_C(0),
9274 UINT64_C(0),
9275 UINT64_C(0),
9276 UINT64_C(0),
9277 UINT64_C(0),
9278 UINT64_C(0),
9279 UINT64_C(0),
9280 UINT64_C(0),
9281 UINT64_C(0),
9282 UINT64_C(0),
9283 UINT64_C(0),
9284 UINT64_C(0),
9285 UINT64_C(0),
9286 UINT64_C(0),
9287 UINT64_C(0),
9288 UINT64_C(0),
9289 UINT64_C(0),
9290 UINT64_C(0),
9291 UINT64_C(0),
9292 UINT64_C(0),
9293 UINT64_C(0),
9294 UINT64_C(0),
9295 UINT64_C(0),
9296 UINT64_C(0),
9297 UINT64_C(0),
9298 UINT64_C(0),
9299 UINT64_C(0),
9300 UINT64_C(0),
9301 UINT64_C(0),
9302 UINT64_C(0),
9303 UINT64_C(0),
9304 UINT64_C(0),
9305 UINT64_C(0),
9306 UINT64_C(0),
9307 UINT64_C(0),
9308 UINT64_C(0),
9309 UINT64_C(0),
9310 UINT64_C(0),
9311 UINT64_C(0),
9312 UINT64_C(0),
9313 UINT64_C(0),
9314 UINT64_C(0),
9315 UINT64_C(0),
9316 UINT64_C(0),
9317 UINT64_C(0),
9318 UINT64_C(0),
9319 UINT64_C(0),
9320 UINT64_C(0),
9321 UINT64_C(0),
9322 UINT64_C(0),
9323 UINT64_C(0),
9324 UINT64_C(0),
9325 UINT64_C(0),
9326 UINT64_C(0),
9327 UINT64_C(0),
9328 UINT64_C(0),
9329 UINT64_C(0),
9330 UINT64_C(0),
9331 UINT64_C(0),
9332 UINT64_C(0),
9333 UINT64_C(0),
9334 UINT64_C(0),
9335 UINT64_C(0),
9336 UINT64_C(0),
9337 UINT64_C(0),
9338 UINT64_C(0),
9339 UINT64_C(0),
9340 UINT64_C(0),
9341 UINT64_C(0),
9342 UINT64_C(0),
9343 UINT64_C(0),
9344 UINT64_C(0),
9345 UINT64_C(0),
9346 UINT64_C(0),
9347 UINT64_C(0),
9348 UINT64_C(0),
9349 UINT64_C(0),
9350 UINT64_C(0),
9351 UINT64_C(0),
9352 UINT64_C(0),
9353 UINT64_C(0),
9354 UINT64_C(0),
9355 UINT64_C(0),
9356 UINT64_C(0),
9357 UINT64_C(0),
9358 UINT64_C(0),
9359 UINT64_C(0),
9360 UINT64_C(0),
9361 UINT64_C(0),
9362 UINT64_C(0),
9363 UINT64_C(0),
9364 UINT64_C(0),
9365 UINT64_C(0),
9366 UINT64_C(0),
9367 UINT64_C(0),
9368 UINT64_C(0),
9369 UINT64_C(0),
9370 UINT64_C(0),
9371 UINT64_C(0),
9372 UINT64_C(0),
9373 UINT64_C(0),
9374 UINT64_C(0),
9375 UINT64_C(0),
9376 UINT64_C(0),
9377 UINT64_C(0),
9378 UINT64_C(0),
9379 UINT64_C(0),
9380 UINT64_C(0),
9381 UINT64_C(0),
9382 UINT64_C(0),
9383 UINT64_C(0),
9384 UINT64_C(0),
9385 UINT64_C(0),
9386 UINT64_C(0),
9387 UINT64_C(0),
9388 UINT64_C(0),
9389 UINT64_C(0),
9390 UINT64_C(0),
9391 UINT64_C(0),
9392 UINT64_C(0),
9393 UINT64_C(0),
9394 UINT64_C(0),
9395 UINT64_C(0),
9396 UINT64_C(0),
9397 UINT64_C(0),
9398 UINT64_C(0),
9399 UINT64_C(0),
9400 UINT64_C(0),
9401 UINT64_C(0),
9402 UINT64_C(0),
9403 UINT64_C(0),
9404 UINT64_C(0),
9405 UINT64_C(0),
9406 UINT64_C(0),
9407 UINT64_C(0),
9408 UINT64_C(0),
9409 UINT64_C(0),
9410 UINT64_C(0),
9411 UINT64_C(0),
9412 UINT64_C(0),
9413 UINT64_C(0),
9414 UINT64_C(0),
9415 UINT64_C(0),
9416 UINT64_C(0),
9417 UINT64_C(0),
9418 UINT64_C(0),
9419 UINT64_C(0),
9420 UINT64_C(0),
9421 UINT64_C(0),
9422 UINT64_C(0),
9423 UINT64_C(0),
9424 UINT64_C(0),
9425 UINT64_C(0),
9426 UINT64_C(0),
9427 UINT64_C(0),
9428 UINT64_C(0),
9429 UINT64_C(0),
9430 UINT64_C(0),
9431 UINT64_C(0),
9432 UINT64_C(0),
9433 UINT64_C(0),
9434 UINT64_C(0),
9435 UINT64_C(0),
9436 UINT64_C(0),
9437 UINT64_C(0),
9438 UINT64_C(0),
9439 UINT64_C(0),
9440 UINT64_C(0),
9441 UINT64_C(0),
9442 UINT64_C(0),
9443 UINT64_C(0),
9444 UINT64_C(0),
9445 UINT64_C(0),
9446 UINT64_C(0),
9447 UINT64_C(0),
9448 UINT64_C(0),
9449 UINT64_C(0),
9450 UINT64_C(0),
9451 UINT64_C(0),
9452 UINT64_C(0),
9453 UINT64_C(0),
9454 UINT64_C(0),
9455 UINT64_C(0),
9456 UINT64_C(0),
9457 UINT64_C(0),
9458 UINT64_C(0),
9459 UINT64_C(0),
9460 UINT64_C(0),
9461 UINT64_C(0),
9462 UINT64_C(0),
9463 UINT64_C(0),
9464 UINT64_C(0),
9465 UINT64_C(0),
9466 UINT64_C(0),
9467 UINT64_C(0),
9468 UINT64_C(0),
9469 UINT64_C(0),
9470 UINT64_C(0),
9471 UINT64_C(0),
9472 UINT64_C(0),
9473 UINT64_C(0),
9474 UINT64_C(0),
9475 UINT64_C(0),
9476 UINT64_C(0),
9477 UINT64_C(0),
9478 UINT64_C(0),
9479 UINT64_C(0),
9480 UINT64_C(0),
9481 UINT64_C(0),
9482 UINT64_C(0),
9483 UINT64_C(0),
9484 UINT64_C(0),
9485 UINT64_C(0),
9486 UINT64_C(0),
9487 UINT64_C(0),
9488 UINT64_C(0),
9489 UINT64_C(0),
9490 UINT64_C(0),
9491 UINT64_C(0),
9492 UINT64_C(0),
9493 UINT64_C(0),
9494 UINT64_C(0),
9495 UINT64_C(0),
9496 UINT64_C(0),
9497 UINT64_C(0),
9498 UINT64_C(0),
9499 UINT64_C(0),
9500 UINT64_C(0),
9501 UINT64_C(0),
9502 UINT64_C(0),
9503 UINT64_C(0),
9504 UINT64_C(0),
9505 UINT64_C(0),
9506 UINT64_C(0),
9507 UINT64_C(0),
9508 UINT64_C(0),
9509 UINT64_C(0),
9510 UINT64_C(0),
9511 UINT64_C(0),
9512 UINT64_C(0),
9513 UINT64_C(0),
9514 UINT64_C(0),
9515 UINT64_C(0),
9516 UINT64_C(0),
9517 UINT64_C(0),
9518 UINT64_C(0),
9519 UINT64_C(0),
9520 UINT64_C(0),
9521 UINT64_C(0),
9522 UINT64_C(0),
9523 UINT64_C(0),
9524 UINT64_C(0),
9525 UINT64_C(0),
9526 UINT64_C(0),
9527 UINT64_C(0),
9528 UINT64_C(0),
9529 UINT64_C(0),
9530 UINT64_C(0),
9531 UINT64_C(0),
9532 UINT64_C(0),
9533 UINT64_C(0),
9534 UINT64_C(0),
9535 UINT64_C(0),
9536 UINT64_C(0),
9537 UINT64_C(0),
9538 UINT64_C(0),
9539 UINT64_C(0),
9540 UINT64_C(0),
9541 UINT64_C(0),
9542 UINT64_C(0),
9543 UINT64_C(0),
9544 UINT64_C(0),
9545 UINT64_C(0),
9546 UINT64_C(0),
9547 UINT64_C(0),
9548 UINT64_C(0),
9549 UINT64_C(0),
9550 UINT64_C(0),
9551 UINT64_C(0),
9552 UINT64_C(0),
9553 UINT64_C(0),
9554 UINT64_C(0),
9555 UINT64_C(0),
9556 UINT64_C(0),
9557 UINT64_C(0),
9558 UINT64_C(0),
9559 UINT64_C(0),
9560 UINT64_C(0),
9561 UINT64_C(0),
9562 UINT64_C(0),
9563 UINT64_C(0),
9564 UINT64_C(0),
9565 UINT64_C(0),
9566 UINT64_C(0),
9567 UINT64_C(0),
9568 UINT64_C(0),
9569 UINT64_C(0),
9570 UINT64_C(0),
9571 UINT64_C(0),
9572 UINT64_C(0),
9573 UINT64_C(0),
9574 UINT64_C(0),
9575 UINT64_C(0),
9576 UINT64_C(0),
9577 UINT64_C(0),
9578 UINT64_C(0),
9579 UINT64_C(0),
9580 UINT64_C(0),
9581 UINT64_C(0),
9582 UINT64_C(0),
9583 UINT64_C(0),
9584 UINT64_C(0),
9585 UINT64_C(0),
9586 UINT64_C(0),
9587 UINT64_C(0),
9588 UINT64_C(0),
9589 UINT64_C(0),
9590 UINT64_C(0),
9591 UINT64_C(0),
9592 UINT64_C(0),
9593 UINT64_C(0),
9594 UINT64_C(0),
9595 UINT64_C(0),
9596 UINT64_C(0),
9597 UINT64_C(0),
9598 UINT64_C(0),
9599 UINT64_C(0),
9600 UINT64_C(0),
9601 UINT64_C(0),
9602 UINT64_C(0),
9603 UINT64_C(0),
9604 UINT64_C(0),
9605 UINT64_C(0),
9606 UINT64_C(0),
9607 UINT64_C(0),
9608 UINT64_C(0),
9609 UINT64_C(0),
9610 UINT64_C(0),
9611 UINT64_C(0),
9612 UINT64_C(0),
9613 UINT64_C(0),
9614 UINT64_C(0),
9615 UINT64_C(0),
9616 UINT64_C(0),
9617 UINT64_C(0),
9618 UINT64_C(0),
9619 UINT64_C(0),
9620 UINT64_C(0),
9621 UINT64_C(0),
9622 UINT64_C(0),
9623 UINT64_C(0),
9624 UINT64_C(0),
9625 UINT64_C(0),
9626 UINT64_C(0),
9627 UINT64_C(0),
9628 UINT64_C(0),
9629 UINT64_C(0),
9630 UINT64_C(0),
9631 UINT64_C(0),
9632 UINT64_C(0),
9633 UINT64_C(0),
9634 UINT64_C(0),
9635 UINT64_C(0),
9636 UINT64_C(0),
9637 UINT64_C(0),
9638 UINT64_C(0),
9639 UINT64_C(0),
9640 UINT64_C(0),
9641 UINT64_C(0),
9642 UINT64_C(0),
9643 UINT64_C(0),
9644 UINT64_C(0),
9645 UINT64_C(0),
9646 UINT64_C(0),
9647 UINT64_C(0),
9648 UINT64_C(0),
9649 UINT64_C(0),
9650 UINT64_C(0),
9651 UINT64_C(0),
9652 UINT64_C(0),
9653 UINT64_C(0),
9654 UINT64_C(0),
9655 UINT64_C(0),
9656 UINT64_C(0),
9657 UINT64_C(0),
9658 UINT64_C(0),
9659 UINT64_C(0),
9660 UINT64_C(0),
9661 UINT64_C(0),
9662 UINT64_C(0),
9663 UINT64_C(0),
9664 UINT64_C(0),
9665 UINT64_C(0),
9666 UINT64_C(0),
9667 UINT64_C(0),
9668 UINT64_C(0),
9669 UINT64_C(0),
9670 UINT64_C(0),
9671 UINT64_C(0),
9672 UINT64_C(0),
9673 UINT64_C(0),
9674 UINT64_C(0),
9675 UINT64_C(0),
9676 UINT64_C(0),
9677 UINT64_C(0),
9678 UINT64_C(0),
9679 UINT64_C(0),
9680 UINT64_C(0),
9681 UINT64_C(0),
9682 UINT64_C(0),
9683 UINT64_C(0),
9684 UINT64_C(0),
9685 UINT64_C(0),
9686 UINT64_C(0),
9687 UINT64_C(0),
9688 UINT64_C(0),
9689 UINT64_C(0),
9690 UINT64_C(0),
9691 UINT64_C(0),
9692 UINT64_C(0),
9693 UINT64_C(0),
9694 UINT64_C(0),
9695 UINT64_C(0),
9696 UINT64_C(0),
9697 UINT64_C(0),
9698 UINT64_C(0),
9699 UINT64_C(0),
9700 UINT64_C(0),
9701 UINT64_C(0),
9702 UINT64_C(0),
9703 UINT64_C(0),
9704 UINT64_C(0),
9705 UINT64_C(0),
9706 UINT64_C(0),
9707 UINT64_C(0),
9708 UINT64_C(0),
9709 UINT64_C(0),
9710 UINT64_C(0),
9711 UINT64_C(0),
9712 UINT64_C(0),
9713 UINT64_C(0),
9714 UINT64_C(0),
9715 UINT64_C(0),
9716 UINT64_C(0),
9717 UINT64_C(0),
9718 UINT64_C(0),
9719 UINT64_C(0),
9720 UINT64_C(0),
9721 UINT64_C(0),
9722 UINT64_C(0),
9723 UINT64_C(0),
9724 UINT64_C(0),
9725 UINT64_C(0),
9726 UINT64_C(0),
9727 UINT64_C(0),
9728 UINT64_C(0),
9729 UINT64_C(0),
9730 UINT64_C(0),
9731 UINT64_C(0),
9732 UINT64_C(0),
9733 UINT64_C(0),
9734 UINT64_C(0),
9735 UINT64_C(0),
9736 UINT64_C(0),
9737 UINT64_C(0),
9738 UINT64_C(0),
9739 UINT64_C(0),
9740 UINT64_C(0),
9741 UINT64_C(0),
9742 UINT64_C(0),
9743 UINT64_C(0),
9744 UINT64_C(0),
9745 UINT64_C(0),
9746 UINT64_C(0),
9747 UINT64_C(0),
9748 UINT64_C(0),
9749 UINT64_C(0),
9750 UINT64_C(0),
9751 UINT64_C(0),
9752 UINT64_C(0),
9753 UINT64_C(0),
9754 UINT64_C(0),
9755 UINT64_C(0),
9756 UINT64_C(0),
9757 UINT64_C(0),
9758 UINT64_C(0),
9759 UINT64_C(0),
9760 UINT64_C(0),
9761 UINT64_C(0),
9762 UINT64_C(0),
9763 UINT64_C(0),
9764 UINT64_C(0),
9765 UINT64_C(0),
9766 UINT64_C(0),
9767 UINT64_C(0),
9768 UINT64_C(0),
9769 UINT64_C(0),
9770 UINT64_C(0),
9771 UINT64_C(0),
9772 UINT64_C(0),
9773 UINT64_C(0),
9774 UINT64_C(0),
9775 UINT64_C(0),
9776 UINT64_C(0),
9777 UINT64_C(0),
9778 UINT64_C(0),
9779 UINT64_C(0),
9780 UINT64_C(0),
9781 UINT64_C(0),
9782 UINT64_C(0),
9783 UINT64_C(0),
9784 UINT64_C(0),
9785 UINT64_C(0),
9786 UINT64_C(0),
9787 UINT64_C(0),
9788 UINT64_C(0),
9789 UINT64_C(0),
9790 UINT64_C(0),
9791 UINT64_C(0),
9792 UINT64_C(0),
9793 UINT64_C(0),
9794 UINT64_C(0),
9795 UINT64_C(0),
9796 UINT64_C(0),
9797 UINT64_C(0),
9798 UINT64_C(0),
9799 UINT64_C(0),
9800 UINT64_C(0),
9801 UINT64_C(0),
9802 UINT64_C(0),
9803 UINT64_C(0),
9804 UINT64_C(0),
9805 UINT64_C(0),
9806 UINT64_C(0),
9807 UINT64_C(0),
9808 UINT64_C(0),
9809 UINT64_C(0),
9810 UINT64_C(0),
9811 UINT64_C(0),
9812 UINT64_C(0),
9813 UINT64_C(0),
9814 UINT64_C(0),
9815 UINT64_C(0),
9816 UINT64_C(0),
9817 UINT64_C(0),
9818 UINT64_C(0),
9819 UINT64_C(0),
9820 UINT64_C(0),
9821 UINT64_C(0),
9822 UINT64_C(0),
9823 UINT64_C(0),
9824 UINT64_C(0),
9825 UINT64_C(0),
9826 UINT64_C(0),
9827 UINT64_C(0),
9828 UINT64_C(0),
9829 UINT64_C(0),
9830 UINT64_C(0),
9831 UINT64_C(0),
9832 UINT64_C(0),
9833 UINT64_C(0),
9834 UINT64_C(0),
9835 UINT64_C(0),
9836 UINT64_C(0),
9837 UINT64_C(0),
9838 UINT64_C(0),
9839 UINT64_C(0),
9840 UINT64_C(0),
9841 UINT64_C(0),
9842 UINT64_C(0),
9843 UINT64_C(0),
9844 UINT64_C(0),
9845 UINT64_C(0),
9846 UINT64_C(0),
9847 UINT64_C(0),
9848 UINT64_C(0),
9849 UINT64_C(0),
9850 UINT64_C(0),
9851 UINT64_C(0),
9852 UINT64_C(0),
9853 UINT64_C(0),
9854 UINT64_C(0),
9855 UINT64_C(0),
9856 UINT64_C(0),
9857 UINT64_C(0),
9858 UINT64_C(0),
9859 UINT64_C(0),
9860 UINT64_C(0),
9861 UINT64_C(0),
9862 UINT64_C(0),
9863 UINT64_C(0),
9864 UINT64_C(0),
9865 UINT64_C(0),
9866 UINT64_C(0),
9867 UINT64_C(0),
9868 UINT64_C(0),
9869 UINT64_C(0),
9870 UINT64_C(0),
9871 UINT64_C(0),
9872 UINT64_C(0),
9873 UINT64_C(0),
9874 UINT64_C(0),
9875 UINT64_C(0),
9876 UINT64_C(0),
9877 UINT64_C(0),
9878 UINT64_C(0),
9879 UINT64_C(0),
9880 UINT64_C(0),
9881 UINT64_C(0),
9882 UINT64_C(0),
9883 UINT64_C(0),
9884 UINT64_C(0),
9885 UINT64_C(0),
9886 UINT64_C(0),
9887 UINT64_C(0),
9888 UINT64_C(0),
9889 UINT64_C(0),
9890 UINT64_C(0),
9891 UINT64_C(0),
9892 UINT64_C(0),
9893 UINT64_C(0),
9894 UINT64_C(0),
9895 UINT64_C(0),
9896 UINT64_C(0),
9897 UINT64_C(0),
9898 UINT64_C(0),
9899 UINT64_C(0),
9900 UINT64_C(0),
9901 UINT64_C(0),
9902 UINT64_C(0),
9903 UINT64_C(0),
9904 UINT64_C(0),
9905 UINT64_C(0),
9906 UINT64_C(0),
9907 UINT64_C(0),
9908 UINT64_C(0),
9909 UINT64_C(0),
9910 UINT64_C(0),
9911 UINT64_C(0),
9912 UINT64_C(0),
9913 UINT64_C(0),
9914 UINT64_C(0),
9915 UINT64_C(0),
9916 UINT64_C(0),
9917 UINT64_C(0),
9918 UINT64_C(0),
9919 UINT64_C(0),
9920 UINT64_C(0),
9921 UINT64_C(0),
9922 UINT64_C(0),
9923 UINT64_C(0),
9924 UINT64_C(0),
9925 UINT64_C(0),
9926 UINT64_C(0),
9927 UINT64_C(0),
9928 UINT64_C(0),
9929 UINT64_C(0),
9930 UINT64_C(0),
9931 UINT64_C(0),
9932 UINT64_C(0),
9933 UINT64_C(0),
9934 UINT64_C(0),
9935 UINT64_C(0),
9936 UINT64_C(0),
9937 UINT64_C(0),
9938 UINT64_C(0),
9939 UINT64_C(0),
9940 UINT64_C(0),
9941 UINT64_C(0),
9942 UINT64_C(0),
9943 UINT64_C(0),
9944 UINT64_C(0),
9945 UINT64_C(0),
9946 UINT64_C(0),
9947 UINT64_C(0),
9948 UINT64_C(0),
9949 UINT64_C(0),
9950 UINT64_C(0),
9951 UINT64_C(0),
9952 UINT64_C(0),
9953 UINT64_C(0),
9954 UINT64_C(0),
9955 UINT64_C(0),
9956 UINT64_C(0),
9957 UINT64_C(0),
9958 UINT64_C(0),
9959 UINT64_C(0),
9960 UINT64_C(0),
9961 UINT64_C(0),
9962 UINT64_C(0),
9963 UINT64_C(0),
9964 UINT64_C(0),
9965 UINT64_C(0),
9966 UINT64_C(0),
9967 UINT64_C(0),
9968 UINT64_C(0),
9969 UINT64_C(0),
9970 UINT64_C(0),
9971 UINT64_C(0),
9972 UINT64_C(0),
9973 UINT64_C(0),
9974 UINT64_C(0),
9975 UINT64_C(0),
9976 UINT64_C(0),
9977 UINT64_C(0),
9978 UINT64_C(0),
9979 UINT64_C(0),
9980 UINT64_C(0),
9981 UINT64_C(0),
9982 UINT64_C(0),
9983 UINT64_C(0),
9984 UINT64_C(0),
9985 UINT64_C(0),
9986 UINT64_C(0),
9987 UINT64_C(0),
9988 UINT64_C(0),
9989 UINT64_C(0),
9990 UINT64_C(0),
9991 UINT64_C(0),
9992 UINT64_C(0),
9993 UINT64_C(0),
9994 UINT64_C(0),
9995 UINT64_C(0),
9996 UINT64_C(0),
9997 UINT64_C(0),
9998 UINT64_C(0),
9999 UINT64_C(0),
10000 UINT64_C(0),
10001 UINT64_C(0),
10002 UINT64_C(0),
10003 UINT64_C(0),
10004 UINT64_C(0),
10005 UINT64_C(0),
10006 UINT64_C(0),
10007 UINT64_C(0),
10008 UINT64_C(0),
10009 UINT64_C(0),
10010 UINT64_C(0),
10011 UINT64_C(0),
10012 UINT64_C(0),
10013 UINT64_C(0),
10014 UINT64_C(0),
10015 UINT64_C(0),
10016 UINT64_C(0),
10017 UINT64_C(0),
10018 UINT64_C(0),
10019 UINT64_C(0),
10020 UINT64_C(0),
10021 UINT64_C(0),
10022 UINT64_C(0),
10023 UINT64_C(0),
10024 UINT64_C(0),
10025 UINT64_C(0),
10026 UINT64_C(0),
10027 UINT64_C(0),
10028 UINT64_C(0),
10029 UINT64_C(0),
10030 UINT64_C(0),
10031 UINT64_C(0),
10032 UINT64_C(0),
10033 UINT64_C(0),
10034 UINT64_C(0),
10035 UINT64_C(0),
10036 UINT64_C(0),
10037 UINT64_C(0),
10038 UINT64_C(0),
10039 UINT64_C(0),
10040 UINT64_C(0),
10041 UINT64_C(0),
10042 UINT64_C(0),
10043 UINT64_C(0),
10044 UINT64_C(0),
10045 UINT64_C(0),
10046 UINT64_C(0),
10047 UINT64_C(0),
10048 UINT64_C(0),
10049 UINT64_C(0),
10050 UINT64_C(0),
10051 UINT64_C(0),
10052 UINT64_C(0),
10053 UINT64_C(0),
10054 UINT64_C(0),
10055 UINT64_C(0),
10056 UINT64_C(0),
10057 UINT64_C(0),
10058 UINT64_C(0),
10059 UINT64_C(0),
10060 UINT64_C(0),
10061 UINT64_C(0),
10062 UINT64_C(0),
10063 UINT64_C(0),
10064 UINT64_C(0),
10065 UINT64_C(0),
10066 UINT64_C(0),
10067 UINT64_C(0),
10068 UINT64_C(0),
10069 UINT64_C(0),
10070 UINT64_C(0),
10071 UINT64_C(0),
10072 UINT64_C(0),
10073 UINT64_C(0),
10074 UINT64_C(0),
10075 UINT64_C(0),
10076 UINT64_C(0),
10077 UINT64_C(0),
10078 UINT64_C(0),
10079 UINT64_C(0),
10080 UINT64_C(0),
10081 UINT64_C(0),
10082 UINT64_C(0),
10083 UINT64_C(0),
10084 UINT64_C(0),
10085 UINT64_C(0),
10086 UINT64_C(0),
10087 UINT64_C(0),
10088 UINT64_C(0),
10089 UINT64_C(0),
10090 UINT64_C(0),
10091 UINT64_C(0),
10092 UINT64_C(0),
10093 UINT64_C(0),
10094 UINT64_C(0),
10095 UINT64_C(0),
10096 UINT64_C(0),
10097 UINT64_C(0),
10098 UINT64_C(0),
10099 UINT64_C(0),
10100 UINT64_C(0),
10101 UINT64_C(0),
10102 UINT64_C(0),
10103 UINT64_C(0),
10104 UINT64_C(0),
10105 UINT64_C(0),
10106 UINT64_C(0),
10107 UINT64_C(0),
10108 UINT64_C(0),
10109 UINT64_C(0),
10110 UINT64_C(0),
10111 UINT64_C(0),
10112 UINT64_C(0),
10113 UINT64_C(0),
10114 UINT64_C(0),
10115 UINT64_C(0),
10116 UINT64_C(0),
10117 UINT64_C(0),
10118 UINT64_C(0),
10119 UINT64_C(0),
10120 UINT64_C(0),
10121 UINT64_C(0),
10122 UINT64_C(0),
10123 UINT64_C(0),
10124 UINT64_C(0),
10125 UINT64_C(0),
10126 UINT64_C(0),
10127 UINT64_C(0),
10128 UINT64_C(0),
10129 UINT64_C(0),
10130 UINT64_C(0),
10131 UINT64_C(0),
10132 UINT64_C(0),
10133 UINT64_C(0),
10134 UINT64_C(0),
10135 UINT64_C(0),
10136 UINT64_C(0),
10137 UINT64_C(0),
10138 UINT64_C(0),
10139 UINT64_C(0),
10140 UINT64_C(0),
10141 UINT64_C(0),
10142 UINT64_C(0),
10143 UINT64_C(0),
10144 UINT64_C(0),
10145 UINT64_C(0),
10146 UINT64_C(0),
10147 UINT64_C(0),
10148 UINT64_C(0),
10149 UINT64_C(0),
10150 UINT64_C(0),
10151 UINT64_C(0),
10152 UINT64_C(0),
10153 UINT64_C(0),
10154 UINT64_C(0),
10155 UINT64_C(0),
10156 UINT64_C(0),
10157 UINT64_C(0),
10158 UINT64_C(0),
10159 UINT64_C(0),
10160 UINT64_C(0),
10161 UINT64_C(0),
10162 UINT64_C(0),
10163 UINT64_C(0),
10164 UINT64_C(0),
10165 UINT64_C(0),
10166 UINT64_C(0),
10167 UINT64_C(0),
10168 UINT64_C(0),
10169 UINT64_C(0),
10170 UINT64_C(0),
10171 UINT64_C(0),
10172 UINT64_C(0),
10173 UINT64_C(0),
10174 UINT64_C(0),
10175 UINT64_C(0),
10176 UINT64_C(0),
10177 UINT64_C(0),
10178 UINT64_C(0),
10179 UINT64_C(0),
10180 UINT64_C(0),
10181 UINT64_C(0),
10182 UINT64_C(0),
10183 UINT64_C(0),
10184 UINT64_C(0),
10185 UINT64_C(0),
10186 UINT64_C(0),
10187 UINT64_C(0),
10188 UINT64_C(0),
10189 UINT64_C(0),
10190 UINT64_C(0),
10191 UINT64_C(0),
10192 UINT64_C(0),
10193 UINT64_C(0),
10194 UINT64_C(0),
10195 UINT64_C(0),
10196 UINT64_C(0),
10197 UINT64_C(0),
10198 UINT64_C(0),
10199 UINT64_C(0),
10200 UINT64_C(0),
10201 UINT64_C(0),
10202 UINT64_C(0),
10203 UINT64_C(0),
10204 UINT64_C(0),
10205 UINT64_C(0),
10206 UINT64_C(0),
10207 UINT64_C(0),
10208 UINT64_C(0),
10209 UINT64_C(0),
10210 UINT64_C(0),
10211 UINT64_C(0),
10212 UINT64_C(0),
10213 UINT64_C(0),
10214 UINT64_C(0),
10215 UINT64_C(0),
10216 UINT64_C(0),
10217 UINT64_C(0),
10218 UINT64_C(0),
10219 UINT64_C(0),
10220 UINT64_C(0),
10221 UINT64_C(0),
10222 UINT64_C(0),
10223 UINT64_C(0),
10224 UINT64_C(0),
10225 UINT64_C(0),
10226 UINT64_C(0),
10227 UINT64_C(0),
10228 UINT64_C(0),
10229 UINT64_C(0),
10230 UINT64_C(0),
10231 UINT64_C(0),
10232 UINT64_C(0),
10233 UINT64_C(0),
10234 UINT64_C(0),
10235 UINT64_C(0),
10236 UINT64_C(0),
10237 UINT64_C(0),
10238 UINT64_C(0),
10239 UINT64_C(0),
10240 UINT64_C(0),
10241 UINT64_C(0),
10242 UINT64_C(0),
10243 UINT64_C(0),
10244 UINT64_C(0),
10245 UINT64_C(0),
10246 UINT64_C(0),
10247 UINT64_C(0),
10248 UINT64_C(0),
10249 UINT64_C(0),
10250 UINT64_C(0),
10251 UINT64_C(0),
10252 UINT64_C(0),
10253 UINT64_C(0),
10254 UINT64_C(0),
10255 UINT64_C(0),
10256 UINT64_C(0),
10257 UINT64_C(0),
10258 UINT64_C(0),
10259 UINT64_C(0),
10260 UINT64_C(0),
10261 UINT64_C(0),
10262 UINT64_C(0),
10263 UINT64_C(0),
10264 UINT64_C(0),
10265 UINT64_C(0),
10266 UINT64_C(0),
10267 UINT64_C(0),
10268 UINT64_C(0),
10269 UINT64_C(0),
10270 UINT64_C(0),
10271 UINT64_C(0),
10272 UINT64_C(0),
10273 UINT64_C(0),
10274 UINT64_C(0),
10275 UINT64_C(0),
10276 UINT64_C(0),
10277 UINT64_C(0),
10278 UINT64_C(0),
10279 UINT64_C(0),
10280 UINT64_C(0),
10281 UINT64_C(0),
10282 UINT64_C(0),
10283 UINT64_C(0),
10284 UINT64_C(0),
10285 UINT64_C(0),
10286 UINT64_C(0),
10287 UINT64_C(0),
10288 UINT64_C(0),
10289 UINT64_C(0),
10290 UINT64_C(0),
10291 UINT64_C(0),
10292 UINT64_C(0),
10293 UINT64_C(0),
10294 UINT64_C(0),
10295 UINT64_C(0),
10296 UINT64_C(0),
10297 UINT64_C(0),
10298 UINT64_C(0),
10299 UINT64_C(0),
10300 UINT64_C(0),
10301 UINT64_C(0),
10302 UINT64_C(0),
10303 UINT64_C(0),
10304 UINT64_C(0),
10305 UINT64_C(0),
10306 UINT64_C(0),
10307 UINT64_C(0),
10308 UINT64_C(0),
10309 UINT64_C(0),
10310 UINT64_C(0),
10311 UINT64_C(0),
10312 UINT64_C(0),
10313 UINT64_C(0),
10314 UINT64_C(0),
10315 UINT64_C(0),
10316 UINT64_C(0),
10317 UINT64_C(0),
10318 UINT64_C(0),
10319 UINT64_C(0),
10320 UINT64_C(0),
10321 UINT64_C(0),
10322 UINT64_C(0),
10323 UINT64_C(0),
10324 UINT64_C(0),
10325 UINT64_C(0),
10326 UINT64_C(0),
10327 UINT64_C(0),
10328 UINT64_C(0),
10329 UINT64_C(0),
10330 UINT64_C(0),
10331 UINT64_C(0),
10332 UINT64_C(0),
10333 UINT64_C(0),
10334 UINT64_C(0),
10335 UINT64_C(0),
10336 UINT64_C(0),
10337 UINT64_C(0),
10338 UINT64_C(0),
10339 UINT64_C(0),
10340 UINT64_C(0),
10341 UINT64_C(0),
10342 UINT64_C(0),
10343 UINT64_C(0),
10344 UINT64_C(0),
10345 UINT64_C(0),
10346 UINT64_C(0),
10347 UINT64_C(0),
10348 UINT64_C(0),
10349 UINT64_C(0),
10350 UINT64_C(0),
10351 UINT64_C(0),
10352 UINT64_C(0),
10353 UINT64_C(0),
10354 UINT64_C(0),
10355 UINT64_C(0),
10356 UINT64_C(0),
10357 UINT64_C(0),
10358 UINT64_C(0),
10359 UINT64_C(0),
10360 UINT64_C(0),
10361 UINT64_C(0),
10362 UINT64_C(0),
10363 UINT64_C(0),
10364 UINT64_C(0),
10365 UINT64_C(0),
10366 UINT64_C(0),
10367 UINT64_C(0),
10368 UINT64_C(0),
10369 UINT64_C(0),
10370 UINT64_C(0),
10371 UINT64_C(0),
10372 UINT64_C(0),
10373 UINT64_C(0),
10374 UINT64_C(0),
10375 UINT64_C(0),
10376 UINT64_C(0),
10377 UINT64_C(0),
10378 UINT64_C(0),
10379 UINT64_C(0),
10380 UINT64_C(0),
10381 UINT64_C(0),
10382 UINT64_C(0),
10383 UINT64_C(0),
10384 UINT64_C(0),
10385 UINT64_C(0),
10386 UINT64_C(0),
10387 UINT64_C(0),
10388 UINT64_C(0),
10389 UINT64_C(0),
10390 UINT64_C(0),
10391 UINT64_C(0),
10392 UINT64_C(0),
10393 UINT64_C(0),
10394 UINT64_C(0),
10395 UINT64_C(0),
10396 UINT64_C(0),
10397 UINT64_C(0),
10398 UINT64_C(0),
10399 UINT64_C(0),
10400 UINT64_C(0),
10401 UINT64_C(0),
10402 UINT64_C(0),
10403 UINT64_C(0),
10404 UINT64_C(0),
10405 UINT64_C(0),
10406 UINT64_C(0),
10407 UINT64_C(0),
10408 UINT64_C(0),
10409 UINT64_C(0),
10410 UINT64_C(0),
10411 UINT64_C(0),
10412 UINT64_C(0),
10413 UINT64_C(0),
10414 UINT64_C(0),
10415 UINT64_C(0),
10416 UINT64_C(0),
10417 UINT64_C(0),
10418 UINT64_C(0),
10419 UINT64_C(0),
10420 UINT64_C(0),
10421 UINT64_C(0),
10422 UINT64_C(0),
10423 UINT64_C(0),
10424 UINT64_C(0),
10425 UINT64_C(0),
10426 UINT64_C(0),
10427 UINT64_C(0),
10428 UINT64_C(0),
10429 UINT64_C(0),
10430 UINT64_C(0),
10431 UINT64_C(0),
10432 UINT64_C(0),
10433 UINT64_C(0),
10434 UINT64_C(0),
10435 UINT64_C(0),
10436 UINT64_C(0),
10437 UINT64_C(0),
10438 UINT64_C(0),
10439 UINT64_C(0),
10440 UINT64_C(0),
10441 UINT64_C(0),
10442 UINT64_C(0),
10443 UINT64_C(0),
10444 UINT64_C(0),
10445 UINT64_C(0),
10446 UINT64_C(0),
10447 UINT64_C(0),
10448 UINT64_C(0),
10449 UINT64_C(0),
10450 UINT64_C(0),
10451 UINT64_C(0),
10452 UINT64_C(0),
10453 UINT64_C(0),
10454 UINT64_C(0),
10455 UINT64_C(0),
10456 UINT64_C(0),
10457 UINT64_C(0),
10458 UINT64_C(0),
10459 UINT64_C(0),
10460 UINT64_C(0),
10461 UINT64_C(0),
10462 UINT64_C(0),
10463 UINT64_C(0),
10464 UINT64_C(0),
10465 UINT64_C(0),
10466 UINT64_C(0),
10467 UINT64_C(0),
10468 UINT64_C(0),
10469 UINT64_C(0),
10470 UINT64_C(0),
10471 UINT64_C(0),
10472 UINT64_C(0),
10473 UINT64_C(0),
10474 UINT64_C(0),
10475 UINT64_C(0),
10476 UINT64_C(0),
10477 UINT64_C(0),
10478 UINT64_C(0),
10479 UINT64_C(0),
10480 UINT64_C(0),
10481 UINT64_C(0),
10482 UINT64_C(0),
10483 UINT64_C(0),
10484 UINT64_C(0),
10485 UINT64_C(0),
10486 UINT64_C(0),
10487 UINT64_C(0),
10488 UINT64_C(0),
10489 UINT64_C(0),
10490 UINT64_C(0),
10491 UINT64_C(0),
10492 UINT64_C(0),
10493 UINT64_C(0),
10494 UINT64_C(0),
10495 UINT64_C(0),
10496 UINT64_C(0),
10497 UINT64_C(0),
10498 UINT64_C(0),
10499 UINT64_C(0),
10500 UINT64_C(0),
10501 UINT64_C(0),
10502 UINT64_C(0),
10503 UINT64_C(0),
10504 UINT64_C(0),
10505 UINT64_C(0),
10506 UINT64_C(0),
10507 UINT64_C(0),
10508 UINT64_C(0),
10509 UINT64_C(0),
10510 UINT64_C(0),
10511 UINT64_C(0),
10512 UINT64_C(0),
10513 UINT64_C(0),
10514 UINT64_C(0),
10515 UINT64_C(0),
10516 UINT64_C(0),
10517 UINT64_C(0),
10518 UINT64_C(0),
10519 UINT64_C(0),
10520 UINT64_C(0),
10521 UINT64_C(0),
10522 UINT64_C(0),
10523 UINT64_C(0),
10524 UINT64_C(0),
10525 UINT64_C(0),
10526 UINT64_C(0),
10527 UINT64_C(0),
10528 UINT64_C(0),
10529 UINT64_C(0),
10530 UINT64_C(0),
10531 UINT64_C(0),
10532 UINT64_C(0),
10533 UINT64_C(0),
10534 UINT64_C(0),
10535 UINT64_C(0),
10536 UINT64_C(0),
10537 UINT64_C(0),
10538 UINT64_C(0),
10539 UINT64_C(0),
10540 UINT64_C(0),
10541 UINT64_C(0),
10542 UINT64_C(0),
10543 UINT64_C(0),
10544 UINT64_C(0),
10545 UINT64_C(0),
10546 UINT64_C(0),
10547 UINT64_C(0),
10548 UINT64_C(0),
10549 UINT64_C(0),
10550 UINT64_C(0),
10551 UINT64_C(0),
10552 UINT64_C(0),
10553 UINT64_C(0),
10554 UINT64_C(0),
10555 UINT64_C(0),
10556 UINT64_C(0),
10557 UINT64_C(0),
10558 UINT64_C(0),
10559 UINT64_C(0),
10560 UINT64_C(0),
10561 UINT64_C(0),
10562 UINT64_C(0),
10563 UINT64_C(0),
10564 UINT64_C(0),
10565 UINT64_C(0),
10566 UINT64_C(0),
10567 UINT64_C(0),
10568 UINT64_C(0),
10569 UINT64_C(0),
10570 UINT64_C(0),
10571 UINT64_C(0),
10572 UINT64_C(0),
10573 UINT64_C(0),
10574 UINT64_C(0),
10575 UINT64_C(0),
10576 UINT64_C(0),
10577 UINT64_C(0),
10578 UINT64_C(0),
10579 UINT64_C(0),
10580 UINT64_C(0),
10581 UINT64_C(0),
10582 UINT64_C(0),
10583 UINT64_C(0),
10584 UINT64_C(0),
10585 UINT64_C(0),
10586 UINT64_C(0),
10587 UINT64_C(0),
10588 UINT64_C(0),
10589 UINT64_C(0),
10590 UINT64_C(0),
10591 UINT64_C(0),
10592 UINT64_C(0),
10593 UINT64_C(0),
10594 UINT64_C(0),
10595 UINT64_C(0),
10596 UINT64_C(0),
10597 UINT64_C(0),
10598 UINT64_C(0),
10599 UINT64_C(0),
10600 UINT64_C(0),
10601 UINT64_C(0),
10602 UINT64_C(0),
10603 UINT64_C(0),
10604 UINT64_C(0),
10605 UINT64_C(0),
10606 UINT64_C(0),
10607 UINT64_C(0),
10608 UINT64_C(0),
10609 UINT64_C(0),
10610 UINT64_C(0),
10611 UINT64_C(0),
10612 UINT64_C(0),
10613 UINT64_C(0),
10614 UINT64_C(0),
10615 UINT64_C(0),
10616 UINT64_C(0),
10617 UINT64_C(0),
10618 UINT64_C(0),
10619 UINT64_C(0),
10620 UINT64_C(0),
10621 UINT64_C(0),
10622 UINT64_C(0),
10623 UINT64_C(0),
10624 UINT64_C(0),
10625 UINT64_C(0),
10626 UINT64_C(0),
10627 UINT64_C(0),
10628 UINT64_C(0),
10629 UINT64_C(0),
10630 UINT64_C(0),
10631 UINT64_C(0),
10632 UINT64_C(0),
10633 UINT64_C(0),
10634 UINT64_C(0),
10635 UINT64_C(0),
10636 UINT64_C(0),
10637 UINT64_C(0),
10638 UINT64_C(0),
10639 UINT64_C(0),
10640 UINT64_C(0),
10641 UINT64_C(0),
10642 UINT64_C(0),
10643 UINT64_C(0),
10644 UINT64_C(0),
10645 UINT64_C(0),
10646 UINT64_C(0),
10647 UINT64_C(0),
10648 UINT64_C(0),
10649 UINT64_C(0),
10650 UINT64_C(0),
10651 UINT64_C(0),
10652 UINT64_C(0),
10653 UINT64_C(0),
10654 UINT64_C(0),
10655 UINT64_C(0),
10656 UINT64_C(0),
10657 UINT64_C(0),
10658 UINT64_C(0),
10659 UINT64_C(0),
10660 UINT64_C(0),
10661 UINT64_C(0),
10662 UINT64_C(0),
10663 UINT64_C(0),
10664 UINT64_C(0),
10665 UINT64_C(0),
10666 UINT64_C(0),
10667 UINT64_C(0),
10668 UINT64_C(0),
10669 UINT64_C(0),
10670 UINT64_C(0),
10671 UINT64_C(0),
10672 UINT64_C(0),
10673 UINT64_C(0),
10674 UINT64_C(0),
10675 UINT64_C(0),
10676 UINT64_C(0),
10677 UINT64_C(0),
10678 UINT64_C(0),
10679 UINT64_C(0),
10680 UINT64_C(0),
10681 UINT64_C(0),
10682 UINT64_C(0),
10683 UINT64_C(0),
10684 UINT64_C(0),
10685 UINT64_C(0),
10686 UINT64_C(0),
10687 UINT64_C(0),
10688 UINT64_C(0),
10689 UINT64_C(0),
10690 UINT64_C(0),
10691 UINT64_C(0),
10692 UINT64_C(0),
10693 UINT64_C(0),
10694 UINT64_C(0),
10695 UINT64_C(0),
10696 UINT64_C(0),
10697 UINT64_C(0),
10698 UINT64_C(0),
10699 UINT64_C(0),
10700 UINT64_C(0),
10701 UINT64_C(0),
10702 UINT64_C(0),
10703 UINT64_C(0),
10704 UINT64_C(0),
10705 UINT64_C(0),
10706 UINT64_C(0),
10707 UINT64_C(0),
10708 UINT64_C(0),
10709 UINT64_C(0),
10710 UINT64_C(0),
10711 UINT64_C(0),
10712 UINT64_C(0),
10713 UINT64_C(0),
10714 UINT64_C(0),
10715 UINT64_C(0),
10716 UINT64_C(0),
10717 UINT64_C(0),
10718 UINT64_C(0),
10719 UINT64_C(0),
10720 UINT64_C(0),
10721 UINT64_C(0),
10722 UINT64_C(0),
10723 UINT64_C(0),
10724 UINT64_C(0),
10725 UINT64_C(0),
10726 UINT64_C(0),
10727 UINT64_C(0),
10728 UINT64_C(0),
10729 UINT64_C(0),
10730 UINT64_C(0),
10731 UINT64_C(0),
10732 UINT64_C(0),
10733 UINT64_C(0),
10734 UINT64_C(0),
10735 UINT64_C(0),
10736 UINT64_C(0),
10737 UINT64_C(0),
10738 UINT64_C(0),
10739 UINT64_C(0),
10740 UINT64_C(0),
10741 UINT64_C(0),
10742 UINT64_C(0),
10743 UINT64_C(0),
10744 UINT64_C(0),
10745 UINT64_C(0),
10746 UINT64_C(0),
10747 UINT64_C(0),
10748 UINT64_C(0),
10749 UINT64_C(0),
10750 UINT64_C(0),
10751 UINT64_C(0),
10752 UINT64_C(0),
10753 UINT64_C(0),
10754 UINT64_C(0),
10755 UINT64_C(0),
10756 UINT64_C(0),
10757 UINT64_C(0),
10758 UINT64_C(0),
10759 UINT64_C(0),
10760 UINT64_C(0),
10761 UINT64_C(0),
10762 UINT64_C(0),
10763 UINT64_C(0),
10764 UINT64_C(0),
10765 UINT64_C(0),
10766 UINT64_C(0),
10767 UINT64_C(0),
10768 UINT64_C(0),
10769 UINT64_C(0),
10770 UINT64_C(0),
10771 UINT64_C(0),
10772 UINT64_C(0),
10773 UINT64_C(0),
10774 UINT64_C(0),
10775 UINT64_C(0),
10776 UINT64_C(0),
10777 UINT64_C(0),
10778 UINT64_C(0),
10779 UINT64_C(0),
10780 UINT64_C(0),
10781 UINT64_C(0),
10782 UINT64_C(0),
10783 UINT64_C(0),
10784 UINT64_C(0),
10785 UINT64_C(0),
10786 UINT64_C(0),
10787 UINT64_C(0),
10788 UINT64_C(0),
10789 UINT64_C(0),
10790 UINT64_C(0),
10791 UINT64_C(0),
10792 UINT64_C(0),
10793 UINT64_C(0),
10794 UINT64_C(0),
10795 UINT64_C(0),
10796 UINT64_C(0),
10797 UINT64_C(0),
10798 UINT64_C(0),
10799 UINT64_C(0),
10800 UINT64_C(0),
10801 UINT64_C(0),
10802 UINT64_C(0),
10803 UINT64_C(0),
10804 UINT64_C(0),
10805 UINT64_C(0),
10806 UINT64_C(0),
10807 UINT64_C(0),
10808 UINT64_C(0),
10809 UINT64_C(0),
10810 UINT64_C(0),
10811 UINT64_C(0),
10812 UINT64_C(0),
10813 UINT64_C(0),
10814 UINT64_C(0),
10815 UINT64_C(0),
10816 UINT64_C(0),
10817 UINT64_C(0),
10818 UINT64_C(0),
10819 UINT64_C(0),
10820 UINT64_C(0),
10821 UINT64_C(0),
10822 UINT64_C(0),
10823 UINT64_C(0),
10824 UINT64_C(0),
10825 UINT64_C(0),
10826 UINT64_C(0),
10827 UINT64_C(0),
10828 UINT64_C(0),
10829 UINT64_C(0),
10830 UINT64_C(0),
10831 UINT64_C(0),
10832 UINT64_C(0),
10833 UINT64_C(0),
10834 UINT64_C(0),
10835 UINT64_C(0),
10836 UINT64_C(0),
10837 UINT64_C(0),
10838 UINT64_C(0),
10839 UINT64_C(0),
10840 UINT64_C(0),
10841 UINT64_C(0),
10842 UINT64_C(0),
10843 UINT64_C(0),
10844 UINT64_C(0),
10845 UINT64_C(0),
10846 UINT64_C(0),
10847 UINT64_C(0),
10848 UINT64_C(0),
10849 UINT64_C(0),
10850 UINT64_C(0),
10851 UINT64_C(0),
10852 UINT64_C(0),
10853 UINT64_C(0),
10854 UINT64_C(0),
10855 UINT64_C(0),
10856 UINT64_C(0),
10857 UINT64_C(0),
10858 UINT64_C(0),
10859 UINT64_C(0),
10860 UINT64_C(0),
10861 UINT64_C(0),
10862 UINT64_C(0),
10863 UINT64_C(0),
10864 UINT64_C(0),
10865 UINT64_C(0),
10866 UINT64_C(0),
10867 UINT64_C(0),
10868 UINT64_C(0),
10869 UINT64_C(0),
10870 UINT64_C(0),
10871 UINT64_C(0),
10872 UINT64_C(0),
10873 UINT64_C(0),
10874 UINT64_C(0),
10875 UINT64_C(0),
10876 UINT64_C(0),
10877 UINT64_C(0),
10878 UINT64_C(0),
10879 UINT64_C(0),
10880 UINT64_C(0),
10881 UINT64_C(0),
10882 UINT64_C(0),
10883 UINT64_C(0),
10884 UINT64_C(0),
10885 UINT64_C(0),
10886 UINT64_C(0),
10887 UINT64_C(0),
10888 UINT64_C(0),
10889 UINT64_C(0),
10890 UINT64_C(0),
10891 UINT64_C(0),
10892 UINT64_C(0),
10893 UINT64_C(0),
10894 UINT64_C(0),
10895 UINT64_C(0),
10896 UINT64_C(0),
10897 UINT64_C(0),
10898 UINT64_C(0),
10899 UINT64_C(0),
10900 UINT64_C(0),
10901 UINT64_C(0),
10902 UINT64_C(0),
10903 UINT64_C(0),
10904 UINT64_C(0),
10905 UINT64_C(0),
10906 UINT64_C(0),
10907 UINT64_C(0),
10908 UINT64_C(0),
10909 UINT64_C(0),
10910 UINT64_C(0),
10911 UINT64_C(0),
10912 UINT64_C(0),
10913 UINT64_C(0),
10914 UINT64_C(0),
10915 UINT64_C(0),
10916 UINT64_C(0),
10917 UINT64_C(0),
10918 UINT64_C(0),
10919 UINT64_C(0),
10920 UINT64_C(0),
10921 UINT64_C(0),
10922 UINT64_C(0),
10923 UINT64_C(0),
10924 UINT64_C(0),
10925 UINT64_C(0),
10926 UINT64_C(0),
10927 UINT64_C(0),
10928 UINT64_C(0),
10929 UINT64_C(0),
10930 UINT64_C(0),
10931 UINT64_C(0),
10932 UINT64_C(0),
10933 UINT64_C(0),
10934 UINT64_C(0),
10935 UINT64_C(0),
10936 UINT64_C(0),
10937 UINT64_C(0),
10938 UINT64_C(0),
10939 UINT64_C(0),
10940 UINT64_C(0),
10941 UINT64_C(0),
10942 UINT64_C(0),
10943 UINT64_C(0),
10944 UINT64_C(0),
10945 UINT64_C(0),
10946 UINT64_C(0),
10947 UINT64_C(0),
10948 UINT64_C(0),
10949 UINT64_C(0),
10950 UINT64_C(0),
10951 UINT64_C(0),
10952 UINT64_C(0),
10953 UINT64_C(0),
10954 UINT64_C(0),
10955 UINT64_C(0),
10956 UINT64_C(0),
10957 UINT64_C(0),
10958 UINT64_C(0),
10959 UINT64_C(0),
10960 UINT64_C(0),
10961 UINT64_C(0),
10962 UINT64_C(0),
10963 UINT64_C(0),
10964 UINT64_C(0),
10965 UINT64_C(0),
10966 UINT64_C(0),
10967 UINT64_C(0),
10968 UINT64_C(0),
10969 UINT64_C(0),
10970 UINT64_C(0),
10971 UINT64_C(0),
10972 UINT64_C(0),
10973 UINT64_C(0),
10974 UINT64_C(0),
10975 UINT64_C(0),
10976 UINT64_C(0),
10977 UINT64_C(0),
10978 UINT64_C(0),
10979 UINT64_C(0),
10980 UINT64_C(0),
10981 UINT64_C(0),
10982 UINT64_C(0),
10983 UINT64_C(0),
10984 UINT64_C(0),
10985 UINT64_C(0),
10986 UINT64_C(0),
10987 UINT64_C(0),
10988 UINT64_C(0),
10989 UINT64_C(0),
10990 UINT64_C(0),
10991 UINT64_C(0),
10992 UINT64_C(0),
10993 UINT64_C(0),
10994 UINT64_C(0),
10995 UINT64_C(0),
10996 UINT64_C(0),
10997 UINT64_C(0),
10998 UINT64_C(0),
10999 UINT64_C(0),
11000 UINT64_C(0),
11001 UINT64_C(0),
11002 UINT64_C(0),
11003 UINT64_C(0),
11004 UINT64_C(0),
11005 UINT64_C(0),
11006 UINT64_C(0),
11007 UINT64_C(0),
11008 UINT64_C(0),
11009 UINT64_C(0),
11010 UINT64_C(0),
11011 UINT64_C(0),
11012 UINT64_C(0),
11013 UINT64_C(0),
11014 UINT64_C(0),
11015 UINT64_C(0),
11016 UINT64_C(0),
11017 UINT64_C(0),
11018 UINT64_C(0),
11019 UINT64_C(0),
11020 UINT64_C(0),
11021 UINT64_C(0),
11022 UINT64_C(0),
11023 UINT64_C(0),
11024 UINT64_C(0),
11025 UINT64_C(0),
11026 UINT64_C(0),
11027 UINT64_C(0),
11028 UINT64_C(0),
11029 UINT64_C(0),
11030 UINT64_C(0),
11031 UINT64_C(0),
11032 UINT64_C(0),
11033 UINT64_C(0),
11034 UINT64_C(0),
11035 UINT64_C(0),
11036 UINT64_C(0),
11037 UINT64_C(0),
11038 UINT64_C(0),
11039 UINT64_C(0),
11040 UINT64_C(0),
11041 UINT64_C(0),
11042 UINT64_C(0),
11043 UINT64_C(0),
11044 UINT64_C(0),
11045 UINT64_C(0),
11046 UINT64_C(0),
11047 UINT64_C(0),
11048 UINT64_C(0),
11049 UINT64_C(0),
11050 UINT64_C(0),
11051 UINT64_C(0),
11052 UINT64_C(0),
11053 UINT64_C(0),
11054 UINT64_C(0),
11055 UINT64_C(0),
11056 UINT64_C(0),
11057 UINT64_C(0),
11058 UINT64_C(0),
11059 UINT64_C(0),
11060 UINT64_C(0),
11061 UINT64_C(0),
11062 UINT64_C(0),
11063 UINT64_C(0),
11064 UINT64_C(0),
11065 UINT64_C(0),
11066 UINT64_C(0),
11067 UINT64_C(0),
11068 UINT64_C(0),
11069 UINT64_C(0),
11070 UINT64_C(0),
11071 UINT64_C(0),
11072 UINT64_C(0),
11073 UINT64_C(0),
11074 UINT64_C(0),
11075 UINT64_C(0),
11076 UINT64_C(0),
11077 UINT64_C(0),
11078 UINT64_C(0),
11079 UINT64_C(0),
11080 UINT64_C(0),
11081 UINT64_C(0),
11082 UINT64_C(0),
11083 UINT64_C(0),
11084 UINT64_C(0),
11085 UINT64_C(0),
11086 UINT64_C(0),
11087 UINT64_C(0),
11088 UINT64_C(0),
11089 UINT64_C(0),
11090 UINT64_C(0),
11091 UINT64_C(0),
11092 UINT64_C(0),
11093 UINT64_C(0),
11094 UINT64_C(0),
11095 UINT64_C(0),
11096 UINT64_C(0),
11097 UINT64_C(0),
11098 UINT64_C(0),
11099 UINT64_C(0),
11100 UINT64_C(0),
11101 UINT64_C(0),
11102 UINT64_C(0),
11103 UINT64_C(0),
11104 UINT64_C(0),
11105 UINT64_C(0),
11106 UINT64_C(0),
11107 UINT64_C(0),
11108 UINT64_C(0),
11109 UINT64_C(0),
11110 UINT64_C(0),
11111 UINT64_C(0),
11112 UINT64_C(0),
11113 UINT64_C(0),
11114 UINT64_C(0),
11115 UINT64_C(0),
11116 UINT64_C(0),
11117 UINT64_C(0),
11118 UINT64_C(0),
11119 UINT64_C(0),
11120 UINT64_C(0),
11121 UINT64_C(0),
11122 UINT64_C(0),
11123 UINT64_C(0),
11124 UINT64_C(0),
11125 UINT64_C(0),
11126 UINT64_C(0),
11127 UINT64_C(0),
11128 UINT64_C(0),
11129 UINT64_C(0),
11130 UINT64_C(0),
11131 UINT64_C(0),
11132 UINT64_C(0),
11133 UINT64_C(0),
11134 UINT64_C(0),
11135 UINT64_C(0),
11136 UINT64_C(0),
11137 UINT64_C(0),
11138 UINT64_C(0),
11139 UINT64_C(0),
11140 UINT64_C(0),
11141 UINT64_C(0),
11142 UINT64_C(0),
11143 UINT64_C(0),
11144 UINT64_C(0),
11145 UINT64_C(0),
11146 UINT64_C(0),
11147 UINT64_C(0),
11148 UINT64_C(0),
11149 UINT64_C(0),
11150 UINT64_C(0),
11151 UINT64_C(0),
11152 UINT64_C(0),
11153 UINT64_C(0),
11154 UINT64_C(0),
11155 UINT64_C(0),
11156 UINT64_C(0),
11157 UINT64_C(0),
11158 UINT64_C(0),
11159 UINT64_C(0),
11160 UINT64_C(0),
11161 UINT64_C(0),
11162 UINT64_C(0),
11163 UINT64_C(0),
11164 UINT64_C(0),
11165 UINT64_C(0),
11166 UINT64_C(0),
11167 UINT64_C(0),
11168 UINT64_C(0),
11169 UINT64_C(0),
11170 UINT64_C(0),
11171 UINT64_C(0),
11172 UINT64_C(0),
11173 UINT64_C(0),
11174 UINT64_C(0),
11175 UINT64_C(0),
11176 UINT64_C(0),
11177 UINT64_C(0),
11178 UINT64_C(0),
11179 UINT64_C(0),
11180 UINT64_C(0),
11181 UINT64_C(0),
11182 UINT64_C(0),
11183 UINT64_C(0),
11184 UINT64_C(0),
11185 UINT64_C(0),
11186 UINT64_C(0),
11187 UINT64_C(0),
11188 UINT64_C(0),
11189 UINT64_C(0),
11190 UINT64_C(0),
11191 UINT64_C(0),
11192 UINT64_C(0),
11193 UINT64_C(0),
11194 UINT64_C(0),
11195 UINT64_C(0),
11196 UINT64_C(0),
11197 UINT64_C(0),
11198 UINT64_C(0),
11199 UINT64_C(0),
11200 UINT64_C(0),
11201 UINT64_C(0),
11202 UINT64_C(0),
11203 UINT64_C(0),
11204 UINT64_C(0),
11205 UINT64_C(0),
11206 UINT64_C(0),
11207 UINT64_C(0),
11208 UINT64_C(0),
11209 UINT64_C(0),
11210 UINT64_C(0),
11211 UINT64_C(0),
11212 UINT64_C(0),
11213 UINT64_C(0),
11214 UINT64_C(0),
11215 UINT64_C(0),
11216 UINT64_C(0),
11217 UINT64_C(0),
11218 UINT64_C(0),
11219 UINT64_C(0),
11220 UINT64_C(0),
11221 UINT64_C(0),
11222 UINT64_C(0),
11223 UINT64_C(0),
11224 UINT64_C(0),
11225 UINT64_C(0),
11226 UINT64_C(0),
11227 UINT64_C(0),
11228 UINT64_C(0),
11229 UINT64_C(0),
11230 UINT64_C(0),
11231 UINT64_C(0),
11232 UINT64_C(0),
11233 UINT64_C(0),
11234 UINT64_C(0),
11235 UINT64_C(0),
11236 UINT64_C(0),
11237 UINT64_C(0),
11238 UINT64_C(0),
11239 UINT64_C(0),
11240 UINT64_C(0),
11241 UINT64_C(0),
11242 UINT64_C(0),
11243 UINT64_C(0),
11244 UINT64_C(0),
11245 UINT64_C(0),
11246 UINT64_C(0),
11247 UINT64_C(0),
11248 UINT64_C(0),
11249 UINT64_C(0),
11250 UINT64_C(0),
11251 UINT64_C(0),
11252 UINT64_C(0),
11253 UINT64_C(0),
11254 UINT64_C(0),
11255 UINT64_C(0),
11256 UINT64_C(0),
11257 UINT64_C(0),
11258 UINT64_C(0),
11259 UINT64_C(0),
11260 UINT64_C(0),
11261 UINT64_C(0),
11262 UINT64_C(0),
11263 UINT64_C(0),
11264 UINT64_C(0),
11265 UINT64_C(0),
11266 UINT64_C(0),
11267 UINT64_C(0),
11268 UINT64_C(0),
11269 UINT64_C(0),
11270 UINT64_C(0),
11271 UINT64_C(0),
11272 UINT64_C(0),
11273 UINT64_C(0),
11274 UINT64_C(0),
11275 UINT64_C(0),
11276 UINT64_C(0),
11277 UINT64_C(0),
11278 UINT64_C(0),
11279 UINT64_C(0),
11280 UINT64_C(0),
11281 UINT64_C(0),
11282 UINT64_C(0),
11283 UINT64_C(0),
11284 UINT64_C(0),
11285 UINT64_C(0),
11286 UINT64_C(0),
11287 UINT64_C(0),
11288 UINT64_C(0),
11289 UINT64_C(0),
11290 UINT64_C(0),
11291 UINT64_C(0),
11292 UINT64_C(0),
11293 UINT64_C(0),
11294 UINT64_C(0),
11295 UINT64_C(0),
11296 UINT64_C(0),
11297 UINT64_C(0),
11298 UINT64_C(0),
11299 UINT64_C(0),
11300 UINT64_C(0),
11301 UINT64_C(0),
11302 UINT64_C(0),
11303 UINT64_C(0),
11304 UINT64_C(0),
11305 UINT64_C(0),
11306 UINT64_C(0),
11307 UINT64_C(0),
11308 UINT64_C(0),
11309 UINT64_C(0),
11310 UINT64_C(0),
11311 UINT64_C(0),
11312 UINT64_C(0),
11313 UINT64_C(0),
11314 UINT64_C(0),
11315 UINT64_C(0),
11316 UINT64_C(0),
11317 UINT64_C(0),
11318 UINT64_C(0),
11319 UINT64_C(0),
11320 UINT64_C(0),
11321 UINT64_C(0),
11322 UINT64_C(0),
11323 UINT64_C(0),
11324 UINT64_C(0),
11325 UINT64_C(0),
11326 UINT64_C(0),
11327 UINT64_C(0),
11328 UINT64_C(0),
11329 UINT64_C(0),
11330 UINT64_C(0),
11331 UINT64_C(0),
11332 UINT64_C(0),
11333 UINT64_C(0),
11334 UINT64_C(0),
11335 UINT64_C(0),
11336 UINT64_C(0),
11337 UINT64_C(0),
11338 UINT64_C(0),
11339 UINT64_C(0),
11340 UINT64_C(0),
11341 UINT64_C(0),
11342 UINT64_C(0),
11343 UINT64_C(0),
11344 UINT64_C(0),
11345 UINT64_C(0),
11346 UINT64_C(0),
11347 UINT64_C(0),
11348 UINT64_C(0),
11349 UINT64_C(0),
11350 UINT64_C(0),
11351 UINT64_C(0),
11352 UINT64_C(0),
11353 UINT64_C(0),
11354 UINT64_C(0),
11355 UINT64_C(0),
11356 UINT64_C(0),
11357 UINT64_C(0),
11358 UINT64_C(0),
11359 UINT64_C(0),
11360 UINT64_C(0),
11361 UINT64_C(0),
11362 UINT64_C(0),
11363 UINT64_C(0),
11364 UINT64_C(0),
11365 UINT64_C(0),
11366 UINT64_C(0),
11367 UINT64_C(0),
11368 UINT64_C(0),
11369 UINT64_C(0),
11370 UINT64_C(0),
11371 UINT64_C(0),
11372 UINT64_C(0),
11373 UINT64_C(0),
11374 UINT64_C(0),
11375 UINT64_C(0),
11376 UINT64_C(0),
11377 UINT64_C(0),
11378 UINT64_C(0),
11379 UINT64_C(0),
11380 UINT64_C(0),
11381 UINT64_C(0),
11382 UINT64_C(0),
11383 UINT64_C(0),
11384 UINT64_C(0),
11385 UINT64_C(0),
11386 UINT64_C(0),
11387 UINT64_C(0),
11388 UINT64_C(0),
11389 UINT64_C(0),
11390 UINT64_C(0),
11391 UINT64_C(0),
11392 UINT64_C(0),
11393 UINT64_C(0),
11394 UINT64_C(0),
11395 UINT64_C(0),
11396 UINT64_C(0),
11397 UINT64_C(0),
11398 UINT64_C(0),
11399 UINT64_C(0),
11400 UINT64_C(0),
11401 UINT64_C(0),
11402 UINT64_C(0),
11403 UINT64_C(0),
11404 UINT64_C(0),
11405 UINT64_C(0),
11406 UINT64_C(0),
11407 UINT64_C(0),
11408 UINT64_C(0),
11409 UINT64_C(0),
11410 UINT64_C(0),
11411 UINT64_C(0),
11412 UINT64_C(0),
11413 UINT64_C(0),
11414 UINT64_C(0),
11415 UINT64_C(0),
11416 UINT64_C(0),
11417 UINT64_C(0),
11418 UINT64_C(0),
11419 UINT64_C(0),
11420 UINT64_C(0),
11421 UINT64_C(0),
11422 UINT64_C(0),
11423 UINT64_C(0),
11424 UINT64_C(0),
11425 UINT64_C(0),
11426 UINT64_C(0),
11427 UINT64_C(0),
11428 UINT64_C(0),
11429 UINT64_C(0),
11430 UINT64_C(0),
11431 UINT64_C(0),
11432 UINT64_C(0),
11433 UINT64_C(0),
11434 UINT64_C(0),
11435 UINT64_C(0),
11436 UINT64_C(0),
11437 UINT64_C(0),
11438 UINT64_C(0),
11439 UINT64_C(0),
11440 UINT64_C(0),
11441 UINT64_C(0),
11442 UINT64_C(0),
11443 UINT64_C(0),
11444 UINT64_C(0),
11445 UINT64_C(0),
11446 UINT64_C(0),
11447 UINT64_C(0),
11448 UINT64_C(0),
11449 UINT64_C(0),
11450 UINT64_C(0),
11451 UINT64_C(0),
11452 UINT64_C(0),
11453 UINT64_C(0),
11454 UINT64_C(0),
11455 UINT64_C(0),
11456 UINT64_C(0),
11457 UINT64_C(0),
11458 UINT64_C(0),
11459 UINT64_C(0),
11460 UINT64_C(0),
11461 UINT64_C(0),
11462 UINT64_C(0),
11463 UINT64_C(0),
11464 UINT64_C(0),
11465 UINT64_C(0),
11466 UINT64_C(0),
11467 UINT64_C(0),
11468 UINT64_C(0),
11469 UINT64_C(0),
11470 UINT64_C(0),
11471 UINT64_C(0),
11472 UINT64_C(0),
11473 UINT64_C(0),
11474 UINT64_C(0),
11475 UINT64_C(0),
11476 UINT64_C(0),
11477 UINT64_C(0),
11478 UINT64_C(0),
11479 UINT64_C(0),
11480 UINT64_C(0),
11481 UINT64_C(0),
11482 UINT64_C(0),
11483 UINT64_C(0),
11484 UINT64_C(0),
11485 UINT64_C(0),
11486 UINT64_C(0),
11487 UINT64_C(0),
11488 UINT64_C(0),
11489 UINT64_C(0),
11490 UINT64_C(0),
11491 UINT64_C(0),
11492 UINT64_C(0),
11493 UINT64_C(0),
11494 UINT64_C(0),
11495 UINT64_C(0),
11496 UINT64_C(0),
11497 UINT64_C(0),
11498 UINT64_C(0),
11499 UINT64_C(0),
11500 UINT64_C(0),
11501 UINT64_C(0),
11502 UINT64_C(0),
11503 UINT64_C(0),
11504 UINT64_C(0),
11505 UINT64_C(0),
11506 UINT64_C(0),
11507 UINT64_C(0),
11508 UINT64_C(0),
11509 UINT64_C(0),
11510 UINT64_C(0),
11511 UINT64_C(0),
11512 UINT64_C(0),
11513 UINT64_C(0),
11514 UINT64_C(0),
11515 UINT64_C(0),
11516 UINT64_C(0),
11517 UINT64_C(0),
11518 UINT64_C(0),
11519 UINT64_C(0),
11520 UINT64_C(0),
11521 UINT64_C(0),
11522 UINT64_C(0),
11523 UINT64_C(0),
11524 UINT64_C(0),
11525 UINT64_C(0),
11526 UINT64_C(0),
11527 UINT64_C(0),
11528 UINT64_C(0),
11529 UINT64_C(0),
11530 UINT64_C(0),
11531 UINT64_C(0),
11532 UINT64_C(0),
11533 UINT64_C(0),
11534 UINT64_C(0),
11535 UINT64_C(0),
11536 UINT64_C(0),
11537 UINT64_C(0),
11538 UINT64_C(0),
11539 UINT64_C(0),
11540 UINT64_C(0),
11541 UINT64_C(0),
11542 UINT64_C(0),
11543 UINT64_C(0),
11544 UINT64_C(0),
11545 UINT64_C(0),
11546 UINT64_C(0),
11547 UINT64_C(0),
11548 UINT64_C(0),
11549 UINT64_C(0),
11550 UINT64_C(0),
11551 UINT64_C(0),
11552 UINT64_C(0),
11553 UINT64_C(0),
11554 UINT64_C(0),
11555 UINT64_C(0),
11556 UINT64_C(0),
11557 UINT64_C(0),
11558 UINT64_C(0),
11559 UINT64_C(0),
11560 UINT64_C(0),
11561 UINT64_C(0),
11562 UINT64_C(0),
11563 UINT64_C(0),
11564 UINT64_C(0),
11565 UINT64_C(0),
11566 UINT64_C(0),
11567 UINT64_C(0),
11568 UINT64_C(0),
11569 UINT64_C(0),
11570 UINT64_C(0),
11571 UINT64_C(0),
11572 UINT64_C(0),
11573 UINT64_C(0),
11574 UINT64_C(0),
11575 UINT64_C(0),
11576 UINT64_C(0),
11577 UINT64_C(0),
11578 UINT64_C(0),
11579 UINT64_C(0),
11580 UINT64_C(0),
11581 UINT64_C(0),
11582 UINT64_C(0),
11583 UINT64_C(0),
11584 UINT64_C(0),
11585 UINT64_C(0),
11586 UINT64_C(0),
11587 UINT64_C(0),
11588 UINT64_C(0),
11589 UINT64_C(0),
11590 UINT64_C(0),
11591 UINT64_C(0),
11592 UINT64_C(0),
11593 UINT64_C(0),
11594 UINT64_C(0),
11595 UINT64_C(0),
11596 UINT64_C(0),
11597 UINT64_C(0),
11598 UINT64_C(0),
11599 UINT64_C(0),
11600 UINT64_C(0),
11601 UINT64_C(0),
11602 UINT64_C(0),
11603 UINT64_C(0),
11604 UINT64_C(0),
11605 UINT64_C(0),
11606 UINT64_C(0),
11607 UINT64_C(0),
11608 UINT64_C(0),
11609 UINT64_C(0),
11610 UINT64_C(0),
11611 UINT64_C(0),
11612 UINT64_C(0),
11613 UINT64_C(0),
11614 UINT64_C(0),
11615 UINT64_C(0),
11616 UINT64_C(0),
11617 UINT64_C(0),
11618 UINT64_C(0),
11619 UINT64_C(0),
11620 UINT64_C(0),
11621 UINT64_C(0),
11622 UINT64_C(0),
11623 UINT64_C(0),
11624 UINT64_C(0),
11625 UINT64_C(0),
11626 UINT64_C(0),
11627 UINT64_C(0),
11628 UINT64_C(0),
11629 UINT64_C(0),
11630 UINT64_C(0),
11631 UINT64_C(0),
11632 UINT64_C(0),
11633 UINT64_C(0),
11634 UINT64_C(0),
11635 UINT64_C(0),
11636 UINT64_C(0),
11637 UINT64_C(0),
11638 UINT64_C(0),
11639 UINT64_C(0),
11640 UINT64_C(0),
11641 UINT64_C(0),
11642 UINT64_C(0),
11643 UINT64_C(0),
11644 UINT64_C(0),
11645 UINT64_C(0),
11646 UINT64_C(0),
11647 UINT64_C(0),
11648 UINT64_C(0),
11649 UINT64_C(0),
11650 UINT64_C(0),
11651 UINT64_C(0),
11652 UINT64_C(0),
11653 UINT64_C(0),
11654 UINT64_C(0),
11655 UINT64_C(0),
11656 UINT64_C(0),
11657 UINT64_C(0),
11658 UINT64_C(0),
11659 UINT64_C(0),
11660 UINT64_C(0),
11661 UINT64_C(0),
11662 UINT64_C(0),
11663 UINT64_C(0),
11664 UINT64_C(0),
11665 UINT64_C(0),
11666 UINT64_C(0),
11667 UINT64_C(0),
11668 UINT64_C(0),
11669 UINT64_C(0),
11670 UINT64_C(0),
11671 UINT64_C(0),
11672 UINT64_C(0),
11673 UINT64_C(0),
11674 UINT64_C(0),
11675 UINT64_C(0),
11676 UINT64_C(0),
11677 UINT64_C(0),
11678 UINT64_C(0),
11679 UINT64_C(0),
11680 UINT64_C(0),
11681 UINT64_C(0),
11682 UINT64_C(0),
11683 UINT64_C(0),
11684 UINT64_C(0),
11685 UINT64_C(0),
11686 UINT64_C(0),
11687 UINT64_C(0),
11688 UINT64_C(0),
11689 UINT64_C(0),
11690 UINT64_C(0),
11691 UINT64_C(0),
11692 UINT64_C(0),
11693 UINT64_C(0),
11694 UINT64_C(0),
11695 UINT64_C(0),
11696 UINT64_C(0),
11697 UINT64_C(0),
11698 UINT64_C(0),
11699 UINT64_C(0),
11700 UINT64_C(0),
11701 UINT64_C(0),
11702 UINT64_C(0),
11703 UINT64_C(0),
11704 UINT64_C(0),
11705 UINT64_C(0),
11706 UINT64_C(0),
11707 UINT64_C(0),
11708 UINT64_C(0),
11709 UINT64_C(0),
11710 UINT64_C(0),
11711 UINT64_C(0),
11712 UINT64_C(0),
11713 UINT64_C(0),
11714 UINT64_C(0),
11715 UINT64_C(0),
11716 UINT64_C(0),
11717 UINT64_C(0),
11718 UINT64_C(0),
11719 UINT64_C(0),
11720 UINT64_C(0),
11721 UINT64_C(0),
11722 UINT64_C(0),
11723 UINT64_C(0),
11724 UINT64_C(0),
11725 UINT64_C(0),
11726 UINT64_C(0),
11727 UINT64_C(0),
11728 UINT64_C(0),
11729 UINT64_C(0),
11730 UINT64_C(0),
11731 UINT64_C(0),
11732 UINT64_C(0),
11733 UINT64_C(0),
11734 UINT64_C(0),
11735 UINT64_C(0),
11736 UINT64_C(0),
11737 UINT64_C(0),
11738 UINT64_C(0),
11739 UINT64_C(0),
11740 UINT64_C(0),
11741 UINT64_C(0),
11742 UINT64_C(0),
11743 UINT64_C(0),
11744 UINT64_C(0),
11745 UINT64_C(0),
11746 UINT64_C(0),
11747 UINT64_C(0),
11748 UINT64_C(0),
11749 UINT64_C(0),
11750 UINT64_C(0),
11751 UINT64_C(0),
11752 UINT64_C(0),
11753 UINT64_C(0),
11754 UINT64_C(0),
11755 UINT64_C(0),
11756 UINT64_C(0),
11757 UINT64_C(0),
11758 UINT64_C(0),
11759 UINT64_C(0),
11760 UINT64_C(0),
11761 UINT64_C(0),
11762 UINT64_C(0),
11763 UINT64_C(0),
11764 UINT64_C(0),
11765 UINT64_C(0),
11766 UINT64_C(0),
11767 UINT64_C(0),
11768 UINT64_C(0),
11769 UINT64_C(0),
11770 UINT64_C(0),
11771 UINT64_C(0),
11772 UINT64_C(0),
11773 UINT64_C(0),
11774 UINT64_C(0),
11775 UINT64_C(0),
11776 UINT64_C(0),
11777 UINT64_C(0),
11778 UINT64_C(0),
11779 UINT64_C(0),
11780 UINT64_C(0),
11781 UINT64_C(0),
11782 UINT64_C(0),
11783 UINT64_C(0),
11784 UINT64_C(0),
11785 UINT64_C(0),
11786 UINT64_C(0),
11787 UINT64_C(0),
11788 UINT64_C(0),
11789 UINT64_C(0),
11790 UINT64_C(0),
11791 UINT64_C(0),
11792 UINT64_C(0),
11793 UINT64_C(0),
11794 UINT64_C(0),
11795 UINT64_C(0),
11796 UINT64_C(0),
11797 UINT64_C(0),
11798 UINT64_C(0),
11799 UINT64_C(0),
11800 UINT64_C(0),
11801 UINT64_C(0),
11802 UINT64_C(0),
11803 UINT64_C(0),
11804 UINT64_C(0),
11805 UINT64_C(0),
11806 UINT64_C(0),
11807 UINT64_C(0),
11808 UINT64_C(0),
11809 UINT64_C(0),
11810 UINT64_C(0),
11811 UINT64_C(0),
11812 UINT64_C(0),
11813 UINT64_C(0),
11814 UINT64_C(0),
11815 UINT64_C(0),
11816 UINT64_C(0),
11817 UINT64_C(0),
11818 UINT64_C(0),
11819 UINT64_C(0),
11820 UINT64_C(0),
11821 UINT64_C(0),
11822 UINT64_C(0),
11823 UINT64_C(0),
11824 UINT64_C(0),
11825 UINT64_C(0),
11826 UINT64_C(0),
11827 UINT64_C(0),
11828 UINT64_C(0),
11829 UINT64_C(0),
11830 UINT64_C(0),
11831 UINT64_C(0),
11832 UINT64_C(0),
11833 UINT64_C(0),
11834 UINT64_C(0),
11835 UINT64_C(0),
11836 UINT64_C(0),
11837 UINT64_C(0),
11838 UINT64_C(0),
11839 UINT64_C(0),
11840 UINT64_C(0),
11841 UINT64_C(0),
11842 UINT64_C(0),
11843 UINT64_C(0),
11844 UINT64_C(0),
11845 UINT64_C(0),
11846 UINT64_C(0),
11847 UINT64_C(0),
11848 UINT64_C(0),
11849 UINT64_C(0),
11850 UINT64_C(0),
11851 UINT64_C(0),
11852 UINT64_C(0),
11853 UINT64_C(0),
11854 UINT64_C(0),
11855 UINT64_C(0),
11856 UINT64_C(0),
11857 UINT64_C(0),
11858 UINT64_C(0),
11859 UINT64_C(0),
11860 UINT64_C(0),
11861 UINT64_C(0),
11862 UINT64_C(0),
11863 UINT64_C(0),
11864 UINT64_C(0),
11865 UINT64_C(0),
11866 UINT64_C(0),
11867 UINT64_C(0),
11868 UINT64_C(0),
11869 UINT64_C(0),
11870 UINT64_C(0),
11871 UINT64_C(0),
11872 UINT64_C(0),
11873 UINT64_C(0),
11874 UINT64_C(0),
11875 UINT64_C(0),
11876 UINT64_C(0),
11877 UINT64_C(0),
11878 UINT64_C(0),
11879 UINT64_C(0),
11880 UINT64_C(0),
11881 UINT64_C(0),
11882 UINT64_C(0),
11883 UINT64_C(0),
11884 UINT64_C(0),
11885 UINT64_C(0),
11886 UINT64_C(0),
11887 UINT64_C(0),
11888 UINT64_C(0),
11889 UINT64_C(0),
11890 UINT64_C(0),
11891 UINT64_C(0),
11892 UINT64_C(0),
11893 UINT64_C(0),
11894 UINT64_C(0),
11895 UINT64_C(0),
11896 UINT64_C(0),
11897 UINT64_C(0),
11898 UINT64_C(0),
11899 UINT64_C(0),
11900 UINT64_C(0),
11901 UINT64_C(0),
11902 UINT64_C(0),
11903 UINT64_C(0),
11904 UINT64_C(0),
11905 UINT64_C(0),
11906 UINT64_C(0),
11907 UINT64_C(0),
11908 UINT64_C(0),
11909 UINT64_C(0),
11910 UINT64_C(0),
11911 UINT64_C(0),
11912 UINT64_C(0),
11913 UINT64_C(0),
11914 UINT64_C(0),
11915 UINT64_C(0),
11916 UINT64_C(0),
11917 UINT64_C(0),
11918 UINT64_C(0),
11919 UINT64_C(0),
11920 UINT64_C(51), // ADD
11921 UINT64_C(19), // ADDI
11922 UINT64_C(27), // ADDIW
11923 UINT64_C(59), // ADDW
11924 UINT64_C(134217787), // ADD_UW
11925 UINT64_C(704643123), // AES32DSI
11926 UINT64_C(771751987), // AES32DSMI
11927 UINT64_C(570425395), // AES32ESI
11928 UINT64_C(637534259), // AES32ESMI
11929 UINT64_C(973078579), // AES64DS
11930 UINT64_C(1040187443), // AES64DSM
11931 UINT64_C(838860851), // AES64ES
11932 UINT64_C(905969715), // AES64ESM
11933 UINT64_C(805310483), // AES64IM
11934 UINT64_C(822087699), // AES64KS1I
11935 UINT64_C(2113929267), // AES64KS2
11936 UINT64_C(47), // AMOADD_B
11937 UINT64_C(67108911), // AMOADD_B_AQ
11938 UINT64_C(100663343), // AMOADD_B_AQ_RL
11939 UINT64_C(33554479), // AMOADD_B_RL
11940 UINT64_C(12335), // AMOADD_D
11941 UINT64_C(67121199), // AMOADD_D_AQ
11942 UINT64_C(100675631), // AMOADD_D_AQ_RL
11943 UINT64_C(33566767), // AMOADD_D_RL
11944 UINT64_C(4143), // AMOADD_H
11945 UINT64_C(67113007), // AMOADD_H_AQ
11946 UINT64_C(100667439), // AMOADD_H_AQ_RL
11947 UINT64_C(33558575), // AMOADD_H_RL
11948 UINT64_C(8239), // AMOADD_W
11949 UINT64_C(67117103), // AMOADD_W_AQ
11950 UINT64_C(100671535), // AMOADD_W_AQ_RL
11951 UINT64_C(33562671), // AMOADD_W_RL
11952 UINT64_C(1610612783), // AMOAND_B
11953 UINT64_C(1677721647), // AMOAND_B_AQ
11954 UINT64_C(1711276079), // AMOAND_B_AQ_RL
11955 UINT64_C(1644167215), // AMOAND_B_RL
11956 UINT64_C(1610625071), // AMOAND_D
11957 UINT64_C(1677733935), // AMOAND_D_AQ
11958 UINT64_C(1711288367), // AMOAND_D_AQ_RL
11959 UINT64_C(1644179503), // AMOAND_D_RL
11960 UINT64_C(1610616879), // AMOAND_H
11961 UINT64_C(1677725743), // AMOAND_H_AQ
11962 UINT64_C(1711280175), // AMOAND_H_AQ_RL
11963 UINT64_C(1644171311), // AMOAND_H_RL
11964 UINT64_C(1610620975), // AMOAND_W
11965 UINT64_C(1677729839), // AMOAND_W_AQ
11966 UINT64_C(1711284271), // AMOAND_W_AQ_RL
11967 UINT64_C(1644175407), // AMOAND_W_RL
11968 UINT64_C(671088687), // AMOCAS_B
11969 UINT64_C(738197551), // AMOCAS_B_AQ
11970 UINT64_C(771751983), // AMOCAS_B_AQ_RL
11971 UINT64_C(704643119), // AMOCAS_B_RL
11972 UINT64_C(671100975), // AMOCAS_D_RV32
11973 UINT64_C(738209839), // AMOCAS_D_RV32_AQ
11974 UINT64_C(771764271), // AMOCAS_D_RV32_AQ_RL
11975 UINT64_C(704655407), // AMOCAS_D_RV32_RL
11976 UINT64_C(671100975), // AMOCAS_D_RV64
11977 UINT64_C(738209839), // AMOCAS_D_RV64_AQ
11978 UINT64_C(771764271), // AMOCAS_D_RV64_AQ_RL
11979 UINT64_C(704655407), // AMOCAS_D_RV64_RL
11980 UINT64_C(671092783), // AMOCAS_H
11981 UINT64_C(738201647), // AMOCAS_H_AQ
11982 UINT64_C(771756079), // AMOCAS_H_AQ_RL
11983 UINT64_C(704647215), // AMOCAS_H_RL
11984 UINT64_C(671105071), // AMOCAS_Q
11985 UINT64_C(738213935), // AMOCAS_Q_AQ
11986 UINT64_C(771768367), // AMOCAS_Q_AQ_RL
11987 UINT64_C(704659503), // AMOCAS_Q_RL
11988 UINT64_C(671096879), // AMOCAS_W
11989 UINT64_C(738205743), // AMOCAS_W_AQ
11990 UINT64_C(771760175), // AMOCAS_W_AQ_RL
11991 UINT64_C(704651311), // AMOCAS_W_RL
11992 UINT64_C(3758096431), // AMOMAXU_B
11993 UINT64_C(3825205295), // AMOMAXU_B_AQ
11994 UINT64_C(3858759727), // AMOMAXU_B_AQ_RL
11995 UINT64_C(3791650863), // AMOMAXU_B_RL
11996 UINT64_C(3758108719), // AMOMAXU_D
11997 UINT64_C(3825217583), // AMOMAXU_D_AQ
11998 UINT64_C(3858772015), // AMOMAXU_D_AQ_RL
11999 UINT64_C(3791663151), // AMOMAXU_D_RL
12000 UINT64_C(3758100527), // AMOMAXU_H
12001 UINT64_C(3825209391), // AMOMAXU_H_AQ
12002 UINT64_C(3858763823), // AMOMAXU_H_AQ_RL
12003 UINT64_C(3791654959), // AMOMAXU_H_RL
12004 UINT64_C(3758104623), // AMOMAXU_W
12005 UINT64_C(3825213487), // AMOMAXU_W_AQ
12006 UINT64_C(3858767919), // AMOMAXU_W_AQ_RL
12007 UINT64_C(3791659055), // AMOMAXU_W_RL
12008 UINT64_C(2684354607), // AMOMAX_B
12009 UINT64_C(2751463471), // AMOMAX_B_AQ
12010 UINT64_C(2785017903), // AMOMAX_B_AQ_RL
12011 UINT64_C(2717909039), // AMOMAX_B_RL
12012 UINT64_C(2684366895), // AMOMAX_D
12013 UINT64_C(2751475759), // AMOMAX_D_AQ
12014 UINT64_C(2785030191), // AMOMAX_D_AQ_RL
12015 UINT64_C(2717921327), // AMOMAX_D_RL
12016 UINT64_C(2684358703), // AMOMAX_H
12017 UINT64_C(2751467567), // AMOMAX_H_AQ
12018 UINT64_C(2785021999), // AMOMAX_H_AQ_RL
12019 UINT64_C(2717913135), // AMOMAX_H_RL
12020 UINT64_C(2684362799), // AMOMAX_W
12021 UINT64_C(2751471663), // AMOMAX_W_AQ
12022 UINT64_C(2785026095), // AMOMAX_W_AQ_RL
12023 UINT64_C(2717917231), // AMOMAX_W_RL
12024 UINT64_C(3221225519), // AMOMINU_B
12025 UINT64_C(3288334383), // AMOMINU_B_AQ
12026 UINT64_C(3321888815), // AMOMINU_B_AQ_RL
12027 UINT64_C(3254779951), // AMOMINU_B_RL
12028 UINT64_C(3221237807), // AMOMINU_D
12029 UINT64_C(3288346671), // AMOMINU_D_AQ
12030 UINT64_C(3321901103), // AMOMINU_D_AQ_RL
12031 UINT64_C(3254792239), // AMOMINU_D_RL
12032 UINT64_C(3221229615), // AMOMINU_H
12033 UINT64_C(3288338479), // AMOMINU_H_AQ
12034 UINT64_C(3321892911), // AMOMINU_H_AQ_RL
12035 UINT64_C(3254784047), // AMOMINU_H_RL
12036 UINT64_C(3221233711), // AMOMINU_W
12037 UINT64_C(3288342575), // AMOMINU_W_AQ
12038 UINT64_C(3321897007), // AMOMINU_W_AQ_RL
12039 UINT64_C(3254788143), // AMOMINU_W_RL
12040 UINT64_C(2147483695), // AMOMIN_B
12041 UINT64_C(2214592559), // AMOMIN_B_AQ
12042 UINT64_C(2248146991), // AMOMIN_B_AQ_RL
12043 UINT64_C(2181038127), // AMOMIN_B_RL
12044 UINT64_C(2147495983), // AMOMIN_D
12045 UINT64_C(2214604847), // AMOMIN_D_AQ
12046 UINT64_C(2248159279), // AMOMIN_D_AQ_RL
12047 UINT64_C(2181050415), // AMOMIN_D_RL
12048 UINT64_C(2147487791), // AMOMIN_H
12049 UINT64_C(2214596655), // AMOMIN_H_AQ
12050 UINT64_C(2248151087), // AMOMIN_H_AQ_RL
12051 UINT64_C(2181042223), // AMOMIN_H_RL
12052 UINT64_C(2147491887), // AMOMIN_W
12053 UINT64_C(2214600751), // AMOMIN_W_AQ
12054 UINT64_C(2248155183), // AMOMIN_W_AQ_RL
12055 UINT64_C(2181046319), // AMOMIN_W_RL
12056 UINT64_C(1073741871), // AMOOR_B
12057 UINT64_C(1140850735), // AMOOR_B_AQ
12058 UINT64_C(1174405167), // AMOOR_B_AQ_RL
12059 UINT64_C(1107296303), // AMOOR_B_RL
12060 UINT64_C(1073754159), // AMOOR_D
12061 UINT64_C(1140863023), // AMOOR_D_AQ
12062 UINT64_C(1174417455), // AMOOR_D_AQ_RL
12063 UINT64_C(1107308591), // AMOOR_D_RL
12064 UINT64_C(1073745967), // AMOOR_H
12065 UINT64_C(1140854831), // AMOOR_H_AQ
12066 UINT64_C(1174409263), // AMOOR_H_AQ_RL
12067 UINT64_C(1107300399), // AMOOR_H_RL
12068 UINT64_C(1073750063), // AMOOR_W
12069 UINT64_C(1140858927), // AMOOR_W_AQ
12070 UINT64_C(1174413359), // AMOOR_W_AQ_RL
12071 UINT64_C(1107304495), // AMOOR_W_RL
12072 UINT64_C(134217775), // AMOSWAP_B
12073 UINT64_C(201326639), // AMOSWAP_B_AQ
12074 UINT64_C(234881071), // AMOSWAP_B_AQ_RL
12075 UINT64_C(167772207), // AMOSWAP_B_RL
12076 UINT64_C(134230063), // AMOSWAP_D
12077 UINT64_C(201338927), // AMOSWAP_D_AQ
12078 UINT64_C(234893359), // AMOSWAP_D_AQ_RL
12079 UINT64_C(167784495), // AMOSWAP_D_RL
12080 UINT64_C(134221871), // AMOSWAP_H
12081 UINT64_C(201330735), // AMOSWAP_H_AQ
12082 UINT64_C(234885167), // AMOSWAP_H_AQ_RL
12083 UINT64_C(167776303), // AMOSWAP_H_RL
12084 UINT64_C(134225967), // AMOSWAP_W
12085 UINT64_C(201334831), // AMOSWAP_W_AQ
12086 UINT64_C(234889263), // AMOSWAP_W_AQ_RL
12087 UINT64_C(167780399), // AMOSWAP_W_RL
12088 UINT64_C(536870959), // AMOXOR_B
12089 UINT64_C(603979823), // AMOXOR_B_AQ
12090 UINT64_C(637534255), // AMOXOR_B_AQ_RL
12091 UINT64_C(570425391), // AMOXOR_B_RL
12092 UINT64_C(536883247), // AMOXOR_D
12093 UINT64_C(603992111), // AMOXOR_D_AQ
12094 UINT64_C(637546543), // AMOXOR_D_AQ_RL
12095 UINT64_C(570437679), // AMOXOR_D_RL
12096 UINT64_C(536875055), // AMOXOR_H
12097 UINT64_C(603983919), // AMOXOR_H_AQ
12098 UINT64_C(637538351), // AMOXOR_H_AQ_RL
12099 UINT64_C(570429487), // AMOXOR_H_RL
12100 UINT64_C(536879151), // AMOXOR_W
12101 UINT64_C(603988015), // AMOXOR_W_AQ
12102 UINT64_C(637542447), // AMOXOR_W_AQ_RL
12103 UINT64_C(570433583), // AMOXOR_W_RL
12104 UINT64_C(28723), // AND
12105 UINT64_C(28691), // ANDI
12106 UINT64_C(1073770547), // ANDN
12107 UINT64_C(23), // AUIPC
12108 UINT64_C(1207963699), // BCLR
12109 UINT64_C(1207963667), // BCLRI
12110 UINT64_C(99), // BEQ
12111 UINT64_C(1207980083), // BEXT
12112 UINT64_C(1207980051), // BEXTI
12113 UINT64_C(20579), // BGE
12114 UINT64_C(28771), // BGEU
12115 UINT64_C(1744834611), // BINV
12116 UINT64_C(1744834579), // BINVI
12117 UINT64_C(16483), // BLT
12118 UINT64_C(24675), // BLTU
12119 UINT64_C(4195), // BNE
12120 UINT64_C(1752190995), // BREV8
12121 UINT64_C(671092787), // BSET
12122 UINT64_C(671092755), // BSETI
12123 UINT64_C(1056783), // CBO_CLEAN
12124 UINT64_C(2105359), // CBO_FLUSH
12125 UINT64_C(8207), // CBO_INVAL
12126 UINT64_C(4202511), // CBO_ZERO
12127 UINT64_C(167776307), // CLMUL
12128 UINT64_C(167784499), // CLMULH
12129 UINT64_C(167780403), // CLMULR
12130 UINT64_C(1610616851), // CLZ
12131 UINT64_C(1610616859), // CLZW
12132 UINT64_C(40962), // CM_JALT
12133 UINT64_C(40962), // CM_JT
12134 UINT64_C(44130), // CM_MVA01S
12135 UINT64_C(44066), // CM_MVSA01
12136 UINT64_C(47618), // CM_POP
12137 UINT64_C(48642), // CM_POPRET
12138 UINT64_C(48130), // CM_POPRETZ
12139 UINT64_C(47106), // CM_PUSH
12140 UINT64_C(1612714003), // CPOP
12141 UINT64_C(1612714011), // CPOPW
12142 UINT64_C(12403), // CSRRC
12143 UINT64_C(28787), // CSRRCI
12144 UINT64_C(8307), // CSRRS
12145 UINT64_C(24691), // CSRRSI
12146 UINT64_C(4211), // CSRRW
12147 UINT64_C(20595), // CSRRWI
12148 UINT64_C(1611665427), // CTZ
12149 UINT64_C(1611665435), // CTZW
12150 UINT64_C(1342189611), // CV_ABS
12151 UINT64_C(1879052411), // CV_ABS_B
12152 UINT64_C(1879048315), // CV_ABS_H
12153 UINT64_C(8283), // CV_ADDN
12154 UINT64_C(2147495979), // CV_ADDNR
12155 UINT64_C(2147491931), // CV_ADDRN
12156 UINT64_C(2214604843), // CV_ADDRNR
12157 UINT64_C(1073750107), // CV_ADDUN
12158 UINT64_C(2181050411), // CV_ADDUNR
12159 UINT64_C(3221233755), // CV_ADDURN
12160 UINT64_C(2248159275), // CV_ADDURNR
12161 UINT64_C(4219), // CV_ADD_B
12162 UINT64_C(1811947643), // CV_ADD_DIV2
12163 UINT64_C(1811955835), // CV_ADD_DIV4
12164 UINT64_C(1811964027), // CV_ADD_DIV8
12165 UINT64_C(123), // CV_ADD_H
12166 UINT64_C(28795), // CV_ADD_SCI_B
12167 UINT64_C(24699), // CV_ADD_SCI_H
12168 UINT64_C(20603), // CV_ADD_SC_B
12169 UINT64_C(16507), // CV_ADD_SC_H
12170 UINT64_C(1744834683), // CV_AND_B
12171 UINT64_C(1744830587), // CV_AND_H
12172 UINT64_C(1744859259), // CV_AND_SCI_B
12173 UINT64_C(1744855163), // CV_AND_SCI_H
12174 UINT64_C(1744851067), // CV_AND_SC_B
12175 UINT64_C(1744846971), // CV_AND_SC_H
12176 UINT64_C(402657403), // CV_AVGU_B
12177 UINT64_C(402653307), // CV_AVGU_H
12178 UINT64_C(402681979), // CV_AVGU_SCI_B
12179 UINT64_C(402677883), // CV_AVGU_SCI_H
12180 UINT64_C(402673787), // CV_AVGU_SC_B
12181 UINT64_C(402669691), // CV_AVGU_SC_H
12182 UINT64_C(268439675), // CV_AVG_B
12183 UINT64_C(268435579), // CV_AVG_H
12184 UINT64_C(268464251), // CV_AVG_SCI_B
12185 UINT64_C(268460155), // CV_AVG_SCI_H
12186 UINT64_C(268456059), // CV_AVG_SC_B
12187 UINT64_C(268451963), // CV_AVG_SC_H
12188 UINT64_C(4187), // CV_BCLR
12189 UINT64_C(939536427), // CV_BCLRR
12190 UINT64_C(24587), // CV_BEQIMM
12191 UINT64_C(3221229659), // CV_BITREV
12192 UINT64_C(28683), // CV_BNEIMM
12193 UINT64_C(1073746011), // CV_BSET
12194 UINT64_C(973090859), // CV_BSETR
12195 UINT64_C(1174417451), // CV_CLB
12196 UINT64_C(1879060523), // CV_CLIP
12197 UINT64_C(1946169387), // CV_CLIPR
12198 UINT64_C(1912614955), // CV_CLIPU
12199 UINT64_C(1979723819), // CV_CLIPUR
12200 UINT64_C(67113083), // CV_CMPEQ_B
12201 UINT64_C(67108987), // CV_CMPEQ_H
12202 UINT64_C(67137659), // CV_CMPEQ_SCI_B
12203 UINT64_C(67133563), // CV_CMPEQ_SCI_H
12204 UINT64_C(67129467), // CV_CMPEQ_SC_B
12205 UINT64_C(67125371), // CV_CMPEQ_SC_H
12206 UINT64_C(1006637179), // CV_CMPGEU_B
12207 UINT64_C(1006633083), // CV_CMPGEU_H
12208 UINT64_C(1006661755), // CV_CMPGEU_SCI_B
12209 UINT64_C(1006657659), // CV_CMPGEU_SCI_H
12210 UINT64_C(1006653563), // CV_CMPGEU_SC_B
12211 UINT64_C(1006649467), // CV_CMPGEU_SC_H
12212 UINT64_C(469766267), // CV_CMPGE_B
12213 UINT64_C(469762171), // CV_CMPGE_H
12214 UINT64_C(469790843), // CV_CMPGE_SCI_B
12215 UINT64_C(469786747), // CV_CMPGE_SCI_H
12216 UINT64_C(469782651), // CV_CMPGE_SC_B
12217 UINT64_C(469778555), // CV_CMPGE_SC_H
12218 UINT64_C(872419451), // CV_CMPGTU_B
12219 UINT64_C(872415355), // CV_CMPGTU_H
12220 UINT64_C(872444027), // CV_CMPGTU_SCI_B
12221 UINT64_C(872439931), // CV_CMPGTU_SCI_H
12222 UINT64_C(872435835), // CV_CMPGTU_SC_B
12223 UINT64_C(872431739), // CV_CMPGTU_SC_H
12224 UINT64_C(335548539), // CV_CMPGT_B
12225 UINT64_C(335544443), // CV_CMPGT_H
12226 UINT64_C(335573115), // CV_CMPGT_SCI_B
12227 UINT64_C(335569019), // CV_CMPGT_SCI_H
12228 UINT64_C(335564923), // CV_CMPGT_SC_B
12229 UINT64_C(335560827), // CV_CMPGT_SC_H
12230 UINT64_C(1275072635), // CV_CMPLEU_B
12231 UINT64_C(1275068539), // CV_CMPLEU_H
12232 UINT64_C(1275097211), // CV_CMPLEU_SCI_B
12233 UINT64_C(1275093115), // CV_CMPLEU_SCI_H
12234 UINT64_C(1275089019), // CV_CMPLEU_SC_B
12235 UINT64_C(1275084923), // CV_CMPLEU_SC_H
12236 UINT64_C(738201723), // CV_CMPLE_B
12237 UINT64_C(738197627), // CV_CMPLE_H
12238 UINT64_C(738226299), // CV_CMPLE_SCI_B
12239 UINT64_C(738222203), // CV_CMPLE_SCI_H
12240 UINT64_C(738218107), // CV_CMPLE_SC_B
12241 UINT64_C(738214011), // CV_CMPLE_SC_H
12242 UINT64_C(1140854907), // CV_CMPLTU_B
12243 UINT64_C(1140850811), // CV_CMPLTU_H
12244 UINT64_C(1140879483), // CV_CMPLTU_SCI_B
12245 UINT64_C(1140875387), // CV_CMPLTU_SCI_H
12246 UINT64_C(1140871291), // CV_CMPLTU_SC_B
12247 UINT64_C(1140867195), // CV_CMPLTU_SC_H
12248 UINT64_C(603983995), // CV_CMPLT_B
12249 UINT64_C(603979899), // CV_CMPLT_H
12250 UINT64_C(604008571), // CV_CMPLT_SCI_B
12251 UINT64_C(604004475), // CV_CMPLT_SCI_H
12252 UINT64_C(604000379), // CV_CMPLT_SC_B
12253 UINT64_C(603996283), // CV_CMPLT_SC_H
12254 UINT64_C(201330811), // CV_CMPNE_B
12255 UINT64_C(201326715), // CV_CMPNE_H
12256 UINT64_C(201355387), // CV_CMPNE_SCI_B
12257 UINT64_C(201351291), // CV_CMPNE_SCI_H
12258 UINT64_C(201347195), // CV_CMPNE_SC_B
12259 UINT64_C(201343099), // CV_CMPNE_SC_H
12260 UINT64_C(1207971883), // CV_CNT
12261 UINT64_C(1543503995), // CV_CPLXCONJ
12262 UINT64_C(1442840699), // CV_CPLXMUL_I
12263 UINT64_C(1442848891), // CV_CPLXMUL_I_DIV2
12264 UINT64_C(1442857083), // CV_CPLXMUL_I_DIV4
12265 UINT64_C(1442865275), // CV_CPLXMUL_I_DIV8
12266 UINT64_C(1409286267), // CV_CPLXMUL_R
12267 UINT64_C(1409294459), // CV_CPLXMUL_R_DIV2
12268 UINT64_C(1409302651), // CV_CPLXMUL_R_DIV4
12269 UINT64_C(1409310843), // CV_CPLXMUL_R_DIV8
12270 UINT64_C(2415923323), // CV_DOTSP_B
12271 UINT64_C(2415919227), // CV_DOTSP_H
12272 UINT64_C(2415947899), // CV_DOTSP_SCI_B
12273 UINT64_C(2415943803), // CV_DOTSP_SCI_H
12274 UINT64_C(2415939707), // CV_DOTSP_SC_B
12275 UINT64_C(2415935611), // CV_DOTSP_SC_H
12276 UINT64_C(2147487867), // CV_DOTUP_B
12277 UINT64_C(2147483771), // CV_DOTUP_H
12278 UINT64_C(2147512443), // CV_DOTUP_SCI_B
12279 UINT64_C(2147508347), // CV_DOTUP_SCI_H
12280 UINT64_C(2147504251), // CV_DOTUP_SC_B
12281 UINT64_C(2147500155), // CV_DOTUP_SC_H
12282 UINT64_C(2281705595), // CV_DOTUSP_B
12283 UINT64_C(2281701499), // CV_DOTUSP_H
12284 UINT64_C(2281730171), // CV_DOTUSP_SCI_B
12285 UINT64_C(2281726075), // CV_DOTUSP_SCI_H
12286 UINT64_C(2281721979), // CV_DOTUSP_SC_B
12287 UINT64_C(2281717883), // CV_DOTUSP_SC_H
12288 UINT64_C(12299), // CV_ELW
12289 UINT64_C(1677733931), // CV_EXTBS
12290 UINT64_C(1711288363), // CV_EXTBZ
12291 UINT64_C(1610625067), // CV_EXTHS
12292 UINT64_C(1644179499), // CV_EXTHZ
12293 UINT64_C(91), // CV_EXTRACT
12294 UINT64_C(805318699), // CV_EXTRACTR
12295 UINT64_C(1073741915), // CV_EXTRACTU
12296 UINT64_C(838873131), // CV_EXTRACTUR
12297 UINT64_C(3087020155), // CV_EXTRACTU_B
12298 UINT64_C(3087016059), // CV_EXTRACTU_H
12299 UINT64_C(3087011963), // CV_EXTRACT_B
12300 UINT64_C(3087007867), // CV_EXTRACT_H
12301 UINT64_C(1107308587), // CV_FF1
12302 UINT64_C(1140863019), // CV_FL1
12303 UINT64_C(2147483739), // CV_INSERT
12304 UINT64_C(872427563), // CV_INSERTR
12305 UINT64_C(3087028347), // CV_INSERT_B
12306 UINT64_C(3087024251), // CV_INSERT_H
12307 UINT64_C(16395), // CV_LBU_ri_inc
12308 UINT64_C(402665515), // CV_LBU_rr
12309 UINT64_C(268447787), // CV_LBU_rr_inc
12310 UINT64_C(11), // CV_LB_ri_inc
12311 UINT64_C(134230059), // CV_LB_rr
12312 UINT64_C(12331), // CV_LB_rr_inc
12313 UINT64_C(20491), // CV_LHU_ri_inc
12314 UINT64_C(436219947), // CV_LHU_rr
12315 UINT64_C(302002219), // CV_LHU_rr_inc
12316 UINT64_C(4107), // CV_LH_ri_inc
12317 UINT64_C(167784491), // CV_LH_rr
12318 UINT64_C(33566763), // CV_LH_rr_inc
12319 UINT64_C(8203), // CV_LW_ri_inc
12320 UINT64_C(201338923), // CV_LW_rr
12321 UINT64_C(67121195), // CV_LW_rr_inc
12322 UINT64_C(2415931435), // CV_MAC
12323 UINT64_C(1073766491), // CV_MACHHSN
12324 UINT64_C(3221250139), // CV_MACHHSRN
12325 UINT64_C(1073770587), // CV_MACHHUN
12326 UINT64_C(3221254235), // CV_MACHHURN
12327 UINT64_C(24667), // CV_MACSN
12328 UINT64_C(2147508315), // CV_MACSRN
12329 UINT64_C(28763), // CV_MACUN
12330 UINT64_C(2147512411), // CV_MACURN
12331 UINT64_C(1509961771), // CV_MAX
12332 UINT64_C(1543516203), // CV_MAXU
12333 UINT64_C(939528315), // CV_MAXU_B
12334 UINT64_C(939524219), // CV_MAXU_H
12335 UINT64_C(939552891), // CV_MAXU_SCI_B
12336 UINT64_C(939548795), // CV_MAXU_SCI_H
12337 UINT64_C(939544699), // CV_MAXU_SC_B
12338 UINT64_C(939540603), // CV_MAXU_SC_H
12339 UINT64_C(805310587), // CV_MAX_B
12340 UINT64_C(805306491), // CV_MAX_H
12341 UINT64_C(805335163), // CV_MAX_SCI_B
12342 UINT64_C(805331067), // CV_MAX_SCI_H
12343 UINT64_C(805326971), // CV_MAX_SC_B
12344 UINT64_C(805322875), // CV_MAX_SC_H
12345 UINT64_C(1442852907), // CV_MIN
12346 UINT64_C(1476407339), // CV_MINU
12347 UINT64_C(671092859), // CV_MINU_B
12348 UINT64_C(671088763), // CV_MINU_H
12349 UINT64_C(671117435), // CV_MINU_SCI_B
12350 UINT64_C(671113339), // CV_MINU_SCI_H
12351 UINT64_C(671109243), // CV_MINU_SC_B
12352 UINT64_C(671105147), // CV_MINU_SC_H
12353 UINT64_C(536875131), // CV_MIN_B
12354 UINT64_C(536871035), // CV_MIN_H
12355 UINT64_C(536899707), // CV_MIN_SCI_B
12356 UINT64_C(536895611), // CV_MIN_SCI_H
12357 UINT64_C(536891515), // CV_MIN_SC_B
12358 UINT64_C(536887419), // CV_MIN_SC_H
12359 UINT64_C(2449485867), // CV_MSU
12360 UINT64_C(1073758299), // CV_MULHHSN
12361 UINT64_C(3221241947), // CV_MULHHSRN
12362 UINT64_C(1073762395), // CV_MULHHUN
12363 UINT64_C(3221246043), // CV_MULHHURN
12364 UINT64_C(16475), // CV_MULSN
12365 UINT64_C(2147500123), // CV_MULSRN
12366 UINT64_C(20571), // CV_MULUN
12367 UINT64_C(2147504219), // CV_MULURN
12368 UINT64_C(1476399227), // CV_OR_B
12369 UINT64_C(1476395131), // CV_OR_H
12370 UINT64_C(1476423803), // CV_OR_SCI_B
12371 UINT64_C(1476419707), // CV_OR_SCI_H
12372 UINT64_C(1476415611), // CV_OR_SC_B
12373 UINT64_C(1476411515), // CV_OR_SC_H
12374 UINT64_C(4026531963), // CV_PACK
12375 UINT64_C(4194308219), // CV_PACKHI_B
12376 UINT64_C(4160753787), // CV_PACKLO_B
12377 UINT64_C(4060086395), // CV_PACK_H
12378 UINT64_C(1073754155), // CV_ROR
12379 UINT64_C(43), // CV_SB_ri_inc
12380 UINT64_C(671100971), // CV_SB_rr
12381 UINT64_C(536883243), // CV_SB_rr_inc
12382 UINT64_C(2818576507), // CV_SDOTSP_B
12383 UINT64_C(2818572411), // CV_SDOTSP_H
12384 UINT64_C(2818601083), // CV_SDOTSP_SCI_B
12385 UINT64_C(2818596987), // CV_SDOTSP_SCI_H
12386 UINT64_C(2818592891), // CV_SDOTSP_SC_B
12387 UINT64_C(2818588795), // CV_SDOTSP_SC_H
12388 UINT64_C(2550141051), // CV_SDOTUP_B
12389 UINT64_C(2550136955), // CV_SDOTUP_H
12390 UINT64_C(2550165627), // CV_SDOTUP_SCI_B
12391 UINT64_C(2550161531), // CV_SDOTUP_SCI_H
12392 UINT64_C(2550157435), // CV_SDOTUP_SC_B
12393 UINT64_C(2550153339), // CV_SDOTUP_SC_H
12394 UINT64_C(2684358779), // CV_SDOTUSP_B
12395 UINT64_C(2684354683), // CV_SDOTUSP_H
12396 UINT64_C(2684383355), // CV_SDOTUSP_SCI_B
12397 UINT64_C(2684379259), // CV_SDOTUSP_SCI_H
12398 UINT64_C(2684375163), // CV_SDOTUSP_SC_B
12399 UINT64_C(2684371067), // CV_SDOTUSP_SC_H
12400 UINT64_C(3758100603), // CV_SHUFFLE2_B
12401 UINT64_C(3758096507), // CV_SHUFFLE2_H
12402 UINT64_C(3221254267), // CV_SHUFFLEI0_SCI_B
12403 UINT64_C(3355471995), // CV_SHUFFLEI1_SCI_B
12404 UINT64_C(3489689723), // CV_SHUFFLEI2_SCI_B
12405 UINT64_C(3623907451), // CV_SHUFFLEI3_SCI_B
12406 UINT64_C(3221229691), // CV_SHUFFLE_B
12407 UINT64_C(3221225595), // CV_SHUFFLE_H
12408 UINT64_C(3221250171), // CV_SHUFFLE_SCI_H
12409 UINT64_C(4139), // CV_SH_ri_inc
12410 UINT64_C(704655403), // CV_SH_rr
12411 UINT64_C(570437675), // CV_SH_rr_inc
12412 UINT64_C(1375744043), // CV_SLET
12413 UINT64_C(1409298475), // CV_SLETU
12414 UINT64_C(1342181499), // CV_SLL_B
12415 UINT64_C(1342177403), // CV_SLL_H
12416 UINT64_C(1342206075), // CV_SLL_SCI_B
12417 UINT64_C(1342201979), // CV_SLL_SCI_H
12418 UINT64_C(1342197883), // CV_SLL_SC_B
12419 UINT64_C(1342193787), // CV_SLL_SC_H
12420 UINT64_C(1207963771), // CV_SRA_B
12421 UINT64_C(1207959675), // CV_SRA_H
12422 UINT64_C(1207988347), // CV_SRA_SCI_B
12423 UINT64_C(1207984251), // CV_SRA_SCI_H
12424 UINT64_C(1207980155), // CV_SRA_SC_B
12425 UINT64_C(1207976059), // CV_SRA_SC_H
12426 UINT64_C(1073746043), // CV_SRL_B
12427 UINT64_C(1073741947), // CV_SRL_H
12428 UINT64_C(1073770619), // CV_SRL_SCI_B
12429 UINT64_C(1073766523), // CV_SRL_SCI_H
12430 UINT64_C(1073762427), // CV_SRL_SC_B
12431 UINT64_C(1073758331), // CV_SRL_SC_H
12432 UINT64_C(12379), // CV_SUBN
12433 UINT64_C(2281713707), // CV_SUBNR
12434 UINT64_C(2147496027), // CV_SUBRN
12435 UINT64_C(2348822571), // CV_SUBRNR
12436 UINT64_C(1677721723), // CV_SUBROTMJ
12437 UINT64_C(1677729915), // CV_SUBROTMJ_DIV2
12438 UINT64_C(1677738107), // CV_SUBROTMJ_DIV4
12439 UINT64_C(1677746299), // CV_SUBROTMJ_DIV8
12440 UINT64_C(1073754203), // CV_SUBUN
12441 UINT64_C(2315268139), // CV_SUBUNR
12442 UINT64_C(3221237851), // CV_SUBURN
12443 UINT64_C(2382377003), // CV_SUBURNR
12444 UINT64_C(134221947), // CV_SUB_B
12445 UINT64_C(1946165371), // CV_SUB_DIV2
12446 UINT64_C(1946173563), // CV_SUB_DIV4
12447 UINT64_C(1946181755), // CV_SUB_DIV8
12448 UINT64_C(134217851), // CV_SUB_H
12449 UINT64_C(134246523), // CV_SUB_SCI_B
12450 UINT64_C(134242427), // CV_SUB_SCI_H
12451 UINT64_C(134238331), // CV_SUB_SC_B
12452 UINT64_C(134234235), // CV_SUB_SC_H
12453 UINT64_C(8235), // CV_SW_ri_inc
12454 UINT64_C(738209835), // CV_SW_rr
12455 UINT64_C(603992107), // CV_SW_rr_inc
12456 UINT64_C(1610616955), // CV_XOR_B
12457 UINT64_C(1610612859), // CV_XOR_H
12458 UINT64_C(1610641531), // CV_XOR_SCI_B
12459 UINT64_C(1610637435), // CV_XOR_SCI_H
12460 UINT64_C(1610633339), // CV_XOR_SC_B
12461 UINT64_C(1610629243), // CV_XOR_SC_H
12462 UINT64_C(234901555), // CZERO_EQZ
12463 UINT64_C(234909747), // CZERO_NEZ
12464 UINT64_C(36866), // C_ADD
12465 UINT64_C(1), // C_ADDI
12466 UINT64_C(24833), // C_ADDI16SP
12467 UINT64_C(0), // C_ADDI4SPN
12468 UINT64_C(8193), // C_ADDIW
12469 UINT64_C(1), // C_ADDI_HINT_IMM_ZERO
12470 UINT64_C(1), // C_ADDI_NOP
12471 UINT64_C(39969), // C_ADDW
12472 UINT64_C(36866), // C_ADD_HINT
12473 UINT64_C(35937), // C_AND
12474 UINT64_C(34817), // C_ANDI
12475 UINT64_C(49153), // C_BEQZ
12476 UINT64_C(57345), // C_BNEZ
12477 UINT64_C(36866), // C_EBREAK
12478 UINT64_C(8192), // C_FLD
12479 UINT64_C(8194), // C_FLDSP
12480 UINT64_C(24576), // C_FLW
12481 UINT64_C(24578), // C_FLWSP
12482 UINT64_C(40960), // C_FSD
12483 UINT64_C(40962), // C_FSDSP
12484 UINT64_C(57344), // C_FSW
12485 UINT64_C(57346), // C_FSWSP
12486 UINT64_C(40961), // C_J
12487 UINT64_C(8193), // C_JAL
12488 UINT64_C(36866), // C_JALR
12489 UINT64_C(32770), // C_JR
12490 UINT64_C(32768), // C_LBU
12491 UINT64_C(24576), // C_LD
12492 UINT64_C(24578), // C_LDSP
12493 UINT64_C(33856), // C_LH
12494 UINT64_C(33792), // C_LHU
12495 UINT64_C(16385), // C_LI
12496 UINT64_C(16385), // C_LI_HINT
12497 UINT64_C(24577), // C_LUI
12498 UINT64_C(24577), // C_LUI_HINT
12499 UINT64_C(16384), // C_LW
12500 UINT64_C(16386), // C_LWSP
12501 UINT64_C(24705), // C_MOP1
12502 UINT64_C(25985), // C_MOP11
12503 UINT64_C(26241), // C_MOP13
12504 UINT64_C(26497), // C_MOP15
12505 UINT64_C(24961), // C_MOP3
12506 UINT64_C(25217), // C_MOP5
12507 UINT64_C(25473), // C_MOP7
12508 UINT64_C(25729), // C_MOP9
12509 UINT64_C(40001), // C_MUL
12510 UINT64_C(32770), // C_MV
12511 UINT64_C(32770), // C_MV_HINT
12512 UINT64_C(1), // C_NOP
12513 UINT64_C(1), // C_NOP_HINT
12514 UINT64_C(40053), // C_NOT
12515 UINT64_C(35905), // C_OR
12516 UINT64_C(34816), // C_SB
12517 UINT64_C(57344), // C_SD
12518 UINT64_C(57346), // C_SDSP
12519 UINT64_C(40037), // C_SEXT_B
12520 UINT64_C(40045), // C_SEXT_H
12521 UINT64_C(35840), // C_SH
12522 UINT64_C(2), // C_SLLI
12523 UINT64_C(2), // C_SLLI64_HINT
12524 UINT64_C(2), // C_SLLI_HINT
12525 UINT64_C(33793), // C_SRAI
12526 UINT64_C(33793), // C_SRAI64_HINT
12527 UINT64_C(32769), // C_SRLI
12528 UINT64_C(32769), // C_SRLI64_HINT
12529 UINT64_C(25217), // C_SSPOPCHK
12530 UINT64_C(24705), // C_SSPUSH
12531 UINT64_C(35841), // C_SUB
12532 UINT64_C(39937), // C_SUBW
12533 UINT64_C(49152), // C_SW
12534 UINT64_C(49154), // C_SWSP
12535 UINT64_C(0), // C_UNIMP
12536 UINT64_C(35873), // C_XOR
12537 UINT64_C(40033), // C_ZEXT_B
12538 UINT64_C(40041), // C_ZEXT_H
12539 UINT64_C(40049), // C_ZEXT_W
12540 UINT64_C(33570867), // DIV
12541 UINT64_C(33574963), // DIVU
12542 UINT64_C(33574971), // DIVUW
12543 UINT64_C(33570875), // DIVW
12544 UINT64_C(2065694835), // DRET
12545 UINT64_C(1048691), // EBREAK
12546 UINT64_C(115), // ECALL
12547 UINT64_C(33554515), // FADD_D
12548 UINT64_C(33554515), // FADD_D_IN32X
12549 UINT64_C(33554515), // FADD_D_INX
12550 UINT64_C(67108947), // FADD_H
12551 UINT64_C(67108947), // FADD_H_INX
12552 UINT64_C(83), // FADD_S
12553 UINT64_C(83), // FADD_S_INX
12554 UINT64_C(3791654995), // FCLASS_D
12555 UINT64_C(3791654995), // FCLASS_D_IN32X
12556 UINT64_C(3791654995), // FCLASS_D_INX
12557 UINT64_C(3825209427), // FCLASS_H
12558 UINT64_C(3825209427), // FCLASS_H_INX
12559 UINT64_C(3758100563), // FCLASS_S
12560 UINT64_C(3758100563), // FCLASS_S_INX
12561 UINT64_C(3263168595), // FCVTMOD_W_D
12562 UINT64_C(1149239379), // FCVT_BF16_S
12563 UINT64_C(1109393491), // FCVT_D_H
12564 UINT64_C(1109393491), // FCVT_D_H_IN32X
12565 UINT64_C(1109393491), // FCVT_D_H_INX
12566 UINT64_C(3525312595), // FCVT_D_L
12567 UINT64_C(3526361171), // FCVT_D_LU
12568 UINT64_C(3526361171), // FCVT_D_LU_INX
12569 UINT64_C(3525312595), // FCVT_D_L_INX
12570 UINT64_C(1107296339), // FCVT_D_S
12571 UINT64_C(1107296339), // FCVT_D_S_IN32X
12572 UINT64_C(1107296339), // FCVT_D_S_INX
12573 UINT64_C(3523215443), // FCVT_D_W
12574 UINT64_C(3524264019), // FCVT_D_WU
12575 UINT64_C(3524264019), // FCVT_D_WU_IN32X
12576 UINT64_C(3524264019), // FCVT_D_WU_INX
12577 UINT64_C(3523215443), // FCVT_D_W_IN32X
12578 UINT64_C(3523215443), // FCVT_D_W_INX
12579 UINT64_C(1141899347), // FCVT_H_D
12580 UINT64_C(1141899347), // FCVT_H_D_IN32X
12581 UINT64_C(1141899347), // FCVT_H_D_INX
12582 UINT64_C(3558867027), // FCVT_H_L
12583 UINT64_C(3559915603), // FCVT_H_LU
12584 UINT64_C(3559915603), // FCVT_H_LU_INX
12585 UINT64_C(3558867027), // FCVT_H_L_INX
12586 UINT64_C(1140850771), // FCVT_H_S
12587 UINT64_C(1140850771), // FCVT_H_S_INX
12588 UINT64_C(3556769875), // FCVT_H_W
12589 UINT64_C(3557818451), // FCVT_H_WU
12590 UINT64_C(3557818451), // FCVT_H_WU_INX
12591 UINT64_C(3556769875), // FCVT_H_W_INX
12592 UINT64_C(3257925715), // FCVT_LU_D
12593 UINT64_C(3257925715), // FCVT_LU_D_INX
12594 UINT64_C(3291480147), // FCVT_LU_H
12595 UINT64_C(3291480147), // FCVT_LU_H_INX
12596 UINT64_C(3224371283), // FCVT_LU_S
12597 UINT64_C(3224371283), // FCVT_LU_S_INX
12598 UINT64_C(3256877139), // FCVT_L_D
12599 UINT64_C(3256877139), // FCVT_L_D_INX
12600 UINT64_C(3290431571), // FCVT_L_H
12601 UINT64_C(3290431571), // FCVT_L_H_INX
12602 UINT64_C(3223322707), // FCVT_L_S
12603 UINT64_C(3223322707), // FCVT_L_S_INX
12604 UINT64_C(1080033363), // FCVT_S_BF16
12605 UINT64_C(1074790483), // FCVT_S_D
12606 UINT64_C(1074790483), // FCVT_S_D_IN32X
12607 UINT64_C(1074790483), // FCVT_S_D_INX
12608 UINT64_C(1075839059), // FCVT_S_H
12609 UINT64_C(1075839059), // FCVT_S_H_INX
12610 UINT64_C(3491758163), // FCVT_S_L
12611 UINT64_C(3492806739), // FCVT_S_LU
12612 UINT64_C(3492806739), // FCVT_S_LU_INX
12613 UINT64_C(3491758163), // FCVT_S_L_INX
12614 UINT64_C(3489661011), // FCVT_S_W
12615 UINT64_C(3490709587), // FCVT_S_WU
12616 UINT64_C(3490709587), // FCVT_S_WU_INX
12617 UINT64_C(3489661011), // FCVT_S_W_INX
12618 UINT64_C(3255828563), // FCVT_WU_D
12619 UINT64_C(3255828563), // FCVT_WU_D_IN32X
12620 UINT64_C(3255828563), // FCVT_WU_D_INX
12621 UINT64_C(3289382995), // FCVT_WU_H
12622 UINT64_C(3289382995), // FCVT_WU_H_INX
12623 UINT64_C(3222274131), // FCVT_WU_S
12624 UINT64_C(3222274131), // FCVT_WU_S_INX
12625 UINT64_C(3254779987), // FCVT_W_D
12626 UINT64_C(3254779987), // FCVT_W_D_IN32X
12627 UINT64_C(3254779987), // FCVT_W_D_INX
12628 UINT64_C(3288334419), // FCVT_W_H
12629 UINT64_C(3288334419), // FCVT_W_H_INX
12630 UINT64_C(3221225555), // FCVT_W_S
12631 UINT64_C(3221225555), // FCVT_W_S_INX
12632 UINT64_C(436207699), // FDIV_D
12633 UINT64_C(436207699), // FDIV_D_IN32X
12634 UINT64_C(436207699), // FDIV_D_INX
12635 UINT64_C(469762131), // FDIV_H
12636 UINT64_C(469762131), // FDIV_H_INX
12637 UINT64_C(402653267), // FDIV_S
12638 UINT64_C(402653267), // FDIV_S_INX
12639 UINT64_C(15), // FENCE
12640 UINT64_C(4111), // FENCE_I
12641 UINT64_C(2200961039), // FENCE_TSO
12642 UINT64_C(2717917267), // FEQ_D
12643 UINT64_C(2717917267), // FEQ_D_IN32X
12644 UINT64_C(2717917267), // FEQ_D_INX
12645 UINT64_C(2751471699), // FEQ_H
12646 UINT64_C(2751471699), // FEQ_H_INX
12647 UINT64_C(2684362835), // FEQ_S
12648 UINT64_C(2684362835), // FEQ_S_INX
12649 UINT64_C(12295), // FLD
12650 UINT64_C(2717925459), // FLEQ_D
12651 UINT64_C(2751479891), // FLEQ_H
12652 UINT64_C(2684371027), // FLEQ_S
12653 UINT64_C(2717909075), // FLE_D
12654 UINT64_C(2717909075), // FLE_D_IN32X
12655 UINT64_C(2717909075), // FLE_D_INX
12656 UINT64_C(2751463507), // FLE_H
12657 UINT64_C(2751463507), // FLE_H_INX
12658 UINT64_C(2684354643), // FLE_S
12659 UINT64_C(2684354643), // FLE_S_INX
12660 UINT64_C(4103), // FLH
12661 UINT64_C(4061134931), // FLI_D
12662 UINT64_C(4094689363), // FLI_H
12663 UINT64_C(4027580499), // FLI_S
12664 UINT64_C(2717929555), // FLTQ_D
12665 UINT64_C(2751483987), // FLTQ_H
12666 UINT64_C(2684375123), // FLTQ_S
12667 UINT64_C(2717913171), // FLT_D
12668 UINT64_C(2717913171), // FLT_D_IN32X
12669 UINT64_C(2717913171), // FLT_D_INX
12670 UINT64_C(2751467603), // FLT_H
12671 UINT64_C(2751467603), // FLT_H_INX
12672 UINT64_C(2684358739), // FLT_S
12673 UINT64_C(2684358739), // FLT_S_INX
12674 UINT64_C(8199), // FLW
12675 UINT64_C(33554499), // FMADD_D
12676 UINT64_C(33554499), // FMADD_D_IN32X
12677 UINT64_C(33554499), // FMADD_D_INX
12678 UINT64_C(67108931), // FMADD_H
12679 UINT64_C(67108931), // FMADD_H_INX
12680 UINT64_C(67), // FMADD_S
12681 UINT64_C(67), // FMADD_S_INX
12682 UINT64_C(704655443), // FMAXM_D
12683 UINT64_C(738209875), // FMAXM_H
12684 UINT64_C(671101011), // FMAXM_S
12685 UINT64_C(704647251), // FMAX_D
12686 UINT64_C(704647251), // FMAX_D_IN32X
12687 UINT64_C(704647251), // FMAX_D_INX
12688 UINT64_C(738201683), // FMAX_H
12689 UINT64_C(738201683), // FMAX_H_INX
12690 UINT64_C(671092819), // FMAX_S
12691 UINT64_C(671092819), // FMAX_S_INX
12692 UINT64_C(704651347), // FMINM_D
12693 UINT64_C(738205779), // FMINM_H
12694 UINT64_C(671096915), // FMINM_S
12695 UINT64_C(704643155), // FMIN_D
12696 UINT64_C(704643155), // FMIN_D_IN32X
12697 UINT64_C(704643155), // FMIN_D_INX
12698 UINT64_C(738197587), // FMIN_H
12699 UINT64_C(738197587), // FMIN_H_INX
12700 UINT64_C(671088723), // FMIN_S
12701 UINT64_C(671088723), // FMIN_S_INX
12702 UINT64_C(33554503), // FMSUB_D
12703 UINT64_C(33554503), // FMSUB_D_IN32X
12704 UINT64_C(33554503), // FMSUB_D_INX
12705 UINT64_C(67108935), // FMSUB_H
12706 UINT64_C(67108935), // FMSUB_H_INX
12707 UINT64_C(71), // FMSUB_S
12708 UINT64_C(71), // FMSUB_S_INX
12709 UINT64_C(301989971), // FMUL_D
12710 UINT64_C(301989971), // FMUL_D_IN32X
12711 UINT64_C(301989971), // FMUL_D_INX
12712 UINT64_C(335544403), // FMUL_H
12713 UINT64_C(335544403), // FMUL_H_INX
12714 UINT64_C(268435539), // FMUL_S
12715 UINT64_C(268435539), // FMUL_S_INX
12716 UINT64_C(3792699475), // FMVH_X_D
12717 UINT64_C(2986344531), // FMVP_D_X
12718 UINT64_C(4060086355), // FMV_D_X
12719 UINT64_C(4093640787), // FMV_H_X
12720 UINT64_C(4026531923), // FMV_W_X
12721 UINT64_C(3791650899), // FMV_X_D
12722 UINT64_C(3825205331), // FMV_X_H
12723 UINT64_C(3758096467), // FMV_X_W
12724 UINT64_C(3758096467), // FMV_X_W_FPR64
12725 UINT64_C(33554511), // FNMADD_D
12726 UINT64_C(33554511), // FNMADD_D_IN32X
12727 UINT64_C(33554511), // FNMADD_D_INX
12728 UINT64_C(67108943), // FNMADD_H
12729 UINT64_C(67108943), // FNMADD_H_INX
12730 UINT64_C(79), // FNMADD_S
12731 UINT64_C(79), // FNMADD_S_INX
12732 UINT64_C(33554507), // FNMSUB_D
12733 UINT64_C(33554507), // FNMSUB_D_IN32X
12734 UINT64_C(33554507), // FNMSUB_D_INX
12735 UINT64_C(67108939), // FNMSUB_H
12736 UINT64_C(67108939), // FNMSUB_H_INX
12737 UINT64_C(75), // FNMSUB_S
12738 UINT64_C(75), // FNMSUB_S_INX
12739 UINT64_C(1112539219), // FROUNDNX_D
12740 UINT64_C(1146093651), // FROUNDNX_H
12741 UINT64_C(1078984787), // FROUNDNX_S
12742 UINT64_C(1111490643), // FROUND_D
12743 UINT64_C(1145045075), // FROUND_H
12744 UINT64_C(1077936211), // FROUND_S
12745 UINT64_C(12327), // FSD
12746 UINT64_C(570429523), // FSGNJN_D
12747 UINT64_C(570429523), // FSGNJN_D_IN32X
12748 UINT64_C(570429523), // FSGNJN_D_INX
12749 UINT64_C(603983955), // FSGNJN_H
12750 UINT64_C(603983955), // FSGNJN_H_INX
12751 UINT64_C(536875091), // FSGNJN_S
12752 UINT64_C(536875091), // FSGNJN_S_INX
12753 UINT64_C(570433619), // FSGNJX_D
12754 UINT64_C(570433619), // FSGNJX_D_IN32X
12755 UINT64_C(570433619), // FSGNJX_D_INX
12756 UINT64_C(603988051), // FSGNJX_H
12757 UINT64_C(603988051), // FSGNJX_H_INX
12758 UINT64_C(536879187), // FSGNJX_S
12759 UINT64_C(536879187), // FSGNJX_S_INX
12760 UINT64_C(570425427), // FSGNJ_D
12761 UINT64_C(570425427), // FSGNJ_D_IN32X
12762 UINT64_C(570425427), // FSGNJ_D_INX
12763 UINT64_C(603979859), // FSGNJ_H
12764 UINT64_C(603979859), // FSGNJ_H_INX
12765 UINT64_C(536870995), // FSGNJ_S
12766 UINT64_C(536870995), // FSGNJ_S_INX
12767 UINT64_C(4135), // FSH
12768 UINT64_C(1509949523), // FSQRT_D
12769 UINT64_C(1509949523), // FSQRT_D_IN32X
12770 UINT64_C(1509949523), // FSQRT_D_INX
12771 UINT64_C(1543503955), // FSQRT_H
12772 UINT64_C(1543503955), // FSQRT_H_INX
12773 UINT64_C(1476395091), // FSQRT_S
12774 UINT64_C(1476395091), // FSQRT_S_INX
12775 UINT64_C(167772243), // FSUB_D
12776 UINT64_C(167772243), // FSUB_D_IN32X
12777 UINT64_C(167772243), // FSUB_D_INX
12778 UINT64_C(201326675), // FSUB_H
12779 UINT64_C(201326675), // FSUB_H_INX
12780 UINT64_C(134217811), // FSUB_S
12781 UINT64_C(134217811), // FSUB_S_INX
12782 UINT64_C(8231), // FSW
12783 UINT64_C(1644167283), // HFENCE_GVMA
12784 UINT64_C(570425459), // HFENCE_VVMA
12785 UINT64_C(1711276147), // HINVAL_GVMA
12786 UINT64_C(637534323), // HINVAL_VVMA
12787 UINT64_C(1680883827), // HLVX_HU
12788 UINT64_C(1747992691), // HLVX_WU
12789 UINT64_C(1610629235), // HLV_B
12790 UINT64_C(1611677811), // HLV_BU
12791 UINT64_C(1811955827), // HLV_D
12792 UINT64_C(1677738099), // HLV_H
12793 UINT64_C(1678786675), // HLV_HU
12794 UINT64_C(1744846963), // HLV_W
12795 UINT64_C(1745895539), // HLV_WU
12796 UINT64_C(1644183667), // HSV_B
12797 UINT64_C(1845510259), // HSV_D
12798 UINT64_C(1711292531), // HSV_H
12799 UINT64_C(1778401395), // HSV_W
12800 UINT64_C(0), // Insn16
12801 UINT64_C(0), // Insn32
12802 UINT64_C(0), // InsnB
12803 UINT64_C(0), // InsnCA
12804 UINT64_C(0), // InsnCB
12805 UINT64_C(0), // InsnCI
12806 UINT64_C(0), // InsnCIW
12807 UINT64_C(0), // InsnCJ
12808 UINT64_C(0), // InsnCL
12809 UINT64_C(0), // InsnCR
12810 UINT64_C(0), // InsnCS
12811 UINT64_C(0), // InsnCSS
12812 UINT64_C(0), // InsnI
12813 UINT64_C(0), // InsnI_Mem
12814 UINT64_C(0), // InsnJ
12815 UINT64_C(0), // InsnR
12816 UINT64_C(0), // InsnR4
12817 UINT64_C(0), // InsnS
12818 UINT64_C(0), // InsnU
12819 UINT64_C(111), // JAL
12820 UINT64_C(103), // JALR
12821 UINT64_C(3), // LB
12822 UINT64_C(16387), // LBU
12823 UINT64_C(872415279), // LB_AQ
12824 UINT64_C(905969711), // LB_AQ_RL
12825 UINT64_C(12291), // LD
12826 UINT64_C(872427567), // LD_AQ
12827 UINT64_C(905981999), // LD_AQ_RL
12828 UINT64_C(4099), // LH
12829 UINT64_C(20483), // LHU
12830 UINT64_C(872419375), // LH_AQ
12831 UINT64_C(905973807), // LH_AQ_RL
12832 UINT64_C(268447791), // LR_D
12833 UINT64_C(335556655), // LR_D_AQ
12834 UINT64_C(369111087), // LR_D_AQ_RL
12835 UINT64_C(302002223), // LR_D_RL
12836 UINT64_C(268443695), // LR_W
12837 UINT64_C(335552559), // LR_W_AQ
12838 UINT64_C(369106991), // LR_W_AQ_RL
12839 UINT64_C(301998127), // LR_W_RL
12840 UINT64_C(55), // LUI
12841 UINT64_C(8195), // LW
12842 UINT64_C(24579), // LWU
12843 UINT64_C(872423471), // LW_AQ
12844 UINT64_C(905977903), // LW_AQ_RL
12845 UINT64_C(167796787), // MAX
12846 UINT64_C(167800883), // MAXU
12847 UINT64_C(167788595), // MIN
12848 UINT64_C(167792691), // MINU
12849 UINT64_C(2176860275), // MOPR0
12850 UINT64_C(2177908851), // MOPR1
12851 UINT64_C(2313175155), // MOPR10
12852 UINT64_C(2314223731), // MOPR11
12853 UINT64_C(2378186867), // MOPR12
12854 UINT64_C(2379235443), // MOPR13
12855 UINT64_C(2380284019), // MOPR14
12856 UINT64_C(2381332595), // MOPR15
12857 UINT64_C(3250602099), // MOPR16
12858 UINT64_C(3251650675), // MOPR17
12859 UINT64_C(3252699251), // MOPR18
12860 UINT64_C(3253747827), // MOPR19
12861 UINT64_C(2178957427), // MOPR2
12862 UINT64_C(3317710963), // MOPR20
12863 UINT64_C(3318759539), // MOPR21
12864 UINT64_C(3319808115), // MOPR22
12865 UINT64_C(3320856691), // MOPR23
12866 UINT64_C(3384819827), // MOPR24
12867 UINT64_C(3385868403), // MOPR25
12868 UINT64_C(3386916979), // MOPR26
12869 UINT64_C(3387965555), // MOPR27
12870 UINT64_C(3451928691), // MOPR28
12871 UINT64_C(3452977267), // MOPR29
12872 UINT64_C(2180006003), // MOPR3
12873 UINT64_C(3454025843), // MOPR30
12874 UINT64_C(3455074419), // MOPR31
12875 UINT64_C(2243969139), // MOPR4
12876 UINT64_C(2245017715), // MOPR5
12877 UINT64_C(2246066291), // MOPR6
12878 UINT64_C(2247114867), // MOPR7
12879 UINT64_C(2311078003), // MOPR8
12880 UINT64_C(2312126579), // MOPR9
12881 UINT64_C(2181054579), // MOPRR0
12882 UINT64_C(2248163443), // MOPRR1
12883 UINT64_C(2315272307), // MOPRR2
12884 UINT64_C(2382381171), // MOPRR3
12885 UINT64_C(3254796403), // MOPRR4
12886 UINT64_C(3321905267), // MOPRR5
12887 UINT64_C(3389014131), // MOPRR6
12888 UINT64_C(3456122995), // MOPRR7
12889 UINT64_C(807403635), // MRET
12890 UINT64_C(33554483), // MUL
12891 UINT64_C(33558579), // MULH
12892 UINT64_C(33562675), // MULHSU
12893 UINT64_C(33566771), // MULHU
12894 UINT64_C(33554491), // MULW
12895 UINT64_C(24627), // OR
12896 UINT64_C(678449171), // ORC_B
12897 UINT64_C(24595), // ORI
12898 UINT64_C(1073766451), // ORN
12899 UINT64_C(134234163), // PACK
12900 UINT64_C(134246451), // PACKH
12901 UINT64_C(134234171), // PACKW
12902 UINT64_C(24595), // PREFETCH_I
12903 UINT64_C(1073171), // PREFETCH_R
12904 UINT64_C(3170323), // PREFETCH_W
12905 UINT64_C(8192), // QK_C_LBU
12906 UINT64_C(32768), // QK_C_LBUSP
12907 UINT64_C(8194), // QK_C_LHU
12908 UINT64_C(32800), // QK_C_LHUSP
12909 UINT64_C(40960), // QK_C_SB
12910 UINT64_C(32832), // QK_C_SBSP
12911 UINT64_C(40962), // QK_C_SH
12912 UINT64_C(32864), // QK_C_SHSP
12913 UINT64_C(33579059), // REM
12914 UINT64_C(33583155), // REMU
12915 UINT64_C(33583163), // REMUW
12916 UINT64_C(33579067), // REMW
12917 UINT64_C(1770016787), // REV8_RV32
12918 UINT64_C(1803571219), // REV8_RV64
12919 UINT64_C(1610616883), // ROL
12920 UINT64_C(1610616891), // ROLW
12921 UINT64_C(1610633267), // ROR
12922 UINT64_C(1610633235), // RORI
12923 UINT64_C(1610633243), // RORIW
12924 UINT64_C(1610633275), // RORW
12925 UINT64_C(35), // SB
12926 UINT64_C(1040187439), // SB_AQ_RL
12927 UINT64_C(973078575), // SB_RL
12928 UINT64_C(402665519), // SC_D
12929 UINT64_C(469774383), // SC_D_AQ
12930 UINT64_C(503328815), // SC_D_AQ_RL
12931 UINT64_C(436219951), // SC_D_RL
12932 UINT64_C(402661423), // SC_W
12933 UINT64_C(469770287), // SC_W_AQ
12934 UINT64_C(503324719), // SC_W_AQ_RL
12935 UINT64_C(436215855), // SC_W_RL
12936 UINT64_C(12323), // SD
12937 UINT64_C(1040199727), // SD_AQ_RL
12938 UINT64_C(973090863), // SD_RL
12939 UINT64_C(1614811155), // SEXT_B
12940 UINT64_C(1615859731), // SEXT_H
12941 UINT64_C(403701875), // SFENCE_INVAL_IR
12942 UINT64_C(301990003), // SFENCE_VMA
12943 UINT64_C(402653299), // SFENCE_W_INVAL
12944 UINT64_C(4229955699), // SF_CDISCARD_D_L1
12945 UINT64_C(810549363), // SF_CEASE
12946 UINT64_C(4227858547), // SF_CFLUSH_D_L1
12947 UINT64_C(4131), // SH
12948 UINT64_C(536879155), // SH1ADD
12949 UINT64_C(536879163), // SH1ADD_UW
12950 UINT64_C(536887347), // SH2ADD
12951 UINT64_C(536887355), // SH2ADD_UW
12952 UINT64_C(536895539), // SH3ADD
12953 UINT64_C(536895547), // SH3ADD_UW
12954 UINT64_C(270536723), // SHA256SIG0
12955 UINT64_C(271585299), // SHA256SIG1
12956 UINT64_C(268439571), // SHA256SUM0
12957 UINT64_C(269488147), // SHA256SUM1
12958 UINT64_C(274731027), // SHA512SIG0
12959 UINT64_C(1543503923), // SHA512SIG0H
12960 UINT64_C(1409286195), // SHA512SIG0L
12961 UINT64_C(275779603), // SHA512SIG1
12962 UINT64_C(1577058355), // SHA512SIG1H
12963 UINT64_C(1442840627), // SHA512SIG1L
12964 UINT64_C(272633875), // SHA512SUM0
12965 UINT64_C(1342177331), // SHA512SUM0R
12966 UINT64_C(273682451), // SHA512SUM1
12967 UINT64_C(1375731763), // SHA512SUM1R
12968 UINT64_C(1040191535), // SH_AQ_RL
12969 UINT64_C(973082671), // SH_RL
12970 UINT64_C(369098867), // SINVAL_VMA
12971 UINT64_C(4147), // SLL
12972 UINT64_C(4115), // SLLI
12973 UINT64_C(4123), // SLLIW
12974 UINT64_C(134221851), // SLLI_UW
12975 UINT64_C(4155), // SLLW
12976 UINT64_C(8243), // SLT
12977 UINT64_C(8211), // SLTI
12978 UINT64_C(12307), // SLTIU
12979 UINT64_C(12339), // SLTU
12980 UINT64_C(276828179), // SM3P0
12981 UINT64_C(277876755), // SM3P1
12982 UINT64_C(805306419), // SM4ED
12983 UINT64_C(872415283), // SM4KS
12984 UINT64_C(1073762355), // SRA
12985 UINT64_C(1073762323), // SRAI
12986 UINT64_C(1073762331), // SRAIW
12987 UINT64_C(1073762363), // SRAW
12988 UINT64_C(270532723), // SRET
12989 UINT64_C(20531), // SRL
12990 UINT64_C(20499), // SRLI
12991 UINT64_C(20507), // SRLIW
12992 UINT64_C(20539), // SRLW
12993 UINT64_C(1207971887), // SSAMOSWAP_D
12994 UINT64_C(1275080751), // SSAMOSWAP_D_AQ
12995 UINT64_C(1308635183), // SSAMOSWAP_D_AQ_RL
12996 UINT64_C(1241526319), // SSAMOSWAP_D_RL
12997 UINT64_C(1207967791), // SSAMOSWAP_W
12998 UINT64_C(1275076655), // SSAMOSWAP_W_AQ
12999 UINT64_C(1308631087), // SSAMOSWAP_W_AQ_RL
13000 UINT64_C(1241522223), // SSAMOSWAP_W_RL
13001 UINT64_C(3451928691), // SSPOPCHK
13002 UINT64_C(3456122995), // SSPUSH
13003 UINT64_C(3451928691), // SSRDP
13004 UINT64_C(1073741875), // SUB
13005 UINT64_C(1073741883), // SUBW
13006 UINT64_C(8227), // SW
13007 UINT64_C(1040195631), // SW_AQ_RL
13008 UINT64_C(973086767), // SW_RL
13009 UINT64_C(2415943691), // THVdotVMAQASU_VV
13010 UINT64_C(2483052555), // THVdotVMAQASU_VX
13011 UINT64_C(2617270283), // THVdotVMAQAUS_VX
13012 UINT64_C(2281725963), // THVdotVMAQAU_VV
13013 UINT64_C(2348834827), // THVdotVMAQAU_VX
13014 UINT64_C(2147508235), // THVdotVMAQA_VV
13015 UINT64_C(2214617099), // THVdotVMAQA_VX
13016 UINT64_C(4107), // TH_ADDSL
13017 UINT64_C(1048587), // TH_DCACHE_CALL
13018 UINT64_C(3145739), // TH_DCACHE_CIALL
13019 UINT64_C(45088779), // TH_DCACHE_CIPA
13020 UINT64_C(36700171), // TH_DCACHE_CISW
13021 UINT64_C(40894475), // TH_DCACHE_CIVA
13022 UINT64_C(42991627), // TH_DCACHE_CPA
13023 UINT64_C(41943051), // TH_DCACHE_CPAL1
13024 UINT64_C(34603019), // TH_DCACHE_CSW
13025 UINT64_C(38797323), // TH_DCACHE_CVA
13026 UINT64_C(37748747), // TH_DCACHE_CVAL1
13027 UINT64_C(2097163), // TH_DCACHE_IALL
13028 UINT64_C(44040203), // TH_DCACHE_IPA
13029 UINT64_C(35651595), // TH_DCACHE_ISW
13030 UINT64_C(39845899), // TH_DCACHE_IVA
13031 UINT64_C(8203), // TH_EXT
13032 UINT64_C(12299), // TH_EXTU
13033 UINT64_C(2214596619), // TH_FF0
13034 UINT64_C(2248151051), // TH_FF1
13035 UINT64_C(1610637323), // TH_FLRD
13036 UINT64_C(1073766411), // TH_FLRW
13037 UINT64_C(1879072779), // TH_FLURD
13038 UINT64_C(1342201867), // TH_FLURW
13039 UINT64_C(1610641419), // TH_FSRD
13040 UINT64_C(1073770507), // TH_FSRW
13041 UINT64_C(1879076875), // TH_FSURD
13042 UINT64_C(1342205963), // TH_FSURW
13043 UINT64_C(16777227), // TH_ICACHE_IALL
13044 UINT64_C(17825803), // TH_ICACHE_IALLS
13045 UINT64_C(58720267), // TH_ICACHE_IPA
13046 UINT64_C(50331659), // TH_ICACHE_IVA
13047 UINT64_C(22020107), // TH_L2CACHE_CALL
13048 UINT64_C(24117259), // TH_L2CACHE_CIALL
13049 UINT64_C(23068683), // TH_L2CACHE_IALL
13050 UINT64_C(402669579), // TH_LBIA
13051 UINT64_C(134234123), // TH_LBIB
13052 UINT64_C(2550153227), // TH_LBUIA
13053 UINT64_C(2281717771), // TH_LBUIB
13054 UINT64_C(4160765963), // TH_LDD
13055 UINT64_C(2013282315), // TH_LDIA
13056 UINT64_C(1744846859), // TH_LDIB
13057 UINT64_C(939540491), // TH_LHIA
13058 UINT64_C(671105035), // TH_LHIB
13059 UINT64_C(3087024139), // TH_LHUIA
13060 UINT64_C(2818588683), // TH_LHUIB
13061 UINT64_C(16395), // TH_LRB
13062 UINT64_C(2147500043), // TH_LRBU
13063 UINT64_C(1610629131), // TH_LRD
13064 UINT64_C(536887307), // TH_LRH
13065 UINT64_C(2684370955), // TH_LRHU
13066 UINT64_C(1073758219), // TH_LRW
13067 UINT64_C(3221241867), // TH_LRWU
13068 UINT64_C(268451851), // TH_LURB
13069 UINT64_C(2415935499), // TH_LURBU
13070 UINT64_C(1879064587), // TH_LURD
13071 UINT64_C(805322763), // TH_LURH
13072 UINT64_C(2952806411), // TH_LURHU
13073 UINT64_C(1342193675), // TH_LURW
13074 UINT64_C(3489677323), // TH_LURWU
13075 UINT64_C(3758112779), // TH_LWD
13076 UINT64_C(1476411403), // TH_LWIA
13077 UINT64_C(1207975947), // TH_LWIB
13078 UINT64_C(4026548235), // TH_LWUD
13079 UINT64_C(3623895051), // TH_LWUIA
13080 UINT64_C(3355459595), // TH_LWUIB
13081 UINT64_C(536875019), // TH_MULA
13082 UINT64_C(671092747), // TH_MULAH
13083 UINT64_C(603983883), // TH_MULAW
13084 UINT64_C(570429451), // TH_MULS
13085 UINT64_C(704647179), // TH_MULSH
13086 UINT64_C(637538315), // TH_MULSW
13087 UINT64_C(1073745931), // TH_MVEQZ
13088 UINT64_C(1107300363), // TH_MVNEZ
13089 UINT64_C(2181042187), // TH_REV
13090 UINT64_C(2415923211), // TH_REVW
13091 UINT64_C(402673675), // TH_SBIA
13092 UINT64_C(134238219), // TH_SBIB
13093 UINT64_C(4160770059), // TH_SDD
13094 UINT64_C(2013286411), // TH_SDIA
13095 UINT64_C(1744850955), // TH_SDIB
13096 UINT64_C(67108875), // TH_SFENCE_VMAS
13097 UINT64_C(939544587), // TH_SHIA
13098 UINT64_C(671109131), // TH_SHIB
13099 UINT64_C(20491), // TH_SRB
13100 UINT64_C(1610633227), // TH_SRD
13101 UINT64_C(536891403), // TH_SRH
13102 UINT64_C(268439563), // TH_SRRI
13103 UINT64_C(335548427), // TH_SRRIW
13104 UINT64_C(1073762315), // TH_SRW
13105 UINT64_C(268455947), // TH_SURB
13106 UINT64_C(1879068683), // TH_SURD
13107 UINT64_C(805326859), // TH_SURH
13108 UINT64_C(1342197771), // TH_SURW
13109 UINT64_C(3758116875), // TH_SWD
13110 UINT64_C(1476415499), // TH_SWIA
13111 UINT64_C(1207980043), // TH_SWIB
13112 UINT64_C(25165835), // TH_SYNC
13113 UINT64_C(27262987), // TH_SYNC_I
13114 UINT64_C(28311563), // TH_SYNC_IS
13115 UINT64_C(26214411), // TH_SYNC_S
13116 UINT64_C(2281705483), // TH_TST
13117 UINT64_C(2147487755), // TH_TSTNBZ
13118 UINT64_C(3221229683), // UNIMP
13119 UINT64_C(149966867), // UNZIP_RV32
13120 UINT64_C(536879191), // VAADDU_VV
13121 UINT64_C(536895575), // VAADDU_VX
13122 UINT64_C(603988055), // VAADD_VV
13123 UINT64_C(604004439), // VAADD_VX
13124 UINT64_C(1073754199), // VADC_VIM
13125 UINT64_C(1073741911), // VADC_VVM
13126 UINT64_C(1073758295), // VADC_VXM
13127 UINT64_C(12375), // VADD_VI
13128 UINT64_C(87), // VADD_VV
13129 UINT64_C(16471), // VADD_VX
13130 UINT64_C(2785058935), // VAESDF_VS
13131 UINT64_C(2717950071), // VAESDF_VV
13132 UINT64_C(2785026167), // VAESDM_VS
13133 UINT64_C(2717917303), // VAESDM_VV
13134 UINT64_C(2785124471), // VAESEF_VS
13135 UINT64_C(2718015607), // VAESEF_VV
13136 UINT64_C(2785091703), // VAESEM_VS
13137 UINT64_C(2717982839), // VAESEM_VV
13138 UINT64_C(2315264119), // VAESKF1_VI
13139 UINT64_C(2852135031), // VAESKF2_VI
13140 UINT64_C(2785255543), // VAESZ_VS
13141 UINT64_C(67108951), // VANDN_VV
13142 UINT64_C(67125335), // VANDN_VX
13143 UINT64_C(603992151), // VAND_VI
13144 UINT64_C(603979863), // VAND_VV
13145 UINT64_C(603996247), // VAND_VX
13146 UINT64_C(671096919), // VASUBU_VV
13147 UINT64_C(671113303), // VASUBU_VX
13148 UINT64_C(738205783), // VASUB_VV
13149 UINT64_C(738222167), // VASUB_VX
13150 UINT64_C(1208229975), // VBREV8_V
13151 UINT64_C(1208295511), // VBREV_V
13152 UINT64_C(872423511), // VCLMULH_VV
13153 UINT64_C(872439895), // VCLMULH_VX
13154 UINT64_C(805314647), // VCLMUL_VV
13155 UINT64_C(805331031), // VCLMUL_VX
13156 UINT64_C(1208361047), // VCLZ_V
13157 UINT64_C(1577066583), // VCOMPRESS_VM
13158 UINT64_C(1074274391), // VCPOP_M
13159 UINT64_C(1208426583), // VCPOP_V
13160 UINT64_C(1208393815), // VCTZ_V
13161 UINT64_C(704663643), // VC_FV
13162 UINT64_C(2852147291), // VC_FVV
13163 UINT64_C(4194324571), // VC_FVW
13164 UINT64_C(33566811), // VC_I
13165 UINT64_C(570437723), // VC_IV
13166 UINT64_C(2717921371), // VC_IVV
13167 UINT64_C(4060098651), // VC_IVW
13168 UINT64_C(570425435), // VC_VV
13169 UINT64_C(2717909083), // VC_VVV
13170 UINT64_C(4060086363), // VC_VVW
13171 UINT64_C(671109211), // VC_V_FV
13172 UINT64_C(2818592859), // VC_V_FVV
13173 UINT64_C(4160770139), // VC_V_FVW
13174 UINT64_C(12379), // VC_V_I
13175 UINT64_C(536883291), // VC_V_IV
13176 UINT64_C(2684366939), // VC_V_IVV
13177 UINT64_C(4026544219), // VC_V_IVW
13178 UINT64_C(536871003), // VC_V_VV
13179 UINT64_C(2684354651), // VC_V_VVV
13180 UINT64_C(4026531931), // VC_V_VVW
13181 UINT64_C(16475), // VC_V_X
13182 UINT64_C(536887387), // VC_V_XV
13183 UINT64_C(2684371035), // VC_V_XVV
13184 UINT64_C(4026548315), // VC_V_XVW
13185 UINT64_C(33570907), // VC_X
13186 UINT64_C(570441819), // VC_XV
13187 UINT64_C(2717925467), // VC_XVV
13188 UINT64_C(4060102747), // VC_XVW
13189 UINT64_C(2147491927), // VDIVU_VV
13190 UINT64_C(2147508311), // VDIVU_VX
13191 UINT64_C(2214600791), // VDIV_VV
13192 UINT64_C(2214617175), // VDIV_VX
13193 UINT64_C(20567), // VFADD_VF
13194 UINT64_C(4183), // VFADD_VV
13195 UINT64_C(1275596887), // VFCLASS_V
13196 UINT64_C(1208029271), // VFCVT_F_XU_V
13197 UINT64_C(1208062039), // VFCVT_F_X_V
13198 UINT64_C(1208160343), // VFCVT_RTZ_XU_F_V
13199 UINT64_C(1208193111), // VFCVT_RTZ_X_F_V
13200 UINT64_C(1207963735), // VFCVT_XU_F_V
13201 UINT64_C(1207996503), // VFCVT_X_F_V
13202 UINT64_C(2147504215), // VFDIV_VF
13203 UINT64_C(2147487831), // VFDIV_VV
13204 UINT64_C(1074307159), // VFIRST_M
13205 UINT64_C(2952810583), // VFMACC_VF
13206 UINT64_C(2952794199), // VFMACC_VV
13207 UINT64_C(2684375127), // VFMADD_VF
13208 UINT64_C(2684358743), // VFMADD_VV
13209 UINT64_C(402673751), // VFMAX_VF
13210 UINT64_C(402657367), // VFMAX_VV
13211 UINT64_C(1543524439), // VFMERGE_VFM
13212 UINT64_C(268456023), // VFMIN_VF
13213 UINT64_C(268439639), // VFMIN_VV
13214 UINT64_C(3087028311), // VFMSAC_VF
13215 UINT64_C(3087011927), // VFMSAC_VV
13216 UINT64_C(2818592855), // VFMSUB_VF
13217 UINT64_C(2818576471), // VFMSUB_VV
13218 UINT64_C(2415939671), // VFMUL_VF
13219 UINT64_C(2415923287), // VFMUL_VV
13220 UINT64_C(1107300439), // VFMV_F_S
13221 UINT64_C(1107316823), // VFMV_S_F
13222 UINT64_C(1577078871), // VFMV_V_F
13223 UINT64_C(1208914007), // VFNCVTBF16_F_F_W
13224 UINT64_C(1208619095), // VFNCVT_F_F_W
13225 UINT64_C(1208553559), // VFNCVT_F_XU_W
13226 UINT64_C(1208586327), // VFNCVT_F_X_W
13227 UINT64_C(1208651863), // VFNCVT_ROD_F_F_W
13228 UINT64_C(1208684631), // VFNCVT_RTZ_XU_F_W
13229 UINT64_C(1208717399), // VFNCVT_RTZ_X_F_W
13230 UINT64_C(1208488023), // VFNCVT_XU_F_W
13231 UINT64_C(1208520791), // VFNCVT_X_F_W
13232 UINT64_C(3019919447), // VFNMACC_VF
13233 UINT64_C(3019903063), // VFNMACC_VV
13234 UINT64_C(2751483991), // VFNMADD_VF
13235 UINT64_C(2751467607), // VFNMADD_VV
13236 UINT64_C(3154137175), // VFNMSAC_VF
13237 UINT64_C(3154120791), // VFNMSAC_VV
13238 UINT64_C(2885701719), // VFNMSUB_VF
13239 UINT64_C(2885685335), // VFNMSUB_VV
13240 UINT64_C(2281721947), // VFNRCLIP_XU_F_QF
13241 UINT64_C(2348830811), // VFNRCLIP_X_F_QF
13242 UINT64_C(2214613079), // VFRDIV_VF
13243 UINT64_C(1275236439), // VFREC7_V
13244 UINT64_C(469766231), // VFREDMAX_VS
13245 UINT64_C(335548503), // VFREDMIN_VS
13246 UINT64_C(201330775), // VFREDOSUM_VS
13247 UINT64_C(67113047), // VFREDUSUM_VS
13248 UINT64_C(1275203671), // VFRSQRT7_V
13249 UINT64_C(2617266263), // VFRSUB_VF
13250 UINT64_C(604000343), // VFSGNJN_VF
13251 UINT64_C(603983959), // VFSGNJN_VV
13252 UINT64_C(671109207), // VFSGNJX_VF
13253 UINT64_C(671092823), // VFSGNJX_VV
13254 UINT64_C(536891479), // VFSGNJ_VF
13255 UINT64_C(536875095), // VFSGNJ_VV
13256 UINT64_C(1006653527), // VFSLIDE1DOWN_VF
13257 UINT64_C(939544663), // VFSLIDE1UP_VF
13258 UINT64_C(1275072599), // VFSQRT_V
13259 UINT64_C(134238295), // VFSUB_VF
13260 UINT64_C(134221911), // VFSUB_VV
13261 UINT64_C(3221246039), // VFWADD_VF
13262 UINT64_C(3221229655), // VFWADD_VV
13263 UINT64_C(3489681495), // VFWADD_WF
13264 UINT64_C(3489665111), // VFWADD_WV
13265 UINT64_C(1208389719), // VFWCVTBF16_F_F_V
13266 UINT64_C(1208356951), // VFWCVT_F_F_V
13267 UINT64_C(1208291415), // VFWCVT_F_XU_V
13268 UINT64_C(1208324183), // VFWCVT_F_X_V
13269 UINT64_C(1208422487), // VFWCVT_RTZ_XU_F_V
13270 UINT64_C(1208455255), // VFWCVT_RTZ_X_F_V
13271 UINT64_C(1208225879), // VFWCVT_XU_F_V
13272 UINT64_C(1208258647), // VFWCVT_X_F_V
13273 UINT64_C(3959443543), // VFWMACCBF16_VF
13274 UINT64_C(3959427159), // VFWMACCBF16_VV
13275 UINT64_C(4060090459), // VFWMACC_4x4x4
13276 UINT64_C(4026552407), // VFWMACC_VF
13277 UINT64_C(4026536023), // VFWMACC_VV
13278 UINT64_C(4160770135), // VFWMSAC_VF
13279 UINT64_C(4160753751), // VFWMSAC_VV
13280 UINT64_C(3758116951), // VFWMUL_VF
13281 UINT64_C(3758100567), // VFWMUL_VV
13282 UINT64_C(4093661271), // VFWNMACC_VF
13283 UINT64_C(4093644887), // VFWNMACC_VV
13284 UINT64_C(4227878999), // VFWNMSAC_VF
13285 UINT64_C(4227862615), // VFWNMSAC_VV
13286 UINT64_C(3422556247), // VFWREDOSUM_VS
13287 UINT64_C(3288338519), // VFWREDUSUM_VS
13288 UINT64_C(3355463767), // VFWSUB_VF
13289 UINT64_C(3355447383), // VFWSUB_VV
13290 UINT64_C(3623899223), // VFWSUB_WF
13291 UINT64_C(3623882839), // VFWSUB_WV
13292 UINT64_C(2986352759), // VGHSH_VV
13293 UINT64_C(2718474359), // VGMUL_VV
13294 UINT64_C(1342742615), // VID_V
13295 UINT64_C(1342709847), // VIOTA_M
13296 UINT64_C(41963527), // VL1RE16_V
13297 UINT64_C(41967623), // VL1RE32_V
13298 UINT64_C(41971719), // VL1RE64_V
13299 UINT64_C(41943047), // VL1RE8_V
13300 UINT64_C(578834439), // VL2RE16_V
13301 UINT64_C(578838535), // VL2RE32_V
13302 UINT64_C(578842631), // VL2RE64_V
13303 UINT64_C(578813959), // VL2RE8_V
13304 UINT64_C(1652576263), // VL4RE16_V
13305 UINT64_C(1652580359), // VL4RE32_V
13306 UINT64_C(1652584455), // VL4RE64_V
13307 UINT64_C(1652555783), // VL4RE8_V
13308 UINT64_C(3800059911), // VL8RE16_V
13309 UINT64_C(3800064007), // VL8RE32_V
13310 UINT64_C(3800068103), // VL8RE64_V
13311 UINT64_C(3800039431), // VL8RE8_V
13312 UINT64_C(16797703), // VLE16FF_V
13313 UINT64_C(20487), // VLE16_V
13314 UINT64_C(16801799), // VLE32FF_V
13315 UINT64_C(24583), // VLE32_V
13316 UINT64_C(16805895), // VLE64FF_V
13317 UINT64_C(28679), // VLE64_V
13318 UINT64_C(16777223), // VLE8FF_V
13319 UINT64_C(7), // VLE8_V
13320 UINT64_C(45088775), // VLM_V
13321 UINT64_C(201347079), // VLOXEI16_V
13322 UINT64_C(201351175), // VLOXEI32_V
13323 UINT64_C(201355271), // VLOXEI64_V
13324 UINT64_C(201326599), // VLOXEI8_V
13325 UINT64_C(738217991), // VLOXSEG2EI16_V
13326 UINT64_C(738222087), // VLOXSEG2EI32_V
13327 UINT64_C(738226183), // VLOXSEG2EI64_V
13328 UINT64_C(738197511), // VLOXSEG2EI8_V
13329 UINT64_C(1275088903), // VLOXSEG3EI16_V
13330 UINT64_C(1275092999), // VLOXSEG3EI32_V
13331 UINT64_C(1275097095), // VLOXSEG3EI64_V
13332 UINT64_C(1275068423), // VLOXSEG3EI8_V
13333 UINT64_C(1811959815), // VLOXSEG4EI16_V
13334 UINT64_C(1811963911), // VLOXSEG4EI32_V
13335 UINT64_C(1811968007), // VLOXSEG4EI64_V
13336 UINT64_C(1811939335), // VLOXSEG4EI8_V
13337 UINT64_C(2348830727), // VLOXSEG5EI16_V
13338 UINT64_C(2348834823), // VLOXSEG5EI32_V
13339 UINT64_C(2348838919), // VLOXSEG5EI64_V
13340 UINT64_C(2348810247), // VLOXSEG5EI8_V
13341 UINT64_C(2885701639), // VLOXSEG6EI16_V
13342 UINT64_C(2885705735), // VLOXSEG6EI32_V
13343 UINT64_C(2885709831), // VLOXSEG6EI64_V
13344 UINT64_C(2885681159), // VLOXSEG6EI8_V
13345 UINT64_C(3422572551), // VLOXSEG7EI16_V
13346 UINT64_C(3422576647), // VLOXSEG7EI32_V
13347 UINT64_C(3422580743), // VLOXSEG7EI64_V
13348 UINT64_C(3422552071), // VLOXSEG7EI8_V
13349 UINT64_C(3959443463), // VLOXSEG8EI16_V
13350 UINT64_C(3959447559), // VLOXSEG8EI32_V
13351 UINT64_C(3959451655), // VLOXSEG8EI64_V
13352 UINT64_C(3959422983), // VLOXSEG8EI8_V
13353 UINT64_C(134238215), // VLSE16_V
13354 UINT64_C(134242311), // VLSE32_V
13355 UINT64_C(134246407), // VLSE64_V
13356 UINT64_C(134217735), // VLSE8_V
13357 UINT64_C(553668615), // VLSEG2E16FF_V
13358 UINT64_C(536891399), // VLSEG2E16_V
13359 UINT64_C(553672711), // VLSEG2E32FF_V
13360 UINT64_C(536895495), // VLSEG2E32_V
13361 UINT64_C(553676807), // VLSEG2E64FF_V
13362 UINT64_C(536899591), // VLSEG2E64_V
13363 UINT64_C(553648135), // VLSEG2E8FF_V
13364 UINT64_C(536870919), // VLSEG2E8_V
13365 UINT64_C(1090539527), // VLSEG3E16FF_V
13366 UINT64_C(1073762311), // VLSEG3E16_V
13367 UINT64_C(1090543623), // VLSEG3E32FF_V
13368 UINT64_C(1073766407), // VLSEG3E32_V
13369 UINT64_C(1090547719), // VLSEG3E64FF_V
13370 UINT64_C(1073770503), // VLSEG3E64_V
13371 UINT64_C(1090519047), // VLSEG3E8FF_V
13372 UINT64_C(1073741831), // VLSEG3E8_V
13373 UINT64_C(1627410439), // VLSEG4E16FF_V
13374 UINT64_C(1610633223), // VLSEG4E16_V
13375 UINT64_C(1627414535), // VLSEG4E32FF_V
13376 UINT64_C(1610637319), // VLSEG4E32_V
13377 UINT64_C(1627418631), // VLSEG4E64FF_V
13378 UINT64_C(1610641415), // VLSEG4E64_V
13379 UINT64_C(1627389959), // VLSEG4E8FF_V
13380 UINT64_C(1610612743), // VLSEG4E8_V
13381 UINT64_C(2164281351), // VLSEG5E16FF_V
13382 UINT64_C(2147504135), // VLSEG5E16_V
13383 UINT64_C(2164285447), // VLSEG5E32FF_V
13384 UINT64_C(2147508231), // VLSEG5E32_V
13385 UINT64_C(2164289543), // VLSEG5E64FF_V
13386 UINT64_C(2147512327), // VLSEG5E64_V
13387 UINT64_C(2164260871), // VLSEG5E8FF_V
13388 UINT64_C(2147483655), // VLSEG5E8_V
13389 UINT64_C(2701152263), // VLSEG6E16FF_V
13390 UINT64_C(2684375047), // VLSEG6E16_V
13391 UINT64_C(2701156359), // VLSEG6E32FF_V
13392 UINT64_C(2684379143), // VLSEG6E32_V
13393 UINT64_C(2701160455), // VLSEG6E64FF_V
13394 UINT64_C(2684383239), // VLSEG6E64_V
13395 UINT64_C(2701131783), // VLSEG6E8FF_V
13396 UINT64_C(2684354567), // VLSEG6E8_V
13397 UINT64_C(3238023175), // VLSEG7E16FF_V
13398 UINT64_C(3221245959), // VLSEG7E16_V
13399 UINT64_C(3238027271), // VLSEG7E32FF_V
13400 UINT64_C(3221250055), // VLSEG7E32_V
13401 UINT64_C(3238031367), // VLSEG7E64FF_V
13402 UINT64_C(3221254151), // VLSEG7E64_V
13403 UINT64_C(3238002695), // VLSEG7E8FF_V
13404 UINT64_C(3221225479), // VLSEG7E8_V
13405 UINT64_C(3774894087), // VLSEG8E16FF_V
13406 UINT64_C(3758116871), // VLSEG8E16_V
13407 UINT64_C(3774898183), // VLSEG8E32FF_V
13408 UINT64_C(3758120967), // VLSEG8E32_V
13409 UINT64_C(3774902279), // VLSEG8E64FF_V
13410 UINT64_C(3758125063), // VLSEG8E64_V
13411 UINT64_C(3774873607), // VLSEG8E8FF_V
13412 UINT64_C(3758096391), // VLSEG8E8_V
13413 UINT64_C(671109127), // VLSSEG2E16_V
13414 UINT64_C(671113223), // VLSSEG2E32_V
13415 UINT64_C(671117319), // VLSSEG2E64_V
13416 UINT64_C(671088647), // VLSSEG2E8_V
13417 UINT64_C(1207980039), // VLSSEG3E16_V
13418 UINT64_C(1207984135), // VLSSEG3E32_V
13419 UINT64_C(1207988231), // VLSSEG3E64_V
13420 UINT64_C(1207959559), // VLSSEG3E8_V
13421 UINT64_C(1744850951), // VLSSEG4E16_V
13422 UINT64_C(1744855047), // VLSSEG4E32_V
13423 UINT64_C(1744859143), // VLSSEG4E64_V
13424 UINT64_C(1744830471), // VLSSEG4E8_V
13425 UINT64_C(2281721863), // VLSSEG5E16_V
13426 UINT64_C(2281725959), // VLSSEG5E32_V
13427 UINT64_C(2281730055), // VLSSEG5E64_V
13428 UINT64_C(2281701383), // VLSSEG5E8_V
13429 UINT64_C(2818592775), // VLSSEG6E16_V
13430 UINT64_C(2818596871), // VLSSEG6E32_V
13431 UINT64_C(2818600967), // VLSSEG6E64_V
13432 UINT64_C(2818572295), // VLSSEG6E8_V
13433 UINT64_C(3355463687), // VLSSEG7E16_V
13434 UINT64_C(3355467783), // VLSSEG7E32_V
13435 UINT64_C(3355471879), // VLSSEG7E64_V
13436 UINT64_C(3355443207), // VLSSEG7E8_V
13437 UINT64_C(3892334599), // VLSSEG8E16_V
13438 UINT64_C(3892338695), // VLSSEG8E32_V
13439 UINT64_C(3892342791), // VLSSEG8E64_V
13440 UINT64_C(3892314119), // VLSSEG8E8_V
13441 UINT64_C(67129351), // VLUXEI16_V
13442 UINT64_C(67133447), // VLUXEI32_V
13443 UINT64_C(67137543), // VLUXEI64_V
13444 UINT64_C(67108871), // VLUXEI8_V
13445 UINT64_C(604000263), // VLUXSEG2EI16_V
13446 UINT64_C(604004359), // VLUXSEG2EI32_V
13447 UINT64_C(604008455), // VLUXSEG2EI64_V
13448 UINT64_C(603979783), // VLUXSEG2EI8_V
13449 UINT64_C(1140871175), // VLUXSEG3EI16_V
13450 UINT64_C(1140875271), // VLUXSEG3EI32_V
13451 UINT64_C(1140879367), // VLUXSEG3EI64_V
13452 UINT64_C(1140850695), // VLUXSEG3EI8_V
13453 UINT64_C(1677742087), // VLUXSEG4EI16_V
13454 UINT64_C(1677746183), // VLUXSEG4EI32_V
13455 UINT64_C(1677750279), // VLUXSEG4EI64_V
13456 UINT64_C(1677721607), // VLUXSEG4EI8_V
13457 UINT64_C(2214612999), // VLUXSEG5EI16_V
13458 UINT64_C(2214617095), // VLUXSEG5EI32_V
13459 UINT64_C(2214621191), // VLUXSEG5EI64_V
13460 UINT64_C(2214592519), // VLUXSEG5EI8_V
13461 UINT64_C(2751483911), // VLUXSEG6EI16_V
13462 UINT64_C(2751488007), // VLUXSEG6EI32_V
13463 UINT64_C(2751492103), // VLUXSEG6EI64_V
13464 UINT64_C(2751463431), // VLUXSEG6EI8_V
13465 UINT64_C(3288354823), // VLUXSEG7EI16_V
13466 UINT64_C(3288358919), // VLUXSEG7EI32_V
13467 UINT64_C(3288363015), // VLUXSEG7EI64_V
13468 UINT64_C(3288334343), // VLUXSEG7EI8_V
13469 UINT64_C(3825225735), // VLUXSEG8EI16_V
13470 UINT64_C(3825229831), // VLUXSEG8EI32_V
13471 UINT64_C(3825233927), // VLUXSEG8EI64_V
13472 UINT64_C(3825205255), // VLUXSEG8EI8_V
13473 UINT64_C(3019907159), // VMACC_VV
13474 UINT64_C(3019923543), // VMACC_VX
13475 UINT64_C(1174417495), // VMADC_VI
13476 UINT64_C(1140863063), // VMADC_VIM
13477 UINT64_C(1174405207), // VMADC_VV
13478 UINT64_C(1140850775), // VMADC_VVM
13479 UINT64_C(1174421591), // VMADC_VX
13480 UINT64_C(1140867159), // VMADC_VXM
13481 UINT64_C(2751471703), // VMADD_VV
13482 UINT64_C(2751488087), // VMADD_VX
13483 UINT64_C(1644175447), // VMANDN_MM
13484 UINT64_C(1711284311), // VMAND_MM
13485 UINT64_C(402653271), // VMAXU_VV
13486 UINT64_C(402669655), // VMAXU_VX
13487 UINT64_C(469762135), // VMAX_VV
13488 UINT64_C(469778519), // VMAX_VX
13489 UINT64_C(1543516247), // VMERGE_VIM
13490 UINT64_C(1543503959), // VMERGE_VVM
13491 UINT64_C(1543520343), // VMERGE_VXM
13492 UINT64_C(1610633303), // VMFEQ_VF
13493 UINT64_C(1610616919), // VMFEQ_VV
13494 UINT64_C(2080395351), // VMFGE_VF
13495 UINT64_C(1946177623), // VMFGT_VF
13496 UINT64_C(1677742167), // VMFLE_VF
13497 UINT64_C(1677725783), // VMFLE_VV
13498 UINT64_C(1811959895), // VMFLT_VF
13499 UINT64_C(1811943511), // VMFLT_VV
13500 UINT64_C(1879068759), // VMFNE_VF
13501 UINT64_C(1879052375), // VMFNE_VV
13502 UINT64_C(268435543), // VMINU_VV
13503 UINT64_C(268451927), // VMINU_VX
13504 UINT64_C(335544407), // VMIN_VV
13505 UINT64_C(335560791), // VMIN_VX
13506 UINT64_C(1979719767), // VMNAND_MM
13507 UINT64_C(2046828631), // VMNOR_MM
13508 UINT64_C(1912610903), // VMORN_MM
13509 UINT64_C(1778393175), // VMOR_MM
13510 UINT64_C(1308622935), // VMSBC_VV
13511 UINT64_C(1275068503), // VMSBC_VVM
13512 UINT64_C(1308639319), // VMSBC_VX
13513 UINT64_C(1275084887), // VMSBC_VXM
13514 UINT64_C(1342218327), // VMSBF_M
13515 UINT64_C(1610625111), // VMSEQ_VI
13516 UINT64_C(1610612823), // VMSEQ_VV
13517 UINT64_C(1610629207), // VMSEQ_VX
13518 UINT64_C(2013278295), // VMSGTU_VI
13519 UINT64_C(2013282391), // VMSGTU_VX
13520 UINT64_C(2080387159), // VMSGT_VI
13521 UINT64_C(2080391255), // VMSGT_VX
13522 UINT64_C(1342283863), // VMSIF_M
13523 UINT64_C(1879060567), // VMSLEU_VI
13524 UINT64_C(1879048279), // VMSLEU_VV
13525 UINT64_C(1879064663), // VMSLEU_VX
13526 UINT64_C(1946169431), // VMSLE_VI
13527 UINT64_C(1946157143), // VMSLE_VV
13528 UINT64_C(1946173527), // VMSLE_VX
13529 UINT64_C(1744830551), // VMSLTU_VV
13530 UINT64_C(1744846935), // VMSLTU_VX
13531 UINT64_C(1811939415), // VMSLT_VV
13532 UINT64_C(1811955799), // VMSLT_VX
13533 UINT64_C(1677733975), // VMSNE_VI
13534 UINT64_C(1677721687), // VMSNE_VV
13535 UINT64_C(1677738071), // VMSNE_VX
13536 UINT64_C(1342251095), // VMSOF_M
13537 UINT64_C(2550145111), // VMULHSU_VV
13538 UINT64_C(2550161495), // VMULHSU_VX
13539 UINT64_C(2415927383), // VMULHU_VV
13540 UINT64_C(2415943767), // VMULHU_VX
13541 UINT64_C(2617253975), // VMULH_VV
13542 UINT64_C(2617270359), // VMULH_VX
13543 UINT64_C(2483036247), // VMUL_VV
13544 UINT64_C(2483052631), // VMUL_VX
13545 UINT64_C(2650812503), // VMV1R_V
13546 UINT64_C(2650845271), // VMV2R_V
13547 UINT64_C(2650910807), // VMV4R_V
13548 UINT64_C(2651041879), // VMV8R_V
13549 UINT64_C(1107320919), // VMV_S_X
13550 UINT64_C(1577070679), // VMV_V_I
13551 UINT64_C(1577058391), // VMV_V_V
13552 UINT64_C(1577074775), // VMV_V_X
13553 UINT64_C(1107304535), // VMV_X_S
13554 UINT64_C(2113937495), // VMXNOR_MM
13555 UINT64_C(1845502039), // VMXOR_MM
13556 UINT64_C(3087020119), // VNCLIPU_WI
13557 UINT64_C(3087007831), // VNCLIPU_WV
13558 UINT64_C(3087024215), // VNCLIPU_WX
13559 UINT64_C(3154128983), // VNCLIP_WI
13560 UINT64_C(3154116695), // VNCLIP_WV
13561 UINT64_C(3154133079), // VNCLIP_WX
13562 UINT64_C(3154124887), // VNMSAC_VV
13563 UINT64_C(3154141271), // VNMSAC_VX
13564 UINT64_C(2885689431), // VNMSUB_VV
13565 UINT64_C(2885705815), // VNMSUB_VX
13566 UINT64_C(3019911255), // VNSRA_WI
13567 UINT64_C(3019898967), // VNSRA_WV
13568 UINT64_C(3019915351), // VNSRA_WX
13569 UINT64_C(2952802391), // VNSRL_WI
13570 UINT64_C(2952790103), // VNSRL_WV
13571 UINT64_C(2952806487), // VNSRL_WX
13572 UINT64_C(671101015), // VOR_VI
13573 UINT64_C(671088727), // VOR_VV
13574 UINT64_C(671105111), // VOR_VX
13575 UINT64_C(3187679323), // VQMACCSU_2x8x2
13576 UINT64_C(4261421147), // VQMACCSU_4x8x4
13577 UINT64_C(3120570459), // VQMACCUS_2x8x2
13578 UINT64_C(4194312283), // VQMACCUS_4x8x4
13579 UINT64_C(2986352731), // VQMACCU_2x8x2
13580 UINT64_C(4060094555), // VQMACCU_4x8x4
13581 UINT64_C(3053461595), // VQMACC_2x8x2
13582 UINT64_C(4127203419), // VQMACC_4x8x4
13583 UINT64_C(67117143), // VREDAND_VS
13584 UINT64_C(402661463), // VREDMAXU_VS
13585 UINT64_C(469770327), // VREDMAX_VS
13586 UINT64_C(268443735), // VREDMINU_VS
13587 UINT64_C(335552599), // VREDMIN_VS
13588 UINT64_C(134226007), // VREDOR_VS
13589 UINT64_C(8279), // VREDSUM_VS
13590 UINT64_C(201334871), // VREDXOR_VS
13591 UINT64_C(2281709655), // VREMU_VV
13592 UINT64_C(2281726039), // VREMU_VX
13593 UINT64_C(2348818519), // VREM_VV
13594 UINT64_C(2348834903), // VREM_VX
13595 UINT64_C(1208262743), // VREV8_V
13596 UINT64_C(939524183), // VRGATHEREI16_VV
13597 UINT64_C(805318743), // VRGATHER_VI
13598 UINT64_C(805306455), // VRGATHER_VV
13599 UINT64_C(805322839), // VRGATHER_VX
13600 UINT64_C(1409286231), // VROL_VV
13601 UINT64_C(1409302615), // VROL_VX
13602 UINT64_C(1342189655), // VROR_VI
13603 UINT64_C(1342177367), // VROR_VV
13604 UINT64_C(1342193751), // VROR_VX
13605 UINT64_C(201338967), // VRSUB_VI
13606 UINT64_C(201343063), // VRSUB_VX
13607 UINT64_C(41943079), // VS1R_V
13608 UINT64_C(578813991), // VS2R_V
13609 UINT64_C(1652555815), // VS4R_V
13610 UINT64_C(3800039463), // VS8R_V
13611 UINT64_C(2147496023), // VSADDU_VI
13612 UINT64_C(2147483735), // VSADDU_VV
13613 UINT64_C(2147500119), // VSADDU_VX
13614 UINT64_C(2214604887), // VSADD_VI
13615 UINT64_C(2214592599), // VSADD_VV
13616 UINT64_C(2214608983), // VSADD_VX
13617 UINT64_C(1207959639), // VSBC_VVM
13618 UINT64_C(1207976023), // VSBC_VXM
13619 UINT64_C(20519), // VSE16_V
13620 UINT64_C(24615), // VSE32_V
13621 UINT64_C(28711), // VSE64_V
13622 UINT64_C(39), // VSE8_V
13623 UINT64_C(3221254231), // VSETIVLI
13624 UINT64_C(2147512407), // VSETVL
13625 UINT64_C(28759), // VSETVLI
13626 UINT64_C(1208197207), // VSEXT_VF2
13627 UINT64_C(1208131671), // VSEXT_VF4
13628 UINT64_C(1208066135), // VSEXT_VF8
13629 UINT64_C(3120570487), // VSHA2CH_VV
13630 UINT64_C(3187679351), // VSHA2CL_VV
13631 UINT64_C(3053461623), // VSHA2MS_VV
13632 UINT64_C(1006657623), // VSLIDE1DOWN_VX
13633 UINT64_C(939548759), // VSLIDE1UP_VX
13634 UINT64_C(1006645335), // VSLIDEDOWN_VI
13635 UINT64_C(1006649431), // VSLIDEDOWN_VX
13636 UINT64_C(939536471), // VSLIDEUP_VI
13637 UINT64_C(939540567), // VSLIDEUP_VX
13638 UINT64_C(2483040343), // VSLL_VI
13639 UINT64_C(2483028055), // VSLL_VV
13640 UINT64_C(2483044439), // VSLL_VX
13641 UINT64_C(2919243895), // VSM3C_VI
13642 UINT64_C(2181046391), // VSM3ME_VV
13643 UINT64_C(2248155255), // VSM4K_VI
13644 UINT64_C(2785550455), // VSM4R_VS
13645 UINT64_C(2718441591), // VSM4R_VV
13646 UINT64_C(2617245783), // VSMUL_VV
13647 UINT64_C(2617262167), // VSMUL_VX
13648 UINT64_C(45088807), // VSM_V
13649 UINT64_C(201347111), // VSOXEI16_V
13650 UINT64_C(201351207), // VSOXEI32_V
13651 UINT64_C(201355303), // VSOXEI64_V
13652 UINT64_C(201326631), // VSOXEI8_V
13653 UINT64_C(738218023), // VSOXSEG2EI16_V
13654 UINT64_C(738222119), // VSOXSEG2EI32_V
13655 UINT64_C(738226215), // VSOXSEG2EI64_V
13656 UINT64_C(738197543), // VSOXSEG2EI8_V
13657 UINT64_C(1275088935), // VSOXSEG3EI16_V
13658 UINT64_C(1275093031), // VSOXSEG3EI32_V
13659 UINT64_C(1275097127), // VSOXSEG3EI64_V
13660 UINT64_C(1275068455), // VSOXSEG3EI8_V
13661 UINT64_C(1811959847), // VSOXSEG4EI16_V
13662 UINT64_C(1811963943), // VSOXSEG4EI32_V
13663 UINT64_C(1811968039), // VSOXSEG4EI64_V
13664 UINT64_C(1811939367), // VSOXSEG4EI8_V
13665 UINT64_C(2348830759), // VSOXSEG5EI16_V
13666 UINT64_C(2348834855), // VSOXSEG5EI32_V
13667 UINT64_C(2348838951), // VSOXSEG5EI64_V
13668 UINT64_C(2348810279), // VSOXSEG5EI8_V
13669 UINT64_C(2885701671), // VSOXSEG6EI16_V
13670 UINT64_C(2885705767), // VSOXSEG6EI32_V
13671 UINT64_C(2885709863), // VSOXSEG6EI64_V
13672 UINT64_C(2885681191), // VSOXSEG6EI8_V
13673 UINT64_C(3422572583), // VSOXSEG7EI16_V
13674 UINT64_C(3422576679), // VSOXSEG7EI32_V
13675 UINT64_C(3422580775), // VSOXSEG7EI64_V
13676 UINT64_C(3422552103), // VSOXSEG7EI8_V
13677 UINT64_C(3959443495), // VSOXSEG8EI16_V
13678 UINT64_C(3959447591), // VSOXSEG8EI32_V
13679 UINT64_C(3959451687), // VSOXSEG8EI64_V
13680 UINT64_C(3959423015), // VSOXSEG8EI8_V
13681 UINT64_C(2751475799), // VSRA_VI
13682 UINT64_C(2751463511), // VSRA_VV
13683 UINT64_C(2751479895), // VSRA_VX
13684 UINT64_C(2684366935), // VSRL_VI
13685 UINT64_C(2684354647), // VSRL_VV
13686 UINT64_C(2684371031), // VSRL_VX
13687 UINT64_C(134238247), // VSSE16_V
13688 UINT64_C(134242343), // VSSE32_V
13689 UINT64_C(134246439), // VSSE64_V
13690 UINT64_C(134217767), // VSSE8_V
13691 UINT64_C(536891431), // VSSEG2E16_V
13692 UINT64_C(536895527), // VSSEG2E32_V
13693 UINT64_C(536899623), // VSSEG2E64_V
13694 UINT64_C(536870951), // VSSEG2E8_V
13695 UINT64_C(1073762343), // VSSEG3E16_V
13696 UINT64_C(1073766439), // VSSEG3E32_V
13697 UINT64_C(1073770535), // VSSEG3E64_V
13698 UINT64_C(1073741863), // VSSEG3E8_V
13699 UINT64_C(1610633255), // VSSEG4E16_V
13700 UINT64_C(1610637351), // VSSEG4E32_V
13701 UINT64_C(1610641447), // VSSEG4E64_V
13702 UINT64_C(1610612775), // VSSEG4E8_V
13703 UINT64_C(2147504167), // VSSEG5E16_V
13704 UINT64_C(2147508263), // VSSEG5E32_V
13705 UINT64_C(2147512359), // VSSEG5E64_V
13706 UINT64_C(2147483687), // VSSEG5E8_V
13707 UINT64_C(2684375079), // VSSEG6E16_V
13708 UINT64_C(2684379175), // VSSEG6E32_V
13709 UINT64_C(2684383271), // VSSEG6E64_V
13710 UINT64_C(2684354599), // VSSEG6E8_V
13711 UINT64_C(3221245991), // VSSEG7E16_V
13712 UINT64_C(3221250087), // VSSEG7E32_V
13713 UINT64_C(3221254183), // VSSEG7E64_V
13714 UINT64_C(3221225511), // VSSEG7E8_V
13715 UINT64_C(3758116903), // VSSEG8E16_V
13716 UINT64_C(3758120999), // VSSEG8E32_V
13717 UINT64_C(3758125095), // VSSEG8E64_V
13718 UINT64_C(3758096423), // VSSEG8E8_V
13719 UINT64_C(2885693527), // VSSRA_VI
13720 UINT64_C(2885681239), // VSSRA_VV
13721 UINT64_C(2885697623), // VSSRA_VX
13722 UINT64_C(2818584663), // VSSRL_VI
13723 UINT64_C(2818572375), // VSSRL_VV
13724 UINT64_C(2818588759), // VSSRL_VX
13725 UINT64_C(671109159), // VSSSEG2E16_V
13726 UINT64_C(671113255), // VSSSEG2E32_V
13727 UINT64_C(671117351), // VSSSEG2E64_V
13728 UINT64_C(671088679), // VSSSEG2E8_V
13729 UINT64_C(1207980071), // VSSSEG3E16_V
13730 UINT64_C(1207984167), // VSSSEG3E32_V
13731 UINT64_C(1207988263), // VSSSEG3E64_V
13732 UINT64_C(1207959591), // VSSSEG3E8_V
13733 UINT64_C(1744850983), // VSSSEG4E16_V
13734 UINT64_C(1744855079), // VSSSEG4E32_V
13735 UINT64_C(1744859175), // VSSSEG4E64_V
13736 UINT64_C(1744830503), // VSSSEG4E8_V
13737 UINT64_C(2281721895), // VSSSEG5E16_V
13738 UINT64_C(2281725991), // VSSSEG5E32_V
13739 UINT64_C(2281730087), // VSSSEG5E64_V
13740 UINT64_C(2281701415), // VSSSEG5E8_V
13741 UINT64_C(2818592807), // VSSSEG6E16_V
13742 UINT64_C(2818596903), // VSSSEG6E32_V
13743 UINT64_C(2818600999), // VSSSEG6E64_V
13744 UINT64_C(2818572327), // VSSSEG6E8_V
13745 UINT64_C(3355463719), // VSSSEG7E16_V
13746 UINT64_C(3355467815), // VSSSEG7E32_V
13747 UINT64_C(3355471911), // VSSSEG7E64_V
13748 UINT64_C(3355443239), // VSSSEG7E8_V
13749 UINT64_C(3892334631), // VSSSEG8E16_V
13750 UINT64_C(3892338727), // VSSSEG8E32_V
13751 UINT64_C(3892342823), // VSSSEG8E64_V
13752 UINT64_C(3892314151), // VSSSEG8E8_V
13753 UINT64_C(2281701463), // VSSUBU_VV
13754 UINT64_C(2281717847), // VSSUBU_VX
13755 UINT64_C(2348810327), // VSSUB_VV
13756 UINT64_C(2348826711), // VSSUB_VX
13757 UINT64_C(134217815), // VSUB_VV
13758 UINT64_C(134234199), // VSUB_VX
13759 UINT64_C(67129383), // VSUXEI16_V
13760 UINT64_C(67133479), // VSUXEI32_V
13761 UINT64_C(67137575), // VSUXEI64_V
13762 UINT64_C(67108903), // VSUXEI8_V
13763 UINT64_C(604000295), // VSUXSEG2EI16_V
13764 UINT64_C(604004391), // VSUXSEG2EI32_V
13765 UINT64_C(604008487), // VSUXSEG2EI64_V
13766 UINT64_C(603979815), // VSUXSEG2EI8_V
13767 UINT64_C(1140871207), // VSUXSEG3EI16_V
13768 UINT64_C(1140875303), // VSUXSEG3EI32_V
13769 UINT64_C(1140879399), // VSUXSEG3EI64_V
13770 UINT64_C(1140850727), // VSUXSEG3EI8_V
13771 UINT64_C(1677742119), // VSUXSEG4EI16_V
13772 UINT64_C(1677746215), // VSUXSEG4EI32_V
13773 UINT64_C(1677750311), // VSUXSEG4EI64_V
13774 UINT64_C(1677721639), // VSUXSEG4EI8_V
13775 UINT64_C(2214613031), // VSUXSEG5EI16_V
13776 UINT64_C(2214617127), // VSUXSEG5EI32_V
13777 UINT64_C(2214621223), // VSUXSEG5EI64_V
13778 UINT64_C(2214592551), // VSUXSEG5EI8_V
13779 UINT64_C(2751483943), // VSUXSEG6EI16_V
13780 UINT64_C(2751488039), // VSUXSEG6EI32_V
13781 UINT64_C(2751492135), // VSUXSEG6EI64_V
13782 UINT64_C(2751463463), // VSUXSEG6EI8_V
13783 UINT64_C(3288354855), // VSUXSEG7EI16_V
13784 UINT64_C(3288358951), // VSUXSEG7EI32_V
13785 UINT64_C(3288363047), // VSUXSEG7EI64_V
13786 UINT64_C(3288334375), // VSUXSEG7EI8_V
13787 UINT64_C(3825225767), // VSUXSEG8EI16_V
13788 UINT64_C(3825229863), // VSUXSEG8EI32_V
13789 UINT64_C(3825233959), // VSUXSEG8EI64_V
13790 UINT64_C(3825205287), // VSUXSEG8EI8_V
13791 UINT64_C(24699), // VT_MASKC
13792 UINT64_C(28795), // VT_MASKCN
13793 UINT64_C(3221233751), // VWADDU_VV
13794 UINT64_C(3221250135), // VWADDU_VX
13795 UINT64_C(3489669207), // VWADDU_WV
13796 UINT64_C(3489685591), // VWADDU_WX
13797 UINT64_C(3288342615), // VWADD_VV
13798 UINT64_C(3288358999), // VWADD_VX
13799 UINT64_C(3556778071), // VWADD_WV
13800 UINT64_C(3556794455), // VWADD_WX
13801 UINT64_C(4227866711), // VWMACCSU_VV
13802 UINT64_C(4227883095), // VWMACCSU_VX
13803 UINT64_C(4160774231), // VWMACCUS_VX
13804 UINT64_C(4026540119), // VWMACCU_VV
13805 UINT64_C(4026556503), // VWMACCU_VX
13806 UINT64_C(4093648983), // VWMACC_VV
13807 UINT64_C(4093665367), // VWMACC_VX
13808 UINT64_C(3892322391), // VWMULSU_VV
13809 UINT64_C(3892338775), // VWMULSU_VX
13810 UINT64_C(3758104663), // VWMULU_VV
13811 UINT64_C(3758121047), // VWMULU_VX
13812 UINT64_C(3959431255), // VWMUL_VV
13813 UINT64_C(3959447639), // VWMUL_VX
13814 UINT64_C(3221225559), // VWREDSUMU_VS
13815 UINT64_C(3288334423), // VWREDSUM_VS
13816 UINT64_C(3556782167), // VWSLL_VI
13817 UINT64_C(3556769879), // VWSLL_VV
13818 UINT64_C(3556786263), // VWSLL_VX
13819 UINT64_C(3355451479), // VWSUBU_VV
13820 UINT64_C(3355467863), // VWSUBU_VX
13821 UINT64_C(3623886935), // VWSUBU_WV
13822 UINT64_C(3623903319), // VWSUBU_WX
13823 UINT64_C(3422560343), // VWSUB_VV
13824 UINT64_C(3422576727), // VWSUB_VX
13825 UINT64_C(3690995799), // VWSUB_WV
13826 UINT64_C(3691012183), // VWSUB_WX
13827 UINT64_C(738209879), // VXOR_VI
13828 UINT64_C(738197591), // VXOR_VV
13829 UINT64_C(738213975), // VXOR_VX
13830 UINT64_C(1208164439), // VZEXT_VF2
13831 UINT64_C(1208098903), // VZEXT_VF4
13832 UINT64_C(1208033367), // VZEXT_VF8
13833 UINT64_C(273678451), // WFI
13834 UINT64_C(13631603), // WRS_NTO
13835 UINT64_C(30408819), // WRS_STO
13836 UINT64_C(1073758259), // XNOR
13837 UINT64_C(16435), // XOR
13838 UINT64_C(16403), // XORI
13839 UINT64_C(671096883), // XPERM4
13840 UINT64_C(671105075), // XPERM8
13841 UINT64_C(134234163), // ZEXT_H_RV32
13842 UINT64_C(134234171), // ZEXT_H_RV64
13843 UINT64_C(149950483), // ZIP_RV32
13844 UINT64_C(0)
13845 };
13846 const unsigned opcode = MI.getOpcode();
13847 uint64_t Value = InstBits[opcode];
13848 uint64_t op = 0;
13849 (void)op; // suppress warning
13850 switch (opcode) {
13851 case RISCV::C_EBREAK:
13852 case RISCV::C_MOP1:
13853 case RISCV::C_MOP3:
13854 case RISCV::C_MOP5:
13855 case RISCV::C_MOP7:
13856 case RISCV::C_MOP9:
13857 case RISCV::C_MOP11:
13858 case RISCV::C_MOP13:
13859 case RISCV::C_MOP15:
13860 case RISCV::C_NOP:
13861 case RISCV::C_SSPOPCHK:
13862 case RISCV::C_SSPUSH:
13863 case RISCV::C_UNIMP:
13864 case RISCV::DRET:
13865 case RISCV::EBREAK:
13866 case RISCV::ECALL:
13867 case RISCV::FENCE_I:
13868 case RISCV::FENCE_TSO:
13869 case RISCV::MRET:
13870 case RISCV::SFENCE_INVAL_IR:
13871 case RISCV::SFENCE_W_INVAL:
13872 case RISCV::SF_CEASE:
13873 case RISCV::SRET:
13874 case RISCV::TH_DCACHE_CALL:
13875 case RISCV::TH_DCACHE_CIALL:
13876 case RISCV::TH_DCACHE_IALL:
13877 case RISCV::TH_ICACHE_IALL:
13878 case RISCV::TH_ICACHE_IALLS:
13879 case RISCV::TH_L2CACHE_CALL:
13880 case RISCV::TH_L2CACHE_CIALL:
13881 case RISCV::TH_L2CACHE_IALL:
13882 case RISCV::TH_SYNC:
13883 case RISCV::TH_SYNC_I:
13884 case RISCV::TH_SYNC_IS:
13885 case RISCV::TH_SYNC_S:
13886 case RISCV::UNIMP:
13887 case RISCV::WFI:
13888 case RISCV::WRS_NTO:
13889 case RISCV::WRS_STO: {
13890 break;
13891 }
13892 case RISCV::C_NOP_HINT: {
13893 // op: imm
13894 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
13895 Value |= (op & UINT64_C(32)) << 7;
13896 Value |= (op & UINT64_C(31)) << 2;
13897 break;
13898 }
13899 case RISCV::C_LI_HINT:
13900 case RISCV::C_LUI_HINT: {
13901 // op: imm
13902 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
13903 Value |= (op & UINT64_C(32)) << 7;
13904 Value |= (op & UINT64_C(31)) << 2;
13905 break;
13906 }
13907 case RISCV::C_LI:
13908 case RISCV::C_LUI: {
13909 // op: imm
13910 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
13911 Value |= (op & UINT64_C(32)) << 7;
13912 Value |= (op & UINT64_C(31)) << 2;
13913 // op: rd
13914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13915 op &= UINT64_C(31);
13916 op <<= 7;
13917 Value |= op;
13918 break;
13919 }
13920 case RISCV::VMV_V_I: {
13921 // op: imm
13922 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
13923 op &= UINT64_C(31);
13924 op <<= 15;
13925 Value |= op;
13926 // op: vd
13927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13928 op &= UINT64_C(31);
13929 op <<= 7;
13930 Value |= op;
13931 break;
13932 }
13933 case RISCV::C_FLDSP:
13934 case RISCV::C_LDSP: {
13935 // op: imm
13936 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
13937 Value |= (op & UINT64_C(32)) << 7;
13938 Value |= (op & UINT64_C(24)) << 2;
13939 Value |= (op & UINT64_C(448)) >> 4;
13940 // op: rd
13941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13942 op &= UINT64_C(31);
13943 op <<= 7;
13944 Value |= op;
13945 break;
13946 }
13947 case RISCV::C_FLWSP:
13948 case RISCV::C_LWSP: {
13949 // op: imm
13950 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
13951 Value |= (op & UINT64_C(32)) << 7;
13952 Value |= (op & UINT64_C(28)) << 2;
13953 Value |= (op & UINT64_C(192)) >> 4;
13954 // op: rd
13955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13956 op &= UINT64_C(31);
13957 op <<= 7;
13958 Value |= op;
13959 break;
13960 }
13961 case RISCV::C_ADDI:
13962 case RISCV::C_ADDIW: {
13963 // op: imm
13964 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
13965 Value |= (op & UINT64_C(32)) << 7;
13966 Value |= (op & UINT64_C(31)) << 2;
13967 // op: rd
13968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13969 op &= UINT64_C(31);
13970 op <<= 7;
13971 Value |= op;
13972 break;
13973 }
13974 case RISCV::C_ANDI: {
13975 // op: imm
13976 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
13977 Value |= (op & UINT64_C(32)) << 7;
13978 Value |= (op & UINT64_C(31)) << 2;
13979 // op: rs1
13980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13981 op &= UINT64_C(7);
13982 op <<= 7;
13983 Value |= op;
13984 break;
13985 }
13986 case RISCV::C_ADDI4SPN: {
13987 // op: imm
13988 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
13989 Value |= (op & UINT64_C(48)) << 7;
13990 Value |= (op & UINT64_C(960)) << 1;
13991 Value |= (op & UINT64_C(4)) << 4;
13992 Value |= (op & UINT64_C(8)) << 2;
13993 // op: rd
13994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13995 op &= UINT64_C(7);
13996 op <<= 2;
13997 Value |= op;
13998 break;
13999 }
14000 case RISCV::C_ADDI16SP: {
14001 // op: imm
14002 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14003 Value |= (op & UINT64_C(512)) << 3;
14004 Value |= (op & UINT64_C(16)) << 2;
14005 Value |= (op & UINT64_C(64)) >> 1;
14006 Value |= (op & UINT64_C(384)) >> 4;
14007 Value |= (op & UINT64_C(32)) >> 3;
14008 break;
14009 }
14010 case RISCV::C_FSDSP:
14011 case RISCV::C_SDSP: {
14012 // op: imm
14013 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14014 Value |= (op & UINT64_C(56)) << 7;
14015 Value |= (op & UINT64_C(448)) << 1;
14016 // op: rs2
14017 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14018 op &= UINT64_C(31);
14019 op <<= 2;
14020 Value |= op;
14021 break;
14022 }
14023 case RISCV::C_FSWSP:
14024 case RISCV::C_SWSP: {
14025 // op: imm
14026 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14027 Value |= (op & UINT64_C(60)) << 7;
14028 Value |= (op & UINT64_C(192)) << 1;
14029 // op: rs2
14030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14031 op &= UINT64_C(31);
14032 op <<= 2;
14033 Value |= op;
14034 break;
14035 }
14036 case RISCV::C_BEQZ:
14037 case RISCV::C_BNEZ: {
14038 // op: imm
14039 op = getImmOpValueAsr1(MI, OpNo: 1, Fixups, STI);
14040 Value |= (op & UINT64_C(128)) << 5;
14041 Value |= (op & UINT64_C(12)) << 8;
14042 Value |= (op & UINT64_C(96));
14043 Value |= (op & UINT64_C(3)) << 3;
14044 Value |= (op & UINT64_C(16)) >> 2;
14045 // op: rs1
14046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14047 op &= UINT64_C(7);
14048 op <<= 7;
14049 Value |= op;
14050 break;
14051 }
14052 case RISCV::C_SLLI_HINT: {
14053 // op: imm
14054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14055 Value |= (op & UINT64_C(32)) << 7;
14056 Value |= (op & UINT64_C(31)) << 2;
14057 break;
14058 }
14059 case RISCV::C_SLLI: {
14060 // op: imm
14061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14062 Value |= (op & UINT64_C(32)) << 7;
14063 Value |= (op & UINT64_C(31)) << 2;
14064 // op: rd
14065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14066 op &= UINT64_C(31);
14067 op <<= 7;
14068 Value |= op;
14069 break;
14070 }
14071 case RISCV::C_SRAI:
14072 case RISCV::C_SRLI: {
14073 // op: imm
14074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14075 Value |= (op & UINT64_C(32)) << 7;
14076 Value |= (op & UINT64_C(31)) << 2;
14077 // op: rs1
14078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14079 op &= UINT64_C(7);
14080 op <<= 7;
14081 Value |= op;
14082 break;
14083 }
14084 case RISCV::C_ADDI_NOP: {
14085 // op: imm
14086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14087 op &= UINT64_C(32);
14088 op <<= 7;
14089 Value |= op;
14090 // op: rd
14091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14092 op &= UINT64_C(31);
14093 op <<= 7;
14094 Value |= op;
14095 break;
14096 }
14097 case RISCV::PREFETCH_I:
14098 case RISCV::PREFETCH_R:
14099 case RISCV::PREFETCH_W: {
14100 // op: imm12
14101 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14102 op &= UINT64_C(4064);
14103 op <<= 20;
14104 Value |= op;
14105 // op: rs1
14106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14107 op &= UINT64_C(31);
14108 op <<= 15;
14109 Value |= op;
14110 break;
14111 }
14112 case RISCV::FSD:
14113 case RISCV::FSH:
14114 case RISCV::FSW:
14115 case RISCV::SB:
14116 case RISCV::SD:
14117 case RISCV::SH:
14118 case RISCV::SW: {
14119 // op: imm12
14120 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14121 Value |= (op & UINT64_C(4064)) << 20;
14122 Value |= (op & UINT64_C(31)) << 7;
14123 // op: rs2
14124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14125 op &= UINT64_C(31);
14126 op <<= 20;
14127 Value |= op;
14128 // op: rs1
14129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14130 op &= UINT64_C(31);
14131 op <<= 15;
14132 Value |= op;
14133 break;
14134 }
14135 case RISCV::CV_SB_ri_inc:
14136 case RISCV::CV_SH_ri_inc:
14137 case RISCV::CV_SW_ri_inc: {
14138 // op: imm12
14139 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
14140 Value |= (op & UINT64_C(4064)) << 20;
14141 Value |= (op & UINT64_C(31)) << 7;
14142 // op: rs2
14143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14144 op &= UINT64_C(31);
14145 op <<= 20;
14146 Value |= op;
14147 // op: rs1
14148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14149 op &= UINT64_C(31);
14150 op <<= 15;
14151 Value |= op;
14152 break;
14153 }
14154 case RISCV::CV_BEQIMM:
14155 case RISCV::CV_BNEIMM: {
14156 // op: imm12
14157 op = getImmOpValueAsr1(MI, OpNo: 2, Fixups, STI);
14158 Value |= (op & UINT64_C(2048)) << 20;
14159 Value |= (op & UINT64_C(1008)) << 21;
14160 Value |= (op & UINT64_C(15)) << 8;
14161 Value |= (op & UINT64_C(1024)) >> 3;
14162 // op: rs1
14163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14164 op &= UINT64_C(31);
14165 op <<= 15;
14166 Value |= op;
14167 // op: imm5
14168 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14169 op &= UINT64_C(31);
14170 op <<= 20;
14171 Value |= op;
14172 break;
14173 }
14174 case RISCV::BEQ:
14175 case RISCV::BGE:
14176 case RISCV::BGEU:
14177 case RISCV::BLT:
14178 case RISCV::BLTU:
14179 case RISCV::BNE: {
14180 // op: imm12
14181 op = getImmOpValueAsr1(MI, OpNo: 2, Fixups, STI);
14182 Value |= (op & UINT64_C(2048)) << 20;
14183 Value |= (op & UINT64_C(1008)) << 21;
14184 Value |= (op & UINT64_C(15)) << 8;
14185 Value |= (op & UINT64_C(1024)) >> 3;
14186 // op: rs2
14187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14188 op &= UINT64_C(31);
14189 op <<= 20;
14190 Value |= op;
14191 // op: rs1
14192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14193 op &= UINT64_C(31);
14194 op <<= 15;
14195 Value |= op;
14196 break;
14197 }
14198 case RISCV::AUIPC:
14199 case RISCV::LUI: {
14200 // op: imm20
14201 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14202 op &= UINT64_C(1048575);
14203 op <<= 12;
14204 Value |= op;
14205 // op: rd
14206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14207 op &= UINT64_C(31);
14208 op <<= 7;
14209 Value |= op;
14210 break;
14211 }
14212 case RISCV::JAL: {
14213 // op: imm20
14214 op = getImmOpValueAsr1(MI, OpNo: 1, Fixups, STI);
14215 Value |= (op & UINT64_C(524288)) << 12;
14216 Value |= (op & UINT64_C(1023)) << 21;
14217 Value |= (op & UINT64_C(1024)) << 10;
14218 Value |= (op & UINT64_C(522240)) << 1;
14219 // op: rd
14220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14221 op &= UINT64_C(31);
14222 op <<= 7;
14223 Value |= op;
14224 break;
14225 }
14226 case RISCV::CM_JALT: {
14227 // op: index
14228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14229 op &= UINT64_C(255);
14230 op <<= 2;
14231 Value |= op;
14232 break;
14233 }
14234 case RISCV::CM_JT: {
14235 // op: index
14236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14237 op &= UINT64_C(31);
14238 op <<= 2;
14239 Value |= op;
14240 break;
14241 }
14242 case RISCV::C_J:
14243 case RISCV::C_JAL: {
14244 // op: offset
14245 op = getImmOpValueAsr1(MI, OpNo: 0, Fixups, STI);
14246 Value |= (op & UINT64_C(1024)) << 2;
14247 Value |= (op & UINT64_C(8)) << 8;
14248 Value |= (op & UINT64_C(384)) << 2;
14249 Value |= (op & UINT64_C(512)) >> 1;
14250 Value |= (op & UINT64_C(32)) << 2;
14251 Value |= (op & UINT64_C(64));
14252 Value |= (op & UINT64_C(7)) << 3;
14253 Value |= (op & UINT64_C(16)) >> 2;
14254 break;
14255 }
14256 case RISCV::InsnS: {
14257 // op: opcode
14258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14259 op &= UINT64_C(127);
14260 Value |= op;
14261 // op: funct3
14262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14263 op &= UINT64_C(7);
14264 op <<= 12;
14265 Value |= op;
14266 // op: imm12
14267 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
14268 Value |= (op & UINT64_C(4064)) << 20;
14269 Value |= (op & UINT64_C(31)) << 7;
14270 // op: rs2
14271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14272 op &= UINT64_C(31);
14273 op <<= 20;
14274 Value |= op;
14275 // op: rs1
14276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14277 op &= UINT64_C(31);
14278 op <<= 15;
14279 Value |= op;
14280 break;
14281 }
14282 case RISCV::InsnB: {
14283 // op: opcode
14284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14285 op &= UINT64_C(127);
14286 Value |= op;
14287 // op: funct3
14288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14289 op &= UINT64_C(7);
14290 op <<= 12;
14291 Value |= op;
14292 // op: imm12
14293 op = getImmOpValueAsr1(MI, OpNo: 4, Fixups, STI);
14294 Value |= (op & UINT64_C(2048)) << 20;
14295 Value |= (op & UINT64_C(1008)) << 21;
14296 Value |= (op & UINT64_C(15)) << 8;
14297 Value |= (op & UINT64_C(1024)) >> 3;
14298 // op: rs2
14299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14300 op &= UINT64_C(31);
14301 op <<= 20;
14302 Value |= op;
14303 // op: rs1
14304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14305 op &= UINT64_C(31);
14306 op <<= 15;
14307 Value |= op;
14308 break;
14309 }
14310 case RISCV::InsnCJ: {
14311 // op: opcode
14312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14313 op &= UINT64_C(3);
14314 Value |= op;
14315 // op: funct3
14316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14317 op &= UINT64_C(7);
14318 op <<= 13;
14319 Value |= op;
14320 // op: imm11
14321 op = getImmOpValueAsr1(MI, OpNo: 2, Fixups, STI);
14322 Value |= (op & UINT64_C(1024)) << 2;
14323 Value |= (op & UINT64_C(8)) << 8;
14324 Value |= (op & UINT64_C(384)) << 2;
14325 Value |= (op & UINT64_C(512)) >> 1;
14326 Value |= (op & UINT64_C(32)) << 2;
14327 Value |= (op & UINT64_C(64));
14328 Value |= (op & UINT64_C(7)) << 3;
14329 Value |= (op & UINT64_C(16)) >> 2;
14330 break;
14331 }
14332 case RISCV::InsnCS: {
14333 // op: opcode
14334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14335 op &= UINT64_C(3);
14336 Value |= op;
14337 // op: funct3
14338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14339 op &= UINT64_C(7);
14340 op <<= 13;
14341 Value |= op;
14342 // op: imm5
14343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14344 Value |= (op & UINT64_C(28)) << 8;
14345 Value |= (op & UINT64_C(3)) << 5;
14346 // op: rs2
14347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14348 op &= UINT64_C(7);
14349 op <<= 2;
14350 Value |= op;
14351 // op: rs1
14352 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14353 op &= UINT64_C(7);
14354 op <<= 7;
14355 Value |= op;
14356 break;
14357 }
14358 case RISCV::InsnCSS: {
14359 // op: opcode
14360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14361 op &= UINT64_C(3);
14362 Value |= op;
14363 // op: funct3
14364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14365 op &= UINT64_C(7);
14366 op <<= 13;
14367 Value |= op;
14368 // op: imm6
14369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14370 op &= UINT64_C(63);
14371 op <<= 7;
14372 Value |= op;
14373 // op: rs2
14374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14375 op &= UINT64_C(31);
14376 op <<= 2;
14377 Value |= op;
14378 break;
14379 }
14380 case RISCV::InsnCB: {
14381 // op: opcode
14382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14383 op &= UINT64_C(3);
14384 Value |= op;
14385 // op: funct3
14386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14387 op &= UINT64_C(7);
14388 op <<= 13;
14389 Value |= op;
14390 // op: imm8
14391 op = getImmOpValueAsr1(MI, OpNo: 3, Fixups, STI);
14392 Value |= (op & UINT64_C(128)) << 5;
14393 Value |= (op & UINT64_C(12)) << 8;
14394 Value |= (op & UINT64_C(96));
14395 Value |= (op & UINT64_C(3)) << 3;
14396 Value |= (op & UINT64_C(16)) >> 2;
14397 // op: rs1
14398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14399 op &= UINT64_C(7);
14400 op <<= 7;
14401 Value |= op;
14402 break;
14403 }
14404 case RISCV::InsnR4: {
14405 // op: opcode
14406 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14407 op &= UINT64_C(127);
14408 Value |= op;
14409 // op: funct2
14410 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14411 op &= UINT64_C(3);
14412 op <<= 25;
14413 Value |= op;
14414 // op: funct3
14415 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14416 op &= UINT64_C(7);
14417 op <<= 12;
14418 Value |= op;
14419 // op: rs3
14420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
14421 op &= UINT64_C(31);
14422 op <<= 27;
14423 Value |= op;
14424 // op: rs2
14425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14426 op &= UINT64_C(31);
14427 op <<= 20;
14428 Value |= op;
14429 // op: rs1
14430 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14431 op &= UINT64_C(31);
14432 op <<= 15;
14433 Value |= op;
14434 // op: rd
14435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14436 op &= UINT64_C(31);
14437 op <<= 7;
14438 Value |= op;
14439 break;
14440 }
14441 case RISCV::InsnI:
14442 case RISCV::InsnI_Mem: {
14443 // op: opcode
14444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14445 op &= UINT64_C(127);
14446 Value |= op;
14447 // op: funct3
14448 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14449 op &= UINT64_C(7);
14450 op <<= 12;
14451 Value |= op;
14452 // op: imm12
14453 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
14454 op &= UINT64_C(4095);
14455 op <<= 20;
14456 Value |= op;
14457 // op: rs1
14458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14459 op &= UINT64_C(31);
14460 op <<= 15;
14461 Value |= op;
14462 // op: rd
14463 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14464 op &= UINT64_C(31);
14465 op <<= 7;
14466 Value |= op;
14467 break;
14468 }
14469 case RISCV::InsnR: {
14470 // op: opcode
14471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14472 op &= UINT64_C(127);
14473 Value |= op;
14474 // op: funct7
14475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14476 op &= UINT64_C(127);
14477 op <<= 25;
14478 Value |= op;
14479 // op: funct3
14480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14481 op &= UINT64_C(7);
14482 op <<= 12;
14483 Value |= op;
14484 // op: rs2
14485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14486 op &= UINT64_C(31);
14487 op <<= 20;
14488 Value |= op;
14489 // op: rs1
14490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14491 op &= UINT64_C(31);
14492 op <<= 15;
14493 Value |= op;
14494 // op: rd
14495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14496 op &= UINT64_C(31);
14497 op <<= 7;
14498 Value |= op;
14499 break;
14500 }
14501 case RISCV::InsnU: {
14502 // op: opcode
14503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14504 op &= UINT64_C(127);
14505 Value |= op;
14506 // op: imm20
14507 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14508 op &= UINT64_C(1048575);
14509 op <<= 12;
14510 Value |= op;
14511 // op: rd
14512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14513 op &= UINT64_C(31);
14514 op <<= 7;
14515 Value |= op;
14516 break;
14517 }
14518 case RISCV::InsnJ: {
14519 // op: opcode
14520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14521 op &= UINT64_C(127);
14522 Value |= op;
14523 // op: imm20
14524 op = getImmOpValueAsr1(MI, OpNo: 2, Fixups, STI);
14525 op &= UINT64_C(1048575);
14526 op <<= 12;
14527 Value |= op;
14528 // op: rd
14529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14530 op &= UINT64_C(31);
14531 op <<= 7;
14532 Value |= op;
14533 break;
14534 }
14535 case RISCV::InsnCL: {
14536 // op: opcode
14537 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14538 op &= UINT64_C(3);
14539 Value |= op;
14540 // op: funct3
14541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14542 op &= UINT64_C(7);
14543 op <<= 13;
14544 Value |= op;
14545 // op: imm5
14546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14547 Value |= (op & UINT64_C(28)) << 8;
14548 Value |= (op & UINT64_C(3)) << 5;
14549 // op: rd
14550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14551 op &= UINT64_C(7);
14552 op <<= 2;
14553 Value |= op;
14554 // op: rs1
14555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14556 op &= UINT64_C(7);
14557 op <<= 7;
14558 Value |= op;
14559 break;
14560 }
14561 case RISCV::InsnCI: {
14562 // op: opcode
14563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14564 op &= UINT64_C(3);
14565 Value |= op;
14566 // op: funct3
14567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14568 op &= UINT64_C(7);
14569 op <<= 13;
14570 Value |= op;
14571 // op: imm6
14572 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
14573 Value |= (op & UINT64_C(32)) << 7;
14574 Value |= (op & UINT64_C(31)) << 2;
14575 // op: rd
14576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14577 op &= UINT64_C(31);
14578 op <<= 7;
14579 Value |= op;
14580 break;
14581 }
14582 case RISCV::InsnCIW: {
14583 // op: opcode
14584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14585 op &= UINT64_C(3);
14586 Value |= op;
14587 // op: funct3
14588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14589 op &= UINT64_C(7);
14590 op <<= 13;
14591 Value |= op;
14592 // op: imm8
14593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14594 op &= UINT64_C(255);
14595 op <<= 5;
14596 Value |= op;
14597 // op: rd
14598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14599 op &= UINT64_C(7);
14600 op <<= 2;
14601 Value |= op;
14602 break;
14603 }
14604 case RISCV::InsnCR: {
14605 // op: opcode
14606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14607 op &= UINT64_C(3);
14608 Value |= op;
14609 // op: funct4
14610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14611 op &= UINT64_C(15);
14612 op <<= 12;
14613 Value |= op;
14614 // op: rs2
14615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14616 op &= UINT64_C(31);
14617 op <<= 2;
14618 Value |= op;
14619 // op: rd
14620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14621 op &= UINT64_C(31);
14622 op <<= 7;
14623 Value |= op;
14624 break;
14625 }
14626 case RISCV::InsnCA: {
14627 // op: opcode
14628 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14629 op &= UINT64_C(3);
14630 Value |= op;
14631 // op: funct6
14632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14633 op &= UINT64_C(63);
14634 op <<= 10;
14635 Value |= op;
14636 // op: funct2
14637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14638 op &= UINT64_C(3);
14639 op <<= 5;
14640 Value |= op;
14641 // op: rd
14642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14643 op &= UINT64_C(7);
14644 op <<= 7;
14645 Value |= op;
14646 // op: rs2
14647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14648 op &= UINT64_C(7);
14649 op <<= 2;
14650 Value |= op;
14651 break;
14652 }
14653 case RISCV::FENCE: {
14654 // op: pred
14655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14656 op &= UINT64_C(15);
14657 op <<= 24;
14658 Value |= op;
14659 // op: succ
14660 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14661 op &= UINT64_C(15);
14662 op <<= 20;
14663 Value |= op;
14664 break;
14665 }
14666 case RISCV::SSRDP: {
14667 // op: rd
14668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14669 op &= UINT64_C(31);
14670 op <<= 7;
14671 Value |= op;
14672 break;
14673 }
14674 case RISCV::CV_LBU_rr:
14675 case RISCV::CV_LB_rr:
14676 case RISCV::CV_LHU_rr:
14677 case RISCV::CV_LH_rr:
14678 case RISCV::CV_LW_rr: {
14679 // op: rd
14680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14681 op &= UINT64_C(31);
14682 op <<= 7;
14683 Value |= op;
14684 // op: cvrr
14685 op = getRegReg(MI, OpNo: 1, Fixups, STI);
14686 Value |= (op & UINT64_C(31)) << 20;
14687 Value |= (op & UINT64_C(992)) << 10;
14688 break;
14689 }
14690 case RISCV::FLI_D:
14691 case RISCV::FLI_H:
14692 case RISCV::FLI_S: {
14693 // op: rd
14694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14695 op &= UINT64_C(31);
14696 op <<= 7;
14697 Value |= op;
14698 // op: imm
14699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14700 op &= UINT64_C(31);
14701 op <<= 15;
14702 Value |= op;
14703 break;
14704 }
14705 case RISCV::C_FLD:
14706 case RISCV::C_LD: {
14707 // op: rd
14708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14709 op &= UINT64_C(7);
14710 op <<= 2;
14711 Value |= op;
14712 // op: rs1
14713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14714 op &= UINT64_C(7);
14715 op <<= 7;
14716 Value |= op;
14717 // op: imm
14718 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14719 Value |= (op & UINT64_C(56)) << 7;
14720 Value |= (op & UINT64_C(192)) >> 1;
14721 break;
14722 }
14723 case RISCV::C_FLW:
14724 case RISCV::C_LW: {
14725 // op: rd
14726 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14727 op &= UINT64_C(7);
14728 op <<= 2;
14729 Value |= op;
14730 // op: rs1
14731 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14732 op &= UINT64_C(7);
14733 op <<= 7;
14734 Value |= op;
14735 // op: imm
14736 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14737 Value |= (op & UINT64_C(56)) << 7;
14738 Value |= (op & UINT64_C(4)) << 4;
14739 Value |= (op & UINT64_C(64)) >> 1;
14740 break;
14741 }
14742 case RISCV::QK_C_LHU: {
14743 // op: rd
14744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14745 op &= UINT64_C(7);
14746 op <<= 2;
14747 Value |= op;
14748 // op: rs1
14749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14750 op &= UINT64_C(7);
14751 op <<= 7;
14752 Value |= op;
14753 // op: imm
14754 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14755 Value |= (op & UINT64_C(56)) << 7;
14756 Value |= (op & UINT64_C(6)) << 4;
14757 break;
14758 }
14759 case RISCV::C_LH:
14760 case RISCV::C_LHU: {
14761 // op: rd
14762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14763 op &= UINT64_C(7);
14764 op <<= 2;
14765 Value |= op;
14766 // op: rs1
14767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14768 op &= UINT64_C(7);
14769 op <<= 7;
14770 Value |= op;
14771 // op: imm
14772 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14773 op &= UINT64_C(2);
14774 op <<= 4;
14775 Value |= op;
14776 break;
14777 }
14778 case RISCV::QK_C_LBU: {
14779 // op: rd
14780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14781 op &= UINT64_C(7);
14782 op <<= 2;
14783 Value |= op;
14784 // op: rs1
14785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14786 op &= UINT64_C(7);
14787 op <<= 7;
14788 Value |= op;
14789 // op: imm
14790 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14791 Value |= (op & UINT64_C(1)) << 12;
14792 Value |= (op & UINT64_C(24)) << 7;
14793 Value |= (op & UINT64_C(6)) << 4;
14794 break;
14795 }
14796 case RISCV::C_LBU: {
14797 // op: rd
14798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14799 op &= UINT64_C(7);
14800 op <<= 2;
14801 Value |= op;
14802 // op: rs1
14803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14804 op &= UINT64_C(7);
14805 op <<= 7;
14806 Value |= op;
14807 // op: imm
14808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14809 Value |= (op & UINT64_C(1)) << 6;
14810 Value |= (op & UINT64_C(2)) << 4;
14811 break;
14812 }
14813 case RISCV::C_ADDI_HINT_IMM_ZERO:
14814 case RISCV::C_SLLI64_HINT: {
14815 // op: rd
14816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14817 op &= UINT64_C(31);
14818 op <<= 7;
14819 Value |= op;
14820 break;
14821 }
14822 case RISCV::C_NOT:
14823 case RISCV::C_SEXT_B:
14824 case RISCV::C_SEXT_H:
14825 case RISCV::C_SRAI64_HINT:
14826 case RISCV::C_SRLI64_HINT:
14827 case RISCV::C_ZEXT_B:
14828 case RISCV::C_ZEXT_H:
14829 case RISCV::C_ZEXT_W: {
14830 // op: rd
14831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14832 op &= UINT64_C(7);
14833 op <<= 7;
14834 Value |= op;
14835 break;
14836 }
14837 case RISCV::QK_C_LHUSP:
14838 case RISCV::QK_C_SHSP: {
14839 // op: rd_rs2
14840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14841 op &= UINT64_C(7);
14842 op <<= 2;
14843 Value |= op;
14844 // op: imm
14845 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14846 Value |= (op & UINT64_C(14)) << 7;
14847 Value |= (op & UINT64_C(16)) << 3;
14848 break;
14849 }
14850 case RISCV::QK_C_LBUSP:
14851 case RISCV::QK_C_SBSP: {
14852 // op: rd_rs2
14853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14854 op &= UINT64_C(7);
14855 op <<= 2;
14856 Value |= op;
14857 // op: imm
14858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14859 op &= UINT64_C(15);
14860 op <<= 7;
14861 Value |= op;
14862 break;
14863 }
14864 case RISCV::CM_POP:
14865 case RISCV::CM_POPRET:
14866 case RISCV::CM_POPRETZ:
14867 case RISCV::CM_PUSH: {
14868 // op: rlist
14869 op = getRlistOpValue(MI, OpNo: 0, Fixups, STI);
14870 op &= UINT64_C(15);
14871 op <<= 4;
14872 Value |= op;
14873 // op: stackadj
14874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14875 op &= UINT64_C(48);
14876 op >>= 2;
14877 Value |= op;
14878 break;
14879 }
14880 case RISCV::CBO_CLEAN:
14881 case RISCV::CBO_FLUSH:
14882 case RISCV::CBO_INVAL:
14883 case RISCV::CBO_ZERO:
14884 case RISCV::SF_CDISCARD_D_L1:
14885 case RISCV::SF_CFLUSH_D_L1:
14886 case RISCV::SSPOPCHK:
14887 case RISCV::TH_DCACHE_CIPA:
14888 case RISCV::TH_DCACHE_CISW:
14889 case RISCV::TH_DCACHE_CIVA:
14890 case RISCV::TH_DCACHE_CPA:
14891 case RISCV::TH_DCACHE_CPAL1:
14892 case RISCV::TH_DCACHE_CSW:
14893 case RISCV::TH_DCACHE_CVA:
14894 case RISCV::TH_DCACHE_CVAL1:
14895 case RISCV::TH_DCACHE_IPA:
14896 case RISCV::TH_DCACHE_ISW:
14897 case RISCV::TH_DCACHE_IVA:
14898 case RISCV::TH_ICACHE_IPA:
14899 case RISCV::TH_ICACHE_IVA: {
14900 // op: rs1
14901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14902 op &= UINT64_C(31);
14903 op <<= 15;
14904 Value |= op;
14905 break;
14906 }
14907 case RISCV::C_JALR:
14908 case RISCV::C_JR: {
14909 // op: rs1
14910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14911 op &= UINT64_C(31);
14912 op <<= 7;
14913 Value |= op;
14914 break;
14915 }
14916 case RISCV::C_MV: {
14917 // op: rs1
14918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14919 op &= UINT64_C(31);
14920 op <<= 7;
14921 Value |= op;
14922 // op: rs2
14923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14924 op &= UINT64_C(31);
14925 op <<= 2;
14926 Value |= op;
14927 break;
14928 }
14929 case RISCV::FCVTMOD_W_D:
14930 case RISCV::FCVT_BF16_S:
14931 case RISCV::FCVT_D_H:
14932 case RISCV::FCVT_D_H_IN32X:
14933 case RISCV::FCVT_D_H_INX:
14934 case RISCV::FCVT_D_L:
14935 case RISCV::FCVT_D_LU:
14936 case RISCV::FCVT_D_LU_INX:
14937 case RISCV::FCVT_D_L_INX:
14938 case RISCV::FCVT_D_S:
14939 case RISCV::FCVT_D_S_IN32X:
14940 case RISCV::FCVT_D_S_INX:
14941 case RISCV::FCVT_D_W:
14942 case RISCV::FCVT_D_WU:
14943 case RISCV::FCVT_D_WU_IN32X:
14944 case RISCV::FCVT_D_WU_INX:
14945 case RISCV::FCVT_D_W_IN32X:
14946 case RISCV::FCVT_D_W_INX:
14947 case RISCV::FCVT_H_D:
14948 case RISCV::FCVT_H_D_IN32X:
14949 case RISCV::FCVT_H_D_INX:
14950 case RISCV::FCVT_H_L:
14951 case RISCV::FCVT_H_LU:
14952 case RISCV::FCVT_H_LU_INX:
14953 case RISCV::FCVT_H_L_INX:
14954 case RISCV::FCVT_H_S:
14955 case RISCV::FCVT_H_S_INX:
14956 case RISCV::FCVT_H_W:
14957 case RISCV::FCVT_H_WU:
14958 case RISCV::FCVT_H_WU_INX:
14959 case RISCV::FCVT_H_W_INX:
14960 case RISCV::FCVT_LU_D:
14961 case RISCV::FCVT_LU_D_INX:
14962 case RISCV::FCVT_LU_H:
14963 case RISCV::FCVT_LU_H_INX:
14964 case RISCV::FCVT_LU_S:
14965 case RISCV::FCVT_LU_S_INX:
14966 case RISCV::FCVT_L_D:
14967 case RISCV::FCVT_L_D_INX:
14968 case RISCV::FCVT_L_H:
14969 case RISCV::FCVT_L_H_INX:
14970 case RISCV::FCVT_L_S:
14971 case RISCV::FCVT_L_S_INX:
14972 case RISCV::FCVT_S_BF16:
14973 case RISCV::FCVT_S_D:
14974 case RISCV::FCVT_S_D_IN32X:
14975 case RISCV::FCVT_S_D_INX:
14976 case RISCV::FCVT_S_H:
14977 case RISCV::FCVT_S_H_INX:
14978 case RISCV::FCVT_S_L:
14979 case RISCV::FCVT_S_LU:
14980 case RISCV::FCVT_S_LU_INX:
14981 case RISCV::FCVT_S_L_INX:
14982 case RISCV::FCVT_S_W:
14983 case RISCV::FCVT_S_WU:
14984 case RISCV::FCVT_S_WU_INX:
14985 case RISCV::FCVT_S_W_INX:
14986 case RISCV::FCVT_WU_D:
14987 case RISCV::FCVT_WU_D_IN32X:
14988 case RISCV::FCVT_WU_D_INX:
14989 case RISCV::FCVT_WU_H:
14990 case RISCV::FCVT_WU_H_INX:
14991 case RISCV::FCVT_WU_S:
14992 case RISCV::FCVT_WU_S_INX:
14993 case RISCV::FCVT_W_D:
14994 case RISCV::FCVT_W_D_IN32X:
14995 case RISCV::FCVT_W_D_INX:
14996 case RISCV::FCVT_W_H:
14997 case RISCV::FCVT_W_H_INX:
14998 case RISCV::FCVT_W_S:
14999 case RISCV::FCVT_W_S_INX:
15000 case RISCV::FROUNDNX_D:
15001 case RISCV::FROUNDNX_H:
15002 case RISCV::FROUNDNX_S:
15003 case RISCV::FROUND_D:
15004 case RISCV::FROUND_H:
15005 case RISCV::FROUND_S:
15006 case RISCV::FSQRT_D:
15007 case RISCV::FSQRT_D_IN32X:
15008 case RISCV::FSQRT_D_INX:
15009 case RISCV::FSQRT_H:
15010 case RISCV::FSQRT_H_INX:
15011 case RISCV::FSQRT_S:
15012 case RISCV::FSQRT_S_INX: {
15013 // op: rs1
15014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15015 op &= UINT64_C(31);
15016 op <<= 15;
15017 Value |= op;
15018 // op: frm
15019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15020 op &= UINT64_C(7);
15021 op <<= 12;
15022 Value |= op;
15023 // op: rd
15024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15025 op &= UINT64_C(31);
15026 op <<= 7;
15027 Value |= op;
15028 break;
15029 }
15030 case RISCV::AES64IM:
15031 case RISCV::BREV8:
15032 case RISCV::CLZ:
15033 case RISCV::CLZW:
15034 case RISCV::CPOP:
15035 case RISCV::CPOPW:
15036 case RISCV::CTZ:
15037 case RISCV::CTZW:
15038 case RISCV::CV_ABS:
15039 case RISCV::CV_ABS_B:
15040 case RISCV::CV_ABS_H:
15041 case RISCV::CV_CLB:
15042 case RISCV::CV_CNT:
15043 case RISCV::CV_CPLXCONJ:
15044 case RISCV::CV_EXTBS:
15045 case RISCV::CV_EXTBZ:
15046 case RISCV::CV_EXTHS:
15047 case RISCV::CV_EXTHZ:
15048 case RISCV::CV_FF1:
15049 case RISCV::CV_FL1:
15050 case RISCV::FCLASS_D:
15051 case RISCV::FCLASS_D_IN32X:
15052 case RISCV::FCLASS_D_INX:
15053 case RISCV::FCLASS_H:
15054 case RISCV::FCLASS_H_INX:
15055 case RISCV::FCLASS_S:
15056 case RISCV::FCLASS_S_INX:
15057 case RISCV::FMVH_X_D:
15058 case RISCV::FMV_D_X:
15059 case RISCV::FMV_H_X:
15060 case RISCV::FMV_W_X:
15061 case RISCV::FMV_X_D:
15062 case RISCV::FMV_X_H:
15063 case RISCV::FMV_X_W:
15064 case RISCV::FMV_X_W_FPR64:
15065 case RISCV::HLVX_HU:
15066 case RISCV::HLVX_WU:
15067 case RISCV::HLV_B:
15068 case RISCV::HLV_BU:
15069 case RISCV::HLV_D:
15070 case RISCV::HLV_H:
15071 case RISCV::HLV_HU:
15072 case RISCV::HLV_W:
15073 case RISCV::HLV_WU:
15074 case RISCV::LB_AQ:
15075 case RISCV::LB_AQ_RL:
15076 case RISCV::LD_AQ:
15077 case RISCV::LD_AQ_RL:
15078 case RISCV::LH_AQ:
15079 case RISCV::LH_AQ_RL:
15080 case RISCV::LR_D:
15081 case RISCV::LR_D_AQ:
15082 case RISCV::LR_D_AQ_RL:
15083 case RISCV::LR_D_RL:
15084 case RISCV::LR_W:
15085 case RISCV::LR_W_AQ:
15086 case RISCV::LR_W_AQ_RL:
15087 case RISCV::LR_W_RL:
15088 case RISCV::LW_AQ:
15089 case RISCV::LW_AQ_RL:
15090 case RISCV::MOPR0:
15091 case RISCV::MOPR1:
15092 case RISCV::MOPR2:
15093 case RISCV::MOPR3:
15094 case RISCV::MOPR4:
15095 case RISCV::MOPR5:
15096 case RISCV::MOPR6:
15097 case RISCV::MOPR7:
15098 case RISCV::MOPR8:
15099 case RISCV::MOPR9:
15100 case RISCV::MOPR10:
15101 case RISCV::MOPR11:
15102 case RISCV::MOPR12:
15103 case RISCV::MOPR13:
15104 case RISCV::MOPR14:
15105 case RISCV::MOPR15:
15106 case RISCV::MOPR16:
15107 case RISCV::MOPR17:
15108 case RISCV::MOPR18:
15109 case RISCV::MOPR19:
15110 case RISCV::MOPR20:
15111 case RISCV::MOPR21:
15112 case RISCV::MOPR22:
15113 case RISCV::MOPR23:
15114 case RISCV::MOPR24:
15115 case RISCV::MOPR25:
15116 case RISCV::MOPR26:
15117 case RISCV::MOPR27:
15118 case RISCV::MOPR28:
15119 case RISCV::MOPR29:
15120 case RISCV::MOPR30:
15121 case RISCV::MOPR31:
15122 case RISCV::ORC_B:
15123 case RISCV::REV8_RV32:
15124 case RISCV::REV8_RV64:
15125 case RISCV::SEXT_B:
15126 case RISCV::SEXT_H:
15127 case RISCV::SHA256SIG0:
15128 case RISCV::SHA256SIG1:
15129 case RISCV::SHA256SUM0:
15130 case RISCV::SHA256SUM1:
15131 case RISCV::SHA512SIG0:
15132 case RISCV::SHA512SIG1:
15133 case RISCV::SHA512SUM0:
15134 case RISCV::SHA512SUM1:
15135 case RISCV::SM3P0:
15136 case RISCV::SM3P1:
15137 case RISCV::TH_FF0:
15138 case RISCV::TH_FF1:
15139 case RISCV::TH_REV:
15140 case RISCV::TH_REVW:
15141 case RISCV::TH_TSTNBZ:
15142 case RISCV::UNZIP_RV32:
15143 case RISCV::ZEXT_H_RV32:
15144 case RISCV::ZEXT_H_RV64:
15145 case RISCV::ZIP_RV32: {
15146 // op: rs1
15147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15148 op &= UINT64_C(31);
15149 op <<= 15;
15150 Value |= op;
15151 // op: rd
15152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15153 op &= UINT64_C(31);
15154 op <<= 7;
15155 Value |= op;
15156 break;
15157 }
15158 case RISCV::ADDI:
15159 case RISCV::ADDIW:
15160 case RISCV::ANDI:
15161 case RISCV::CV_ELW:
15162 case RISCV::FLD:
15163 case RISCV::FLH:
15164 case RISCV::FLW:
15165 case RISCV::JALR:
15166 case RISCV::LB:
15167 case RISCV::LBU:
15168 case RISCV::LD:
15169 case RISCV::LH:
15170 case RISCV::LHU:
15171 case RISCV::LW:
15172 case RISCV::LWU:
15173 case RISCV::ORI:
15174 case RISCV::SLTI:
15175 case RISCV::SLTIU:
15176 case RISCV::XORI: {
15177 // op: rs1
15178 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15179 op &= UINT64_C(31);
15180 op <<= 15;
15181 Value |= op;
15182 // op: rd
15183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15184 op &= UINT64_C(31);
15185 op <<= 7;
15186 Value |= op;
15187 // op: imm12
15188 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15189 op &= UINT64_C(4095);
15190 op <<= 20;
15191 Value |= op;
15192 break;
15193 }
15194 case RISCV::CV_CLIP:
15195 case RISCV::CV_CLIPU: {
15196 // op: rs1
15197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15198 op &= UINT64_C(31);
15199 op <<= 15;
15200 Value |= op;
15201 // op: rd
15202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15203 op &= UINT64_C(31);
15204 op <<= 7;
15205 Value |= op;
15206 // op: imm5
15207 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15208 op &= UINT64_C(31);
15209 op <<= 20;
15210 Value |= op;
15211 break;
15212 }
15213 case RISCV::CV_ADD_SCI_B:
15214 case RISCV::CV_ADD_SCI_H:
15215 case RISCV::CV_AND_SCI_B:
15216 case RISCV::CV_AND_SCI_H:
15217 case RISCV::CV_AVG_SCI_B:
15218 case RISCV::CV_AVG_SCI_H:
15219 case RISCV::CV_CMPEQ_SCI_B:
15220 case RISCV::CV_CMPEQ_SCI_H:
15221 case RISCV::CV_CMPGE_SCI_B:
15222 case RISCV::CV_CMPGE_SCI_H:
15223 case RISCV::CV_CMPGT_SCI_B:
15224 case RISCV::CV_CMPGT_SCI_H:
15225 case RISCV::CV_CMPLE_SCI_B:
15226 case RISCV::CV_CMPLE_SCI_H:
15227 case RISCV::CV_CMPLT_SCI_B:
15228 case RISCV::CV_CMPLT_SCI_H:
15229 case RISCV::CV_CMPNE_SCI_B:
15230 case RISCV::CV_CMPNE_SCI_H:
15231 case RISCV::CV_DOTSP_SCI_B:
15232 case RISCV::CV_DOTSP_SCI_H:
15233 case RISCV::CV_DOTUSP_SCI_B:
15234 case RISCV::CV_DOTUSP_SCI_H:
15235 case RISCV::CV_MAX_SCI_B:
15236 case RISCV::CV_MAX_SCI_H:
15237 case RISCV::CV_MIN_SCI_B:
15238 case RISCV::CV_MIN_SCI_H:
15239 case RISCV::CV_OR_SCI_B:
15240 case RISCV::CV_OR_SCI_H:
15241 case RISCV::CV_SUB_SCI_B:
15242 case RISCV::CV_SUB_SCI_H:
15243 case RISCV::CV_XOR_SCI_B:
15244 case RISCV::CV_XOR_SCI_H: {
15245 // op: rs1
15246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15247 op &= UINT64_C(31);
15248 op <<= 15;
15249 Value |= op;
15250 // op: rd
15251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15252 op &= UINT64_C(31);
15253 op <<= 7;
15254 Value |= op;
15255 // op: imm6
15256 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15257 Value |= (op & UINT64_C(1)) << 25;
15258 Value |= (op & UINT64_C(62)) << 19;
15259 break;
15260 }
15261 case RISCV::CV_AVGU_SCI_B:
15262 case RISCV::CV_AVGU_SCI_H:
15263 case RISCV::CV_CMPGEU_SCI_B:
15264 case RISCV::CV_CMPGEU_SCI_H:
15265 case RISCV::CV_CMPGTU_SCI_B:
15266 case RISCV::CV_CMPGTU_SCI_H:
15267 case RISCV::CV_CMPLEU_SCI_B:
15268 case RISCV::CV_CMPLEU_SCI_H:
15269 case RISCV::CV_CMPLTU_SCI_B:
15270 case RISCV::CV_CMPLTU_SCI_H:
15271 case RISCV::CV_DOTUP_SCI_B:
15272 case RISCV::CV_DOTUP_SCI_H:
15273 case RISCV::CV_EXTRACTU_B:
15274 case RISCV::CV_EXTRACTU_H:
15275 case RISCV::CV_EXTRACT_B:
15276 case RISCV::CV_EXTRACT_H:
15277 case RISCV::CV_MAXU_SCI_B:
15278 case RISCV::CV_MAXU_SCI_H:
15279 case RISCV::CV_MINU_SCI_B:
15280 case RISCV::CV_MINU_SCI_H:
15281 case RISCV::CV_SHUFFLEI0_SCI_B:
15282 case RISCV::CV_SHUFFLEI1_SCI_B:
15283 case RISCV::CV_SHUFFLEI2_SCI_B:
15284 case RISCV::CV_SHUFFLEI3_SCI_B:
15285 case RISCV::CV_SHUFFLE_SCI_H:
15286 case RISCV::CV_SLL_SCI_B:
15287 case RISCV::CV_SLL_SCI_H:
15288 case RISCV::CV_SRA_SCI_B:
15289 case RISCV::CV_SRA_SCI_H:
15290 case RISCV::CV_SRL_SCI_B:
15291 case RISCV::CV_SRL_SCI_H: {
15292 // op: rs1
15293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15294 op &= UINT64_C(31);
15295 op <<= 15;
15296 Value |= op;
15297 // op: rd
15298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15299 op &= UINT64_C(31);
15300 op <<= 7;
15301 Value |= op;
15302 // op: imm6
15303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15304 Value |= (op & UINT64_C(1)) << 25;
15305 Value |= (op & UINT64_C(62)) << 19;
15306 break;
15307 }
15308 case RISCV::CV_BCLR:
15309 case RISCV::CV_BITREV:
15310 case RISCV::CV_BSET:
15311 case RISCV::CV_EXTRACT:
15312 case RISCV::CV_EXTRACTU: {
15313 // op: rs1
15314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15315 op &= UINT64_C(31);
15316 op <<= 15;
15317 Value |= op;
15318 // op: rd
15319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15320 op &= UINT64_C(31);
15321 op <<= 7;
15322 Value |= op;
15323 // op: is3
15324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15325 op &= UINT64_C(31);
15326 op <<= 25;
15327 Value |= op;
15328 // op: is2
15329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15330 op &= UINT64_C(31);
15331 op <<= 20;
15332 Value |= op;
15333 break;
15334 }
15335 case RISCV::TH_EXT:
15336 case RISCV::TH_EXTU: {
15337 // op: rs1
15338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15339 op &= UINT64_C(31);
15340 op <<= 15;
15341 Value |= op;
15342 // op: rd
15343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15344 op &= UINT64_C(31);
15345 op <<= 7;
15346 Value |= op;
15347 // op: msb
15348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15349 op &= UINT64_C(63);
15350 op <<= 26;
15351 Value |= op;
15352 // op: lsb
15353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15354 op &= UINT64_C(63);
15355 op <<= 20;
15356 Value |= op;
15357 break;
15358 }
15359 case RISCV::AES64KS1I: {
15360 // op: rs1
15361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15362 op &= UINT64_C(31);
15363 op <<= 15;
15364 Value |= op;
15365 // op: rd
15366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15367 op &= UINT64_C(31);
15368 op <<= 7;
15369 Value |= op;
15370 // op: rnum
15371 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15372 op &= UINT64_C(15);
15373 op <<= 20;
15374 Value |= op;
15375 break;
15376 }
15377 case RISCV::RORIW:
15378 case RISCV::SLLIW:
15379 case RISCV::SRAIW:
15380 case RISCV::SRLIW:
15381 case RISCV::TH_SRRIW: {
15382 // op: rs1
15383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15384 op &= UINT64_C(31);
15385 op <<= 15;
15386 Value |= op;
15387 // op: rd
15388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15389 op &= UINT64_C(31);
15390 op <<= 7;
15391 Value |= op;
15392 // op: shamt
15393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15394 op &= UINT64_C(31);
15395 op <<= 20;
15396 Value |= op;
15397 break;
15398 }
15399 case RISCV::BCLRI:
15400 case RISCV::BEXTI:
15401 case RISCV::BINVI:
15402 case RISCV::BSETI:
15403 case RISCV::RORI:
15404 case RISCV::SLLI:
15405 case RISCV::SLLI_UW:
15406 case RISCV::SRAI:
15407 case RISCV::SRLI:
15408 case RISCV::TH_SRRI:
15409 case RISCV::TH_TST: {
15410 // op: rs1
15411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15412 op &= UINT64_C(31);
15413 op <<= 15;
15414 Value |= op;
15415 // op: rd
15416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15417 op &= UINT64_C(31);
15418 op <<= 7;
15419 Value |= op;
15420 // op: shamt
15421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15422 op &= UINT64_C(63);
15423 op <<= 20;
15424 Value |= op;
15425 break;
15426 }
15427 case RISCV::VSETVLI: {
15428 // op: rs1
15429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15430 op &= UINT64_C(31);
15431 op <<= 15;
15432 Value |= op;
15433 // op: rd
15434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15435 op &= UINT64_C(31);
15436 op <<= 7;
15437 Value |= op;
15438 // op: vtypei
15439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15440 op &= UINT64_C(2047);
15441 op <<= 20;
15442 Value |= op;
15443 break;
15444 }
15445 case RISCV::VFMV_V_F:
15446 case RISCV::VL1RE8_V:
15447 case RISCV::VL1RE16_V:
15448 case RISCV::VL1RE32_V:
15449 case RISCV::VL1RE64_V:
15450 case RISCV::VL2RE8_V:
15451 case RISCV::VL2RE16_V:
15452 case RISCV::VL2RE32_V:
15453 case RISCV::VL2RE64_V:
15454 case RISCV::VL4RE8_V:
15455 case RISCV::VL4RE16_V:
15456 case RISCV::VL4RE32_V:
15457 case RISCV::VL4RE64_V:
15458 case RISCV::VL8RE8_V:
15459 case RISCV::VL8RE16_V:
15460 case RISCV::VL8RE32_V:
15461 case RISCV::VL8RE64_V:
15462 case RISCV::VLM_V:
15463 case RISCV::VMV_V_X: {
15464 // op: rs1
15465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15466 op &= UINT64_C(31);
15467 op <<= 15;
15468 Value |= op;
15469 // op: vd
15470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15471 op &= UINT64_C(31);
15472 op <<= 7;
15473 Value |= op;
15474 break;
15475 }
15476 case RISCV::VLE8FF_V:
15477 case RISCV::VLE8_V:
15478 case RISCV::VLE16FF_V:
15479 case RISCV::VLE16_V:
15480 case RISCV::VLE32FF_V:
15481 case RISCV::VLE32_V:
15482 case RISCV::VLE64FF_V:
15483 case RISCV::VLE64_V:
15484 case RISCV::VLSEG2E8FF_V:
15485 case RISCV::VLSEG2E8_V:
15486 case RISCV::VLSEG2E16FF_V:
15487 case RISCV::VLSEG2E16_V:
15488 case RISCV::VLSEG2E32FF_V:
15489 case RISCV::VLSEG2E32_V:
15490 case RISCV::VLSEG2E64FF_V:
15491 case RISCV::VLSEG2E64_V:
15492 case RISCV::VLSEG3E8FF_V:
15493 case RISCV::VLSEG3E8_V:
15494 case RISCV::VLSEG3E16FF_V:
15495 case RISCV::VLSEG3E16_V:
15496 case RISCV::VLSEG3E32FF_V:
15497 case RISCV::VLSEG3E32_V:
15498 case RISCV::VLSEG3E64FF_V:
15499 case RISCV::VLSEG3E64_V:
15500 case RISCV::VLSEG4E8FF_V:
15501 case RISCV::VLSEG4E8_V:
15502 case RISCV::VLSEG4E16FF_V:
15503 case RISCV::VLSEG4E16_V:
15504 case RISCV::VLSEG4E32FF_V:
15505 case RISCV::VLSEG4E32_V:
15506 case RISCV::VLSEG4E64FF_V:
15507 case RISCV::VLSEG4E64_V:
15508 case RISCV::VLSEG5E8FF_V:
15509 case RISCV::VLSEG5E8_V:
15510 case RISCV::VLSEG5E16FF_V:
15511 case RISCV::VLSEG5E16_V:
15512 case RISCV::VLSEG5E32FF_V:
15513 case RISCV::VLSEG5E32_V:
15514 case RISCV::VLSEG5E64FF_V:
15515 case RISCV::VLSEG5E64_V:
15516 case RISCV::VLSEG6E8FF_V:
15517 case RISCV::VLSEG6E8_V:
15518 case RISCV::VLSEG6E16FF_V:
15519 case RISCV::VLSEG6E16_V:
15520 case RISCV::VLSEG6E32FF_V:
15521 case RISCV::VLSEG6E32_V:
15522 case RISCV::VLSEG6E64FF_V:
15523 case RISCV::VLSEG6E64_V:
15524 case RISCV::VLSEG7E8FF_V:
15525 case RISCV::VLSEG7E8_V:
15526 case RISCV::VLSEG7E16FF_V:
15527 case RISCV::VLSEG7E16_V:
15528 case RISCV::VLSEG7E32FF_V:
15529 case RISCV::VLSEG7E32_V:
15530 case RISCV::VLSEG7E64FF_V:
15531 case RISCV::VLSEG7E64_V:
15532 case RISCV::VLSEG8E8FF_V:
15533 case RISCV::VLSEG8E8_V:
15534 case RISCV::VLSEG8E16FF_V:
15535 case RISCV::VLSEG8E16_V:
15536 case RISCV::VLSEG8E32FF_V:
15537 case RISCV::VLSEG8E32_V:
15538 case RISCV::VLSEG8E64FF_V:
15539 case RISCV::VLSEG8E64_V: {
15540 // op: rs1
15541 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15542 op &= UINT64_C(31);
15543 op <<= 15;
15544 Value |= op;
15545 // op: vd
15546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15547 op &= UINT64_C(31);
15548 op <<= 7;
15549 Value |= op;
15550 // op: vm
15551 op = getVMaskReg(MI, OpNo: 2, Fixups, STI);
15552 op &= UINT64_C(1);
15553 op <<= 25;
15554 Value |= op;
15555 break;
15556 }
15557 case RISCV::VS1R_V:
15558 case RISCV::VS2R_V:
15559 case RISCV::VS4R_V:
15560 case RISCV::VS8R_V:
15561 case RISCV::VSM_V: {
15562 // op: rs1
15563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15564 op &= UINT64_C(31);
15565 op <<= 15;
15566 Value |= op;
15567 // op: vs3
15568 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15569 op &= UINT64_C(31);
15570 op <<= 7;
15571 Value |= op;
15572 break;
15573 }
15574 case RISCV::VSE8_V:
15575 case RISCV::VSE16_V:
15576 case RISCV::VSE32_V:
15577 case RISCV::VSE64_V:
15578 case RISCV::VSSEG2E8_V:
15579 case RISCV::VSSEG2E16_V:
15580 case RISCV::VSSEG2E32_V:
15581 case RISCV::VSSEG2E64_V:
15582 case RISCV::VSSEG3E8_V:
15583 case RISCV::VSSEG3E16_V:
15584 case RISCV::VSSEG3E32_V:
15585 case RISCV::VSSEG3E64_V:
15586 case RISCV::VSSEG4E8_V:
15587 case RISCV::VSSEG4E16_V:
15588 case RISCV::VSSEG4E32_V:
15589 case RISCV::VSSEG4E64_V:
15590 case RISCV::VSSEG5E8_V:
15591 case RISCV::VSSEG5E16_V:
15592 case RISCV::VSSEG5E32_V:
15593 case RISCV::VSSEG5E64_V:
15594 case RISCV::VSSEG6E8_V:
15595 case RISCV::VSSEG6E16_V:
15596 case RISCV::VSSEG6E32_V:
15597 case RISCV::VSSEG6E64_V:
15598 case RISCV::VSSEG7E8_V:
15599 case RISCV::VSSEG7E16_V:
15600 case RISCV::VSSEG7E32_V:
15601 case RISCV::VSSEG7E64_V:
15602 case RISCV::VSSEG8E8_V:
15603 case RISCV::VSSEG8E16_V:
15604 case RISCV::VSSEG8E32_V:
15605 case RISCV::VSSEG8E64_V: {
15606 // op: rs1
15607 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15608 op &= UINT64_C(31);
15609 op <<= 15;
15610 Value |= op;
15611 // op: vs3
15612 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15613 op &= UINT64_C(31);
15614 op <<= 7;
15615 Value |= op;
15616 // op: vm
15617 op = getVMaskReg(MI, OpNo: 2, Fixups, STI);
15618 op &= UINT64_C(1);
15619 op <<= 25;
15620 Value |= op;
15621 break;
15622 }
15623 case RISCV::C_ADD: {
15624 // op: rs1
15625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15626 op &= UINT64_C(31);
15627 op <<= 7;
15628 Value |= op;
15629 // op: rs2
15630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15631 op &= UINT64_C(31);
15632 op <<= 2;
15633 Value |= op;
15634 break;
15635 }
15636 case RISCV::CV_LBU_ri_inc:
15637 case RISCV::CV_LB_ri_inc:
15638 case RISCV::CV_LHU_ri_inc:
15639 case RISCV::CV_LH_ri_inc:
15640 case RISCV::CV_LW_ri_inc: {
15641 // op: rs1
15642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15643 op &= UINT64_C(31);
15644 op <<= 15;
15645 Value |= op;
15646 // op: rd
15647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15648 op &= UINT64_C(31);
15649 op <<= 7;
15650 Value |= op;
15651 // op: imm12
15652 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15653 op &= UINT64_C(4095);
15654 op <<= 20;
15655 Value |= op;
15656 break;
15657 }
15658 case RISCV::CSRRC:
15659 case RISCV::CSRRCI:
15660 case RISCV::CSRRS:
15661 case RISCV::CSRRSI:
15662 case RISCV::CSRRW:
15663 case RISCV::CSRRWI: {
15664 // op: rs1
15665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15666 op &= UINT64_C(31);
15667 op <<= 15;
15668 Value |= op;
15669 // op: rd
15670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15671 op &= UINT64_C(31);
15672 op <<= 7;
15673 Value |= op;
15674 // op: imm12
15675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15676 op &= UINT64_C(4095);
15677 op <<= 20;
15678 Value |= op;
15679 break;
15680 }
15681 case RISCV::TH_LBIA:
15682 case RISCV::TH_LBIB:
15683 case RISCV::TH_LBUIA:
15684 case RISCV::TH_LBUIB:
15685 case RISCV::TH_LDIA:
15686 case RISCV::TH_LDIB:
15687 case RISCV::TH_LHIA:
15688 case RISCV::TH_LHIB:
15689 case RISCV::TH_LHUIA:
15690 case RISCV::TH_LHUIB:
15691 case RISCV::TH_LWIA:
15692 case RISCV::TH_LWIB:
15693 case RISCV::TH_LWUIA:
15694 case RISCV::TH_LWUIB: {
15695 // op: rs1
15696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15697 op &= UINT64_C(31);
15698 op <<= 15;
15699 Value |= op;
15700 // op: rd
15701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15702 op &= UINT64_C(31);
15703 op <<= 7;
15704 Value |= op;
15705 // op: simm5
15706 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15707 op &= UINT64_C(31);
15708 op <<= 20;
15709 Value |= op;
15710 // op: uimm2
15711 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15712 op &= UINT64_C(3);
15713 op <<= 25;
15714 Value |= op;
15715 break;
15716 }
15717 case RISCV::CV_SDOTSP_SCI_B:
15718 case RISCV::CV_SDOTSP_SCI_H:
15719 case RISCV::CV_SDOTUSP_SCI_B:
15720 case RISCV::CV_SDOTUSP_SCI_H: {
15721 // op: rs1
15722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15723 op &= UINT64_C(31);
15724 op <<= 15;
15725 Value |= op;
15726 // op: rd
15727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15728 op &= UINT64_C(31);
15729 op <<= 7;
15730 Value |= op;
15731 // op: imm6
15732 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15733 Value |= (op & UINT64_C(1)) << 25;
15734 Value |= (op & UINT64_C(62)) << 19;
15735 break;
15736 }
15737 case RISCV::CV_INSERT_B:
15738 case RISCV::CV_INSERT_H:
15739 case RISCV::CV_SDOTUP_SCI_B:
15740 case RISCV::CV_SDOTUP_SCI_H: {
15741 // op: rs1
15742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15743 op &= UINT64_C(31);
15744 op <<= 15;
15745 Value |= op;
15746 // op: rd
15747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15748 op &= UINT64_C(31);
15749 op <<= 7;
15750 Value |= op;
15751 // op: imm6
15752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15753 Value |= (op & UINT64_C(1)) << 25;
15754 Value |= (op & UINT64_C(62)) << 19;
15755 break;
15756 }
15757 case RISCV::CV_INSERT: {
15758 // op: rs1
15759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15760 op &= UINT64_C(31);
15761 op <<= 15;
15762 Value |= op;
15763 // op: rd
15764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15765 op &= UINT64_C(31);
15766 op <<= 7;
15767 Value |= op;
15768 // op: is3
15769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15770 op &= UINT64_C(31);
15771 op <<= 25;
15772 Value |= op;
15773 // op: is2
15774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15775 op &= UINT64_C(31);
15776 op <<= 20;
15777 Value |= op;
15778 break;
15779 }
15780 case RISCV::TH_SBIA:
15781 case RISCV::TH_SBIB:
15782 case RISCV::TH_SDIA:
15783 case RISCV::TH_SDIB:
15784 case RISCV::TH_SHIA:
15785 case RISCV::TH_SHIB:
15786 case RISCV::TH_SWIA:
15787 case RISCV::TH_SWIB: {
15788 // op: rs1
15789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15790 op &= UINT64_C(31);
15791 op <<= 15;
15792 Value |= op;
15793 // op: rd
15794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15795 op &= UINT64_C(31);
15796 op <<= 7;
15797 Value |= op;
15798 // op: simm5
15799 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15800 op &= UINT64_C(31);
15801 op <<= 20;
15802 Value |= op;
15803 // op: uimm2
15804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15805 op &= UINT64_C(3);
15806 op <<= 25;
15807 Value |= op;
15808 break;
15809 }
15810 case RISCV::VFMV_S_F:
15811 case RISCV::VMV_S_X: {
15812 // op: rs1
15813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15814 op &= UINT64_C(31);
15815 op <<= 15;
15816 Value |= op;
15817 // op: vd
15818 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15819 op &= UINT64_C(31);
15820 op <<= 7;
15821 Value |= op;
15822 break;
15823 }
15824 case RISCV::SSPUSH: {
15825 // op: rs2
15826 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15827 op &= UINT64_C(31);
15828 op <<= 20;
15829 Value |= op;
15830 break;
15831 }
15832 case RISCV::CV_SB_rr:
15833 case RISCV::CV_SH_rr:
15834 case RISCV::CV_SW_rr: {
15835 // op: rs2
15836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15837 op &= UINT64_C(31);
15838 op <<= 20;
15839 Value |= op;
15840 // op: cvrr
15841 op = getRegReg(MI, OpNo: 1, Fixups, STI);
15842 Value |= (op & UINT64_C(992)) << 10;
15843 Value |= (op & UINT64_C(31)) << 7;
15844 break;
15845 }
15846 case RISCV::HSV_B:
15847 case RISCV::HSV_D:
15848 case RISCV::HSV_H:
15849 case RISCV::HSV_W: {
15850 // op: rs2
15851 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15852 op &= UINT64_C(31);
15853 op <<= 20;
15854 Value |= op;
15855 // op: rs1
15856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15857 op &= UINT64_C(31);
15858 op <<= 15;
15859 Value |= op;
15860 break;
15861 }
15862 case RISCV::C_FSD:
15863 case RISCV::C_SD: {
15864 // op: rs2
15865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15866 op &= UINT64_C(7);
15867 op <<= 2;
15868 Value |= op;
15869 // op: rs1
15870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15871 op &= UINT64_C(7);
15872 op <<= 7;
15873 Value |= op;
15874 // op: imm
15875 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15876 Value |= (op & UINT64_C(56)) << 7;
15877 Value |= (op & UINT64_C(192)) >> 1;
15878 break;
15879 }
15880 case RISCV::C_FSW:
15881 case RISCV::C_SW: {
15882 // op: rs2
15883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15884 op &= UINT64_C(7);
15885 op <<= 2;
15886 Value |= op;
15887 // op: rs1
15888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15889 op &= UINT64_C(7);
15890 op <<= 7;
15891 Value |= op;
15892 // op: imm
15893 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15894 Value |= (op & UINT64_C(56)) << 7;
15895 Value |= (op & UINT64_C(4)) << 4;
15896 Value |= (op & UINT64_C(64)) >> 1;
15897 break;
15898 }
15899 case RISCV::QK_C_SH: {
15900 // op: rs2
15901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15902 op &= UINT64_C(7);
15903 op <<= 2;
15904 Value |= op;
15905 // op: rs1
15906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15907 op &= UINT64_C(7);
15908 op <<= 7;
15909 Value |= op;
15910 // op: imm
15911 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15912 Value |= (op & UINT64_C(56)) << 7;
15913 Value |= (op & UINT64_C(6)) << 4;
15914 break;
15915 }
15916 case RISCV::C_SH: {
15917 // op: rs2
15918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15919 op &= UINT64_C(7);
15920 op <<= 2;
15921 Value |= op;
15922 // op: rs1
15923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15924 op &= UINT64_C(7);
15925 op <<= 7;
15926 Value |= op;
15927 // op: imm
15928 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15929 op &= UINT64_C(2);
15930 op <<= 4;
15931 Value |= op;
15932 break;
15933 }
15934 case RISCV::QK_C_SB: {
15935 // op: rs2
15936 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15937 op &= UINT64_C(7);
15938 op <<= 2;
15939 Value |= op;
15940 // op: rs1
15941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15942 op &= UINT64_C(7);
15943 op <<= 7;
15944 Value |= op;
15945 // op: imm
15946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15947 Value |= (op & UINT64_C(1)) << 12;
15948 Value |= (op & UINT64_C(24)) << 7;
15949 Value |= (op & UINT64_C(6)) << 4;
15950 break;
15951 }
15952 case RISCV::C_SB: {
15953 // op: rs2
15954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15955 op &= UINT64_C(7);
15956 op <<= 2;
15957 Value |= op;
15958 // op: rs1
15959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15960 op &= UINT64_C(7);
15961 op <<= 7;
15962 Value |= op;
15963 // op: imm
15964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15965 Value |= (op & UINT64_C(1)) << 6;
15966 Value |= (op & UINT64_C(2)) << 4;
15967 break;
15968 }
15969 case RISCV::VC_I: {
15970 // op: rs2
15971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15972 op &= UINT64_C(31);
15973 op <<= 20;
15974 Value |= op;
15975 // op: rs1
15976 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15977 op &= UINT64_C(31);
15978 op <<= 15;
15979 Value |= op;
15980 // op: rd
15981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15982 op &= UINT64_C(31);
15983 op <<= 7;
15984 Value |= op;
15985 // op: funct6_lo2
15986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15987 op &= UINT64_C(3);
15988 op <<= 26;
15989 Value |= op;
15990 break;
15991 }
15992 case RISCV::HFENCE_GVMA:
15993 case RISCV::HFENCE_VVMA:
15994 case RISCV::HINVAL_GVMA:
15995 case RISCV::HINVAL_VVMA:
15996 case RISCV::SB_AQ_RL:
15997 case RISCV::SB_RL:
15998 case RISCV::SD_AQ_RL:
15999 case RISCV::SD_RL:
16000 case RISCV::SFENCE_VMA:
16001 case RISCV::SH_AQ_RL:
16002 case RISCV::SH_RL:
16003 case RISCV::SINVAL_VMA:
16004 case RISCV::SW_AQ_RL:
16005 case RISCV::SW_RL:
16006 case RISCV::TH_SFENCE_VMAS: {
16007 // op: rs2
16008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16009 op &= UINT64_C(31);
16010 op <<= 20;
16011 Value |= op;
16012 // op: rs1
16013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16014 op &= UINT64_C(31);
16015 op <<= 15;
16016 Value |= op;
16017 break;
16018 }
16019 case RISCV::TH_LDD:
16020 case RISCV::TH_LWD:
16021 case RISCV::TH_LWUD:
16022 case RISCV::TH_SDD:
16023 case RISCV::TH_SWD: {
16024 // op: rs2
16025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16026 op &= UINT64_C(31);
16027 op <<= 20;
16028 Value |= op;
16029 // op: rs1
16030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16031 op &= UINT64_C(31);
16032 op <<= 15;
16033 Value |= op;
16034 // op: rd
16035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16036 op &= UINT64_C(31);
16037 op <<= 7;
16038 Value |= op;
16039 // op: uimm2
16040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16041 op &= UINT64_C(3);
16042 op <<= 25;
16043 Value |= op;
16044 break;
16045 }
16046 case RISCV::VC_X: {
16047 // op: rs2
16048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16049 op &= UINT64_C(31);
16050 op <<= 20;
16051 Value |= op;
16052 // op: rs1
16053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16054 op &= UINT64_C(31);
16055 op <<= 15;
16056 Value |= op;
16057 // op: rd
16058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16059 op &= UINT64_C(31);
16060 op <<= 7;
16061 Value |= op;
16062 // op: funct6_lo2
16063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16064 op &= UINT64_C(3);
16065 op <<= 26;
16066 Value |= op;
16067 break;
16068 }
16069 case RISCV::C_MV_HINT: {
16070 // op: rs2
16071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16072 op &= UINT64_C(31);
16073 op <<= 2;
16074 Value |= op;
16075 break;
16076 }
16077 case RISCV::CM_MVA01S:
16078 case RISCV::CM_MVSA01: {
16079 // op: rs2
16080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16081 op &= UINT64_C(7);
16082 op <<= 2;
16083 Value |= op;
16084 // op: rs1
16085 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16086 op &= UINT64_C(7);
16087 op <<= 7;
16088 Value |= op;
16089 break;
16090 }
16091 case RISCV::VC_V_I:
16092 case RISCV::VC_V_IV: {
16093 // op: rs2
16094 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16095 op &= UINT64_C(31);
16096 op <<= 20;
16097 Value |= op;
16098 // op: rs1
16099 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
16100 op &= UINT64_C(31);
16101 op <<= 15;
16102 Value |= op;
16103 // op: rd
16104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16105 op &= UINT64_C(31);
16106 op <<= 7;
16107 Value |= op;
16108 // op: funct6_lo2
16109 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16110 op &= UINT64_C(3);
16111 op <<= 26;
16112 Value |= op;
16113 break;
16114 }
16115 case RISCV::VC_IV:
16116 case RISCV::VC_IVV:
16117 case RISCV::VC_IVW: {
16118 // op: rs2
16119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16120 op &= UINT64_C(31);
16121 op <<= 20;
16122 Value |= op;
16123 // op: rs1
16124 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
16125 op &= UINT64_C(31);
16126 op <<= 15;
16127 Value |= op;
16128 // op: rd
16129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16130 op &= UINT64_C(31);
16131 op <<= 7;
16132 Value |= op;
16133 // op: funct6_lo2
16134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16135 op &= UINT64_C(3);
16136 op <<= 26;
16137 Value |= op;
16138 break;
16139 }
16140 case RISCV::FADD_D:
16141 case RISCV::FADD_D_IN32X:
16142 case RISCV::FADD_D_INX:
16143 case RISCV::FADD_H:
16144 case RISCV::FADD_H_INX:
16145 case RISCV::FADD_S:
16146 case RISCV::FADD_S_INX:
16147 case RISCV::FDIV_D:
16148 case RISCV::FDIV_D_IN32X:
16149 case RISCV::FDIV_D_INX:
16150 case RISCV::FDIV_H:
16151 case RISCV::FDIV_H_INX:
16152 case RISCV::FDIV_S:
16153 case RISCV::FDIV_S_INX:
16154 case RISCV::FMUL_D:
16155 case RISCV::FMUL_D_IN32X:
16156 case RISCV::FMUL_D_INX:
16157 case RISCV::FMUL_H:
16158 case RISCV::FMUL_H_INX:
16159 case RISCV::FMUL_S:
16160 case RISCV::FMUL_S_INX:
16161 case RISCV::FSUB_D:
16162 case RISCV::FSUB_D_IN32X:
16163 case RISCV::FSUB_D_INX:
16164 case RISCV::FSUB_H:
16165 case RISCV::FSUB_H_INX:
16166 case RISCV::FSUB_S:
16167 case RISCV::FSUB_S_INX: {
16168 // op: rs2
16169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16170 op &= UINT64_C(31);
16171 op <<= 20;
16172 Value |= op;
16173 // op: rs1
16174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16175 op &= UINT64_C(31);
16176 op <<= 15;
16177 Value |= op;
16178 // op: frm
16179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16180 op &= UINT64_C(7);
16181 op <<= 12;
16182 Value |= op;
16183 // op: rd
16184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16185 op &= UINT64_C(31);
16186 op <<= 7;
16187 Value |= op;
16188 break;
16189 }
16190 case RISCV::ADD:
16191 case RISCV::ADDW:
16192 case RISCV::ADD_UW:
16193 case RISCV::AES64DS:
16194 case RISCV::AES64DSM:
16195 case RISCV::AES64ES:
16196 case RISCV::AES64ESM:
16197 case RISCV::AES64KS2:
16198 case RISCV::AMOADD_B:
16199 case RISCV::AMOADD_B_AQ:
16200 case RISCV::AMOADD_B_AQ_RL:
16201 case RISCV::AMOADD_B_RL:
16202 case RISCV::AMOADD_D:
16203 case RISCV::AMOADD_D_AQ:
16204 case RISCV::AMOADD_D_AQ_RL:
16205 case RISCV::AMOADD_D_RL:
16206 case RISCV::AMOADD_H:
16207 case RISCV::AMOADD_H_AQ:
16208 case RISCV::AMOADD_H_AQ_RL:
16209 case RISCV::AMOADD_H_RL:
16210 case RISCV::AMOADD_W:
16211 case RISCV::AMOADD_W_AQ:
16212 case RISCV::AMOADD_W_AQ_RL:
16213 case RISCV::AMOADD_W_RL:
16214 case RISCV::AMOAND_B:
16215 case RISCV::AMOAND_B_AQ:
16216 case RISCV::AMOAND_B_AQ_RL:
16217 case RISCV::AMOAND_B_RL:
16218 case RISCV::AMOAND_D:
16219 case RISCV::AMOAND_D_AQ:
16220 case RISCV::AMOAND_D_AQ_RL:
16221 case RISCV::AMOAND_D_RL:
16222 case RISCV::AMOAND_H:
16223 case RISCV::AMOAND_H_AQ:
16224 case RISCV::AMOAND_H_AQ_RL:
16225 case RISCV::AMOAND_H_RL:
16226 case RISCV::AMOAND_W:
16227 case RISCV::AMOAND_W_AQ:
16228 case RISCV::AMOAND_W_AQ_RL:
16229 case RISCV::AMOAND_W_RL:
16230 case RISCV::AMOMAXU_B:
16231 case RISCV::AMOMAXU_B_AQ:
16232 case RISCV::AMOMAXU_B_AQ_RL:
16233 case RISCV::AMOMAXU_B_RL:
16234 case RISCV::AMOMAXU_D:
16235 case RISCV::AMOMAXU_D_AQ:
16236 case RISCV::AMOMAXU_D_AQ_RL:
16237 case RISCV::AMOMAXU_D_RL:
16238 case RISCV::AMOMAXU_H:
16239 case RISCV::AMOMAXU_H_AQ:
16240 case RISCV::AMOMAXU_H_AQ_RL:
16241 case RISCV::AMOMAXU_H_RL:
16242 case RISCV::AMOMAXU_W:
16243 case RISCV::AMOMAXU_W_AQ:
16244 case RISCV::AMOMAXU_W_AQ_RL:
16245 case RISCV::AMOMAXU_W_RL:
16246 case RISCV::AMOMAX_B:
16247 case RISCV::AMOMAX_B_AQ:
16248 case RISCV::AMOMAX_B_AQ_RL:
16249 case RISCV::AMOMAX_B_RL:
16250 case RISCV::AMOMAX_D:
16251 case RISCV::AMOMAX_D_AQ:
16252 case RISCV::AMOMAX_D_AQ_RL:
16253 case RISCV::AMOMAX_D_RL:
16254 case RISCV::AMOMAX_H:
16255 case RISCV::AMOMAX_H_AQ:
16256 case RISCV::AMOMAX_H_AQ_RL:
16257 case RISCV::AMOMAX_H_RL:
16258 case RISCV::AMOMAX_W:
16259 case RISCV::AMOMAX_W_AQ:
16260 case RISCV::AMOMAX_W_AQ_RL:
16261 case RISCV::AMOMAX_W_RL:
16262 case RISCV::AMOMINU_B:
16263 case RISCV::AMOMINU_B_AQ:
16264 case RISCV::AMOMINU_B_AQ_RL:
16265 case RISCV::AMOMINU_B_RL:
16266 case RISCV::AMOMINU_D:
16267 case RISCV::AMOMINU_D_AQ:
16268 case RISCV::AMOMINU_D_AQ_RL:
16269 case RISCV::AMOMINU_D_RL:
16270 case RISCV::AMOMINU_H:
16271 case RISCV::AMOMINU_H_AQ:
16272 case RISCV::AMOMINU_H_AQ_RL:
16273 case RISCV::AMOMINU_H_RL:
16274 case RISCV::AMOMINU_W:
16275 case RISCV::AMOMINU_W_AQ:
16276 case RISCV::AMOMINU_W_AQ_RL:
16277 case RISCV::AMOMINU_W_RL:
16278 case RISCV::AMOMIN_B:
16279 case RISCV::AMOMIN_B_AQ:
16280 case RISCV::AMOMIN_B_AQ_RL:
16281 case RISCV::AMOMIN_B_RL:
16282 case RISCV::AMOMIN_D:
16283 case RISCV::AMOMIN_D_AQ:
16284 case RISCV::AMOMIN_D_AQ_RL:
16285 case RISCV::AMOMIN_D_RL:
16286 case RISCV::AMOMIN_H:
16287 case RISCV::AMOMIN_H_AQ:
16288 case RISCV::AMOMIN_H_AQ_RL:
16289 case RISCV::AMOMIN_H_RL:
16290 case RISCV::AMOMIN_W:
16291 case RISCV::AMOMIN_W_AQ:
16292 case RISCV::AMOMIN_W_AQ_RL:
16293 case RISCV::AMOMIN_W_RL:
16294 case RISCV::AMOOR_B:
16295 case RISCV::AMOOR_B_AQ:
16296 case RISCV::AMOOR_B_AQ_RL:
16297 case RISCV::AMOOR_B_RL:
16298 case RISCV::AMOOR_D:
16299 case RISCV::AMOOR_D_AQ:
16300 case RISCV::AMOOR_D_AQ_RL:
16301 case RISCV::AMOOR_D_RL:
16302 case RISCV::AMOOR_H:
16303 case RISCV::AMOOR_H_AQ:
16304 case RISCV::AMOOR_H_AQ_RL:
16305 case RISCV::AMOOR_H_RL:
16306 case RISCV::AMOOR_W:
16307 case RISCV::AMOOR_W_AQ:
16308 case RISCV::AMOOR_W_AQ_RL:
16309 case RISCV::AMOOR_W_RL:
16310 case RISCV::AMOSWAP_B:
16311 case RISCV::AMOSWAP_B_AQ:
16312 case RISCV::AMOSWAP_B_AQ_RL:
16313 case RISCV::AMOSWAP_B_RL:
16314 case RISCV::AMOSWAP_D:
16315 case RISCV::AMOSWAP_D_AQ:
16316 case RISCV::AMOSWAP_D_AQ_RL:
16317 case RISCV::AMOSWAP_D_RL:
16318 case RISCV::AMOSWAP_H:
16319 case RISCV::AMOSWAP_H_AQ:
16320 case RISCV::AMOSWAP_H_AQ_RL:
16321 case RISCV::AMOSWAP_H_RL:
16322 case RISCV::AMOSWAP_W:
16323 case RISCV::AMOSWAP_W_AQ:
16324 case RISCV::AMOSWAP_W_AQ_RL:
16325 case RISCV::AMOSWAP_W_RL:
16326 case RISCV::AMOXOR_B:
16327 case RISCV::AMOXOR_B_AQ:
16328 case RISCV::AMOXOR_B_AQ_RL:
16329 case RISCV::AMOXOR_B_RL:
16330 case RISCV::AMOXOR_D:
16331 case RISCV::AMOXOR_D_AQ:
16332 case RISCV::AMOXOR_D_AQ_RL:
16333 case RISCV::AMOXOR_D_RL:
16334 case RISCV::AMOXOR_H:
16335 case RISCV::AMOXOR_H_AQ:
16336 case RISCV::AMOXOR_H_AQ_RL:
16337 case RISCV::AMOXOR_H_RL:
16338 case RISCV::AMOXOR_W:
16339 case RISCV::AMOXOR_W_AQ:
16340 case RISCV::AMOXOR_W_AQ_RL:
16341 case RISCV::AMOXOR_W_RL:
16342 case RISCV::AND:
16343 case RISCV::ANDN:
16344 case RISCV::BCLR:
16345 case RISCV::BEXT:
16346 case RISCV::BINV:
16347 case RISCV::BSET:
16348 case RISCV::CLMUL:
16349 case RISCV::CLMULH:
16350 case RISCV::CLMULR:
16351 case RISCV::CV_ADD_B:
16352 case RISCV::CV_ADD_DIV2:
16353 case RISCV::CV_ADD_DIV4:
16354 case RISCV::CV_ADD_DIV8:
16355 case RISCV::CV_ADD_H:
16356 case RISCV::CV_ADD_SC_B:
16357 case RISCV::CV_ADD_SC_H:
16358 case RISCV::CV_AND_B:
16359 case RISCV::CV_AND_H:
16360 case RISCV::CV_AND_SC_B:
16361 case RISCV::CV_AND_SC_H:
16362 case RISCV::CV_AVGU_B:
16363 case RISCV::CV_AVGU_H:
16364 case RISCV::CV_AVGU_SC_B:
16365 case RISCV::CV_AVGU_SC_H:
16366 case RISCV::CV_AVG_B:
16367 case RISCV::CV_AVG_H:
16368 case RISCV::CV_AVG_SC_B:
16369 case RISCV::CV_AVG_SC_H:
16370 case RISCV::CV_BCLRR:
16371 case RISCV::CV_BSETR:
16372 case RISCV::CV_CLIPR:
16373 case RISCV::CV_CLIPUR:
16374 case RISCV::CV_CMPEQ_B:
16375 case RISCV::CV_CMPEQ_H:
16376 case RISCV::CV_CMPEQ_SC_B:
16377 case RISCV::CV_CMPEQ_SC_H:
16378 case RISCV::CV_CMPGEU_B:
16379 case RISCV::CV_CMPGEU_H:
16380 case RISCV::CV_CMPGEU_SC_B:
16381 case RISCV::CV_CMPGEU_SC_H:
16382 case RISCV::CV_CMPGE_B:
16383 case RISCV::CV_CMPGE_H:
16384 case RISCV::CV_CMPGE_SC_B:
16385 case RISCV::CV_CMPGE_SC_H:
16386 case RISCV::CV_CMPGTU_B:
16387 case RISCV::CV_CMPGTU_H:
16388 case RISCV::CV_CMPGTU_SC_B:
16389 case RISCV::CV_CMPGTU_SC_H:
16390 case RISCV::CV_CMPGT_B:
16391 case RISCV::CV_CMPGT_H:
16392 case RISCV::CV_CMPGT_SC_B:
16393 case RISCV::CV_CMPGT_SC_H:
16394 case RISCV::CV_CMPLEU_B:
16395 case RISCV::CV_CMPLEU_H:
16396 case RISCV::CV_CMPLEU_SC_B:
16397 case RISCV::CV_CMPLEU_SC_H:
16398 case RISCV::CV_CMPLE_B:
16399 case RISCV::CV_CMPLE_H:
16400 case RISCV::CV_CMPLE_SC_B:
16401 case RISCV::CV_CMPLE_SC_H:
16402 case RISCV::CV_CMPLTU_B:
16403 case RISCV::CV_CMPLTU_H:
16404 case RISCV::CV_CMPLTU_SC_B:
16405 case RISCV::CV_CMPLTU_SC_H:
16406 case RISCV::CV_CMPLT_B:
16407 case RISCV::CV_CMPLT_H:
16408 case RISCV::CV_CMPLT_SC_B:
16409 case RISCV::CV_CMPLT_SC_H:
16410 case RISCV::CV_CMPNE_B:
16411 case RISCV::CV_CMPNE_H:
16412 case RISCV::CV_CMPNE_SC_B:
16413 case RISCV::CV_CMPNE_SC_H:
16414 case RISCV::CV_DOTSP_B:
16415 case RISCV::CV_DOTSP_H:
16416 case RISCV::CV_DOTSP_SC_B:
16417 case RISCV::CV_DOTSP_SC_H:
16418 case RISCV::CV_DOTUP_B:
16419 case RISCV::CV_DOTUP_H:
16420 case RISCV::CV_DOTUP_SC_B:
16421 case RISCV::CV_DOTUP_SC_H:
16422 case RISCV::CV_DOTUSP_B:
16423 case RISCV::CV_DOTUSP_H:
16424 case RISCV::CV_DOTUSP_SC_B:
16425 case RISCV::CV_DOTUSP_SC_H:
16426 case RISCV::CV_EXTRACTR:
16427 case RISCV::CV_EXTRACTUR:
16428 case RISCV::CV_MAX:
16429 case RISCV::CV_MAXU:
16430 case RISCV::CV_MAXU_B:
16431 case RISCV::CV_MAXU_H:
16432 case RISCV::CV_MAXU_SC_B:
16433 case RISCV::CV_MAXU_SC_H:
16434 case RISCV::CV_MAX_B:
16435 case RISCV::CV_MAX_H:
16436 case RISCV::CV_MAX_SC_B:
16437 case RISCV::CV_MAX_SC_H:
16438 case RISCV::CV_MIN:
16439 case RISCV::CV_MINU:
16440 case RISCV::CV_MINU_B:
16441 case RISCV::CV_MINU_H:
16442 case RISCV::CV_MINU_SC_B:
16443 case RISCV::CV_MINU_SC_H:
16444 case RISCV::CV_MIN_B:
16445 case RISCV::CV_MIN_H:
16446 case RISCV::CV_MIN_SC_B:
16447 case RISCV::CV_MIN_SC_H:
16448 case RISCV::CV_OR_B:
16449 case RISCV::CV_OR_H:
16450 case RISCV::CV_OR_SC_B:
16451 case RISCV::CV_OR_SC_H:
16452 case RISCV::CV_PACK:
16453 case RISCV::CV_PACK_H:
16454 case RISCV::CV_ROR:
16455 case RISCV::CV_SHUFFLE_B:
16456 case RISCV::CV_SHUFFLE_H:
16457 case RISCV::CV_SLET:
16458 case RISCV::CV_SLETU:
16459 case RISCV::CV_SLL_B:
16460 case RISCV::CV_SLL_H:
16461 case RISCV::CV_SLL_SC_B:
16462 case RISCV::CV_SLL_SC_H:
16463 case RISCV::CV_SRA_B:
16464 case RISCV::CV_SRA_H:
16465 case RISCV::CV_SRA_SC_B:
16466 case RISCV::CV_SRA_SC_H:
16467 case RISCV::CV_SRL_B:
16468 case RISCV::CV_SRL_H:
16469 case RISCV::CV_SRL_SC_B:
16470 case RISCV::CV_SRL_SC_H:
16471 case RISCV::CV_SUBROTMJ:
16472 case RISCV::CV_SUBROTMJ_DIV2:
16473 case RISCV::CV_SUBROTMJ_DIV4:
16474 case RISCV::CV_SUBROTMJ_DIV8:
16475 case RISCV::CV_SUB_B:
16476 case RISCV::CV_SUB_DIV2:
16477 case RISCV::CV_SUB_DIV4:
16478 case RISCV::CV_SUB_DIV8:
16479 case RISCV::CV_SUB_H:
16480 case RISCV::CV_SUB_SC_B:
16481 case RISCV::CV_SUB_SC_H:
16482 case RISCV::CV_XOR_B:
16483 case RISCV::CV_XOR_H:
16484 case RISCV::CV_XOR_SC_B:
16485 case RISCV::CV_XOR_SC_H:
16486 case RISCV::CZERO_EQZ:
16487 case RISCV::CZERO_NEZ:
16488 case RISCV::DIV:
16489 case RISCV::DIVU:
16490 case RISCV::DIVUW:
16491 case RISCV::DIVW:
16492 case RISCV::FEQ_D:
16493 case RISCV::FEQ_D_IN32X:
16494 case RISCV::FEQ_D_INX:
16495 case RISCV::FEQ_H:
16496 case RISCV::FEQ_H_INX:
16497 case RISCV::FEQ_S:
16498 case RISCV::FEQ_S_INX:
16499 case RISCV::FLEQ_D:
16500 case RISCV::FLEQ_H:
16501 case RISCV::FLEQ_S:
16502 case RISCV::FLE_D:
16503 case RISCV::FLE_D_IN32X:
16504 case RISCV::FLE_D_INX:
16505 case RISCV::FLE_H:
16506 case RISCV::FLE_H_INX:
16507 case RISCV::FLE_S:
16508 case RISCV::FLE_S_INX:
16509 case RISCV::FLTQ_D:
16510 case RISCV::FLTQ_H:
16511 case RISCV::FLTQ_S:
16512 case RISCV::FLT_D:
16513 case RISCV::FLT_D_IN32X:
16514 case RISCV::FLT_D_INX:
16515 case RISCV::FLT_H:
16516 case RISCV::FLT_H_INX:
16517 case RISCV::FLT_S:
16518 case RISCV::FLT_S_INX:
16519 case RISCV::FMAXM_D:
16520 case RISCV::FMAXM_H:
16521 case RISCV::FMAXM_S:
16522 case RISCV::FMAX_D:
16523 case RISCV::FMAX_D_IN32X:
16524 case RISCV::FMAX_D_INX:
16525 case RISCV::FMAX_H:
16526 case RISCV::FMAX_H_INX:
16527 case RISCV::FMAX_S:
16528 case RISCV::FMAX_S_INX:
16529 case RISCV::FMINM_D:
16530 case RISCV::FMINM_H:
16531 case RISCV::FMINM_S:
16532 case RISCV::FMIN_D:
16533 case RISCV::FMIN_D_IN32X:
16534 case RISCV::FMIN_D_INX:
16535 case RISCV::FMIN_H:
16536 case RISCV::FMIN_H_INX:
16537 case RISCV::FMIN_S:
16538 case RISCV::FMIN_S_INX:
16539 case RISCV::FMVP_D_X:
16540 case RISCV::FSGNJN_D:
16541 case RISCV::FSGNJN_D_IN32X:
16542 case RISCV::FSGNJN_D_INX:
16543 case RISCV::FSGNJN_H:
16544 case RISCV::FSGNJN_H_INX:
16545 case RISCV::FSGNJN_S:
16546 case RISCV::FSGNJN_S_INX:
16547 case RISCV::FSGNJX_D:
16548 case RISCV::FSGNJX_D_IN32X:
16549 case RISCV::FSGNJX_D_INX:
16550 case RISCV::FSGNJX_H:
16551 case RISCV::FSGNJX_H_INX:
16552 case RISCV::FSGNJX_S:
16553 case RISCV::FSGNJX_S_INX:
16554 case RISCV::FSGNJ_D:
16555 case RISCV::FSGNJ_D_IN32X:
16556 case RISCV::FSGNJ_D_INX:
16557 case RISCV::FSGNJ_H:
16558 case RISCV::FSGNJ_H_INX:
16559 case RISCV::FSGNJ_S:
16560 case RISCV::FSGNJ_S_INX:
16561 case RISCV::MAX:
16562 case RISCV::MAXU:
16563 case RISCV::MIN:
16564 case RISCV::MINU:
16565 case RISCV::MOPRR0:
16566 case RISCV::MOPRR1:
16567 case RISCV::MOPRR2:
16568 case RISCV::MOPRR3:
16569 case RISCV::MOPRR4:
16570 case RISCV::MOPRR5:
16571 case RISCV::MOPRR6:
16572 case RISCV::MOPRR7:
16573 case RISCV::MUL:
16574 case RISCV::MULH:
16575 case RISCV::MULHSU:
16576 case RISCV::MULHU:
16577 case RISCV::MULW:
16578 case RISCV::OR:
16579 case RISCV::ORN:
16580 case RISCV::PACK:
16581 case RISCV::PACKH:
16582 case RISCV::PACKW:
16583 case RISCV::REM:
16584 case RISCV::REMU:
16585 case RISCV::REMUW:
16586 case RISCV::REMW:
16587 case RISCV::ROL:
16588 case RISCV::ROLW:
16589 case RISCV::ROR:
16590 case RISCV::RORW:
16591 case RISCV::SC_D:
16592 case RISCV::SC_D_AQ:
16593 case RISCV::SC_D_AQ_RL:
16594 case RISCV::SC_D_RL:
16595 case RISCV::SC_W:
16596 case RISCV::SC_W_AQ:
16597 case RISCV::SC_W_AQ_RL:
16598 case RISCV::SC_W_RL:
16599 case RISCV::SH1ADD:
16600 case RISCV::SH1ADD_UW:
16601 case RISCV::SH2ADD:
16602 case RISCV::SH2ADD_UW:
16603 case RISCV::SH3ADD:
16604 case RISCV::SH3ADD_UW:
16605 case RISCV::SHA512SIG0H:
16606 case RISCV::SHA512SIG0L:
16607 case RISCV::SHA512SIG1H:
16608 case RISCV::SHA512SIG1L:
16609 case RISCV::SHA512SUM0R:
16610 case RISCV::SHA512SUM1R:
16611 case RISCV::SLL:
16612 case RISCV::SLLW:
16613 case RISCV::SLT:
16614 case RISCV::SLTU:
16615 case RISCV::SRA:
16616 case RISCV::SRAW:
16617 case RISCV::SRL:
16618 case RISCV::SRLW:
16619 case RISCV::SSAMOSWAP_D:
16620 case RISCV::SSAMOSWAP_D_AQ:
16621 case RISCV::SSAMOSWAP_D_AQ_RL:
16622 case RISCV::SSAMOSWAP_D_RL:
16623 case RISCV::SSAMOSWAP_W:
16624 case RISCV::SSAMOSWAP_W_AQ:
16625 case RISCV::SSAMOSWAP_W_AQ_RL:
16626 case RISCV::SSAMOSWAP_W_RL:
16627 case RISCV::SUB:
16628 case RISCV::SUBW:
16629 case RISCV::VFWMACC_4x4x4:
16630 case RISCV::VQMACCSU_2x8x2:
16631 case RISCV::VQMACCSU_4x8x4:
16632 case RISCV::VQMACCUS_2x8x2:
16633 case RISCV::VQMACCUS_4x8x4:
16634 case RISCV::VQMACCU_2x8x2:
16635 case RISCV::VQMACCU_4x8x4:
16636 case RISCV::VQMACC_2x8x2:
16637 case RISCV::VQMACC_4x8x4:
16638 case RISCV::VSETVL:
16639 case RISCV::VT_MASKC:
16640 case RISCV::VT_MASKCN:
16641 case RISCV::XNOR:
16642 case RISCV::XOR:
16643 case RISCV::XPERM4:
16644 case RISCV::XPERM8: {
16645 // op: rs2
16646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16647 op &= UINT64_C(31);
16648 op <<= 20;
16649 Value |= op;
16650 // op: rs1
16651 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16652 op &= UINT64_C(31);
16653 op <<= 15;
16654 Value |= op;
16655 // op: rd
16656 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16657 op &= UINT64_C(31);
16658 op <<= 7;
16659 Value |= op;
16660 break;
16661 }
16662 case RISCV::AES32DSI:
16663 case RISCV::AES32DSMI:
16664 case RISCV::AES32ESI:
16665 case RISCV::AES32ESMI:
16666 case RISCV::SM4ED:
16667 case RISCV::SM4KS: {
16668 // op: rs2
16669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16670 op &= UINT64_C(31);
16671 op <<= 20;
16672 Value |= op;
16673 // op: rs1
16674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16675 op &= UINT64_C(31);
16676 op <<= 15;
16677 Value |= op;
16678 // op: rd
16679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16680 op &= UINT64_C(31);
16681 op <<= 7;
16682 Value |= op;
16683 // op: bs
16684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16685 op &= UINT64_C(3);
16686 op <<= 30;
16687 Value |= op;
16688 break;
16689 }
16690 case RISCV::CV_ADDN:
16691 case RISCV::CV_ADDRN:
16692 case RISCV::CV_ADDUN:
16693 case RISCV::CV_ADDURN:
16694 case RISCV::CV_MULHHSN:
16695 case RISCV::CV_MULHHSRN:
16696 case RISCV::CV_MULHHUN:
16697 case RISCV::CV_MULHHURN:
16698 case RISCV::CV_MULSN:
16699 case RISCV::CV_MULSRN:
16700 case RISCV::CV_MULUN:
16701 case RISCV::CV_MULURN:
16702 case RISCV::CV_SUBN:
16703 case RISCV::CV_SUBRN:
16704 case RISCV::CV_SUBUN:
16705 case RISCV::CV_SUBURN: {
16706 // op: rs2
16707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16708 op &= UINT64_C(31);
16709 op <<= 20;
16710 Value |= op;
16711 // op: rs1
16712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16713 op &= UINT64_C(31);
16714 op <<= 15;
16715 Value |= op;
16716 // op: rd
16717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16718 op &= UINT64_C(31);
16719 op <<= 7;
16720 Value |= op;
16721 // op: imm5
16722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16723 op &= UINT64_C(31);
16724 op <<= 25;
16725 Value |= op;
16726 break;
16727 }
16728 case RISCV::TH_ADDSL:
16729 case RISCV::TH_FLRD:
16730 case RISCV::TH_FLRW:
16731 case RISCV::TH_FLURD:
16732 case RISCV::TH_FLURW:
16733 case RISCV::TH_FSRD:
16734 case RISCV::TH_FSRW:
16735 case RISCV::TH_FSURD:
16736 case RISCV::TH_FSURW:
16737 case RISCV::TH_LRB:
16738 case RISCV::TH_LRBU:
16739 case RISCV::TH_LRD:
16740 case RISCV::TH_LRH:
16741 case RISCV::TH_LRHU:
16742 case RISCV::TH_LRW:
16743 case RISCV::TH_LRWU:
16744 case RISCV::TH_LURB:
16745 case RISCV::TH_LURBU:
16746 case RISCV::TH_LURD:
16747 case RISCV::TH_LURH:
16748 case RISCV::TH_LURHU:
16749 case RISCV::TH_LURW:
16750 case RISCV::TH_LURWU:
16751 case RISCV::TH_SRB:
16752 case RISCV::TH_SRD:
16753 case RISCV::TH_SRH:
16754 case RISCV::TH_SRW:
16755 case RISCV::TH_SURB:
16756 case RISCV::TH_SURD:
16757 case RISCV::TH_SURH:
16758 case RISCV::TH_SURW: {
16759 // op: rs2
16760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16761 op &= UINT64_C(31);
16762 op <<= 20;
16763 Value |= op;
16764 // op: rs1
16765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16766 op &= UINT64_C(31);
16767 op <<= 15;
16768 Value |= op;
16769 // op: rd
16770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16771 op &= UINT64_C(31);
16772 op <<= 7;
16773 Value |= op;
16774 // op: uimm2
16775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16776 op &= UINT64_C(3);
16777 op <<= 25;
16778 Value |= op;
16779 break;
16780 }
16781 case RISCV::VLSE8_V:
16782 case RISCV::VLSE16_V:
16783 case RISCV::VLSE32_V:
16784 case RISCV::VLSE64_V:
16785 case RISCV::VLSSEG2E8_V:
16786 case RISCV::VLSSEG2E16_V:
16787 case RISCV::VLSSEG2E32_V:
16788 case RISCV::VLSSEG2E64_V:
16789 case RISCV::VLSSEG3E8_V:
16790 case RISCV::VLSSEG3E16_V:
16791 case RISCV::VLSSEG3E32_V:
16792 case RISCV::VLSSEG3E64_V:
16793 case RISCV::VLSSEG4E8_V:
16794 case RISCV::VLSSEG4E16_V:
16795 case RISCV::VLSSEG4E32_V:
16796 case RISCV::VLSSEG4E64_V:
16797 case RISCV::VLSSEG5E8_V:
16798 case RISCV::VLSSEG5E16_V:
16799 case RISCV::VLSSEG5E32_V:
16800 case RISCV::VLSSEG5E64_V:
16801 case RISCV::VLSSEG6E8_V:
16802 case RISCV::VLSSEG6E16_V:
16803 case RISCV::VLSSEG6E32_V:
16804 case RISCV::VLSSEG6E64_V:
16805 case RISCV::VLSSEG7E8_V:
16806 case RISCV::VLSSEG7E16_V:
16807 case RISCV::VLSSEG7E32_V:
16808 case RISCV::VLSSEG7E64_V:
16809 case RISCV::VLSSEG8E8_V:
16810 case RISCV::VLSSEG8E16_V:
16811 case RISCV::VLSSEG8E32_V:
16812 case RISCV::VLSSEG8E64_V: {
16813 // op: rs2
16814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16815 op &= UINT64_C(31);
16816 op <<= 20;
16817 Value |= op;
16818 // op: rs1
16819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16820 op &= UINT64_C(31);
16821 op <<= 15;
16822 Value |= op;
16823 // op: vd
16824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16825 op &= UINT64_C(31);
16826 op <<= 7;
16827 Value |= op;
16828 // op: vm
16829 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
16830 op &= UINT64_C(1);
16831 op <<= 25;
16832 Value |= op;
16833 break;
16834 }
16835 case RISCV::VSSE8_V:
16836 case RISCV::VSSE16_V:
16837 case RISCV::VSSE32_V:
16838 case RISCV::VSSE64_V:
16839 case RISCV::VSSSEG2E8_V:
16840 case RISCV::VSSSEG2E16_V:
16841 case RISCV::VSSSEG2E32_V:
16842 case RISCV::VSSSEG2E64_V:
16843 case RISCV::VSSSEG3E8_V:
16844 case RISCV::VSSSEG3E16_V:
16845 case RISCV::VSSSEG3E32_V:
16846 case RISCV::VSSSEG3E64_V:
16847 case RISCV::VSSSEG4E8_V:
16848 case RISCV::VSSSEG4E16_V:
16849 case RISCV::VSSSEG4E32_V:
16850 case RISCV::VSSSEG4E64_V:
16851 case RISCV::VSSSEG5E8_V:
16852 case RISCV::VSSSEG5E16_V:
16853 case RISCV::VSSSEG5E32_V:
16854 case RISCV::VSSSEG5E64_V:
16855 case RISCV::VSSSEG6E8_V:
16856 case RISCV::VSSSEG6E16_V:
16857 case RISCV::VSSSEG6E32_V:
16858 case RISCV::VSSSEG6E64_V:
16859 case RISCV::VSSSEG7E8_V:
16860 case RISCV::VSSSEG7E16_V:
16861 case RISCV::VSSSEG7E32_V:
16862 case RISCV::VSSSEG7E64_V:
16863 case RISCV::VSSSEG8E8_V:
16864 case RISCV::VSSSEG8E16_V:
16865 case RISCV::VSSSEG8E32_V:
16866 case RISCV::VSSSEG8E64_V: {
16867 // op: rs2
16868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16869 op &= UINT64_C(31);
16870 op <<= 20;
16871 Value |= op;
16872 // op: rs1
16873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16874 op &= UINT64_C(31);
16875 op <<= 15;
16876 Value |= op;
16877 // op: vs3
16878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16879 op &= UINT64_C(31);
16880 op <<= 7;
16881 Value |= op;
16882 // op: vm
16883 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
16884 op &= UINT64_C(1);
16885 op <<= 25;
16886 Value |= op;
16887 break;
16888 }
16889 case RISCV::VC_V_FV: {
16890 // op: rs2
16891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16892 op &= UINT64_C(31);
16893 op <<= 20;
16894 Value |= op;
16895 // op: rs1
16896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16897 op &= UINT64_C(31);
16898 op <<= 15;
16899 Value |= op;
16900 // op: rd
16901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16902 op &= UINT64_C(31);
16903 op <<= 7;
16904 Value |= op;
16905 // op: funct6_lo1
16906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16907 op &= UINT64_C(1);
16908 op <<= 26;
16909 Value |= op;
16910 break;
16911 }
16912 case RISCV::VC_V_VV:
16913 case RISCV::VC_V_X:
16914 case RISCV::VC_V_XV: {
16915 // op: rs2
16916 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16917 op &= UINT64_C(31);
16918 op <<= 20;
16919 Value |= op;
16920 // op: rs1
16921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16922 op &= UINT64_C(31);
16923 op <<= 15;
16924 Value |= op;
16925 // op: rd
16926 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16927 op &= UINT64_C(31);
16928 op <<= 7;
16929 Value |= op;
16930 // op: funct6_lo2
16931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16932 op &= UINT64_C(3);
16933 op <<= 26;
16934 Value |= op;
16935 break;
16936 }
16937 case RISCV::VC_FV:
16938 case RISCV::VC_FVV:
16939 case RISCV::VC_FVW: {
16940 // op: rs2
16941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16942 op &= UINT64_C(31);
16943 op <<= 20;
16944 Value |= op;
16945 // op: rs1
16946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16947 op &= UINT64_C(31);
16948 op <<= 15;
16949 Value |= op;
16950 // op: rd
16951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16952 op &= UINT64_C(31);
16953 op <<= 7;
16954 Value |= op;
16955 // op: funct6_lo1
16956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16957 op &= UINT64_C(1);
16958 op <<= 26;
16959 Value |= op;
16960 break;
16961 }
16962 case RISCV::VC_VV:
16963 case RISCV::VC_VVV:
16964 case RISCV::VC_VVW:
16965 case RISCV::VC_XV:
16966 case RISCV::VC_XVV:
16967 case RISCV::VC_XVW: {
16968 // op: rs2
16969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16970 op &= UINT64_C(31);
16971 op <<= 20;
16972 Value |= op;
16973 // op: rs1
16974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16975 op &= UINT64_C(31);
16976 op <<= 15;
16977 Value |= op;
16978 // op: rd
16979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16980 op &= UINT64_C(31);
16981 op <<= 7;
16982 Value |= op;
16983 // op: funct6_lo2
16984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16985 op &= UINT64_C(3);
16986 op <<= 26;
16987 Value |= op;
16988 break;
16989 }
16990 case RISCV::C_ADD_HINT: {
16991 // op: rs2
16992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16993 op &= UINT64_C(31);
16994 op <<= 2;
16995 Value |= op;
16996 break;
16997 }
16998 case RISCV::C_ADDW:
16999 case RISCV::C_AND:
17000 case RISCV::C_MUL:
17001 case RISCV::C_OR:
17002 case RISCV::C_SUB:
17003 case RISCV::C_SUBW:
17004 case RISCV::C_XOR: {
17005 // op: rs2
17006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17007 op &= UINT64_C(7);
17008 op <<= 2;
17009 Value |= op;
17010 // op: rd
17011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17012 op &= UINT64_C(7);
17013 op <<= 7;
17014 Value |= op;
17015 break;
17016 }
17017 case RISCV::VC_V_IVV:
17018 case RISCV::VC_V_IVW: {
17019 // op: rs2
17020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17021 op &= UINT64_C(31);
17022 op <<= 20;
17023 Value |= op;
17024 // op: rs1
17025 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
17026 op &= UINT64_C(31);
17027 op <<= 15;
17028 Value |= op;
17029 // op: rd
17030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17031 op &= UINT64_C(31);
17032 op <<= 7;
17033 Value |= op;
17034 // op: funct6_lo2
17035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17036 op &= UINT64_C(3);
17037 op <<= 26;
17038 Value |= op;
17039 break;
17040 }
17041 case RISCV::CV_LBU_rr_inc:
17042 case RISCV::CV_LB_rr_inc:
17043 case RISCV::CV_LHU_rr_inc:
17044 case RISCV::CV_LH_rr_inc:
17045 case RISCV::CV_LW_rr_inc: {
17046 // op: rs2
17047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17048 op &= UINT64_C(31);
17049 op <<= 20;
17050 Value |= op;
17051 // op: rs1
17052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17053 op &= UINT64_C(31);
17054 op <<= 15;
17055 Value |= op;
17056 // op: rd
17057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17058 op &= UINT64_C(31);
17059 op <<= 7;
17060 Value |= op;
17061 break;
17062 }
17063 case RISCV::AMOCAS_B:
17064 case RISCV::AMOCAS_B_AQ:
17065 case RISCV::AMOCAS_B_AQ_RL:
17066 case RISCV::AMOCAS_B_RL:
17067 case RISCV::AMOCAS_D_RV32:
17068 case RISCV::AMOCAS_D_RV32_AQ:
17069 case RISCV::AMOCAS_D_RV32_AQ_RL:
17070 case RISCV::AMOCAS_D_RV32_RL:
17071 case RISCV::AMOCAS_D_RV64:
17072 case RISCV::AMOCAS_D_RV64_AQ:
17073 case RISCV::AMOCAS_D_RV64_AQ_RL:
17074 case RISCV::AMOCAS_D_RV64_RL:
17075 case RISCV::AMOCAS_H:
17076 case RISCV::AMOCAS_H_AQ:
17077 case RISCV::AMOCAS_H_AQ_RL:
17078 case RISCV::AMOCAS_H_RL:
17079 case RISCV::AMOCAS_Q:
17080 case RISCV::AMOCAS_Q_AQ:
17081 case RISCV::AMOCAS_Q_AQ_RL:
17082 case RISCV::AMOCAS_Q_RL:
17083 case RISCV::AMOCAS_W:
17084 case RISCV::AMOCAS_W_AQ:
17085 case RISCV::AMOCAS_W_AQ_RL:
17086 case RISCV::AMOCAS_W_RL:
17087 case RISCV::CV_ADDNR:
17088 case RISCV::CV_ADDRNR:
17089 case RISCV::CV_ADDUNR:
17090 case RISCV::CV_ADDURNR:
17091 case RISCV::CV_CPLXMUL_I:
17092 case RISCV::CV_CPLXMUL_I_DIV2:
17093 case RISCV::CV_CPLXMUL_I_DIV4:
17094 case RISCV::CV_CPLXMUL_I_DIV8:
17095 case RISCV::CV_CPLXMUL_R:
17096 case RISCV::CV_CPLXMUL_R_DIV2:
17097 case RISCV::CV_CPLXMUL_R_DIV4:
17098 case RISCV::CV_CPLXMUL_R_DIV8:
17099 case RISCV::CV_INSERTR:
17100 case RISCV::CV_MAC:
17101 case RISCV::CV_MSU:
17102 case RISCV::CV_PACKHI_B:
17103 case RISCV::CV_PACKLO_B:
17104 case RISCV::CV_SDOTSP_B:
17105 case RISCV::CV_SDOTSP_H:
17106 case RISCV::CV_SDOTSP_SC_B:
17107 case RISCV::CV_SDOTSP_SC_H:
17108 case RISCV::CV_SDOTUP_B:
17109 case RISCV::CV_SDOTUP_H:
17110 case RISCV::CV_SDOTUP_SC_B:
17111 case RISCV::CV_SDOTUP_SC_H:
17112 case RISCV::CV_SDOTUSP_B:
17113 case RISCV::CV_SDOTUSP_H:
17114 case RISCV::CV_SDOTUSP_SC_B:
17115 case RISCV::CV_SDOTUSP_SC_H:
17116 case RISCV::CV_SHUFFLE2_B:
17117 case RISCV::CV_SHUFFLE2_H:
17118 case RISCV::CV_SUBNR:
17119 case RISCV::CV_SUBRNR:
17120 case RISCV::CV_SUBUNR:
17121 case RISCV::CV_SUBURNR:
17122 case RISCV::TH_MULA:
17123 case RISCV::TH_MULAH:
17124 case RISCV::TH_MULAW:
17125 case RISCV::TH_MULS:
17126 case RISCV::TH_MULSH:
17127 case RISCV::TH_MULSW:
17128 case RISCV::TH_MVEQZ:
17129 case RISCV::TH_MVNEZ: {
17130 // op: rs2
17131 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17132 op &= UINT64_C(31);
17133 op <<= 20;
17134 Value |= op;
17135 // op: rs1
17136 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17137 op &= UINT64_C(31);
17138 op <<= 15;
17139 Value |= op;
17140 // op: rd
17141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17142 op &= UINT64_C(31);
17143 op <<= 7;
17144 Value |= op;
17145 break;
17146 }
17147 case RISCV::CV_MACHHSN:
17148 case RISCV::CV_MACHHSRN:
17149 case RISCV::CV_MACHHUN:
17150 case RISCV::CV_MACHHURN:
17151 case RISCV::CV_MACSN:
17152 case RISCV::CV_MACSRN:
17153 case RISCV::CV_MACUN:
17154 case RISCV::CV_MACURN: {
17155 // op: rs2
17156 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17157 op &= UINT64_C(31);
17158 op <<= 20;
17159 Value |= op;
17160 // op: rs1
17161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17162 op &= UINT64_C(31);
17163 op <<= 15;
17164 Value |= op;
17165 // op: rd
17166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17167 op &= UINT64_C(31);
17168 op <<= 7;
17169 Value |= op;
17170 // op: imm5
17171 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17172 op &= UINT64_C(31);
17173 op <<= 25;
17174 Value |= op;
17175 break;
17176 }
17177 case RISCV::VC_V_FVV:
17178 case RISCV::VC_V_FVW: {
17179 // op: rs2
17180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17181 op &= UINT64_C(31);
17182 op <<= 20;
17183 Value |= op;
17184 // op: rs1
17185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17186 op &= UINT64_C(31);
17187 op <<= 15;
17188 Value |= op;
17189 // op: rd
17190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17191 op &= UINT64_C(31);
17192 op <<= 7;
17193 Value |= op;
17194 // op: funct6_lo1
17195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17196 op &= UINT64_C(1);
17197 op <<= 26;
17198 Value |= op;
17199 break;
17200 }
17201 case RISCV::VC_V_VVV:
17202 case RISCV::VC_V_VVW:
17203 case RISCV::VC_V_XVV:
17204 case RISCV::VC_V_XVW: {
17205 // op: rs2
17206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17207 op &= UINT64_C(31);
17208 op <<= 20;
17209 Value |= op;
17210 // op: rs1
17211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17212 op &= UINT64_C(31);
17213 op <<= 15;
17214 Value |= op;
17215 // op: rd
17216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17217 op &= UINT64_C(31);
17218 op <<= 7;
17219 Value |= op;
17220 // op: funct6_lo2
17221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17222 op &= UINT64_C(3);
17223 op <<= 26;
17224 Value |= op;
17225 break;
17226 }
17227 case RISCV::FMADD_D:
17228 case RISCV::FMADD_D_IN32X:
17229 case RISCV::FMADD_D_INX:
17230 case RISCV::FMADD_H:
17231 case RISCV::FMADD_H_INX:
17232 case RISCV::FMADD_S:
17233 case RISCV::FMADD_S_INX:
17234 case RISCV::FMSUB_D:
17235 case RISCV::FMSUB_D_IN32X:
17236 case RISCV::FMSUB_D_INX:
17237 case RISCV::FMSUB_H:
17238 case RISCV::FMSUB_H_INX:
17239 case RISCV::FMSUB_S:
17240 case RISCV::FMSUB_S_INX:
17241 case RISCV::FNMADD_D:
17242 case RISCV::FNMADD_D_IN32X:
17243 case RISCV::FNMADD_D_INX:
17244 case RISCV::FNMADD_H:
17245 case RISCV::FNMADD_H_INX:
17246 case RISCV::FNMADD_S:
17247 case RISCV::FNMADD_S_INX:
17248 case RISCV::FNMSUB_D:
17249 case RISCV::FNMSUB_D_IN32X:
17250 case RISCV::FNMSUB_D_INX:
17251 case RISCV::FNMSUB_H:
17252 case RISCV::FNMSUB_H_INX:
17253 case RISCV::FNMSUB_S:
17254 case RISCV::FNMSUB_S_INX: {
17255 // op: rs3
17256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17257 op &= UINT64_C(31);
17258 op <<= 27;
17259 Value |= op;
17260 // op: rs2
17261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17262 op &= UINT64_C(31);
17263 op <<= 20;
17264 Value |= op;
17265 // op: rs1
17266 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17267 op &= UINT64_C(31);
17268 op <<= 15;
17269 Value |= op;
17270 // op: frm
17271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17272 op &= UINT64_C(7);
17273 op <<= 12;
17274 Value |= op;
17275 // op: rd
17276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17277 op &= UINT64_C(31);
17278 op <<= 7;
17279 Value |= op;
17280 break;
17281 }
17282 case RISCV::CV_SB_rr_inc:
17283 case RISCV::CV_SH_rr_inc:
17284 case RISCV::CV_SW_rr_inc: {
17285 // op: rs3
17286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17287 op &= UINT64_C(31);
17288 op <<= 7;
17289 Value |= op;
17290 // op: rs2
17291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17292 op &= UINT64_C(31);
17293 op <<= 20;
17294 Value |= op;
17295 // op: rs1
17296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17297 op &= UINT64_C(31);
17298 op <<= 15;
17299 Value |= op;
17300 break;
17301 }
17302 case RISCV::VSETIVLI: {
17303 // op: uimm
17304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17305 op &= UINT64_C(31);
17306 op <<= 15;
17307 Value |= op;
17308 // op: rd
17309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17310 op &= UINT64_C(31);
17311 op <<= 7;
17312 Value |= op;
17313 // op: vtypei
17314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17315 op &= UINT64_C(1023);
17316 op <<= 20;
17317 Value |= op;
17318 break;
17319 }
17320 case RISCV::Insn32: {
17321 // op: value
17322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17323 op &= UINT64_C(4294967295);
17324 Value |= op;
17325 break;
17326 }
17327 case RISCV::Insn16: {
17328 // op: value
17329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17330 op &= UINT64_C(65535);
17331 Value |= op;
17332 break;
17333 }
17334 case RISCV::VID_V: {
17335 // op: vd
17336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17337 op &= UINT64_C(31);
17338 op <<= 7;
17339 Value |= op;
17340 // op: vm
17341 op = getVMaskReg(MI, OpNo: 1, Fixups, STI);
17342 op &= UINT64_C(1);
17343 op <<= 25;
17344 Value |= op;
17345 break;
17346 }
17347 case RISCV::VMV_V_V: {
17348 // op: vs1
17349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17350 op &= UINT64_C(31);
17351 op <<= 15;
17352 Value |= op;
17353 // op: vd
17354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17355 op &= UINT64_C(31);
17356 op <<= 7;
17357 Value |= op;
17358 break;
17359 }
17360 case RISCV::VADC_VIM:
17361 case RISCV::VMADC_VI:
17362 case RISCV::VMADC_VIM:
17363 case RISCV::VMERGE_VIM: {
17364 // op: vs2
17365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17366 op &= UINT64_C(31);
17367 op <<= 20;
17368 Value |= op;
17369 // op: imm
17370 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17371 op &= UINT64_C(31);
17372 op <<= 15;
17373 Value |= op;
17374 // op: vd
17375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17376 op &= UINT64_C(31);
17377 op <<= 7;
17378 Value |= op;
17379 break;
17380 }
17381 case RISCV::VADD_VI:
17382 case RISCV::VAND_VI:
17383 case RISCV::VMSEQ_VI:
17384 case RISCV::VMSGTU_VI:
17385 case RISCV::VMSGT_VI:
17386 case RISCV::VMSLEU_VI:
17387 case RISCV::VMSLE_VI:
17388 case RISCV::VMSNE_VI:
17389 case RISCV::VOR_VI:
17390 case RISCV::VRSUB_VI:
17391 case RISCV::VSADDU_VI:
17392 case RISCV::VSADD_VI:
17393 case RISCV::VXOR_VI: {
17394 // op: vs2
17395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17396 op &= UINT64_C(31);
17397 op <<= 20;
17398 Value |= op;
17399 // op: imm
17400 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17401 op &= UINT64_C(31);
17402 op <<= 15;
17403 Value |= op;
17404 // op: vd
17405 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17406 op &= UINT64_C(31);
17407 op <<= 7;
17408 Value |= op;
17409 // op: vm
17410 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
17411 op &= UINT64_C(1);
17412 op <<= 25;
17413 Value |= op;
17414 break;
17415 }
17416 case RISCV::VROR_VI: {
17417 // op: vs2
17418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17419 op &= UINT64_C(31);
17420 op <<= 20;
17421 Value |= op;
17422 // op: imm
17423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17424 Value |= (op & UINT64_C(32)) << 21;
17425 Value |= (op & UINT64_C(31)) << 15;
17426 // op: vd
17427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17428 op &= UINT64_C(31);
17429 op <<= 7;
17430 Value |= op;
17431 // op: vm
17432 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
17433 op &= UINT64_C(1);
17434 op <<= 25;
17435 Value |= op;
17436 break;
17437 }
17438 case RISCV::VAESKF1_VI:
17439 case RISCV::VSM4K_VI: {
17440 // op: vs2
17441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17442 op &= UINT64_C(31);
17443 op <<= 20;
17444 Value |= op;
17445 // op: imm
17446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17447 op &= UINT64_C(31);
17448 op <<= 15;
17449 Value |= op;
17450 // op: vd
17451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17452 op &= UINT64_C(31);
17453 op <<= 7;
17454 Value |= op;
17455 break;
17456 }
17457 case RISCV::VNCLIPU_WI:
17458 case RISCV::VNCLIP_WI:
17459 case RISCV::VNSRA_WI:
17460 case RISCV::VNSRL_WI:
17461 case RISCV::VRGATHER_VI:
17462 case RISCV::VSLIDEDOWN_VI:
17463 case RISCV::VSLIDEUP_VI:
17464 case RISCV::VSLL_VI:
17465 case RISCV::VSRA_VI:
17466 case RISCV::VSRL_VI:
17467 case RISCV::VSSRA_VI:
17468 case RISCV::VSSRL_VI:
17469 case RISCV::VWSLL_VI: {
17470 // op: vs2
17471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17472 op &= UINT64_C(31);
17473 op <<= 20;
17474 Value |= op;
17475 // op: imm
17476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17477 op &= UINT64_C(31);
17478 op <<= 15;
17479 Value |= op;
17480 // op: vd
17481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17482 op &= UINT64_C(31);
17483 op <<= 7;
17484 Value |= op;
17485 // op: vm
17486 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
17487 op &= UINT64_C(1);
17488 op <<= 25;
17489 Value |= op;
17490 break;
17491 }
17492 case RISCV::VADC_VXM:
17493 case RISCV::VFMERGE_VFM:
17494 case RISCV::VMADC_VX:
17495 case RISCV::VMADC_VXM:
17496 case RISCV::VMERGE_VXM:
17497 case RISCV::VMSBC_VX:
17498 case RISCV::VMSBC_VXM:
17499 case RISCV::VSBC_VXM: {
17500 // op: vs2
17501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17502 op &= UINT64_C(31);
17503 op <<= 20;
17504 Value |= op;
17505 // op: rs1
17506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17507 op &= UINT64_C(31);
17508 op <<= 15;
17509 Value |= op;
17510 // op: vd
17511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17512 op &= UINT64_C(31);
17513 op <<= 7;
17514 Value |= op;
17515 break;
17516 }
17517 case RISCV::VAADDU_VX:
17518 case RISCV::VAADD_VX:
17519 case RISCV::VADD_VX:
17520 case RISCV::VANDN_VX:
17521 case RISCV::VAND_VX:
17522 case RISCV::VASUBU_VX:
17523 case RISCV::VASUB_VX:
17524 case RISCV::VCLMULH_VX:
17525 case RISCV::VCLMUL_VX:
17526 case RISCV::VDIVU_VX:
17527 case RISCV::VDIV_VX:
17528 case RISCV::VFADD_VF:
17529 case RISCV::VFDIV_VF:
17530 case RISCV::VFMAX_VF:
17531 case RISCV::VFMIN_VF:
17532 case RISCV::VFMUL_VF:
17533 case RISCV::VFNRCLIP_XU_F_QF:
17534 case RISCV::VFNRCLIP_X_F_QF:
17535 case RISCV::VFRDIV_VF:
17536 case RISCV::VFRSUB_VF:
17537 case RISCV::VFSGNJN_VF:
17538 case RISCV::VFSGNJX_VF:
17539 case RISCV::VFSGNJ_VF:
17540 case RISCV::VFSLIDE1DOWN_VF:
17541 case RISCV::VFSLIDE1UP_VF:
17542 case RISCV::VFSUB_VF:
17543 case RISCV::VFWADD_VF:
17544 case RISCV::VFWADD_WF:
17545 case RISCV::VFWMUL_VF:
17546 case RISCV::VFWSUB_VF:
17547 case RISCV::VFWSUB_WF:
17548 case RISCV::VMAXU_VX:
17549 case RISCV::VMAX_VX:
17550 case RISCV::VMFEQ_VF:
17551 case RISCV::VMFGE_VF:
17552 case RISCV::VMFGT_VF:
17553 case RISCV::VMFLE_VF:
17554 case RISCV::VMFLT_VF:
17555 case RISCV::VMFNE_VF:
17556 case RISCV::VMINU_VX:
17557 case RISCV::VMIN_VX:
17558 case RISCV::VMSEQ_VX:
17559 case RISCV::VMSGTU_VX:
17560 case RISCV::VMSGT_VX:
17561 case RISCV::VMSLEU_VX:
17562 case RISCV::VMSLE_VX:
17563 case RISCV::VMSLTU_VX:
17564 case RISCV::VMSLT_VX:
17565 case RISCV::VMSNE_VX:
17566 case RISCV::VMULHSU_VX:
17567 case RISCV::VMULHU_VX:
17568 case RISCV::VMULH_VX:
17569 case RISCV::VMUL_VX:
17570 case RISCV::VNCLIPU_WX:
17571 case RISCV::VNCLIP_WX:
17572 case RISCV::VNSRA_WX:
17573 case RISCV::VNSRL_WX:
17574 case RISCV::VOR_VX:
17575 case RISCV::VREMU_VX:
17576 case RISCV::VREM_VX:
17577 case RISCV::VRGATHER_VX:
17578 case RISCV::VROL_VX:
17579 case RISCV::VROR_VX:
17580 case RISCV::VRSUB_VX:
17581 case RISCV::VSADDU_VX:
17582 case RISCV::VSADD_VX:
17583 case RISCV::VSLIDE1DOWN_VX:
17584 case RISCV::VSLIDE1UP_VX:
17585 case RISCV::VSLIDEDOWN_VX:
17586 case RISCV::VSLIDEUP_VX:
17587 case RISCV::VSLL_VX:
17588 case RISCV::VSMUL_VX:
17589 case RISCV::VSRA_VX:
17590 case RISCV::VSRL_VX:
17591 case RISCV::VSSRA_VX:
17592 case RISCV::VSSRL_VX:
17593 case RISCV::VSSUBU_VX:
17594 case RISCV::VSSUB_VX:
17595 case RISCV::VSUB_VX:
17596 case RISCV::VWADDU_VX:
17597 case RISCV::VWADDU_WX:
17598 case RISCV::VWADD_VX:
17599 case RISCV::VWADD_WX:
17600 case RISCV::VWMULSU_VX:
17601 case RISCV::VWMULU_VX:
17602 case RISCV::VWMUL_VX:
17603 case RISCV::VWSLL_VX:
17604 case RISCV::VWSUBU_VX:
17605 case RISCV::VWSUBU_WX:
17606 case RISCV::VWSUB_VX:
17607 case RISCV::VWSUB_WX:
17608 case RISCV::VXOR_VX: {
17609 // op: vs2
17610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17611 op &= UINT64_C(31);
17612 op <<= 20;
17613 Value |= op;
17614 // op: rs1
17615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17616 op &= UINT64_C(31);
17617 op <<= 15;
17618 Value |= op;
17619 // op: vd
17620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17621 op &= UINT64_C(31);
17622 op <<= 7;
17623 Value |= op;
17624 // op: vm
17625 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
17626 op &= UINT64_C(1);
17627 op <<= 25;
17628 Value |= op;
17629 break;
17630 }
17631 case RISCV::VFMV_F_S:
17632 case RISCV::VMV1R_V:
17633 case RISCV::VMV2R_V:
17634 case RISCV::VMV4R_V:
17635 case RISCV::VMV8R_V:
17636 case RISCV::VMV_X_S: {
17637 // op: vs2
17638 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17639 op &= UINT64_C(31);
17640 op <<= 20;
17641 Value |= op;
17642 // op: vd
17643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17644 op &= UINT64_C(31);
17645 op <<= 7;
17646 Value |= op;
17647 break;
17648 }
17649 case RISCV::VBREV8_V:
17650 case RISCV::VBREV_V:
17651 case RISCV::VCLZ_V:
17652 case RISCV::VCPOP_M:
17653 case RISCV::VCPOP_V:
17654 case RISCV::VCTZ_V:
17655 case RISCV::VFCLASS_V:
17656 case RISCV::VFCVT_F_XU_V:
17657 case RISCV::VFCVT_F_X_V:
17658 case RISCV::VFCVT_RTZ_XU_F_V:
17659 case RISCV::VFCVT_RTZ_X_F_V:
17660 case RISCV::VFCVT_XU_F_V:
17661 case RISCV::VFCVT_X_F_V:
17662 case RISCV::VFIRST_M:
17663 case RISCV::VFNCVTBF16_F_F_W:
17664 case RISCV::VFNCVT_F_F_W:
17665 case RISCV::VFNCVT_F_XU_W:
17666 case RISCV::VFNCVT_F_X_W:
17667 case RISCV::VFNCVT_ROD_F_F_W:
17668 case RISCV::VFNCVT_RTZ_XU_F_W:
17669 case RISCV::VFNCVT_RTZ_X_F_W:
17670 case RISCV::VFNCVT_XU_F_W:
17671 case RISCV::VFNCVT_X_F_W:
17672 case RISCV::VFREC7_V:
17673 case RISCV::VFRSQRT7_V:
17674 case RISCV::VFSQRT_V:
17675 case RISCV::VFWCVTBF16_F_F_V:
17676 case RISCV::VFWCVT_F_F_V:
17677 case RISCV::VFWCVT_F_XU_V:
17678 case RISCV::VFWCVT_F_X_V:
17679 case RISCV::VFWCVT_RTZ_XU_F_V:
17680 case RISCV::VFWCVT_RTZ_X_F_V:
17681 case RISCV::VFWCVT_XU_F_V:
17682 case RISCV::VFWCVT_X_F_V:
17683 case RISCV::VIOTA_M:
17684 case RISCV::VMSBF_M:
17685 case RISCV::VMSIF_M:
17686 case RISCV::VMSOF_M:
17687 case RISCV::VREV8_V:
17688 case RISCV::VSEXT_VF2:
17689 case RISCV::VSEXT_VF4:
17690 case RISCV::VSEXT_VF8:
17691 case RISCV::VZEXT_VF2:
17692 case RISCV::VZEXT_VF4:
17693 case RISCV::VZEXT_VF8: {
17694 // op: vs2
17695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17696 op &= UINT64_C(31);
17697 op <<= 20;
17698 Value |= op;
17699 // op: vd
17700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17701 op &= UINT64_C(31);
17702 op <<= 7;
17703 Value |= op;
17704 // op: vm
17705 op = getVMaskReg(MI, OpNo: 2, Fixups, STI);
17706 op &= UINT64_C(1);
17707 op <<= 25;
17708 Value |= op;
17709 break;
17710 }
17711 case RISCV::VADC_VVM:
17712 case RISCV::VCOMPRESS_VM:
17713 case RISCV::VMADC_VV:
17714 case RISCV::VMADC_VVM:
17715 case RISCV::VMANDN_MM:
17716 case RISCV::VMAND_MM:
17717 case RISCV::VMERGE_VVM:
17718 case RISCV::VMNAND_MM:
17719 case RISCV::VMNOR_MM:
17720 case RISCV::VMORN_MM:
17721 case RISCV::VMOR_MM:
17722 case RISCV::VMSBC_VV:
17723 case RISCV::VMSBC_VVM:
17724 case RISCV::VMXNOR_MM:
17725 case RISCV::VMXOR_MM:
17726 case RISCV::VSBC_VVM:
17727 case RISCV::VSM3ME_VV: {
17728 // op: vs2
17729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17730 op &= UINT64_C(31);
17731 op <<= 20;
17732 Value |= op;
17733 // op: vs1
17734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17735 op &= UINT64_C(31);
17736 op <<= 15;
17737 Value |= op;
17738 // op: vd
17739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17740 op &= UINT64_C(31);
17741 op <<= 7;
17742 Value |= op;
17743 break;
17744 }
17745 case RISCV::VAADDU_VV:
17746 case RISCV::VAADD_VV:
17747 case RISCV::VADD_VV:
17748 case RISCV::VANDN_VV:
17749 case RISCV::VAND_VV:
17750 case RISCV::VASUBU_VV:
17751 case RISCV::VASUB_VV:
17752 case RISCV::VCLMULH_VV:
17753 case RISCV::VCLMUL_VV:
17754 case RISCV::VDIVU_VV:
17755 case RISCV::VDIV_VV:
17756 case RISCV::VFADD_VV:
17757 case RISCV::VFDIV_VV:
17758 case RISCV::VFMAX_VV:
17759 case RISCV::VFMIN_VV:
17760 case RISCV::VFMUL_VV:
17761 case RISCV::VFREDMAX_VS:
17762 case RISCV::VFREDMIN_VS:
17763 case RISCV::VFREDOSUM_VS:
17764 case RISCV::VFREDUSUM_VS:
17765 case RISCV::VFSGNJN_VV:
17766 case RISCV::VFSGNJX_VV:
17767 case RISCV::VFSGNJ_VV:
17768 case RISCV::VFSUB_VV:
17769 case RISCV::VFWADD_VV:
17770 case RISCV::VFWADD_WV:
17771 case RISCV::VFWMUL_VV:
17772 case RISCV::VFWREDOSUM_VS:
17773 case RISCV::VFWREDUSUM_VS:
17774 case RISCV::VFWSUB_VV:
17775 case RISCV::VFWSUB_WV:
17776 case RISCV::VMAXU_VV:
17777 case RISCV::VMAX_VV:
17778 case RISCV::VMFEQ_VV:
17779 case RISCV::VMFLE_VV:
17780 case RISCV::VMFLT_VV:
17781 case RISCV::VMFNE_VV:
17782 case RISCV::VMINU_VV:
17783 case RISCV::VMIN_VV:
17784 case RISCV::VMSEQ_VV:
17785 case RISCV::VMSLEU_VV:
17786 case RISCV::VMSLE_VV:
17787 case RISCV::VMSLTU_VV:
17788 case RISCV::VMSLT_VV:
17789 case RISCV::VMSNE_VV:
17790 case RISCV::VMULHSU_VV:
17791 case RISCV::VMULHU_VV:
17792 case RISCV::VMULH_VV:
17793 case RISCV::VMUL_VV:
17794 case RISCV::VNCLIPU_WV:
17795 case RISCV::VNCLIP_WV:
17796 case RISCV::VNSRA_WV:
17797 case RISCV::VNSRL_WV:
17798 case RISCV::VOR_VV:
17799 case RISCV::VREDAND_VS:
17800 case RISCV::VREDMAXU_VS:
17801 case RISCV::VREDMAX_VS:
17802 case RISCV::VREDMINU_VS:
17803 case RISCV::VREDMIN_VS:
17804 case RISCV::VREDOR_VS:
17805 case RISCV::VREDSUM_VS:
17806 case RISCV::VREDXOR_VS:
17807 case RISCV::VREMU_VV:
17808 case RISCV::VREM_VV:
17809 case RISCV::VRGATHEREI16_VV:
17810 case RISCV::VRGATHER_VV:
17811 case RISCV::VROL_VV:
17812 case RISCV::VROR_VV:
17813 case RISCV::VSADDU_VV:
17814 case RISCV::VSADD_VV:
17815 case RISCV::VSLL_VV:
17816 case RISCV::VSMUL_VV:
17817 case RISCV::VSRA_VV:
17818 case RISCV::VSRL_VV:
17819 case RISCV::VSSRA_VV:
17820 case RISCV::VSSRL_VV:
17821 case RISCV::VSSUBU_VV:
17822 case RISCV::VSSUB_VV:
17823 case RISCV::VSUB_VV:
17824 case RISCV::VWADDU_VV:
17825 case RISCV::VWADDU_WV:
17826 case RISCV::VWADD_VV:
17827 case RISCV::VWADD_WV:
17828 case RISCV::VWMULSU_VV:
17829 case RISCV::VWMULU_VV:
17830 case RISCV::VWMUL_VV:
17831 case RISCV::VWREDSUMU_VS:
17832 case RISCV::VWREDSUM_VS:
17833 case RISCV::VWSLL_VV:
17834 case RISCV::VWSUBU_VV:
17835 case RISCV::VWSUBU_WV:
17836 case RISCV::VWSUB_VV:
17837 case RISCV::VWSUB_WV:
17838 case RISCV::VXOR_VV: {
17839 // op: vs2
17840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17841 op &= UINT64_C(31);
17842 op <<= 20;
17843 Value |= op;
17844 // op: vs1
17845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17846 op &= UINT64_C(31);
17847 op <<= 15;
17848 Value |= op;
17849 // op: vd
17850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17851 op &= UINT64_C(31);
17852 op <<= 7;
17853 Value |= op;
17854 // op: vm
17855 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
17856 op &= UINT64_C(1);
17857 op <<= 25;
17858 Value |= op;
17859 break;
17860 }
17861 case RISCV::VAESKF2_VI:
17862 case RISCV::VSM3C_VI: {
17863 // op: vs2
17864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17865 op &= UINT64_C(31);
17866 op <<= 20;
17867 Value |= op;
17868 // op: imm
17869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17870 op &= UINT64_C(31);
17871 op <<= 15;
17872 Value |= op;
17873 // op: vd
17874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17875 op &= UINT64_C(31);
17876 op <<= 7;
17877 Value |= op;
17878 break;
17879 }
17880 case RISCV::VLOXEI8_V:
17881 case RISCV::VLOXEI16_V:
17882 case RISCV::VLOXEI32_V:
17883 case RISCV::VLOXEI64_V:
17884 case RISCV::VLOXSEG2EI8_V:
17885 case RISCV::VLOXSEG2EI16_V:
17886 case RISCV::VLOXSEG2EI32_V:
17887 case RISCV::VLOXSEG2EI64_V:
17888 case RISCV::VLOXSEG3EI8_V:
17889 case RISCV::VLOXSEG3EI16_V:
17890 case RISCV::VLOXSEG3EI32_V:
17891 case RISCV::VLOXSEG3EI64_V:
17892 case RISCV::VLOXSEG4EI8_V:
17893 case RISCV::VLOXSEG4EI16_V:
17894 case RISCV::VLOXSEG4EI32_V:
17895 case RISCV::VLOXSEG4EI64_V:
17896 case RISCV::VLOXSEG5EI8_V:
17897 case RISCV::VLOXSEG5EI16_V:
17898 case RISCV::VLOXSEG5EI32_V:
17899 case RISCV::VLOXSEG5EI64_V:
17900 case RISCV::VLOXSEG6EI8_V:
17901 case RISCV::VLOXSEG6EI16_V:
17902 case RISCV::VLOXSEG6EI32_V:
17903 case RISCV::VLOXSEG6EI64_V:
17904 case RISCV::VLOXSEG7EI8_V:
17905 case RISCV::VLOXSEG7EI16_V:
17906 case RISCV::VLOXSEG7EI32_V:
17907 case RISCV::VLOXSEG7EI64_V:
17908 case RISCV::VLOXSEG8EI8_V:
17909 case RISCV::VLOXSEG8EI16_V:
17910 case RISCV::VLOXSEG8EI32_V:
17911 case RISCV::VLOXSEG8EI64_V:
17912 case RISCV::VLUXEI8_V:
17913 case RISCV::VLUXEI16_V:
17914 case RISCV::VLUXEI32_V:
17915 case RISCV::VLUXEI64_V:
17916 case RISCV::VLUXSEG2EI8_V:
17917 case RISCV::VLUXSEG2EI16_V:
17918 case RISCV::VLUXSEG2EI32_V:
17919 case RISCV::VLUXSEG2EI64_V:
17920 case RISCV::VLUXSEG3EI8_V:
17921 case RISCV::VLUXSEG3EI16_V:
17922 case RISCV::VLUXSEG3EI32_V:
17923 case RISCV::VLUXSEG3EI64_V:
17924 case RISCV::VLUXSEG4EI8_V:
17925 case RISCV::VLUXSEG4EI16_V:
17926 case RISCV::VLUXSEG4EI32_V:
17927 case RISCV::VLUXSEG4EI64_V:
17928 case RISCV::VLUXSEG5EI8_V:
17929 case RISCV::VLUXSEG5EI16_V:
17930 case RISCV::VLUXSEG5EI32_V:
17931 case RISCV::VLUXSEG5EI64_V:
17932 case RISCV::VLUXSEG6EI8_V:
17933 case RISCV::VLUXSEG6EI16_V:
17934 case RISCV::VLUXSEG6EI32_V:
17935 case RISCV::VLUXSEG6EI64_V:
17936 case RISCV::VLUXSEG7EI8_V:
17937 case RISCV::VLUXSEG7EI16_V:
17938 case RISCV::VLUXSEG7EI32_V:
17939 case RISCV::VLUXSEG7EI64_V:
17940 case RISCV::VLUXSEG8EI8_V:
17941 case RISCV::VLUXSEG8EI16_V:
17942 case RISCV::VLUXSEG8EI32_V:
17943 case RISCV::VLUXSEG8EI64_V: {
17944 // op: vs2
17945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17946 op &= UINT64_C(31);
17947 op <<= 20;
17948 Value |= op;
17949 // op: rs1
17950 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17951 op &= UINT64_C(31);
17952 op <<= 15;
17953 Value |= op;
17954 // op: vd
17955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17956 op &= UINT64_C(31);
17957 op <<= 7;
17958 Value |= op;
17959 // op: vm
17960 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
17961 op &= UINT64_C(1);
17962 op <<= 25;
17963 Value |= op;
17964 break;
17965 }
17966 case RISCV::VSOXEI8_V:
17967 case RISCV::VSOXEI16_V:
17968 case RISCV::VSOXEI32_V:
17969 case RISCV::VSOXEI64_V:
17970 case RISCV::VSOXSEG2EI8_V:
17971 case RISCV::VSOXSEG2EI16_V:
17972 case RISCV::VSOXSEG2EI32_V:
17973 case RISCV::VSOXSEG2EI64_V:
17974 case RISCV::VSOXSEG3EI8_V:
17975 case RISCV::VSOXSEG3EI16_V:
17976 case RISCV::VSOXSEG3EI32_V:
17977 case RISCV::VSOXSEG3EI64_V:
17978 case RISCV::VSOXSEG4EI8_V:
17979 case RISCV::VSOXSEG4EI16_V:
17980 case RISCV::VSOXSEG4EI32_V:
17981 case RISCV::VSOXSEG4EI64_V:
17982 case RISCV::VSOXSEG5EI8_V:
17983 case RISCV::VSOXSEG5EI16_V:
17984 case RISCV::VSOXSEG5EI32_V:
17985 case RISCV::VSOXSEG5EI64_V:
17986 case RISCV::VSOXSEG6EI8_V:
17987 case RISCV::VSOXSEG6EI16_V:
17988 case RISCV::VSOXSEG6EI32_V:
17989 case RISCV::VSOXSEG6EI64_V:
17990 case RISCV::VSOXSEG7EI8_V:
17991 case RISCV::VSOXSEG7EI16_V:
17992 case RISCV::VSOXSEG7EI32_V:
17993 case RISCV::VSOXSEG7EI64_V:
17994 case RISCV::VSOXSEG8EI8_V:
17995 case RISCV::VSOXSEG8EI16_V:
17996 case RISCV::VSOXSEG8EI32_V:
17997 case RISCV::VSOXSEG8EI64_V:
17998 case RISCV::VSUXEI8_V:
17999 case RISCV::VSUXEI16_V:
18000 case RISCV::VSUXEI32_V:
18001 case RISCV::VSUXEI64_V:
18002 case RISCV::VSUXSEG2EI8_V:
18003 case RISCV::VSUXSEG2EI16_V:
18004 case RISCV::VSUXSEG2EI32_V:
18005 case RISCV::VSUXSEG2EI64_V:
18006 case RISCV::VSUXSEG3EI8_V:
18007 case RISCV::VSUXSEG3EI16_V:
18008 case RISCV::VSUXSEG3EI32_V:
18009 case RISCV::VSUXSEG3EI64_V:
18010 case RISCV::VSUXSEG4EI8_V:
18011 case RISCV::VSUXSEG4EI16_V:
18012 case RISCV::VSUXSEG4EI32_V:
18013 case RISCV::VSUXSEG4EI64_V:
18014 case RISCV::VSUXSEG5EI8_V:
18015 case RISCV::VSUXSEG5EI16_V:
18016 case RISCV::VSUXSEG5EI32_V:
18017 case RISCV::VSUXSEG5EI64_V:
18018 case RISCV::VSUXSEG6EI8_V:
18019 case RISCV::VSUXSEG6EI16_V:
18020 case RISCV::VSUXSEG6EI32_V:
18021 case RISCV::VSUXSEG6EI64_V:
18022 case RISCV::VSUXSEG7EI8_V:
18023 case RISCV::VSUXSEG7EI16_V:
18024 case RISCV::VSUXSEG7EI32_V:
18025 case RISCV::VSUXSEG7EI64_V:
18026 case RISCV::VSUXSEG8EI8_V:
18027 case RISCV::VSUXSEG8EI16_V:
18028 case RISCV::VSUXSEG8EI32_V:
18029 case RISCV::VSUXSEG8EI64_V: {
18030 // op: vs2
18031 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18032 op &= UINT64_C(31);
18033 op <<= 20;
18034 Value |= op;
18035 // op: rs1
18036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18037 op &= UINT64_C(31);
18038 op <<= 15;
18039 Value |= op;
18040 // op: vs3
18041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18042 op &= UINT64_C(31);
18043 op <<= 7;
18044 Value |= op;
18045 // op: vm
18046 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
18047 op &= UINT64_C(1);
18048 op <<= 25;
18049 Value |= op;
18050 break;
18051 }
18052 case RISCV::VAESDF_VS:
18053 case RISCV::VAESDF_VV:
18054 case RISCV::VAESDM_VS:
18055 case RISCV::VAESDM_VV:
18056 case RISCV::VAESEF_VS:
18057 case RISCV::VAESEF_VV:
18058 case RISCV::VAESEM_VS:
18059 case RISCV::VAESEM_VV:
18060 case RISCV::VAESZ_VS:
18061 case RISCV::VGMUL_VV:
18062 case RISCV::VSM4R_VS:
18063 case RISCV::VSM4R_VV: {
18064 // op: vs2
18065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18066 op &= UINT64_C(31);
18067 op <<= 20;
18068 Value |= op;
18069 // op: vd
18070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18071 op &= UINT64_C(31);
18072 op <<= 7;
18073 Value |= op;
18074 break;
18075 }
18076 case RISCV::VGHSH_VV:
18077 case RISCV::VSHA2CH_VV:
18078 case RISCV::VSHA2CL_VV:
18079 case RISCV::VSHA2MS_VV: {
18080 // op: vs2
18081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18082 op &= UINT64_C(31);
18083 op <<= 20;
18084 Value |= op;
18085 // op: vs1
18086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18087 op &= UINT64_C(31);
18088 op <<= 15;
18089 Value |= op;
18090 // op: vd
18091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18092 op &= UINT64_C(31);
18093 op <<= 7;
18094 Value |= op;
18095 break;
18096 }
18097 case RISCV::THVdotVMAQASU_VX:
18098 case RISCV::THVdotVMAQAUS_VX:
18099 case RISCV::THVdotVMAQAU_VX:
18100 case RISCV::THVdotVMAQA_VX:
18101 case RISCV::VFMACC_VF:
18102 case RISCV::VFMADD_VF:
18103 case RISCV::VFMSAC_VF:
18104 case RISCV::VFMSUB_VF:
18105 case RISCV::VFNMACC_VF:
18106 case RISCV::VFNMADD_VF:
18107 case RISCV::VFNMSAC_VF:
18108 case RISCV::VFNMSUB_VF:
18109 case RISCV::VFWMACCBF16_VF:
18110 case RISCV::VFWMACC_VF:
18111 case RISCV::VFWMSAC_VF:
18112 case RISCV::VFWNMACC_VF:
18113 case RISCV::VFWNMSAC_VF:
18114 case RISCV::VMACC_VX:
18115 case RISCV::VMADD_VX:
18116 case RISCV::VNMSAC_VX:
18117 case RISCV::VNMSUB_VX:
18118 case RISCV::VWMACCSU_VX:
18119 case RISCV::VWMACCUS_VX:
18120 case RISCV::VWMACCU_VX:
18121 case RISCV::VWMACC_VX: {
18122 // op: vs2
18123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18124 op &= UINT64_C(31);
18125 op <<= 20;
18126 Value |= op;
18127 // op: rs1
18128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18129 op &= UINT64_C(31);
18130 op <<= 15;
18131 Value |= op;
18132 // op: vd
18133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18134 op &= UINT64_C(31);
18135 op <<= 7;
18136 Value |= op;
18137 // op: vm
18138 op = getVMaskReg(MI, OpNo: 4, Fixups, STI);
18139 op &= UINT64_C(1);
18140 op <<= 25;
18141 Value |= op;
18142 break;
18143 }
18144 case RISCV::THVdotVMAQASU_VV:
18145 case RISCV::THVdotVMAQAU_VV:
18146 case RISCV::THVdotVMAQA_VV:
18147 case RISCV::VFMACC_VV:
18148 case RISCV::VFMADD_VV:
18149 case RISCV::VFMSAC_VV:
18150 case RISCV::VFMSUB_VV:
18151 case RISCV::VFNMACC_VV:
18152 case RISCV::VFNMADD_VV:
18153 case RISCV::VFNMSAC_VV:
18154 case RISCV::VFNMSUB_VV:
18155 case RISCV::VFWMACCBF16_VV:
18156 case RISCV::VFWMACC_VV:
18157 case RISCV::VFWMSAC_VV:
18158 case RISCV::VFWNMACC_VV:
18159 case RISCV::VFWNMSAC_VV:
18160 case RISCV::VMACC_VV:
18161 case RISCV::VMADD_VV:
18162 case RISCV::VNMSAC_VV:
18163 case RISCV::VNMSUB_VV:
18164 case RISCV::VWMACCSU_VV:
18165 case RISCV::VWMACCU_VV:
18166 case RISCV::VWMACC_VV: {
18167 // op: vs2
18168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18169 op &= UINT64_C(31);
18170 op <<= 20;
18171 Value |= op;
18172 // op: vs1
18173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18174 op &= UINT64_C(31);
18175 op <<= 15;
18176 Value |= op;
18177 // op: vd
18178 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18179 op &= UINT64_C(31);
18180 op <<= 7;
18181 Value |= op;
18182 // op: vm
18183 op = getVMaskReg(MI, OpNo: 4, Fixups, STI);
18184 op &= UINT64_C(1);
18185 op <<= 25;
18186 Value |= op;
18187 break;
18188 }
18189 default:
18190 std::string msg;
18191 raw_string_ostream Msg(msg);
18192 Msg << "Not supported instr: " << MI;
18193 report_fatal_error(reason: Msg.str().c_str());
18194 }
18195 return Value;
18196}
18197
18198#ifdef GET_OPERAND_BIT_OFFSET
18199#undef GET_OPERAND_BIT_OFFSET
18200
18201uint32_t RISCVMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
18202 unsigned OpNum,
18203 const MCSubtargetInfo &STI) const {
18204 switch (MI.getOpcode()) {
18205 case RISCV::C_EBREAK:
18206 case RISCV::C_MOP1:
18207 case RISCV::C_MOP3:
18208 case RISCV::C_MOP5:
18209 case RISCV::C_MOP7:
18210 case RISCV::C_MOP9:
18211 case RISCV::C_MOP11:
18212 case RISCV::C_MOP13:
18213 case RISCV::C_MOP15:
18214 case RISCV::C_NOP:
18215 case RISCV::C_SSPOPCHK:
18216 case RISCV::C_SSPUSH:
18217 case RISCV::C_UNIMP:
18218 case RISCV::DRET:
18219 case RISCV::EBREAK:
18220 case RISCV::ECALL:
18221 case RISCV::FENCE_I:
18222 case RISCV::FENCE_TSO:
18223 case RISCV::MRET:
18224 case RISCV::SFENCE_INVAL_IR:
18225 case RISCV::SFENCE_W_INVAL:
18226 case RISCV::SF_CEASE:
18227 case RISCV::SRET:
18228 case RISCV::TH_DCACHE_CALL:
18229 case RISCV::TH_DCACHE_CIALL:
18230 case RISCV::TH_DCACHE_IALL:
18231 case RISCV::TH_ICACHE_IALL:
18232 case RISCV::TH_ICACHE_IALLS:
18233 case RISCV::TH_L2CACHE_CALL:
18234 case RISCV::TH_L2CACHE_CIALL:
18235 case RISCV::TH_L2CACHE_IALL:
18236 case RISCV::TH_SYNC:
18237 case RISCV::TH_SYNC_I:
18238 case RISCV::TH_SYNC_IS:
18239 case RISCV::TH_SYNC_S:
18240 case RISCV::UNIMP:
18241 case RISCV::WFI:
18242 case RISCV::WRS_NTO:
18243 case RISCV::WRS_STO: {
18244 break;
18245 }
18246 case RISCV::C_NOP_HINT: {
18247 switch (OpNum) {
18248 case 0:
18249 // op: imm
18250 return 2;
18251 }
18252 break;
18253 }
18254 case RISCV::CM_JALT:
18255 case RISCV::CM_JT: {
18256 switch (OpNum) {
18257 case 0:
18258 // op: index
18259 return 2;
18260 }
18261 break;
18262 }
18263 case RISCV::C_J:
18264 case RISCV::C_JAL: {
18265 switch (OpNum) {
18266 case 0:
18267 // op: offset
18268 return 2;
18269 }
18270 break;
18271 }
18272 case RISCV::InsnS: {
18273 switch (OpNum) {
18274 case 0:
18275 // op: opcode
18276 return 0;
18277 case 1:
18278 // op: funct3
18279 return 12;
18280 case 4:
18281 // op: imm12
18282 return 7;
18283 case 2:
18284 // op: rs2
18285 return 20;
18286 case 3:
18287 // op: rs1
18288 return 15;
18289 }
18290 break;
18291 }
18292 case RISCV::InsnB: {
18293 switch (OpNum) {
18294 case 0:
18295 // op: opcode
18296 return 0;
18297 case 1:
18298 // op: funct3
18299 return 12;
18300 case 4:
18301 // op: imm12
18302 return 7;
18303 case 3:
18304 // op: rs2
18305 return 20;
18306 case 2:
18307 // op: rs1
18308 return 15;
18309 }
18310 break;
18311 }
18312 case RISCV::InsnCJ: {
18313 switch (OpNum) {
18314 case 0:
18315 // op: opcode
18316 return 0;
18317 case 1:
18318 // op: funct3
18319 return 13;
18320 case 2:
18321 // op: imm11
18322 return 2;
18323 }
18324 break;
18325 }
18326 case RISCV::InsnCSS: {
18327 switch (OpNum) {
18328 case 0:
18329 // op: opcode
18330 return 0;
18331 case 1:
18332 // op: funct3
18333 return 13;
18334 case 3:
18335 // op: imm6
18336 return 7;
18337 case 2:
18338 // op: rs2
18339 return 2;
18340 }
18341 break;
18342 }
18343 case RISCV::InsnCB: {
18344 switch (OpNum) {
18345 case 0:
18346 // op: opcode
18347 return 0;
18348 case 1:
18349 // op: funct3
18350 return 13;
18351 case 3:
18352 // op: imm8
18353 return 2;
18354 case 2:
18355 // op: rs1
18356 return 7;
18357 }
18358 break;
18359 }
18360 case RISCV::InsnCS: {
18361 switch (OpNum) {
18362 case 0:
18363 // op: opcode
18364 return 0;
18365 case 1:
18366 // op: funct3
18367 return 13;
18368 case 4:
18369 // op: imm5
18370 return 5;
18371 case 2:
18372 // op: rs2
18373 return 2;
18374 case 3:
18375 // op: rs1
18376 return 7;
18377 }
18378 break;
18379 }
18380 case RISCV::FENCE: {
18381 switch (OpNum) {
18382 case 0:
18383 // op: pred
18384 return 24;
18385 case 1:
18386 // op: succ
18387 return 20;
18388 }
18389 break;
18390 }
18391 case RISCV::C_FLD:
18392 case RISCV::C_FLW:
18393 case RISCV::C_LBU:
18394 case RISCV::C_LD:
18395 case RISCV::C_LH:
18396 case RISCV::C_LHU:
18397 case RISCV::C_LW:
18398 case RISCV::QK_C_LBU:
18399 case RISCV::QK_C_LHU: {
18400 switch (OpNum) {
18401 case 0:
18402 // op: rd
18403 return 2;
18404 case 1:
18405 // op: rs1
18406 return 7;
18407 case 2:
18408 // op: imm
18409 return 5;
18410 }
18411 break;
18412 }
18413 case RISCV::CV_LBU_rr:
18414 case RISCV::CV_LB_rr:
18415 case RISCV::CV_LHU_rr:
18416 case RISCV::CV_LH_rr:
18417 case RISCV::CV_LW_rr: {
18418 switch (OpNum) {
18419 case 0:
18420 // op: rd
18421 return 7;
18422 case 1:
18423 // op: cvrr
18424 return 15;
18425 }
18426 break;
18427 }
18428 case RISCV::FLI_D:
18429 case RISCV::FLI_H:
18430 case RISCV::FLI_S: {
18431 switch (OpNum) {
18432 case 0:
18433 // op: rd
18434 return 7;
18435 case 1:
18436 // op: imm
18437 return 15;
18438 }
18439 break;
18440 }
18441 case RISCV::SSRDP: {
18442 switch (OpNum) {
18443 case 0:
18444 // op: rd
18445 return 7;
18446 }
18447 break;
18448 }
18449 case RISCV::QK_C_LBUSP:
18450 case RISCV::QK_C_LHUSP:
18451 case RISCV::QK_C_SBSP:
18452 case RISCV::QK_C_SHSP: {
18453 switch (OpNum) {
18454 case 0:
18455 // op: rd_rs2
18456 return 2;
18457 case 2:
18458 // op: imm
18459 return 7;
18460 }
18461 break;
18462 }
18463 case RISCV::CM_POP:
18464 case RISCV::CM_POPRET:
18465 case RISCV::CM_POPRETZ:
18466 case RISCV::CM_PUSH: {
18467 switch (OpNum) {
18468 case 0:
18469 // op: rlist
18470 return 4;
18471 case 1:
18472 // op: stackadj
18473 return 2;
18474 }
18475 break;
18476 }
18477 case RISCV::CBO_CLEAN:
18478 case RISCV::CBO_FLUSH:
18479 case RISCV::CBO_INVAL:
18480 case RISCV::CBO_ZERO:
18481 case RISCV::SF_CDISCARD_D_L1:
18482 case RISCV::SF_CFLUSH_D_L1:
18483 case RISCV::SSPOPCHK:
18484 case RISCV::TH_DCACHE_CIPA:
18485 case RISCV::TH_DCACHE_CISW:
18486 case RISCV::TH_DCACHE_CIVA:
18487 case RISCV::TH_DCACHE_CPA:
18488 case RISCV::TH_DCACHE_CPAL1:
18489 case RISCV::TH_DCACHE_CSW:
18490 case RISCV::TH_DCACHE_CVA:
18491 case RISCV::TH_DCACHE_CVAL1:
18492 case RISCV::TH_DCACHE_IPA:
18493 case RISCV::TH_DCACHE_ISW:
18494 case RISCV::TH_DCACHE_IVA:
18495 case RISCV::TH_ICACHE_IPA:
18496 case RISCV::TH_ICACHE_IVA: {
18497 switch (OpNum) {
18498 case 0:
18499 // op: rs1
18500 return 15;
18501 }
18502 break;
18503 }
18504 case RISCV::C_MV: {
18505 switch (OpNum) {
18506 case 0:
18507 // op: rs1
18508 return 7;
18509 case 1:
18510 // op: rs2
18511 return 2;
18512 }
18513 break;
18514 }
18515 case RISCV::C_JALR:
18516 case RISCV::C_JR: {
18517 switch (OpNum) {
18518 case 0:
18519 // op: rs1
18520 return 7;
18521 }
18522 break;
18523 }
18524 case RISCV::CV_SB_rr:
18525 case RISCV::CV_SH_rr:
18526 case RISCV::CV_SW_rr: {
18527 switch (OpNum) {
18528 case 0:
18529 // op: rs2
18530 return 20;
18531 case 1:
18532 // op: cvrr
18533 return 7;
18534 }
18535 break;
18536 }
18537 case RISCV::HSV_B:
18538 case RISCV::HSV_D:
18539 case RISCV::HSV_H:
18540 case RISCV::HSV_W: {
18541 switch (OpNum) {
18542 case 0:
18543 // op: rs2
18544 return 20;
18545 case 1:
18546 // op: rs1
18547 return 15;
18548 }
18549 break;
18550 }
18551 case RISCV::SSPUSH: {
18552 switch (OpNum) {
18553 case 0:
18554 // op: rs2
18555 return 20;
18556 }
18557 break;
18558 }
18559 case RISCV::C_FSD:
18560 case RISCV::C_FSW:
18561 case RISCV::C_SB:
18562 case RISCV::C_SD:
18563 case RISCV::C_SH:
18564 case RISCV::C_SW:
18565 case RISCV::QK_C_SB:
18566 case RISCV::QK_C_SH: {
18567 switch (OpNum) {
18568 case 0:
18569 // op: rs2
18570 return 2;
18571 case 1:
18572 // op: rs1
18573 return 7;
18574 case 2:
18575 // op: imm
18576 return 5;
18577 }
18578 break;
18579 }
18580 case RISCV::Insn16:
18581 case RISCV::Insn32: {
18582 switch (OpNum) {
18583 case 0:
18584 // op: value
18585 return 0;
18586 }
18587 break;
18588 }
18589 case RISCV::VID_V: {
18590 switch (OpNum) {
18591 case 0:
18592 // op: vd
18593 return 7;
18594 case 1:
18595 // op: vm
18596 return 25;
18597 }
18598 break;
18599 }
18600 case RISCV::VMV_V_I: {
18601 switch (OpNum) {
18602 case 1:
18603 // op: imm
18604 return 15;
18605 case 0:
18606 // op: vd
18607 return 7;
18608 }
18609 break;
18610 }
18611 case RISCV::C_LI:
18612 case RISCV::C_LUI: {
18613 switch (OpNum) {
18614 case 1:
18615 // op: imm
18616 return 2;
18617 case 0:
18618 // op: rd
18619 return 7;
18620 }
18621 break;
18622 }
18623 case RISCV::C_BEQZ:
18624 case RISCV::C_BNEZ: {
18625 switch (OpNum) {
18626 case 1:
18627 // op: imm
18628 return 2;
18629 case 0:
18630 // op: rs1
18631 return 7;
18632 }
18633 break;
18634 }
18635 case RISCV::C_LI_HINT:
18636 case RISCV::C_LUI_HINT: {
18637 switch (OpNum) {
18638 case 1:
18639 // op: imm
18640 return 2;
18641 }
18642 break;
18643 }
18644 case RISCV::PREFETCH_I:
18645 case RISCV::PREFETCH_R:
18646 case RISCV::PREFETCH_W: {
18647 switch (OpNum) {
18648 case 1:
18649 // op: imm12
18650 return 25;
18651 case 0:
18652 // op: rs1
18653 return 15;
18654 }
18655 break;
18656 }
18657 case RISCV::AUIPC:
18658 case RISCV::JAL:
18659 case RISCV::LUI: {
18660 switch (OpNum) {
18661 case 1:
18662 // op: imm20
18663 return 12;
18664 case 0:
18665 // op: rd
18666 return 7;
18667 }
18668 break;
18669 }
18670 case RISCV::InsnI:
18671 case RISCV::InsnI_Mem: {
18672 switch (OpNum) {
18673 case 1:
18674 // op: opcode
18675 return 0;
18676 case 2:
18677 // op: funct3
18678 return 12;
18679 case 4:
18680 // op: imm12
18681 return 20;
18682 case 3:
18683 // op: rs1
18684 return 15;
18685 case 0:
18686 // op: rd
18687 return 7;
18688 }
18689 break;
18690 }
18691 case RISCV::InsnCI: {
18692 switch (OpNum) {
18693 case 1:
18694 // op: opcode
18695 return 0;
18696 case 2:
18697 // op: funct3
18698 return 13;
18699 case 3:
18700 // op: imm6
18701 return 2;
18702 case 0:
18703 // op: rd
18704 return 7;
18705 }
18706 break;
18707 }
18708 case RISCV::InsnCIW: {
18709 switch (OpNum) {
18710 case 1:
18711 // op: opcode
18712 return 0;
18713 case 2:
18714 // op: funct3
18715 return 13;
18716 case 3:
18717 // op: imm8
18718 return 5;
18719 case 0:
18720 // op: rd
18721 return 2;
18722 }
18723 break;
18724 }
18725 case RISCV::InsnCL: {
18726 switch (OpNum) {
18727 case 1:
18728 // op: opcode
18729 return 0;
18730 case 2:
18731 // op: funct3
18732 return 13;
18733 case 4:
18734 // op: imm5
18735 return 5;
18736 case 0:
18737 // op: rd
18738 return 2;
18739 case 3:
18740 // op: rs1
18741 return 7;
18742 }
18743 break;
18744 }
18745 case RISCV::InsnCR: {
18746 switch (OpNum) {
18747 case 1:
18748 // op: opcode
18749 return 0;
18750 case 2:
18751 // op: funct4
18752 return 12;
18753 case 3:
18754 // op: rs2
18755 return 2;
18756 case 0:
18757 // op: rd
18758 return 7;
18759 }
18760 break;
18761 }
18762 case RISCV::InsnCA: {
18763 switch (OpNum) {
18764 case 1:
18765 // op: opcode
18766 return 0;
18767 case 2:
18768 // op: funct6
18769 return 10;
18770 case 3:
18771 // op: funct2
18772 return 5;
18773 case 0:
18774 // op: rd
18775 return 7;
18776 case 4:
18777 // op: rs2
18778 return 2;
18779 }
18780 break;
18781 }
18782 case RISCV::InsnJ:
18783 case RISCV::InsnU: {
18784 switch (OpNum) {
18785 case 1:
18786 // op: opcode
18787 return 0;
18788 case 2:
18789 // op: imm20
18790 return 12;
18791 case 0:
18792 // op: rd
18793 return 7;
18794 }
18795 break;
18796 }
18797 case RISCV::InsnR4: {
18798 switch (OpNum) {
18799 case 1:
18800 // op: opcode
18801 return 0;
18802 case 3:
18803 // op: funct2
18804 return 25;
18805 case 2:
18806 // op: funct3
18807 return 12;
18808 case 6:
18809 // op: rs3
18810 return 27;
18811 case 5:
18812 // op: rs2
18813 return 20;
18814 case 4:
18815 // op: rs1
18816 return 15;
18817 case 0:
18818 // op: rd
18819 return 7;
18820 }
18821 break;
18822 }
18823 case RISCV::InsnR: {
18824 switch (OpNum) {
18825 case 1:
18826 // op: opcode
18827 return 0;
18828 case 3:
18829 // op: funct7
18830 return 25;
18831 case 2:
18832 // op: funct3
18833 return 12;
18834 case 5:
18835 // op: rs2
18836 return 20;
18837 case 4:
18838 // op: rs1
18839 return 15;
18840 case 0:
18841 // op: rd
18842 return 7;
18843 }
18844 break;
18845 }
18846 case RISCV::C_ADDI_HINT_IMM_ZERO:
18847 case RISCV::C_NOT:
18848 case RISCV::C_SEXT_B:
18849 case RISCV::C_SEXT_H:
18850 case RISCV::C_SLLI64_HINT:
18851 case RISCV::C_SRAI64_HINT:
18852 case RISCV::C_SRLI64_HINT:
18853 case RISCV::C_ZEXT_B:
18854 case RISCV::C_ZEXT_H:
18855 case RISCV::C_ZEXT_W: {
18856 switch (OpNum) {
18857 case 1:
18858 // op: rd
18859 return 7;
18860 }
18861 break;
18862 }
18863 case RISCV::ADDI:
18864 case RISCV::ADDIW:
18865 case RISCV::ANDI:
18866 case RISCV::CV_ELW:
18867 case RISCV::FLD:
18868 case RISCV::FLH:
18869 case RISCV::FLW:
18870 case RISCV::JALR:
18871 case RISCV::LB:
18872 case RISCV::LBU:
18873 case RISCV::LD:
18874 case RISCV::LH:
18875 case RISCV::LHU:
18876 case RISCV::LW:
18877 case RISCV::LWU:
18878 case RISCV::ORI:
18879 case RISCV::SLTI:
18880 case RISCV::SLTIU:
18881 case RISCV::XORI: {
18882 switch (OpNum) {
18883 case 1:
18884 // op: rs1
18885 return 15;
18886 case 0:
18887 // op: rd
18888 return 7;
18889 case 2:
18890 // op: imm12
18891 return 20;
18892 }
18893 break;
18894 }
18895 case RISCV::CV_CLIP:
18896 case RISCV::CV_CLIPU: {
18897 switch (OpNum) {
18898 case 1:
18899 // op: rs1
18900 return 15;
18901 case 0:
18902 // op: rd
18903 return 7;
18904 case 2:
18905 // op: imm5
18906 return 20;
18907 }
18908 break;
18909 }
18910 case RISCV::CV_ADD_SCI_B:
18911 case RISCV::CV_ADD_SCI_H:
18912 case RISCV::CV_AND_SCI_B:
18913 case RISCV::CV_AND_SCI_H:
18914 case RISCV::CV_AVGU_SCI_B:
18915 case RISCV::CV_AVGU_SCI_H:
18916 case RISCV::CV_AVG_SCI_B:
18917 case RISCV::CV_AVG_SCI_H:
18918 case RISCV::CV_CMPEQ_SCI_B:
18919 case RISCV::CV_CMPEQ_SCI_H:
18920 case RISCV::CV_CMPGEU_SCI_B:
18921 case RISCV::CV_CMPGEU_SCI_H:
18922 case RISCV::CV_CMPGE_SCI_B:
18923 case RISCV::CV_CMPGE_SCI_H:
18924 case RISCV::CV_CMPGTU_SCI_B:
18925 case RISCV::CV_CMPGTU_SCI_H:
18926 case RISCV::CV_CMPGT_SCI_B:
18927 case RISCV::CV_CMPGT_SCI_H:
18928 case RISCV::CV_CMPLEU_SCI_B:
18929 case RISCV::CV_CMPLEU_SCI_H:
18930 case RISCV::CV_CMPLE_SCI_B:
18931 case RISCV::CV_CMPLE_SCI_H:
18932 case RISCV::CV_CMPLTU_SCI_B:
18933 case RISCV::CV_CMPLTU_SCI_H:
18934 case RISCV::CV_CMPLT_SCI_B:
18935 case RISCV::CV_CMPLT_SCI_H:
18936 case RISCV::CV_CMPNE_SCI_B:
18937 case RISCV::CV_CMPNE_SCI_H:
18938 case RISCV::CV_DOTSP_SCI_B:
18939 case RISCV::CV_DOTSP_SCI_H:
18940 case RISCV::CV_DOTUP_SCI_B:
18941 case RISCV::CV_DOTUP_SCI_H:
18942 case RISCV::CV_DOTUSP_SCI_B:
18943 case RISCV::CV_DOTUSP_SCI_H:
18944 case RISCV::CV_EXTRACTU_B:
18945 case RISCV::CV_EXTRACTU_H:
18946 case RISCV::CV_EXTRACT_B:
18947 case RISCV::CV_EXTRACT_H:
18948 case RISCV::CV_MAXU_SCI_B:
18949 case RISCV::CV_MAXU_SCI_H:
18950 case RISCV::CV_MAX_SCI_B:
18951 case RISCV::CV_MAX_SCI_H:
18952 case RISCV::CV_MINU_SCI_B:
18953 case RISCV::CV_MINU_SCI_H:
18954 case RISCV::CV_MIN_SCI_B:
18955 case RISCV::CV_MIN_SCI_H:
18956 case RISCV::CV_OR_SCI_B:
18957 case RISCV::CV_OR_SCI_H:
18958 case RISCV::CV_SHUFFLEI0_SCI_B:
18959 case RISCV::CV_SHUFFLEI1_SCI_B:
18960 case RISCV::CV_SHUFFLEI2_SCI_B:
18961 case RISCV::CV_SHUFFLEI3_SCI_B:
18962 case RISCV::CV_SHUFFLE_SCI_H:
18963 case RISCV::CV_SLL_SCI_B:
18964 case RISCV::CV_SLL_SCI_H:
18965 case RISCV::CV_SRA_SCI_B:
18966 case RISCV::CV_SRA_SCI_H:
18967 case RISCV::CV_SRL_SCI_B:
18968 case RISCV::CV_SRL_SCI_H:
18969 case RISCV::CV_SUB_SCI_B:
18970 case RISCV::CV_SUB_SCI_H:
18971 case RISCV::CV_XOR_SCI_B:
18972 case RISCV::CV_XOR_SCI_H: {
18973 switch (OpNum) {
18974 case 1:
18975 // op: rs1
18976 return 15;
18977 case 0:
18978 // op: rd
18979 return 7;
18980 case 2:
18981 // op: imm6
18982 return 20;
18983 }
18984 break;
18985 }
18986 case RISCV::CV_BCLR:
18987 case RISCV::CV_BITREV:
18988 case RISCV::CV_BSET:
18989 case RISCV::CV_EXTRACT:
18990 case RISCV::CV_EXTRACTU: {
18991 switch (OpNum) {
18992 case 1:
18993 // op: rs1
18994 return 15;
18995 case 0:
18996 // op: rd
18997 return 7;
18998 case 2:
18999 // op: is3
19000 return 25;
19001 case 3:
19002 // op: is2
19003 return 20;
19004 }
19005 break;
19006 }
19007 case RISCV::TH_EXT:
19008 case RISCV::TH_EXTU: {
19009 switch (OpNum) {
19010 case 1:
19011 // op: rs1
19012 return 15;
19013 case 0:
19014 // op: rd
19015 return 7;
19016 case 2:
19017 // op: msb
19018 return 26;
19019 case 3:
19020 // op: lsb
19021 return 20;
19022 }
19023 break;
19024 }
19025 case RISCV::AES64KS1I: {
19026 switch (OpNum) {
19027 case 1:
19028 // op: rs1
19029 return 15;
19030 case 0:
19031 // op: rd
19032 return 7;
19033 case 2:
19034 // op: rnum
19035 return 20;
19036 }
19037 break;
19038 }
19039 case RISCV::BCLRI:
19040 case RISCV::BEXTI:
19041 case RISCV::BINVI:
19042 case RISCV::BSETI:
19043 case RISCV::RORI:
19044 case RISCV::RORIW:
19045 case RISCV::SLLI:
19046 case RISCV::SLLIW:
19047 case RISCV::SLLI_UW:
19048 case RISCV::SRAI:
19049 case RISCV::SRAIW:
19050 case RISCV::SRLI:
19051 case RISCV::SRLIW:
19052 case RISCV::TH_SRRI:
19053 case RISCV::TH_SRRIW:
19054 case RISCV::TH_TST: {
19055 switch (OpNum) {
19056 case 1:
19057 // op: rs1
19058 return 15;
19059 case 0:
19060 // op: rd
19061 return 7;
19062 case 2:
19063 // op: shamt
19064 return 20;
19065 }
19066 break;
19067 }
19068 case RISCV::VSETVLI: {
19069 switch (OpNum) {
19070 case 1:
19071 // op: rs1
19072 return 15;
19073 case 0:
19074 // op: rd
19075 return 7;
19076 case 2:
19077 // op: vtypei
19078 return 20;
19079 }
19080 break;
19081 }
19082 case RISCV::AES64IM:
19083 case RISCV::BREV8:
19084 case RISCV::CLZ:
19085 case RISCV::CLZW:
19086 case RISCV::CPOP:
19087 case RISCV::CPOPW:
19088 case RISCV::CTZ:
19089 case RISCV::CTZW:
19090 case RISCV::CV_ABS:
19091 case RISCV::CV_ABS_B:
19092 case RISCV::CV_ABS_H:
19093 case RISCV::CV_CLB:
19094 case RISCV::CV_CNT:
19095 case RISCV::CV_CPLXCONJ:
19096 case RISCV::CV_EXTBS:
19097 case RISCV::CV_EXTBZ:
19098 case RISCV::CV_EXTHS:
19099 case RISCV::CV_EXTHZ:
19100 case RISCV::CV_FF1:
19101 case RISCV::CV_FL1:
19102 case RISCV::FCLASS_D:
19103 case RISCV::FCLASS_D_IN32X:
19104 case RISCV::FCLASS_D_INX:
19105 case RISCV::FCLASS_H:
19106 case RISCV::FCLASS_H_INX:
19107 case RISCV::FCLASS_S:
19108 case RISCV::FCLASS_S_INX:
19109 case RISCV::FMVH_X_D:
19110 case RISCV::FMV_D_X:
19111 case RISCV::FMV_H_X:
19112 case RISCV::FMV_W_X:
19113 case RISCV::FMV_X_D:
19114 case RISCV::FMV_X_H:
19115 case RISCV::FMV_X_W:
19116 case RISCV::FMV_X_W_FPR64:
19117 case RISCV::HLVX_HU:
19118 case RISCV::HLVX_WU:
19119 case RISCV::HLV_B:
19120 case RISCV::HLV_BU:
19121 case RISCV::HLV_D:
19122 case RISCV::HLV_H:
19123 case RISCV::HLV_HU:
19124 case RISCV::HLV_W:
19125 case RISCV::HLV_WU:
19126 case RISCV::LB_AQ:
19127 case RISCV::LB_AQ_RL:
19128 case RISCV::LD_AQ:
19129 case RISCV::LD_AQ_RL:
19130 case RISCV::LH_AQ:
19131 case RISCV::LH_AQ_RL:
19132 case RISCV::LR_D:
19133 case RISCV::LR_D_AQ:
19134 case RISCV::LR_D_AQ_RL:
19135 case RISCV::LR_D_RL:
19136 case RISCV::LR_W:
19137 case RISCV::LR_W_AQ:
19138 case RISCV::LR_W_AQ_RL:
19139 case RISCV::LR_W_RL:
19140 case RISCV::LW_AQ:
19141 case RISCV::LW_AQ_RL:
19142 case RISCV::MOPR0:
19143 case RISCV::MOPR1:
19144 case RISCV::MOPR2:
19145 case RISCV::MOPR3:
19146 case RISCV::MOPR4:
19147 case RISCV::MOPR5:
19148 case RISCV::MOPR6:
19149 case RISCV::MOPR7:
19150 case RISCV::MOPR8:
19151 case RISCV::MOPR9:
19152 case RISCV::MOPR10:
19153 case RISCV::MOPR11:
19154 case RISCV::MOPR12:
19155 case RISCV::MOPR13:
19156 case RISCV::MOPR14:
19157 case RISCV::MOPR15:
19158 case RISCV::MOPR16:
19159 case RISCV::MOPR17:
19160 case RISCV::MOPR18:
19161 case RISCV::MOPR19:
19162 case RISCV::MOPR20:
19163 case RISCV::MOPR21:
19164 case RISCV::MOPR22:
19165 case RISCV::MOPR23:
19166 case RISCV::MOPR24:
19167 case RISCV::MOPR25:
19168 case RISCV::MOPR26:
19169 case RISCV::MOPR27:
19170 case RISCV::MOPR28:
19171 case RISCV::MOPR29:
19172 case RISCV::MOPR30:
19173 case RISCV::MOPR31:
19174 case RISCV::ORC_B:
19175 case RISCV::REV8_RV32:
19176 case RISCV::REV8_RV64:
19177 case RISCV::SEXT_B:
19178 case RISCV::SEXT_H:
19179 case RISCV::SHA256SIG0:
19180 case RISCV::SHA256SIG1:
19181 case RISCV::SHA256SUM0:
19182 case RISCV::SHA256SUM1:
19183 case RISCV::SHA512SIG0:
19184 case RISCV::SHA512SIG1:
19185 case RISCV::SHA512SUM0:
19186 case RISCV::SHA512SUM1:
19187 case RISCV::SM3P0:
19188 case RISCV::SM3P1:
19189 case RISCV::TH_FF0:
19190 case RISCV::TH_FF1:
19191 case RISCV::TH_REV:
19192 case RISCV::TH_REVW:
19193 case RISCV::TH_TSTNBZ:
19194 case RISCV::UNZIP_RV32:
19195 case RISCV::ZEXT_H_RV32:
19196 case RISCV::ZEXT_H_RV64:
19197 case RISCV::ZIP_RV32: {
19198 switch (OpNum) {
19199 case 1:
19200 // op: rs1
19201 return 15;
19202 case 0:
19203 // op: rd
19204 return 7;
19205 }
19206 break;
19207 }
19208 case RISCV::VLE8FF_V:
19209 case RISCV::VLE8_V:
19210 case RISCV::VLE16FF_V:
19211 case RISCV::VLE16_V:
19212 case RISCV::VLE32FF_V:
19213 case RISCV::VLE32_V:
19214 case RISCV::VLE64FF_V:
19215 case RISCV::VLE64_V:
19216 case RISCV::VLSEG2E8FF_V:
19217 case RISCV::VLSEG2E8_V:
19218 case RISCV::VLSEG2E16FF_V:
19219 case RISCV::VLSEG2E16_V:
19220 case RISCV::VLSEG2E32FF_V:
19221 case RISCV::VLSEG2E32_V:
19222 case RISCV::VLSEG2E64FF_V:
19223 case RISCV::VLSEG2E64_V:
19224 case RISCV::VLSEG3E8FF_V:
19225 case RISCV::VLSEG3E8_V:
19226 case RISCV::VLSEG3E16FF_V:
19227 case RISCV::VLSEG3E16_V:
19228 case RISCV::VLSEG3E32FF_V:
19229 case RISCV::VLSEG3E32_V:
19230 case RISCV::VLSEG3E64FF_V:
19231 case RISCV::VLSEG3E64_V:
19232 case RISCV::VLSEG4E8FF_V:
19233 case RISCV::VLSEG4E8_V:
19234 case RISCV::VLSEG4E16FF_V:
19235 case RISCV::VLSEG4E16_V:
19236 case RISCV::VLSEG4E32FF_V:
19237 case RISCV::VLSEG4E32_V:
19238 case RISCV::VLSEG4E64FF_V:
19239 case RISCV::VLSEG4E64_V:
19240 case RISCV::VLSEG5E8FF_V:
19241 case RISCV::VLSEG5E8_V:
19242 case RISCV::VLSEG5E16FF_V:
19243 case RISCV::VLSEG5E16_V:
19244 case RISCV::VLSEG5E32FF_V:
19245 case RISCV::VLSEG5E32_V:
19246 case RISCV::VLSEG5E64FF_V:
19247 case RISCV::VLSEG5E64_V:
19248 case RISCV::VLSEG6E8FF_V:
19249 case RISCV::VLSEG6E8_V:
19250 case RISCV::VLSEG6E16FF_V:
19251 case RISCV::VLSEG6E16_V:
19252 case RISCV::VLSEG6E32FF_V:
19253 case RISCV::VLSEG6E32_V:
19254 case RISCV::VLSEG6E64FF_V:
19255 case RISCV::VLSEG6E64_V:
19256 case RISCV::VLSEG7E8FF_V:
19257 case RISCV::VLSEG7E8_V:
19258 case RISCV::VLSEG7E16FF_V:
19259 case RISCV::VLSEG7E16_V:
19260 case RISCV::VLSEG7E32FF_V:
19261 case RISCV::VLSEG7E32_V:
19262 case RISCV::VLSEG7E64FF_V:
19263 case RISCV::VLSEG7E64_V:
19264 case RISCV::VLSEG8E8FF_V:
19265 case RISCV::VLSEG8E8_V:
19266 case RISCV::VLSEG8E16FF_V:
19267 case RISCV::VLSEG8E16_V:
19268 case RISCV::VLSEG8E32FF_V:
19269 case RISCV::VLSEG8E32_V:
19270 case RISCV::VLSEG8E64FF_V:
19271 case RISCV::VLSEG8E64_V: {
19272 switch (OpNum) {
19273 case 1:
19274 // op: rs1
19275 return 15;
19276 case 0:
19277 // op: vd
19278 return 7;
19279 case 2:
19280 // op: vm
19281 return 25;
19282 }
19283 break;
19284 }
19285 case RISCV::VFMV_V_F:
19286 case RISCV::VL1RE8_V:
19287 case RISCV::VL1RE16_V:
19288 case RISCV::VL1RE32_V:
19289 case RISCV::VL1RE64_V:
19290 case RISCV::VL2RE8_V:
19291 case RISCV::VL2RE16_V:
19292 case RISCV::VL2RE32_V:
19293 case RISCV::VL2RE64_V:
19294 case RISCV::VL4RE8_V:
19295 case RISCV::VL4RE16_V:
19296 case RISCV::VL4RE32_V:
19297 case RISCV::VL4RE64_V:
19298 case RISCV::VL8RE8_V:
19299 case RISCV::VL8RE16_V:
19300 case RISCV::VL8RE32_V:
19301 case RISCV::VL8RE64_V:
19302 case RISCV::VLM_V:
19303 case RISCV::VMV_V_X: {
19304 switch (OpNum) {
19305 case 1:
19306 // op: rs1
19307 return 15;
19308 case 0:
19309 // op: vd
19310 return 7;
19311 }
19312 break;
19313 }
19314 case RISCV::VSE8_V:
19315 case RISCV::VSE16_V:
19316 case RISCV::VSE32_V:
19317 case RISCV::VSE64_V:
19318 case RISCV::VSSEG2E8_V:
19319 case RISCV::VSSEG2E16_V:
19320 case RISCV::VSSEG2E32_V:
19321 case RISCV::VSSEG2E64_V:
19322 case RISCV::VSSEG3E8_V:
19323 case RISCV::VSSEG3E16_V:
19324 case RISCV::VSSEG3E32_V:
19325 case RISCV::VSSEG3E64_V:
19326 case RISCV::VSSEG4E8_V:
19327 case RISCV::VSSEG4E16_V:
19328 case RISCV::VSSEG4E32_V:
19329 case RISCV::VSSEG4E64_V:
19330 case RISCV::VSSEG5E8_V:
19331 case RISCV::VSSEG5E16_V:
19332 case RISCV::VSSEG5E32_V:
19333 case RISCV::VSSEG5E64_V:
19334 case RISCV::VSSEG6E8_V:
19335 case RISCV::VSSEG6E16_V:
19336 case RISCV::VSSEG6E32_V:
19337 case RISCV::VSSEG6E64_V:
19338 case RISCV::VSSEG7E8_V:
19339 case RISCV::VSSEG7E16_V:
19340 case RISCV::VSSEG7E32_V:
19341 case RISCV::VSSEG7E64_V:
19342 case RISCV::VSSEG8E8_V:
19343 case RISCV::VSSEG8E16_V:
19344 case RISCV::VSSEG8E32_V:
19345 case RISCV::VSSEG8E64_V: {
19346 switch (OpNum) {
19347 case 1:
19348 // op: rs1
19349 return 15;
19350 case 0:
19351 // op: vs3
19352 return 7;
19353 case 2:
19354 // op: vm
19355 return 25;
19356 }
19357 break;
19358 }
19359 case RISCV::VS1R_V:
19360 case RISCV::VS2R_V:
19361 case RISCV::VS4R_V:
19362 case RISCV::VS8R_V:
19363 case RISCV::VSM_V: {
19364 switch (OpNum) {
19365 case 1:
19366 // op: rs1
19367 return 15;
19368 case 0:
19369 // op: vs3
19370 return 7;
19371 }
19372 break;
19373 }
19374 case RISCV::FCVTMOD_W_D:
19375 case RISCV::FCVT_BF16_S:
19376 case RISCV::FCVT_D_H:
19377 case RISCV::FCVT_D_H_IN32X:
19378 case RISCV::FCVT_D_H_INX:
19379 case RISCV::FCVT_D_L:
19380 case RISCV::FCVT_D_LU:
19381 case RISCV::FCVT_D_LU_INX:
19382 case RISCV::FCVT_D_L_INX:
19383 case RISCV::FCVT_D_S:
19384 case RISCV::FCVT_D_S_IN32X:
19385 case RISCV::FCVT_D_S_INX:
19386 case RISCV::FCVT_D_W:
19387 case RISCV::FCVT_D_WU:
19388 case RISCV::FCVT_D_WU_IN32X:
19389 case RISCV::FCVT_D_WU_INX:
19390 case RISCV::FCVT_D_W_IN32X:
19391 case RISCV::FCVT_D_W_INX:
19392 case RISCV::FCVT_H_D:
19393 case RISCV::FCVT_H_D_IN32X:
19394 case RISCV::FCVT_H_D_INX:
19395 case RISCV::FCVT_H_L:
19396 case RISCV::FCVT_H_LU:
19397 case RISCV::FCVT_H_LU_INX:
19398 case RISCV::FCVT_H_L_INX:
19399 case RISCV::FCVT_H_S:
19400 case RISCV::FCVT_H_S_INX:
19401 case RISCV::FCVT_H_W:
19402 case RISCV::FCVT_H_WU:
19403 case RISCV::FCVT_H_WU_INX:
19404 case RISCV::FCVT_H_W_INX:
19405 case RISCV::FCVT_LU_D:
19406 case RISCV::FCVT_LU_D_INX:
19407 case RISCV::FCVT_LU_H:
19408 case RISCV::FCVT_LU_H_INX:
19409 case RISCV::FCVT_LU_S:
19410 case RISCV::FCVT_LU_S_INX:
19411 case RISCV::FCVT_L_D:
19412 case RISCV::FCVT_L_D_INX:
19413 case RISCV::FCVT_L_H:
19414 case RISCV::FCVT_L_H_INX:
19415 case RISCV::FCVT_L_S:
19416 case RISCV::FCVT_L_S_INX:
19417 case RISCV::FCVT_S_BF16:
19418 case RISCV::FCVT_S_D:
19419 case RISCV::FCVT_S_D_IN32X:
19420 case RISCV::FCVT_S_D_INX:
19421 case RISCV::FCVT_S_H:
19422 case RISCV::FCVT_S_H_INX:
19423 case RISCV::FCVT_S_L:
19424 case RISCV::FCVT_S_LU:
19425 case RISCV::FCVT_S_LU_INX:
19426 case RISCV::FCVT_S_L_INX:
19427 case RISCV::FCVT_S_W:
19428 case RISCV::FCVT_S_WU:
19429 case RISCV::FCVT_S_WU_INX:
19430 case RISCV::FCVT_S_W_INX:
19431 case RISCV::FCVT_WU_D:
19432 case RISCV::FCVT_WU_D_IN32X:
19433 case RISCV::FCVT_WU_D_INX:
19434 case RISCV::FCVT_WU_H:
19435 case RISCV::FCVT_WU_H_INX:
19436 case RISCV::FCVT_WU_S:
19437 case RISCV::FCVT_WU_S_INX:
19438 case RISCV::FCVT_W_D:
19439 case RISCV::FCVT_W_D_IN32X:
19440 case RISCV::FCVT_W_D_INX:
19441 case RISCV::FCVT_W_H:
19442 case RISCV::FCVT_W_H_INX:
19443 case RISCV::FCVT_W_S:
19444 case RISCV::FCVT_W_S_INX:
19445 case RISCV::FROUNDNX_D:
19446 case RISCV::FROUNDNX_H:
19447 case RISCV::FROUNDNX_S:
19448 case RISCV::FROUND_D:
19449 case RISCV::FROUND_H:
19450 case RISCV::FROUND_S:
19451 case RISCV::FSQRT_D:
19452 case RISCV::FSQRT_D_IN32X:
19453 case RISCV::FSQRT_D_INX:
19454 case RISCV::FSQRT_H:
19455 case RISCV::FSQRT_H_INX:
19456 case RISCV::FSQRT_S:
19457 case RISCV::FSQRT_S_INX: {
19458 switch (OpNum) {
19459 case 1:
19460 // op: rs1
19461 return 15;
19462 case 2:
19463 // op: frm
19464 return 12;
19465 case 0:
19466 // op: rd
19467 return 7;
19468 }
19469 break;
19470 }
19471 case RISCV::C_ADD: {
19472 switch (OpNum) {
19473 case 1:
19474 // op: rs1
19475 return 7;
19476 case 2:
19477 // op: rs2
19478 return 2;
19479 }
19480 break;
19481 }
19482 case RISCV::HFENCE_GVMA:
19483 case RISCV::HFENCE_VVMA:
19484 case RISCV::HINVAL_GVMA:
19485 case RISCV::HINVAL_VVMA:
19486 case RISCV::SB_AQ_RL:
19487 case RISCV::SB_RL:
19488 case RISCV::SD_AQ_RL:
19489 case RISCV::SD_RL:
19490 case RISCV::SFENCE_VMA:
19491 case RISCV::SH_AQ_RL:
19492 case RISCV::SH_RL:
19493 case RISCV::SINVAL_VMA:
19494 case RISCV::SW_AQ_RL:
19495 case RISCV::SW_RL:
19496 case RISCV::TH_SFENCE_VMAS: {
19497 switch (OpNum) {
19498 case 1:
19499 // op: rs2
19500 return 20;
19501 case 0:
19502 // op: rs1
19503 return 15;
19504 }
19505 break;
19506 }
19507 case RISCV::TH_LDD:
19508 case RISCV::TH_LWD:
19509 case RISCV::TH_LWUD:
19510 case RISCV::TH_SDD:
19511 case RISCV::TH_SWD: {
19512 switch (OpNum) {
19513 case 1:
19514 // op: rs2
19515 return 20;
19516 case 2:
19517 // op: rs1
19518 return 15;
19519 case 0:
19520 // op: rd
19521 return 7;
19522 case 3:
19523 // op: uimm2
19524 return 25;
19525 }
19526 break;
19527 }
19528 case RISCV::VC_I:
19529 case RISCV::VC_X: {
19530 switch (OpNum) {
19531 case 1:
19532 // op: rs2
19533 return 20;
19534 case 3:
19535 // op: rs1
19536 return 15;
19537 case 2:
19538 // op: rd
19539 return 7;
19540 case 0:
19541 // op: funct6_lo2
19542 return 26;
19543 }
19544 break;
19545 }
19546 case RISCV::CM_MVA01S:
19547 case RISCV::CM_MVSA01: {
19548 switch (OpNum) {
19549 case 1:
19550 // op: rs2
19551 return 2;
19552 case 0:
19553 // op: rs1
19554 return 7;
19555 }
19556 break;
19557 }
19558 case RISCV::C_MV_HINT: {
19559 switch (OpNum) {
19560 case 1:
19561 // op: rs2
19562 return 2;
19563 }
19564 break;
19565 }
19566 case RISCV::VSETIVLI: {
19567 switch (OpNum) {
19568 case 1:
19569 // op: uimm
19570 return 15;
19571 case 0:
19572 // op: rd
19573 return 7;
19574 case 2:
19575 // op: vtypei
19576 return 20;
19577 }
19578 break;
19579 }
19580 case RISCV::VMV_V_V: {
19581 switch (OpNum) {
19582 case 1:
19583 // op: vs1
19584 return 15;
19585 case 0:
19586 // op: vd
19587 return 7;
19588 }
19589 break;
19590 }
19591 case RISCV::VBREV8_V:
19592 case RISCV::VBREV_V:
19593 case RISCV::VCLZ_V:
19594 case RISCV::VCPOP_M:
19595 case RISCV::VCPOP_V:
19596 case RISCV::VCTZ_V:
19597 case RISCV::VFCLASS_V:
19598 case RISCV::VFCVT_F_XU_V:
19599 case RISCV::VFCVT_F_X_V:
19600 case RISCV::VFCVT_RTZ_XU_F_V:
19601 case RISCV::VFCVT_RTZ_X_F_V:
19602 case RISCV::VFCVT_XU_F_V:
19603 case RISCV::VFCVT_X_F_V:
19604 case RISCV::VFIRST_M:
19605 case RISCV::VFNCVTBF16_F_F_W:
19606 case RISCV::VFNCVT_F_F_W:
19607 case RISCV::VFNCVT_F_XU_W:
19608 case RISCV::VFNCVT_F_X_W:
19609 case RISCV::VFNCVT_ROD_F_F_W:
19610 case RISCV::VFNCVT_RTZ_XU_F_W:
19611 case RISCV::VFNCVT_RTZ_X_F_W:
19612 case RISCV::VFNCVT_XU_F_W:
19613 case RISCV::VFNCVT_X_F_W:
19614 case RISCV::VFREC7_V:
19615 case RISCV::VFRSQRT7_V:
19616 case RISCV::VFSQRT_V:
19617 case RISCV::VFWCVTBF16_F_F_V:
19618 case RISCV::VFWCVT_F_F_V:
19619 case RISCV::VFWCVT_F_XU_V:
19620 case RISCV::VFWCVT_F_X_V:
19621 case RISCV::VFWCVT_RTZ_XU_F_V:
19622 case RISCV::VFWCVT_RTZ_X_F_V:
19623 case RISCV::VFWCVT_XU_F_V:
19624 case RISCV::VFWCVT_X_F_V:
19625 case RISCV::VIOTA_M:
19626 case RISCV::VMSBF_M:
19627 case RISCV::VMSIF_M:
19628 case RISCV::VMSOF_M:
19629 case RISCV::VREV8_V:
19630 case RISCV::VSEXT_VF2:
19631 case RISCV::VSEXT_VF4:
19632 case RISCV::VSEXT_VF8:
19633 case RISCV::VZEXT_VF2:
19634 case RISCV::VZEXT_VF4:
19635 case RISCV::VZEXT_VF8: {
19636 switch (OpNum) {
19637 case 1:
19638 // op: vs2
19639 return 20;
19640 case 0:
19641 // op: vd
19642 return 7;
19643 case 2:
19644 // op: vm
19645 return 25;
19646 }
19647 break;
19648 }
19649 case RISCV::VFMV_F_S:
19650 case RISCV::VMV1R_V:
19651 case RISCV::VMV2R_V:
19652 case RISCV::VMV4R_V:
19653 case RISCV::VMV8R_V:
19654 case RISCV::VMV_X_S: {
19655 switch (OpNum) {
19656 case 1:
19657 // op: vs2
19658 return 20;
19659 case 0:
19660 // op: vd
19661 return 7;
19662 }
19663 break;
19664 }
19665 case RISCV::VADD_VI:
19666 case RISCV::VAND_VI:
19667 case RISCV::VMSEQ_VI:
19668 case RISCV::VMSGTU_VI:
19669 case RISCV::VMSGT_VI:
19670 case RISCV::VMSLEU_VI:
19671 case RISCV::VMSLE_VI:
19672 case RISCV::VMSNE_VI:
19673 case RISCV::VNCLIPU_WI:
19674 case RISCV::VNCLIP_WI:
19675 case RISCV::VNSRA_WI:
19676 case RISCV::VNSRL_WI:
19677 case RISCV::VOR_VI:
19678 case RISCV::VRGATHER_VI:
19679 case RISCV::VROR_VI:
19680 case RISCV::VRSUB_VI:
19681 case RISCV::VSADDU_VI:
19682 case RISCV::VSADD_VI:
19683 case RISCV::VSLIDEDOWN_VI:
19684 case RISCV::VSLIDEUP_VI:
19685 case RISCV::VSLL_VI:
19686 case RISCV::VSRA_VI:
19687 case RISCV::VSRL_VI:
19688 case RISCV::VSSRA_VI:
19689 case RISCV::VSSRL_VI:
19690 case RISCV::VWSLL_VI:
19691 case RISCV::VXOR_VI: {
19692 switch (OpNum) {
19693 case 1:
19694 // op: vs2
19695 return 20;
19696 case 2:
19697 // op: imm
19698 return 15;
19699 case 0:
19700 // op: vd
19701 return 7;
19702 case 3:
19703 // op: vm
19704 return 25;
19705 }
19706 break;
19707 }
19708 case RISCV::VADC_VIM:
19709 case RISCV::VAESKF1_VI:
19710 case RISCV::VMADC_VI:
19711 case RISCV::VMADC_VIM:
19712 case RISCV::VMERGE_VIM:
19713 case RISCV::VSM4K_VI: {
19714 switch (OpNum) {
19715 case 1:
19716 // op: vs2
19717 return 20;
19718 case 2:
19719 // op: imm
19720 return 15;
19721 case 0:
19722 // op: vd
19723 return 7;
19724 }
19725 break;
19726 }
19727 case RISCV::VAADDU_VX:
19728 case RISCV::VAADD_VX:
19729 case RISCV::VADD_VX:
19730 case RISCV::VANDN_VX:
19731 case RISCV::VAND_VX:
19732 case RISCV::VASUBU_VX:
19733 case RISCV::VASUB_VX:
19734 case RISCV::VCLMULH_VX:
19735 case RISCV::VCLMUL_VX:
19736 case RISCV::VDIVU_VX:
19737 case RISCV::VDIV_VX:
19738 case RISCV::VFADD_VF:
19739 case RISCV::VFDIV_VF:
19740 case RISCV::VFMAX_VF:
19741 case RISCV::VFMIN_VF:
19742 case RISCV::VFMUL_VF:
19743 case RISCV::VFNRCLIP_XU_F_QF:
19744 case RISCV::VFNRCLIP_X_F_QF:
19745 case RISCV::VFRDIV_VF:
19746 case RISCV::VFRSUB_VF:
19747 case RISCV::VFSGNJN_VF:
19748 case RISCV::VFSGNJX_VF:
19749 case RISCV::VFSGNJ_VF:
19750 case RISCV::VFSLIDE1DOWN_VF:
19751 case RISCV::VFSLIDE1UP_VF:
19752 case RISCV::VFSUB_VF:
19753 case RISCV::VFWADD_VF:
19754 case RISCV::VFWADD_WF:
19755 case RISCV::VFWMUL_VF:
19756 case RISCV::VFWSUB_VF:
19757 case RISCV::VFWSUB_WF:
19758 case RISCV::VMAXU_VX:
19759 case RISCV::VMAX_VX:
19760 case RISCV::VMFEQ_VF:
19761 case RISCV::VMFGE_VF:
19762 case RISCV::VMFGT_VF:
19763 case RISCV::VMFLE_VF:
19764 case RISCV::VMFLT_VF:
19765 case RISCV::VMFNE_VF:
19766 case RISCV::VMINU_VX:
19767 case RISCV::VMIN_VX:
19768 case RISCV::VMSEQ_VX:
19769 case RISCV::VMSGTU_VX:
19770 case RISCV::VMSGT_VX:
19771 case RISCV::VMSLEU_VX:
19772 case RISCV::VMSLE_VX:
19773 case RISCV::VMSLTU_VX:
19774 case RISCV::VMSLT_VX:
19775 case RISCV::VMSNE_VX:
19776 case RISCV::VMULHSU_VX:
19777 case RISCV::VMULHU_VX:
19778 case RISCV::VMULH_VX:
19779 case RISCV::VMUL_VX:
19780 case RISCV::VNCLIPU_WX:
19781 case RISCV::VNCLIP_WX:
19782 case RISCV::VNSRA_WX:
19783 case RISCV::VNSRL_WX:
19784 case RISCV::VOR_VX:
19785 case RISCV::VREMU_VX:
19786 case RISCV::VREM_VX:
19787 case RISCV::VRGATHER_VX:
19788 case RISCV::VROL_VX:
19789 case RISCV::VROR_VX:
19790 case RISCV::VRSUB_VX:
19791 case RISCV::VSADDU_VX:
19792 case RISCV::VSADD_VX:
19793 case RISCV::VSLIDE1DOWN_VX:
19794 case RISCV::VSLIDE1UP_VX:
19795 case RISCV::VSLIDEDOWN_VX:
19796 case RISCV::VSLIDEUP_VX:
19797 case RISCV::VSLL_VX:
19798 case RISCV::VSMUL_VX:
19799 case RISCV::VSRA_VX:
19800 case RISCV::VSRL_VX:
19801 case RISCV::VSSRA_VX:
19802 case RISCV::VSSRL_VX:
19803 case RISCV::VSSUBU_VX:
19804 case RISCV::VSSUB_VX:
19805 case RISCV::VSUB_VX:
19806 case RISCV::VWADDU_VX:
19807 case RISCV::VWADDU_WX:
19808 case RISCV::VWADD_VX:
19809 case RISCV::VWADD_WX:
19810 case RISCV::VWMULSU_VX:
19811 case RISCV::VWMULU_VX:
19812 case RISCV::VWMUL_VX:
19813 case RISCV::VWSLL_VX:
19814 case RISCV::VWSUBU_VX:
19815 case RISCV::VWSUBU_WX:
19816 case RISCV::VWSUB_VX:
19817 case RISCV::VWSUB_WX:
19818 case RISCV::VXOR_VX: {
19819 switch (OpNum) {
19820 case 1:
19821 // op: vs2
19822 return 20;
19823 case 2:
19824 // op: rs1
19825 return 15;
19826 case 0:
19827 // op: vd
19828 return 7;
19829 case 3:
19830 // op: vm
19831 return 25;
19832 }
19833 break;
19834 }
19835 case RISCV::VADC_VXM:
19836 case RISCV::VFMERGE_VFM:
19837 case RISCV::VMADC_VX:
19838 case RISCV::VMADC_VXM:
19839 case RISCV::VMERGE_VXM:
19840 case RISCV::VMSBC_VX:
19841 case RISCV::VMSBC_VXM:
19842 case RISCV::VSBC_VXM: {
19843 switch (OpNum) {
19844 case 1:
19845 // op: vs2
19846 return 20;
19847 case 2:
19848 // op: rs1
19849 return 15;
19850 case 0:
19851 // op: vd
19852 return 7;
19853 }
19854 break;
19855 }
19856 case RISCV::VAADDU_VV:
19857 case RISCV::VAADD_VV:
19858 case RISCV::VADD_VV:
19859 case RISCV::VANDN_VV:
19860 case RISCV::VAND_VV:
19861 case RISCV::VASUBU_VV:
19862 case RISCV::VASUB_VV:
19863 case RISCV::VCLMULH_VV:
19864 case RISCV::VCLMUL_VV:
19865 case RISCV::VDIVU_VV:
19866 case RISCV::VDIV_VV:
19867 case RISCV::VFADD_VV:
19868 case RISCV::VFDIV_VV:
19869 case RISCV::VFMAX_VV:
19870 case RISCV::VFMIN_VV:
19871 case RISCV::VFMUL_VV:
19872 case RISCV::VFREDMAX_VS:
19873 case RISCV::VFREDMIN_VS:
19874 case RISCV::VFREDOSUM_VS:
19875 case RISCV::VFREDUSUM_VS:
19876 case RISCV::VFSGNJN_VV:
19877 case RISCV::VFSGNJX_VV:
19878 case RISCV::VFSGNJ_VV:
19879 case RISCV::VFSUB_VV:
19880 case RISCV::VFWADD_VV:
19881 case RISCV::VFWADD_WV:
19882 case RISCV::VFWMUL_VV:
19883 case RISCV::VFWREDOSUM_VS:
19884 case RISCV::VFWREDUSUM_VS:
19885 case RISCV::VFWSUB_VV:
19886 case RISCV::VFWSUB_WV:
19887 case RISCV::VMAXU_VV:
19888 case RISCV::VMAX_VV:
19889 case RISCV::VMFEQ_VV:
19890 case RISCV::VMFLE_VV:
19891 case RISCV::VMFLT_VV:
19892 case RISCV::VMFNE_VV:
19893 case RISCV::VMINU_VV:
19894 case RISCV::VMIN_VV:
19895 case RISCV::VMSEQ_VV:
19896 case RISCV::VMSLEU_VV:
19897 case RISCV::VMSLE_VV:
19898 case RISCV::VMSLTU_VV:
19899 case RISCV::VMSLT_VV:
19900 case RISCV::VMSNE_VV:
19901 case RISCV::VMULHSU_VV:
19902 case RISCV::VMULHU_VV:
19903 case RISCV::VMULH_VV:
19904 case RISCV::VMUL_VV:
19905 case RISCV::VNCLIPU_WV:
19906 case RISCV::VNCLIP_WV:
19907 case RISCV::VNSRA_WV:
19908 case RISCV::VNSRL_WV:
19909 case RISCV::VOR_VV:
19910 case RISCV::VREDAND_VS:
19911 case RISCV::VREDMAXU_VS:
19912 case RISCV::VREDMAX_VS:
19913 case RISCV::VREDMINU_VS:
19914 case RISCV::VREDMIN_VS:
19915 case RISCV::VREDOR_VS:
19916 case RISCV::VREDSUM_VS:
19917 case RISCV::VREDXOR_VS:
19918 case RISCV::VREMU_VV:
19919 case RISCV::VREM_VV:
19920 case RISCV::VRGATHEREI16_VV:
19921 case RISCV::VRGATHER_VV:
19922 case RISCV::VROL_VV:
19923 case RISCV::VROR_VV:
19924 case RISCV::VSADDU_VV:
19925 case RISCV::VSADD_VV:
19926 case RISCV::VSLL_VV:
19927 case RISCV::VSMUL_VV:
19928 case RISCV::VSRA_VV:
19929 case RISCV::VSRL_VV:
19930 case RISCV::VSSRA_VV:
19931 case RISCV::VSSRL_VV:
19932 case RISCV::VSSUBU_VV:
19933 case RISCV::VSSUB_VV:
19934 case RISCV::VSUB_VV:
19935 case RISCV::VWADDU_VV:
19936 case RISCV::VWADDU_WV:
19937 case RISCV::VWADD_VV:
19938 case RISCV::VWADD_WV:
19939 case RISCV::VWMULSU_VV:
19940 case RISCV::VWMULU_VV:
19941 case RISCV::VWMUL_VV:
19942 case RISCV::VWREDSUMU_VS:
19943 case RISCV::VWREDSUM_VS:
19944 case RISCV::VWSLL_VV:
19945 case RISCV::VWSUBU_VV:
19946 case RISCV::VWSUBU_WV:
19947 case RISCV::VWSUB_VV:
19948 case RISCV::VWSUB_WV:
19949 case RISCV::VXOR_VV: {
19950 switch (OpNum) {
19951 case 1:
19952 // op: vs2
19953 return 20;
19954 case 2:
19955 // op: vs1
19956 return 15;
19957 case 0:
19958 // op: vd
19959 return 7;
19960 case 3:
19961 // op: vm
19962 return 25;
19963 }
19964 break;
19965 }
19966 case RISCV::VADC_VVM:
19967 case RISCV::VCOMPRESS_VM:
19968 case RISCV::VMADC_VV:
19969 case RISCV::VMADC_VVM:
19970 case RISCV::VMANDN_MM:
19971 case RISCV::VMAND_MM:
19972 case RISCV::VMERGE_VVM:
19973 case RISCV::VMNAND_MM:
19974 case RISCV::VMNOR_MM:
19975 case RISCV::VMORN_MM:
19976 case RISCV::VMOR_MM:
19977 case RISCV::VMSBC_VV:
19978 case RISCV::VMSBC_VVM:
19979 case RISCV::VMXNOR_MM:
19980 case RISCV::VMXOR_MM:
19981 case RISCV::VSBC_VVM:
19982 case RISCV::VSM3ME_VV: {
19983 switch (OpNum) {
19984 case 1:
19985 // op: vs2
19986 return 20;
19987 case 2:
19988 // op: vs1
19989 return 15;
19990 case 0:
19991 // op: vd
19992 return 7;
19993 }
19994 break;
19995 }
19996 case RISCV::C_ADDI_NOP: {
19997 switch (OpNum) {
19998 case 2:
19999 // op: imm
20000 return 12;
20001 case 1:
20002 // op: rd
20003 return 7;
20004 }
20005 break;
20006 }
20007 case RISCV::C_FLDSP:
20008 case RISCV::C_FLWSP:
20009 case RISCV::C_LDSP:
20010 case RISCV::C_LWSP: {
20011 switch (OpNum) {
20012 case 2:
20013 // op: imm
20014 return 2;
20015 case 0:
20016 // op: rd
20017 return 7;
20018 }
20019 break;
20020 }
20021 case RISCV::C_ADDI:
20022 case RISCV::C_ADDIW:
20023 case RISCV::C_SLLI: {
20024 switch (OpNum) {
20025 case 2:
20026 // op: imm
20027 return 2;
20028 case 1:
20029 // op: rd
20030 return 7;
20031 }
20032 break;
20033 }
20034 case RISCV::C_ANDI:
20035 case RISCV::C_SRAI:
20036 case RISCV::C_SRLI: {
20037 switch (OpNum) {
20038 case 2:
20039 // op: imm
20040 return 2;
20041 case 1:
20042 // op: rs1
20043 return 7;
20044 }
20045 break;
20046 }
20047 case RISCV::C_ADDI16SP:
20048 case RISCV::C_SLLI_HINT: {
20049 switch (OpNum) {
20050 case 2:
20051 // op: imm
20052 return 2;
20053 }
20054 break;
20055 }
20056 case RISCV::C_ADDI4SPN: {
20057 switch (OpNum) {
20058 case 2:
20059 // op: imm
20060 return 5;
20061 case 0:
20062 // op: rd
20063 return 2;
20064 }
20065 break;
20066 }
20067 case RISCV::C_FSDSP:
20068 case RISCV::C_FSWSP:
20069 case RISCV::C_SDSP:
20070 case RISCV::C_SWSP: {
20071 switch (OpNum) {
20072 case 2:
20073 // op: imm
20074 return 7;
20075 case 0:
20076 // op: rs2
20077 return 2;
20078 }
20079 break;
20080 }
20081 case RISCV::CV_BEQIMM:
20082 case RISCV::CV_BNEIMM: {
20083 switch (OpNum) {
20084 case 2:
20085 // op: imm12
20086 return 7;
20087 case 0:
20088 // op: rs1
20089 return 15;
20090 case 1:
20091 // op: imm5
20092 return 20;
20093 }
20094 break;
20095 }
20096 case RISCV::FSD:
20097 case RISCV::FSH:
20098 case RISCV::FSW:
20099 case RISCV::SB:
20100 case RISCV::SD:
20101 case RISCV::SH:
20102 case RISCV::SW: {
20103 switch (OpNum) {
20104 case 2:
20105 // op: imm12
20106 return 7;
20107 case 0:
20108 // op: rs2
20109 return 20;
20110 case 1:
20111 // op: rs1
20112 return 15;
20113 }
20114 break;
20115 }
20116 case RISCV::BEQ:
20117 case RISCV::BGE:
20118 case RISCV::BGEU:
20119 case RISCV::BLT:
20120 case RISCV::BLTU:
20121 case RISCV::BNE: {
20122 switch (OpNum) {
20123 case 2:
20124 // op: imm12
20125 return 7;
20126 case 1:
20127 // op: rs2
20128 return 20;
20129 case 0:
20130 // op: rs1
20131 return 15;
20132 }
20133 break;
20134 }
20135 case RISCV::CSRRC:
20136 case RISCV::CSRRCI:
20137 case RISCV::CSRRS:
20138 case RISCV::CSRRSI:
20139 case RISCV::CSRRW:
20140 case RISCV::CSRRWI: {
20141 switch (OpNum) {
20142 case 2:
20143 // op: rs1
20144 return 15;
20145 case 0:
20146 // op: rd
20147 return 7;
20148 case 1:
20149 // op: imm12
20150 return 20;
20151 }
20152 break;
20153 }
20154 case RISCV::CV_LBU_ri_inc:
20155 case RISCV::CV_LB_ri_inc:
20156 case RISCV::CV_LHU_ri_inc:
20157 case RISCV::CV_LH_ri_inc:
20158 case RISCV::CV_LW_ri_inc: {
20159 switch (OpNum) {
20160 case 2:
20161 // op: rs1
20162 return 15;
20163 case 0:
20164 // op: rd
20165 return 7;
20166 case 3:
20167 // op: imm12
20168 return 20;
20169 }
20170 break;
20171 }
20172 case RISCV::TH_LBIA:
20173 case RISCV::TH_LBIB:
20174 case RISCV::TH_LBUIA:
20175 case RISCV::TH_LBUIB:
20176 case RISCV::TH_LDIA:
20177 case RISCV::TH_LDIB:
20178 case RISCV::TH_LHIA:
20179 case RISCV::TH_LHIB:
20180 case RISCV::TH_LHUIA:
20181 case RISCV::TH_LHUIB:
20182 case RISCV::TH_LWIA:
20183 case RISCV::TH_LWIB:
20184 case RISCV::TH_LWUIA:
20185 case RISCV::TH_LWUIB: {
20186 switch (OpNum) {
20187 case 2:
20188 // op: rs1
20189 return 15;
20190 case 0:
20191 // op: rd
20192 return 7;
20193 case 3:
20194 // op: simm5
20195 return 20;
20196 case 4:
20197 // op: uimm2
20198 return 25;
20199 }
20200 break;
20201 }
20202 case RISCV::CV_INSERT_B:
20203 case RISCV::CV_INSERT_H:
20204 case RISCV::CV_SDOTSP_SCI_B:
20205 case RISCV::CV_SDOTSP_SCI_H:
20206 case RISCV::CV_SDOTUP_SCI_B:
20207 case RISCV::CV_SDOTUP_SCI_H:
20208 case RISCV::CV_SDOTUSP_SCI_B:
20209 case RISCV::CV_SDOTUSP_SCI_H: {
20210 switch (OpNum) {
20211 case 2:
20212 // op: rs1
20213 return 15;
20214 case 1:
20215 // op: rd
20216 return 7;
20217 case 3:
20218 // op: imm6
20219 return 20;
20220 }
20221 break;
20222 }
20223 case RISCV::CV_INSERT: {
20224 switch (OpNum) {
20225 case 2:
20226 // op: rs1
20227 return 15;
20228 case 1:
20229 // op: rd
20230 return 7;
20231 case 3:
20232 // op: is3
20233 return 25;
20234 case 4:
20235 // op: is2
20236 return 20;
20237 }
20238 break;
20239 }
20240 case RISCV::TH_SBIA:
20241 case RISCV::TH_SBIB:
20242 case RISCV::TH_SDIA:
20243 case RISCV::TH_SDIB:
20244 case RISCV::TH_SHIA:
20245 case RISCV::TH_SHIB:
20246 case RISCV::TH_SWIA:
20247 case RISCV::TH_SWIB: {
20248 switch (OpNum) {
20249 case 2:
20250 // op: rs1
20251 return 15;
20252 case 1:
20253 // op: rd
20254 return 7;
20255 case 3:
20256 // op: simm5
20257 return 20;
20258 case 4:
20259 // op: uimm2
20260 return 25;
20261 }
20262 break;
20263 }
20264 case RISCV::VFMV_S_F:
20265 case RISCV::VMV_S_X: {
20266 switch (OpNum) {
20267 case 2:
20268 // op: rs1
20269 return 15;
20270 case 1:
20271 // op: vd
20272 return 7;
20273 }
20274 break;
20275 }
20276 case RISCV::AES32DSI:
20277 case RISCV::AES32DSMI:
20278 case RISCV::AES32ESI:
20279 case RISCV::AES32ESMI:
20280 case RISCV::SM4ED:
20281 case RISCV::SM4KS: {
20282 switch (OpNum) {
20283 case 2:
20284 // op: rs2
20285 return 20;
20286 case 1:
20287 // op: rs1
20288 return 15;
20289 case 0:
20290 // op: rd
20291 return 7;
20292 case 3:
20293 // op: bs
20294 return 30;
20295 }
20296 break;
20297 }
20298 case RISCV::CV_ADDN:
20299 case RISCV::CV_ADDRN:
20300 case RISCV::CV_ADDUN:
20301 case RISCV::CV_ADDURN:
20302 case RISCV::CV_MULHHSN:
20303 case RISCV::CV_MULHHSRN:
20304 case RISCV::CV_MULHHUN:
20305 case RISCV::CV_MULHHURN:
20306 case RISCV::CV_MULSN:
20307 case RISCV::CV_MULSRN:
20308 case RISCV::CV_MULUN:
20309 case RISCV::CV_MULURN:
20310 case RISCV::CV_SUBN:
20311 case RISCV::CV_SUBRN:
20312 case RISCV::CV_SUBUN:
20313 case RISCV::CV_SUBURN: {
20314 switch (OpNum) {
20315 case 2:
20316 // op: rs2
20317 return 20;
20318 case 1:
20319 // op: rs1
20320 return 15;
20321 case 0:
20322 // op: rd
20323 return 7;
20324 case 3:
20325 // op: imm5
20326 return 25;
20327 }
20328 break;
20329 }
20330 case RISCV::TH_ADDSL:
20331 case RISCV::TH_FLRD:
20332 case RISCV::TH_FLRW:
20333 case RISCV::TH_FLURD:
20334 case RISCV::TH_FLURW:
20335 case RISCV::TH_FSRD:
20336 case RISCV::TH_FSRW:
20337 case RISCV::TH_FSURD:
20338 case RISCV::TH_FSURW:
20339 case RISCV::TH_LRB:
20340 case RISCV::TH_LRBU:
20341 case RISCV::TH_LRD:
20342 case RISCV::TH_LRH:
20343 case RISCV::TH_LRHU:
20344 case RISCV::TH_LRW:
20345 case RISCV::TH_LRWU:
20346 case RISCV::TH_LURB:
20347 case RISCV::TH_LURBU:
20348 case RISCV::TH_LURD:
20349 case RISCV::TH_LURH:
20350 case RISCV::TH_LURHU:
20351 case RISCV::TH_LURW:
20352 case RISCV::TH_LURWU:
20353 case RISCV::TH_SRB:
20354 case RISCV::TH_SRD:
20355 case RISCV::TH_SRH:
20356 case RISCV::TH_SRW:
20357 case RISCV::TH_SURB:
20358 case RISCV::TH_SURD:
20359 case RISCV::TH_SURH:
20360 case RISCV::TH_SURW: {
20361 switch (OpNum) {
20362 case 2:
20363 // op: rs2
20364 return 20;
20365 case 1:
20366 // op: rs1
20367 return 15;
20368 case 0:
20369 // op: rd
20370 return 7;
20371 case 3:
20372 // op: uimm2
20373 return 25;
20374 }
20375 break;
20376 }
20377 case RISCV::ADD:
20378 case RISCV::ADDW:
20379 case RISCV::ADD_UW:
20380 case RISCV::AES64DS:
20381 case RISCV::AES64DSM:
20382 case RISCV::AES64ES:
20383 case RISCV::AES64ESM:
20384 case RISCV::AES64KS2:
20385 case RISCV::AMOADD_B:
20386 case RISCV::AMOADD_B_AQ:
20387 case RISCV::AMOADD_B_AQ_RL:
20388 case RISCV::AMOADD_B_RL:
20389 case RISCV::AMOADD_D:
20390 case RISCV::AMOADD_D_AQ:
20391 case RISCV::AMOADD_D_AQ_RL:
20392 case RISCV::AMOADD_D_RL:
20393 case RISCV::AMOADD_H:
20394 case RISCV::AMOADD_H_AQ:
20395 case RISCV::AMOADD_H_AQ_RL:
20396 case RISCV::AMOADD_H_RL:
20397 case RISCV::AMOADD_W:
20398 case RISCV::AMOADD_W_AQ:
20399 case RISCV::AMOADD_W_AQ_RL:
20400 case RISCV::AMOADD_W_RL:
20401 case RISCV::AMOAND_B:
20402 case RISCV::AMOAND_B_AQ:
20403 case RISCV::AMOAND_B_AQ_RL:
20404 case RISCV::AMOAND_B_RL:
20405 case RISCV::AMOAND_D:
20406 case RISCV::AMOAND_D_AQ:
20407 case RISCV::AMOAND_D_AQ_RL:
20408 case RISCV::AMOAND_D_RL:
20409 case RISCV::AMOAND_H:
20410 case RISCV::AMOAND_H_AQ:
20411 case RISCV::AMOAND_H_AQ_RL:
20412 case RISCV::AMOAND_H_RL:
20413 case RISCV::AMOAND_W:
20414 case RISCV::AMOAND_W_AQ:
20415 case RISCV::AMOAND_W_AQ_RL:
20416 case RISCV::AMOAND_W_RL:
20417 case RISCV::AMOMAXU_B:
20418 case RISCV::AMOMAXU_B_AQ:
20419 case RISCV::AMOMAXU_B_AQ_RL:
20420 case RISCV::AMOMAXU_B_RL:
20421 case RISCV::AMOMAXU_D:
20422 case RISCV::AMOMAXU_D_AQ:
20423 case RISCV::AMOMAXU_D_AQ_RL:
20424 case RISCV::AMOMAXU_D_RL:
20425 case RISCV::AMOMAXU_H:
20426 case RISCV::AMOMAXU_H_AQ:
20427 case RISCV::AMOMAXU_H_AQ_RL:
20428 case RISCV::AMOMAXU_H_RL:
20429 case RISCV::AMOMAXU_W:
20430 case RISCV::AMOMAXU_W_AQ:
20431 case RISCV::AMOMAXU_W_AQ_RL:
20432 case RISCV::AMOMAXU_W_RL:
20433 case RISCV::AMOMAX_B:
20434 case RISCV::AMOMAX_B_AQ:
20435 case RISCV::AMOMAX_B_AQ_RL:
20436 case RISCV::AMOMAX_B_RL:
20437 case RISCV::AMOMAX_D:
20438 case RISCV::AMOMAX_D_AQ:
20439 case RISCV::AMOMAX_D_AQ_RL:
20440 case RISCV::AMOMAX_D_RL:
20441 case RISCV::AMOMAX_H:
20442 case RISCV::AMOMAX_H_AQ:
20443 case RISCV::AMOMAX_H_AQ_RL:
20444 case RISCV::AMOMAX_H_RL:
20445 case RISCV::AMOMAX_W:
20446 case RISCV::AMOMAX_W_AQ:
20447 case RISCV::AMOMAX_W_AQ_RL:
20448 case RISCV::AMOMAX_W_RL:
20449 case RISCV::AMOMINU_B:
20450 case RISCV::AMOMINU_B_AQ:
20451 case RISCV::AMOMINU_B_AQ_RL:
20452 case RISCV::AMOMINU_B_RL:
20453 case RISCV::AMOMINU_D:
20454 case RISCV::AMOMINU_D_AQ:
20455 case RISCV::AMOMINU_D_AQ_RL:
20456 case RISCV::AMOMINU_D_RL:
20457 case RISCV::AMOMINU_H:
20458 case RISCV::AMOMINU_H_AQ:
20459 case RISCV::AMOMINU_H_AQ_RL:
20460 case RISCV::AMOMINU_H_RL:
20461 case RISCV::AMOMINU_W:
20462 case RISCV::AMOMINU_W_AQ:
20463 case RISCV::AMOMINU_W_AQ_RL:
20464 case RISCV::AMOMINU_W_RL:
20465 case RISCV::AMOMIN_B:
20466 case RISCV::AMOMIN_B_AQ:
20467 case RISCV::AMOMIN_B_AQ_RL:
20468 case RISCV::AMOMIN_B_RL:
20469 case RISCV::AMOMIN_D:
20470 case RISCV::AMOMIN_D_AQ:
20471 case RISCV::AMOMIN_D_AQ_RL:
20472 case RISCV::AMOMIN_D_RL:
20473 case RISCV::AMOMIN_H:
20474 case RISCV::AMOMIN_H_AQ:
20475 case RISCV::AMOMIN_H_AQ_RL:
20476 case RISCV::AMOMIN_H_RL:
20477 case RISCV::AMOMIN_W:
20478 case RISCV::AMOMIN_W_AQ:
20479 case RISCV::AMOMIN_W_AQ_RL:
20480 case RISCV::AMOMIN_W_RL:
20481 case RISCV::AMOOR_B:
20482 case RISCV::AMOOR_B_AQ:
20483 case RISCV::AMOOR_B_AQ_RL:
20484 case RISCV::AMOOR_B_RL:
20485 case RISCV::AMOOR_D:
20486 case RISCV::AMOOR_D_AQ:
20487 case RISCV::AMOOR_D_AQ_RL:
20488 case RISCV::AMOOR_D_RL:
20489 case RISCV::AMOOR_H:
20490 case RISCV::AMOOR_H_AQ:
20491 case RISCV::AMOOR_H_AQ_RL:
20492 case RISCV::AMOOR_H_RL:
20493 case RISCV::AMOOR_W:
20494 case RISCV::AMOOR_W_AQ:
20495 case RISCV::AMOOR_W_AQ_RL:
20496 case RISCV::AMOOR_W_RL:
20497 case RISCV::AMOSWAP_B:
20498 case RISCV::AMOSWAP_B_AQ:
20499 case RISCV::AMOSWAP_B_AQ_RL:
20500 case RISCV::AMOSWAP_B_RL:
20501 case RISCV::AMOSWAP_D:
20502 case RISCV::AMOSWAP_D_AQ:
20503 case RISCV::AMOSWAP_D_AQ_RL:
20504 case RISCV::AMOSWAP_D_RL:
20505 case RISCV::AMOSWAP_H:
20506 case RISCV::AMOSWAP_H_AQ:
20507 case RISCV::AMOSWAP_H_AQ_RL:
20508 case RISCV::AMOSWAP_H_RL:
20509 case RISCV::AMOSWAP_W:
20510 case RISCV::AMOSWAP_W_AQ:
20511 case RISCV::AMOSWAP_W_AQ_RL:
20512 case RISCV::AMOSWAP_W_RL:
20513 case RISCV::AMOXOR_B:
20514 case RISCV::AMOXOR_B_AQ:
20515 case RISCV::AMOXOR_B_AQ_RL:
20516 case RISCV::AMOXOR_B_RL:
20517 case RISCV::AMOXOR_D:
20518 case RISCV::AMOXOR_D_AQ:
20519 case RISCV::AMOXOR_D_AQ_RL:
20520 case RISCV::AMOXOR_D_RL:
20521 case RISCV::AMOXOR_H:
20522 case RISCV::AMOXOR_H_AQ:
20523 case RISCV::AMOXOR_H_AQ_RL:
20524 case RISCV::AMOXOR_H_RL:
20525 case RISCV::AMOXOR_W:
20526 case RISCV::AMOXOR_W_AQ:
20527 case RISCV::AMOXOR_W_AQ_RL:
20528 case RISCV::AMOXOR_W_RL:
20529 case RISCV::AND:
20530 case RISCV::ANDN:
20531 case RISCV::BCLR:
20532 case RISCV::BEXT:
20533 case RISCV::BINV:
20534 case RISCV::BSET:
20535 case RISCV::CLMUL:
20536 case RISCV::CLMULH:
20537 case RISCV::CLMULR:
20538 case RISCV::CV_ADD_B:
20539 case RISCV::CV_ADD_DIV2:
20540 case RISCV::CV_ADD_DIV4:
20541 case RISCV::CV_ADD_DIV8:
20542 case RISCV::CV_ADD_H:
20543 case RISCV::CV_ADD_SC_B:
20544 case RISCV::CV_ADD_SC_H:
20545 case RISCV::CV_AND_B:
20546 case RISCV::CV_AND_H:
20547 case RISCV::CV_AND_SC_B:
20548 case RISCV::CV_AND_SC_H:
20549 case RISCV::CV_AVGU_B:
20550 case RISCV::CV_AVGU_H:
20551 case RISCV::CV_AVGU_SC_B:
20552 case RISCV::CV_AVGU_SC_H:
20553 case RISCV::CV_AVG_B:
20554 case RISCV::CV_AVG_H:
20555 case RISCV::CV_AVG_SC_B:
20556 case RISCV::CV_AVG_SC_H:
20557 case RISCV::CV_BCLRR:
20558 case RISCV::CV_BSETR:
20559 case RISCV::CV_CLIPR:
20560 case RISCV::CV_CLIPUR:
20561 case RISCV::CV_CMPEQ_B:
20562 case RISCV::CV_CMPEQ_H:
20563 case RISCV::CV_CMPEQ_SC_B:
20564 case RISCV::CV_CMPEQ_SC_H:
20565 case RISCV::CV_CMPGEU_B:
20566 case RISCV::CV_CMPGEU_H:
20567 case RISCV::CV_CMPGEU_SC_B:
20568 case RISCV::CV_CMPGEU_SC_H:
20569 case RISCV::CV_CMPGE_B:
20570 case RISCV::CV_CMPGE_H:
20571 case RISCV::CV_CMPGE_SC_B:
20572 case RISCV::CV_CMPGE_SC_H:
20573 case RISCV::CV_CMPGTU_B:
20574 case RISCV::CV_CMPGTU_H:
20575 case RISCV::CV_CMPGTU_SC_B:
20576 case RISCV::CV_CMPGTU_SC_H:
20577 case RISCV::CV_CMPGT_B:
20578 case RISCV::CV_CMPGT_H:
20579 case RISCV::CV_CMPGT_SC_B:
20580 case RISCV::CV_CMPGT_SC_H:
20581 case RISCV::CV_CMPLEU_B:
20582 case RISCV::CV_CMPLEU_H:
20583 case RISCV::CV_CMPLEU_SC_B:
20584 case RISCV::CV_CMPLEU_SC_H:
20585 case RISCV::CV_CMPLE_B:
20586 case RISCV::CV_CMPLE_H:
20587 case RISCV::CV_CMPLE_SC_B:
20588 case RISCV::CV_CMPLE_SC_H:
20589 case RISCV::CV_CMPLTU_B:
20590 case RISCV::CV_CMPLTU_H:
20591 case RISCV::CV_CMPLTU_SC_B:
20592 case RISCV::CV_CMPLTU_SC_H:
20593 case RISCV::CV_CMPLT_B:
20594 case RISCV::CV_CMPLT_H:
20595 case RISCV::CV_CMPLT_SC_B:
20596 case RISCV::CV_CMPLT_SC_H:
20597 case RISCV::CV_CMPNE_B:
20598 case RISCV::CV_CMPNE_H:
20599 case RISCV::CV_CMPNE_SC_B:
20600 case RISCV::CV_CMPNE_SC_H:
20601 case RISCV::CV_DOTSP_B:
20602 case RISCV::CV_DOTSP_H:
20603 case RISCV::CV_DOTSP_SC_B:
20604 case RISCV::CV_DOTSP_SC_H:
20605 case RISCV::CV_DOTUP_B:
20606 case RISCV::CV_DOTUP_H:
20607 case RISCV::CV_DOTUP_SC_B:
20608 case RISCV::CV_DOTUP_SC_H:
20609 case RISCV::CV_DOTUSP_B:
20610 case RISCV::CV_DOTUSP_H:
20611 case RISCV::CV_DOTUSP_SC_B:
20612 case RISCV::CV_DOTUSP_SC_H:
20613 case RISCV::CV_EXTRACTR:
20614 case RISCV::CV_EXTRACTUR:
20615 case RISCV::CV_MAX:
20616 case RISCV::CV_MAXU:
20617 case RISCV::CV_MAXU_B:
20618 case RISCV::CV_MAXU_H:
20619 case RISCV::CV_MAXU_SC_B:
20620 case RISCV::CV_MAXU_SC_H:
20621 case RISCV::CV_MAX_B:
20622 case RISCV::CV_MAX_H:
20623 case RISCV::CV_MAX_SC_B:
20624 case RISCV::CV_MAX_SC_H:
20625 case RISCV::CV_MIN:
20626 case RISCV::CV_MINU:
20627 case RISCV::CV_MINU_B:
20628 case RISCV::CV_MINU_H:
20629 case RISCV::CV_MINU_SC_B:
20630 case RISCV::CV_MINU_SC_H:
20631 case RISCV::CV_MIN_B:
20632 case RISCV::CV_MIN_H:
20633 case RISCV::CV_MIN_SC_B:
20634 case RISCV::CV_MIN_SC_H:
20635 case RISCV::CV_OR_B:
20636 case RISCV::CV_OR_H:
20637 case RISCV::CV_OR_SC_B:
20638 case RISCV::CV_OR_SC_H:
20639 case RISCV::CV_PACK:
20640 case RISCV::CV_PACK_H:
20641 case RISCV::CV_ROR:
20642 case RISCV::CV_SHUFFLE_B:
20643 case RISCV::CV_SHUFFLE_H:
20644 case RISCV::CV_SLET:
20645 case RISCV::CV_SLETU:
20646 case RISCV::CV_SLL_B:
20647 case RISCV::CV_SLL_H:
20648 case RISCV::CV_SLL_SC_B:
20649 case RISCV::CV_SLL_SC_H:
20650 case RISCV::CV_SRA_B:
20651 case RISCV::CV_SRA_H:
20652 case RISCV::CV_SRA_SC_B:
20653 case RISCV::CV_SRA_SC_H:
20654 case RISCV::CV_SRL_B:
20655 case RISCV::CV_SRL_H:
20656 case RISCV::CV_SRL_SC_B:
20657 case RISCV::CV_SRL_SC_H:
20658 case RISCV::CV_SUBROTMJ:
20659 case RISCV::CV_SUBROTMJ_DIV2:
20660 case RISCV::CV_SUBROTMJ_DIV4:
20661 case RISCV::CV_SUBROTMJ_DIV8:
20662 case RISCV::CV_SUB_B:
20663 case RISCV::CV_SUB_DIV2:
20664 case RISCV::CV_SUB_DIV4:
20665 case RISCV::CV_SUB_DIV8:
20666 case RISCV::CV_SUB_H:
20667 case RISCV::CV_SUB_SC_B:
20668 case RISCV::CV_SUB_SC_H:
20669 case RISCV::CV_XOR_B:
20670 case RISCV::CV_XOR_H:
20671 case RISCV::CV_XOR_SC_B:
20672 case RISCV::CV_XOR_SC_H:
20673 case RISCV::CZERO_EQZ:
20674 case RISCV::CZERO_NEZ:
20675 case RISCV::DIV:
20676 case RISCV::DIVU:
20677 case RISCV::DIVUW:
20678 case RISCV::DIVW:
20679 case RISCV::FEQ_D:
20680 case RISCV::FEQ_D_IN32X:
20681 case RISCV::FEQ_D_INX:
20682 case RISCV::FEQ_H:
20683 case RISCV::FEQ_H_INX:
20684 case RISCV::FEQ_S:
20685 case RISCV::FEQ_S_INX:
20686 case RISCV::FLEQ_D:
20687 case RISCV::FLEQ_H:
20688 case RISCV::FLEQ_S:
20689 case RISCV::FLE_D:
20690 case RISCV::FLE_D_IN32X:
20691 case RISCV::FLE_D_INX:
20692 case RISCV::FLE_H:
20693 case RISCV::FLE_H_INX:
20694 case RISCV::FLE_S:
20695 case RISCV::FLE_S_INX:
20696 case RISCV::FLTQ_D:
20697 case RISCV::FLTQ_H:
20698 case RISCV::FLTQ_S:
20699 case RISCV::FLT_D:
20700 case RISCV::FLT_D_IN32X:
20701 case RISCV::FLT_D_INX:
20702 case RISCV::FLT_H:
20703 case RISCV::FLT_H_INX:
20704 case RISCV::FLT_S:
20705 case RISCV::FLT_S_INX:
20706 case RISCV::FMAXM_D:
20707 case RISCV::FMAXM_H:
20708 case RISCV::FMAXM_S:
20709 case RISCV::FMAX_D:
20710 case RISCV::FMAX_D_IN32X:
20711 case RISCV::FMAX_D_INX:
20712 case RISCV::FMAX_H:
20713 case RISCV::FMAX_H_INX:
20714 case RISCV::FMAX_S:
20715 case RISCV::FMAX_S_INX:
20716 case RISCV::FMINM_D:
20717 case RISCV::FMINM_H:
20718 case RISCV::FMINM_S:
20719 case RISCV::FMIN_D:
20720 case RISCV::FMIN_D_IN32X:
20721 case RISCV::FMIN_D_INX:
20722 case RISCV::FMIN_H:
20723 case RISCV::FMIN_H_INX:
20724 case RISCV::FMIN_S:
20725 case RISCV::FMIN_S_INX:
20726 case RISCV::FMVP_D_X:
20727 case RISCV::FSGNJN_D:
20728 case RISCV::FSGNJN_D_IN32X:
20729 case RISCV::FSGNJN_D_INX:
20730 case RISCV::FSGNJN_H:
20731 case RISCV::FSGNJN_H_INX:
20732 case RISCV::FSGNJN_S:
20733 case RISCV::FSGNJN_S_INX:
20734 case RISCV::FSGNJX_D:
20735 case RISCV::FSGNJX_D_IN32X:
20736 case RISCV::FSGNJX_D_INX:
20737 case RISCV::FSGNJX_H:
20738 case RISCV::FSGNJX_H_INX:
20739 case RISCV::FSGNJX_S:
20740 case RISCV::FSGNJX_S_INX:
20741 case RISCV::FSGNJ_D:
20742 case RISCV::FSGNJ_D_IN32X:
20743 case RISCV::FSGNJ_D_INX:
20744 case RISCV::FSGNJ_H:
20745 case RISCV::FSGNJ_H_INX:
20746 case RISCV::FSGNJ_S:
20747 case RISCV::FSGNJ_S_INX:
20748 case RISCV::MAX:
20749 case RISCV::MAXU:
20750 case RISCV::MIN:
20751 case RISCV::MINU:
20752 case RISCV::MOPRR0:
20753 case RISCV::MOPRR1:
20754 case RISCV::MOPRR2:
20755 case RISCV::MOPRR3:
20756 case RISCV::MOPRR4:
20757 case RISCV::MOPRR5:
20758 case RISCV::MOPRR6:
20759 case RISCV::MOPRR7:
20760 case RISCV::MUL:
20761 case RISCV::MULH:
20762 case RISCV::MULHSU:
20763 case RISCV::MULHU:
20764 case RISCV::MULW:
20765 case RISCV::OR:
20766 case RISCV::ORN:
20767 case RISCV::PACK:
20768 case RISCV::PACKH:
20769 case RISCV::PACKW:
20770 case RISCV::REM:
20771 case RISCV::REMU:
20772 case RISCV::REMUW:
20773 case RISCV::REMW:
20774 case RISCV::ROL:
20775 case RISCV::ROLW:
20776 case RISCV::ROR:
20777 case RISCV::RORW:
20778 case RISCV::SC_D:
20779 case RISCV::SC_D_AQ:
20780 case RISCV::SC_D_AQ_RL:
20781 case RISCV::SC_D_RL:
20782 case RISCV::SC_W:
20783 case RISCV::SC_W_AQ:
20784 case RISCV::SC_W_AQ_RL:
20785 case RISCV::SC_W_RL:
20786 case RISCV::SH1ADD:
20787 case RISCV::SH1ADD_UW:
20788 case RISCV::SH2ADD:
20789 case RISCV::SH2ADD_UW:
20790 case RISCV::SH3ADD:
20791 case RISCV::SH3ADD_UW:
20792 case RISCV::SHA512SIG0H:
20793 case RISCV::SHA512SIG0L:
20794 case RISCV::SHA512SIG1H:
20795 case RISCV::SHA512SIG1L:
20796 case RISCV::SHA512SUM0R:
20797 case RISCV::SHA512SUM1R:
20798 case RISCV::SLL:
20799 case RISCV::SLLW:
20800 case RISCV::SLT:
20801 case RISCV::SLTU:
20802 case RISCV::SRA:
20803 case RISCV::SRAW:
20804 case RISCV::SRL:
20805 case RISCV::SRLW:
20806 case RISCV::SSAMOSWAP_D:
20807 case RISCV::SSAMOSWAP_D_AQ:
20808 case RISCV::SSAMOSWAP_D_AQ_RL:
20809 case RISCV::SSAMOSWAP_D_RL:
20810 case RISCV::SSAMOSWAP_W:
20811 case RISCV::SSAMOSWAP_W_AQ:
20812 case RISCV::SSAMOSWAP_W_AQ_RL:
20813 case RISCV::SSAMOSWAP_W_RL:
20814 case RISCV::SUB:
20815 case RISCV::SUBW:
20816 case RISCV::VFWMACC_4x4x4:
20817 case RISCV::VQMACCSU_2x8x2:
20818 case RISCV::VQMACCSU_4x8x4:
20819 case RISCV::VQMACCUS_2x8x2:
20820 case RISCV::VQMACCUS_4x8x4:
20821 case RISCV::VQMACCU_2x8x2:
20822 case RISCV::VQMACCU_4x8x4:
20823 case RISCV::VQMACC_2x8x2:
20824 case RISCV::VQMACC_4x8x4:
20825 case RISCV::VSETVL:
20826 case RISCV::VT_MASKC:
20827 case RISCV::VT_MASKCN:
20828 case RISCV::XNOR:
20829 case RISCV::XOR:
20830 case RISCV::XPERM4:
20831 case RISCV::XPERM8: {
20832 switch (OpNum) {
20833 case 2:
20834 // op: rs2
20835 return 20;
20836 case 1:
20837 // op: rs1
20838 return 15;
20839 case 0:
20840 // op: rd
20841 return 7;
20842 }
20843 break;
20844 }
20845 case RISCV::VLSE8_V:
20846 case RISCV::VLSE16_V:
20847 case RISCV::VLSE32_V:
20848 case RISCV::VLSE64_V:
20849 case RISCV::VLSSEG2E8_V:
20850 case RISCV::VLSSEG2E16_V:
20851 case RISCV::VLSSEG2E32_V:
20852 case RISCV::VLSSEG2E64_V:
20853 case RISCV::VLSSEG3E8_V:
20854 case RISCV::VLSSEG3E16_V:
20855 case RISCV::VLSSEG3E32_V:
20856 case RISCV::VLSSEG3E64_V:
20857 case RISCV::VLSSEG4E8_V:
20858 case RISCV::VLSSEG4E16_V:
20859 case RISCV::VLSSEG4E32_V:
20860 case RISCV::VLSSEG4E64_V:
20861 case RISCV::VLSSEG5E8_V:
20862 case RISCV::VLSSEG5E16_V:
20863 case RISCV::VLSSEG5E32_V:
20864 case RISCV::VLSSEG5E64_V:
20865 case RISCV::VLSSEG6E8_V:
20866 case RISCV::VLSSEG6E16_V:
20867 case RISCV::VLSSEG6E32_V:
20868 case RISCV::VLSSEG6E64_V:
20869 case RISCV::VLSSEG7E8_V:
20870 case RISCV::VLSSEG7E16_V:
20871 case RISCV::VLSSEG7E32_V:
20872 case RISCV::VLSSEG7E64_V:
20873 case RISCV::VLSSEG8E8_V:
20874 case RISCV::VLSSEG8E16_V:
20875 case RISCV::VLSSEG8E32_V:
20876 case RISCV::VLSSEG8E64_V: {
20877 switch (OpNum) {
20878 case 2:
20879 // op: rs2
20880 return 20;
20881 case 1:
20882 // op: rs1
20883 return 15;
20884 case 0:
20885 // op: vd
20886 return 7;
20887 case 3:
20888 // op: vm
20889 return 25;
20890 }
20891 break;
20892 }
20893 case RISCV::VSSE8_V:
20894 case RISCV::VSSE16_V:
20895 case RISCV::VSSE32_V:
20896 case RISCV::VSSE64_V:
20897 case RISCV::VSSSEG2E8_V:
20898 case RISCV::VSSSEG2E16_V:
20899 case RISCV::VSSSEG2E32_V:
20900 case RISCV::VSSSEG2E64_V:
20901 case RISCV::VSSSEG3E8_V:
20902 case RISCV::VSSSEG3E16_V:
20903 case RISCV::VSSSEG3E32_V:
20904 case RISCV::VSSSEG3E64_V:
20905 case RISCV::VSSSEG4E8_V:
20906 case RISCV::VSSSEG4E16_V:
20907 case RISCV::VSSSEG4E32_V:
20908 case RISCV::VSSSEG4E64_V:
20909 case RISCV::VSSSEG5E8_V:
20910 case RISCV::VSSSEG5E16_V:
20911 case RISCV::VSSSEG5E32_V:
20912 case RISCV::VSSSEG5E64_V:
20913 case RISCV::VSSSEG6E8_V:
20914 case RISCV::VSSSEG6E16_V:
20915 case RISCV::VSSSEG6E32_V:
20916 case RISCV::VSSSEG6E64_V:
20917 case RISCV::VSSSEG7E8_V:
20918 case RISCV::VSSSEG7E16_V:
20919 case RISCV::VSSSEG7E32_V:
20920 case RISCV::VSSSEG7E64_V:
20921 case RISCV::VSSSEG8E8_V:
20922 case RISCV::VSSSEG8E16_V:
20923 case RISCV::VSSSEG8E32_V:
20924 case RISCV::VSSSEG8E64_V: {
20925 switch (OpNum) {
20926 case 2:
20927 // op: rs2
20928 return 20;
20929 case 1:
20930 // op: rs1
20931 return 15;
20932 case 0:
20933 // op: vs3
20934 return 7;
20935 case 3:
20936 // op: vm
20937 return 25;
20938 }
20939 break;
20940 }
20941 case RISCV::FADD_D:
20942 case RISCV::FADD_D_IN32X:
20943 case RISCV::FADD_D_INX:
20944 case RISCV::FADD_H:
20945 case RISCV::FADD_H_INX:
20946 case RISCV::FADD_S:
20947 case RISCV::FADD_S_INX:
20948 case RISCV::FDIV_D:
20949 case RISCV::FDIV_D_IN32X:
20950 case RISCV::FDIV_D_INX:
20951 case RISCV::FDIV_H:
20952 case RISCV::FDIV_H_INX:
20953 case RISCV::FDIV_S:
20954 case RISCV::FDIV_S_INX:
20955 case RISCV::FMUL_D:
20956 case RISCV::FMUL_D_IN32X:
20957 case RISCV::FMUL_D_INX:
20958 case RISCV::FMUL_H:
20959 case RISCV::FMUL_H_INX:
20960 case RISCV::FMUL_S:
20961 case RISCV::FMUL_S_INX:
20962 case RISCV::FSUB_D:
20963 case RISCV::FSUB_D_IN32X:
20964 case RISCV::FSUB_D_INX:
20965 case RISCV::FSUB_H:
20966 case RISCV::FSUB_H_INX:
20967 case RISCV::FSUB_S:
20968 case RISCV::FSUB_S_INX: {
20969 switch (OpNum) {
20970 case 2:
20971 // op: rs2
20972 return 20;
20973 case 1:
20974 // op: rs1
20975 return 15;
20976 case 3:
20977 // op: frm
20978 return 12;
20979 case 0:
20980 // op: rd
20981 return 7;
20982 }
20983 break;
20984 }
20985 case RISCV::VC_V_FV: {
20986 switch (OpNum) {
20987 case 2:
20988 // op: rs2
20989 return 20;
20990 case 3:
20991 // op: rs1
20992 return 15;
20993 case 0:
20994 // op: rd
20995 return 7;
20996 case 1:
20997 // op: funct6_lo1
20998 return 26;
20999 }
21000 break;
21001 }
21002 case RISCV::VC_V_I:
21003 case RISCV::VC_V_IV:
21004 case RISCV::VC_V_VV:
21005 case RISCV::VC_V_X:
21006 case RISCV::VC_V_XV: {
21007 switch (OpNum) {
21008 case 2:
21009 // op: rs2
21010 return 20;
21011 case 3:
21012 // op: rs1
21013 return 15;
21014 case 0:
21015 // op: rd
21016 return 7;
21017 case 1:
21018 // op: funct6_lo2
21019 return 26;
21020 }
21021 break;
21022 }
21023 case RISCV::VC_FV:
21024 case RISCV::VC_FVV:
21025 case RISCV::VC_FVW: {
21026 switch (OpNum) {
21027 case 2:
21028 // op: rs2
21029 return 20;
21030 case 3:
21031 // op: rs1
21032 return 15;
21033 case 1:
21034 // op: rd
21035 return 7;
21036 case 0:
21037 // op: funct6_lo1
21038 return 26;
21039 }
21040 break;
21041 }
21042 case RISCV::VC_IV:
21043 case RISCV::VC_IVV:
21044 case RISCV::VC_IVW:
21045 case RISCV::VC_VV:
21046 case RISCV::VC_VVV:
21047 case RISCV::VC_VVW:
21048 case RISCV::VC_XV:
21049 case RISCV::VC_XVV:
21050 case RISCV::VC_XVW: {
21051 switch (OpNum) {
21052 case 2:
21053 // op: rs2
21054 return 20;
21055 case 3:
21056 // op: rs1
21057 return 15;
21058 case 1:
21059 // op: rd
21060 return 7;
21061 case 0:
21062 // op: funct6_lo2
21063 return 26;
21064 }
21065 break;
21066 }
21067 case RISCV::C_ADDW:
21068 case RISCV::C_AND:
21069 case RISCV::C_MUL:
21070 case RISCV::C_OR:
21071 case RISCV::C_SUB:
21072 case RISCV::C_SUBW:
21073 case RISCV::C_XOR: {
21074 switch (OpNum) {
21075 case 2:
21076 // op: rs2
21077 return 2;
21078 case 1:
21079 // op: rd
21080 return 7;
21081 }
21082 break;
21083 }
21084 case RISCV::C_ADD_HINT: {
21085 switch (OpNum) {
21086 case 2:
21087 // op: rs2
21088 return 2;
21089 }
21090 break;
21091 }
21092 case RISCV::VLOXEI8_V:
21093 case RISCV::VLOXEI16_V:
21094 case RISCV::VLOXEI32_V:
21095 case RISCV::VLOXEI64_V:
21096 case RISCV::VLOXSEG2EI8_V:
21097 case RISCV::VLOXSEG2EI16_V:
21098 case RISCV::VLOXSEG2EI32_V:
21099 case RISCV::VLOXSEG2EI64_V:
21100 case RISCV::VLOXSEG3EI8_V:
21101 case RISCV::VLOXSEG3EI16_V:
21102 case RISCV::VLOXSEG3EI32_V:
21103 case RISCV::VLOXSEG3EI64_V:
21104 case RISCV::VLOXSEG4EI8_V:
21105 case RISCV::VLOXSEG4EI16_V:
21106 case RISCV::VLOXSEG4EI32_V:
21107 case RISCV::VLOXSEG4EI64_V:
21108 case RISCV::VLOXSEG5EI8_V:
21109 case RISCV::VLOXSEG5EI16_V:
21110 case RISCV::VLOXSEG5EI32_V:
21111 case RISCV::VLOXSEG5EI64_V:
21112 case RISCV::VLOXSEG6EI8_V:
21113 case RISCV::VLOXSEG6EI16_V:
21114 case RISCV::VLOXSEG6EI32_V:
21115 case RISCV::VLOXSEG6EI64_V:
21116 case RISCV::VLOXSEG7EI8_V:
21117 case RISCV::VLOXSEG7EI16_V:
21118 case RISCV::VLOXSEG7EI32_V:
21119 case RISCV::VLOXSEG7EI64_V:
21120 case RISCV::VLOXSEG8EI8_V:
21121 case RISCV::VLOXSEG8EI16_V:
21122 case RISCV::VLOXSEG8EI32_V:
21123 case RISCV::VLOXSEG8EI64_V:
21124 case RISCV::VLUXEI8_V:
21125 case RISCV::VLUXEI16_V:
21126 case RISCV::VLUXEI32_V:
21127 case RISCV::VLUXEI64_V:
21128 case RISCV::VLUXSEG2EI8_V:
21129 case RISCV::VLUXSEG2EI16_V:
21130 case RISCV::VLUXSEG2EI32_V:
21131 case RISCV::VLUXSEG2EI64_V:
21132 case RISCV::VLUXSEG3EI8_V:
21133 case RISCV::VLUXSEG3EI16_V:
21134 case RISCV::VLUXSEG3EI32_V:
21135 case RISCV::VLUXSEG3EI64_V:
21136 case RISCV::VLUXSEG4EI8_V:
21137 case RISCV::VLUXSEG4EI16_V:
21138 case RISCV::VLUXSEG4EI32_V:
21139 case RISCV::VLUXSEG4EI64_V:
21140 case RISCV::VLUXSEG5EI8_V:
21141 case RISCV::VLUXSEG5EI16_V:
21142 case RISCV::VLUXSEG5EI32_V:
21143 case RISCV::VLUXSEG5EI64_V:
21144 case RISCV::VLUXSEG6EI8_V:
21145 case RISCV::VLUXSEG6EI16_V:
21146 case RISCV::VLUXSEG6EI32_V:
21147 case RISCV::VLUXSEG6EI64_V:
21148 case RISCV::VLUXSEG7EI8_V:
21149 case RISCV::VLUXSEG7EI16_V:
21150 case RISCV::VLUXSEG7EI32_V:
21151 case RISCV::VLUXSEG7EI64_V:
21152 case RISCV::VLUXSEG8EI8_V:
21153 case RISCV::VLUXSEG8EI16_V:
21154 case RISCV::VLUXSEG8EI32_V:
21155 case RISCV::VLUXSEG8EI64_V: {
21156 switch (OpNum) {
21157 case 2:
21158 // op: vs2
21159 return 20;
21160 case 1:
21161 // op: rs1
21162 return 15;
21163 case 0:
21164 // op: vd
21165 return 7;
21166 case 3:
21167 // op: vm
21168 return 25;
21169 }
21170 break;
21171 }
21172 case RISCV::VSOXEI8_V:
21173 case RISCV::VSOXEI16_V:
21174 case RISCV::VSOXEI32_V:
21175 case RISCV::VSOXEI64_V:
21176 case RISCV::VSOXSEG2EI8_V:
21177 case RISCV::VSOXSEG2EI16_V:
21178 case RISCV::VSOXSEG2EI32_V:
21179 case RISCV::VSOXSEG2EI64_V:
21180 case RISCV::VSOXSEG3EI8_V:
21181 case RISCV::VSOXSEG3EI16_V:
21182 case RISCV::VSOXSEG3EI32_V:
21183 case RISCV::VSOXSEG3EI64_V:
21184 case RISCV::VSOXSEG4EI8_V:
21185 case RISCV::VSOXSEG4EI16_V:
21186 case RISCV::VSOXSEG4EI32_V:
21187 case RISCV::VSOXSEG4EI64_V:
21188 case RISCV::VSOXSEG5EI8_V:
21189 case RISCV::VSOXSEG5EI16_V:
21190 case RISCV::VSOXSEG5EI32_V:
21191 case RISCV::VSOXSEG5EI64_V:
21192 case RISCV::VSOXSEG6EI8_V:
21193 case RISCV::VSOXSEG6EI16_V:
21194 case RISCV::VSOXSEG6EI32_V:
21195 case RISCV::VSOXSEG6EI64_V:
21196 case RISCV::VSOXSEG7EI8_V:
21197 case RISCV::VSOXSEG7EI16_V:
21198 case RISCV::VSOXSEG7EI32_V:
21199 case RISCV::VSOXSEG7EI64_V:
21200 case RISCV::VSOXSEG8EI8_V:
21201 case RISCV::VSOXSEG8EI16_V:
21202 case RISCV::VSOXSEG8EI32_V:
21203 case RISCV::VSOXSEG8EI64_V:
21204 case RISCV::VSUXEI8_V:
21205 case RISCV::VSUXEI16_V:
21206 case RISCV::VSUXEI32_V:
21207 case RISCV::VSUXEI64_V:
21208 case RISCV::VSUXSEG2EI8_V:
21209 case RISCV::VSUXSEG2EI16_V:
21210 case RISCV::VSUXSEG2EI32_V:
21211 case RISCV::VSUXSEG2EI64_V:
21212 case RISCV::VSUXSEG3EI8_V:
21213 case RISCV::VSUXSEG3EI16_V:
21214 case RISCV::VSUXSEG3EI32_V:
21215 case RISCV::VSUXSEG3EI64_V:
21216 case RISCV::VSUXSEG4EI8_V:
21217 case RISCV::VSUXSEG4EI16_V:
21218 case RISCV::VSUXSEG4EI32_V:
21219 case RISCV::VSUXSEG4EI64_V:
21220 case RISCV::VSUXSEG5EI8_V:
21221 case RISCV::VSUXSEG5EI16_V:
21222 case RISCV::VSUXSEG5EI32_V:
21223 case RISCV::VSUXSEG5EI64_V:
21224 case RISCV::VSUXSEG6EI8_V:
21225 case RISCV::VSUXSEG6EI16_V:
21226 case RISCV::VSUXSEG6EI32_V:
21227 case RISCV::VSUXSEG6EI64_V:
21228 case RISCV::VSUXSEG7EI8_V:
21229 case RISCV::VSUXSEG7EI16_V:
21230 case RISCV::VSUXSEG7EI32_V:
21231 case RISCV::VSUXSEG7EI64_V:
21232 case RISCV::VSUXSEG8EI8_V:
21233 case RISCV::VSUXSEG8EI16_V:
21234 case RISCV::VSUXSEG8EI32_V:
21235 case RISCV::VSUXSEG8EI64_V: {
21236 switch (OpNum) {
21237 case 2:
21238 // op: vs2
21239 return 20;
21240 case 1:
21241 // op: rs1
21242 return 15;
21243 case 0:
21244 // op: vs3
21245 return 7;
21246 case 3:
21247 // op: vm
21248 return 25;
21249 }
21250 break;
21251 }
21252 case RISCV::VAESDF_VS:
21253 case RISCV::VAESDF_VV:
21254 case RISCV::VAESDM_VS:
21255 case RISCV::VAESDM_VV:
21256 case RISCV::VAESEF_VS:
21257 case RISCV::VAESEF_VV:
21258 case RISCV::VAESEM_VS:
21259 case RISCV::VAESEM_VV:
21260 case RISCV::VAESZ_VS:
21261 case RISCV::VGMUL_VV:
21262 case RISCV::VSM4R_VS:
21263 case RISCV::VSM4R_VV: {
21264 switch (OpNum) {
21265 case 2:
21266 // op: vs2
21267 return 20;
21268 case 1:
21269 // op: vd
21270 return 7;
21271 }
21272 break;
21273 }
21274 case RISCV::VAESKF2_VI:
21275 case RISCV::VSM3C_VI: {
21276 switch (OpNum) {
21277 case 2:
21278 // op: vs2
21279 return 20;
21280 case 3:
21281 // op: imm
21282 return 15;
21283 case 1:
21284 // op: vd
21285 return 7;
21286 }
21287 break;
21288 }
21289 case RISCV::VGHSH_VV:
21290 case RISCV::VSHA2CH_VV:
21291 case RISCV::VSHA2CL_VV:
21292 case RISCV::VSHA2MS_VV: {
21293 switch (OpNum) {
21294 case 2:
21295 // op: vs2
21296 return 20;
21297 case 3:
21298 // op: vs1
21299 return 15;
21300 case 1:
21301 // op: vd
21302 return 7;
21303 }
21304 break;
21305 }
21306 case RISCV::CV_SB_ri_inc:
21307 case RISCV::CV_SH_ri_inc:
21308 case RISCV::CV_SW_ri_inc: {
21309 switch (OpNum) {
21310 case 3:
21311 // op: imm12
21312 return 7;
21313 case 1:
21314 // op: rs2
21315 return 20;
21316 case 2:
21317 // op: rs1
21318 return 15;
21319 }
21320 break;
21321 }
21322 case RISCV::CV_LBU_rr_inc:
21323 case RISCV::CV_LB_rr_inc:
21324 case RISCV::CV_LHU_rr_inc:
21325 case RISCV::CV_LH_rr_inc:
21326 case RISCV::CV_LW_rr_inc: {
21327 switch (OpNum) {
21328 case 3:
21329 // op: rs2
21330 return 20;
21331 case 2:
21332 // op: rs1
21333 return 15;
21334 case 0:
21335 // op: rd
21336 return 7;
21337 }
21338 break;
21339 }
21340 case RISCV::CV_MACHHSN:
21341 case RISCV::CV_MACHHSRN:
21342 case RISCV::CV_MACHHUN:
21343 case RISCV::CV_MACHHURN:
21344 case RISCV::CV_MACSN:
21345 case RISCV::CV_MACSRN:
21346 case RISCV::CV_MACUN:
21347 case RISCV::CV_MACURN: {
21348 switch (OpNum) {
21349 case 3:
21350 // op: rs2
21351 return 20;
21352 case 2:
21353 // op: rs1
21354 return 15;
21355 case 1:
21356 // op: rd
21357 return 7;
21358 case 4:
21359 // op: imm5
21360 return 25;
21361 }
21362 break;
21363 }
21364 case RISCV::AMOCAS_B:
21365 case RISCV::AMOCAS_B_AQ:
21366 case RISCV::AMOCAS_B_AQ_RL:
21367 case RISCV::AMOCAS_B_RL:
21368 case RISCV::AMOCAS_D_RV32:
21369 case RISCV::AMOCAS_D_RV32_AQ:
21370 case RISCV::AMOCAS_D_RV32_AQ_RL:
21371 case RISCV::AMOCAS_D_RV32_RL:
21372 case RISCV::AMOCAS_D_RV64:
21373 case RISCV::AMOCAS_D_RV64_AQ:
21374 case RISCV::AMOCAS_D_RV64_AQ_RL:
21375 case RISCV::AMOCAS_D_RV64_RL:
21376 case RISCV::AMOCAS_H:
21377 case RISCV::AMOCAS_H_AQ:
21378 case RISCV::AMOCAS_H_AQ_RL:
21379 case RISCV::AMOCAS_H_RL:
21380 case RISCV::AMOCAS_Q:
21381 case RISCV::AMOCAS_Q_AQ:
21382 case RISCV::AMOCAS_Q_AQ_RL:
21383 case RISCV::AMOCAS_Q_RL:
21384 case RISCV::AMOCAS_W:
21385 case RISCV::AMOCAS_W_AQ:
21386 case RISCV::AMOCAS_W_AQ_RL:
21387 case RISCV::AMOCAS_W_RL:
21388 case RISCV::CV_ADDNR:
21389 case RISCV::CV_ADDRNR:
21390 case RISCV::CV_ADDUNR:
21391 case RISCV::CV_ADDURNR:
21392 case RISCV::CV_CPLXMUL_I:
21393 case RISCV::CV_CPLXMUL_I_DIV2:
21394 case RISCV::CV_CPLXMUL_I_DIV4:
21395 case RISCV::CV_CPLXMUL_I_DIV8:
21396 case RISCV::CV_CPLXMUL_R:
21397 case RISCV::CV_CPLXMUL_R_DIV2:
21398 case RISCV::CV_CPLXMUL_R_DIV4:
21399 case RISCV::CV_CPLXMUL_R_DIV8:
21400 case RISCV::CV_INSERTR:
21401 case RISCV::CV_MAC:
21402 case RISCV::CV_MSU:
21403 case RISCV::CV_PACKHI_B:
21404 case RISCV::CV_PACKLO_B:
21405 case RISCV::CV_SDOTSP_B:
21406 case RISCV::CV_SDOTSP_H:
21407 case RISCV::CV_SDOTSP_SC_B:
21408 case RISCV::CV_SDOTSP_SC_H:
21409 case RISCV::CV_SDOTUP_B:
21410 case RISCV::CV_SDOTUP_H:
21411 case RISCV::CV_SDOTUP_SC_B:
21412 case RISCV::CV_SDOTUP_SC_H:
21413 case RISCV::CV_SDOTUSP_B:
21414 case RISCV::CV_SDOTUSP_H:
21415 case RISCV::CV_SDOTUSP_SC_B:
21416 case RISCV::CV_SDOTUSP_SC_H:
21417 case RISCV::CV_SHUFFLE2_B:
21418 case RISCV::CV_SHUFFLE2_H:
21419 case RISCV::CV_SUBNR:
21420 case RISCV::CV_SUBRNR:
21421 case RISCV::CV_SUBUNR:
21422 case RISCV::CV_SUBURNR:
21423 case RISCV::TH_MULA:
21424 case RISCV::TH_MULAH:
21425 case RISCV::TH_MULAW:
21426 case RISCV::TH_MULS:
21427 case RISCV::TH_MULSH:
21428 case RISCV::TH_MULSW:
21429 case RISCV::TH_MVEQZ:
21430 case RISCV::TH_MVNEZ: {
21431 switch (OpNum) {
21432 case 3:
21433 // op: rs2
21434 return 20;
21435 case 2:
21436 // op: rs1
21437 return 15;
21438 case 1:
21439 // op: rd
21440 return 7;
21441 }
21442 break;
21443 }
21444 case RISCV::VC_V_FVV:
21445 case RISCV::VC_V_FVW: {
21446 switch (OpNum) {
21447 case 3:
21448 // op: rs2
21449 return 20;
21450 case 4:
21451 // op: rs1
21452 return 15;
21453 case 2:
21454 // op: rd
21455 return 7;
21456 case 1:
21457 // op: funct6_lo1
21458 return 26;
21459 }
21460 break;
21461 }
21462 case RISCV::VC_V_IVV:
21463 case RISCV::VC_V_IVW:
21464 case RISCV::VC_V_VVV:
21465 case RISCV::VC_V_VVW:
21466 case RISCV::VC_V_XVV:
21467 case RISCV::VC_V_XVW: {
21468 switch (OpNum) {
21469 case 3:
21470 // op: rs2
21471 return 20;
21472 case 4:
21473 // op: rs1
21474 return 15;
21475 case 2:
21476 // op: rd
21477 return 7;
21478 case 1:
21479 // op: funct6_lo2
21480 return 26;
21481 }
21482 break;
21483 }
21484 case RISCV::FMADD_D:
21485 case RISCV::FMADD_D_IN32X:
21486 case RISCV::FMADD_D_INX:
21487 case RISCV::FMADD_H:
21488 case RISCV::FMADD_H_INX:
21489 case RISCV::FMADD_S:
21490 case RISCV::FMADD_S_INX:
21491 case RISCV::FMSUB_D:
21492 case RISCV::FMSUB_D_IN32X:
21493 case RISCV::FMSUB_D_INX:
21494 case RISCV::FMSUB_H:
21495 case RISCV::FMSUB_H_INX:
21496 case RISCV::FMSUB_S:
21497 case RISCV::FMSUB_S_INX:
21498 case RISCV::FNMADD_D:
21499 case RISCV::FNMADD_D_IN32X:
21500 case RISCV::FNMADD_D_INX:
21501 case RISCV::FNMADD_H:
21502 case RISCV::FNMADD_H_INX:
21503 case RISCV::FNMADD_S:
21504 case RISCV::FNMADD_S_INX:
21505 case RISCV::FNMSUB_D:
21506 case RISCV::FNMSUB_D_IN32X:
21507 case RISCV::FNMSUB_D_INX:
21508 case RISCV::FNMSUB_H:
21509 case RISCV::FNMSUB_H_INX:
21510 case RISCV::FNMSUB_S:
21511 case RISCV::FNMSUB_S_INX: {
21512 switch (OpNum) {
21513 case 3:
21514 // op: rs3
21515 return 27;
21516 case 2:
21517 // op: rs2
21518 return 20;
21519 case 1:
21520 // op: rs1
21521 return 15;
21522 case 4:
21523 // op: frm
21524 return 12;
21525 case 0:
21526 // op: rd
21527 return 7;
21528 }
21529 break;
21530 }
21531 case RISCV::CV_SB_rr_inc:
21532 case RISCV::CV_SH_rr_inc:
21533 case RISCV::CV_SW_rr_inc: {
21534 switch (OpNum) {
21535 case 3:
21536 // op: rs3
21537 return 7;
21538 case 1:
21539 // op: rs2
21540 return 20;
21541 case 2:
21542 // op: rs1
21543 return 15;
21544 }
21545 break;
21546 }
21547 case RISCV::THVdotVMAQASU_VX:
21548 case RISCV::THVdotVMAQAUS_VX:
21549 case RISCV::THVdotVMAQAU_VX:
21550 case RISCV::THVdotVMAQA_VX:
21551 case RISCV::VFMACC_VF:
21552 case RISCV::VFMADD_VF:
21553 case RISCV::VFMSAC_VF:
21554 case RISCV::VFMSUB_VF:
21555 case RISCV::VFNMACC_VF:
21556 case RISCV::VFNMADD_VF:
21557 case RISCV::VFNMSAC_VF:
21558 case RISCV::VFNMSUB_VF:
21559 case RISCV::VFWMACCBF16_VF:
21560 case RISCV::VFWMACC_VF:
21561 case RISCV::VFWMSAC_VF:
21562 case RISCV::VFWNMACC_VF:
21563 case RISCV::VFWNMSAC_VF:
21564 case RISCV::VMACC_VX:
21565 case RISCV::VMADD_VX:
21566 case RISCV::VNMSAC_VX:
21567 case RISCV::VNMSUB_VX:
21568 case RISCV::VWMACCSU_VX:
21569 case RISCV::VWMACCUS_VX:
21570 case RISCV::VWMACCU_VX:
21571 case RISCV::VWMACC_VX: {
21572 switch (OpNum) {
21573 case 3:
21574 // op: vs2
21575 return 20;
21576 case 2:
21577 // op: rs1
21578 return 15;
21579 case 1:
21580 // op: vd
21581 return 7;
21582 case 4:
21583 // op: vm
21584 return 25;
21585 }
21586 break;
21587 }
21588 case RISCV::THVdotVMAQASU_VV:
21589 case RISCV::THVdotVMAQAU_VV:
21590 case RISCV::THVdotVMAQA_VV:
21591 case RISCV::VFMACC_VV:
21592 case RISCV::VFMADD_VV:
21593 case RISCV::VFMSAC_VV:
21594 case RISCV::VFMSUB_VV:
21595 case RISCV::VFNMACC_VV:
21596 case RISCV::VFNMADD_VV:
21597 case RISCV::VFNMSAC_VV:
21598 case RISCV::VFNMSUB_VV:
21599 case RISCV::VFWMACCBF16_VV:
21600 case RISCV::VFWMACC_VV:
21601 case RISCV::VFWMSAC_VV:
21602 case RISCV::VFWNMACC_VV:
21603 case RISCV::VFWNMSAC_VV:
21604 case RISCV::VMACC_VV:
21605 case RISCV::VMADD_VV:
21606 case RISCV::VNMSAC_VV:
21607 case RISCV::VNMSUB_VV:
21608 case RISCV::VWMACCSU_VV:
21609 case RISCV::VWMACCU_VV:
21610 case RISCV::VWMACC_VV: {
21611 switch (OpNum) {
21612 case 3:
21613 // op: vs2
21614 return 20;
21615 case 2:
21616 // op: vs1
21617 return 15;
21618 case 1:
21619 // op: vd
21620 return 7;
21621 case 4:
21622 // op: vm
21623 return 25;
21624 }
21625 break;
21626 }
21627 }
21628 std::string msg;
21629 raw_string_ostream Msg(msg);
21630 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
21631 report_fatal_error(Msg.str().c_str());
21632}
21633
21634#endif // GET_OPERAND_BIT_OFFSET
21635
21636