1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | |* *| |
3 | |* Macro Fusion Predicators *| |
4 | |* *| |
5 | |* Automatically generated file, do not edit! *| |
6 | |* *| |
7 | \*===----------------------------------------------------------------------===*/ |
8 | |
9 | #ifdef GET_RISCV_MACRO_FUSION_PRED_DECL |
10 | #undef GET_RISCV_MACRO_FUSION_PRED_DECL |
11 | |
12 | namespace llvm { |
13 | bool isTuneAUIPCADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
14 | bool isTuneLDADDFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
15 | bool isTuneLUIADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
16 | bool isTuneShiftedZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
17 | bool isTuneZExtHFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
18 | bool isTuneZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
19 | } // end namespace llvm |
20 | |
21 | #endif |
22 | |
23 | #ifdef GET_RISCV_MACRO_FUSION_PRED_IMPL |
24 | #undef GET_RISCV_MACRO_FUSION_PRED_IMPL |
25 | |
26 | namespace llvm { |
27 | bool isTuneAUIPCADDIFusion( |
28 | const TargetInstrInfo &TII, |
29 | const TargetSubtargetInfo &STI, |
30 | const MachineInstr *FirstMI, |
31 | const MachineInstr &SecondMI) { |
32 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
33 | { |
34 | const MachineInstr *MI = &SecondMI; |
35 | if (( MI->getOpcode() != RISCV::ADDI )) |
36 | return false; |
37 | } |
38 | if (!FirstMI) |
39 | return true; |
40 | { |
41 | const MachineInstr *MI = FirstMI; |
42 | if (( MI->getOpcode() != RISCV::AUIPC )) |
43 | return false; |
44 | } |
45 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
46 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
47 | return false; |
48 | } |
49 | { |
50 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
51 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
52 | return false; |
53 | } |
54 | if (!(FirstMI->getOperand(0).isReg() && |
55 | SecondMI.getOperand(1).isReg() && |
56 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
57 | return false; |
58 | return true; |
59 | } |
60 | bool isTuneLDADDFusion( |
61 | const TargetInstrInfo &TII, |
62 | const TargetSubtargetInfo &STI, |
63 | const MachineInstr *FirstMI, |
64 | const MachineInstr &SecondMI) { |
65 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
66 | { |
67 | const MachineInstr *MI = &SecondMI; |
68 | if (!( |
69 | ( MI->getOpcode() == RISCV::LD ) |
70 | && MI->getOperand(2).isImm() |
71 | && MI->getOperand(2).getImm() == 0 |
72 | )) |
73 | return false; |
74 | } |
75 | if (!FirstMI) |
76 | return true; |
77 | { |
78 | const MachineInstr *MI = FirstMI; |
79 | if (( MI->getOpcode() != RISCV::ADD )) |
80 | return false; |
81 | } |
82 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
83 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
84 | return false; |
85 | } |
86 | { |
87 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
88 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
89 | return false; |
90 | } |
91 | if (!(FirstMI->getOperand(0).isReg() && |
92 | SecondMI.getOperand(1).isReg() && |
93 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
94 | return false; |
95 | return true; |
96 | } |
97 | bool isTuneLUIADDIFusion( |
98 | const TargetInstrInfo &TII, |
99 | const TargetSubtargetInfo &STI, |
100 | const MachineInstr *FirstMI, |
101 | const MachineInstr &SecondMI) { |
102 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
103 | { |
104 | const MachineInstr *MI = &SecondMI; |
105 | if (( |
106 | MI->getOpcode() != RISCV::ADDI |
107 | && MI->getOpcode() != RISCV::ADDIW |
108 | )) |
109 | return false; |
110 | } |
111 | if (!FirstMI) |
112 | return true; |
113 | { |
114 | const MachineInstr *MI = FirstMI; |
115 | if (( MI->getOpcode() != RISCV::LUI )) |
116 | return false; |
117 | } |
118 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
119 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
120 | return false; |
121 | } |
122 | { |
123 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
124 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
125 | return false; |
126 | } |
127 | if (!(FirstMI->getOperand(0).isReg() && |
128 | SecondMI.getOperand(1).isReg() && |
129 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
130 | return false; |
131 | return true; |
132 | } |
133 | bool isTuneShiftedZExtWFusion( |
134 | const TargetInstrInfo &TII, |
135 | const TargetSubtargetInfo &STI, |
136 | const MachineInstr *FirstMI, |
137 | const MachineInstr &SecondMI) { |
138 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
139 | { |
140 | const MachineInstr *MI = &SecondMI; |
141 | if (!( |
142 | ( MI->getOpcode() == RISCV::SRLI ) |
143 | && MI->getOperand(2).isImm() |
144 | && ( |
145 | MI->getOperand(2).getImm() >= 0 |
146 | && MI->getOperand(2).getImm() <= 31 |
147 | ) |
148 | )) |
149 | return false; |
150 | } |
151 | if (!FirstMI) |
152 | return true; |
153 | { |
154 | const MachineInstr *MI = FirstMI; |
155 | if (!( |
156 | ( MI->getOpcode() == RISCV::SLLI ) |
157 | && MI->getOperand(2).isImm() |
158 | && MI->getOperand(2).getImm() == 32 |
159 | )) |
160 | return false; |
161 | } |
162 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
163 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
164 | return false; |
165 | } |
166 | { |
167 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
168 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
169 | return false; |
170 | } |
171 | if (!(FirstMI->getOperand(0).isReg() && |
172 | SecondMI.getOperand(1).isReg() && |
173 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
174 | return false; |
175 | return true; |
176 | } |
177 | bool isTuneZExtHFusion( |
178 | const TargetInstrInfo &TII, |
179 | const TargetSubtargetInfo &STI, |
180 | const MachineInstr *FirstMI, |
181 | const MachineInstr &SecondMI) { |
182 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
183 | { |
184 | const MachineInstr *MI = &SecondMI; |
185 | if (!( |
186 | ( MI->getOpcode() == RISCV::SRLI ) |
187 | && MI->getOperand(2).isImm() |
188 | && MI->getOperand(2).getImm() == 48 |
189 | )) |
190 | return false; |
191 | } |
192 | if (!FirstMI) |
193 | return true; |
194 | { |
195 | const MachineInstr *MI = FirstMI; |
196 | if (!( |
197 | ( MI->getOpcode() == RISCV::SLLI ) |
198 | && MI->getOperand(2).isImm() |
199 | && MI->getOperand(2).getImm() == 48 |
200 | )) |
201 | return false; |
202 | } |
203 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
204 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
205 | return false; |
206 | } |
207 | { |
208 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
209 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
210 | return false; |
211 | } |
212 | if (!(FirstMI->getOperand(0).isReg() && |
213 | SecondMI.getOperand(1).isReg() && |
214 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
215 | return false; |
216 | return true; |
217 | } |
218 | bool isTuneZExtWFusion( |
219 | const TargetInstrInfo &TII, |
220 | const TargetSubtargetInfo &STI, |
221 | const MachineInstr *FirstMI, |
222 | const MachineInstr &SecondMI) { |
223 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
224 | { |
225 | const MachineInstr *MI = &SecondMI; |
226 | if (!( |
227 | ( MI->getOpcode() == RISCV::SRLI ) |
228 | && MI->getOperand(2).isImm() |
229 | && MI->getOperand(2).getImm() == 32 |
230 | )) |
231 | return false; |
232 | } |
233 | if (!FirstMI) |
234 | return true; |
235 | { |
236 | const MachineInstr *MI = FirstMI; |
237 | if (!( |
238 | ( MI->getOpcode() == RISCV::SLLI ) |
239 | && MI->getOperand(2).isImm() |
240 | && MI->getOperand(2).getImm() == 32 |
241 | )) |
242 | return false; |
243 | } |
244 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
245 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
246 | return false; |
247 | } |
248 | { |
249 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
250 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
251 | return false; |
252 | } |
253 | if (!(FirstMI->getOperand(0).isReg() && |
254 | SecondMI.getOperand(1).isReg() && |
255 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
256 | return false; |
257 | return true; |
258 | } |
259 | } // end namespace llvm |
260 | |
261 | #endif |
262 | |