1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace RISCV {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 FPRBRegBankID = 0,
16 GPRBRegBankID = 1,
17 VRBRegBankID = 2,
18 NumRegisterBanks,
19};
20} // end namespace RISCV
21} // end namespace llvm
22#endif // GET_REGBANK_DECLARATIONS
23
24#ifdef GET_TARGET_REGBANK_CLASS
25#undef GET_TARGET_REGBANK_CLASS
26private:
27 static const RegisterBank *RegBanks[];
28 static const unsigned Sizes[];
29
30protected:
31 RISCVGenRegisterBankInfo(unsigned HwMode = 0);
32
33#endif // GET_TARGET_REGBANK_CLASS
34
35#ifdef GET_TARGET_REGBANK_IMPL
36#undef GET_TARGET_REGBANK_IMPL
37namespace llvm {
38namespace RISCV {
39const uint32_t FPRBRegBankCoverageData[] = {
40 // 0-31
41 (1u << (RISCV::FPR16RegClassID - 0)) |
42 (1u << (RISCV::FPR32RegClassID - 0)) |
43 (1u << (RISCV::FPR32CRegClassID - 0)) |
44 0,
45 // 32-63
46 (1u << (RISCV::FPR64RegClassID - 32)) |
47 (1u << (RISCV::FPR64CRegClassID - 32)) |
48 0,
49 // 64-95
50 0,
51};
52const uint32_t GPRBRegBankCoverageData[] = {
53 // 0-31
54 (1u << (RISCV::GPRRegClassID - 0)) |
55 (1u << (RISCV::GPRF16RegClassID - 0)) |
56 (1u << (RISCV::GPRF32RegClassID - 0)) |
57 (1u << (RISCV::GPRNoX0RegClassID - 0)) |
58 (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
59 (1u << (RISCV::GPRJALRRegClassID - 0)) |
60 (1u << (RISCV::GPRJALRNonX7RegClassID - 0)) |
61 (1u << (RISCV::GPRTCNonX7RegClassID - 0)) |
62 (1u << (RISCV::GPRC_and_GPRTCRegClassID - 0)) |
63 (1u << (RISCV::GPRCRegClassID - 0)) |
64 (1u << (RISCV::GPRC_and_SR07RegClassID - 0)) |
65 (1u << (RISCV::SR07RegClassID - 0)) |
66 (1u << (RISCV::GPRTCRegClassID - 0)) |
67 (1u << (RISCV::GPRX7RegClassID - 0)) |
68 (1u << (RISCV::GPRX1X5RegClassID - 0)) |
69 (1u << (RISCV::GPRX1RegClassID - 0)) |
70 (1u << (RISCV::GPRX5RegClassID - 0)) |
71 (1u << (RISCV::SPRegClassID - 0)) |
72 (1u << (RISCV::GPRX0RegClassID - 0)) |
73 0,
74 // 32-63
75 0,
76 // 64-95
77 0,
78};
79const uint32_t VRBRegBankCoverageData[] = {
80 // 0-31
81 0,
82 // 32-63
83 (1u << (RISCV::VMRegClassID - 32)) |
84 (1u << (RISCV::VRRegClassID - 32)) |
85 (1u << (RISCV::VRNoV0RegClassID - 32)) |
86 (1u << (RISCV::VRM2RegClassID - 32)) |
87 (1u << (RISCV::VRM2NoV0RegClassID - 32)) |
88 (1u << (RISCV::VRM4RegClassID - 32)) |
89 (1u << (RISCV::VRM4NoV0RegClassID - 32)) |
90 (1u << (RISCV::VMV0RegClassID - 32)) |
91 (1u << (RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID - 32)) |
92 (1u << (RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 32)) |
93 0,
94 // 64-95
95 (1u << (RISCV::VRM8RegClassID - 64)) |
96 (1u << (RISCV::VRM8NoV0RegClassID - 64)) |
97 (1u << (RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID - 64)) |
98 0,
99};
100
101constexpr RegisterBank FPRBRegBank(/* ID */ RISCV::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 87);
102constexpr RegisterBank GPRBRegBank(/* ID */ RISCV::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 87);
103constexpr RegisterBank VRBRegBank(/* ID */ RISCV::VRBRegBankID, /* Name */ "VRB", /* CoveredRegClasses */ VRBRegBankCoverageData, /* NumRegClasses */ 87);
104} // end namespace RISCV
105
106const RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
107 &RISCV::FPRBRegBank,
108 &RISCV::GPRBRegBank,
109 &RISCV::VRBRegBank,
110};
111
112const unsigned RISCVGenRegisterBankInfo::Sizes[] = {
113 // Mode = 0 (Default)
114 64,
115 32,
116 512,
117 // Mode = 1 (RV64)
118 64,
119 64,
120 512,
121};
122
123RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo(unsigned HwMode)
124 : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks, Sizes, HwMode) {
125 // Assert that RegBank indices match their ID's
126#ifndef NDEBUG
127 for (auto RB : enumerate(RegBanks))
128 assert(RB.index() == RB.value()->getID() && "Index != ID");
129#endif // NDEBUG
130}
131} // end namespace llvm
132#endif // GET_TARGET_REGBANK_IMPL
133